[patch 1/1] sdhci-base-clock-freqency-change-in-spec-3.0

[patch 1/1] sdhci-base-clock-freqency-change-in-spec-3.0

[zhangfei gao]

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>From 6b82bd3c0fe55b7060b8d96801e5e2c4fecc79b7 Mon Sep 17 00:00:00 2001
From: Zhangfei Gao <zgao6@marvell.com>
Date: Fri, 20 Aug 2010 14:02:36 -0400
Subject: [PATCH] sdhci: base clock freqency change in spec 3.0

	sdhc spec 3.0:       Capabilities Register bits[15-08] is Base Clock Freqency
	sdhc spec 1.0 & 2.0: Capabilities Register bits[13-08] is Base Clock Freqency

Signed-off-by: Zhangfei Gao <zgao6@marvell.com>
---
 drivers/mmc/host/sdhci.c |    8 ++++++--
 drivers/mmc/host/sdhci.h |    1 +
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 7855121..458e5d4 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1778,8 +1778,12 @@ int sdhci_add_host(struct sdhci_host *host)
 		mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
 	}

-	host->max_clk =
-		(caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
+	if (host->version >= SDHCI_SPEC_300)
+		host->max_clk =
+			(caps & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
+	else
+		host->max_clk =
+			(caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
 	host->max_clk *= 1000000;
 	if (host->max_clk == 0 || host->quirks &
 			SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 036cfae..8f71f56 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -140,6 +140,7 @@
 #define  SDHCI_TIMEOUT_CLK_SHIFT 0
 #define  SDHCI_TIMEOUT_CLK_UNIT	0x00000080
 #define  SDHCI_CLOCK_BASE_MASK	0x00003F00
+#define  SDHCI_CLOCK_V3_BASE_MASK	0x0000FF00
 #define  SDHCI_CLOCK_BASE_SHIFT	8
 #define  SDHCI_MAX_BLOCK_MASK	0x00030000
 #define  SDHCI_MAX_BLOCK_SHIFT  16
-- 
1.7.0.4

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From 6b82bd3c0fe55b7060b8d96801e5e2c4fecc79b7 Mon Sep 17 00:00:00 2001
From: Zhangfei Gao <zgao6@marvell.com>
Date: Fri, 20 Aug 2010 14:02:36 -0400
Subject: [PATCH] sdhci: base clock freqency change in spec 3.0

	sdhc spec 3.0:       Capabilities Register bits[15-08] is Base Clock Freqency
	sdhc spec 1.0 & 2.0: Capabilities Register bits[13-08] is Base Clock Freqency

Signed-off-by: Zhangfei Gao <zgao6@marvell.com>
---
 drivers/mmc/host/sdhci.c |    8 ++++++--
 drivers/mmc/host/sdhci.h |    1 +
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 7855121..458e5d4 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1778,8 +1778,12 @@ int sdhci_add_host(struct sdhci_host *host)
 		mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
 	}
 
-	host->max_clk =
-		(caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
+	if (host->version >= SDHCI_SPEC_300)
+		host->max_clk =
+			(caps & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
+	else
+		host->max_clk =
+			(caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
 	host->max_clk *= 1000000;
 	if (host->max_clk == 0 || host->quirks &
 			SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 036cfae..8f71f56 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -140,6 +140,7 @@
 #define  SDHCI_TIMEOUT_CLK_SHIFT 0
 #define  SDHCI_TIMEOUT_CLK_UNIT	0x00000080
 #define  SDHCI_CLOCK_BASE_MASK	0x00003F00
+#define  SDHCI_CLOCK_V3_BASE_MASK	0x0000FF00
 #define  SDHCI_CLOCK_BASE_SHIFT	8
 #define  SDHCI_MAX_BLOCK_MASK	0x00030000
 #define  SDHCI_MAX_BLOCK_SHIFT  16
-- 
1.7.0.4

Re: [patch 1/1] sdhci-base-clock-freqency-change-in-spec-3.0

[zhangfei gao]

On Fri, Aug 20, 2010 at 2:22 AM, zhangfei gao <zhangfei.gao@gmail.com> wrote:
> From 6b82bd3c0fe55b7060b8d96801e5e2c4fecc79b7 Mon Sep 17 00:00:00 2001
> From: Zhangfei Gao <zgao6@marvell.com>
> Date: Fri, 20 Aug 2010 14:02:36 -0400
> Subject: [PATCH] sdhci: base clock freqency change in spec 3.0
>
>        sdhc spec 3.0:       Capabilities Register bits[15-08] is Base Clock Freqency
>        sdhc spec 1.0 & 2.0: Capabilities Register bits[13-08] is Base Clock Freqency
>
> Signed-off-by: Zhangfei Gao <zgao6@marvell.com>
> ---
>  drivers/mmc/host/sdhci.c |    8 ++++++--
>  drivers/mmc/host/sdhci.h |    1 +
>  2 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index 7855121..458e5d4 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -1778,8 +1778,12 @@ int sdhci_add_host(struct sdhci_host *host)
>                mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
>        }
>
> -       host->max_clk =
> -               (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
> +       if (host->version >= SDHCI_SPEC_300)
> +               host->max_clk =
> +                       (caps & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
> +       else
> +               host->max_clk =
> +                       (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
>        host->max_clk *= 1000000;
>        if (host->max_clk == 0 || host->quirks &
>                        SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
> diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
> index 036cfae..8f71f56 100644
> --- a/drivers/mmc/host/sdhci.h
> +++ b/drivers/mmc/host/sdhci.h
> @@ -140,6 +140,7 @@
>  #define  SDHCI_TIMEOUT_CLK_SHIFT 0
>  #define  SDHCI_TIMEOUT_CLK_UNIT        0x00000080
>  #define  SDHCI_CLOCK_BASE_MASK 0x00003F00
> +#define  SDHCI_CLOCK_V3_BASE_MASK      0x0000FF00
>  #define  SDHCI_CLOCK_BASE_SHIFT        8
>  #define  SDHCI_MAX_BLOCK_MASK  0x00030000
>  #define  SDHCI_MAX_BLOCK_SHIFT  16
> --
> 1.7.0.4
>

This patch should be based on
sdhci-support-10-bit-divided-clock-Mode.patch, since SDHCI_SPEC_300 is
defined inside.
 +#define   SDHCI_SPEC_300       2

Re: [patch 1/1] sdhci-base-clock-freqency-change-in-spec-3.0

[Chris Ball]

Hi,

On Fri, Aug 20, 2010 at 02:22:56AM -0400, zhangfei gao wrote:
> From: Zhangfei Gao <zgao6@marvell.com>
> Date: Fri, 20 Aug 2010 14:02:36 -0400
> Subject: [PATCH] sdhci: base clock freqency change in spec 3.0

Thanks, applied to mmc-next.

We should have all of the changes required for SDHC 3.0 (8-bit wide data,
10-bit divided clock mode, base clock frequency change) present in the
mmc-next tree now.  Would someone with access to 3.0 hardware be able to
test that it's all working?

-- 
Chris Ball   <cjb@laptop.org>   <http://printf.net/>
One Laptop Per Child

Re: [patch 1/1] sdhci-base-clock-freqency-change-in-spec-3.0

[Wolfram Sang]

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On Tue, Sep 14, 2010 at 02:18:53PM +0100, Chris Ball wrote:
> Hi,
> 
> On Fri, Aug 20, 2010 at 02:22:56AM -0400, zhangfei gao wrote:
> > From: Zhangfei Gao <zgao6@marvell.com>
> > Date: Fri, 20 Aug 2010 14:02:36 -0400
> > Subject: [PATCH] sdhci: base clock freqency change in spec 3.0
> 
> Thanks, applied to mmc-next.
> 
> We should have all of the changes required for SDHC 3.0 (8-bit wide data,
> 10-bit divided clock mode, base clock frequency change) present in the
> mmc-next tree now.  Would someone with access to 3.0 hardware be able to
> test that it's all working?

Is the 8-bit support really according to the standard? I wonder because
the bit currently used by sdhci.c is marked as "reserved/new assignment
now allowed" in the simplified v2.0 spec.

Regards,

   Wolfram

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

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Re: [patch 1/1] sdhci-base-clock-freqency-change-in-spec-3.0

[Wolfram Sang]

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On Wed, Sep 15, 2010 at 11:35:18AM +0800, zhangfei gao wrote:

> > Is the 8-bit support really according to the standard? I wonder because
> > the bit currently used by sdhci.c is marked as "reserved/new assignment
> > now allowed" in the simplified v2.0 spec.
> 
> Attached capacity in sdh 3.0.
> 6-bit base clock frequece is support in 1.0 and 2.0, support 10M to 63M.
> 8-bit is supported in 3.0, and support 10M to 255M.

I meant 8-bit bus width. Which bit in which register selects this?

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

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Re: [patch 1/1] sdhci-base-clock-freqency-change-in-spec-3.0

[zhangfei gao]

On Wed, Sep 15, 2010 at 6:10 PM, Wolfram Sang <w.sang@pengutronix.de> wrote:
> On Wed, Sep 15, 2010 at 11:35:18AM +0800, zhangfei gao wrote:
>
>> > Is the 8-bit support really according to the standard? I wonder because
>> > the bit currently used by sdhci.c is marked as "reserved/new assignment
>> > now allowed" in the simplified v2.0 spec.
>>
>> Attached capacity in sdh 3.0.
>> 6-bit base clock frequece is support in 1.0 and 2.0, support 10M to 63M.
>> 8-bit is supported in 3.0, and support 10M to 255M.
>
> I meant 8-bit bus width. Which bit in which register selects this?

The 8-bit bus width usually used in embeded mmc, like Micron emmc and
sandisk emmc, bit[5] of host controller (0x28h) is added in sdh spec
3.0, and the patch is already in the latest kernel.

>
> --
> Pengutronix e.K.                           | Wolfram Sang                |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
>
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