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From: Hans Rosenfeld <hans.rosenfeld@amd.com>
To: Ingo Molnar <mingo@elte.hu>
Cc: "hpa@zytor.com" <hpa@zytor.com>,
	"tglx@linutronix.de" <tglx@linutronix.de>,
	"Herrmann3, Andreas" <Andreas.Herrmann3@amd.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"x86@kernel.org" <x86@kernel.org>
Subject: Re: [PATCH 4/4] x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs
Date: Tue, 1 Feb 2011 16:14:55 +0100	[thread overview]
Message-ID: <20110201151455.GA9507@escobedo.osrc.amd.com> (raw)
In-Reply-To: <20110127124756.GA16094@elte.hu>

On Thu, Jan 27, 2011 at 07:47:56AM -0500, Ingo Molnar wrote:
> > The problem is that cpuinfo_x86.compute_unit_id etc. don't exist unless
> > CONFIG_SMP is enabled. I don't think there is any reason why this should
> > be that way, but changing this just for this particular L3 feature seems
> > too intrusive. Do you really want me to do that?
> 
> All the CONFIG_X86_HT #ifdefs in arch/x86/kernel/cpu/amd.c look pretty ugly too - 
> and it's not really a properly modularized solution.
> 
> We generally want to unify the SMP and UP kernels as much as possible. 'CONFIG_SMP' 
> is not really a property of the hardware, it's a property of the software.
> 
> If some topology information should be excluded then it can already be done by 
> turning off CONFIG_CPU_SUP_AMD under CONFIG_EXPERT.

I see several solutions to resolve this issue:

1. Remove #ifdef CONFIG_SMP around compute_unit_id in struct cpuinfo_x86
   and then use my original patch. This would work without introducing
   new #ifdef ugliness with the L3 cache partitioning, but it would
   increase #ifdef ugliness in struct cpuinfo_x86. Also, compute_unit_id
   would just so happen to be initialized to 0, there would be no other
   code using it for CONFIG_SMP. L3 cache partitioning would be the
   first SMP-specific feature to be available in non-SMP kernels.

2. Same as #1, but remove CONFIG_SMP completely from struct cpuinfo_x86.
   This would mean less #ifdef ugliness there, but then we would have a
   bunch of unused fields in there in non-SMP kernels, which would also
   just be initialized to 0. I don't think that would be correct for
   booted_cores, but as it is unused I don't see an immediate problem
   with that. Of course, this is also neither correct nor less ugly.

3. Same as #2, but also rework all code using those fields to be usable
   on non-SMP kernels. This would be essentially a rework of all that
   CONFIG_SMP stuff, and I think thats too much to ask for just for a
   little extra L3 feature.

Maybe I'm missing something here, but I don't see how this could be
done cleanly in any other way at this time.

Of course, you could just take the modified patch I sent you. That would
be ugly, but not more so than the existing code. If this is not
acceptable, please tell me which of the other two ugly solutions you
would prefer.


Hans


-- 
%SYSTEM-F-ANARCHISM, The operating system has been overthrown


  reply	other threads:[~2011-02-01 15:15 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-01-24 15:05 [PATCH 0/4] x86, amd: family 0x15 L3 cache features Hans Rosenfeld
2011-01-24 15:05 ` [PATCH 1/4] x86, amd: Normalize compute unit IDs on multi-node processors Hans Rosenfeld
2011-01-26 10:57   ` [tip:x86/amd-nb] " tip-bot for Andreas Herrmann
2011-02-14 14:30     ` Ingo Molnar
2011-02-14 17:14       ` [PATCH] x86, amd: Fix uninitialized variable warning Borislav Petkov
2011-02-15  3:10         ` [tip:x86/amd-nb] x86, amd: Initialize variable properly tip-bot for Borislav Petkov
2011-02-04 22:07   ` [PATCH 1/4] x86, amd: Normalize compute unit IDs on multi-node processors Andrew Morton
2011-01-24 15:05 ` [PATCH 2/4] x86, amd: Enable L3 cache index disable on family 0x15 Hans Rosenfeld
2011-01-26 10:58   ` [tip:x86/amd-nb] " tip-bot for Hans Rosenfeld
2011-01-24 15:05 ` [PATCH 3/4] x86, amd: Extend AMD northbridge caching code to support "Link Control" devices Hans Rosenfeld
2011-01-26 10:58   ` [tip:x86/amd-nb] " tip-bot for Hans Rosenfeld
2011-01-24 15:05 ` [PATCH 4/4] x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs Hans Rosenfeld
2011-01-26 10:56   ` Ingo Molnar
2011-01-26 17:05     ` Hans Rosenfeld
2011-01-26 17:08     ` Hans Rosenfeld
2011-01-26 20:56       ` Ingo Molnar
2011-01-27 11:50         ` Hans Rosenfeld
2011-01-27 12:47           ` Ingo Molnar
2011-02-01 15:14             ` Hans Rosenfeld [this message]
2011-02-07 17:10             ` Hans Rosenfeld
2011-02-08 12:03               ` [tip:x86/amd-nb] " tip-bot for Hans Rosenfeld
  -- strict thread matches above, loose matches on Subject: below --
2010-12-20 17:13 [PATCH 0/4] x86, amd: family 0x15 L3 cache features Hans Rosenfeld
2010-12-20 17:13 ` [PATCH 4/4] x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs Hans Rosenfeld

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