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From: tip-bot for Andreas Herrmann <andreas.herrmann3@amd.com>
To: linux-tip-commits@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, hpa@zytor.com, mingo@redhat.com,
	andreas.herrmann3@amd.com, tglx@linutronix.de, mingo@elte.hu
Subject: [tip:x86/amd-nb] x86, amd: Normalize compute unit IDs on multi-node processors
Date: Wed, 26 Jan 2011 10:57:53 GMT	[thread overview]
Message-ID: <tip-d518573de63fb119e5e9a3137386544671387681@git.kernel.org> (raw)
In-Reply-To: <1295881543-572552-2-git-send-email-hans.rosenfeld@amd.com>

Commit-ID:  d518573de63fb119e5e9a3137386544671387681
Gitweb:     http://git.kernel.org/tip/d518573de63fb119e5e9a3137386544671387681
Author:     Andreas Herrmann <andreas.herrmann3@amd.com>
AuthorDate: Mon, 24 Jan 2011 16:05:40 +0100
Committer:  Ingo Molnar <mingo@elte.hu>
CommitDate: Wed, 26 Jan 2011 08:28:22 +0100

x86, amd: Normalize compute unit IDs on multi-node processors

On multi-node CPUs we don't need the socket wide compute unit ID
but the node-wide compute unit ID. Thus we need to normalize the
value. This is similar to what we do with cpu_core_id.

A compute unit is then identified by physical_package_id,
node_id, and compute_unit_id.

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
LKML-Reference: <1295881543-572552-2-git-send-email-hans.rosenfeld@amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
 arch/x86/kernel/cpu/amd.c |    8 ++++++--
 arch/x86/kernel/smpboot.c |    1 +
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 7c7bedb..990cc48 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -261,7 +261,7 @@ static int __cpuinit nearby_node(int apicid)
 #ifdef CONFIG_X86_HT
 static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c)
 {
-	u32 nodes;
+	u32 nodes, cores_per_cu;
 	u8 node_id;
 	int cpu = smp_processor_id();
 
@@ -276,6 +276,7 @@ static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c)
 		/* get compute unit information */
 		smp_num_siblings = ((ebx >> 8) & 3) + 1;
 		c->compute_unit_id = ebx & 0xff;
+		cores_per_cu = ((ebx >> 8) & 3) + 1;
 	} else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
 		u64 value;
 
@@ -288,15 +289,18 @@ static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c)
 	/* fixup multi-node processor information */
 	if (nodes > 1) {
 		u32 cores_per_node;
+		u32 cus_per_node;
 
 		set_cpu_cap(c, X86_FEATURE_AMD_DCM);
 		cores_per_node = c->x86_max_cores / nodes;
+		cus_per_node = cores_per_node / cores_per_cu;
 
 		/* store NodeID, use llc_shared_map to store sibling info */
 		per_cpu(cpu_llc_id, cpu) = node_id;
 
 		/* core id to be in range from 0 to (cores_per_node - 1) */
-		c->cpu_core_id = c->cpu_core_id % cores_per_node;
+		c->cpu_core_id %= cores_per_node;
+		c->compute_unit_id %= cus_per_node;
 	}
 }
 #endif
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index 0cbe8c0..fbaa222 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -414,6 +414,7 @@ void __cpuinit set_cpu_sibling_map(int cpu)
 
 			if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
 				if (c->phys_proc_id == o->phys_proc_id &&
+				    per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i) &&
 				    c->compute_unit_id == o->compute_unit_id)
 					link_thread_siblings(cpu, i);
 			} else if (c->phys_proc_id == o->phys_proc_id &&

  reply	other threads:[~2011-01-26 10:58 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-01-24 15:05 [PATCH 0/4] x86, amd: family 0x15 L3 cache features Hans Rosenfeld
2011-01-24 15:05 ` [PATCH 1/4] x86, amd: Normalize compute unit IDs on multi-node processors Hans Rosenfeld
2011-01-26 10:57   ` tip-bot for Andreas Herrmann [this message]
2011-02-14 14:30     ` [tip:x86/amd-nb] " Ingo Molnar
2011-02-14 17:14       ` [PATCH] x86, amd: Fix uninitialized variable warning Borislav Petkov
2011-02-15  3:10         ` [tip:x86/amd-nb] x86, amd: Initialize variable properly tip-bot for Borislav Petkov
2011-02-04 22:07   ` [PATCH 1/4] x86, amd: Normalize compute unit IDs on multi-node processors Andrew Morton
2011-01-24 15:05 ` [PATCH 2/4] x86, amd: Enable L3 cache index disable on family 0x15 Hans Rosenfeld
2011-01-26 10:58   ` [tip:x86/amd-nb] " tip-bot for Hans Rosenfeld
2011-01-24 15:05 ` [PATCH 3/4] x86, amd: Extend AMD northbridge caching code to support "Link Control" devices Hans Rosenfeld
2011-01-26 10:58   ` [tip:x86/amd-nb] " tip-bot for Hans Rosenfeld
2011-01-24 15:05 ` [PATCH 4/4] x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs Hans Rosenfeld
2011-01-26 10:56   ` Ingo Molnar
2011-01-26 17:05     ` Hans Rosenfeld
2011-01-26 17:08     ` Hans Rosenfeld
2011-01-26 20:56       ` Ingo Molnar
2011-01-27 11:50         ` Hans Rosenfeld
2011-01-27 12:47           ` Ingo Molnar
2011-02-01 15:14             ` Hans Rosenfeld
2011-02-07 17:10             ` Hans Rosenfeld
2011-02-08 12:03               ` [tip:x86/amd-nb] " tip-bot for Hans Rosenfeld

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