[PATCH 0/5] ARM: omap4 related fixes for 2.6.39

[PATCH 0/5] ARM: omap4 related fixes for 2.6.39

[Santosh Shilimkar]

The series mainly does below
	- Makes ARM local timers selection runtime instead of compile time.
	- Enables the LOCAL_TIMER support for OMAP4430
	- Add and enable PL310 Errata for flush by Way
	- Fixes the NR_CPU value in omap2plus config
	- Removes the un-necessary omap44xx_sram_init FIXME

Boot tested on OMAP4430 ES1.0 and ES2.X silicons.

The following changes since commit 100b33c8bd8a3235fd0b7948338d6cbb3db3c63d:
  Linus Torvalds (1):
        Linux 2.6.38-rc4

are available in the git repository at:

  git://dev.omapzoom.org/pub/scm/santosh/kernel-omap4-base.git omap4-misc_for.39

Santosh Shilimkar (5):
  ARM: smp: Select local timers vs dummy timer support runtime
  omap4: Enable ARM local timers with OMAP4430 es1.0 exception
  ARM: l2x0: Errata fix for flush by Way operation can cause data
    corruption
  omap2plus: omap4: Set NR_CPU to 2 instead of default 4
  omap4: Remove 'FIXME: omap44xx_sram_init not implemented'

 arch/arm/Kconfig                     |   11 +++++++++++
 arch/arm/configs/omap2plus_defconfig |    1 +
 arch/arm/include/asm/localtimer.h    |    8 +++++++-
 arch/arm/kernel/smp.c                |    7 +++----
 arch/arm/mach-msm/timer.c            |    3 ++-
 arch/arm/mach-omap2/Kconfig          |    2 ++
 arch/arm/mach-omap2/timer-mpu.c      |    7 ++++++-
 arch/arm/mach-realview/localtimer.c  |    3 ++-
 arch/arm/mach-s5pv310/localtimer.c   |    3 ++-
 arch/arm/mach-shmobile/localtimer.c  |    3 ++-
 arch/arm/mach-tegra/localtimer.c     |    3 ++-
 arch/arm/mach-ux500/localtimer.c     |    3 ++-
 arch/arm/mach-vexpress/localtimer.c  |    3 ++-
 arch/arm/mm/cache-l2x0.c             |   16 ++++++++++------
 arch/arm/plat-omap/sram.c            |   16 ----------------
 15 files changed, 54 insertions(+), 35 deletions(-)

[PATCH 0/5] ARM: omap4 related fixes for 2.6.39

[Santosh Shilimkar]

The series mainly does below
	- Makes ARM local timers selection runtime instead of compile time.
	- Enables the LOCAL_TIMER support for OMAP4430
	- Add and enable PL310 Errata for flush by Way
	- Fixes the NR_CPU value in omap2plus config
	- Removes the un-necessary omap44xx_sram_init FIXME

Boot tested on OMAP4430 ES1.0 and ES2.X silicons.

The following changes since commit 100b33c8bd8a3235fd0b7948338d6cbb3db3c63d:
  Linus Torvalds (1):
        Linux 2.6.38-rc4

are available in the git repository at:

  git://dev.omapzoom.org/pub/scm/santosh/kernel-omap4-base.git omap4-misc_for.39

Santosh Shilimkar (5):
  ARM: smp: Select local timers vs dummy timer support runtime
  omap4: Enable ARM local timers with OMAP4430 es1.0 exception
  ARM: l2x0: Errata fix for flush by Way operation can cause data
    corruption
  omap2plus: omap4: Set NR_CPU to 2 instead of default 4
  omap4: Remove 'FIXME: omap44xx_sram_init not implemented'

 arch/arm/Kconfig                     |   11 +++++++++++
 arch/arm/configs/omap2plus_defconfig |    1 +
 arch/arm/include/asm/localtimer.h    |    8 +++++++-
 arch/arm/kernel/smp.c                |    7 +++----
 arch/arm/mach-msm/timer.c            |    3 ++-
 arch/arm/mach-omap2/Kconfig          |    2 ++
 arch/arm/mach-omap2/timer-mpu.c      |    7 ++++++-
 arch/arm/mach-realview/localtimer.c  |    3 ++-
 arch/arm/mach-s5pv310/localtimer.c   |    3 ++-
 arch/arm/mach-shmobile/localtimer.c  |    3 ++-
 arch/arm/mach-tegra/localtimer.c     |    3 ++-
 arch/arm/mach-ux500/localtimer.c     |    3 ++-
 arch/arm/mach-vexpress/localtimer.c  |    3 ++-
 arch/arm/mm/cache-l2x0.c             |   16 ++++++++++------
 arch/arm/plat-omap/sram.c            |   16 ----------------
 15 files changed, 54 insertions(+), 35 deletions(-)

[PATCH 1/5] ARM: smp: Select local timers vs dummy timer support runtime

[Santosh Shilimkar]

The current code support of dummy timers in absence of local
timer is compile time. This is an attempt to convert it to runtime
so that on few SOC version if the local timers aren't supported
kernel can switch to dummy timers. OMAP4430 ES1.0 does suffer from
this limitation.

This patch should not have any functional impact on affected
files.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@codeaurora.org>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Colin Cross <ccross@android.com>
Cc: Erik Gilling <konkers@android.com>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@stericsson.com>
---
 arch/arm/include/asm/localtimer.h   |    8 +++++++-
 arch/arm/kernel/smp.c               |    7 +++----
 arch/arm/mach-msm/timer.c           |    3 ++-
 arch/arm/mach-omap2/timer-mpu.c     |    3 ++-
 arch/arm/mach-realview/localtimer.c |    3 ++-
 arch/arm/mach-s5pv310/localtimer.c  |    3 ++-
 arch/arm/mach-shmobile/localtimer.c |    3 ++-
 arch/arm/mach-tegra/localtimer.c    |    3 ++-
 arch/arm/mach-ux500/localtimer.c    |    3 ++-
 arch/arm/mach-vexpress/localtimer.c |    3 ++-
 10 files changed, 26 insertions(+), 13 deletions(-)

diff --git a/arch/arm/include/asm/localtimer.h b/arch/arm/include/asm/localtimer.h
index 6bc63ab..080d74f 100644
--- a/arch/arm/include/asm/localtimer.h
+++ b/arch/arm/include/asm/localtimer.h
@@ -44,8 +44,14 @@ int local_timer_ack(void);
 /*
  * Setup a local timer interrupt for a CPU.
  */
-void local_timer_setup(struct clock_event_device *);
+int local_timer_setup(struct clock_event_device *);
 
+#else
+
+static inline int local_timer_setup(struct clock_event_device *evt)
+{
+	return -ENXIO;
+}
 #endif
 
 #endif
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 4539ebc..7b9cc53 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -474,13 +474,12 @@ static void smp_timer_broadcast(const struct cpumask *mask)
 #define smp_timer_broadcast	NULL
 #endif
 
-#ifndef CONFIG_LOCAL_TIMERS
 static void broadcast_timer_set_mode(enum clock_event_mode mode,
 	struct clock_event_device *evt)
 {
 }
 
-static void local_timer_setup(struct clock_event_device *evt)
+static void dummy_timer_setup(struct clock_event_device *evt)
 {
 	evt->name	= "dummy_timer";
 	evt->features	= CLOCK_EVT_FEAT_ONESHOT |
@@ -492,7 +491,6 @@ static void local_timer_setup(struct clock_event_device *evt)
 
 	clockevents_register_device(evt);
 }
-#endif
 
 void __cpuinit percpu_timer_setup(void)
 {
@@ -502,7 +500,8 @@ void __cpuinit percpu_timer_setup(void)
 	evt->cpumask = cpumask_of(cpu);
 	evt->broadcast = smp_timer_broadcast;
 
-	local_timer_setup(evt);
+	if (local_timer_setup(evt))
+		dummy_timer_setup(evt);
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index c105d28..ae85aa9 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -255,7 +255,7 @@ static void __init msm_timer_init(void)
 }
 
 #ifdef CONFIG_SMP
-void __cpuinit local_timer_setup(struct clock_event_device *evt)
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
 	struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];
 
@@ -287,6 +287,7 @@ void __cpuinit local_timer_setup(struct clock_event_device *evt)
 	gic_enable_ppi(clock->irq.irq);
 
 	clockevents_register_device(evt);
+	return 0;
 }
 
 inline int local_timer_ack(void)
diff --git a/arch/arm/mach-omap2/timer-mpu.c b/arch/arm/mach-omap2/timer-mpu.c
index 954682e..09c73dc 100644
--- a/arch/arm/mach-omap2/timer-mpu.c
+++ b/arch/arm/mach-omap2/timer-mpu.c
@@ -26,9 +26,10 @@
 /*
  * Setup the local clock events for a CPU.
  */
-void __cpuinit local_timer_setup(struct clock_event_device *evt)
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
 	evt->irq = OMAP44XX_IRQ_LOCALTIMER;
 	twd_timer_setup(evt);
+	return 0;
 }
 
diff --git a/arch/arm/mach-realview/localtimer.c b/arch/arm/mach-realview/localtimer.c
index 60b4e11..aca29ce 100644
--- a/arch/arm/mach-realview/localtimer.c
+++ b/arch/arm/mach-realview/localtimer.c
@@ -19,8 +19,9 @@
 /*
  * Setup the local clock events for a CPU.
  */
-void __cpuinit local_timer_setup(struct clock_event_device *evt)
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
 	evt->irq = IRQ_LOCALTIMER;
 	twd_timer_setup(evt);
+	return 0;
 }
diff --git a/arch/arm/mach-s5pv310/localtimer.c b/arch/arm/mach-s5pv310/localtimer.c
index 2784036..8239c6a 100644
--- a/arch/arm/mach-s5pv310/localtimer.c
+++ b/arch/arm/mach-s5pv310/localtimer.c
@@ -18,8 +18,9 @@
 /*
  * Setup the local clock events for a CPU.
  */
-void __cpuinit local_timer_setup(struct clock_event_device *evt)
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
 	evt->irq = IRQ_LOCALTIMER;
 	twd_timer_setup(evt);
+	return 0;
 }
diff --git a/arch/arm/mach-shmobile/localtimer.c b/arch/arm/mach-shmobile/localtimer.c
index 2111c28..ad9ccc9 100644
--- a/arch/arm/mach-shmobile/localtimer.c
+++ b/arch/arm/mach-shmobile/localtimer.c
@@ -18,8 +18,9 @@
 /*
  * Setup the local clock events for a CPU.
  */
-void __cpuinit local_timer_setup(struct clock_event_device *evt)
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
 	evt->irq = 29;
 	twd_timer_setup(evt);
+	return 0;
 }
diff --git a/arch/arm/mach-tegra/localtimer.c b/arch/arm/mach-tegra/localtimer.c
index f81ca7c..e91d681 100644
--- a/arch/arm/mach-tegra/localtimer.c
+++ b/arch/arm/mach-tegra/localtimer.c
@@ -18,8 +18,9 @@
 /*
  * Setup the local clock events for a CPU.
  */
-void __cpuinit local_timer_setup(struct clock_event_device *evt)
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
 	evt->irq = IRQ_LOCALTIMER;
 	twd_timer_setup(evt);
+	return 0;
 }
diff --git a/arch/arm/mach-ux500/localtimer.c b/arch/arm/mach-ux500/localtimer.c
index 2288f6a..5ba1133 100644
--- a/arch/arm/mach-ux500/localtimer.c
+++ b/arch/arm/mach-ux500/localtimer.c
@@ -21,8 +21,9 @@
 /*
  * Setup the local clock events for a CPU.
  */
-void __cpuinit local_timer_setup(struct clock_event_device *evt)
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
 	evt->irq = IRQ_LOCALTIMER;
 	twd_timer_setup(evt);
+	return 0;
 }
diff --git a/arch/arm/mach-vexpress/localtimer.c b/arch/arm/mach-vexpress/localtimer.c
index c0e3a59..e5adbfa 100644
--- a/arch/arm/mach-vexpress/localtimer.c
+++ b/arch/arm/mach-vexpress/localtimer.c
@@ -19,8 +19,9 @@
 /*
  * Setup the local clock events for a CPU.
  */
-void __cpuinit local_timer_setup(struct clock_event_device *evt)
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
 	evt->irq = IRQ_LOCALTIMER;
 	twd_timer_setup(evt);
+	return 0;
 }
-- 
1.6.0.4

[PATCH 1/5] ARM: smp: Select local timers vs dummy timer support runtime

[Santosh Shilimkar]

The current code support of dummy timers in absence of local
timer is compile time. This is an attempt to convert it to runtime
so that on few SOC version if the local timers aren't supported
kernel can switch to dummy timers. OMAP4430 ES1.0 does suffer from
this limitation.

This patch should not have any functional impact on affected
files.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@codeaurora.org>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Colin Cross <ccross@android.com>
Cc: Erik Gilling <konkers@android.com>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@stericsson.com>
---
 arch/arm/include/asm/localtimer.h   |    8 +++++++-
 arch/arm/kernel/smp.c               |    7 +++----
 arch/arm/mach-msm/timer.c           |    3 ++-
 arch/arm/mach-omap2/timer-mpu.c     |    3 ++-
 arch/arm/mach-realview/localtimer.c |    3 ++-
 arch/arm/mach-s5pv310/localtimer.c  |    3 ++-
 arch/arm/mach-shmobile/localtimer.c |    3 ++-
 arch/arm/mach-tegra/localtimer.c    |    3 ++-
 arch/arm/mach-ux500/localtimer.c    |    3 ++-
 arch/arm/mach-vexpress/localtimer.c |    3 ++-
 10 files changed, 26 insertions(+), 13 deletions(-)

diff --git a/arch/arm/include/asm/localtimer.h b/arch/arm/include/asm/localtimer.h
index 6bc63ab..080d74f 100644
--- a/arch/arm/include/asm/localtimer.h
+++ b/arch/arm/include/asm/localtimer.h
@@ -44,8 +44,14 @@ int local_timer_ack(void);
 /*
  * Setup a local timer interrupt for a CPU.
  */
-void local_timer_setup(struct clock_event_device *);
+int local_timer_setup(struct clock_event_device *);
 
+#else
+
+static inline int local_timer_setup(struct clock_event_device *evt)
+{
+	return -ENXIO;
+}
 #endif
 
 #endif
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 4539ebc..7b9cc53 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -474,13 +474,12 @@ static void smp_timer_broadcast(const struct cpumask *mask)
 #define smp_timer_broadcast	NULL
 #endif
 
-#ifndef CONFIG_LOCAL_TIMERS
 static void broadcast_timer_set_mode(enum clock_event_mode mode,
 	struct clock_event_device *evt)
 {
 }
 
-static void local_timer_setup(struct clock_event_device *evt)
+static void dummy_timer_setup(struct clock_event_device *evt)
 {
 	evt->name	= "dummy_timer";
 	evt->features	= CLOCK_EVT_FEAT_ONESHOT |
@@ -492,7 +491,6 @@ static void local_timer_setup(struct clock_event_device *evt)
 
 	clockevents_register_device(evt);
 }
-#endif
 
 void __cpuinit percpu_timer_setup(void)
 {
@@ -502,7 +500,8 @@ void __cpuinit percpu_timer_setup(void)
 	evt->cpumask = cpumask_of(cpu);
 	evt->broadcast = smp_timer_broadcast;
 
-	local_timer_setup(evt);
+	if (local_timer_setup(evt))
+		dummy_timer_setup(evt);
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index c105d28..ae85aa9 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -255,7 +255,7 @@ static void __init msm_timer_init(void)
 }
 
 #ifdef CONFIG_SMP
-void __cpuinit local_timer_setup(struct clock_event_device *evt)
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
 	struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];
 
@@ -287,6 +287,7 @@ void __cpuinit local_timer_setup(struct clock_event_device *evt)
 	gic_enable_ppi(clock->irq.irq);
 
 	clockevents_register_device(evt);
+	return 0;
 }
 
 inline int local_timer_ack(void)
diff --git a/arch/arm/mach-omap2/timer-mpu.c b/arch/arm/mach-omap2/timer-mpu.c
index 954682e..09c73dc 100644
--- a/arch/arm/mach-omap2/timer-mpu.c
+++ b/arch/arm/mach-omap2/timer-mpu.c
@@ -26,9 +26,10 @@
 /*
  * Setup the local clock events for a CPU.
  */
-void __cpuinit local_timer_setup(struct clock_event_device *evt)
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
 	evt->irq = OMAP44XX_IRQ_LOCALTIMER;
 	twd_timer_setup(evt);
+	return 0;
 }
 
diff --git a/arch/arm/mach-realview/localtimer.c b/arch/arm/mach-realview/localtimer.c
index 60b4e11..aca29ce 100644
--- a/arch/arm/mach-realview/localtimer.c
+++ b/arch/arm/mach-realview/localtimer.c
@@ -19,8 +19,9 @@
 /*
  * Setup the local clock events for a CPU.
  */
-void __cpuinit local_timer_setup(struct clock_event_device *evt)
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
 	evt->irq = IRQ_LOCALTIMER;
 	twd_timer_setup(evt);
+	return 0;
 }
diff --git a/arch/arm/mach-s5pv310/localtimer.c b/arch/arm/mach-s5pv310/localtimer.c
index 2784036..8239c6a 100644
--- a/arch/arm/mach-s5pv310/localtimer.c
+++ b/arch/arm/mach-s5pv310/localtimer.c
@@ -18,8 +18,9 @@
 /*
  * Setup the local clock events for a CPU.
  */
-void __cpuinit local_timer_setup(struct clock_event_device *evt)
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
 	evt->irq = IRQ_LOCALTIMER;
 	twd_timer_setup(evt);
+	return 0;
 }
diff --git a/arch/arm/mach-shmobile/localtimer.c b/arch/arm/mach-shmobile/localtimer.c
index 2111c28..ad9ccc9 100644
--- a/arch/arm/mach-shmobile/localtimer.c
+++ b/arch/arm/mach-shmobile/localtimer.c
@@ -18,8 +18,9 @@
 /*
  * Setup the local clock events for a CPU.
  */
-void __cpuinit local_timer_setup(struct clock_event_device *evt)
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
 	evt->irq = 29;
 	twd_timer_setup(evt);
+	return 0;
 }
diff --git a/arch/arm/mach-tegra/localtimer.c b/arch/arm/mach-tegra/localtimer.c
index f81ca7c..e91d681 100644
--- a/arch/arm/mach-tegra/localtimer.c
+++ b/arch/arm/mach-tegra/localtimer.c
@@ -18,8 +18,9 @@
 /*
  * Setup the local clock events for a CPU.
  */
-void __cpuinit local_timer_setup(struct clock_event_device *evt)
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
 	evt->irq = IRQ_LOCALTIMER;
 	twd_timer_setup(evt);
+	return 0;
 }
diff --git a/arch/arm/mach-ux500/localtimer.c b/arch/arm/mach-ux500/localtimer.c
index 2288f6a..5ba1133 100644
--- a/arch/arm/mach-ux500/localtimer.c
+++ b/arch/arm/mach-ux500/localtimer.c
@@ -21,8 +21,9 @@
 /*
  * Setup the local clock events for a CPU.
  */
-void __cpuinit local_timer_setup(struct clock_event_device *evt)
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
 	evt->irq = IRQ_LOCALTIMER;
 	twd_timer_setup(evt);
+	return 0;
 }
diff --git a/arch/arm/mach-vexpress/localtimer.c b/arch/arm/mach-vexpress/localtimer.c
index c0e3a59..e5adbfa 100644
--- a/arch/arm/mach-vexpress/localtimer.c
+++ b/arch/arm/mach-vexpress/localtimer.c
@@ -19,8 +19,9 @@
 /*
  * Setup the local clock events for a CPU.
  */
-void __cpuinit local_timer_setup(struct clock_event_device *evt)
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
 	evt->irq = IRQ_LOCALTIMER;
 	twd_timer_setup(evt);
+	return 0;
 }
-- 
1.6.0.4

[PATCH 2/5] omap4: Enable ARM local timers with OMAP4430 es1.0 exception

[Santosh Shilimkar]

On OMAP4430 ES1.0 the local timers are gated by security. Enable the
CONFIG_LOCAL_TIMERS for omap2plus build and handle the OMAP4430 es1.0
exception case.

This patch has dependency on the first patch in this series.
	ARM: smp: Select local timers vs dummy timer support runtime

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/mach-omap2/Kconfig     |    1 +
 arch/arm/mach-omap2/timer-mpu.c |    4 ++++
 2 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 1a2cf62..f285dd7 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -44,6 +44,7 @@ config ARCH_OMAP4
 	depends on ARCH_OMAP2PLUS
 	select CPU_V7
 	select ARM_GIC
+	select LOCAL_TIMERS
 	select PL310_ERRATA_588369
 	select ARM_ERRATA_720789
 	select ARCH_HAS_OPP
diff --git a/arch/arm/mach-omap2/timer-mpu.c b/arch/arm/mach-omap2/timer-mpu.c
index 09c73dc..31c0ac4 100644
--- a/arch/arm/mach-omap2/timer-mpu.c
+++ b/arch/arm/mach-omap2/timer-mpu.c
@@ -28,6 +28,10 @@
  */
 int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
+	/* Local timers are not supprted on OMAP4430 ES1.0 */
+	if (omap_rev() == OMAP4430_REV_ES1_0)
+		return -ENXIO;
+
 	evt->irq = OMAP44XX_IRQ_LOCALTIMER;
 	twd_timer_setup(evt);
 	return 0;
-- 
1.6.0.4

[PATCH 2/5] omap4: Enable ARM local timers with OMAP4430 es1.0 exception

[Santosh Shilimkar]

On OMAP4430 ES1.0 the local timers are gated by security. Enable the
CONFIG_LOCAL_TIMERS for omap2plus build and handle the OMAP4430 es1.0
exception case.

This patch has dependency on the first patch in this series.
	ARM: smp: Select local timers vs dummy timer support runtime

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/mach-omap2/Kconfig     |    1 +
 arch/arm/mach-omap2/timer-mpu.c |    4 ++++
 2 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 1a2cf62..f285dd7 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -44,6 +44,7 @@ config ARCH_OMAP4
 	depends on ARCH_OMAP2PLUS
 	select CPU_V7
 	select ARM_GIC
+	select LOCAL_TIMERS
 	select PL310_ERRATA_588369
 	select ARM_ERRATA_720789
 	select ARCH_HAS_OPP
diff --git a/arch/arm/mach-omap2/timer-mpu.c b/arch/arm/mach-omap2/timer-mpu.c
index 09c73dc..31c0ac4 100644
--- a/arch/arm/mach-omap2/timer-mpu.c
+++ b/arch/arm/mach-omap2/timer-mpu.c
@@ -28,6 +28,10 @@
  */
 int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
+	/* Local timers are not supprted on OMAP4430 ES1.0 */
+	if (omap_rev() == OMAP4430_REV_ES1_0)
+		return -ENXIO;
+
 	evt->irq = OMAP44XX_IRQ_LOCALTIMER;
 	twd_timer_setup(evt);
 	return 0;
-- 
1.6.0.4

[PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Santosh Shilimkar]

PL310 implements the Clean & Invalidate by Way L2 cache maintenance
operation (offset 0x7FC). This operation runs in background so that
PL310 can handle normal accesses while it is in progress. Under very
rare circumstances, due to this erratum, write data can be lost when
PL310 treats a cacheable write transaction during a Clean & Invalidate
by Way operation.

Workaround:
Disable Write-Back and Cache Linefill (Debug Control Register)
Clean & Invalidate by Way (0x7FC)
Re-enable Write-Back and Cache Linefill (Debug Control Register)

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm/Kconfig            |   11 +++++++++++
 arch/arm/mach-omap2/Kconfig |    1 +
 arch/arm/mm/cache-l2x0.c    |   16 ++++++++++------
 3 files changed, 22 insertions(+), 6 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5cff165..2e6b879 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1177,6 +1177,17 @@ config ARM_ERRATA_743622
 	  visible impact on the overall performance or power consumption of the
 	  processor.
 
+config PL310_ERRATA_727915
+	bool "Background Clean & Invalidate by Way operation can cause data corruption"
+	depends on CACHE_L2X0 && ARCH_OMAP4
+	help
+	  PL310 implements the Clean & Invalidate by Way L2 cache maintenance
+	  operation (offset 0x7FC). This operation runs in background so that
+	  PL310 can handle normal accesses while it is in progress. Under very
+	  rare circumstances, due to this erratum, write data can be lost when
+	  PL310 treats a cacheable write transaction during a Clean &
+	  Invalidate by Way operation Note that this errata uses Texas
+	  Instrument's secure monitor api to implement the work around.
 endmenu
 
 source "arch/arm/common/Kconfig"
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index f285dd7..1f0ff75 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -46,6 +46,7 @@ config ARCH_OMAP4
 	select ARM_GIC
 	select LOCAL_TIMERS
 	select PL310_ERRATA_588369
+	select PL310_ERRATA_727915
 	select ARM_ERRATA_720789
 	select ARCH_HAS_OPP
 	select PM_OPP if PM
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 170c9bb..c7c8fbe 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -67,7 +67,7 @@ static inline void l2x0_inv_line(unsigned long addr)
 	writel_relaxed(addr, base + L2X0_INV_LINE_PA);
 }
 
-#ifdef CONFIG_PL310_ERRATA_588369
+#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
 static void debug_writel(unsigned long val)
 {
 	extern void omap_smc1(u32 fn, u32 arg);
@@ -78,7 +78,14 @@ static void debug_writel(unsigned long val)
 	 */
 	omap_smc1(0x100, val);
 }
+#else
+/* Optimised out for non-errata case */
+static inline void debug_writel(unsigned long val)
+{
+}
+#endif
 
+#ifdef CONFIG_PL310_ERRATA_588369
 static inline void l2x0_flush_line(unsigned long addr)
 {
 	void __iomem *base = l2x0_base;
@@ -91,11 +98,6 @@ static inline void l2x0_flush_line(unsigned long addr)
 }
 #else
 
-/* Optimised out for non-errata case */
-static inline void debug_writel(unsigned long val)
-{
-}
-
 static inline void l2x0_flush_line(unsigned long addr)
 {
 	void __iomem *base = l2x0_base;
@@ -119,9 +121,11 @@ static void l2x0_flush_all(void)
 
 	/* clean all ways */
 	spin_lock_irqsave(&l2x0_lock, flags);
+	debug_writel(0x03);
 	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
 	cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
 	cache_sync();
+	debug_writel(0x00);
 	spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
-- 
1.6.0.4

[PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Santosh Shilimkar]

PL310 implements the Clean & Invalidate by Way L2 cache maintenance
operation (offset 0x7FC). This operation runs in background so that
PL310 can handle normal accesses while it is in progress. Under very
rare circumstances, due to this erratum, write data can be lost when
PL310 treats a cacheable write transaction during a Clean & Invalidate
by Way operation.

Workaround:
Disable Write-Back and Cache Linefill (Debug Control Register)
Clean & Invalidate by Way (0x7FC)
Re-enable Write-Back and Cache Linefill (Debug Control Register)

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm/Kconfig            |   11 +++++++++++
 arch/arm/mach-omap2/Kconfig |    1 +
 arch/arm/mm/cache-l2x0.c    |   16 ++++++++++------
 3 files changed, 22 insertions(+), 6 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5cff165..2e6b879 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1177,6 +1177,17 @@ config ARM_ERRATA_743622
 	  visible impact on the overall performance or power consumption of the
 	  processor.
 
+config PL310_ERRATA_727915
+	bool "Background Clean & Invalidate by Way operation can cause data corruption"
+	depends on CACHE_L2X0 && ARCH_OMAP4
+	help
+	  PL310 implements the Clean & Invalidate by Way L2 cache maintenance
+	  operation (offset 0x7FC). This operation runs in background so that
+	  PL310 can handle normal accesses while it is in progress. Under very
+	  rare circumstances, due to this erratum, write data can be lost when
+	  PL310 treats a cacheable write transaction during a Clean &
+	  Invalidate by Way operation Note that this errata uses Texas
+	  Instrument's secure monitor api to implement the work around.
 endmenu
 
 source "arch/arm/common/Kconfig"
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index f285dd7..1f0ff75 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -46,6 +46,7 @@ config ARCH_OMAP4
 	select ARM_GIC
 	select LOCAL_TIMERS
 	select PL310_ERRATA_588369
+	select PL310_ERRATA_727915
 	select ARM_ERRATA_720789
 	select ARCH_HAS_OPP
 	select PM_OPP if PM
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 170c9bb..c7c8fbe 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -67,7 +67,7 @@ static inline void l2x0_inv_line(unsigned long addr)
 	writel_relaxed(addr, base + L2X0_INV_LINE_PA);
 }
 
-#ifdef CONFIG_PL310_ERRATA_588369
+#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
 static void debug_writel(unsigned long val)
 {
 	extern void omap_smc1(u32 fn, u32 arg);
@@ -78,7 +78,14 @@ static void debug_writel(unsigned long val)
 	 */
 	omap_smc1(0x100, val);
 }
+#else
+/* Optimised out for non-errata case */
+static inline void debug_writel(unsigned long val)
+{
+}
+#endif
 
+#ifdef CONFIG_PL310_ERRATA_588369
 static inline void l2x0_flush_line(unsigned long addr)
 {
 	void __iomem *base = l2x0_base;
@@ -91,11 +98,6 @@ static inline void l2x0_flush_line(unsigned long addr)
 }
 #else
 
-/* Optimised out for non-errata case */
-static inline void debug_writel(unsigned long val)
-{
-}
-
 static inline void l2x0_flush_line(unsigned long addr)
 {
 	void __iomem *base = l2x0_base;
@@ -119,9 +121,11 @@ static void l2x0_flush_all(void)
 
 	/* clean all ways */
 	spin_lock_irqsave(&l2x0_lock, flags);
+	debug_writel(0x03);
 	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
 	cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
 	cache_sync();
+	debug_writel(0x00);
 	spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
-- 
1.6.0.4

[PATCH 4/5] omap2plus: omap4: Set NR_CPU to 2 instead of default 4

[Santosh Shilimkar]

The omap2plus_defconfig picks default NR_CPU value as 4 which isn't
correct for OMAP4430. Available CPUs are ony 2, so fix the same.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/configs/omap2plus_defconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index ae890ca..019fb7c 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -58,6 +58,7 @@ CONFIG_ARM_ERRATA_411920=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_SMP=y
+CONFIG_NR_CPUS=2
 # CONFIG_LOCAL_TIMERS is not set
 CONFIG_AEABI=y
 CONFIG_LEDS=y
-- 
1.6.0.4

[PATCH 4/5] omap2plus: omap4: Set NR_CPU to 2 instead of default 4

[Santosh Shilimkar]

The omap2plus_defconfig picks default NR_CPU value as 4 which isn't
correct for OMAP4430. Available CPUs are ony 2, so fix the same.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/configs/omap2plus_defconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index ae890ca..019fb7c 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -58,6 +58,7 @@ CONFIG_ARM_ERRATA_411920=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_SMP=y
+CONFIG_NR_CPUS=2
 # CONFIG_LOCAL_TIMERS is not set
 CONFIG_AEABI=y
 CONFIG_LEDS=y
-- 
1.6.0.4

[PATCH 5/5] omap4: Remove 'FIXME: omap44xx_sram_init not implemented'

[Santosh Shilimkar]

The omap44xx_sram_init() implements functionality to push some
code on SRAM whenever the code can't be executed from external
memory. The low power and DVFS code can be executed from
external DDR itself thanks to OMAP4  memory controller hardware
support. So on OMAP4, sram_push kind of functionality isn't needed.

Hence remove the FIXME warning added for implementing sram push
feature on OMAP4.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/plat-omap/sram.c |   16 ----------------
 1 files changed, 0 insertions(+), 16 deletions(-)

diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index e26e504..2d7bded 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -405,20 +405,6 @@ static inline int omap34xx_sram_init(void)
 }
 #endif
 
-#ifdef CONFIG_ARCH_OMAP4
-static int __init omap44xx_sram_init(void)
-{
-	printk(KERN_ERR "FIXME: %s not implemented\n", __func__);
-
-	return -ENODEV;
-}
-#else
-static inline int omap44xx_sram_init(void)
-{
-	return 0;
-}
-#endif
-
 int __init omap_sram_init(void)
 {
 	omap_detect_sram();
@@ -432,8 +418,6 @@ int __init omap_sram_init(void)
 		omap243x_sram_init();
 	else if (cpu_is_omap34xx())
 		omap34xx_sram_init();
-	else if (cpu_is_omap44xx())
-		omap44xx_sram_init();
 
 	return 0;
 }
-- 
1.6.0.4

[PATCH 5/5] omap4: Remove 'FIXME: omap44xx_sram_init not implemented'

[Santosh Shilimkar]

The omap44xx_sram_init() implements functionality to push some
code on SRAM whenever the code can't be executed from external
memory. The low power and DVFS code can be executed from
external DDR itself thanks to OMAP4  memory controller hardware
support. So on OMAP4, sram_push kind of functionality isn't needed.

Hence remove the FIXME warning added for implementing sram push
feature on OMAP4.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/plat-omap/sram.c |   16 ----------------
 1 files changed, 0 insertions(+), 16 deletions(-)

diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index e26e504..2d7bded 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -405,20 +405,6 @@ static inline int omap34xx_sram_init(void)
 }
 #endif
 
-#ifdef CONFIG_ARCH_OMAP4
-static int __init omap44xx_sram_init(void)
-{
-	printk(KERN_ERR "FIXME: %s not implemented\n", __func__);
-
-	return -ENODEV;
-}
-#else
-static inline int omap44xx_sram_init(void)
-{
-	return 0;
-}
-#endif
-
 int __init omap_sram_init(void)
 {
 	omap_detect_sram();
@@ -432,8 +418,6 @@ int __init omap_sram_init(void)
 		omap243x_sram_init();
 	else if (cpu_is_omap34xx())
 		omap34xx_sram_init();
-	else if (cpu_is_omap44xx())
-		omap44xx_sram_init();
 
 	return 0;
 }
-- 
1.6.0.4

Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Andrei Warkentin]

On Sat, Feb 12, 2011 at 5:29 AM, Santosh Shilimkar
<santosh.shilimkar@ti.com> wrote:
> PL310 implements the Clean & Invalidate by Way L2 cache maintenance
> operation (offset 0x7FC). This operation runs in background so that
> PL310 can handle normal accesses while it is in progress. Under very
> rare circumstances, due to this erratum, write data can be lost when
> PL310 treats a cacheable write transaction during a Clean & Invalidate
> by Way operation.
>
> Workaround:
> Disable Write-Back and Cache Linefill (Debug Control Register)
> Clean & Invalidate by Way (0x7FC)
> Re-enable Write-Back and Cache Linefill (Debug Control Register)
>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> ---
>  arch/arm/Kconfig            |   11 +++++++++++
>  arch/arm/mach-omap2/Kconfig |    1 +
>  arch/arm/mm/cache-l2x0.c    |   16 ++++++++++------
>  3 files changed, 22 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 5cff165..2e6b879 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1177,6 +1177,17 @@ config ARM_ERRATA_743622
>          visible impact on the overall performance or power consumption of the
>          processor.
>
> +config PL310_ERRATA_727915
> +       bool "Background Clean & Invalidate by Way operation can cause data corruption"
> +       depends on CACHE_L2X0 && ARCH_OMAP4
> +       help
> +         PL310 implements the Clean & Invalidate by Way L2 cache maintenance
> +         operation (offset 0x7FC). This operation runs in background so that
> +         PL310 can handle normal accesses while it is in progress. Under very
> +         rare circumstances, due to this erratum, write data can be lost when
> +         PL310 treats a cacheable write transaction during a Clean &
> +         Invalidate by Way operation Note that this errata uses Texas
> +         Instrument's secure monitor api to implement the work around.
>  endmenu
>
>  source "arch/arm/common/Kconfig"
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index f285dd7..1f0ff75 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -46,6 +46,7 @@ config ARCH_OMAP4
>        select ARM_GIC
>        select LOCAL_TIMERS
>        select PL310_ERRATA_588369
> +       select PL310_ERRATA_727915
>        select ARM_ERRATA_720789
>        select ARCH_HAS_OPP
>        select PM_OPP if PM
> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> index 170c9bb..c7c8fbe 100644
> --- a/arch/arm/mm/cache-l2x0.c
> +++ b/arch/arm/mm/cache-l2x0.c
> @@ -67,7 +67,7 @@ static inline void l2x0_inv_line(unsigned long addr)
>        writel_relaxed(addr, base + L2X0_INV_LINE_PA);
>  }
>
> -#ifdef CONFIG_PL310_ERRATA_588369
> +#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
>  static void debug_writel(unsigned long val)
>  {
>        extern void omap_smc1(u32 fn, u32 arg);
> @@ -78,7 +78,14 @@ static void debug_writel(unsigned long val)
>         */
>        omap_smc1(0x100, val);
>  }
> +#else
> +/* Optimised out for non-errata case */
> +static inline void debug_writel(unsigned long val)
> +{
> +}
> +#endif
>
> +#ifdef CONFIG_PL310_ERRATA_588369
>  static inline void l2x0_flush_line(unsigned long addr)
>  {
>        void __iomem *base = l2x0_base;
> @@ -91,11 +98,6 @@ static inline void l2x0_flush_line(unsigned long addr)
>  }
>  #else
>
> -/* Optimised out for non-errata case */
> -static inline void debug_writel(unsigned long val)
> -{
> -}
> -
>  static inline void l2x0_flush_line(unsigned long addr)
>  {
>        void __iomem *base = l2x0_base;
> @@ -119,9 +121,11 @@ static void l2x0_flush_all(void)
>
>        /* clean all ways */
>        spin_lock_irqsave(&l2x0_lock, flags);
> +       debug_writel(0x03);
>        writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
>        cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
>        cache_sync();
> +       debug_writel(0x00);
>        spin_unlock_irqrestore(&l2x0_lock, flags);
>  }
>
> --
> 1.6.0.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>

Can these PL310 errata fixes be made more generic? PL310 is present in
non-OMAP platforms too, which lack the TI hypervisor. And these
platforms might have the same PL310 rev, and suffer the same glitches.
While ideally there is some kind of hypervisor_ops to modify the
protected register, at the very least there should be the generic
debug_write handling the  "I  can write all PL310 regs" case. If
you're interested I have a patch someplace that tried to do this,
hopefully I can still find it.

[PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Andrei Warkentin]

On Sat, Feb 12, 2011 at 5:29 AM, Santosh Shilimkar
<santosh.shilimkar@ti.com> wrote:
> PL310 implements the Clean & Invalidate by Way L2 cache maintenance
> operation (offset 0x7FC). This operation runs in background so that
> PL310 can handle normal accesses while it is in progress. Under very
> rare circumstances, due to this erratum, write data can be lost when
> PL310 treats a cacheable write transaction during a Clean & Invalidate
> by Way operation.
>
> Workaround:
> Disable Write-Back and Cache Linefill (Debug Control Register)
> Clean & Invalidate by Way (0x7FC)
> Re-enable Write-Back and Cache Linefill (Debug Control Register)
>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> ---
> ?arch/arm/Kconfig ? ? ? ? ? ?| ? 11 +++++++++++
> ?arch/arm/mach-omap2/Kconfig | ? ?1 +
> ?arch/arm/mm/cache-l2x0.c ? ?| ? 16 ++++++++++------
> ?3 files changed, 22 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 5cff165..2e6b879 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1177,6 +1177,17 @@ config ARM_ERRATA_743622
> ? ? ? ? ?visible impact on the overall performance or power consumption of the
> ? ? ? ? ?processor.
>
> +config PL310_ERRATA_727915
> + ? ? ? bool "Background Clean & Invalidate by Way operation can cause data corruption"
> + ? ? ? depends on CACHE_L2X0 && ARCH_OMAP4
> + ? ? ? help
> + ? ? ? ? PL310 implements the Clean & Invalidate by Way L2 cache maintenance
> + ? ? ? ? operation (offset 0x7FC). This operation runs in background so that
> + ? ? ? ? PL310 can handle normal accesses while it is in progress. Under very
> + ? ? ? ? rare circumstances, due to this erratum, write data can be lost when
> + ? ? ? ? PL310 treats a cacheable write transaction during a Clean &
> + ? ? ? ? Invalidate by Way operation Note that this errata uses Texas
> + ? ? ? ? Instrument's secure monitor api to implement the work around.
> ?endmenu
>
> ?source "arch/arm/common/Kconfig"
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index f285dd7..1f0ff75 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -46,6 +46,7 @@ config ARCH_OMAP4
> ? ? ? ?select ARM_GIC
> ? ? ? ?select LOCAL_TIMERS
> ? ? ? ?select PL310_ERRATA_588369
> + ? ? ? select PL310_ERRATA_727915
> ? ? ? ?select ARM_ERRATA_720789
> ? ? ? ?select ARCH_HAS_OPP
> ? ? ? ?select PM_OPP if PM
> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> index 170c9bb..c7c8fbe 100644
> --- a/arch/arm/mm/cache-l2x0.c
> +++ b/arch/arm/mm/cache-l2x0.c
> @@ -67,7 +67,7 @@ static inline void l2x0_inv_line(unsigned long addr)
> ? ? ? ?writel_relaxed(addr, base + L2X0_INV_LINE_PA);
> ?}
>
> -#ifdef CONFIG_PL310_ERRATA_588369
> +#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
> ?static void debug_writel(unsigned long val)
> ?{
> ? ? ? ?extern void omap_smc1(u32 fn, u32 arg);
> @@ -78,7 +78,14 @@ static void debug_writel(unsigned long val)
> ? ? ? ? */
> ? ? ? ?omap_smc1(0x100, val);
> ?}
> +#else
> +/* Optimised out for non-errata case */
> +static inline void debug_writel(unsigned long val)
> +{
> +}
> +#endif
>
> +#ifdef CONFIG_PL310_ERRATA_588369
> ?static inline void l2x0_flush_line(unsigned long addr)
> ?{
> ? ? ? ?void __iomem *base = l2x0_base;
> @@ -91,11 +98,6 @@ static inline void l2x0_flush_line(unsigned long addr)
> ?}
> ?#else
>
> -/* Optimised out for non-errata case */
> -static inline void debug_writel(unsigned long val)
> -{
> -}
> -
> ?static inline void l2x0_flush_line(unsigned long addr)
> ?{
> ? ? ? ?void __iomem *base = l2x0_base;
> @@ -119,9 +121,11 @@ static void l2x0_flush_all(void)
>
> ? ? ? ?/* clean all ways */
> ? ? ? ?spin_lock_irqsave(&l2x0_lock, flags);
> + ? ? ? debug_writel(0x03);
> ? ? ? ?writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
> ? ? ? ?cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
> ? ? ? ?cache_sync();
> + ? ? ? debug_writel(0x00);
> ? ? ? ?spin_unlock_irqrestore(&l2x0_lock, flags);
> ?}
>
> --
> 1.6.0.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>

Can these PL310 errata fixes be made more generic? PL310 is present in
non-OMAP platforms too, which lack the TI hypervisor. And these
platforms might have the same PL310 rev, and suffer the same glitches.
While ideally there is some kind of hypervisor_ops to modify the
protected register, at the very least there should be the generic
debug_write handling the  "I  can write all PL310 regs" case. If
you're interested I have a patch someplace that tried to do this,
hopefully I can still find it.

RE: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Santosh Shilimkar]

> -----Original Message-----
> From: Andrei Warkentin [mailto:andreiw@motorola.com]
> Sent: Saturday, February 12, 2011 11:20 PM
> To: Santosh Shilimkar
> Cc: linux-omap@vger.kernel.org; khilman@ti.com; tony@atomide.com;
> linux-arm-kernel@lists.infradead.org; Catalin Marinas
> Subject: Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
> operation can cause data corruption
>
[....]

>
> Can these PL310 errata fixes be made more generic? PL310 is present
> in
> non-OMAP platforms too, which lack the TI hypervisor. And these
> platforms might have the same PL310 rev, and suffer the same
> glitches.
> While ideally there is some kind of hypervisor_ops to modify the
> protected register, at the very least there should be the generic
> debug_write handling the  "I  can write all PL310 regs" case. If
> you're interested I have a patch someplace that tried to do this,
> hopefully I can still find it.

They are kind of generic. If you look at it, the only change
Which is arch specific is the implementation of "debug_writel" function.
Today this code is not in generic PL310 code, but
OMAP specific.

May be we can make this as exported function pointer, which
arch's can populate.

Will that work for you ?

Regards,
Santosh

[PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Santosh Shilimkar]

> -----Original Message-----
> From: Andrei Warkentin [mailto:andreiw at motorola.com]
> Sent: Saturday, February 12, 2011 11:20 PM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; tony at atomide.com;
> linux-arm-kernel at lists.infradead.org; Catalin Marinas
> Subject: Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
> operation can cause data corruption
>
[....]

>
> Can these PL310 errata fixes be made more generic? PL310 is present
> in
> non-OMAP platforms too, which lack the TI hypervisor. And these
> platforms might have the same PL310 rev, and suffer the same
> glitches.
> While ideally there is some kind of hypervisor_ops to modify the
> protected register, at the very least there should be the generic
> debug_write handling the  "I  can write all PL310 regs" case. If
> you're interested I have a patch someplace that tried to do this,
> hopefully I can still find it.

They are kind of generic. If you look at it, the only change
Which is arch specific is the implementation of "debug_writel" function.
Today this code is not in generic PL310 code, but
OMAP specific.

May be we can make this as exported function pointer, which
arch's can populate.

Will that work for you ?

Regards,
Santosh

Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Andrei Warkentin]

On Sat, Feb 12, 2011 at 11:59 AM, Santosh Shilimkar
<santosh.shilimkar@ti.com> wrote:
>> -----Original Message-----
>> From: Andrei Warkentin [mailto:andreiw@motorola.com]
>> Sent: Saturday, February 12, 2011 11:20 PM
>> To: Santosh Shilimkar
>> Cc: linux-omap@vger.kernel.org; khilman@ti.com; tony@atomide.com;
>> linux-arm-kernel@lists.infradead.org; Catalin Marinas
>> Subject: Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
>> operation can cause data corruption
>>
> [....]
>
>>
>> Can these PL310 errata fixes be made more generic? PL310 is present
>> in
>> non-OMAP platforms too, which lack the TI hypervisor. And these
>> platforms might have the same PL310 rev, and suffer the same
>> glitches.
>> While ideally there is some kind of hypervisor_ops to modify the
>> protected register, at the very least there should be the generic
>> debug_write handling the  "I  can write all PL310 regs" case. If
>> you're interested I have a patch someplace that tried to do this,
>> hopefully I can still find it.
>
> They are kind of generic. If you look at it, the only change
> Which is arch specific is the implementation of "debug_writel" function.
> Today this code is not in generic PL310 code, but
> OMAP specific.
>
> May be we can make this as exported function pointer, which
> arch's can populate.
>
> Will that work for you ?
>
> Regards,
> Santosh
>

Ie something like the following.... what do you think???

#define L2X0_DCR (0xF40)

static void debug_writel(unsigned long val)
{
#ifdef CONFIG_ARCH_OMAP4
       omap_smc1(0x100, val);
#else
       writel_relaxed(val, l2x0_base + L2X0_DCR);
#endif
}
...
...

       /* clean all ways */
       spin_lock_irqsave(&l2x0_lock, flags);
#ifdef CONFIG_PL310_ERRATA_727915
       debug_writel(DCR_DWB | DCR_DCL); <---- not 0x3, but self-documenting
#endif
       writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
       cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
       cache_sync();
#ifdef CONFIG_PL310_ERRATA_727915
       debug_writel(0x00);
#endif
       spin_unlock_irqrestore(&l2x0_lock, flags);
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[PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Andrei Warkentin]

On Sat, Feb 12, 2011 at 11:59 AM, Santosh Shilimkar
<santosh.shilimkar@ti.com> wrote:
>> -----Original Message-----
>> From: Andrei Warkentin [mailto:andreiw at motorola.com]
>> Sent: Saturday, February 12, 2011 11:20 PM
>> To: Santosh Shilimkar
>> Cc: linux-omap at vger.kernel.org; khilman at ti.com; tony at atomide.com;
>> linux-arm-kernel at lists.infradead.org; Catalin Marinas
>> Subject: Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
>> operation can cause data corruption
>>
> [....]
>
>>
>> Can these PL310 errata fixes be made more generic? PL310 is present
>> in
>> non-OMAP platforms too, which lack the TI hypervisor. And these
>> platforms might have the same PL310 rev, and suffer the same
>> glitches.
>> While ideally there is some kind of hypervisor_ops to modify the
>> protected register, at the very least there should be the generic
>> debug_write handling the ?"I ?can write all PL310 regs" case. If
>> you're interested I have a patch someplace that tried to do this,
>> hopefully I can still find it.
>
> They are kind of generic. If you look at it, the only change
> Which is arch specific is the implementation of "debug_writel" function.
> Today this code is not in generic PL310 code, but
> OMAP specific.
>
> May be we can make this as exported function pointer, which
> arch's can populate.
>
> Will that work for you ?
>
> Regards,
> Santosh
>

Ie something like the following.... what do you think???

#define L2X0_DCR (0xF40)

static void debug_writel(unsigned long val)
{
#ifdef CONFIG_ARCH_OMAP4
       omap_smc1(0x100, val);
#else
       writel_relaxed(val, l2x0_base + L2X0_DCR);
#endif
}
...
...

       /* clean all ways */
       spin_lock_irqsave(&l2x0_lock, flags);
#ifdef CONFIG_PL310_ERRATA_727915
       debug_writel(DCR_DWB | DCR_DCL); <---- not 0x3, but self-documenting
#endif
       writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
       cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
       cache_sync();
#ifdef CONFIG_PL310_ERRATA_727915
       debug_writel(0x00);
#endif
       spin_unlock_irqrestore(&l2x0_lock, flags);

RE: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Santosh Shilimkar]

> -----Original Message-----
> From: Andrei Warkentin [mailto:andreiw@motorola.com]
> Sent: Sunday, February 13, 2011 4:48 AM
> To: Santosh Shilimkar
> Cc: linux-omap@vger.kernel.org; Kevin Hilman; tony@atomide.com;
> linux-arm-kernel@lists.infradead.org; Catalin Marinas
> Subject: Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
> operation can cause data corruption
>
> On Sat, Feb 12, 2011 at 11:59 AM, Santosh Shilimkar
> <santosh.shilimkar@ti.com> wrote:
> >> -----Original Message-----
> >> From: Andrei Warkentin [mailto:andreiw@motorola.com]
> >> Sent: Saturday, February 12, 2011 11:20 PM
> >> To: Santosh Shilimkar
> >> Cc: linux-omap@vger.kernel.org; khilman@ti.com; tony@atomide.com;
> >> linux-arm-kernel@lists.infradead.org; Catalin Marinas
> >> Subject: Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
> >> operation can cause data corruption
> >>
> > [....]
> >
> >>
> >> Can these PL310 errata fixes be made more generic? PL310 is
> present
> >> in
> >> non-OMAP platforms too, which lack the TI hypervisor. And these
> >> platforms might have the same PL310 rev, and suffer the same
> >> glitches.
> >> While ideally there is some kind of hypervisor_ops to modify the
> >> protected register, at the very least there should be the generic
> >> debug_write handling the  "I  can write all PL310 regs" case. If
> >> you're interested I have a patch someplace that tried to do this,
> >> hopefully I can still find it.
> >
> > They are kind of generic. If you look at it, the only change
> > Which is arch specific is the implementation of "debug_writel"
> function.
> > Today this code is not in generic PL310 code, but
> > OMAP specific.
> >
> > May be we can make this as exported function pointer, which
> > arch's can populate.
> >
> > Will that work for you ?
> >
> > Regards,
> > Santosh
> >
>
> Ie something like the following.... what do you think???
>
> #define L2X0_DCR (0xF40)
>
> static void debug_writel(unsigned long val)
> {
> #ifdef CONFIG_ARCH_OMAP4
>        omap_smc1(0x100, val);
> #else
>        writel_relaxed(val, l2x0_base + L2X0_DCR);
> #endif
> }
> ...
I understood that from first comment. But I am not in favor
of polluting common ARM files with SOC specific #ifdeffery.
We have gone over this when first errata support
was added for PL310

I have a better way to handle this scenario.
Expect an updated patch for this.

Regards,
Santosh
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[PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Santosh Shilimkar]

> -----Original Message-----
> From: Andrei Warkentin [mailto:andreiw at motorola.com]
> Sent: Sunday, February 13, 2011 4:48 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; Kevin Hilman; tony at atomide.com;
> linux-arm-kernel at lists.infradead.org; Catalin Marinas
> Subject: Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
> operation can cause data corruption
>
> On Sat, Feb 12, 2011 at 11:59 AM, Santosh Shilimkar
> <santosh.shilimkar@ti.com> wrote:
> >> -----Original Message-----
> >> From: Andrei Warkentin [mailto:andreiw at motorola.com]
> >> Sent: Saturday, February 12, 2011 11:20 PM
> >> To: Santosh Shilimkar
> >> Cc: linux-omap at vger.kernel.org; khilman at ti.com; tony at atomide.com;
> >> linux-arm-kernel at lists.infradead.org; Catalin Marinas
> >> Subject: Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
> >> operation can cause data corruption
> >>
> > [....]
> >
> >>
> >> Can these PL310 errata fixes be made more generic? PL310 is
> present
> >> in
> >> non-OMAP platforms too, which lack the TI hypervisor. And these
> >> platforms might have the same PL310 rev, and suffer the same
> >> glitches.
> >> While ideally there is some kind of hypervisor_ops to modify the
> >> protected register, at the very least there should be the generic
> >> debug_write handling the ?"I ?can write all PL310 regs" case. If
> >> you're interested I have a patch someplace that tried to do this,
> >> hopefully I can still find it.
> >
> > They are kind of generic. If you look at it, the only change
> > Which is arch specific is the implementation of "debug_writel"
> function.
> > Today this code is not in generic PL310 code, but
> > OMAP specific.
> >
> > May be we can make this as exported function pointer, which
> > arch's can populate.
> >
> > Will that work for you ?
> >
> > Regards,
> > Santosh
> >
>
> Ie something like the following.... what do you think???
>
> #define L2X0_DCR (0xF40)
>
> static void debug_writel(unsigned long val)
> {
> #ifdef CONFIG_ARCH_OMAP4
>        omap_smc1(0x100, val);
> #else
>        writel_relaxed(val, l2x0_base + L2X0_DCR);
> #endif
> }
> ...
I understood that from first comment. But I am not in favor
of polluting common ARM files with SOC specific #ifdeffery.
We have gone over this when first errata support
was added for PL310

I have a better way to handle this scenario.
Expect an updated patch for this.

Regards,
Santosh

Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Andrei Warkentin]

On Sun, Feb 13, 2011 at 11:08 PM, Santosh Shilimkar
<santosh.shilimkar@ti.com> wrote:
>> -----Original Message-----
>> From: Andrei Warkentin [mailto:andreiw@motorola.com]
>> Sent: Sunday, February 13, 2011 4:48 AM
>> To: Santosh Shilimkar
>> Cc: linux-omap@vger.kernel.org; Kevin Hilman; tony@atomide.com;
>> linux-arm-kernel@lists.infradead.org; Catalin Marinas
>> Subject: Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
>> operation can cause data corruption
>>
>> On Sat, Feb 12, 2011 at 11:59 AM, Santosh Shilimkar
>> <santosh.shilimkar@ti.com> wrote:
>> >> -----Original Message-----
>> >> From: Andrei Warkentin [mailto:andreiw@motorola.com]
>> >> Sent: Saturday, February 12, 2011 11:20 PM
>> >> To: Santosh Shilimkar
>> >> Cc: linux-omap@vger.kernel.org; khilman@ti.com; tony@atomide.com;
>> >> linux-arm-kernel@lists.infradead.org; Catalin Marinas
>> >> Subject: Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
>> >> operation can cause data corruption
>> >>
>> > [....]
>> >
>> >>
>> >> Can these PL310 errata fixes be made more generic? PL310 is
>> present
>> >> in
>> >> non-OMAP platforms too, which lack the TI hypervisor. And these
>> >> platforms might have the same PL310 rev, and suffer the same
>> >> glitches.
>> >> While ideally there is some kind of hypervisor_ops to modify the
>> >> protected register, at the very least there should be the generic
>> >> debug_write handling the  "I  can write all PL310 regs" case. If
>> >> you're interested I have a patch someplace that tried to do this,
>> >> hopefully I can still find it.
>> >
>> > They are kind of generic. If you look at it, the only change
>> > Which is arch specific is the implementation of "debug_writel"
>> function.
>> > Today this code is not in generic PL310 code, but
>> > OMAP specific.
>> >
>> > May be we can make this as exported function pointer, which
>> > arch's can populate.
>> >
>> > Will that work for you ?
>> >
>> > Regards,
>> > Santosh
>> >
>>
>> Ie something like the following.... what do you think???
>>
>> #define L2X0_DCR (0xF40)
>>
>> static void debug_writel(unsigned long val)
>> {
>> #ifdef CONFIG_ARCH_OMAP4
>>        omap_smc1(0x100, val);
>> #else
>>        writel_relaxed(val, l2x0_base + L2X0_DCR);
>> #endif
>> }
>> ...
> I understood that from first comment. But I am not in favor
> of polluting common ARM files with SOC specific #ifdeffery.
> We have gone over this when first errata support
> was added for PL310
>
> I have a better way to handle this scenario.
> Expect an updated patch for this.
>
> Regards,
> Santosh
>

Fair enough, but you're doing it right now :-). I believe the smarter
approach would be to start abstracting all accesses to secure-only
resources (like the DCR reg). This would be your "hypervisor"
interface. Then provide an implementation for your TI secure monitor.
Obviously over time :).
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[PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Andrei Warkentin]

On Sun, Feb 13, 2011 at 11:08 PM, Santosh Shilimkar
<santosh.shilimkar@ti.com> wrote:
>> -----Original Message-----
>> From: Andrei Warkentin [mailto:andreiw at motorola.com]
>> Sent: Sunday, February 13, 2011 4:48 AM
>> To: Santosh Shilimkar
>> Cc: linux-omap at vger.kernel.org; Kevin Hilman; tony at atomide.com;
>> linux-arm-kernel at lists.infradead.org; Catalin Marinas
>> Subject: Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
>> operation can cause data corruption
>>
>> On Sat, Feb 12, 2011 at 11:59 AM, Santosh Shilimkar
>> <santosh.shilimkar@ti.com> wrote:
>> >> -----Original Message-----
>> >> From: Andrei Warkentin [mailto:andreiw at motorola.com]
>> >> Sent: Saturday, February 12, 2011 11:20 PM
>> >> To: Santosh Shilimkar
>> >> Cc: linux-omap at vger.kernel.org; khilman at ti.com; tony at atomide.com;
>> >> linux-arm-kernel at lists.infradead.org; Catalin Marinas
>> >> Subject: Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
>> >> operation can cause data corruption
>> >>
>> > [....]
>> >
>> >>
>> >> Can these PL310 errata fixes be made more generic? PL310 is
>> present
>> >> in
>> >> non-OMAP platforms too, which lack the TI hypervisor. And these
>> >> platforms might have the same PL310 rev, and suffer the same
>> >> glitches.
>> >> While ideally there is some kind of hypervisor_ops to modify the
>> >> protected register, at the very least there should be the generic
>> >> debug_write handling the ?"I ?can write all PL310 regs" case. If
>> >> you're interested I have a patch someplace that tried to do this,
>> >> hopefully I can still find it.
>> >
>> > They are kind of generic. If you look at it, the only change
>> > Which is arch specific is the implementation of "debug_writel"
>> function.
>> > Today this code is not in generic PL310 code, but
>> > OMAP specific.
>> >
>> > May be we can make this as exported function pointer, which
>> > arch's can populate.
>> >
>> > Will that work for you ?
>> >
>> > Regards,
>> > Santosh
>> >
>>
>> Ie something like the following.... what do you think???
>>
>> #define L2X0_DCR (0xF40)
>>
>> static void debug_writel(unsigned long val)
>> {
>> #ifdef CONFIG_ARCH_OMAP4
>> ? ? ? ?omap_smc1(0x100, val);
>> #else
>> ? ? ? ?writel_relaxed(val, l2x0_base + L2X0_DCR);
>> #endif
>> }
>> ...
> I understood that from first comment. But I am not in favor
> of polluting common ARM files with SOC specific #ifdeffery.
> We have gone over this when first errata support
> was added for PL310
>
> I have a better way to handle this scenario.
> Expect an updated patch for this.
>
> Regards,
> Santosh
>

Fair enough, but you're doing it right now :-). I believe the smarter
approach would be to start abstracting all accesses to secure-only
resources (like the DCR reg). This would be your "hypervisor"
interface. Then provide an implementation for your TI secure monitor.
Obviously over time :).

Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Andrei Warkentin]

[-- Attachment #1: Type: text/plain, Size: 756 bytes --]

On Mon, Feb 14, 2011 at 1:33 PM, Andrei Warkentin <andreiw@motorola.com> wrote:
>
> Fair enough, but you're doing it right now :-). I believe the smarter
> approach would be to start abstracting all accesses to secure-only
> resources (like the DCR reg). This would be your "hypervisor"
> interface. Then provide an implementation for your TI secure monitor.
> Obviously over time :).
>

Santosh,

Maybe this can influence you in some ways. I have this old patch
sitting around, although it does #ifdef around the TI stuff, simply
because I wasn't really interested in moving it out.
I group the errata by revs so it's simpler to see what you need and
what you don't. Obviously there aren't that many, but it does provide
a pattern to follow...

Thanks,
A

[-- Attachment #2: 0001-ARM-PL310-Cleanup-errata-handling-for-cache-controll.patch --]
[-- Type: text/x-diff, Size: 9799 bytes --]

From be41c69f48d5886c76148c2ad378dae78e590534 Mon Sep 17 00:00:00 2001
From: Andrei Warkentin <andreiw@motorola.com>
Date: Mon, 14 Feb 2011 15:34:06 -0600
Subject: [PATCH] ARM PL310: Cleanup errata handling for cache controller.

Adds a revision option for PL310 cache controller. All errata
now depend on the revision selected. Picking a particular revision
results in selecting all required errata. CACHE_PL310_REV_UNKNOWN
is used when manual control is desired.

Signed-off-by: Andrei Warkentin <andreiw@motorola.com>

Change-Id: I8804af5d7a476737ce259b5d6a2a132c50082d66
---
 arch/arm/Kconfig                        |   36 ++++++++++++-------
 arch/arm/configs/omap_4430sdp_defconfig |    5 ++-
 arch/arm/mm/Kconfig                     |   52 +++++++++++++++++++++++++++
 arch/arm/mm/cache-l2x0.c                |   58 +++++++++++++++++++++++-------
 4 files changed, 122 insertions(+), 29 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cd2c427..20af15f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1014,6 +1014,28 @@ if !MMU
 source "arch/arm/Kconfig-nommu"
 endif
 
+config ARM_TRUSTZONE_UNSECURE
+       bool "TrustZone: Support for running in an unsecure domain"
+       depends on CPU_V6 || CPU_V7
+       help
+         This enables TZ-specific behaviors with respect to modifying state
+	 that is secure-only in a TrustZone system. You will need to select
+	 a specific Hypervisor/Secure Monitor.
+
+choice
+       prompt "TrustZone Hypervisor/Secure Monitor"
+       depends on ARM_TRUSTZONE_UNSECURE
+       default ARM_TRUSTZONE_UNSECURE_UNKNOWN
+       help
+         Pick the TrustZone Hypervisor/Secure Monitor, under which Linux
+	 will run in an unsecure domain.
+config ARM_TRUSTZONE_UNSECURE_UNKNOWN
+       bool "Unknown"
+config ARM_TRUSTZONE_UNSECURE_TI
+       bool "Texas Instruments Secure Monitor API"
+       depends on ARCH_OMAP4
+endchoice
+
 config ARM_ERRATA_411920
 	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
 	depends on CPU_V6 && !SMP
@@ -1090,20 +1112,6 @@ config ARM_ERRATA_742231
 	  register of the Cortex-A9 which reduces the linefill issuing
 	  capabilities of the processor.
 
-config PL310_ERRATA_588369
-	bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
-	depends on CACHE_L2X0 && ARCH_OMAP4
-	help
-	   The PL310 L2 cache controller implements three types of Clean &
-	   Invalidate maintenance operations: by Physical Address
-	   (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
-	   They are architecturally defined to behave as the execution of a
-	   clean operation followed immediately by an invalidate operation,
-	   both performing to the same memory location. This functionality
-	   is not correctly implemented in PL310 as clean lines are not
-	   invalidated as a result of these operations. Note that this errata
-	   uses Texas Instrument's secure monitor api.
-
 config ARM_ERRATA_720789
 	bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
 	depends on CPU_V7 && SMP
diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig
index 14c1e18..ac4091c 100644
--- a/arch/arm/configs/omap_4430sdp_defconfig
+++ b/arch/arm/configs/omap_4430sdp_defconfig
@@ -13,6 +13,8 @@ CONFIG_MODULE_SRCVERSION_ALL=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_OMAP=y
 CONFIG_ARCH_OMAP4=y
+CONFIG_ARM_TRUSTZONE_UNSECURE=y
+CONFIG_ARM_TRUSTZONE_UNSECURE_TI=y
 # CONFIG_ARCH_OMAP2PLUS_TYPICAL is not set
 # CONFIG_ARCH_OMAP2 is not set
 # CONFIG_ARCH_OMAP3 is not set
@@ -21,7 +23,8 @@ CONFIG_OMAP_32K_TIMER=y
 CONFIG_OMAP_DM_TIMER=y
 CONFIG_MACH_OMAP_4430SDP=y
 # CONFIG_ARM_THUMB is not set
-CONFIG_PL310_ERRATA_588369=y
+CONFIG_CACHE_PL310_REV_UNKNOWN=y
+CONFIG_CACHE_PL310_ERRATA_588369=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=2
 # CONFIG_LOCAL_TIMERS is not set
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index cc6f9d6..057fa76 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -786,6 +786,58 @@ config CACHE_PL310
 	help
 	  This option enables support for the PL310 cache controller.
 
+choice
+	prompt "PL310 revision"
+	depends on CACHE_PL310
+	default CACHE_PL310_REV_UNKNOWN
+	help
+	  This option selects the specific revision of the PL310 cache
+	  controller used. Picking a choice selects specific workarounds
+	  for that chip revision.
+config CACHE_PL310_REV_R0P0
+       bool "r0p0"
+       select CACHE_PL310_ERRATA_588369
+config CACHE_PL310_REV_R1P0
+       bool "r1p0"
+       select CACHE_PL310_ERRATA_588369
+config CACHE_PL310_REV_R2P0
+       bool "r2p0"
+       select CACHE_PL310_ERRATA_727915
+config CACHE_PL310_REV_R3P0
+       bool "r3p0"
+       select CACHE_PL310_ERRATA_727915
+config CACHE_PL310_REV_R3P1
+       bool "r3p1"
+config CACHE_PL310_REV_R3P1_50REL0
+       bool "r3p1-50rel0"
+config CACHE_PL310_REV_UNKNOWN
+       bool "Unknown revision"
+endchoice
+
+config CACHE_PL310_ERRATA_727915
+	bool "PL310 727915: Background Clean and Invalidate by Way operation can cause data corruption"
+	depends on CACHE_PL310_REV_UNKNOWN || CACHE_PL310_REV_R2P0 || CACHE_PL310_REV_R3P0
+	help
+	  PL310 implements the Clean & Invalidate by Way L2 cache maintenance
+	  operation (offset 0x7FC). This operation runs in background so that
+	  PL310 can handle normal accesses while it is in progress. Under very
+	  rare circumstances, due to this erratum, write data can be lost when
+	  PL310 treats a cacheable write transaction during a Clean & Invalidate
+	  by Way operation.
+
+config CACHE_PL310_ERRATA_588369
+	bool "PL310 588369: Clean & Invalidate maintenance operations do not invalidate clean lines"
+	depends on CACHE_PL310_REV_UNKNOWN || CACHE_PL310_REV_R0P0 || CACHE_PL310_REV_R1P0
+	help
+	   The PL310 L2 cache controller implements three types of Clean &
+	   Invalidate maintenance operations: by Physical Address
+	   (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
+	   They are architecturally defined to behave as the execution of a
+	   clean operation followed immediately by an invalidate operation,
+	   both performing to the same memory location. This functionality
+	   is not correctly implemented in PL310 as clean lines are not
+	   invalidated as a result of these operations.
+
 config CACHE_TAUROS2
 	bool "Enable the Tauros2 L2 cache controller"
 	depends on (ARCH_DOVE || ARCH_MMP)
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 9abfa5d..f4237c5 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -85,8 +85,13 @@ static inline void l2x0_inv_line(unsigned long addr)
 	writel_relaxed(addr, base + L2X0_INV_LINE_PA);
 }
 
-#ifdef CONFIG_PL310_ERRATA_588369
-static void debug_writel(unsigned long val)
+#ifdef CONFIG_ARM_TRUSTZONE_UNSECURE
+/*
+ * PL310 Debug Control Register is accessible only from
+ * the secure domain.
+ */
+#ifdef CONFIG_ARM_TRUSTZONE_UNSECURE_TI
+static inline void debug_writel(unsigned long val)
 {
 	extern void omap_smc1(u32 fn, u32 arg);
 
@@ -96,31 +101,33 @@ static void debug_writel(unsigned long val)
 	 */
 	omap_smc1(0x100, val);
 }
+#else
+#error Unsupported TrustZone Hypervisor/Secure Monitor
+#endif
+#else
+/*
+ * No TrustZone or we're in the secure domain.
+ */
+static inline void debug_writel(unsigned long val)
+{
+	writel(val, l2x0_base + L2X0_DEBUG_CTRL);
+}
+#endif
 
 static inline void l2x0_flush_line(unsigned long addr)
 {
 	void __iomem *base = l2x0_base;
 
-	/* Clean by PA followed by Invalidate by PA */
+#ifdef CONFIG_CACHE_PL310_ERRATA_588369
 	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
 	writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
 	cache_wait(base + L2X0_INV_LINE_PA, 1);
 	writel_relaxed(addr, base + L2X0_INV_LINE_PA);
-}
 #else
-
-/* Optimised out for non-errata case */
-static inline void debug_writel(unsigned long val)
-{
-}
-
-static inline void l2x0_flush_line(unsigned long addr)
-{
-	void __iomem *base = l2x0_base;
 	cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
 	writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
-}
 #endif
+}
 
 static void l2x0_cache_sync(void)
 {
@@ -149,9 +156,20 @@ static inline void l2x0_flush_all(void)
 
 	/* flush all ways */
 	_l2x0_lock(&l2x0_lock, flags);
+#ifdef CONFIG_CACHE_PL310_ERRATA_727915
+	debug_writel(0x03);
+#endif
+
+	/*
+	  TODO: Doesn't errata 588369 imply that this
+	  has to be replaced by a CLEAN_WAY and INV_WAY as well?
+	*/
 	writel(0xff, l2x0_base + L2X0_CLEAN_INV_WAY);
 	cache_wait_always(l2x0_base + L2X0_CLEAN_INV_WAY, 0xff);
 	cache_sync();
+#ifdef CONFIG_CACHE_PL310_ERRATA_727915
+	debug_writel(0x0);
+#endif
 	_l2x0_unlock(&l2x0_lock, flags);
 }
 
@@ -163,17 +181,25 @@ static void l2x0_inv_range(unsigned long start, unsigned long end)
 	_l2x0_lock(&l2x0_lock, flags);
 	if (start & (CACHE_LINE_SIZE - 1)) {
 		start &= ~(CACHE_LINE_SIZE - 1);
+#ifdef CONFIG_CACHE_PL310_ERRATA_588369
 		debug_writel(0x03);
+#endif
 		l2x0_flush_line(start);
+#ifdef CONFIG_CACHE_PL310_ERRATA_588369
 		debug_writel(0x00);
+#endif
 		start += CACHE_LINE_SIZE;
 	}
 
 	if (end & (CACHE_LINE_SIZE - 1)) {
 		end &= ~(CACHE_LINE_SIZE - 1);
+#ifdef CONFIG_CACHE_PL310_ERRATA_588369
 		debug_writel(0x03);
+#endif
 		l2x0_flush_line(end);
+#ifdef CONFIG_CACHE_PL310_ERRATA_588369
 		debug_writel(0x00);
+#endif
 	}
 
 	while (start < end) {
@@ -229,12 +255,16 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
 	while (start < end) {
 		unsigned long blk_end = block_end(start, end);
 
+#ifdef CONFIG_CACHE_PL310_ERRATA_588369
 		debug_writel(0x03);
+#endif
 		while (start < blk_end) {
 			l2x0_flush_line(start);
 			start += CACHE_LINE_SIZE;
 		}
+#ifdef CONFIG_CACHE_PL310_ERRATA_588369
 		debug_writel(0x00);
+#endif
 
 		if (blk_end < end) {
 			_l2x0_unlock(&l2x0_lock, flags);
-- 
1.7.0.4

[PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Andrei Warkentin]

On Mon, Feb 14, 2011 at 1:33 PM, Andrei Warkentin <andreiw@motorola.com> wrote:
>
> Fair enough, but you're doing it right now :-). I believe the smarter
> approach would be to start abstracting all accesses to secure-only
> resources (like the DCR reg). This would be your "hypervisor"
> interface. Then provide an implementation for your TI secure monitor.
> Obviously over time :).
>

Santosh,

Maybe this can influence you in some ways. I have this old patch
sitting around, although it does #ifdef around the TI stuff, simply
because I wasn't really interested in moving it out.
I group the errata by revs so it's simpler to see what you need and
what you don't. Obviously there aren't that many, but it does provide
a pattern to follow...

Thanks,
A
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Re: [PATCH 2/5] omap4: Enable ARM local timers with OMAP4430 es1.0 exception

[Tony Lindgren]

* Santosh Shilimkar <santosh.shilimkar@ti.com> [110212 03:28]:
> On OMAP4430 ES1.0 the local timers are gated by security. Enable the
> CONFIG_LOCAL_TIMERS for omap2plus build and handle the OMAP4430 es1.0
> exception case.
> 
> This patch has dependency on the first patch in this series.
> 	ARM: smp: Select local timers vs dummy timer support runtime
> 
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>

Acked-by: Tony Lindgren <tony@atomide.com>

> ---
>  arch/arm/mach-omap2/Kconfig     |    1 +
>  arch/arm/mach-omap2/timer-mpu.c |    4 ++++
>  2 files changed, 5 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index 1a2cf62..f285dd7 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -44,6 +44,7 @@ config ARCH_OMAP4
>  	depends on ARCH_OMAP2PLUS
>  	select CPU_V7
>  	select ARM_GIC
> +	select LOCAL_TIMERS
>  	select PL310_ERRATA_588369
>  	select ARM_ERRATA_720789
>  	select ARCH_HAS_OPP
> diff --git a/arch/arm/mach-omap2/timer-mpu.c b/arch/arm/mach-omap2/timer-mpu.c
> index 09c73dc..31c0ac4 100644
> --- a/arch/arm/mach-omap2/timer-mpu.c
> +++ b/arch/arm/mach-omap2/timer-mpu.c
> @@ -28,6 +28,10 @@
>   */
>  int __cpuinit local_timer_setup(struct clock_event_device *evt)
>  {
> +	/* Local timers are not supprted on OMAP4430 ES1.0 */
> +	if (omap_rev() == OMAP4430_REV_ES1_0)
> +		return -ENXIO;
> +
>  	evt->irq = OMAP44XX_IRQ_LOCALTIMER;
>  	twd_timer_setup(evt);
>  	return 0;
> -- 
> 1.6.0.4
> 

[PATCH 2/5] omap4: Enable ARM local timers with OMAP4430 es1.0 exception

[Tony Lindgren]

* Santosh Shilimkar <santosh.shilimkar@ti.com> [110212 03:28]:
> On OMAP4430 ES1.0 the local timers are gated by security. Enable the
> CONFIG_LOCAL_TIMERS for omap2plus build and handle the OMAP4430 es1.0
> exception case.
> 
> This patch has dependency on the first patch in this series.
> 	ARM: smp: Select local timers vs dummy timer support runtime
> 
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>

Acked-by: Tony Lindgren <tony@atomide.com>

> ---
>  arch/arm/mach-omap2/Kconfig     |    1 +
>  arch/arm/mach-omap2/timer-mpu.c |    4 ++++
>  2 files changed, 5 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index 1a2cf62..f285dd7 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -44,6 +44,7 @@ config ARCH_OMAP4
>  	depends on ARCH_OMAP2PLUS
>  	select CPU_V7
>  	select ARM_GIC
> +	select LOCAL_TIMERS
>  	select PL310_ERRATA_588369
>  	select ARM_ERRATA_720789
>  	select ARCH_HAS_OPP
> diff --git a/arch/arm/mach-omap2/timer-mpu.c b/arch/arm/mach-omap2/timer-mpu.c
> index 09c73dc..31c0ac4 100644
> --- a/arch/arm/mach-omap2/timer-mpu.c
> +++ b/arch/arm/mach-omap2/timer-mpu.c
> @@ -28,6 +28,10 @@
>   */
>  int __cpuinit local_timer_setup(struct clock_event_device *evt)
>  {
> +	/* Local timers are not supprted on OMAP4430 ES1.0 */
> +	if (omap_rev() == OMAP4430_REV_ES1_0)
> +		return -ENXIO;
> +
>  	evt->irq = OMAP44XX_IRQ_LOCALTIMER;
>  	twd_timer_setup(evt);
>  	return 0;
> -- 
> 1.6.0.4
> 

Re: [PATCH 4/5] omap2plus: omap4: Set NR_CPU to 2 instead of default 4

[Tony Lindgren]

* Santosh Shilimkar <santosh.shilimkar@ti.com> [110212 03:28]:
> The omap2plus_defconfig picks default NR_CPU value as 4 which isn't
> correct for OMAP4430. Available CPUs are ony 2, so fix the same.

I'll queue this for the upcoming merge window.

Tony

[PATCH 4/5] omap2plus: omap4: Set NR_CPU to 2 instead of default 4

[Tony Lindgren]

* Santosh Shilimkar <santosh.shilimkar@ti.com> [110212 03:28]:
> The omap2plus_defconfig picks default NR_CPU value as 4 which isn't
> correct for OMAP4430. Available CPUs are ony 2, so fix the same.

I'll queue this for the upcoming merge window.

Tony

Re: [PATCH 5/5] omap4: Remove 'FIXME: omap44xx_sram_init not implemented'

[Tony Lindgren]

* Santosh Shilimkar <santosh.shilimkar@ti.com> [110212 03:28]:
> The omap44xx_sram_init() implements functionality to push some
> code on SRAM whenever the code can't be executed from external
> memory. The low power and DVFS code can be executed from
> external DDR itself thanks to OMAP4  memory controller hardware
> support. So on OMAP4, sram_push kind of functionality isn't needed.
> 
> Hence remove the FIXME warning added for implementing sram push
> feature on OMAP4.

Will take this one too.

Tony

[PATCH 5/5] omap4: Remove 'FIXME: omap44xx_sram_init not implemented'

[Tony Lindgren]

* Santosh Shilimkar <santosh.shilimkar@ti.com> [110212 03:28]:
> The omap44xx_sram_init() implements functionality to push some
> code on SRAM whenever the code can't be executed from external
> memory. The low power and DVFS code can be executed from
> external DDR itself thanks to OMAP4  memory controller hardware
> support. So on OMAP4, sram_push kind of functionality isn't needed.
> 
> Hence remove the FIXME warning added for implementing sram push
> feature on OMAP4.

Will take this one too.

Tony

Re: [PATCH 1/5] ARM: smp: Select local timers vs dummy timer support runtime

[David Brown]

On Sat, Feb 12 2011, Santosh Shilimkar wrote:

> The current code support of dummy timers in absence of local
> timer is compile time. This is an attempt to convert it to runtime
> so that on few SOC version if the local timers aren't supported
> kernel can switch to dummy timers. OMAP4430 ES1.0 does suffer from
> this limitation.
>
> This patch should not have any functional impact on affected
> files.
>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
>  arch/arm/mach-msm/timer.c           |    3 ++-

Acked-By: David Brown <davidb@codeaurora.org>

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH 1/5] ARM: smp: Select local timers vs dummy timer support runtime

[David Brown]

On Sat, Feb 12 2011, Santosh Shilimkar wrote:

> The current code support of dummy timers in absence of local
> timer is compile time. This is an attempt to convert it to runtime
> so that on few SOC version if the local timers aren't supported
> kernel can switch to dummy timers. OMAP4430 ES1.0 does suffer from
> this limitation.
>
> This patch should not have any functional impact on affected
> files.
>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
>  arch/arm/mach-msm/timer.c           |    3 ++-

Acked-By: David Brown <davidb@codeaurora.org>

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH 1/5] ARM: smp: Select local timers vs dummy timer support runtime

[David Brown]

Let's try this again from the correct email address...

On Sat, Feb 12 2011, Santosh Shilimkar wrote:

> The current code support of dummy timers in absence of local
> timer is compile time. This is an attempt to convert it to runtime
> so that on few SOC version if the local timers aren't supported
> kernel can switch to dummy timers. OMAP4430 ES1.0 does suffer from
> this limitation.
>
> This patch should not have any functional impact on affected
> files.
>
>  arch/arm/mach-msm/timer.c           |    3 ++-

Acked-by: David Brown <davidb@codeaurora.org>

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH 1/5] ARM: smp: Select local timers vs dummy timer support runtime

[David Brown]

Let's try this again from the correct email address...

On Sat, Feb 12 2011, Santosh Shilimkar wrote:

> The current code support of dummy timers in absence of local
> timer is compile time. This is an attempt to convert it to runtime
> so that on few SOC version if the local timers aren't supported
> kernel can switch to dummy timers. OMAP4430 ES1.0 does suffer from
> this limitation.
>
> This patch should not have any functional impact on affected
> files.
>
>  arch/arm/mach-msm/timer.c           |    3 ++-

Acked-by: David Brown <davidb@codeaurora.org>

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

RE: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Santosh Shilimkar]

[-- Attachment #1: Type: text/plain, Size: 6772 bytes --]

> -----Original Message-----
> From: Santosh Shilimkar [mailto:santosh.shilimkar@ti.com]
> Sent: Monday, February 14, 2011 10:39 AM
> To: Andrei Warkentin
> Cc: linux-omap@vger.kernel.org; Kevin Hilman; tony@atomide.com;
> linux-arm-kernel@lists.infradead.org; Catalin Marinas
> Subject: RE: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
> operation can cause data corruption
>

[....]

> > ...
> I understood that from first comment. But I am not in favor
> of polluting common ARM files with SOC specific #ifdeffery.
> We have gone over this when first errata support
> was added for PL310
>
> I have a better way to handle this scenario.
> Expect an updated patch for this.
>

Below is the updated version which should remove any
OMAP dependency on these errata's. Attached same.

----
From: Santosh Shilimkar <santosh.shilimkar@ti.com>
Date: Fri, 14 Jan 2011 14:16:04 +0530
Subject: [v2 PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation
can cause data corruption

PL310 implements the Clean & Invalidate by Way L2 cache maintenance
operation (offset 0x7FC). This operation runs in background so that
PL310 can handle normal accesses while it is in progress. Under very
rare circumstances, due to this erratum, write data can be lost when
PL310 treats a cacheable write transaction during a Clean & Invalidate
by Way operation.

Workaround:
Disable Write-Back and Cache Linefill (Debug Control Register)
Clean & Invalidate by Way (0x7FC)
Re-enable Write-Back and Cache Linefill (Debug Control Register)

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm/Kconfig                   |   13 ++++++++++++-
 arch/arm/include/asm/outercache.h  |    1 +
 arch/arm/mach-omap2/Kconfig        |    3 +++
 arch/arm/mach-omap2/omap4-common.c |    7 +++++++
 arch/arm/mm/cache-l2x0.c           |   28 +++++++++++++++-------------
 5 files changed, 38 insertions(+), 14 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5cff165..ebadd95 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1140,7 +1140,7 @@ config ARM_ERRATA_742231

 config PL310_ERRATA_588369
 	bool "Clean & Invalidate maintenance operations do not invalidate
clean lines"
-	depends on CACHE_L2X0 && ARCH_OMAP4
+	depends on CACHE_L2X0 && CACHE_PL310
 	help
 	   The PL310 L2 cache controller implements three types of Clean &
 	   Invalidate maintenance operations: by Physical Address
@@ -1177,6 +1177,17 @@ config ARM_ERRATA_743622
 	  visible impact on the overall performance or power consumption
of the
 	  processor.

+config PL310_ERRATA_727915
+	bool "Background Clean & Invalidate by Way operation can cause
data corruption"
+	depends on CACHE_L2X0 && CACHE_PL310
+	help
+	  PL310 implements the Clean & Invalidate by Way L2 cache
maintenance
+	  operation (offset 0x7FC). This operation runs in background so
that
+	  PL310 can handle normal accesses while it is in progress. Under
very
+	  rare circumstances, due to this erratum, write data can be lost
when
+	  PL310 treats a cacheable write transaction during a Clean &
+	  Invalidate by Way operation Note that this errata uses Texas
+	  Instrument's secure monitor api to implement the work around.
 endmenu

 source "arch/arm/common/Kconfig"
diff --git a/arch/arm/include/asm/outercache.h
b/arch/arm/include/asm/outercache.h
index fc19009..348d513 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -31,6 +31,7 @@ struct outer_cache_fns {
 #ifdef CONFIG_OUTER_CACHE_SYNC
 	void (*sync)(void);
 #endif
+	void (*set_debug)(unsigned long);
 };

 #ifdef CONFIG_OUTER_CACHE
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index f285dd7..fd11ab4 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -45,7 +45,10 @@ config ARCH_OMAP4
 	select CPU_V7
 	select ARM_GIC
 	select LOCAL_TIMERS
+	select CACHE_L2X0
+	select CACHE_PL310
 	select PL310_ERRATA_588369
+	select PL310_ERRATA_727915
 	select ARM_ERRATA_720789
 	select ARCH_HAS_OPP
 	select PM_OPP if PM
diff --git a/arch/arm/mach-omap2/omap4-common.c
b/arch/arm/mach-omap2/omap4-common.c
index 1926864..9ef8c29 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -52,6 +52,12 @@ static void omap4_l2x0_disable(void)
 	omap_smc1(0x102, 0x0);
 }

+static void omap4_l2x0_set_debug(unsigned long val)
+{
+	/* Program PL310 L2 Cache controller debug register */
+	omap_smc1(0x100, val);
+}
+
 static int __init omap_l2_cache_init(void)
 {
 	u32 aux_ctrl = 0;
@@ -99,6 +105,7 @@ static int __init omap_l2_cache_init(void)
 	 * specific one
 	*/
 	outer_cache.disable = omap4_l2x0_disable;
+	outer_cache.set_debug = omap4_l2x0_set_debug;

 	return 0;
 }
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 170c9bb..a8caee4 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -67,18 +67,22 @@ static inline void l2x0_inv_line(unsigned long addr)
 	writel_relaxed(addr, base + L2X0_INV_LINE_PA);
 }

-#ifdef CONFIG_PL310_ERRATA_588369
+#if defined(CONFIG_PL310_ERRATA_588369) ||
defined(CONFIG_PL310_ERRATA_727915)
 static void debug_writel(unsigned long val)
 {
-	extern void omap_smc1(u32 fn, u32 arg);
-
-	/*
-	 * Texas Instrument secure monitor api to modify the
-	 * PL310 Debug Control Register.
-	 */
-	omap_smc1(0x100, val);
+	if (outer_cache.set_debug)
+		outer_cache.set_debug(val);
+	else
+		writel(val, l2x0_base + L2X0_DEBUG_CTRL);
+}
+#else
+/* Optimised out for non-errata case */
+static inline void debug_writel(unsigned long val)
+{
 }
+#endif

+#ifdef CONFIG_PL310_ERRATA_588369
 static inline void l2x0_flush_line(unsigned long addr)
 {
 	void __iomem *base = l2x0_base;
@@ -91,11 +95,6 @@ static inline void l2x0_flush_line(unsigned long addr)
 }
 #else

-/* Optimised out for non-errata case */
-static inline void debug_writel(unsigned long val)
-{
-}
-
 static inline void l2x0_flush_line(unsigned long addr)
 {
 	void __iomem *base = l2x0_base;
@@ -119,9 +118,11 @@ static void l2x0_flush_all(void)

 	/* clean all ways */
 	spin_lock_irqsave(&l2x0_lock, flags);
+	debug_writel(0x03);
 	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
 	cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
 	cache_sync();
+	debug_writel(0x00);
 	spin_unlock_irqrestore(&l2x0_lock, flags);
 }

@@ -329,6 +330,7 @@ void __init l2x0_init(void __iomem *base, __u32
aux_val, __u32 aux_mask)
 	outer_cache.flush_all = l2x0_flush_all;
 	outer_cache.inv_all = l2x0_inv_all;
 	outer_cache.disable = l2x0_disable;
+	outer_cache.set_debug = NULL;

 	printk(KERN_INFO "%s cache controller enabled\n", type);
 	printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x,
Cache size: %d B\n",
-- 
1.6.0.4

[-- Attachment #2: 0003-ARM-l2x0-Errata-fix-for-flush-by-Way-operation-can.patch --]
[-- Type: application/octet-stream, Size: 6062 bytes --]

From 4063a3881e67197443cf447beada0e5265071828 Mon Sep 17 00:00:00 2001
From: Santosh Shilimkar <santosh.shilimkar@ti.com>
Date: Fri, 14 Jan 2011 14:16:04 +0530
Subject: [v2 PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

PL310 implements the Clean & Invalidate by Way L2 cache maintenance
operation (offset 0x7FC). This operation runs in background so that
PL310 can handle normal accesses while it is in progress. Under very
rare circumstances, due to this erratum, write data can be lost when
PL310 treats a cacheable write transaction during a Clean & Invalidate
by Way operation.

Workaround:
Disable Write-Back and Cache Linefill (Debug Control Register)
Clean & Invalidate by Way (0x7FC)
Re-enable Write-Back and Cache Linefill (Debug Control Register)

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm/Kconfig                   |   13 ++++++++++++-
 arch/arm/include/asm/outercache.h  |    1 +
 arch/arm/mach-omap2/Kconfig        |    3 +++
 arch/arm/mach-omap2/omap4-common.c |    7 +++++++
 arch/arm/mm/cache-l2x0.c           |   28 +++++++++++++++-------------
 5 files changed, 38 insertions(+), 14 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5cff165..ebadd95 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1140,7 +1140,7 @@ config ARM_ERRATA_742231
 
 config PL310_ERRATA_588369
 	bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
-	depends on CACHE_L2X0 && ARCH_OMAP4
+	depends on CACHE_L2X0 && CACHE_PL310
 	help
 	   The PL310 L2 cache controller implements three types of Clean &
 	   Invalidate maintenance operations: by Physical Address
@@ -1177,6 +1177,17 @@ config ARM_ERRATA_743622
 	  visible impact on the overall performance or power consumption of the
 	  processor.
 
+config PL310_ERRATA_727915
+	bool "Background Clean & Invalidate by Way operation can cause data corruption"
+	depends on CACHE_L2X0 && CACHE_PL310
+	help
+	  PL310 implements the Clean & Invalidate by Way L2 cache maintenance
+	  operation (offset 0x7FC). This operation runs in background so that
+	  PL310 can handle normal accesses while it is in progress. Under very
+	  rare circumstances, due to this erratum, write data can be lost when
+	  PL310 treats a cacheable write transaction during a Clean &
+	  Invalidate by Way operation Note that this errata uses Texas
+	  Instrument's secure monitor api to implement the work around.
 endmenu
 
 source "arch/arm/common/Kconfig"
diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h
index fc19009..348d513 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -31,6 +31,7 @@ struct outer_cache_fns {
 #ifdef CONFIG_OUTER_CACHE_SYNC
 	void (*sync)(void);
 #endif
+	void (*set_debug)(unsigned long);
 };
 
 #ifdef CONFIG_OUTER_CACHE
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index f285dd7..fd11ab4 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -45,7 +45,10 @@ config ARCH_OMAP4
 	select CPU_V7
 	select ARM_GIC
 	select LOCAL_TIMERS
+	select CACHE_L2X0
+	select CACHE_PL310
 	select PL310_ERRATA_588369
+	select PL310_ERRATA_727915
 	select ARM_ERRATA_720789
 	select ARCH_HAS_OPP
 	select PM_OPP if PM
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 1926864..9ef8c29 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -52,6 +52,12 @@ static void omap4_l2x0_disable(void)
 	omap_smc1(0x102, 0x0);
 }
 
+static void omap4_l2x0_set_debug(unsigned long val)
+{
+	/* Program PL310 L2 Cache controller debug register */
+	omap_smc1(0x100, val);
+}
+
 static int __init omap_l2_cache_init(void)
 {
 	u32 aux_ctrl = 0;
@@ -99,6 +105,7 @@ static int __init omap_l2_cache_init(void)
 	 * specific one
 	*/
 	outer_cache.disable = omap4_l2x0_disable;
+	outer_cache.set_debug = omap4_l2x0_set_debug;
 
 	return 0;
 }
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 170c9bb..a8caee4 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -67,18 +67,22 @@ static inline void l2x0_inv_line(unsigned long addr)
 	writel_relaxed(addr, base + L2X0_INV_LINE_PA);
 }
 
-#ifdef CONFIG_PL310_ERRATA_588369
+#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
 static void debug_writel(unsigned long val)
 {
-	extern void omap_smc1(u32 fn, u32 arg);
-
-	/*
-	 * Texas Instrument secure monitor api to modify the
-	 * PL310 Debug Control Register.
-	 */
-	omap_smc1(0x100, val);
+	if (outer_cache.set_debug)
+		outer_cache.set_debug(val);
+	else
+		writel(val, l2x0_base + L2X0_DEBUG_CTRL);
+}
+#else
+/* Optimised out for non-errata case */
+static inline void debug_writel(unsigned long val)
+{
 }
+#endif
 
+#ifdef CONFIG_PL310_ERRATA_588369
 static inline void l2x0_flush_line(unsigned long addr)
 {
 	void __iomem *base = l2x0_base;
@@ -91,11 +95,6 @@ static inline void l2x0_flush_line(unsigned long addr)
 }
 #else
 
-/* Optimised out for non-errata case */
-static inline void debug_writel(unsigned long val)
-{
-}
-
 static inline void l2x0_flush_line(unsigned long addr)
 {
 	void __iomem *base = l2x0_base;
@@ -119,9 +118,11 @@ static void l2x0_flush_all(void)
 
 	/* clean all ways */
 	spin_lock_irqsave(&l2x0_lock, flags);
+	debug_writel(0x03);
 	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
 	cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
 	cache_sync();
+	debug_writel(0x00);
 	spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
@@ -329,6 +330,7 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
 	outer_cache.flush_all = l2x0_flush_all;
 	outer_cache.inv_all = l2x0_inv_all;
 	outer_cache.disable = l2x0_disable;
+	outer_cache.set_debug = NULL;
 
 	printk(KERN_INFO "%s cache controller enabled\n", type);
 	printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
-- 
1.6.0.4

[PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Santosh Shilimkar]

> -----Original Message-----
> From: Santosh Shilimkar [mailto:santosh.shilimkar at ti.com]
> Sent: Monday, February 14, 2011 10:39 AM
> To: Andrei Warkentin
> Cc: linux-omap at vger.kernel.org; Kevin Hilman; tony at atomide.com;
> linux-arm-kernel at lists.infradead.org; Catalin Marinas
> Subject: RE: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
> operation can cause data corruption
>

[....]

> > ...
> I understood that from first comment. But I am not in favor
> of polluting common ARM files with SOC specific #ifdeffery.
> We have gone over this when first errata support
> was added for PL310
>
> I have a better way to handle this scenario.
> Expect an updated patch for this.
>

Below is the updated version which should remove any
OMAP dependency on these errata's. Attached same.

----
From: Santosh Shilimkar <santosh.shilimkar@ti.com>
Date: Fri, 14 Jan 2011 14:16:04 +0530
Subject: [v2 PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation
can cause data corruption

PL310 implements the Clean & Invalidate by Way L2 cache maintenance
operation (offset 0x7FC). This operation runs in background so that
PL310 can handle normal accesses while it is in progress. Under very
rare circumstances, due to this erratum, write data can be lost when
PL310 treats a cacheable write transaction during a Clean & Invalidate
by Way operation.

Workaround:
Disable Write-Back and Cache Linefill (Debug Control Register)
Clean & Invalidate by Way (0x7FC)
Re-enable Write-Back and Cache Linefill (Debug Control Register)

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm/Kconfig                   |   13 ++++++++++++-
 arch/arm/include/asm/outercache.h  |    1 +
 arch/arm/mach-omap2/Kconfig        |    3 +++
 arch/arm/mach-omap2/omap4-common.c |    7 +++++++
 arch/arm/mm/cache-l2x0.c           |   28 +++++++++++++++-------------
 5 files changed, 38 insertions(+), 14 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5cff165..ebadd95 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1140,7 +1140,7 @@ config ARM_ERRATA_742231

 config PL310_ERRATA_588369
 	bool "Clean & Invalidate maintenance operations do not invalidate
clean lines"
-	depends on CACHE_L2X0 && ARCH_OMAP4
+	depends on CACHE_L2X0 && CACHE_PL310
 	help
 	   The PL310 L2 cache controller implements three types of Clean &
 	   Invalidate maintenance operations: by Physical Address
@@ -1177,6 +1177,17 @@ config ARM_ERRATA_743622
 	  visible impact on the overall performance or power consumption
of the
 	  processor.

+config PL310_ERRATA_727915
+	bool "Background Clean & Invalidate by Way operation can cause
data corruption"
+	depends on CACHE_L2X0 && CACHE_PL310
+	help
+	  PL310 implements the Clean & Invalidate by Way L2 cache
maintenance
+	  operation (offset 0x7FC). This operation runs in background so
that
+	  PL310 can handle normal accesses while it is in progress. Under
very
+	  rare circumstances, due to this erratum, write data can be lost
when
+	  PL310 treats a cacheable write transaction during a Clean &
+	  Invalidate by Way operation Note that this errata uses Texas
+	  Instrument's secure monitor api to implement the work around.
 endmenu

 source "arch/arm/common/Kconfig"
diff --git a/arch/arm/include/asm/outercache.h
b/arch/arm/include/asm/outercache.h
index fc19009..348d513 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -31,6 +31,7 @@ struct outer_cache_fns {
 #ifdef CONFIG_OUTER_CACHE_SYNC
 	void (*sync)(void);
 #endif
+	void (*set_debug)(unsigned long);
 };

 #ifdef CONFIG_OUTER_CACHE
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index f285dd7..fd11ab4 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -45,7 +45,10 @@ config ARCH_OMAP4
 	select CPU_V7
 	select ARM_GIC
 	select LOCAL_TIMERS
+	select CACHE_L2X0
+	select CACHE_PL310
 	select PL310_ERRATA_588369
+	select PL310_ERRATA_727915
 	select ARM_ERRATA_720789
 	select ARCH_HAS_OPP
 	select PM_OPP if PM
diff --git a/arch/arm/mach-omap2/omap4-common.c
b/arch/arm/mach-omap2/omap4-common.c
index 1926864..9ef8c29 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -52,6 +52,12 @@ static void omap4_l2x0_disable(void)
 	omap_smc1(0x102, 0x0);
 }

+static void omap4_l2x0_set_debug(unsigned long val)
+{
+	/* Program PL310 L2 Cache controller debug register */
+	omap_smc1(0x100, val);
+}
+
 static int __init omap_l2_cache_init(void)
 {
 	u32 aux_ctrl = 0;
@@ -99,6 +105,7 @@ static int __init omap_l2_cache_init(void)
 	 * specific one
 	*/
 	outer_cache.disable = omap4_l2x0_disable;
+	outer_cache.set_debug = omap4_l2x0_set_debug;

 	return 0;
 }
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 170c9bb..a8caee4 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -67,18 +67,22 @@ static inline void l2x0_inv_line(unsigned long addr)
 	writel_relaxed(addr, base + L2X0_INV_LINE_PA);
 }

-#ifdef CONFIG_PL310_ERRATA_588369
+#if defined(CONFIG_PL310_ERRATA_588369) ||
defined(CONFIG_PL310_ERRATA_727915)
 static void debug_writel(unsigned long val)
 {
-	extern void omap_smc1(u32 fn, u32 arg);
-
-	/*
-	 * Texas Instrument secure monitor api to modify the
-	 * PL310 Debug Control Register.
-	 */
-	omap_smc1(0x100, val);
+	if (outer_cache.set_debug)
+		outer_cache.set_debug(val);
+	else
+		writel(val, l2x0_base + L2X0_DEBUG_CTRL);
+}
+#else
+/* Optimised out for non-errata case */
+static inline void debug_writel(unsigned long val)
+{
 }
+#endif

+#ifdef CONFIG_PL310_ERRATA_588369
 static inline void l2x0_flush_line(unsigned long addr)
 {
 	void __iomem *base = l2x0_base;
@@ -91,11 +95,6 @@ static inline void l2x0_flush_line(unsigned long addr)
 }
 #else

-/* Optimised out for non-errata case */
-static inline void debug_writel(unsigned long val)
-{
-}
-
 static inline void l2x0_flush_line(unsigned long addr)
 {
 	void __iomem *base = l2x0_base;
@@ -119,9 +118,11 @@ static void l2x0_flush_all(void)

 	/* clean all ways */
 	spin_lock_irqsave(&l2x0_lock, flags);
+	debug_writel(0x03);
 	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
 	cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
 	cache_sync();
+	debug_writel(0x00);
 	spin_unlock_irqrestore(&l2x0_lock, flags);
 }

@@ -329,6 +330,7 @@ void __init l2x0_init(void __iomem *base, __u32
aux_val, __u32 aux_mask)
 	outer_cache.flush_all = l2x0_flush_all;
 	outer_cache.inv_all = l2x0_inv_all;
 	outer_cache.disable = l2x0_disable;
+	outer_cache.set_debug = NULL;

 	printk(KERN_INFO "%s cache controller enabled\n", type);
 	printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x,
Cache size: %d B\n",
-- 
1.6.0.4
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Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Andrei Warkentin]

On Tue, Feb 15, 2011 at 1:14 AM, Santosh Shilimkar
<santosh.shilimkar@ti.com> wrote:
>> -----Original Message-----
>> From: Santosh Shilimkar [mailto:santosh.shilimkar@ti.com]
>> Sent: Monday, February 14, 2011 10:39 AM
>> To: Andrei Warkentin
>> Cc: linux-omap@vger.kernel.org; Kevin Hilman; tony@atomide.com;
>> linux-arm-kernel@lists.infradead.org; Catalin Marinas
>> Subject: RE: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
>> operation can cause data corruption
>>
>
> [....]
>
>> > ...
>> I understood that from first comment. But I am not in favor
>> of polluting common ARM files with SOC specific #ifdeffery.
>> We have gone over this when first errata support
>> was added for PL310
>>
>> I have a better way to handle this scenario.
>> Expect an updated patch for this.
>>
>
> Below is the updated version which should remove any
> OMAP dependency on these errata's. Attached same.
>
> ----
> From: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Date: Fri, 14 Jan 2011 14:16:04 +0530
> Subject: [v2 PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation
> can cause data corruption
>
> PL310 implements the Clean & Invalidate by Way L2 cache maintenance
> operation (offset 0x7FC). This operation runs in background so that
> PL310 can handle normal accesses while it is in progress. Under very
> rare circumstances, due to this erratum, write data can be lost when
> PL310 treats a cacheable write transaction during a Clean & Invalidate
> by Way operation.
>
> Workaround:
> Disable Write-Back and Cache Linefill (Debug Control Register)
> Clean & Invalidate by Way (0x7FC)
> Re-enable Write-Back and Cache Linefill (Debug Control Register)
>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> ---
>  arch/arm/Kconfig                   |   13 ++++++++++++-
>  arch/arm/include/asm/outercache.h  |    1 +
>  arch/arm/mach-omap2/Kconfig        |    3 +++
>  arch/arm/mach-omap2/omap4-common.c |    7 +++++++
>  arch/arm/mm/cache-l2x0.c           |   28 +++++++++++++++-------------
>  5 files changed, 38 insertions(+), 14 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 5cff165..ebadd95 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1140,7 +1140,7 @@ config ARM_ERRATA_742231
>
>  config PL310_ERRATA_588369
>        bool "Clean & Invalidate maintenance operations do not invalidate
> clean lines"
> -       depends on CACHE_L2X0 && ARCH_OMAP4
> +       depends on CACHE_L2X0 && CACHE_PL310
>        help
>           The PL310 L2 cache controller implements three types of Clean &
>           Invalidate maintenance operations: by Physical Address
> @@ -1177,6 +1177,17 @@ config ARM_ERRATA_743622
>          visible impact on the overall performance or power consumption
> of the
>          processor.
>
> +config PL310_ERRATA_727915
> +       bool "Background Clean & Invalidate by Way operation can cause
> data corruption"
> +       depends on CACHE_L2X0 && CACHE_PL310
> +       help
> +         PL310 implements the Clean & Invalidate by Way L2 cache
> maintenance
> +         operation (offset 0x7FC). This operation runs in background so
> that
> +         PL310 can handle normal accesses while it is in progress. Under
> very
> +         rare circumstances, due to this erratum, write data can be lost
> when
> +         PL310 treats a cacheable write transaction during a Clean &
> +         Invalidate by Way operation Note that this errata uses Texas
> +         Instrument's secure monitor api to implement the work around.
>  endmenu
>
>  source "arch/arm/common/Kconfig"
> diff --git a/arch/arm/include/asm/outercache.h
> b/arch/arm/include/asm/outercache.h
> index fc19009..348d513 100644
> --- a/arch/arm/include/asm/outercache.h
> +++ b/arch/arm/include/asm/outercache.h
> @@ -31,6 +31,7 @@ struct outer_cache_fns {
>  #ifdef CONFIG_OUTER_CACHE_SYNC
>        void (*sync)(void);
>  #endif
> +       void (*set_debug)(unsigned long);
>  };
>
>  #ifdef CONFIG_OUTER_CACHE
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index f285dd7..fd11ab4 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -45,7 +45,10 @@ config ARCH_OMAP4
>        select CPU_V7
>        select ARM_GIC
>        select LOCAL_TIMERS
> +       select CACHE_L2X0
> +       select CACHE_PL310
>        select PL310_ERRATA_588369
> +       select PL310_ERRATA_727915
>        select ARM_ERRATA_720789
>        select ARCH_HAS_OPP
>        select PM_OPP if PM
> diff --git a/arch/arm/mach-omap2/omap4-common.c
> b/arch/arm/mach-omap2/omap4-common.c
> index 1926864..9ef8c29 100644
> --- a/arch/arm/mach-omap2/omap4-common.c
> +++ b/arch/arm/mach-omap2/omap4-common.c
> @@ -52,6 +52,12 @@ static void omap4_l2x0_disable(void)
>        omap_smc1(0x102, 0x0);
>  }
>
> +static void omap4_l2x0_set_debug(unsigned long val)
> +{
> +       /* Program PL310 L2 Cache controller debug register */
> +       omap_smc1(0x100, val);
> +}
> +
>  static int __init omap_l2_cache_init(void)
>  {
>        u32 aux_ctrl = 0;
> @@ -99,6 +105,7 @@ static int __init omap_l2_cache_init(void)
>         * specific one
>        */
>        outer_cache.disable = omap4_l2x0_disable;
> +       outer_cache.set_debug = omap4_l2x0_set_debug;
>
>        return 0;
>  }
> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> index 170c9bb..a8caee4 100644
> --- a/arch/arm/mm/cache-l2x0.c
> +++ b/arch/arm/mm/cache-l2x0.c
> @@ -67,18 +67,22 @@ static inline void l2x0_inv_line(unsigned long addr)
>        writel_relaxed(addr, base + L2X0_INV_LINE_PA);
>  }
>
> -#ifdef CONFIG_PL310_ERRATA_588369
> +#if defined(CONFIG_PL310_ERRATA_588369) ||
> defined(CONFIG_PL310_ERRATA_727915)
>  static void debug_writel(unsigned long val)
>  {
> -       extern void omap_smc1(u32 fn, u32 arg);
> -
> -       /*
> -        * Texas Instrument secure monitor api to modify the
> -        * PL310 Debug Control Register.
> -        */
> -       omap_smc1(0x100, val);
> +       if (outer_cache.set_debug)
> +               outer_cache.set_debug(val);
> +       else
> +               writel(val, l2x0_base + L2X0_DEBUG_CTRL);
> +}
> +#else
> +/* Optimised out for non-errata case */
> +static inline void debug_writel(unsigned long val)
> +{
>  }
> +#endif
>
> +#ifdef CONFIG_PL310_ERRATA_588369
>  static inline void l2x0_flush_line(unsigned long addr)
>  {
>        void __iomem *base = l2x0_base;
> @@ -91,11 +95,6 @@ static inline void l2x0_flush_line(unsigned long addr)
>  }
>  #else
>
> -/* Optimised out for non-errata case */
> -static inline void debug_writel(unsigned long val)
> -{
> -}
> -
>  static inline void l2x0_flush_line(unsigned long addr)
>  {
>        void __iomem *base = l2x0_base;
> @@ -119,9 +118,11 @@ static void l2x0_flush_all(void)
>
>        /* clean all ways */
>        spin_lock_irqsave(&l2x0_lock, flags);
> +       debug_writel(0x03);
>        writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
>        cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
>        cache_sync();
> +       debug_writel(0x00);
>        spin_unlock_irqrestore(&l2x0_lock, flags);
>  }
>
> @@ -329,6 +330,7 @@ void __init l2x0_init(void __iomem *base, __u32
> aux_val, __u32 aux_mask)
>        outer_cache.flush_all = l2x0_flush_all;
>        outer_cache.inv_all = l2x0_inv_all;
>        outer_cache.disable = l2x0_disable;
> +       outer_cache.set_debug = NULL;
>
>        printk(KERN_INFO "%s cache controller enabled\n", type);
>        printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x,
> Cache size: %d B\n",
> --
> 1.6.0.4
>

Why set by default to NULL, why not have a normal l2x0_set_debug which
just does a write to L2X0_DEBUG_CTRL, and then just invoke the
function pointer when you wish to manipulate the DCR? That way you
don't need the runtime check, and it's just clearer, I think.

Also, why not do something like -
....
do_stuff();
#ifdef CONFIG_NEED_ERRATA_1234
do_errata_stuff();
#endif
do_more_stuff();
...

instead of  -

...
#ifdef CONFIG_NEED_ERRATA_1234
do_some_stuf() {
bar();
}
#else
{
do_some_stuff() {
}
// nothing
}

do_stuff();
do_some_stuff();
do_more_stuff();

It's not exactly clear otherwise what's happening and why there are
these extra calls that sometimes are compiled in, and sometimes
aren't. The way I am suggesting, you would just look at a function
block and you can easily tell what is different in the errata case,
and you don't need to jump back and forth to figure that out. I think
it makes for cleaner code.

And it would be nice if the errata had some revision data attached to
them, as in my suggestion patch I sent earlier. It's a nuisance to
look at Kconfig wondering which errata you might be interested in,
especially if your platform spans several generations and revs of
different parts. Then you need to dig up an errata sheet and scan it
yourself. The alternative is to be able to select a known rev for
PL310, for example, which would just pick the errata that apply to
that rev, or at least mention the affected revs in the documentation
for the option.
--
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[PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Andrei Warkentin]

On Tue, Feb 15, 2011 at 1:14 AM, Santosh Shilimkar
<santosh.shilimkar@ti.com> wrote:
>> -----Original Message-----
>> From: Santosh Shilimkar [mailto:santosh.shilimkar at ti.com]
>> Sent: Monday, February 14, 2011 10:39 AM
>> To: Andrei Warkentin
>> Cc: linux-omap at vger.kernel.org; Kevin Hilman; tony at atomide.com;
>> linux-arm-kernel at lists.infradead.org; Catalin Marinas
>> Subject: RE: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
>> operation can cause data corruption
>>
>
> [....]
>
>> > ...
>> I understood that from first comment. But I am not in favor
>> of polluting common ARM files with SOC specific #ifdeffery.
>> We have gone over this when first errata support
>> was added for PL310
>>
>> I have a better way to handle this scenario.
>> Expect an updated patch for this.
>>
>
> Below is the updated version which should remove any
> OMAP dependency on these errata's. Attached same.
>
> ----
> From: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Date: Fri, 14 Jan 2011 14:16:04 +0530
> Subject: [v2 PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation
> can cause data corruption
>
> PL310 implements the Clean & Invalidate by Way L2 cache maintenance
> operation (offset 0x7FC). This operation runs in background so that
> PL310 can handle normal accesses while it is in progress. Under very
> rare circumstances, due to this erratum, write data can be lost when
> PL310 treats a cacheable write transaction during a Clean & Invalidate
> by Way operation.
>
> Workaround:
> Disable Write-Back and Cache Linefill (Debug Control Register)
> Clean & Invalidate by Way (0x7FC)
> Re-enable Write-Back and Cache Linefill (Debug Control Register)
>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> ---
> ?arch/arm/Kconfig ? ? ? ? ? ? ? ? ? | ? 13 ++++++++++++-
> ?arch/arm/include/asm/outercache.h ?| ? ?1 +
> ?arch/arm/mach-omap2/Kconfig ? ? ? ?| ? ?3 +++
> ?arch/arm/mach-omap2/omap4-common.c | ? ?7 +++++++
> ?arch/arm/mm/cache-l2x0.c ? ? ? ? ? | ? 28 +++++++++++++++-------------
> ?5 files changed, 38 insertions(+), 14 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 5cff165..ebadd95 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1140,7 +1140,7 @@ config ARM_ERRATA_742231
>
> ?config PL310_ERRATA_588369
> ? ? ? ?bool "Clean & Invalidate maintenance operations do not invalidate
> clean lines"
> - ? ? ? depends on CACHE_L2X0 && ARCH_OMAP4
> + ? ? ? depends on CACHE_L2X0 && CACHE_PL310
> ? ? ? ?help
> ? ? ? ? ? The PL310 L2 cache controller implements three types of Clean &
> ? ? ? ? ? Invalidate maintenance operations: by Physical Address
> @@ -1177,6 +1177,17 @@ config ARM_ERRATA_743622
> ? ? ? ? ?visible impact on the overall performance or power consumption
> of the
> ? ? ? ? ?processor.
>
> +config PL310_ERRATA_727915
> + ? ? ? bool "Background Clean & Invalidate by Way operation can cause
> data corruption"
> + ? ? ? depends on CACHE_L2X0 && CACHE_PL310
> + ? ? ? help
> + ? ? ? ? PL310 implements the Clean & Invalidate by Way L2 cache
> maintenance
> + ? ? ? ? operation (offset 0x7FC). This operation runs in background so
> that
> + ? ? ? ? PL310 can handle normal accesses while it is in progress. Under
> very
> + ? ? ? ? rare circumstances, due to this erratum, write data can be lost
> when
> + ? ? ? ? PL310 treats a cacheable write transaction during a Clean &
> + ? ? ? ? Invalidate by Way operation Note that this errata uses Texas
> + ? ? ? ? Instrument's secure monitor api to implement the work around.
> ?endmenu
>
> ?source "arch/arm/common/Kconfig"
> diff --git a/arch/arm/include/asm/outercache.h
> b/arch/arm/include/asm/outercache.h
> index fc19009..348d513 100644
> --- a/arch/arm/include/asm/outercache.h
> +++ b/arch/arm/include/asm/outercache.h
> @@ -31,6 +31,7 @@ struct outer_cache_fns {
> ?#ifdef CONFIG_OUTER_CACHE_SYNC
> ? ? ? ?void (*sync)(void);
> ?#endif
> + ? ? ? void (*set_debug)(unsigned long);
> ?};
>
> ?#ifdef CONFIG_OUTER_CACHE
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index f285dd7..fd11ab4 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -45,7 +45,10 @@ config ARCH_OMAP4
> ? ? ? ?select CPU_V7
> ? ? ? ?select ARM_GIC
> ? ? ? ?select LOCAL_TIMERS
> + ? ? ? select CACHE_L2X0
> + ? ? ? select CACHE_PL310
> ? ? ? ?select PL310_ERRATA_588369
> + ? ? ? select PL310_ERRATA_727915
> ? ? ? ?select ARM_ERRATA_720789
> ? ? ? ?select ARCH_HAS_OPP
> ? ? ? ?select PM_OPP if PM
> diff --git a/arch/arm/mach-omap2/omap4-common.c
> b/arch/arm/mach-omap2/omap4-common.c
> index 1926864..9ef8c29 100644
> --- a/arch/arm/mach-omap2/omap4-common.c
> +++ b/arch/arm/mach-omap2/omap4-common.c
> @@ -52,6 +52,12 @@ static void omap4_l2x0_disable(void)
> ? ? ? ?omap_smc1(0x102, 0x0);
> ?}
>
> +static void omap4_l2x0_set_debug(unsigned long val)
> +{
> + ? ? ? /* Program PL310 L2 Cache controller debug register */
> + ? ? ? omap_smc1(0x100, val);
> +}
> +
> ?static int __init omap_l2_cache_init(void)
> ?{
> ? ? ? ?u32 aux_ctrl = 0;
> @@ -99,6 +105,7 @@ static int __init omap_l2_cache_init(void)
> ? ? ? ? * specific one
> ? ? ? ?*/
> ? ? ? ?outer_cache.disable = omap4_l2x0_disable;
> + ? ? ? outer_cache.set_debug = omap4_l2x0_set_debug;
>
> ? ? ? ?return 0;
> ?}
> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> index 170c9bb..a8caee4 100644
> --- a/arch/arm/mm/cache-l2x0.c
> +++ b/arch/arm/mm/cache-l2x0.c
> @@ -67,18 +67,22 @@ static inline void l2x0_inv_line(unsigned long addr)
> ? ? ? ?writel_relaxed(addr, base + L2X0_INV_LINE_PA);
> ?}
>
> -#ifdef CONFIG_PL310_ERRATA_588369
> +#if defined(CONFIG_PL310_ERRATA_588369) ||
> defined(CONFIG_PL310_ERRATA_727915)
> ?static void debug_writel(unsigned long val)
> ?{
> - ? ? ? extern void omap_smc1(u32 fn, u32 arg);
> -
> - ? ? ? /*
> - ? ? ? ?* Texas Instrument secure monitor api to modify the
> - ? ? ? ?* PL310 Debug Control Register.
> - ? ? ? ?*/
> - ? ? ? omap_smc1(0x100, val);
> + ? ? ? if (outer_cache.set_debug)
> + ? ? ? ? ? ? ? outer_cache.set_debug(val);
> + ? ? ? else
> + ? ? ? ? ? ? ? writel(val, l2x0_base + L2X0_DEBUG_CTRL);
> +}
> +#else
> +/* Optimised out for non-errata case */
> +static inline void debug_writel(unsigned long val)
> +{
> ?}
> +#endif
>
> +#ifdef CONFIG_PL310_ERRATA_588369
> ?static inline void l2x0_flush_line(unsigned long addr)
> ?{
> ? ? ? ?void __iomem *base = l2x0_base;
> @@ -91,11 +95,6 @@ static inline void l2x0_flush_line(unsigned long addr)
> ?}
> ?#else
>
> -/* Optimised out for non-errata case */
> -static inline void debug_writel(unsigned long val)
> -{
> -}
> -
> ?static inline void l2x0_flush_line(unsigned long addr)
> ?{
> ? ? ? ?void __iomem *base = l2x0_base;
> @@ -119,9 +118,11 @@ static void l2x0_flush_all(void)
>
> ? ? ? ?/* clean all ways */
> ? ? ? ?spin_lock_irqsave(&l2x0_lock, flags);
> + ? ? ? debug_writel(0x03);
> ? ? ? ?writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
> ? ? ? ?cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
> ? ? ? ?cache_sync();
> + ? ? ? debug_writel(0x00);
> ? ? ? ?spin_unlock_irqrestore(&l2x0_lock, flags);
> ?}
>
> @@ -329,6 +330,7 @@ void __init l2x0_init(void __iomem *base, __u32
> aux_val, __u32 aux_mask)
> ? ? ? ?outer_cache.flush_all = l2x0_flush_all;
> ? ? ? ?outer_cache.inv_all = l2x0_inv_all;
> ? ? ? ?outer_cache.disable = l2x0_disable;
> + ? ? ? outer_cache.set_debug = NULL;
>
> ? ? ? ?printk(KERN_INFO "%s cache controller enabled\n", type);
> ? ? ? ?printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x,
> Cache size: %d B\n",
> --
> 1.6.0.4
>

Why set by default to NULL, why not have a normal l2x0_set_debug which
just does a write to L2X0_DEBUG_CTRL, and then just invoke the
function pointer when you wish to manipulate the DCR? That way you
don't need the runtime check, and it's just clearer, I think.

Also, why not do something like -
....
do_stuff();
#ifdef CONFIG_NEED_ERRATA_1234
do_errata_stuff();
#endif
do_more_stuff();
...

instead of  -

...
#ifdef CONFIG_NEED_ERRATA_1234
do_some_stuf() {
bar();
}
#else
{
do_some_stuff() {
}
// nothing
}

do_stuff();
do_some_stuff();
do_more_stuff();

It's not exactly clear otherwise what's happening and why there are
these extra calls that sometimes are compiled in, and sometimes
aren't. The way I am suggesting, you would just look at a function
block and you can easily tell what is different in the errata case,
and you don't need to jump back and forth to figure that out. I think
it makes for cleaner code.

And it would be nice if the errata had some revision data attached to
them, as in my suggestion patch I sent earlier. It's a nuisance to
look at Kconfig wondering which errata you might be interested in,
especially if your platform spans several generations and revs of
different parts. Then you need to dig up an errata sheet and scan it
yourself. The alternative is to be able to select a known rev for
PL310, for example, which would just pick the errata that apply to
that rev, or at least mention the affected revs in the documentation
for the option.

RE: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Santosh Shilimkar]

> -----Original Message-----
> From: Andrei Warkentin [mailto:andreiw@motorola.com]
> Sent: Tuesday, February 15, 2011 2:40 PM
> To: Santosh Shilimkar
> Cc: linux-arm-kernel@lists.infradead.org; linux-
> omap@vger.kernel.org; Kevin Hilman; tony@atomide.com; Catalin
> Marinas
> Subject: Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
> operation can cause data corruption
>
> On Tue, Feb 15, 2011 at 1:14 AM, Santosh Shilimkar
> <santosh.shilimkar@ti.com> wrote:
> >> -----Original Message-----
> >> From: Santosh Shilimkar [mailto:santosh.shilimkar@ti.com]
> >> Sent: Monday, February 14, 2011 10:39 AM
> >> To: Andrei Warkentin
> >> Cc: linux-omap@vger.kernel.org; Kevin Hilman; tony@atomide.com;
> >> linux-arm-kernel@lists.infradead.org; Catalin Marinas
> >> Subject: RE: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
> >> operation can cause data corruption
> >>
> >

[....]

> >
>
> Why set by default to NULL, why not have a normal l2x0_set_debug
> which
> just does a write to L2X0_DEBUG_CTRL, and then just invoke the
> function pointer when you wish to manipulate the DCR? That way you
> don't need the runtime check, and it's just clearer, I think.
>
I though about it. There more changes in the file and hence I
avoided it. This can be done though.

> Also, why not do something like -
> ....
> do_stuff();
> #ifdef CONFIG_NEED_ERRATA_1234
> do_errata_stuff();
> #endif
> do_more_stuff();
> ...
>
Which makes code completely ugly.

> instead of  -
>
> ...
> #ifdef CONFIG_NEED_ERRATA_1234
> do_some_stuf() {
> bar();
> }
> #else
> {
> do_some_stuff() {
> }
> // nothing
> }
>
We have already discussed this. The code becomes ugly. If you
are interested in the reasoning, please check archives.

Russell and Catalin has suggested above.

If you understand the errata in first place, you could
understand the comment.

I let Catalin, Russell comment on it more, but unnecessary
CONFIG options and polluting every function with #If, else
checks don't make sense. Rest of your comments are related
to this.

Regards,
Santosh

[PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Santosh Shilimkar]

> -----Original Message-----
> From: Andrei Warkentin [mailto:andreiw at motorola.com]
> Sent: Tuesday, February 15, 2011 2:40 PM
> To: Santosh Shilimkar
> Cc: linux-arm-kernel at lists.infradead.org; linux-
> omap at vger.kernel.org; Kevin Hilman; tony at atomide.com; Catalin
> Marinas
> Subject: Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
> operation can cause data corruption
>
> On Tue, Feb 15, 2011 at 1:14 AM, Santosh Shilimkar
> <santosh.shilimkar@ti.com> wrote:
> >> -----Original Message-----
> >> From: Santosh Shilimkar [mailto:santosh.shilimkar at ti.com]
> >> Sent: Monday, February 14, 2011 10:39 AM
> >> To: Andrei Warkentin
> >> Cc: linux-omap at vger.kernel.org; Kevin Hilman; tony at atomide.com;
> >> linux-arm-kernel at lists.infradead.org; Catalin Marinas
> >> Subject: RE: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
> >> operation can cause data corruption
> >>
> >

[....]

> >
>
> Why set by default to NULL, why not have a normal l2x0_set_debug
> which
> just does a write to L2X0_DEBUG_CTRL, and then just invoke the
> function pointer when you wish to manipulate the DCR? That way you
> don't need the runtime check, and it's just clearer, I think.
>
I though about it. There more changes in the file and hence I
avoided it. This can be done though.

> Also, why not do something like -
> ....
> do_stuff();
> #ifdef CONFIG_NEED_ERRATA_1234
> do_errata_stuff();
> #endif
> do_more_stuff();
> ...
>
Which makes code completely ugly.

> instead of  -
>
> ...
> #ifdef CONFIG_NEED_ERRATA_1234
> do_some_stuf() {
> bar();
> }
> #else
> {
> do_some_stuff() {
> }
> // nothing
> }
>
We have already discussed this. The code becomes ugly. If you
are interested in the reasoning, please check archives.

Russell and Catalin has suggested above.

If you understand the errata in first place, you could
understand the comment.

I let Catalin, Russell comment on it more, but unnecessary
CONFIG options and polluting every function with #If, else
checks don't make sense. Rest of your comments are related
to this.

Regards,
Santosh

RE: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Santosh Shilimkar]

Catalin,
> -----Original Message-----
> From: Santosh Shilimkar [mailto:santosh.shilimkar@ti.com]
> Sent: Tuesday, February 15, 2011 12:44 PM
> To: linux-arm-kernel@lists.infradead.org; Andrei Warkentin
> Cc: linux-omap@vger.kernel.org; Kevin Hilman; tony@atomide.com;
> Catalin Marinas
> Subject: RE: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
> operation can cause data corruption
>
> > -----Original Message-----
> > From: Santosh Shilimkar [mailto:santosh.shilimkar@ti.com]
> > Sent: Monday, February 14, 2011 10:39 AM
> > To: Andrei Warkentin
> > Cc: linux-omap@vger.kernel.org; Kevin Hilman; tony@atomide.com;
> > linux-arm-kernel@lists.infradead.org; Catalin Marinas
> > Subject: RE: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
> > operation can cause data corruption
> >
>
> [....]
>
> > > ...
> > I understood that from first comment. But I am not in favor
> > of polluting common ARM files with SOC specific #ifdeffery.
> > We have gone over this when first errata support
> > was added for PL310
> >
> > I have a better way to handle this scenario.
> > Expect an updated patch for this.
> >
>
> Below is the updated version which should remove any
> OMAP dependency on these errata's. Attached same.
>
> ----
> From: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Date: Fri, 14 Jan 2011 14:16:04 +0530
> Subject: [v2 PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
> operation
> can cause data corruption
>
> PL310 implements the Clean & Invalidate by Way L2 cache maintenance
> operation (offset 0x7FC). This operation runs in background so that
> PL310 can handle normal accesses while it is in progress. Under very
> rare circumstances, due to this erratum, write data can be lost when
> PL310 treats a cacheable write transaction during a Clean &
> Invalidate
> by Way operation.
>
> Workaround:
> Disable Write-Back and Cache Linefill (Debug Control Register)
> Clean & Invalidate by Way (0x7FC)
> Re-enable Write-Back and Cache Linefill (Debug Control Register)
>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> ---

Ack , Nak ?

>  arch/arm/Kconfig                   |   13 ++++++++++++-
>  arch/arm/include/asm/outercache.h  |    1 +
>  arch/arm/mach-omap2/Kconfig        |    3 +++
>  arch/arm/mach-omap2/omap4-common.c |    7 +++++++
>  arch/arm/mm/cache-l2x0.c           |   28 +++++++++++++++----------
> ---
>  5 files changed, 38 insertions(+), 14 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 5cff165..ebadd95 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1140,7 +1140,7 @@ config ARM_ERRATA_742231
>
>  config PL310_ERRATA_588369
>  	bool "Clean & Invalidate maintenance operations do not
> invalidate
> clean lines"
> -	depends on CACHE_L2X0 && ARCH_OMAP4
> +	depends on CACHE_L2X0 && CACHE_PL310
>  	help
>  	   The PL310 L2 cache controller implements three types of
> Clean &
>  	   Invalidate maintenance operations: by Physical Address
> @@ -1177,6 +1177,17 @@ config ARM_ERRATA_743622
>  	  visible impact on the overall performance or power
> consumption
> of the
>  	  processor.
>
> +config PL310_ERRATA_727915
> +	bool "Background Clean & Invalidate by Way operation can cause
> data corruption"
> +	depends on CACHE_L2X0 && CACHE_PL310
> +	help
> +	  PL310 implements the Clean & Invalidate by Way L2 cache
> maintenance
> +	  operation (offset 0x7FC). This operation runs in background
> so
> that
> +	  PL310 can handle normal accesses while it is in progress.
> Under
> very
> +	  rare circumstances, due to this erratum, write data can be
> lost
> when
> +	  PL310 treats a cacheable write transaction during a Clean &
> +	  Invalidate by Way operation Note that this errata uses Texas
> +	  Instrument's secure monitor api to implement the work
> around.
>  endmenu
>
>  source "arch/arm/common/Kconfig"
> diff --git a/arch/arm/include/asm/outercache.h
> b/arch/arm/include/asm/outercache.h
> index fc19009..348d513 100644
> --- a/arch/arm/include/asm/outercache.h
> +++ b/arch/arm/include/asm/outercache.h
> @@ -31,6 +31,7 @@ struct outer_cache_fns {
>  #ifdef CONFIG_OUTER_CACHE_SYNC
>  	void (*sync)(void);
>  #endif
> +	void (*set_debug)(unsigned long);
>  };
>
>  #ifdef CONFIG_OUTER_CACHE
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-
> omap2/Kconfig
> index f285dd7..fd11ab4 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -45,7 +45,10 @@ config ARCH_OMAP4
>  	select CPU_V7
>  	select ARM_GIC
>  	select LOCAL_TIMERS
> +	select CACHE_L2X0
> +	select CACHE_PL310
>  	select PL310_ERRATA_588369
> +	select PL310_ERRATA_727915
>  	select ARM_ERRATA_720789
>  	select ARCH_HAS_OPP
>  	select PM_OPP if PM
> diff --git a/arch/arm/mach-omap2/omap4-common.c
> b/arch/arm/mach-omap2/omap4-common.c
> index 1926864..9ef8c29 100644
> --- a/arch/arm/mach-omap2/omap4-common.c
> +++ b/arch/arm/mach-omap2/omap4-common.c
> @@ -52,6 +52,12 @@ static void omap4_l2x0_disable(void)
>  	omap_smc1(0x102, 0x0);
>  }
>
> +static void omap4_l2x0_set_debug(unsigned long val)
> +{
> +	/* Program PL310 L2 Cache controller debug register */
> +	omap_smc1(0x100, val);
> +}
> +
>  static int __init omap_l2_cache_init(void)
>  {
>  	u32 aux_ctrl = 0;
> @@ -99,6 +105,7 @@ static int __init omap_l2_cache_init(void)
>  	 * specific one
>  	*/
>  	outer_cache.disable = omap4_l2x0_disable;
> +	outer_cache.set_debug = omap4_l2x0_set_debug;
>
>  	return 0;
>  }
> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> index 170c9bb..a8caee4 100644
> --- a/arch/arm/mm/cache-l2x0.c
> +++ b/arch/arm/mm/cache-l2x0.c
> @@ -67,18 +67,22 @@ static inline void l2x0_inv_line(unsigned long
> addr)
>  	writel_relaxed(addr, base + L2X0_INV_LINE_PA);
>  }
>
> -#ifdef CONFIG_PL310_ERRATA_588369
> +#if defined(CONFIG_PL310_ERRATA_588369) ||
> defined(CONFIG_PL310_ERRATA_727915)
>  static void debug_writel(unsigned long val)
>  {
> -	extern void omap_smc1(u32 fn, u32 arg);
> -
> -	/*
> -	 * Texas Instrument secure monitor api to modify the
> -	 * PL310 Debug Control Register.
> -	 */
> -	omap_smc1(0x100, val);
> +	if (outer_cache.set_debug)
> +		outer_cache.set_debug(val);
> +	else
> +		writel(val, l2x0_base + L2X0_DEBUG_CTRL);
> +}
> +#else
> +/* Optimised out for non-errata case */
> +static inline void debug_writel(unsigned long val)
> +{
>  }
> +#endif
>
> +#ifdef CONFIG_PL310_ERRATA_588369
>  static inline void l2x0_flush_line(unsigned long addr)
>  {
>  	void __iomem *base = l2x0_base;
> @@ -91,11 +95,6 @@ static inline void l2x0_flush_line(unsigned long
> addr)
>  }
>  #else
>
> -/* Optimised out for non-errata case */
> -static inline void debug_writel(unsigned long val)
> -{
> -}
> -
>  static inline void l2x0_flush_line(unsigned long addr)
>  {
>  	void __iomem *base = l2x0_base;
> @@ -119,9 +118,11 @@ static void l2x0_flush_all(void)
>
>  	/* clean all ways */
>  	spin_lock_irqsave(&l2x0_lock, flags);
> +	debug_writel(0x03);
>  	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
>  	cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
>  	cache_sync();
> +	debug_writel(0x00);
>  	spin_unlock_irqrestore(&l2x0_lock, flags);
>  }
>
> @@ -329,6 +330,7 @@ void __init l2x0_init(void __iomem *base, __u32
> aux_val, __u32 aux_mask)
>  	outer_cache.flush_all = l2x0_flush_all;
>  	outer_cache.inv_all = l2x0_inv_all;
>  	outer_cache.disable = l2x0_disable;
> +	outer_cache.set_debug = NULL;
>
>  	printk(KERN_INFO "%s cache controller enabled\n", type);
>  	printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL
> 0x%08x,
> Cache size: %d B\n",
> --
> 1.6.0.4

[PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Santosh Shilimkar]

Catalin,
> -----Original Message-----
> From: Santosh Shilimkar [mailto:santosh.shilimkar at ti.com]
> Sent: Tuesday, February 15, 2011 12:44 PM
> To: linux-arm-kernel at lists.infradead.org; Andrei Warkentin
> Cc: linux-omap at vger.kernel.org; Kevin Hilman; tony at atomide.com;
> Catalin Marinas
> Subject: RE: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
> operation can cause data corruption
>
> > -----Original Message-----
> > From: Santosh Shilimkar [mailto:santosh.shilimkar at ti.com]
> > Sent: Monday, February 14, 2011 10:39 AM
> > To: Andrei Warkentin
> > Cc: linux-omap at vger.kernel.org; Kevin Hilman; tony at atomide.com;
> > linux-arm-kernel at lists.infradead.org; Catalin Marinas
> > Subject: RE: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
> > operation can cause data corruption
> >
>
> [....]
>
> > > ...
> > I understood that from first comment. But I am not in favor
> > of polluting common ARM files with SOC specific #ifdeffery.
> > We have gone over this when first errata support
> > was added for PL310
> >
> > I have a better way to handle this scenario.
> > Expect an updated patch for this.
> >
>
> Below is the updated version which should remove any
> OMAP dependency on these errata's. Attached same.
>
> ----
> From: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Date: Fri, 14 Jan 2011 14:16:04 +0530
> Subject: [v2 PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
> operation
> can cause data corruption
>
> PL310 implements the Clean & Invalidate by Way L2 cache maintenance
> operation (offset 0x7FC). This operation runs in background so that
> PL310 can handle normal accesses while it is in progress. Under very
> rare circumstances, due to this erratum, write data can be lost when
> PL310 treats a cacheable write transaction during a Clean &
> Invalidate
> by Way operation.
>
> Workaround:
> Disable Write-Back and Cache Linefill (Debug Control Register)
> Clean & Invalidate by Way (0x7FC)
> Re-enable Write-Back and Cache Linefill (Debug Control Register)
>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> ---

Ack , Nak ?

>  arch/arm/Kconfig                   |   13 ++++++++++++-
>  arch/arm/include/asm/outercache.h  |    1 +
>  arch/arm/mach-omap2/Kconfig        |    3 +++
>  arch/arm/mach-omap2/omap4-common.c |    7 +++++++
>  arch/arm/mm/cache-l2x0.c           |   28 +++++++++++++++----------
> ---
>  5 files changed, 38 insertions(+), 14 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 5cff165..ebadd95 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1140,7 +1140,7 @@ config ARM_ERRATA_742231
>
>  config PL310_ERRATA_588369
>  	bool "Clean & Invalidate maintenance operations do not
> invalidate
> clean lines"
> -	depends on CACHE_L2X0 && ARCH_OMAP4
> +	depends on CACHE_L2X0 && CACHE_PL310
>  	help
>  	   The PL310 L2 cache controller implements three types of
> Clean &
>  	   Invalidate maintenance operations: by Physical Address
> @@ -1177,6 +1177,17 @@ config ARM_ERRATA_743622
>  	  visible impact on the overall performance or power
> consumption
> of the
>  	  processor.
>
> +config PL310_ERRATA_727915
> +	bool "Background Clean & Invalidate by Way operation can cause
> data corruption"
> +	depends on CACHE_L2X0 && CACHE_PL310
> +	help
> +	  PL310 implements the Clean & Invalidate by Way L2 cache
> maintenance
> +	  operation (offset 0x7FC). This operation runs in background
> so
> that
> +	  PL310 can handle normal accesses while it is in progress.
> Under
> very
> +	  rare circumstances, due to this erratum, write data can be
> lost
> when
> +	  PL310 treats a cacheable write transaction during a Clean &
> +	  Invalidate by Way operation Note that this errata uses Texas
> +	  Instrument's secure monitor api to implement the work
> around.
>  endmenu
>
>  source "arch/arm/common/Kconfig"
> diff --git a/arch/arm/include/asm/outercache.h
> b/arch/arm/include/asm/outercache.h
> index fc19009..348d513 100644
> --- a/arch/arm/include/asm/outercache.h
> +++ b/arch/arm/include/asm/outercache.h
> @@ -31,6 +31,7 @@ struct outer_cache_fns {
>  #ifdef CONFIG_OUTER_CACHE_SYNC
>  	void (*sync)(void);
>  #endif
> +	void (*set_debug)(unsigned long);
>  };
>
>  #ifdef CONFIG_OUTER_CACHE
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-
> omap2/Kconfig
> index f285dd7..fd11ab4 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -45,7 +45,10 @@ config ARCH_OMAP4
>  	select CPU_V7
>  	select ARM_GIC
>  	select LOCAL_TIMERS
> +	select CACHE_L2X0
> +	select CACHE_PL310
>  	select PL310_ERRATA_588369
> +	select PL310_ERRATA_727915
>  	select ARM_ERRATA_720789
>  	select ARCH_HAS_OPP
>  	select PM_OPP if PM
> diff --git a/arch/arm/mach-omap2/omap4-common.c
> b/arch/arm/mach-omap2/omap4-common.c
> index 1926864..9ef8c29 100644
> --- a/arch/arm/mach-omap2/omap4-common.c
> +++ b/arch/arm/mach-omap2/omap4-common.c
> @@ -52,6 +52,12 @@ static void omap4_l2x0_disable(void)
>  	omap_smc1(0x102, 0x0);
>  }
>
> +static void omap4_l2x0_set_debug(unsigned long val)
> +{
> +	/* Program PL310 L2 Cache controller debug register */
> +	omap_smc1(0x100, val);
> +}
> +
>  static int __init omap_l2_cache_init(void)
>  {
>  	u32 aux_ctrl = 0;
> @@ -99,6 +105,7 @@ static int __init omap_l2_cache_init(void)
>  	 * specific one
>  	*/
>  	outer_cache.disable = omap4_l2x0_disable;
> +	outer_cache.set_debug = omap4_l2x0_set_debug;
>
>  	return 0;
>  }
> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> index 170c9bb..a8caee4 100644
> --- a/arch/arm/mm/cache-l2x0.c
> +++ b/arch/arm/mm/cache-l2x0.c
> @@ -67,18 +67,22 @@ static inline void l2x0_inv_line(unsigned long
> addr)
>  	writel_relaxed(addr, base + L2X0_INV_LINE_PA);
>  }
>
> -#ifdef CONFIG_PL310_ERRATA_588369
> +#if defined(CONFIG_PL310_ERRATA_588369) ||
> defined(CONFIG_PL310_ERRATA_727915)
>  static void debug_writel(unsigned long val)
>  {
> -	extern void omap_smc1(u32 fn, u32 arg);
> -
> -	/*
> -	 * Texas Instrument secure monitor api to modify the
> -	 * PL310 Debug Control Register.
> -	 */
> -	omap_smc1(0x100, val);
> +	if (outer_cache.set_debug)
> +		outer_cache.set_debug(val);
> +	else
> +		writel(val, l2x0_base + L2X0_DEBUG_CTRL);
> +}
> +#else
> +/* Optimised out for non-errata case */
> +static inline void debug_writel(unsigned long val)
> +{
>  }
> +#endif
>
> +#ifdef CONFIG_PL310_ERRATA_588369
>  static inline void l2x0_flush_line(unsigned long addr)
>  {
>  	void __iomem *base = l2x0_base;
> @@ -91,11 +95,6 @@ static inline void l2x0_flush_line(unsigned long
> addr)
>  }
>  #else
>
> -/* Optimised out for non-errata case */
> -static inline void debug_writel(unsigned long val)
> -{
> -}
> -
>  static inline void l2x0_flush_line(unsigned long addr)
>  {
>  	void __iomem *base = l2x0_base;
> @@ -119,9 +118,11 @@ static void l2x0_flush_all(void)
>
>  	/* clean all ways */
>  	spin_lock_irqsave(&l2x0_lock, flags);
> +	debug_writel(0x03);
>  	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
>  	cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
>  	cache_sync();
> +	debug_writel(0x00);
>  	spin_unlock_irqrestore(&l2x0_lock, flags);
>  }
>
> @@ -329,6 +330,7 @@ void __init l2x0_init(void __iomem *base, __u32
> aux_val, __u32 aux_mask)
>  	outer_cache.flush_all = l2x0_flush_all;
>  	outer_cache.inv_all = l2x0_inv_all;
>  	outer_cache.disable = l2x0_disable;
> +	outer_cache.set_debug = NULL;
>
>  	printk(KERN_INFO "%s cache controller enabled\n", type);
>  	printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL
> 0x%08x,
> Cache size: %d B\n",
> --
> 1.6.0.4

RE: [PATCH 1/5] ARM: smp: Select local timers vs dummy timer support runtime

[Santosh Shilimkar]

Russell,
> -----Original Message-----
> From: Santosh Shilimkar [mailto:santosh.shilimkar@ti.com]
> Sent: Saturday, February 12, 2011 5:00 PM
> To: linux-omap@vger.kernel.org
> Cc: khilman@ti.com; linux-arm-kernel@lists.infradead.org;
> tony@atomide.com; Santosh Shilimkar; Russell King; David Brown;
> Daniel Walker; Bryan Huntsman; Kukjin Kim; Paul Mundt; Magnus Damm;
> Colin Cross; Erik Gilling; Srinidhi Kasagar; Linus Walleij
> Subject: [PATCH 1/5] ARM: smp: Select local timers vs dummy timer
> support runtime
>
> The current code support of dummy timers in absence of local
> timer is compile time. This is an attempt to convert it to runtime
> so that on few SOC version if the local timers aren't supported
> kernel can switch to dummy timers. OMAP4430 ES1.0 does suffer from
> this limitation.
>
> This patch should not have any functional impact on affected
> files.
>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: David Brown <davidb@codeaurora.org>
> Cc: Daniel Walker <dwalker@codeaurora.org>
> Cc: Bryan Huntsman <bryanh@codeaurora.org>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Cc: Paul Mundt <lethal@linux-sh.org>
> Cc: Magnus Damm <magnus.damm@gmail.com>
> Cc: Colin Cross <ccross@android.com>
> Cc: Erik Gilling <konkers@android.com>
> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
> Cc: Linus Walleij <linus.walleij@stericsson.com>
> ---
Any comments on this one?
So far David has acked this for mach-msm.

>  arch/arm/include/asm/localtimer.h   |    8 +++++++-
>  arch/arm/kernel/smp.c               |    7 +++----
>  arch/arm/mach-msm/timer.c           |    3 ++-
>  arch/arm/mach-omap2/timer-mpu.c     |    3 ++-
>  arch/arm/mach-realview/localtimer.c |    3 ++-
>  arch/arm/mach-s5pv310/localtimer.c  |    3 ++-
>  arch/arm/mach-shmobile/localtimer.c |    3 ++-
>  arch/arm/mach-tegra/localtimer.c    |    3 ++-
>  arch/arm/mach-ux500/localtimer.c    |    3 ++-
>  arch/arm/mach-vexpress/localtimer.c |    3 ++-
>  10 files changed, 26 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm/include/asm/localtimer.h
> b/arch/arm/include/asm/localtimer.h
> index 6bc63ab..080d74f 100644
> --- a/arch/arm/include/asm/localtimer.h
> +++ b/arch/arm/include/asm/localtimer.h
> @@ -44,8 +44,14 @@ int local_timer_ack(void);
>  /*
>   * Setup a local timer interrupt for a CPU.
>   */
> -void local_timer_setup(struct clock_event_device *);
> +int local_timer_setup(struct clock_event_device *);
>
> +#else
> +
> +static inline int local_timer_setup(struct clock_event_device *evt)
> +{
> +	return -ENXIO;
> +}
>  #endif
>
>  #endif
> diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
> index 4539ebc..7b9cc53 100644
> --- a/arch/arm/kernel/smp.c
> +++ b/arch/arm/kernel/smp.c
> @@ -474,13 +474,12 @@ static void smp_timer_broadcast(const struct
> cpumask *mask)
>  #define smp_timer_broadcast	NULL
>  #endif
>
> -#ifndef CONFIG_LOCAL_TIMERS
>  static void broadcast_timer_set_mode(enum clock_event_mode mode,
>  	struct clock_event_device *evt)
>  {
>  }
>
> -static void local_timer_setup(struct clock_event_device *evt)
> +static void dummy_timer_setup(struct clock_event_device *evt)
>  {
>  	evt->name	= "dummy_timer";
>  	evt->features	= CLOCK_EVT_FEAT_ONESHOT |
> @@ -492,7 +491,6 @@ static void local_timer_setup(struct
> clock_event_device *evt)
>
>  	clockevents_register_device(evt);
>  }
> -#endif
>
>  void __cpuinit percpu_timer_setup(void)
>  {
> @@ -502,7 +500,8 @@ void __cpuinit percpu_timer_setup(void)
>  	evt->cpumask = cpumask_of(cpu);
>  	evt->broadcast = smp_timer_broadcast;
>
> -	local_timer_setup(evt);
> +	if (local_timer_setup(evt))
> +		dummy_timer_setup(evt);
>  }
>
>  #ifdef CONFIG_HOTPLUG_CPU
> diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
> index c105d28..ae85aa9 100644
> --- a/arch/arm/mach-msm/timer.c
> +++ b/arch/arm/mach-msm/timer.c
> @@ -255,7 +255,7 @@ static void __init msm_timer_init(void)
>  }
>
>  #ifdef CONFIG_SMP
> -void __cpuinit local_timer_setup(struct clock_event_device *evt)
> +int __cpuinit local_timer_setup(struct clock_event_device *evt)
>  {
>  	struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];
>
> @@ -287,6 +287,7 @@ void __cpuinit local_timer_setup(struct
> clock_event_device *evt)
>  	gic_enable_ppi(clock->irq.irq);
>
>  	clockevents_register_device(evt);
> +	return 0;
>  }
>
>  inline int local_timer_ack(void)
> diff --git a/arch/arm/mach-omap2/timer-mpu.c b/arch/arm/mach-
> omap2/timer-mpu.c
> index 954682e..09c73dc 100644
> --- a/arch/arm/mach-omap2/timer-mpu.c
> +++ b/arch/arm/mach-omap2/timer-mpu.c
> @@ -26,9 +26,10 @@
>  /*
>   * Setup the local clock events for a CPU.
>   */
> -void __cpuinit local_timer_setup(struct clock_event_device *evt)
> +int __cpuinit local_timer_setup(struct clock_event_device *evt)
>  {
>  	evt->irq = OMAP44XX_IRQ_LOCALTIMER;
>  	twd_timer_setup(evt);
> +	return 0;
>  }
>
> diff --git a/arch/arm/mach-realview/localtimer.c b/arch/arm/mach-
> realview/localtimer.c
> index 60b4e11..aca29ce 100644
> --- a/arch/arm/mach-realview/localtimer.c
> +++ b/arch/arm/mach-realview/localtimer.c
> @@ -19,8 +19,9 @@
>  /*
>   * Setup the local clock events for a CPU.
>   */
> -void __cpuinit local_timer_setup(struct clock_event_device *evt)
> +int __cpuinit local_timer_setup(struct clock_event_device *evt)
>  {
>  	evt->irq = IRQ_LOCALTIMER;
>  	twd_timer_setup(evt);
> +	return 0;
>  }
> diff --git a/arch/arm/mach-s5pv310/localtimer.c b/arch/arm/mach-
> s5pv310/localtimer.c
> index 2784036..8239c6a 100644
> --- a/arch/arm/mach-s5pv310/localtimer.c
> +++ b/arch/arm/mach-s5pv310/localtimer.c
> @@ -18,8 +18,9 @@
>  /*
>   * Setup the local clock events for a CPU.
>   */
> -void __cpuinit local_timer_setup(struct clock_event_device *evt)
> +int __cpuinit local_timer_setup(struct clock_event_device *evt)
>  {
>  	evt->irq = IRQ_LOCALTIMER;
>  	twd_timer_setup(evt);
> +	return 0;
>  }
> diff --git a/arch/arm/mach-shmobile/localtimer.c b/arch/arm/mach-
> shmobile/localtimer.c
> index 2111c28..ad9ccc9 100644
> --- a/arch/arm/mach-shmobile/localtimer.c
> +++ b/arch/arm/mach-shmobile/localtimer.c
> @@ -18,8 +18,9 @@
>  /*
>   * Setup the local clock events for a CPU.
>   */
> -void __cpuinit local_timer_setup(struct clock_event_device *evt)
> +int __cpuinit local_timer_setup(struct clock_event_device *evt)
>  {
>  	evt->irq = 29;
>  	twd_timer_setup(evt);
> +	return 0;
>  }
> diff --git a/arch/arm/mach-tegra/localtimer.c b/arch/arm/mach-
> tegra/localtimer.c
> index f81ca7c..e91d681 100644
> --- a/arch/arm/mach-tegra/localtimer.c
> +++ b/arch/arm/mach-tegra/localtimer.c
> @@ -18,8 +18,9 @@
>  /*
>   * Setup the local clock events for a CPU.
>   */
> -void __cpuinit local_timer_setup(struct clock_event_device *evt)
> +int __cpuinit local_timer_setup(struct clock_event_device *evt)
>  {
>  	evt->irq = IRQ_LOCALTIMER;
>  	twd_timer_setup(evt);
> +	return 0;
>  }
> diff --git a/arch/arm/mach-ux500/localtimer.c b/arch/arm/mach-
> ux500/localtimer.c
> index 2288f6a..5ba1133 100644
> --- a/arch/arm/mach-ux500/localtimer.c
> +++ b/arch/arm/mach-ux500/localtimer.c
> @@ -21,8 +21,9 @@
>  /*
>   * Setup the local clock events for a CPU.
>   */
> -void __cpuinit local_timer_setup(struct clock_event_device *evt)
> +int __cpuinit local_timer_setup(struct clock_event_device *evt)
>  {
>  	evt->irq = IRQ_LOCALTIMER;
>  	twd_timer_setup(evt);
> +	return 0;
>  }
> diff --git a/arch/arm/mach-vexpress/localtimer.c b/arch/arm/mach-
> vexpress/localtimer.c
> index c0e3a59..e5adbfa 100644
> --- a/arch/arm/mach-vexpress/localtimer.c
> +++ b/arch/arm/mach-vexpress/localtimer.c
> @@ -19,8 +19,9 @@
>  /*
>   * Setup the local clock events for a CPU.
>   */
> -void __cpuinit local_timer_setup(struct clock_event_device *evt)
> +int __cpuinit local_timer_setup(struct clock_event_device *evt)
>  {
>  	evt->irq = IRQ_LOCALTIMER;
>  	twd_timer_setup(evt);
> +	return 0;
>  }
> --
> 1.6.0.4

[PATCH 1/5] ARM: smp: Select local timers vs dummy timer support runtime

[Santosh Shilimkar]

Russell,
> -----Original Message-----
> From: Santosh Shilimkar [mailto:santosh.shilimkar at ti.com]
> Sent: Saturday, February 12, 2011 5:00 PM
> To: linux-omap at vger.kernel.org
> Cc: khilman at ti.com; linux-arm-kernel at lists.infradead.org;
> tony at atomide.com; Santosh Shilimkar; Russell King; David Brown;
> Daniel Walker; Bryan Huntsman; Kukjin Kim; Paul Mundt; Magnus Damm;
> Colin Cross; Erik Gilling; Srinidhi Kasagar; Linus Walleij
> Subject: [PATCH 1/5] ARM: smp: Select local timers vs dummy timer
> support runtime
>
> The current code support of dummy timers in absence of local
> timer is compile time. This is an attempt to convert it to runtime
> so that on few SOC version if the local timers aren't supported
> kernel can switch to dummy timers. OMAP4430 ES1.0 does suffer from
> this limitation.
>
> This patch should not have any functional impact on affected
> files.
>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: David Brown <davidb@codeaurora.org>
> Cc: Daniel Walker <dwalker@codeaurora.org>
> Cc: Bryan Huntsman <bryanh@codeaurora.org>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Cc: Paul Mundt <lethal@linux-sh.org>
> Cc: Magnus Damm <magnus.damm@gmail.com>
> Cc: Colin Cross <ccross@android.com>
> Cc: Erik Gilling <konkers@android.com>
> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
> Cc: Linus Walleij <linus.walleij@stericsson.com>
> ---
Any comments on this one?
So far David has acked this for mach-msm.

>  arch/arm/include/asm/localtimer.h   |    8 +++++++-
>  arch/arm/kernel/smp.c               |    7 +++----
>  arch/arm/mach-msm/timer.c           |    3 ++-
>  arch/arm/mach-omap2/timer-mpu.c     |    3 ++-
>  arch/arm/mach-realview/localtimer.c |    3 ++-
>  arch/arm/mach-s5pv310/localtimer.c  |    3 ++-
>  arch/arm/mach-shmobile/localtimer.c |    3 ++-
>  arch/arm/mach-tegra/localtimer.c    |    3 ++-
>  arch/arm/mach-ux500/localtimer.c    |    3 ++-
>  arch/arm/mach-vexpress/localtimer.c |    3 ++-
>  10 files changed, 26 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm/include/asm/localtimer.h
> b/arch/arm/include/asm/localtimer.h
> index 6bc63ab..080d74f 100644
> --- a/arch/arm/include/asm/localtimer.h
> +++ b/arch/arm/include/asm/localtimer.h
> @@ -44,8 +44,14 @@ int local_timer_ack(void);
>  /*
>   * Setup a local timer interrupt for a CPU.
>   */
> -void local_timer_setup(struct clock_event_device *);
> +int local_timer_setup(struct clock_event_device *);
>
> +#else
> +
> +static inline int local_timer_setup(struct clock_event_device *evt)
> +{
> +	return -ENXIO;
> +}
>  #endif
>
>  #endif
> diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
> index 4539ebc..7b9cc53 100644
> --- a/arch/arm/kernel/smp.c
> +++ b/arch/arm/kernel/smp.c
> @@ -474,13 +474,12 @@ static void smp_timer_broadcast(const struct
> cpumask *mask)
>  #define smp_timer_broadcast	NULL
>  #endif
>
> -#ifndef CONFIG_LOCAL_TIMERS
>  static void broadcast_timer_set_mode(enum clock_event_mode mode,
>  	struct clock_event_device *evt)
>  {
>  }
>
> -static void local_timer_setup(struct clock_event_device *evt)
> +static void dummy_timer_setup(struct clock_event_device *evt)
>  {
>  	evt->name	= "dummy_timer";
>  	evt->features	= CLOCK_EVT_FEAT_ONESHOT |
> @@ -492,7 +491,6 @@ static void local_timer_setup(struct
> clock_event_device *evt)
>
>  	clockevents_register_device(evt);
>  }
> -#endif
>
>  void __cpuinit percpu_timer_setup(void)
>  {
> @@ -502,7 +500,8 @@ void __cpuinit percpu_timer_setup(void)
>  	evt->cpumask = cpumask_of(cpu);
>  	evt->broadcast = smp_timer_broadcast;
>
> -	local_timer_setup(evt);
> +	if (local_timer_setup(evt))
> +		dummy_timer_setup(evt);
>  }
>
>  #ifdef CONFIG_HOTPLUG_CPU
> diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
> index c105d28..ae85aa9 100644
> --- a/arch/arm/mach-msm/timer.c
> +++ b/arch/arm/mach-msm/timer.c
> @@ -255,7 +255,7 @@ static void __init msm_timer_init(void)
>  }
>
>  #ifdef CONFIG_SMP
> -void __cpuinit local_timer_setup(struct clock_event_device *evt)
> +int __cpuinit local_timer_setup(struct clock_event_device *evt)
>  {
>  	struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];
>
> @@ -287,6 +287,7 @@ void __cpuinit local_timer_setup(struct
> clock_event_device *evt)
>  	gic_enable_ppi(clock->irq.irq);
>
>  	clockevents_register_device(evt);
> +	return 0;
>  }
>
>  inline int local_timer_ack(void)
> diff --git a/arch/arm/mach-omap2/timer-mpu.c b/arch/arm/mach-
> omap2/timer-mpu.c
> index 954682e..09c73dc 100644
> --- a/arch/arm/mach-omap2/timer-mpu.c
> +++ b/arch/arm/mach-omap2/timer-mpu.c
> @@ -26,9 +26,10 @@
>  /*
>   * Setup the local clock events for a CPU.
>   */
> -void __cpuinit local_timer_setup(struct clock_event_device *evt)
> +int __cpuinit local_timer_setup(struct clock_event_device *evt)
>  {
>  	evt->irq = OMAP44XX_IRQ_LOCALTIMER;
>  	twd_timer_setup(evt);
> +	return 0;
>  }
>
> diff --git a/arch/arm/mach-realview/localtimer.c b/arch/arm/mach-
> realview/localtimer.c
> index 60b4e11..aca29ce 100644
> --- a/arch/arm/mach-realview/localtimer.c
> +++ b/arch/arm/mach-realview/localtimer.c
> @@ -19,8 +19,9 @@
>  /*
>   * Setup the local clock events for a CPU.
>   */
> -void __cpuinit local_timer_setup(struct clock_event_device *evt)
> +int __cpuinit local_timer_setup(struct clock_event_device *evt)
>  {
>  	evt->irq = IRQ_LOCALTIMER;
>  	twd_timer_setup(evt);
> +	return 0;
>  }
> diff --git a/arch/arm/mach-s5pv310/localtimer.c b/arch/arm/mach-
> s5pv310/localtimer.c
> index 2784036..8239c6a 100644
> --- a/arch/arm/mach-s5pv310/localtimer.c
> +++ b/arch/arm/mach-s5pv310/localtimer.c
> @@ -18,8 +18,9 @@
>  /*
>   * Setup the local clock events for a CPU.
>   */
> -void __cpuinit local_timer_setup(struct clock_event_device *evt)
> +int __cpuinit local_timer_setup(struct clock_event_device *evt)
>  {
>  	evt->irq = IRQ_LOCALTIMER;
>  	twd_timer_setup(evt);
> +	return 0;
>  }
> diff --git a/arch/arm/mach-shmobile/localtimer.c b/arch/arm/mach-
> shmobile/localtimer.c
> index 2111c28..ad9ccc9 100644
> --- a/arch/arm/mach-shmobile/localtimer.c
> +++ b/arch/arm/mach-shmobile/localtimer.c
> @@ -18,8 +18,9 @@
>  /*
>   * Setup the local clock events for a CPU.
>   */
> -void __cpuinit local_timer_setup(struct clock_event_device *evt)
> +int __cpuinit local_timer_setup(struct clock_event_device *evt)
>  {
>  	evt->irq = 29;
>  	twd_timer_setup(evt);
> +	return 0;
>  }
> diff --git a/arch/arm/mach-tegra/localtimer.c b/arch/arm/mach-
> tegra/localtimer.c
> index f81ca7c..e91d681 100644
> --- a/arch/arm/mach-tegra/localtimer.c
> +++ b/arch/arm/mach-tegra/localtimer.c
> @@ -18,8 +18,9 @@
>  /*
>   * Setup the local clock events for a CPU.
>   */
> -void __cpuinit local_timer_setup(struct clock_event_device *evt)
> +int __cpuinit local_timer_setup(struct clock_event_device *evt)
>  {
>  	evt->irq = IRQ_LOCALTIMER;
>  	twd_timer_setup(evt);
> +	return 0;
>  }
> diff --git a/arch/arm/mach-ux500/localtimer.c b/arch/arm/mach-
> ux500/localtimer.c
> index 2288f6a..5ba1133 100644
> --- a/arch/arm/mach-ux500/localtimer.c
> +++ b/arch/arm/mach-ux500/localtimer.c
> @@ -21,8 +21,9 @@
>  /*
>   * Setup the local clock events for a CPU.
>   */
> -void __cpuinit local_timer_setup(struct clock_event_device *evt)
> +int __cpuinit local_timer_setup(struct clock_event_device *evt)
>  {
>  	evt->irq = IRQ_LOCALTIMER;
>  	twd_timer_setup(evt);
> +	return 0;
>  }
> diff --git a/arch/arm/mach-vexpress/localtimer.c b/arch/arm/mach-
> vexpress/localtimer.c
> index c0e3a59..e5adbfa 100644
> --- a/arch/arm/mach-vexpress/localtimer.c
> +++ b/arch/arm/mach-vexpress/localtimer.c
> @@ -19,8 +19,9 @@
>  /*
>   * Setup the local clock events for a CPU.
>   */
> -void __cpuinit local_timer_setup(struct clock_event_device *evt)
> +int __cpuinit local_timer_setup(struct clock_event_device *evt)
>  {
>  	evt->irq = IRQ_LOCALTIMER;
>  	twd_timer_setup(evt);
> +	return 0;
>  }
> --
> 1.6.0.4

Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Catalin Marinas]

On 15 February 2011 07:14, Santosh Shilimkar <santosh.shilimkar@ti.com> wrote:
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1140,7 +1140,7 @@ config ARM_ERRATA_742231
>
>  config PL310_ERRATA_588369
>        bool "Clean & Invalidate maintenance operations do not invalidate
> clean lines"
> -       depends on CACHE_L2X0 && ARCH_OMAP4
> +       depends on CACHE_L2X0 && CACHE_PL310

It can just depend on CACHE_PL310 as this depends on CACHE_L2X0.

> +config PL310_ERRATA_727915
> +       bool "Background Clean & Invalidate by Way operation can cause
> data corruption"
> +       depends on CACHE_L2X0 && CACHE_PL310

Same here.

> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -45,7 +45,10 @@ config ARCH_OMAP4
>        select CPU_V7
>        select ARM_GIC
>        select LOCAL_TIMERS
> +       select CACHE_L2X0

CACHE_L2X0 has a long dependency list. You could add ARCH_OMAP4 in
there or just change the other platforms to select a HAVE_CACHE_L2X0.
Ideally we would like this option to be selectable in config just in
case you want to debug some issues.

> --- a/arch/arm/mach-omap2/omap4-common.c
> +++ b/arch/arm/mach-omap2/omap4-common.c
> @@ -52,6 +52,12 @@ static void omap4_l2x0_disable(void)
>        omap_smc1(0x102, 0x0);
>  }
>
> +static void omap4_l2x0_set_debug(unsigned long val)
> +{
> +       /* Program PL310 L2 Cache controller debug register */
> +       omap_smc1(0x100, val);
> +}

This part together with the Kconfig changes for OMAP4 could be a
separate patch, OMAP-specific.

The rest seems fine.

-- 
Catalin
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[PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Catalin Marinas]

On 15 February 2011 07:14, Santosh Shilimkar <santosh.shilimkar@ti.com> wrote:
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1140,7 +1140,7 @@ config ARM_ERRATA_742231
>
> ?config PL310_ERRATA_588369
> ? ? ? ?bool "Clean & Invalidate maintenance operations do not invalidate
> clean lines"
> - ? ? ? depends on CACHE_L2X0 && ARCH_OMAP4
> + ? ? ? depends on CACHE_L2X0 && CACHE_PL310

It can just depend on CACHE_PL310 as this depends on CACHE_L2X0.

> +config PL310_ERRATA_727915
> + ? ? ? bool "Background Clean & Invalidate by Way operation can cause
> data corruption"
> + ? ? ? depends on CACHE_L2X0 && CACHE_PL310

Same here.

> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -45,7 +45,10 @@ config ARCH_OMAP4
> ? ? ? ?select CPU_V7
> ? ? ? ?select ARM_GIC
> ? ? ? ?select LOCAL_TIMERS
> + ? ? ? select CACHE_L2X0

CACHE_L2X0 has a long dependency list. You could add ARCH_OMAP4 in
there or just change the other platforms to select a HAVE_CACHE_L2X0.
Ideally we would like this option to be selectable in config just in
case you want to debug some issues.

> --- a/arch/arm/mach-omap2/omap4-common.c
> +++ b/arch/arm/mach-omap2/omap4-common.c
> @@ -52,6 +52,12 @@ static void omap4_l2x0_disable(void)
> ? ? ? ?omap_smc1(0x102, 0x0);
> ?}
>
> +static void omap4_l2x0_set_debug(unsigned long val)
> +{
> + ? ? ? /* Program PL310 L2 Cache controller debug register */
> + ? ? ? omap_smc1(0x100, val);
> +}

This part together with the Kconfig changes for OMAP4 could be a
separate patch, OMAP-specific.

The rest seems fine.

-- 
Catalin

RE: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Santosh Shilimkar]

> -----Original Message-----
> From: catalin.marinas@gmail.com [mailto:catalin.marinas@gmail.com]
> On Behalf Of Catalin Marinas
> Sent: Wednesday, February 16, 2011 9:24 PM
> To: Santosh Shilimkar
> Cc: linux-arm-kernel@lists.infradead.org; Andrei Warkentin; Kevin
> Hilman; tony@atomide.com; linux-omap@vger.kernel.org
> Subject: Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
> operation can cause data corruption
>
> On 15 February 2011 07:14, Santosh Shilimkar
> <santosh.shilimkar@ti.com> wrote:
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -1140,7 +1140,7 @@ config ARM_ERRATA_742231
> >
> >  config PL310_ERRATA_588369
> >        bool "Clean & Invalidate maintenance operations do not
> invalidate
> > clean lines"
> > -       depends on CACHE_L2X0 && ARCH_OMAP4
> > +       depends on CACHE_L2X0 && CACHE_PL310
>
> It can just depend on CACHE_PL310 as this depends on CACHE_L2X0.
>
Ok.
> > +config PL310_ERRATA_727915
> > +       bool "Background Clean & Invalidate by Way operation can
> cause
> > data corruption"
> > +       depends on CACHE_L2X0 && CACHE_PL310
>
> Same here.
>
> > --- a/arch/arm/mach-omap2/Kconfig
> > +++ b/arch/arm/mach-omap2/Kconfig
> > @@ -45,7 +45,10 @@ config ARCH_OMAP4
> >        select CPU_V7
> >        select ARM_GIC
> >        select LOCAL_TIMERS
> > +       select CACHE_L2X0
>
> CACHE_L2X0 has a long dependency list. You could add ARCH_OMAP4 in
> there or just change the other platforms to select a
> HAVE_CACHE_L2X0.
> Ideally we would like this option to be selectable in config just in
> case you want to debug some issues.
>
I will add ARCH_OMAP4 under CACHE_L2X0.

> > --- a/arch/arm/mach-omap2/omap4-common.c
> > +++ b/arch/arm/mach-omap2/omap4-common.c
> > @@ -52,6 +52,12 @@ static void omap4_l2x0_disable(void)
> >        omap_smc1(0x102, 0x0);
> >  }
> >
> > +static void omap4_l2x0_set_debug(unsigned long val)
> > +{
> > +       /* Program PL310 L2 Cache controller debug register */
> > +       omap_smc1(0x100, val);
> > +}
>
> This part together with the Kconfig changes for OMAP4 could be a
> separate patch, OMAP-specific.
>
Agree. I will split this patch and repost.

> The rest seems fine.

Thanks for the feedback.

Regards,
Santosh
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[PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Santosh Shilimkar]

> -----Original Message-----
> From: catalin.marinas at gmail.com [mailto:catalin.marinas at gmail.com]
> On Behalf Of Catalin Marinas
> Sent: Wednesday, February 16, 2011 9:24 PM
> To: Santosh Shilimkar
> Cc: linux-arm-kernel at lists.infradead.org; Andrei Warkentin; Kevin
> Hilman; tony at atomide.com; linux-omap at vger.kernel.org
> Subject: Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
> operation can cause data corruption
>
> On 15 February 2011 07:14, Santosh Shilimkar
> <santosh.shilimkar@ti.com> wrote:
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -1140,7 +1140,7 @@ config ARM_ERRATA_742231
> >
> > ?config PL310_ERRATA_588369
> > ? ? ? ?bool "Clean & Invalidate maintenance operations do not
> invalidate
> > clean lines"
> > - ? ? ? depends on CACHE_L2X0 && ARCH_OMAP4
> > + ? ? ? depends on CACHE_L2X0 && CACHE_PL310
>
> It can just depend on CACHE_PL310 as this depends on CACHE_L2X0.
>
Ok.
> > +config PL310_ERRATA_727915
> > + ? ? ? bool "Background Clean & Invalidate by Way operation can
> cause
> > data corruption"
> > + ? ? ? depends on CACHE_L2X0 && CACHE_PL310
>
> Same here.
>
> > --- a/arch/arm/mach-omap2/Kconfig
> > +++ b/arch/arm/mach-omap2/Kconfig
> > @@ -45,7 +45,10 @@ config ARCH_OMAP4
> > ? ? ? ?select CPU_V7
> > ? ? ? ?select ARM_GIC
> > ? ? ? ?select LOCAL_TIMERS
> > + ? ? ? select CACHE_L2X0
>
> CACHE_L2X0 has a long dependency list. You could add ARCH_OMAP4 in
> there or just change the other platforms to select a
> HAVE_CACHE_L2X0.
> Ideally we would like this option to be selectable in config just in
> case you want to debug some issues.
>
I will add ARCH_OMAP4 under CACHE_L2X0.

> > --- a/arch/arm/mach-omap2/omap4-common.c
> > +++ b/arch/arm/mach-omap2/omap4-common.c
> > @@ -52,6 +52,12 @@ static void omap4_l2x0_disable(void)
> > ? ? ? ?omap_smc1(0x102, 0x0);
> > ?}
> >
> > +static void omap4_l2x0_set_debug(unsigned long val)
> > +{
> > + ? ? ? /* Program PL310 L2 Cache controller debug register */
> > + ? ? ? omap_smc1(0x100, val);
> > +}
>
> This part together with the Kconfig changes for OMAP4 could be a
> separate patch, OMAP-specific.
>
Agree. I will split this patch and repost.

> The rest seems fine.

Thanks for the feedback.

Regards,
Santosh

RE: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Santosh Shilimkar]

> -----Original Message-----
> From: catalin.marinas@gmail.com [mailto:catalin.marinas@gmail.com]
> On Behalf Of Catalin Marinas
> Sent: Wednesday, February 16, 2011 9:24 PM
> To: Santosh Shilimkar
> Cc: linux-arm-kernel@lists.infradead.org; Andrei Warkentin; Kevin
> Hilman; tony@atomide.com; linux-omap@vger.kernel.org
> Subject: Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
> operation can cause data corruption
>
> On 15 February 2011 07:14, Santosh Shilimkar
> <santosh.shilimkar@ti.com> wrote:
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -1140,7 +1140,7 @@ config ARM_ERRATA_742231
> >
> >  config PL310_ERRATA_588369
> >        bool "Clean & Invalidate maintenance operations do not
> invalidate
> > clean lines"
> > -       depends on CACHE_L2X0 && ARCH_OMAP4
> > +       depends on CACHE_L2X0 && CACHE_PL310
>
> It can just depend on CACHE_PL310 as this depends on CACHE_L2X0.
>
With CACHE_PL310 alone, I get below warning.

warning: (ARCH_OMAP4) selects PL310_ERRATA_588369 which has unmet direct
dependencies (CACHE_PL310)

This is coming because Pl310 can't be selected on V6 and OMAP
common build has V6 and V7 both enabled.

So to avoid the warning and also able to select the errata in
OMAP build, I am making the errata's depends on CACHE_L2X0
with comment.

Regards,
Santosh
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[PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Santosh Shilimkar]

> -----Original Message-----
> From: catalin.marinas at gmail.com [mailto:catalin.marinas at gmail.com]
> On Behalf Of Catalin Marinas
> Sent: Wednesday, February 16, 2011 9:24 PM
> To: Santosh Shilimkar
> Cc: linux-arm-kernel at lists.infradead.org; Andrei Warkentin; Kevin
> Hilman; tony at atomide.com; linux-omap at vger.kernel.org
> Subject: Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
> operation can cause data corruption
>
> On 15 February 2011 07:14, Santosh Shilimkar
> <santosh.shilimkar@ti.com> wrote:
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -1140,7 +1140,7 @@ config ARM_ERRATA_742231
> >
> > ?config PL310_ERRATA_588369
> > ? ? ? ?bool "Clean & Invalidate maintenance operations do not
> invalidate
> > clean lines"
> > - ? ? ? depends on CACHE_L2X0 && ARCH_OMAP4
> > + ? ? ? depends on CACHE_L2X0 && CACHE_PL310
>
> It can just depend on CACHE_PL310 as this depends on CACHE_L2X0.
>
With CACHE_PL310 alone, I get below warning.

warning: (ARCH_OMAP4) selects PL310_ERRATA_588369 which has unmet direct
dependencies (CACHE_PL310)

This is coming because Pl310 can't be selected on V6 and OMAP
common build has V6 and V7 both enabled.

So to avoid the warning and also able to select the errata in
OMAP build, I am making the errata's depends on CACHE_L2X0
with comment.

Regards,
Santosh

RE: [PATCH 2/5] omap4: Enable ARM local timers with OMAP4430 es1.0 exception

[Santosh Shilimkar]

[-- Attachment #1: Type: text/plain, Size: 2436 bytes --]

> -----Original Message-----
> From: Santosh Shilimkar [mailto:santosh.shilimkar@ti.com]
> Sent: Saturday, February 12, 2011 5:00 PM
> To: linux-omap@vger.kernel.org
> Cc: khilman@ti.com; linux-arm-kernel@lists.infradead.org;
> tony@atomide.com; Santosh Shilimkar
> Subject: [PATCH 2/5] omap4: Enable ARM local timers with OMAP4430
> es1.0 exception
>
[....]

> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-
> omap2/Kconfig
> index 1a2cf62..f285dd7 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -44,6 +44,7 @@ config ARCH_OMAP4
>  	depends on ARCH_OMAP2PLUS
>  	select CPU_V7
>  	select ARM_GIC
> +	select LOCAL_TIMERS
This change should be 'select LOCAL_TIMERS if SMP'

Otherwise, with !SMP, the build will break.
Here is the updated version with Tony's ack added.

--------
>From f76f0efffafccf76be7d820f2f775311b06087bd Mon Sep 17 00:00:00 2001
From: Santosh Shilimkar <santosh.shilimkar@ti.com>
Date: Thu, 27 Jan 2011 17:10:34 +0530
Subject: [PATCH] omap4: Enable ARM local timers with OMAP4430 es1.0
exception

On OMAP4430 ES1.0 the local timers are gated by security. Enable the
CONFIG_LOCAL_TIMERS for omap2plus build and handle the OMAP4430 es1.0
exception case.

This patch has dependency on the first patch in this series.
	ARM: smp: Select local timers vs dummy timer support runtime

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/mach-omap2/Kconfig     |    1 +
 arch/arm/mach-omap2/timer-mpu.c |    4 ++++
 2 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 1a2cf62..f285dd7 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -44,6 +44,7 @@ config ARCH_OMAP4
 	depends on ARCH_OMAP2PLUS
 	select CPU_V7
 	select ARM_GIC
+	select LOCAL_TIMERS
 	select PL310_ERRATA_588369
 	select ARM_ERRATA_720789
 	select ARCH_HAS_OPP
diff --git a/arch/arm/mach-omap2/timer-mpu.c
b/arch/arm/mach-omap2/timer-mpu.c
index 09c73dc..31c0ac4 100644
--- a/arch/arm/mach-omap2/timer-mpu.c
+++ b/arch/arm/mach-omap2/timer-mpu.c
@@ -28,6 +28,10 @@
  */
 int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
+	/* Local timers are not supprted on OMAP4430 ES1.0 */
+	if (omap_rev() == OMAP4430_REV_ES1_0)
+		return -ENXIO;
+
 	evt->irq = OMAP44XX_IRQ_LOCALTIMER;
 	twd_timer_setup(evt);
 	return 0;
-- 
1.6.0.4

[-- Attachment #2: 0002-omap4-Enable-ARM-local-timers-with-OMAP4430-es1.0-e.patch --]
[-- Type: application/octet-stream, Size: 1617 bytes --]

From f76f0efffafccf76be7d820f2f775311b06087bd Mon Sep 17 00:00:00 2001
From: Santosh Shilimkar <santosh.shilimkar@ti.com>
Date: Thu, 27 Jan 2011 17:10:34 +0530
Subject: [PATCH] omap4: Enable ARM local timers with OMAP4430 es1.0 exception

On OMAP4430 ES1.0 the local timers are gated by security. Enable the
CONFIG_LOCAL_TIMERS for omap2plus build and handle the OMAP4430 es1.0
exception case.

This patch has dependency on the first patch in this series.
	ARM: smp: Select local timers vs dummy timer support runtime

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/mach-omap2/Kconfig     |    1 +
 arch/arm/mach-omap2/timer-mpu.c |    4 ++++
 2 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 1a2cf62..f285dd7 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -44,6 +44,7 @@ config ARCH_OMAP4
 	depends on ARCH_OMAP2PLUS
 	select CPU_V7
 	select ARM_GIC
+	select LOCAL_TIMERS if SMP
 	select PL310_ERRATA_588369
 	select ARM_ERRATA_720789
 	select ARCH_HAS_OPP
diff --git a/arch/arm/mach-omap2/timer-mpu.c b/arch/arm/mach-omap2/timer-mpu.c
index 09c73dc..31c0ac4 100644
--- a/arch/arm/mach-omap2/timer-mpu.c
+++ b/arch/arm/mach-omap2/timer-mpu.c
@@ -28,6 +28,10 @@
  */
 int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
+	/* Local timers are not supprted on OMAP4430 ES1.0 */
+	if (omap_rev() == OMAP4430_REV_ES1_0)
+		return -ENXIO;
+
 	evt->irq = OMAP44XX_IRQ_LOCALTIMER;
 	twd_timer_setup(evt);
 	return 0;
-- 
1.6.0.4

[PATCH 2/5] omap4: Enable ARM local timers with OMAP4430 es1.0 exception

[Santosh Shilimkar]

> -----Original Message-----
> From: Santosh Shilimkar [mailto:santosh.shilimkar at ti.com]
> Sent: Saturday, February 12, 2011 5:00 PM
> To: linux-omap at vger.kernel.org
> Cc: khilman at ti.com; linux-arm-kernel at lists.infradead.org;
> tony at atomide.com; Santosh Shilimkar
> Subject: [PATCH 2/5] omap4: Enable ARM local timers with OMAP4430
> es1.0 exception
>
[....]

> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-
> omap2/Kconfig
> index 1a2cf62..f285dd7 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -44,6 +44,7 @@ config ARCH_OMAP4
>  	depends on ARCH_OMAP2PLUS
>  	select CPU_V7
>  	select ARM_GIC
> +	select LOCAL_TIMERS
This change should be 'select LOCAL_TIMERS if SMP'

Otherwise, with !SMP, the build will break.
Here is the updated version with Tony's ack added.

--------

Re: [PATCH 1/5] ARM: smp: Select local timers vs dummy timer support runtime

[Russell King - ARM Linux]

On Sat, Feb 12, 2011 at 04:59:43PM +0530, Santosh Shilimkar wrote:
> -#ifndef CONFIG_LOCAL_TIMERS
>  static void broadcast_timer_set_mode(enum clock_event_mode mode,
>  	struct clock_event_device *evt)
>  {
>  }
>  
> -static void local_timer_setup(struct clock_event_device *evt)
> +static void dummy_timer_setup(struct clock_event_device *evt)

Please call this broadcast_timer_setup().

[PATCH 1/5] ARM: smp: Select local timers vs dummy timer support runtime

[Russell King - ARM Linux]

On Sat, Feb 12, 2011 at 04:59:43PM +0530, Santosh Shilimkar wrote:
> -#ifndef CONFIG_LOCAL_TIMERS
>  static void broadcast_timer_set_mode(enum clock_event_mode mode,
>  	struct clock_event_device *evt)
>  {
>  }
>  
> -static void local_timer_setup(struct clock_event_device *evt)
> +static void dummy_timer_setup(struct clock_event_device *evt)

Please call this broadcast_timer_setup().

RE: [PATCH 1/5] ARM: smp: Select local timers vs dummy timersupport runtime

[Santosh Shilimkar]

> -----Original Message-----
> From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk]
> Sent: Sunday, February 20, 2011 4:34 PM
> To: Santosh Shilimkar
> Cc: linux-omap@vger.kernel.org; khilman@ti.com; linux-arm-
> kernel@lists.infradead.org; tony@atomide.com; David Brown; Daniel
> Walker; Bryan Huntsman; Kukjin Kim; Paul Mundt; Magnus Damm; Colin
> Cross; Erik Gilling; Srinidhi Kasagar; Linus Walleij
> Subject: Re: [PATCH 1/5] ARM: smp: Select local timers vs dummy
> timersupport runtime
>
> On Sat, Feb 12, 2011 at 04:59:43PM +0530, Santosh Shilimkar wrote:
> > -#ifndef CONFIG_LOCAL_TIMERS
> >  static void broadcast_timer_set_mode(enum clock_event_mode mode,
> >  	struct clock_event_device *evt)
> >  {
> >  }
> >
> > -static void local_timer_setup(struct clock_event_device *evt)
> > +static void dummy_timer_setup(struct clock_event_device *evt)
>
> Please call this broadcast_timer_setup().

Right. Will fix this.

Regards
Santosh

[PATCH 1/5] ARM: smp: Select local timers vs dummy timersupport runtime

[Santosh Shilimkar]

> -----Original Message-----
> From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk]
> Sent: Sunday, February 20, 2011 4:34 PM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; khilman at ti.com; linux-arm-
> kernel at lists.infradead.org; tony at atomide.com; David Brown; Daniel
> Walker; Bryan Huntsman; Kukjin Kim; Paul Mundt; Magnus Damm; Colin
> Cross; Erik Gilling; Srinidhi Kasagar; Linus Walleij
> Subject: Re: [PATCH 1/5] ARM: smp: Select local timers vs dummy
> timersupport runtime
>
> On Sat, Feb 12, 2011 at 04:59:43PM +0530, Santosh Shilimkar wrote:
> > -#ifndef CONFIG_LOCAL_TIMERS
> >  static void broadcast_timer_set_mode(enum clock_event_mode mode,
> >  	struct clock_event_device *evt)
> >  {
> >  }
> >
> > -static void local_timer_setup(struct clock_event_device *evt)
> > +static void dummy_timer_setup(struct clock_event_device *evt)
>
> Please call this broadcast_timer_setup().

Right. Will fix this.

Regards
Santosh

Re: [PATCH 1/5] ARM: smp: Select local timers vs dummy timersupport runtime

[Russell King - ARM Linux]

On Sun, Feb 20, 2011 at 04:37:36PM +0530, Santosh Shilimkar wrote:
> > -----Original Message-----
> > From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk]
> > Sent: Sunday, February 20, 2011 4:34 PM
> > To: Santosh Shilimkar
> > Cc: linux-omap@vger.kernel.org; khilman@ti.com; linux-arm-
> > kernel@lists.infradead.org; tony@atomide.com; David Brown; Daniel
> > Walker; Bryan Huntsman; Kukjin Kim; Paul Mundt; Magnus Damm; Colin
> > Cross; Erik Gilling; Srinidhi Kasagar; Linus Walleij
> > Subject: Re: [PATCH 1/5] ARM: smp: Select local timers vs dummy
> > timersupport runtime
> >
> > On Sat, Feb 12, 2011 at 04:59:43PM +0530, Santosh Shilimkar wrote:
> > > -#ifndef CONFIG_LOCAL_TIMERS
> > >  static void broadcast_timer_set_mode(enum clock_event_mode mode,
> > >  	struct clock_event_device *evt)
> > >  {
> > >  }
> > >
> > > -static void local_timer_setup(struct clock_event_device *evt)
> > > +static void dummy_timer_setup(struct clock_event_device *evt)
> >
> > Please call this broadcast_timer_setup().
> 
> Right. Will fix this.

Grr.  This conflicts horribly with the Versatile stuff.  Can you recreate
against what currently appears in devel rather than mainline please?

[PATCH 1/5] ARM: smp: Select local timers vs dummy timersupport runtime

[Russell King - ARM Linux]

On Sun, Feb 20, 2011 at 04:37:36PM +0530, Santosh Shilimkar wrote:
> > -----Original Message-----
> > From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk]
> > Sent: Sunday, February 20, 2011 4:34 PM
> > To: Santosh Shilimkar
> > Cc: linux-omap at vger.kernel.org; khilman at ti.com; linux-arm-
> > kernel at lists.infradead.org; tony at atomide.com; David Brown; Daniel
> > Walker; Bryan Huntsman; Kukjin Kim; Paul Mundt; Magnus Damm; Colin
> > Cross; Erik Gilling; Srinidhi Kasagar; Linus Walleij
> > Subject: Re: [PATCH 1/5] ARM: smp: Select local timers vs dummy
> > timersupport runtime
> >
> > On Sat, Feb 12, 2011 at 04:59:43PM +0530, Santosh Shilimkar wrote:
> > > -#ifndef CONFIG_LOCAL_TIMERS
> > >  static void broadcast_timer_set_mode(enum clock_event_mode mode,
> > >  	struct clock_event_device *evt)
> > >  {
> > >  }
> > >
> > > -static void local_timer_setup(struct clock_event_device *evt)
> > > +static void dummy_timer_setup(struct clock_event_device *evt)
> >
> > Please call this broadcast_timer_setup().
> 
> Right. Will fix this.

Grr.  This conflicts horribly with the Versatile stuff.  Can you recreate
against what currently appears in devel rather than mainline please?

RE: [PATCH 1/5] ARM: smp: Select local timers vs dummytimersupport runtime

[Santosh Shilimkar]

> -----Original Message-----
> From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk]
> Sent: Wednesday, February 23, 2011 10:07 PM
> To: Santosh Shilimkar
> Cc: linux-omap@vger.kernel.org; Kevin Hilman; linux-arm-
> kernel@lists.infradead.org; tony@atomide.com; David Brown; Daniel
> Walker; Bryan Huntsman; Kukjin Kim; Paul Mundt; Magnus Damm; Colin
> Cross; Erik Gilling; Srinidhi Kasagar; Linus Walleij
> Subject: Re: [PATCH 1/5] ARM: smp: Select local timers vs
> dummytimersupport runtime
>
> On Sun, Feb 20, 2011 at 04:37:36PM +0530, Santosh Shilimkar wrote:
> > > -----Original Message-----
> > > From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk]
> > > Sent: Sunday, February 20, 2011 4:34 PM
> > > To: Santosh Shilimkar
> > > Cc: linux-omap@vger.kernel.org; khilman@ti.com; linux-arm-
> > > kernel@lists.infradead.org; tony@atomide.com; David Brown;
> Daniel
> > > Walker; Bryan Huntsman; Kukjin Kim; Paul Mundt; Magnus Damm;
> Colin
> > > Cross; Erik Gilling; Srinidhi Kasagar; Linus Walleij
> > > Subject: Re: [PATCH 1/5] ARM: smp: Select local timers vs dummy
> > > timersupport runtime
> > >
> > > On Sat, Feb 12, 2011 at 04:59:43PM +0530, Santosh Shilimkar
> wrote:
> > > > -#ifndef CONFIG_LOCAL_TIMERS
> > > >  static void broadcast_timer_set_mode(enum clock_event_mode
> mode,
> > > >  	struct clock_event_device *evt)
> > > >  {
> > > >  }
> > > >
> > > > -static void local_timer_setup(struct clock_event_device *evt)
> > > > +static void dummy_timer_setup(struct clock_event_device *evt)
> > >
> > > Please call this broadcast_timer_setup().
> >
> > Right. Will fix this.
>
> Grr.  This conflicts horribly with the Versatile stuff.  Can you
> recreate
> against what currently appears in devel rather than mainline please?
Ok. I will pull your devel branch and rebase it

[PATCH 1/5] ARM: smp: Select local timers vs dummytimersupport runtime

[Santosh Shilimkar]

> -----Original Message-----
> From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk]
> Sent: Wednesday, February 23, 2011 10:07 PM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; Kevin Hilman; linux-arm-
> kernel at lists.infradead.org; tony at atomide.com; David Brown; Daniel
> Walker; Bryan Huntsman; Kukjin Kim; Paul Mundt; Magnus Damm; Colin
> Cross; Erik Gilling; Srinidhi Kasagar; Linus Walleij
> Subject: Re: [PATCH 1/5] ARM: smp: Select local timers vs
> dummytimersupport runtime
>
> On Sun, Feb 20, 2011 at 04:37:36PM +0530, Santosh Shilimkar wrote:
> > > -----Original Message-----
> > > From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk]
> > > Sent: Sunday, February 20, 2011 4:34 PM
> > > To: Santosh Shilimkar
> > > Cc: linux-omap at vger.kernel.org; khilman at ti.com; linux-arm-
> > > kernel at lists.infradead.org; tony at atomide.com; David Brown;
> Daniel
> > > Walker; Bryan Huntsman; Kukjin Kim; Paul Mundt; Magnus Damm;
> Colin
> > > Cross; Erik Gilling; Srinidhi Kasagar; Linus Walleij
> > > Subject: Re: [PATCH 1/5] ARM: smp: Select local timers vs dummy
> > > timersupport runtime
> > >
> > > On Sat, Feb 12, 2011 at 04:59:43PM +0530, Santosh Shilimkar
> wrote:
> > > > -#ifndef CONFIG_LOCAL_TIMERS
> > > >  static void broadcast_timer_set_mode(enum clock_event_mode
> mode,
> > > >  	struct clock_event_device *evt)
> > > >  {
> > > >  }
> > > >
> > > > -static void local_timer_setup(struct clock_event_device *evt)
> > > > +static void dummy_timer_setup(struct clock_event_device *evt)
> > >
> > > Please call this broadcast_timer_setup().
> >
> > Right. Will fix this.
>
> Grr.  This conflicts horribly with the Versatile stuff.  Can you
> recreate
> against what currently appears in devel rather than mainline please?
Ok. I will pull your devel branch and rebase it

RE: [PATCH 1/5] ARM: smp: Select local timers vs dummytimersupport runtime

[Santosh Shilimkar]

> -----Original Message-----
> From: Santosh Shilimkar [mailto:santosh.shilimkar@ti.com]
> Sent: Wednesday, February 23, 2011 10:09 PM
> To: Russell King - ARM Linux
> Cc: linux-omap@vger.kernel.org; Kevin Hilman; linux-arm-
> kernel@lists.infradead.org; tony@atomide.com; David Brown; Daniel
> Walker; Bryan Huntsman; Kukjin Kim; Paul Mundt; Magnus Damm; Colin
> Cross; Erik Gilling; Srinidhi Kasagar; Linus Walleij
> Subject: RE: [PATCH 1/5] ARM: smp: Select local timers vs
> dummytimersupport runtime

[....]

> >
> > Grr.  This conflicts horribly with the Versatile stuff.  Can you
> > recreate
> > against what currently appears in devel rather than mainline
> please?
> Ok. I will pull your devel branch and rebase it

Done.
Patch 6759/1 and patch 6760/1 in patch system

Regards,
Santosh

[PATCH 1/5] ARM: smp: Select local timers vs dummytimersupport runtime

[Santosh Shilimkar]

> -----Original Message-----
> From: Santosh Shilimkar [mailto:santosh.shilimkar at ti.com]
> Sent: Wednesday, February 23, 2011 10:09 PM
> To: Russell King - ARM Linux
> Cc: linux-omap at vger.kernel.org; Kevin Hilman; linux-arm-
> kernel at lists.infradead.org; tony at atomide.com; David Brown; Daniel
> Walker; Bryan Huntsman; Kukjin Kim; Paul Mundt; Magnus Damm; Colin
> Cross; Erik Gilling; Srinidhi Kasagar; Linus Walleij
> Subject: RE: [PATCH 1/5] ARM: smp: Select local timers vs
> dummytimersupport runtime

[....]

> >
> > Grr.  This conflicts horribly with the Versatile stuff.  Can you
> > recreate
> > against what currently appears in devel rather than mainline
> please?
> Ok. I will pull your devel branch and rebase it

Done.
Patch 6759/1 and patch 6760/1 in patch system

Regards,
Santosh

Re: [PATCH 1/5] ARM: smp: Select local timers vs dummytimersupport runtime

[Russell King - ARM Linux]

On Wed, Feb 23, 2011 at 11:28:11PM +0530, Santosh Shilimkar wrote:
> Patch 6759/1 and patch 6760/1 in patch system

Was there any difference between 6760 and 6753 ?

[PATCH 1/5] ARM: smp: Select local timers vs dummytimersupport runtime

[Russell King - ARM Linux]

On Wed, Feb 23, 2011 at 11:28:11PM +0530, Santosh Shilimkar wrote:
> Patch 6759/1 and patch 6760/1 in patch system

Was there any difference between 6760 and 6753 ?

RE: [PATCH 1/5] ARM: smp: Select local timers vs dummytimersupportruntime

[Santosh Shilimkar]

> -----Original Message-----
> From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk]
> Sent: Thursday, February 24, 2011 12:33 AM
> To: Santosh Shilimkar
> Cc: linux-omap@vger.kernel.org; Kevin Hilman; linux-arm-
> kernel@lists.infradead.org; tony@atomide.com; David Brown; Daniel
> Walker; Bryan Huntsman; Kukjin Kim; Paul Mundt; Magnus Damm; Colin
> Cross; Erik Gilling; Srinidhi Kasagar; Linus Walleij
> Subject: Re: [PATCH 1/5] ARM: smp: Select local timers vs
> dummytimersupportruntime
>
> On Wed, Feb 23, 2011 at 11:28:11PM +0530, Santosh Shilimkar wrote:
> > Patch 6759/1 and patch 6760/1 in patch system
>
> Was there any difference between 6760 and 6753 ?
Nope.
I just rebased them together and pushed

[PATCH 1/5] ARM: smp: Select local timers vs dummytimersupportruntime

[Santosh Shilimkar]

> -----Original Message-----
> From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk]
> Sent: Thursday, February 24, 2011 12:33 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; Kevin Hilman; linux-arm-
> kernel at lists.infradead.org; tony at atomide.com; David Brown; Daniel
> Walker; Bryan Huntsman; Kukjin Kim; Paul Mundt; Magnus Damm; Colin
> Cross; Erik Gilling; Srinidhi Kasagar; Linus Walleij
> Subject: Re: [PATCH 1/5] ARM: smp: Select local timers vs
> dummytimersupportruntime
>
> On Wed, Feb 23, 2011 at 11:28:11PM +0530, Santosh Shilimkar wrote:
> > Patch 6759/1 and patch 6760/1 in patch system
>
> Was there any difference between 6760 and 6753 ?
Nope.
I just rebased them together and pushed

Re: [PATCH 1/5] ARM: smp: Select local timers vs dummytimersupportruntime

[Russell King - ARM Linux]

On Thu, Feb 24, 2011 at 12:41:38AM +0530, Santosh Shilimkar wrote:
> > -----Original Message-----
> > From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk]
> > Sent: Thursday, February 24, 2011 12:33 AM
> > To: Santosh Shilimkar
> > Cc: linux-omap@vger.kernel.org; Kevin Hilman; linux-arm-
> > kernel@lists.infradead.org; tony@atomide.com; David Brown; Daniel
> > Walker; Bryan Huntsman; Kukjin Kim; Paul Mundt; Magnus Damm; Colin
> > Cross; Erik Gilling; Srinidhi Kasagar; Linus Walleij
> > Subject: Re: [PATCH 1/5] ARM: smp: Select local timers vs
> > dummytimersupportruntime
> >
> > On Wed, Feb 23, 2011 at 11:28:11PM +0530, Santosh Shilimkar wrote:
> > > Patch 6759/1 and patch 6760/1 in patch system
> >
> > Was there any difference between 6760 and 6753 ?
> Nope.
> I just rebased them together and pushed

Well, both patches are identical, so I'll stick with 6753/1 which I've
already merged.

Thanks

[PATCH 1/5] ARM: smp: Select local timers vs dummytimersupportruntime

[Russell King - ARM Linux]

On Thu, Feb 24, 2011 at 12:41:38AM +0530, Santosh Shilimkar wrote:
> > -----Original Message-----
> > From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk]
> > Sent: Thursday, February 24, 2011 12:33 AM
> > To: Santosh Shilimkar
> > Cc: linux-omap at vger.kernel.org; Kevin Hilman; linux-arm-
> > kernel at lists.infradead.org; tony at atomide.com; David Brown; Daniel
> > Walker; Bryan Huntsman; Kukjin Kim; Paul Mundt; Magnus Damm; Colin
> > Cross; Erik Gilling; Srinidhi Kasagar; Linus Walleij
> > Subject: Re: [PATCH 1/5] ARM: smp: Select local timers vs
> > dummytimersupportruntime
> >
> > On Wed, Feb 23, 2011 at 11:28:11PM +0530, Santosh Shilimkar wrote:
> > > Patch 6759/1 and patch 6760/1 in patch system
> >
> > Was there any difference between 6760 and 6753 ?
> Nope.
> I just rebased them together and pushed

Well, both patches are identical, so I'll stick with 6753/1 which I've
already merged.

Thanks

RE: [PATCH 1/5] ARM: smp: Select local timers vsdummytimersupportruntime

[Santosh Shilimkar]

> -----Original Message-----
> From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk]
> Sent: Thursday, February 24, 2011 1:26 AM
> To: Santosh Shilimkar
> Cc: linux-omap@vger.kernel.org; Kevin Hilman; linux-arm-
> kernel@lists.infradead.org; tony@atomide.com; David Brown; Daniel
> Walker; Bryan Huntsman; Kukjin Kim; Paul Mundt; Magnus Damm; Colin
> Cross; Erik Gilling; Srinidhi Kasagar; Linus Walleij
> Subject: Re: [PATCH 1/5] ARM: smp: Select local timers
> vsdummytimersupportruntime
>
> On Thu, Feb 24, 2011 at 12:41:38AM +0530, Santosh Shilimkar wrote:
> > > -----Original Message-----
> > > From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk]
> > > Sent: Thursday, February 24, 2011 12:33 AM
> > > To: Santosh Shilimkar
> > > Cc: linux-omap@vger.kernel.org; Kevin Hilman; linux-arm-
> > > kernel@lists.infradead.org; tony@atomide.com; David Brown;
> Daniel
> > > Walker; Bryan Huntsman; Kukjin Kim; Paul Mundt; Magnus Damm;
> Colin
> > > Cross; Erik Gilling; Srinidhi Kasagar; Linus Walleij
> > > Subject: Re: [PATCH 1/5] ARM: smp: Select local timers vs
> > > dummytimersupportruntime
> > >
> > > On Wed, Feb 23, 2011 at 11:28:11PM +0530, Santosh Shilimkar
> wrote:
> > > > Patch 6759/1 and patch 6760/1 in patch system
> > >
> > > Was there any difference between 6760 and 6753 ?
> > Nope.
> > I just rebased them together and pushed
>
> Well, both patches are identical, so I'll stick with 6753/1 which
> I've already merged.
>
Thanks.
I got discarded messege for 6753, so I submitted it.
As you noticed, they are same.

[PATCH 1/5] ARM: smp: Select local timers vsdummytimersupportruntime

[Santosh Shilimkar]

> -----Original Message-----
> From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk]
> Sent: Thursday, February 24, 2011 1:26 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; Kevin Hilman; linux-arm-
> kernel at lists.infradead.org; tony at atomide.com; David Brown; Daniel
> Walker; Bryan Huntsman; Kukjin Kim; Paul Mundt; Magnus Damm; Colin
> Cross; Erik Gilling; Srinidhi Kasagar; Linus Walleij
> Subject: Re: [PATCH 1/5] ARM: smp: Select local timers
> vsdummytimersupportruntime
>
> On Thu, Feb 24, 2011 at 12:41:38AM +0530, Santosh Shilimkar wrote:
> > > -----Original Message-----
> > > From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk]
> > > Sent: Thursday, February 24, 2011 12:33 AM
> > > To: Santosh Shilimkar
> > > Cc: linux-omap at vger.kernel.org; Kevin Hilman; linux-arm-
> > > kernel at lists.infradead.org; tony at atomide.com; David Brown;
> Daniel
> > > Walker; Bryan Huntsman; Kukjin Kim; Paul Mundt; Magnus Damm;
> Colin
> > > Cross; Erik Gilling; Srinidhi Kasagar; Linus Walleij
> > > Subject: Re: [PATCH 1/5] ARM: smp: Select local timers vs
> > > dummytimersupportruntime
> > >
> > > On Wed, Feb 23, 2011 at 11:28:11PM +0530, Santosh Shilimkar
> wrote:
> > > > Patch 6759/1 and patch 6760/1 in patch system
> > >
> > > Was there any difference between 6760 and 6753 ?
> > Nope.
> > I just rebased them together and pushed
>
> Well, both patches are identical, so I'll stick with 6753/1 which
> I've already merged.
>
Thanks.
I got discarded messege for 6753, so I submitted it.
As you noticed, they are same.