[U-Boot] [PATCH 0/9] Series short description

[U-Boot] [PATCH 0/9] Series short description

[Eric Jarrige]

The following series adds support for the Armadeus Project
board apf9328 and also fixes some driver issues or improvements
concerning the Freescale iMX1 cpu, DM9000 ethernet controler and
the final call to the relocated board_init_r for the arm920t.
The last arm920t patch should be applicable to the whole arm cpu family
if some other CPU have the same behavior of mirroring the flash
memory to a different address at power on reset.

---

Eric Jarrige (9):
      mx1: export imx_gpio_mode() function
      mx1: add i2c registers
      apf9328: Add Armadeus Project board APF9328
      apf9328: add apf9328 board in Makefile
      apf9328: add default board configuration file
      mx1: improve PLL freq computation
      mx1: change a printf in speed.c to use debug instead
      DM9000: change some printf to use debug instead
      arm920t: Fix jump to the relocated board_init_r


 MAINTAINERS                              |    4 
 MAKEALL                                  |    1 
 arch/arm/cpu/arm920t/imx/speed.c         |   31 -
 arch/arm/cpu/arm920t/start.S             |    4 
 arch/arm/include/asm/arch-imx/imx-regs.h |   30 +
 board/armadeus/apf9328/Makefile          |   51 +
 board/armadeus/apf9328/apf9328.c         |   91 +++
 board/armadeus/apf9328/apf9328fpga.c     |   89 +++
 board/armadeus/apf9328/apf9328fpga.h     |   31 +
 board/armadeus/apf9328/eeprom.c          |   88 +++
 board/armadeus/apf9328/fpga.c            |  121 ++++
 board/armadeus/apf9328/fpga.h            |   30 +
 board/armadeus/apf9328/i2c.c             |  276 ++++++++
 board/armadeus/apf9328/lowlevel_init.S   |  469 ++++++++++++++
 boards.cfg                               |    1 
 drivers/net/dm9000x.c                    |    8 
 include/configs/apf9328.h                | 1034 ++++++++++++++++++++++++++++++
 17 files changed, 2333 insertions(+), 26 deletions(-)
 create mode 100644 board/armadeus/apf9328/Makefile
 create mode 100644 board/armadeus/apf9328/apf9328.c
 create mode 100644 board/armadeus/apf9328/apf9328fpga.c
 create mode 100644 board/armadeus/apf9328/apf9328fpga.h
 create mode 100644 board/armadeus/apf9328/eeprom.c
 create mode 100644 board/armadeus/apf9328/fpga.c
 create mode 100644 board/armadeus/apf9328/fpga.h
 create mode 100644 board/armadeus/apf9328/i2c.c
 create mode 100644 board/armadeus/apf9328/lowlevel_init.S
 create mode 100644 include/configs/apf9328.h

-- 
Best regards,
Eric Jarrige

[U-Boot] [PATCH 1/9] mx1: export imx_gpio_mode() function

[Eric Jarrige]

Add imx_gpio_mode() to Freescale imx1/L/S public functions

Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org>
Cc: Stefano Babic <sbabic@denx.de>
---
 arch/arm/include/asm/arch-imx/imx-regs.h |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-imx/imx-regs.h b/arch/arm/include/asm/arch-imx/imx-regs.h
index ec94ba9..0c26a36 100644
--- a/arch/arm/include/asm/arch-imx/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx/imx-regs.h
@@ -1,5 +1,12 @@
 #ifndef _IMX_REGS_H
 #define _IMX_REGS_H
+
+#ifndef __ASSEMBLY__
+
+extern void imx_gpio_mode(int gpio_mode);
+
+#endif /* __ASSEMBLY__ */
+
 /* ------------------------------------------------------------------------
  *  Motorola IMX system registers
  * ------------------------------------------------------------------------

[U-Boot] [PATCH 2/9] mx1: add i2c registers

[Eric Jarrige]

Add i2c registers for Freescale imx1/L/S

Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org>
Cc: Stefano Babic <sbabic@denx.de>
---
 arch/arm/include/asm/arch-imx/imx-regs.h |   23 +++++++++++++++++++++++
 1 files changed, 23 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-imx/imx-regs.h b/arch/arm/include/asm/arch-imx/imx-regs.h
index 0c26a36..a7b3404 100644
--- a/arch/arm/include/asm/arch-imx/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx/imx-regs.h
@@ -638,4 +638,27 @@ extern void imx_gpio_mode(int gpio_mode);
 #define TSTAT_CAPT     (1<<1)  /* Capture event */
 #define TSTAT_COMP     (1)     /* Compare event */
 
+/*
+ * I2C module
+ */
+#define IADR   __REG(IMX_I2C_BASE + 0x000) /* I2C Address Register */
+#define IFDR   __REG(IMX_I2C_BASE + 0x004) /* I2C Frequency Divider Register*/
+#define I2CR   __REG(IMX_I2C_BASE + 0x008) /* I2C Control Register */
+#define I2SR   __REG(IMX_I2C_BASE + 0x00C) /* I2C Status Register */
+#define I2DR   __REG(IMX_I2C_BASE + 0x010) /* I2C Data I/O Register */
+/* I2C Control Register Bit Fields */
+#define I2CR_IEN 	(1<<7)		/* I2C Enable */
+#define I2CR_IIEN 	(1<<6)		/* I2C Interrupt Enable */
+#define I2CR_MSTA 	(1<<5)		/* I2C Master/Slave Mode Select */
+#define I2CR_MTX 	(1<<4)		/* I2C Transmit/Receive Mode Select */
+#define I2CR_TXAK 	(1<<3)		/* I2C Transmit Acknowledge Enable */
+#define I2CR_RSTA 	(1<<2)		/* I2C Repeated START */
+#define I2SR_ICF 	(1<<7)		/* I2C Data Transfer */
+#define I2SR_IAAS 	(1<<6)		/* I2C Addressed As a Slave */
+#define I2SR_IBB 	(1<<5)		/* I2C Bus Busy */
+#define I2SR_IAL 	(1<<4)		/* I2C Arbitration Lost */
+#define I2SR_SRW 	(1<<2)		/* I2C Slave Read/Write	*/
+#define I2SR_IIF 	(1<<1)		/* I2C interrupt */
+#define I2SR_RXAK 	(1<<0)		/* I2C Received Acknowledge */
+
 #endif				/* _IMX_REGS_H */

[U-Boot] [PATCH 2/9] mx1: add i2c registers

[Stefano Babic]

On 08/10/2011 10:33 PM, Eric Jarrige wrote:
> Add i2c registers for Freescale imx1/L/S
> 
> Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
>  arch/arm/include/asm/arch-imx/imx-regs.h |   23 +++++++++++++++++++++++
>  1 files changed, 23 insertions(+), 0 deletions(-)
> 

Hi Eric,

>  
> +/*
> + * I2C module
> + */
> +#define IADR   __REG(IMX_I2C_BASE + 0x000) /* I2C Address Register */
> +#define IFDR   __REG(IMX_I2C_BASE + 0x004) /* I2C Frequency Divider Register*/
> +#define I2CR   __REG(IMX_I2C_BASE + 0x008) /* I2C Control Register */
> +#define I2SR   __REG(IMX_I2C_BASE + 0x00C) /* I2C Status Register */
> +#define I2DR   __REG(IMX_I2C_BASE + 0x010) /* I2C Data I/O Register */

See my comments on your [PATCH 3/9] apf9328: Add Armadeus Project board
APF9328. Access to registers must be done via accessors and __REG macro
should be removed.

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH 2/9] mx1: add i2c registers

[Eric Jarrige]

Hi Stefano,

On 11 ao?t 2011, at 10:52, Stefano Babic wrote:

> On 08/10/2011 10:33 PM, Eric Jarrige wrote:
>> Add i2c registers for Freescale imx1/L/S
>> 
>> Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org>
>> Cc: Stefano Babic <sbabic@denx.de>
>> ---
>> arch/arm/include/asm/arch-imx/imx-regs.h |   23 +++++++++++++++++++++++
>> 1 files changed, 23 insertions(+), 0 deletions(-)
>> 
> 
> Hi Eric,
> 
>> 
>> +/*
>> + * I2C module
>> + */
>> +#define IADR   __REG(IMX_I2C_BASE + 0x000) /* I2C Address Register */
>> +#define IFDR   __REG(IMX_I2C_BASE + 0x004) /* I2C Frequency Divider Register*/
>> +#define I2CR   __REG(IMX_I2C_BASE + 0x008) /* I2C Control Register */
>> +#define I2SR   __REG(IMX_I2C_BASE + 0x00C) /* I2C Status Register */
>> +#define I2DR   __REG(IMX_I2C_BASE + 0x010) /* I2C Data I/O Register */
> 
> See my comments on your [PATCH 3/9] apf9328: Add Armadeus Project board
> APF9328. Access to registers must be done via accessors and __REG macro
> should be removed.

Ok, I remove the i2c driver from the apf9328 set of patches
change the __REG macro to C struct and submit the i2c driver in a separate set of patches according to your comment in the [PATCH 3/9]

Cheers,
Eric

[U-Boot] [PATCH 2/9] mx1: add i2c registers

[Wolfgang Denk]

Dear Eric Jarrige,

In message <20110810203310.21204.54944.stgit@shuttle2.etheralp.ch> you wrote:
> Add i2c registers for Freescale imx1/L/S
> 
> Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
>  arch/arm/include/asm/arch-imx/imx-regs.h |   23 +++++++++++++++++++++++
>  1 files changed, 23 insertions(+), 0 deletions(-)

Checkpatch says:

total: 0 errors, 13 warnings, 27 lines checked

Please clean up and resubmit.  Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The perversity of nature is nowhere better demonstrated by  the  fact
that,  when  exposed to the same atmosphere, bread becomes hard while
crackers become soft.

[U-Boot] [PATCH 3/9] apf9328: Add Armadeus Project board APF9328

[Eric Jarrige]

Add Armadeus Project board APF9328

Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org>
Signed-off-by: Nicolas Colombain <nicolas.colombain@armadeus.com>
---
 board/armadeus/apf9328/Makefile        |   51 +++
 board/armadeus/apf9328/apf9328.c       |   91 ++++++
 board/armadeus/apf9328/apf9328fpga.c   |   89 ++++++
 board/armadeus/apf9328/apf9328fpga.h   |   31 ++
 board/armadeus/apf9328/eeprom.c        |   88 ++++++
 board/armadeus/apf9328/fpga.c          |  121 ++++++++
 board/armadeus/apf9328/fpga.h          |   30 ++
 board/armadeus/apf9328/i2c.c           |  276 +++++++++++++++++++
 board/armadeus/apf9328/lowlevel_init.S |  469 ++++++++++++++++++++++++++++++++
 9 files changed, 1246 insertions(+), 0 deletions(-)
 create mode 100644 board/armadeus/apf9328/Makefile
 create mode 100644 board/armadeus/apf9328/apf9328.c
 create mode 100644 board/armadeus/apf9328/apf9328fpga.c
 create mode 100644 board/armadeus/apf9328/apf9328fpga.h
 create mode 100644 board/armadeus/apf9328/eeprom.c
 create mode 100644 board/armadeus/apf9328/fpga.c
 create mode 100644 board/armadeus/apf9328/fpga.h
 create mode 100644 board/armadeus/apf9328/i2c.c
 create mode 100644 board/armadeus/apf9328/lowlevel_init.S

diff --git a/board/armadeus/apf9328/Makefile b/board/armadeus/apf9328/Makefile
new file mode 100644
index 0000000..0f097cd
--- /dev/null
+++ b/board/armadeus/apf9328/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= apf9328.o i2c.o apf9328fpga.o fpga.o eeprom.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/armadeus/apf9328/apf9328.c b/board/armadeus/apf9328/apf9328.c
new file mode 100644
index 0000000..2250221
--- /dev/null
+++ b/board/armadeus/apf9328/apf9328.c
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2005-2011
+ * Nicolas Colombin <thom25@users.sourceforge.net>
+ * Eric Jarrige <eric.jarrige@armadeus.org>
+ * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+#include <flash.h>
+#include <netdev.h>
+#include "apf9328fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+	gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_1_BASE,
+				    CONFIG_SYS_SDRAM_1_SIZE);
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+#if (CONFIG_NR_DRAM_BANKS > 0)
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_1_BASE;
+	gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_1_SIZE;
+#endif
+}
+
+/*
+ * Miscellaneous intialization
+ */
+int misc_init_r(void)
+{
+	char *s;
+
+#if (CONFIG_FPGA)
+	apf9328_init_fpga();
+#endif
+
+#if (CONFIG_DRIVER_DM9000)
+	imx_gpio_mode(GPIO_PORTB | GPIO_DR | GPIO_IN | 14);
+#endif
+
+	/* detect compatibility issue of environment version */
+	s = getenv("env_version");
+	if ((NULL == s) || (0 != strcmp(s, CONFIG_ENV_VERSION))) {
+		printf("*** Warning - Environment version change suggests: "
+		       "run flash_reset_env; reset\n");
+	}
+
+	return 0;
+}
+
+void show_boot_progress(int status)
+{
+	return;
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+	return dm9000_initialize(bis);
+}
+#endif
diff --git a/board/armadeus/apf9328/apf9328fpga.c b/board/armadeus/apf9328/apf9328fpga.c
new file mode 100644
index 0000000..d64c0d4
--- /dev/null
+++ b/board/armadeus/apf9328/apf9328fpga.c
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2005-2011
+ * Nicolas Colombin <thom25@users.sourceforge.net>
+ * Eric Jarrige <eric.jarrige@armadeus.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * Spartan 3 FPGA configuration support for the APF9328 daughter board
+ */
+
+#include <common.h>
+#include <spartan3.h>
+#include <command.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/io.h>
+#include "apf9328fpga.h"
+
+#if (CONFIG_FPGA)
+DECLARE_GLOBAL_DATA_PTR;
+/* Note that these are pointers to code that is in Flash.  They will be
+ * relocated at runtime.
+ * Spartan3 code is used to download our Spartan 3 :) code is compatible.
+ * Just take care about the file size
+*/
+Xilinx_Spartan3_Slave_Serial_fns fpga_fns = {
+	fpga_pre_fn,
+	fpga_pgm_fn,
+	fpga_clk_fn,
+	fpga_init_fn,
+	fpga_done_fn,
+	fpga_wr_fn,
+};
+
+Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+	{Xilinx_Spartan3,
+	 slave_serial,
+	 XILINX_XC3S400_SIZE,
+	 (void *)&fpga_fns,
+	 0}
+};
+
+/*
+ * Initialize the fpga.  Return 1 on success, 0 on failure.
+ */
+int apf9328_init_fpga(void)
+{
+	char *autoload = getenv("firmware_autoload");
+	int i, lout = 1;
+
+	debug("%s:%d: Initialize FPGA interface (relocation offset= 0x%.8lx)\n",
+		__func__, __LINE__, gd->reloc_off);
+
+	fpga_init();
+
+	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+		debug("%s:%d: Adding fpga %d\n", __func__, __LINE__, i);
+		fpga_add(fpga_xilinx, &fpga[i]);
+	}
+
+	if ((autoload) && (0 == strcmp(autoload, "1"))) {
+		if (FPGA_SUCCESS != fpga_load(0, (void *)CONFIG_FIRMWARE_ADDR,
+					      (size_t) CONFIG_FIRMWARE_LEN)) {
+			lout = 0;
+			printf("Firmware not loaded!\n");
+		}
+	}
+	return 1;
+}
+
+#endif /* CONFIG_FPGA */
diff --git a/board/armadeus/apf9328/apf9328fpga.h b/board/armadeus/apf9328/apf9328fpga.h
new file mode 100644
index 0000000..2a15443
--- /dev/null
+++ b/board/armadeus/apf9328/apf9328fpga.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland at enterasys.com.
+ * Keith Outwater, keith_outwater at mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * Spartan 3 FPGA configuration support for the APF9328 daughter board
+ */
+
+#include "fpga.h"
+extern int apf9328_init_fpga(void);
diff --git a/board/armadeus/apf9328/eeprom.c b/board/armadeus/apf9328/eeprom.c
new file mode 100644
index 0000000..8f2ad9a
--- /dev/null
+++ b/board/armadeus/apf9328/eeprom.c
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2008-2011 Armadeus Project
+ * (C) Copyright 2007
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <dm9000.h>
+
+static int do_read_dm9000_eeprom(cmd_tbl_t *cmdtp, int flag, int argc,
+				 char * const argv[])
+{
+	unsigned int i;
+	u8 data[2];
+
+	for (i = 0; i < 0x40; i++) {
+		if (!(i % 0x10))
+			printf("\n%08x:", i);
+		dm9000_read_srom_word(i, data);
+		printf(" %02x%02x", data[1], data[0]);
+	}
+	printf("\n");
+	return 0;
+}
+
+static int do_write_dm9000_eeprom(cmd_tbl_t *cmdtp, int flag, int argc,
+				  char * const argv[])
+{
+	unsigned long offset, value;
+
+	if (argc < 4) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	strict_strtoul(argv[2], 16, &offset);
+	strict_strtoul(argv[3], 16, &value);
+	if (offset > 0x40) {
+		printf("Wrong offset : 0x%lx\n", offset);
+		cmd_usage(cmdtp);
+		return 1;
+	}
+	dm9000_write_srom_word(offset, value);
+	return 0;
+}
+
+int do_dm9000_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc < 2) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	if (strcmp(argv[1], "read") == 0) {
+		return do_read_dm9000_eeprom(cmdtp, flag, argc, argv);
+	} else if (strcmp(argv[1], "write") == 0) {
+		return do_write_dm9000_eeprom(cmdtp, flag, argc, argv);
+	} else {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+}
+
+U_BOOT_CMD(dm9000ee, 4, 1, do_dm9000_eeprom,
+	   "Read/Write eeprom connected to Ethernet Controller",
+	   "\ndm9000ee write <word offset> <value> \n"
+	   "\tdm9000ee read \n"
+	   "\tword:\t\t00-02 : MAC Address\n"
+	   "\t\t\t03-07 : DM9000 Configuration\n" "\t\t\t08-63 : User data");
diff --git a/board/armadeus/apf9328/fpga.c b/board/armadeus/apf9328/fpga.c
new file mode 100644
index 0000000..ec4c251
--- /dev/null
+++ b/board/armadeus/apf9328/fpga.c
@@ -0,0 +1,121 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland at enterasys.com.
+ * Keith Outwater, keith_outwater at mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+
+#if (CONFIG_FPGA)
+
+#include <asm/arch/imx-regs.h>
+#include <asm/io.h>
+#include <config.h>
+
+#define GPIO_PORT(x)  ((x >> 5) & 3)
+#define GPIO_SET(x)   (DR(GPIO_PORT(x)) |= (1<<(x & GPIO_PIN_MASK)))
+#define GPIO_CLEAR(x) (DR(GPIO_PORT(x)) &= ~(1<<(x & GPIO_PIN_MASK)))
+#define GPIO_WRITE(x, y) (y ? GPIO_SET(x) : GPIO_CLEAR(x))
+#define GPIO_READ(x)  ((SSR(GPIO_PORT(x)) & (1<<(x & GPIO_PIN_MASK))))
+
+/*
+ * Port bit numbers for the serial slave controls
+ */
+#define FPGA_INIT	CONFIG_SYS_FPGA_INIT
+#define FPGA_DONE	CONFIG_SYS_FPGA_DONE
+#define FPGA_DIN	CONFIG_SYS_FPGA_DATA
+#define FPGA_PROGRAM	CONFIG_SYS_FPGA_PRG
+#define FPGA_CLOCK	CONFIG_SYS_FPGA_CLK
+
+/* Note that these are pointers to code that is in Flash.  They will be
+ * relocated at runtime.
+ * Spartan2 code is used to download our Spartan 3 :) code is compatible.
+ * Just take care about the file size
+*/
+
+/*
+ * nitialize GPIO port B before download
+ */
+int fpga_pre_fn(int cookie)
+{
+	debug("%s:%d: FPGA PRE ", __func__, __LINE__);
+
+	/* Initialize GPIO pins */
+	imx_gpio_mode(FPGA_INIT | GPIO_DR | GPIO_IN);
+	imx_gpio_mode(FPGA_DONE | GPIO_DR | GPIO_IN);
+	imx_gpio_mode(FPGA_DIN | GPIO_DR | GPIO_OUT);
+	imx_gpio_mode(FPGA_PROGRAM | GPIO_DR | GPIO_OUT);
+	imx_gpio_mode(FPGA_CLOCK | GPIO_DR | GPIO_OUT);
+	return cookie;
+}
+
+/*
+ * Set the FPGA's active-low program line to the specified level
+ */
+int fpga_pgm_fn(int assert, int flush, int cookie)
+{
+	debug("%s:%d: FPGA PROGRAM %s", __func__, __LINE__,
+	       assert ? "high" : "low");
+	GPIO_WRITE(FPGA_PROGRAM, !assert);
+	return assert;
+}
+
+/*
+ * Set the FPGA's active-high clock line to the specified level
+ */
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+	debug("%s:%d: FPGA CLOCK %s", __func__, __LINE__,
+	       assert_clk ? "high" : "low");
+	GPIO_WRITE(FPGA_CLOCK, assert_clk);
+	return assert_clk;
+}
+
+/*
+ * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
+ * asserted (low).
+ */
+int fpga_init_fn(int cookie)
+{
+	debug("%s:%d: INIT check... ", __func__, __LINE__);
+	return !GPIO_READ(FPGA_INIT);
+}
+
+/*
+ * Test the state of the active-high FPGA DONE pin
+ */
+int fpga_done_fn(int cookie)
+{
+	debug("%s:%d: DONE check... ", __func__, __LINE__);
+	return GPIO_READ(FPGA_DONE);
+}
+
+/*
+ * Set the FPGA's data line to the specified level
+ */
+int fpga_wr_fn(int assert_write, int flush, int cookie)
+{
+	debug("%s:%d: DATA write... ", __func__, __LINE__);
+	GPIO_WRITE(FPGA_DIN, assert_write);
+	return assert_write;
+}
+
+#endif /* CONFIG_FPGA */
diff --git a/board/armadeus/apf9328/fpga.h b/board/armadeus/apf9328/fpga.h
new file mode 100644
index 0000000..3b226d7
--- /dev/null
+++ b/board/armadeus/apf9328/fpga.h
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland at enterasys.com.
+ * Keith Outwater, keith_outwater at mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+extern int fpga_pre_fn(int cookie);
+extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int fpga_init_fn(int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int fpga_wr_fn(int assert_write, int flush, int cookie);
diff --git a/board/armadeus/apf9328/i2c.c b/board/armadeus/apf9328/i2c.c
new file mode 100644
index 0000000..0ba0a8d
--- /dev/null
+++ b/board/armadeus/apf9328/i2c.c
@@ -0,0 +1,276 @@
+/*
+ * (C) Copyright 2005-2011 ej Armadeus Project <eric.jarrige@armadeus.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_HARD_I2C
+
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <i2c.h>
+
+/*-----------------------------------------------------------------------
+ * Definitions
+ */
+
+#define I2C_ACK		0	/* level to ack a byte */
+#define I2C_NOACK	1	/* level to noack a byte */
+
+/*-----------------------------------------------------------------------
+ * Local functions
+ */
+
+/*-----------------------------------------------------------------------
+ * START: High -> Low on SDA while SCL is High
+ * after check for a bus free
+ */
+static void imxi2c_send_start(void)
+{
+	while (I2SR & I2SR_IBB)
+		udelay(1);
+
+	I2CR |= I2CR_MSTA;
+	I2SR &= ~I2SR_IIF;
+}
+
+/*-----------------------------------------------------------------------
+ * STOP: Low -> High on SDA while SCL is High
+ * after the end of previous transfer
+ */
+static void imxi2c_send_stop(void)
+{
+	while (!(I2SR & I2SR_ICF))
+		udelay(1);
+
+	I2CR &= ~I2CR_MSTA;
+}
+
+/*-----------------------------------------------------------------------
+ * Send 8 bits and look for an acknowledgement.
+ */
+static int imxi2c_write_byte(uchar data)
+{
+	while (!(I2SR & I2SR_ICF))	/* Wait end of transfer */
+		udelay(1);
+
+	I2CR |= I2CR_MTX;
+	I2SR &= ~I2SR_IIF;
+	I2DR = data;
+
+	while (!(I2SR & I2SR_IIF))	/* checking IIF before ICF: FIXME */
+		udelay(1);
+
+	I2SR &= ~I2SR_IIF;
+
+	while (!(I2SR & I2SR_ICF))	/* Wait end of transfer */
+		udelay(1);
+
+	return I2SR & I2SR_RXAK;	/* not a nack is an ack */
+}
+
+/*-----------------------------------------------------------------------
+ * if ack == I2C_ACK, ACK the byte so can continue reading, else
+ * send I2C_NOACK to end the read.
+ */
+static uchar imxi2c_read_byte(int ack)
+{
+	int data;
+
+	while (!(I2SR & I2SR_ICF))
+		udelay(1);
+
+	I2CR &= ~I2CR_MTX;
+
+	if (ack)
+		I2CR |= I2CR_TXAK;
+	else
+		I2CR &= ~I2CR_TXAK;
+
+	data = I2DR;
+	return data;
+}
+
+/* ------------------------------------------------------------------------
+ * API Functions
+ * ------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------
+ * i2c_init compute the i2c divider to reach the requested speed
+ * see mxl reference manual
+ */
+void i2c_init(int speed, int slaveaddr)
+{
+	int hclk_dividers[] = {
+		30, 32, 36, 42, 48, 52, 60, 72,
+		80, 88, 104, 128, 144, 160, 192, 240,
+		288, 320, 384, 480, 576, 640, 768, 960,
+		1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840,
+		22, 24, 26, 26, 32, 36, 40, 44,
+		48, 56, 64, 72, 80, 96, 112, 128,
+		160, 192, 224, 256, 320, 384, 448, 512,
+		640, 768, 896, 1024, 1280, 1536, 1792, 2048
+	};
+	int refDiv = get_HCLK() / speed;
+	int i, tmpIC;
+
+	imx_gpio_mode(PA15_PF_I2C_SDA);
+	imx_gpio_mode(PA16_PF_I2C_SCL);
+
+	tmpIC = (sizeof(hclk_dividers) / sizeof(int)) - 1;
+	for (i = tmpIC; i >= 0; i--) {
+		if ((hclk_dividers[i] >= refDiv)
+		    && (hclk_dividers[i] < hclk_dividers[tmpIC])) {
+			tmpIC = i;
+		}
+	}
+
+	IFDR = tmpIC;
+	IADR = slaveaddr << 1;
+
+	if (I2SR & I2SR_IBB)
+		imxi2c_send_stop();
+
+	I2CR |= I2CR_IEN;
+}
+
+/*-----------------------------------------------------------------------
+ * Probe to see if a chip is present. Also good for checking for the
+ * completion of EEPROM writes since the chip stops responding until
+ * the write completes (typically 10mSec).
+ * probe sends a read command to probe a an address
+ */
+int i2c_probe(uchar addr)
+{
+	int rc;
+
+	imxi2c_send_start();
+	rc = imxi2c_write_byte((addr << 1) | 0);
+	imxi2c_send_stop();
+
+	return rc ? 1 : 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Read bytes
+ */
+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+	int shift;
+	debug("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n",
+	       chip, addr, alen, buffer, len);
+
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
+	/*
+	 * EEPROM chips that implement "address overflow" are ones
+	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
+	 * address and the extra bits end up in the "chip address"
+	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
+	 * four 256 byte chips.
+	 *
+	 * Note that we consider the length of the address field to
+	 * still be one byte because the extra address bits are
+	 * hidden in the chip address.
+	 */
+	chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
+
+	debug("i2c_read: fix addr_overflow: chip %02X addr %02X\n",
+	       chip, addr);
+#endif
+
+	/*
+	 * Do the addressing portion of a write cycle to set the
+	 * chip's address pointer. If the address length is zero,
+	 * don't do the normal write cycle to set the address pointer,
+	 * there is no address pointer in this chip.
+	 */
+	imxi2c_send_start();
+	if (alen > 0) {
+		if (imxi2c_write_byte(chip << 1)) {	/* write cycle */
+			imxi2c_send_stop();
+			debug("i2c_read, no chip responded %02X\n", chip);
+			return 1;
+		}
+		shift = (alen - 1) * 8;
+		while (alen-- > 0) {
+			if (imxi2c_write_byte(addr >> shift)) {
+				debug("i2c_read, address not <ACK>ed\n");
+				return 1;
+			}
+			shift -= 8;
+		}
+
+		/* reportedly some chips need a full stop */
+		imxi2c_send_stop();
+		imxi2c_send_start();
+	}
+	/*
+	 * Send the chip address again, this time for a read cycle.
+	 * Then read the data. On the last byte, we do a NACK instead
+	 * of an ACK(len == 0) to terminate the read.
+	 */
+	imxi2c_write_byte((chip << 1) | 1);	/* read cycle */
+	imxi2c_read_byte(len <= 2);
+	while (len-- > 1)
+		*buffer++ = imxi2c_read_byte(len == 1);
+
+	imxi2c_send_stop();
+	*buffer++ = imxi2c_read_byte(0);
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Write bytes
+ */
+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+	int shift, failures = 0;
+
+	debug("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n",
+	       chip, addr, alen, buffer, len);
+
+	imxi2c_send_start();
+	if (imxi2c_write_byte(chip << 1)) {	/* write cycle */
+		imxi2c_send_stop();
+		debug("i2c_write, no chip responded %02X\n", chip);
+		return 1;
+	}
+	shift = (alen - 1) * 8;
+	while (alen-- > 0) {
+		if (imxi2c_write_byte(addr >> shift)) {
+			debug("i2c_write, address not <ACK>ed\n");
+			return 1;
+		}
+		shift -= 8;
+	}
+
+	while (len-- > 0) {
+		if (imxi2c_write_byte(*buffer++))
+			failures++;
+	}
+	imxi2c_send_stop();
+	return failures;
+}
+
+#endif /* CONFIG_HARD_I2C */
diff --git a/board/armadeus/apf9328/lowlevel_init.S b/board/armadeus/apf9328/lowlevel_init.S
new file mode 100644
index 0000000..e4c6157
--- /dev/null
+++ b/board/armadeus/apf9328/lowlevel_init.S
@@ -0,0 +1,469 @@
+/*
+ * (C) Copyright 2005-2011 ej Armadeus Project <eric.jarrige@armadeus.org>
+ * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
+ * 02111-1307, USA.
+ *
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/imx-regs.h>
+
+.globl lowlevel_init
+lowlevel_init:
+/* Change PERCLK1DIV to 14 ie 14+1 */
+	ldr		r0,	=PCDR
+	ldr		r1,	=CONFIG_SYS_PCDR_VAL
+	str		r1,	[r0]
+
+/* set MCU PLL Control Register 0 */
+
+	ldr		r0,	=MPCTL0
+	ldr		r1,	=CONFIG_SYS_MPCTL0_VAL
+	str		r1,	[r0]
+
+/* set MCU PLL Control Register 1 */
+
+	ldr		r0,	=MPCTL1
+	ldr		r1,	=CONFIG_SYS_MPCTL1_VAL
+	str		r1,	[r0]
+
+/* set mpll restart bit */
+	ldr		r0, =CSCR
+	ldr		r1, [r0]
+	orr		r1,r1,#(1<<21)
+	str		r1, [r0]
+
+	mov		r2,#0x10
+1:
+	mov		r3,#0x2000
+2:
+	subs	r3,r3,#1
+	bne		2b
+
+	subs	r2,r2,#1
+	bne		1b
+
+/* set System PLL Control Register 0 */
+
+	ldr		r0,	=SPCTL0
+	ldr		r1,	=CONFIG_SYS_SPCTL0_VAL
+	str		r1,	[r0]
+
+/* set System PLL Control Register 1 */
+
+	ldr		r0,	=SPCTL1
+	ldr		r1,	=CONFIG_SYS_SPCTL1_VAL
+	str		r1,	[r0]
+
+/* set spll restart bit */
+	ldr		r0, =CSCR
+	ldr		r1, [r0]
+	orr		r1,r1,#(1<<22)
+	str		r1, [r0]
+
+	mov		r2,#0x10
+1:
+	mov		r3,#0x2000
+2:
+	subs	r3,r3,#1
+	bne		2b
+
+	subs	r2,r2,#1
+	bne		1b
+
+	ldr		r0,	=CSCR
+	ldr		r1,	=CONFIG_SYS_CSCR_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GPCR
+	ldr		r1,	=CONFIG_SYS_GPCR_VAL
+	str		r1,	[r0]
+
+/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
+ *this.....
+ *
+ * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
+ * register 1, this stops it using the output of the PLL and thus runs at the
+ * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
+ * use the value set in the CM_OSC registers...regardless of what you set it
+ * too!  Thus, although i thought i was running at 140MHz, i'm actually running
+ *@40!..
+
+ * Slapping this into my bootloader does the trick...
+
+ * MRC p15,0,r0,c1,c0,0	 ; read core configuration register
+ * ORR r0,r0,#0xC0000000	; set asynchronous clocks and not fastbus mode
+ * MCR p15,0,r0,c1,c0,0	 ; write modified value to core configuration
+ * register
+ */
+	MRC p15,0,r0,c1,c0,0
+	ORR r0,r0,#0xC0000000
+	MCR p15,0,r0,c1,c0,0
+
+/*	ldr		r0,	=GPR(0)
+	ldr		r1,	=CONFIG_SYS_GPR_A_VAL
+	str		r1,	[r0]
+*/
+
+	ldr		r0,	=DR(0)
+	ldr		r1,	=CONFIG_SYS_DR_A_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=OCR1(0)
+	ldr		r1,	=CONFIG_SYS_OCR1_A_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=OCR2(0)
+	ldr		r1,	=CONFIG_SYS_OCR2_A_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=ICONFA1(0)
+	ldr		r1,	=CONFIG_SYS_ICFA1_A_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=ICONFA2(0)
+	ldr		r1,	=CONFIG_SYS_ICFA2_A_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=ICONFB1(0)
+	ldr		r1,	=CONFIG_SYS_ICFB1_A_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=ICONFB2(0)
+	ldr		r1,	=CONFIG_SYS_ICFB2_A_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=ICR1(0)
+	ldr		r1,	=CONFIG_SYS_ICR1_A_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=ICR2(0)
+	ldr		r1,	=CONFIG_SYS_ICR2_A_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=IMR(0)
+	ldr		r1,	=CONFIG_SYS_IMR_A_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=DDIR(0)
+	ldr		r1,	=CONFIG_SYS_DDIR_A_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GPR(0)
+	ldr		r1,	=CONFIG_SYS_GPR_A_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=PUEN(0)
+	ldr		r1,	=CONFIG_SYS_PUEN_A_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GIUS(0)
+	ldr		r1,	=CONFIG_SYS_GIUS_A_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=DR(1)
+	ldr		r1,	=CONFIG_SYS_DR_B_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=OCR1(1)
+	ldr		r1,	=CONFIG_SYS_OCR1_B_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=OCR2(1)
+	ldr		r1,	=CONFIG_SYS_OCR2_B_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=ICONFA1(1)
+	ldr		r1,	=CONFIG_SYS_ICFA1_B_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=ICONFA2(1)
+	ldr		r1,	=CONFIG_SYS_ICFA2_B_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=ICONFB1(1)
+	ldr		r1,	=CONFIG_SYS_ICFB1_B_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=ICONFB2(1)
+	ldr		r1,	=CONFIG_SYS_ICFB2_B_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=ICR1(1)
+	ldr		r1,	=CONFIG_SYS_ICR1_B_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=ICR2(1)
+	ldr		r1,	=CONFIG_SYS_ICR2_B_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=IMR(1)
+	ldr		r1,	=CONFIG_SYS_IMR_B_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=DDIR(1)
+	ldr		r1,	=CONFIG_SYS_DDIR_B_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GPR(1)
+	ldr		r1,	=CONFIG_SYS_GPR_B_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=PUEN(1)
+	ldr		r1,	=CONFIG_SYS_PUEN_B_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GIUS(1)
+	ldr		r1,	=CONFIG_SYS_GIUS_B_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=DR(2)
+	ldr		r1,	=CONFIG_SYS_DR_C_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=OCR1(2)
+	ldr		r1,	=CONFIG_SYS_OCR1_C_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=OCR2(2)
+	ldr		r1,	=CONFIG_SYS_OCR2_C_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=ICONFA1(2)
+	ldr		r1,	=CONFIG_SYS_ICFA1_C_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=ICONFA2(2)
+	ldr		r1,	=CONFIG_SYS_ICFA2_C_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=ICONFB1(2)
+	ldr		r1,	=CONFIG_SYS_ICFB1_C_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=ICONFB2(2)
+	ldr		r1,	=CONFIG_SYS_ICFB2_C_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=ICR1(2)
+	ldr		r1,	=CONFIG_SYS_ICR1_C_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=ICR2(2)
+	ldr		r1,	=CONFIG_SYS_ICR2_C_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=IMR(2)
+	ldr		r1,	=CONFIG_SYS_IMR_C_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=DDIR(2)
+	ldr		r1,	=CONFIG_SYS_DDIR_C_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GPR(2)
+	ldr		r1,	=CONFIG_SYS_GPR_C_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=PUEN(2)
+	ldr		r1,	=CONFIG_SYS_PUEN_C_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GIUS(2)
+	ldr		r1,	=CONFIG_SYS_GIUS_C_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=DR(3)
+	ldr		r1,	=CONFIG_SYS_DR_D_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=OCR1(3)
+	ldr		r1,	=CONFIG_SYS_OCR1_D_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=OCR2(3)
+	ldr		r1,	=CONFIG_SYS_OCR2_D_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=ICONFA1(3)
+	ldr		r1,	=CONFIG_SYS_ICFA1_D_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=ICONFA2(3)
+	ldr		r1,	=CONFIG_SYS_ICFA2_D_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=ICONFB1(3)
+	ldr		r1,	=CONFIG_SYS_ICFB1_D_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=ICONFB2(3)
+	ldr		r1,	=CONFIG_SYS_ICFB2_D_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=ICR1(3)
+	ldr		r1,	=CONFIG_SYS_ICR1_D_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=ICR2(3)
+	ldr		r1,	=CONFIG_SYS_ICR2_D_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=IMR(3)
+	ldr		r1,	=CONFIG_SYS_IMR_D_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=DDIR(3)
+	ldr		r1,	=CONFIG_SYS_DDIR_D_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GPR(3)
+	ldr		r1,	=CONFIG_SYS_GPR_D_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=PUEN(3)
+	ldr		r1,	=CONFIG_SYS_PUEN_D_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GIUS(3)
+	ldr		r1,	=CONFIG_SYS_GIUS_D_VAL
+	str		r1,	[r0]
+
+/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
+
+	ldr		r0,	=FMCR
+	ldr		r1,	=CONFIG_SYS_FMCR_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=CS0U
+	ldr		r1,	=CONFIG_SYS_CS0U_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=CS0L
+	ldr		r1,	=CONFIG_SYS_CS0L_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=CS1U
+	ldr		r1,	=CONFIG_SYS_CS1U_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=CS1L
+	ldr		r1,	=CONFIG_SYS_CS1L_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=CS2U
+	ldr		r1,	=CONFIG_SYS_CS2U_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=CS2L
+	ldr		r1,	=CONFIG_SYS_CS2L_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=CS3U
+	ldr		r1,	=CONFIG_SYS_CS3U_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=CS3L
+	ldr		r1,	=CONFIG_SYS_CS3L_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=CS4U
+	ldr		r1,	=CONFIG_SYS_CS4U_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=CS4L
+	ldr		r1,	=CONFIG_SYS_CS4L_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=CS5U
+	ldr		r1,	=CONFIG_SYS_CS5U_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=CS5L
+	ldr		r1,	=CONFIG_SYS_CS5L_VAL
+	str		r1,	[r0]
+
+	adr	r0, sdramsetup	/* r0 <- current position of code */
+	/* test if we run from flash or RAM */
+	ldr	r1, =CONFIG_SYS_SDRAM_1_BASE
+	cmp	r1, r0		/* don't reloc during debug*/
+	bhi		sdramsetup
+	/* test if we run from flash or RAM */
+	ldr	r1, =CONFIG_SYS_FLASH_BASE
+	cmp	r0, r1		/* don't reloc during debug */
+	bmi		copy2ram
+
+/* SDRAM Setup */
+sdramsetup:
+	ldr		r0, =SDCTL0
+	ldr		r1, =CONFIG_SYS_PRECHARGE_CMD
+	str		r1,	[r0]
+
+	ldr		r1, =CONFIG_SYS_SDRAM_1_BASE			\
+				+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
+	ldr		r2,	[r1]
+
+	ldr		r1, =CONFIG_SYS_AUTOREFRESH_CMD
+	str		r1,	[r0]
+
+	ldr		r1, =CONFIG_SYS_SDRAM_1_BASE
+	ldr		r2,	[r1] /* Issue AutoRefresh Command */
+	ldr		r2,	[r1]
+	ldr		r2,	[r1]
+	ldr		r2,	[r1]
+	ldr		r2,	[r1]
+	ldr		r2,	[r1]
+	ldr		r2,	[r1]
+	ldr		r2,	[r1]
+
+	ldr		r1, =CONFIG_SYS_SET_MODE_REG_CMD
+	str		r1,	[r0]
+
+	ldr		r1, =CONFIG_SYS_SDRAM_1_BASE			\
+				+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
+	str		r2,	[r1]
+
+	ldr		r1, =CONFIG_SYS_NORMAL_RW_CMD
+	str		r1,	[r0]
+/* make U-Boot runnable form "almost" anywhere */
+/* but SYS_TEXT_BASE should be in RAM */
+copy2ram:		/* populate _TEXT_BASE with U-Boot from load addr */
+	ldr	r0, _start_adr
+	ldr	r1, _copy2ram
+	sub	r1, r1, r0
+	adr	r0, copy2ram
+	sub	r0, r0, r1
+	ldr	r1, =CONFIG_SYS_TEXT_BASE
+	cmp	r0, r1
+	beq	end_of_copy2ram		/* skip U-Boot copy */
+	ldr	r2, =CONFIG_SYS_MONITOR_LEN
+	add	r2, r2, r0		/* r2 <- source end address	    */
+
+copy_loop:
+	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
+	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
+
+end_of_copy2ram:
+	mov	pc,lr
+
+_copy2ram:
+	.word copy2ram
+_start_adr:
+	.word _start

[U-Boot] [PATCH 3/9] apf9328: Add Armadeus Project board APF9328

[Stefano Babic]

On 08/10/2011 10:33 PM, Eric Jarrige wrote:
> Add Armadeus Project board APF9328
> 
> Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org>
> Signed-off-by: Nicolas Colombain <nicolas.colombain@armadeus.com>

Hi Eric,


> diff --git a/board/armadeus/apf9328/apf9328.c b/board/armadeus/apf9328/apf9328.c
> new file mode 100644
> index 0000000..2250221
> --- /dev/null
> +++ b/board/armadeus/apf9328/apf9328.c
> @@ -0,0 +1,91 @@
> +/*
> + * (C) Copyright 2005-2011
> + * Nicolas Colombin <thom25@users.sourceforge.net>
> + * Eric Jarrige <eric.jarrige@armadeus.org>
> + * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + *
> + */
> +
> +#include <common.h>
> +#include <asm/arch/imx-regs.h>
> +#include <flash.h>
> +#include <netdev.h>
> +#include "apf9328fpga.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int board_init(void)
> +{
> +	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;

Is there no MACH_TYPE for this board ? It is uncommon for an ARM board.
Should this board run Linux ?

> +void dram_init_banksize(void)
> +{
> +#if (CONFIG_NR_DRAM_BANKS > 0)

I think you can get rid of this #ifdef, if you have no RAM at all you
cannot simply run u-boot.

> + * Miscellaneous intialization
> + */
> +int misc_init_r(void)
> +{
> +	char *s;
> +
> +#if (CONFIG_FPGA)
> +	apf9328_init_fpga();
> +#endif
> +
> +#if (CONFIG_DRIVER_DM9000)
> +	imx_gpio_mode(GPIO_PORTB | GPIO_DR | GPIO_IN | 14);

Is there a reason to put this code here and not in board_eth_init ? It
is related to Ethernet and I am supposing this setup should be done
before dm9000_initialize.

> +
> +void show_boot_progress(int status)
> +{
> +	return;
> +}

This function seems to me not very useful. Is it not better to drop it ?
It is not strictly required.
You set also #undef CONFIG_SHOW_BOOT_PROGRESS in the configuration file.


> +#if (CONFIG_FPGA)
> +DECLARE_GLOBAL_DATA_PTR;
> +/* Note that these are pointers to code that is in Flash.  They will be
> + * relocated at runtime.
> + * Spartan3 code is used to download our Spartan 3 :) code is compatible.
> + * Just take care about the file size
> +*/
> +Xilinx_Spartan3_Slave_Serial_fns fpga_fns = {
> +	fpga_pre_fn,
> +	fpga_pgm_fn,
> +	fpga_clk_fn,
> +	fpga_init_fn,
> +	fpga_done_fn,
> +	fpga_wr_fn,
> +};
> +
> +Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {

Do you have more as one FPGA on your board ? And if this is true, they
share the same firmware ? (I see only one CONFIG_FIRMWARE_ADDR..)

> +/*
> + * Initialize the fpga.  Return 1 on success, 0 on failure.
> + */
> +int apf9328_init_fpga(void)
> +{
> +	char *autoload = getenv("firmware_autoload");
> +	int i, lout = 1;
> +
> +	debug("%s:%d: Initialize FPGA interface (relocation offset= 0x%.8lx)\n",
> +		__func__, __LINE__, gd->reloc_off);
> +
> +	fpga_init();
> +
> +	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
> +		debug("%s:%d: Adding fpga %d\n", __func__, __LINE__, i);
> +		fpga_add(fpga_xilinx, &fpga[i]);
> +	}
> +
> +	if ((autoload) && (0 == strcmp(autoload, "1"))) {
> +		if (FPGA_SUCCESS != fpga_load(0, (void *)CONFIG_FIRMWARE_ADDR,

I am confused...you add in the configuration file a variable
"firmware_addr=", and you set it as default to CONFIG_FIRMWARE_ADDR, but
you do not use this variable at all. Do you not shoul get the address
with getenv("firmware_addr") instead of the precompiled value ?

If you add some new CONFIG_ switches in U-Boot, you must document them
in the Readme file. However, CONFIG_FIRMWARE_* do not need to be global,
right ?

> +/*
> + * Spartan 3 FPGA configuration support for the APF9328 daughter board
> + */
> +
> +#include "fpga.h"
> +extern int apf9328_init_fpga(void);
> diff --git a/board/armadeus/apf9328/eeprom.c b/board/armadeus/apf9328/eeprom.c

It seems to much fo me to add a new file only for a single prototype.
and it is used only in apf9328fpga.c, as I can see.

> +
> +#include <common.h>
> +#include <command.h>
> +#include <dm9000.h>
> +
> +static int do_read_dm9000_eeprom(cmd_tbl_t *cmdtp, int flag, int argc,
> +				 char * const argv[])
> +{
> +	unsigned int i;
> +	u8 data[2];
> +
> +	for (i = 0; i < 0x40; i++) {
> +		if (!(i % 0x10))
> +			printf("\n%08x:", i);
> +		dm9000_read_srom_word(i, data);
> +		printf(" %02x%02x", data[1], data[0]);
> +	}

These functions can be factorized. I think the best place is inside the
DM9000 driver itself, removing them from board code.


> +#include <common.h>
> +
> +#if (CONFIG_FPGA)

#ifdef. We do not want to explicitely set the value for the CONFIG_
switches. It must be enough to use

#define CONFIG_FPGA

in your configuration file,

> +/*
> + * nitialize GPIO port B before download

Initialize

> +extern int fpga_pre_fn(int cookie);
> +extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
> +extern int fpga_init_fn(int cookie);
> +extern int fpga_done_fn(int cookie);
> +extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
> +extern int fpga_wr_fn(int assert_write, int flush, int cookie);

Maybe can you add here the prototy you set in apf9328.h ?

> diff --git a/board/armadeus/apf9328/i2c.c b/board/armadeus/apf9328/i2c.c

This is a I2C driver, and must be stored into drivers/i2c, not in board
directory. Please split your patch and push a separate patch only for
the I2C code, sending it to the I2C maintainer, too.

> +#include <common.h>
> +
> +#ifdef CONFIG_HARD_I2C
> +
> +#include <asm/io.h>
> +#include <asm/arch/imx-regs.h>
> +#include <i2c.h>
> +
> +/*-----------------------------------------------------------------------
> + * Definitions
> + */
> +
> +#define I2C_ACK		0	/* level to ack a byte */
> +#define I2C_NOACK	1	/* level to noack a byte */
> +
> +/*-----------------------------------------------------------------------
> + * Local functions
> + */
> +
> +/*-----------------------------------------------------------------------
> + * START: High -> Low on SDA while SCL is High
> + * after check for a bus free
> + */
> +static void imxi2c_send_start(void)
> +{
> +	while (I2SR & I2SR_IBB)
> +		udelay(1);

You are using the __REG macros, that are not allowed anymore in new
u-boot code. Instead of that, please add C structure and use general
accessors (writel, readl,...) to access to the registers. This comment
apply to the whole code here.


> diff --git a/board/armadeus/apf9328/lowlevel_init.S b/board/armadeus/apf9328/lowlevel_init.S
> new file mode 100644
> index 0000000..e4c6157
> --- /dev/null
> +++ b/board/armadeus/apf9328/lowlevel_init.S
> @@ -0,0 +1,469 @@
> +/*
> + * (C) Copyright 2005-2011 ej Armadeus Project <eric.jarrige@armadeus.org>
> + * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
> + * 02111-1307, USA.
> + *
> + */
> +
> +#include <config.h>
> +#include <version.h>
> +#include <asm/arch/imx-regs.h>
> +
> +.globl lowlevel_init
> +lowlevel_init:
> +/* Change PERCLK1DIV to 14 ie 14+1 */
> +	ldr		r0,	=PCDR
> +	ldr		r1,	=CONFIG_SYS_PCDR_VAL
> +	str		r1,	[r0]
> +
> +/* set MCU PLL Control Register 0 */
> +
> +	ldr		r0,	=MPCTL0
> +	ldr		r1,	=CONFIG_SYS_MPCTL0_VAL
> +	str		r1,	[r0]
> +
> +/* set MCU PLL Control Register 1 */
> +
> +	ldr		r0,	=MPCTL1
> +	ldr		r1,	=CONFIG_SYS_MPCTL1_VAL
> +	str		r1,	[r0]
> +
> +/* set mpll restart bit */
> +	ldr		r0, =CSCR
> +	ldr		r1, [r0]
> +	orr		r1,r1,#(1<<21)
> +	str		r1, [r0]
> +
> +	mov		r2,#0x10
> +1:
> +	mov		r3,#0x2000
> +2:
> +	subs	r3,r3,#1
> +	bne		2b
> +
> +	subs	r2,r2,#1
> +	bne		1b
> +
> +/* set System PLL Control Register 0 */
> +
> +	ldr		r0,	=SPCTL0
> +	ldr		r1,	=CONFIG_SYS_SPCTL0_VAL
> +	str		r1,	[r0]
> +
> +/* set System PLL Control Register 1 */
> +
> +	ldr		r0,	=SPCTL1
> +	ldr		r1,	=CONFIG_SYS_SPCTL1_VAL
> +	str		r1,	[r0]
> +
> +/* set spll restart bit */
> +	ldr		r0, =CSCR
> +	ldr		r1, [r0]
> +	orr		r1,r1,#(1<<22)
> +	str		r1, [r0]
> +
> +	mov		r2,#0x10
> +1:
> +	mov		r3,#0x2000
> +2:
> +	subs	r3,r3,#1
> +	bne		2b
> +
> +	subs	r2,r2,#1
> +	bne		1b
> +
> +	ldr		r0,	=CSCR
> +	ldr		r1,	=CONFIG_SYS_CSCR_VAL
> +	str		r1,	[r0]
> +
> +	ldr		r0,	=GPCR
> +	ldr		r1,	=CONFIG_SYS_GPCR_VAL
> +	str		r1,	[r0]
> +
> +/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
> + *this.....
> + *
> + * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
> + * register 1, this stops it using the output of the PLL and thus runs at the
> + * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
> + * use the value set in the CM_OSC registers...regardless of what you set it
> + * too!  Thus, although i thought i was running at 140MHz, i'm actually running
> + * at 40!..
> +
> + * Slapping this into my bootloader does the trick...
> +
> + * MRC p15,0,r0,c1,c0,0	 ; read core configuration register
> + * ORR r0,r0,#0xC0000000	; set asynchronous clocks and not fastbus mode
> + * MCR p15,0,r0,c1,c0,0	 ; write modified value to core configuration
> + * register
> + */
> +	MRC p15,0,r0,c1,c0,0
> +	ORR r0,r0,#0xC0000000
> +	MCR p15,0,r0,c1,c0,0
> +
> +/*	ldr		r0,	=GPR(0)

Do not add dead code, simply drop it.

However, this code is quite the same I can find on other IMX boards. Can
we factorize it and push it as common code ?

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH 3/9] apf9328: Add Armadeus Project board APF9328

[Eric Jarrige]

Hi Stefano,

> On 08/10/2011 10:33 PM, Eric Jarrige wrote:
>> Add Armadeus Project board APF9328
>> 
>> Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org>
>> Signed-off-by: Nicolas Colombain <nicolas.colombain@armadeus.com>
> 
> Hi Eric,
> 
> 
>> diff --git a/board/armadeus/apf9328/apf9328.c b/board/armadeus/apf9328/apf9328.c
>> new file mode 100644
>> index 0000000..2250221
>> --- /dev/null
>> +++ b/board/armadeus/apf9328/apf9328.c
>> @@ -0,0 +1,91 @@
>> +/*
>> + * (C) Copyright 2005-2011
>> + * Nicolas Colombin <thom25@users.sourceforge.net>
>> + * Eric Jarrige <eric.jarrige@armadeus.org>
>> + * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> + * MA 02111-1307 USA
>> + *
>> + */
>> +
>> +#include <common.h>
>> +#include <asm/arch/imx-regs.h>
>> +#include <flash.h>
>> +#include <netdev.h>
>> +#include "apf9328fpga.h"
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +int board_init(void)
>> +{
>> +	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
> 
> Is there no MACH_TYPE for this board ? It is uncommon for an ARM board.
> Should this board run Linux ?
The MACH_TYPE for this board is 906. This board runs linux and the integration in linux is on going.
> 
>> +void dram_init_banksize(void)
>> +{
>> +#if (CONFIG_NR_DRAM_BANKS > 0)
> 
> I think you can get rid of this #ifdef, if you have no RAM at all you
> cannot simply run u-boot.
Good point. I will fix it.

> 
>> + * Miscellaneous intialization
>> + */
>> +int misc_init_r(void)
>> +{
>> +	char *s;
>> +
>> +#if (CONFIG_FPGA)
>> +	apf9328_init_fpga();
>> +#endif
>> +
>> +#if (CONFIG_DRIVER_DM9000)
>> +	imx_gpio_mode(GPIO_PORTB | GPIO_DR | GPIO_IN | 14);
> 
> Is there a reason to put this code here and not in board_eth_init ? It
> is related to Ethernet and I am supposing this setup should be done
> before dm9000_initialize.
The idea is to keep the configuration  of the CPU pins at one place and to keep the initialization of the ethernet controller in a separate function. 
Here this principle of segregation is not obvious as there is only one GPIO pin to configure.

 
> 
>> +
>> +void show_boot_progress(int status)
>> +{
>> +	return;
>> +}
> 
> This function seems to me not very useful. Is it not better to drop it ?
> It is not strictly required.
> You set also #undef CONFIG_SHOW_BOOT_PROGRESS in the configuration file.
Well I choosed to keep it in place in empty state to be the template for the final user to add their own debug method if needed.
If it is an issue I would prefer to define the CONFIG_SHOW_BOOT_PROGRESS in the configuration file than removing this empty show_boot_progress as the main purpose of the board is education and trainings on embedded developments.

> 
> 
>> +#if (CONFIG_FPGA)
>> +DECLARE_GLOBAL_DATA_PTR;
>> +/* Note that these are pointers to code that is in Flash.  They will be
>> + * relocated at runtime.
>> + * Spartan3 code is used to download our Spartan 3 :) code is compatible.
>> + * Just take care about the file size
>> +*/
>> +Xilinx_Spartan3_Slave_Serial_fns fpga_fns = {
>> +	fpga_pre_fn,
>> +	fpga_pgm_fn,
>> +	fpga_clk_fn,
>> +	fpga_init_fn,
>> +	fpga_done_fn,
>> +	fpga_wr_fn,
>> +};
>> +
>> +Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
> 
> Do you have more as one FPGA on your board ? And if this is true, they
> share the same firmware ? (I see only one CONFIG_FIRMWARE_ADDR..)
The APF9328 is a SOM therefore it possible to connect some other FPGA to the board. In such a situation the idea is to concatenate all the bitstream files in the firmware partition.
During the download process to the FPGAs the end of one FPGA download starts the download of the next one using the FPGA signal PRG_DONE.
So that it possible to have all firmware in only one partition and save memory space by using bitstream files.
To be honest I do not remember if someone use this feature on this board but that is . 

> 
>> +/*
>> + * Initialize the fpga.  Return 1 on success, 0 on failure.
>> + */
>> +int apf9328_init_fpga(void)
>> +{
>> +	char *autoload = getenv("firmware_autoload");
>> +	int i, lout = 1;
>> +
>> +	debug("%s:%d: Initialize FPGA interface (relocation offset= 0x%.8lx)\n",
>> +		__func__, __LINE__, gd->reloc_off);
>> +
>> +	fpga_init();
>> +
>> +	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
>> +		debug("%s:%d: Adding fpga %d\n", __func__, __LINE__, i);
>> +		fpga_add(fpga_xilinx, &fpga[i]);
>> +	}
>> +
>> +	if ((autoload) && (0 == strcmp(autoload, "1"))) {
>> +		if (FPGA_SUCCESS != fpga_load(0, (void *)CONFIG_FIRMWARE_ADDR,
> 
> I am confused...you add in the configuration file a variable
> "firmware_addr=", and you set it as default to CONFIG_FIRMWARE_ADDR, but
> you do not use this variable at all. Do you not shoul get the address
> with getenv("firmware_addr") instead of the precompiled value ?

I use this variable in the script "flash_firmware" but it is a good point as I should
use getenv() instead of the CONFIG_FIRMWARE_ADDR.
I will do it. Thx

> 
> If you add some new CONFIG_ switches in U-Boot, you must document them
> in the Readme file. However, CONFIG_FIRMWARE_* do not need to be global,
> right ?
For the time being this switch applies to this board only. So I did not plan to document it in the README.
It is not clear for me if I should add a documentation in the README since this switch is only used in the APF9328 source files.

> 
>> +/*
>> + * Spartan 3 FPGA configuration support for the APF9328 daughter board
>> + */
>> +
>> +#include "fpga.h"
>> +extern int apf9328_init_fpga(void);
>> diff --git a/board/armadeus/apf9328/eeprom.c b/board/armadeus/apf9328/eeprom.c
> 
> It seems to much fo me to add a new file only for a single prototype.
> and it is used only in apf9328fpga.c, as I can see.

this file defines the public prototype of the function implemented in apf9328fpga.c and used in apf9328.c
I agree that it would not make sense to add a header file with prototypes never used anywhere else in the code.

> 
>> +
>> +#include <common.h>
>> +#include <command.h>
>> +#include <dm9000.h>
>> +
>> +static int do_read_dm9000_eeprom(cmd_tbl_t *cmdtp, int flag, int argc,
>> +				 char * const argv[])
>> +{
>> +	unsigned int i;
>> +	u8 data[2];
>> +
>> +	for (i = 0; i < 0x40; i++) {
>> +		if (!(i % 0x10))
>> +			printf("\n%08x:", i);
>> +		dm9000_read_srom_word(i, data);
>> +		printf(" %02x%02x", data[1], data[0]);
>> +	}
> 
> These functions can be factorized. I think the best place is inside the
> DM9000 driver itself, removing them from board code.

Good point. I will propose your recommendation as I am already pushing  a patch  for the DM9000

> 
> 
>> +#include <common.h>
>> +
>> +#if (CONFIG_FPGA)
> 
> #ifdef. We do not want to explicitely set the value for the CONFIG_
> switches. It must be enough to use
> 
> #define CONFIG_FPGA
> 
> in your configuration file,

I am fully in agrement with that. Thx

> 
>> +/*
>> + * nitialize GPIO port B before download
> 
> Initialize

Sure.

> 
>> +extern int fpga_pre_fn(int cookie);
>> +extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
>> +extern int fpga_init_fn(int cookie);
>> +extern int fpga_done_fn(int cookie);
>> +extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
>> +extern int fpga_wr_fn(int assert_write, int flush, int cookie);
> 
> Maybe can you add here the prototy you set in apf9328.h ?

Well, What do you think to add the prototype directly in apf9328.c: extern int apf9328_init_fpga(void);
This will avoid to expose the fpga_xx_fn to apf9328.c that does not care how the firmware is moved from CPU to FPGA
and therefore remove the very small apf9328_fpga.h

> 
>> diff --git a/board/armadeus/apf9328/i2c.c b/board/armadeus/apf9328/i2c.c
> 
> This is a I2C driver, and must be stored into drivers/i2c, not in board
> directory. Please split your patch and push a separate patch only for
> the I2C code, sending it to the I2C maintainer, too.

ok

> 
>> +#include <common.h>
>> +
>> +#ifdef CONFIG_HARD_I2C
>> +
>> +#include <asm/io.h>
>> +#include <asm/arch/imx-regs.h>
>> +#include <i2c.h>
>> +
>> +/*-----------------------------------------------------------------------
>> + * Definitions
>> + */
>> +
>> +#define I2C_ACK		0	/* level to ack a byte */
>> +#define I2C_NOACK	1	/* level to noack a byte */
>> +
>> +/*-----------------------------------------------------------------------
>> + * Local functions
>> + */
>> +
>> +/*-----------------------------------------------------------------------
>> + * START: High -> Low on SDA while SCL is High
>> + * after check for a bus free
>> + */
>> +static void imxi2c_send_start(void)
>> +{
>> +	while (I2SR & I2SR_IBB)
>> +		udelay(1);
> 
> You are using the __REG macros, that are not allowed anymore in new
> u-boot code. Instead of that, please add C structure and use general
> accessors (writel, readl,...) to access to the registers. This comment
> apply to the whole code here.
> 
> 
>> diff --git a/board/armadeus/apf9328/lowlevel_init.S b/board/armadeus/apf9328/lowlevel_init.S
>> new file mode 100644
>> index 0000000..e4c6157
>> --- /dev/null
>> +++ b/board/armadeus/apf9328/lowlevel_init.S
>> @@ -0,0 +1,469 @@
>> +/*
>> + * (C) Copyright 2005-2011 ej Armadeus Project <eric.jarrige@armadeus.org>
>> + * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License
>> + * as published by the Free Software Foundation; either version 2
>> + * of the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
>> + * 02111-1307, USA.
>> + *
>> + */
>> +
>> +#include <config.h>
>> +#include <version.h>
>> +#include <asm/arch/imx-regs.h>
>> +
>> +.globl lowlevel_init
>> +lowlevel_init:
>> +/* Change PERCLK1DIV to 14 ie 14+1 */
>> +	ldr		r0,	=PCDR
>> +	ldr		r1,	=CONFIG_SYS_PCDR_VAL
>> +	str		r1,	[r0]
>> +
>> +/* set MCU PLL Control Register 0 */
>> +
>> +	ldr		r0,	=MPCTL0
>> +	ldr		r1,	=CONFIG_SYS_MPCTL0_VAL
>> +	str		r1,	[r0]
>> +
>> +/* set MCU PLL Control Register 1 */
>> +
>> +	ldr		r0,	=MPCTL1
>> +	ldr		r1,	=CONFIG_SYS_MPCTL1_VAL
>> +	str		r1,	[r0]
>> +
>> +/* set mpll restart bit */
>> +	ldr		r0, =CSCR
>> +	ldr		r1, [r0]
>> +	orr		r1,r1,#(1<<21)
>> +	str		r1, [r0]
>> +
>> +	mov		r2,#0x10
>> +1:
>> +	mov		r3,#0x2000
>> +2:
>> +	subs	r3,r3,#1
>> +	bne		2b
>> +
>> +	subs	r2,r2,#1
>> +	bne		1b
>> +
>> +/* set System PLL Control Register 0 */
>> +
>> +	ldr		r0,	=SPCTL0
>> +	ldr		r1,	=CONFIG_SYS_SPCTL0_VAL
>> +	str		r1,	[r0]
>> +
>> +/* set System PLL Control Register 1 */
>> +
>> +	ldr		r0,	=SPCTL1
>> +	ldr		r1,	=CONFIG_SYS_SPCTL1_VAL
>> +	str		r1,	[r0]
>> +
>> +/* set spll restart bit */
>> +	ldr		r0, =CSCR
>> +	ldr		r1, [r0]
>> +	orr		r1,r1,#(1<<22)
>> +	str		r1, [r0]
>> +
>> +	mov		r2,#0x10
>> +1:
>> +	mov		r3,#0x2000
>> +2:
>> +	subs	r3,r3,#1
>> +	bne		2b
>> +
>> +	subs	r2,r2,#1
>> +	bne		1b
>> +
>> +	ldr		r0,	=CSCR
>> +	ldr		r1,	=CONFIG_SYS_CSCR_VAL
>> +	str		r1,	[r0]
>> +
>> +	ldr		r0,	=GPCR
>> +	ldr		r1,	=CONFIG_SYS_GPCR_VAL
>> +	str		r1,	[r0]
>> +
>> +/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
>> + *this.....
>> + *
>> + * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
>> + * register 1, this stops it using the output of the PLL and thus runs at the
>> + * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
>> + * use the value set in the CM_OSC registers...regardless of what you set it
>> + * too!  Thus, although i thought i was running at 140MHz, i'm actually running
>> + * at 40!..
>> +
>> + * Slapping this into my bootloader does the trick...
>> +
>> + * MRC p15,0,r0,c1,c0,0	 ; read core configuration register
>> + * ORR r0,r0,#0xC0000000	; set asynchronous clocks and not fastbus mode
>> + * MCR p15,0,r0,c1,c0,0	 ; write modified value to core configuration
>> + * register
>> + */
>> +	MRC p15,0,r0,c1,c0,0
>> +	ORR r0,r0,#0xC0000000
>> +	MCR p15,0,r0,c1,c0,0
>> +
>> +/*	ldr		r0,	=GPR(0)
> 
> Do not add dead code, simply drop it.

Sure.

> 
> However, this code is quite the same I can find on other IMX boards. Can
> we factorize it and push it as common code ?

The other boards use hardcoded values that are not compatible with the apf9328 board.
We do not use the same components and so cannot reuse or merge their code.
A factorization would require deep changes in the config files of every board.
For this old CPU there is no chance to convince the maintainers of the other boards to rework their implementation and specifically the boot code in assembly.

On the other hand I am working on some other ARM SOC more recent, so It may worth the pain to invest some effrot of  factorization on modern CPUs.
What is your opinion?

Thanks and best regards,
Eric

[U-Boot] [PATCH 3/9] apf9328: Add Armadeus Project board APF9328

[Stefano Babic]

On 08/12/2011 01:41 AM, Eric Jarrige wrote:

Hi Eric,

>>> +int board_init(void) +{ +	gd->bd->bi_arch_number =
>>> CONFIG_MACH_TYPE;
>> 
>> Is there no MACH_TYPE for this board ? It is uncommon for an ARM
>> board. Should this board run Linux ?
> The MACH_TYPE for this board is 906. This board runs linux and the
> integration in linux is on going.

Ok, I have understood. The only thing you can directly set
MACH_TYPE_APF9328 here. IMHO it is more readable.

>>> +#if (CONFIG_DRIVER_DM9000) +	imx_gpio_mode(GPIO_PORTB | GPIO_DR
>>> | GPIO_IN | 14);
>> 
>> Is there a reason to put this code here and not in board_eth_init ?
>> It is related to Ethernet and I am supposing this setup should be
>> done before dm9000_initialize.
> The idea is to keep the configuration  of the CPU pins at one place
> and to keep the initialization of the ethernet controller in a
> separate function. Here this principle of segregation is not obvious
> as there is only one GPIO pin to configure.

Ok, understood. Maybe it is better to move this kind of initialization
adding a board_early_init_f() function (you need
CONFIG_BOARD_EARLY_INIT_F in your config). This assures that the gpio is
always set before the ethernet is initialized, as I suppose it must be.
Letting in the misc_init() works now, but the order could be changed in
future - the erarly entry point is thought for hardware initialization
before starting the drivers.

>> This function seems to me not very useful. Is it not better to drop
>> it ? It is not strictly required. You set also #undef
>> CONFIG_SHOW_BOOT_PROGRESS in the configuration file.
> Well I choosed to keep it in place in empty state to be the template
> for the final user to add their own debug method if needed. If it is
> an issue I would prefer to define the CONFIG_SHOW_BOOT_PROGRESS in
> the configuration file than removing this empty show_boot_progress as
> the main purpose of the board is education and trainings on embedded
> developments.

However, if the function is empty, the functionality is not shown - it
is quite dead code and does not teach very much. What about to add some
very simple code, as a print() or switching a led, for example, to
indicate which is the goal of the function ?

>> Do you have more as one FPGA on your board ? And if this is true,
>> they share the same firmware ? (I see only one
>> CONFIG_FIRMWARE_ADDR..)
> The APF9328 is a SOM therefore it possible to connect some other FPGA
> to the board. In such a situation the idea is to concatenate all the
> bitstream files in the firmware partition. During the download
> process to the FPGAs the end of one FPGA download starts the download
> of the next one using the FPGA signal PRG_DONE. So that it possible
> to have all firmware in only one partition and save memory space by
> using bitstream files. To be honest I do not remember if someone use
> this feature on this board but that is .

You are the best to say if it is work. Reading the code, I have expected
to see one fpga_load for each defined fpga structure, using offset
inside the loop to pass the correct start and length for each image.

Can you add a comment to explain the behavior and the fact the FPGAs are
concatenated ?


> For the time being this switch applies to this board only. So I did
> not plan to document it in the README. It is not clear for me if I
> should add a documentation in the README since this switch is only
> used in the APF9328 source files.

Then drop all this stuff from the configuration file and rename in a way
it is clear it is specific for your board only. You do not need to
document them in the README, because they are not general CONFIG_ switches.

> Well, What do you think to add the prototype directly in apf9328.c:
> extern int apf9328_init_fpga(void); This will avoid to expose the
> fpga_xx_fn to apf9328.c that does not care how the firmware is moved
> from CPU to FPGA and therefore remove the very small apf9328_fpga.h

Agree.

>> However, this code is quite the same I can find on other IMX
>> boards. Can we factorize it and push it as common code ?
> 
> The other boards use hardcoded values that are not compatible with
> the apf9328 board. We do not use the same components and so cannot
> reuse or merge their code. A factorization would require deep changes
> in the config files of every board. For this old CPU there is no
> chance to convince the maintainers of the other boards to rework
> their implementation and specifically the boot code in assembly.

This is right. These processors are obsolete, there are no more active
development for them. It is enough to see how many patches for theses
processors were sent to the list in the last years (only 1, to fix the
mx1ads board).

> 
> On the other hand I am working on some other ARM SOC more recent, so
> It may worth the pain to invest some effrot of  factorization on
> modern CPUs. What is your opinion?

Of course, this is a must and duplication of code must be avoided.
However, is there a chance to move your assembly file into
arch/arm/cpu/arm920t/imx/, making it available if someone else needs to
use these old-ancient processors ? We do not need to touch the other boards.

I see you load most values from the configuration file, and the code is
straightforward - storing these values into the registers. Any chance ?

Best regards,
Stefano Babic


-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH 3/9] apf9328: Add Armadeus Project board APF9328

[Igor Grinberg]

On 08/12/11 09:49, Stefano Babic wrote:
> On 08/12/2011 01:41 AM, Eric Jarrige wrote:
>
> Hi Eric,
>
>>>> +int board_init(void) +{ +	gd->bd->bi_arch_number =
>>>> CONFIG_MACH_TYPE;
>>> Is there no MACH_TYPE for this board ? It is uncommon for an ARM
>>> board. Should this board run Linux ?
>> The MACH_TYPE for this board is 906. This board runs linux and the
>> integration in linux is on going.
> Ok, I have understood. The only thing you can directly set
> MACH_TYPE_APF9328 here. IMHO it is more readable.

You should not do this here unless you support multiple mach types in a single file.
Please, see the CONFIG_MACH_TYPE in the U-Boot documentation (README file).



-- 
Regards,
Igor.

[U-Boot] [PATCH 3/9] apf9328: Add Armadeus Project board APF9328

[Eric Jarrige]

Hi Higor, Hi Stefano,

On 17 ao?t 2011, at 09:31, Igor Grinberg wrote:

> 
> On 08/12/11 09:49, Stefano Babic wrote:
>> On 08/12/2011 01:41 AM, Eric Jarrige wrote:
>> 
>> Hi Eric,
>> 
>>>>> +int board_init(void) +{ +	gd->bd->bi_arch_number =
>>>>> CONFIG_MACH_TYPE;
>>>> Is there no MACH_TYPE for this board ? It is uncommon for an ARM
>>>> board. Should this board run Linux ?
>>> The MACH_TYPE for this board is 906. This board runs linux and the
>>> integration in linux is on going.
>> Ok, I have understood. The only thing you can directly set
>> MACH_TYPE_APF9328 here. IMHO it is more readable.
> 
> You should not do this here unless you support multiple mach types in a single file.
> Please, see the CONFIG_MACH_TYPE in the U-Boot documentation (README file).

Here is the README sentence regarding CONFIG_MACH_TYPE:

> CONFIG_MACH_TYPE        [relevant for ARM only][mandatory]
>
> This setting is mandatory for all boards that have only one
> machine type and must be used to specify the machine type
> number as it appears in the ARM machine registry
> (see http://www.arm.linux.org.uk/developer/machines/).
> Only boards that have multiple machine types supported
> in a single configuration file and the machine type is
> runtime discoverable, do not have to use this setting.

My understanding is:
1) CONFIG_MACH_TYPE has to be defined in apf9328.h
2) as gd->bd->bi_arch_number is already initialize in board.c i should completely remove this second initialization from the apf9382.c

arch/arm/lib/board.c:
 262 void board_init_f(ulong bootflag)
 ..
 277 
 278 #ifdef CONFIG_MACH_TYPE
 279         gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
 280 #endif 

Please let me know if missed something.

Thx and best regards,
Eric

[U-Boot] [PATCH 3/9] apf9328: Add Armadeus Project board APF9328

[Igor Grinberg]

On 08/18/11 00:58, Eric Jarrige wrote:
> Hi Higor, Hi Stefano,
>
> On 17 ao?t 2011, at 09:31, Igor Grinberg wrote:
>
>> On 08/12/11 09:49, Stefano Babic wrote:
>>> On 08/12/2011 01:41 AM, Eric Jarrige wrote:
>>>
>>> Hi Eric,
>>>
>>>>>> +int board_init(void) +{ +	gd->bd->bi_arch_number =
>>>>>> CONFIG_MACH_TYPE;
>>>>> Is there no MACH_TYPE for this board ? It is uncommon for an ARM
>>>>> board. Should this board run Linux ?
>>>> The MACH_TYPE for this board is 906. This board runs linux and the
>>>> integration in linux is on going.
>>> Ok, I have understood. The only thing you can directly set
>>> MACH_TYPE_APF9328 here. IMHO it is more readable.
>> You should not do this here unless you support multiple mach types in a single file.
>> Please, see the CONFIG_MACH_TYPE in the U-Boot documentation (README file).
> Here is the README sentence regarding CONFIG_MACH_TYPE:
>
>> CONFIG_MACH_TYPE        [relevant for ARM only][mandatory]
>>
>> This setting is mandatory for all boards that have only one
>> machine type and must be used to specify the machine type
>> number as it appears in the ARM machine registry
>> (see http://www.arm.linux.org.uk/developer/machines/).
>> Only boards that have multiple machine types supported
>> in a single configuration file and the machine type is
>> runtime discoverable, do not have to use this setting.
> My understanding is:
> 1) CONFIG_MACH_TYPE has to be defined in apf9328.h
> 2) as gd->bd->bi_arch_number is already initialize in board.c i should completely remove this second initialization from the apf9382.c

Right. Just remove that line.



-- 
Regards,
Igor.

[U-Boot] [PATCH 3/9] apf9328: Add Armadeus Project board APF9328

[Stefano Babic]

On 08/17/2011 11:58 PM, Eric Jarrige wrote:
> Hi Higor, Hi Stefano,
> 

Hi Eric,

> My understanding is:
> 1) CONFIG_MACH_TYPE has to be defined in apf9328.h
> 2) as gd->bd->bi_arch_number is already initialize in board.c i should completely remove this second initialization from the apf9382.c

You are right - drop only the line in apf9382.c

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH 4/9] apf9328: add apf9328 board in Makefile

[Eric Jarrige]

add apf9328 board definition in makefile, MAKEALL and MAINTAINERS list

Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org>
---
 MAINTAINERS |    4 ++++
 MAKEALL     |    1 +
 boards.cfg  |    1 +
 3 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index f895e9a..48807fe 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -686,6 +686,10 @@ Grazvydas Ignotas <notasas@gmail.com>
 
 	omap3_pandora	ARM ARMV7 (OMAP3xx SoC)
 
+Eric Jarrige <eric.jarrige@armadeus.org>
+
+	apf9328		ARM920T (iMX1)
+
 Gary Jennejohn <garyj@denx.de>
 
 	smdk2400	ARM920T
diff --git a/MAKEALL b/MAKEALL
index 3b98f03..f1aa6fc 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -320,6 +320,7 @@ LIST_ARM7="		\
 
 LIST_ARM9="			\
 	a320evb			\
+	apf9328			\
 	ap920t			\
 	ap922_XA10		\
 	ap926ejs		\
diff --git a/boards.cfg b/boards.cfg
index 6827cf3..1b4da54 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -49,6 +49,7 @@ lpc2292sodimm                arm         arm720t     -                   -
 SMN42                        arm         arm720t     -                   siemens        lpc2292
 evb4510                      arm         arm720t     -                   -              s3c4510b
 a320evb                      arm         arm920t     -                   faraday        a320
+apf9328                      arm         arm920t     apf9328             armadeus       imx
 at91rm9200ek                 arm         arm920t     at91rm9200ek        atmel          at91        at91rm9200ek
 at91rm9200ek_ram             arm         arm920t     at91rm9200ek        atmel          at91        at91rm9200ek:RAMBOOT
 eb_cpux9k2                   arm         arm920t     -                   BuS            at91

[U-Boot] [PATCH 5/9] apf9328: add default board configuration file

[Eric Jarrige]

Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org>
---
 include/configs/apf9328.h | 1034 +++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 1034 insertions(+), 0 deletions(-)
 create mode 100644 include/configs/apf9328.h

diff --git a/include/configs/apf9328.h b/include/configs/apf9328.h
new file mode 100644
index 0000000..b609887
--- /dev/null
+++ b/include/configs/apf9328.h
@@ -0,0 +1,1034 @@
+/*
+ * (C) Copyright 2005-2011 ej Armadeus Project <eric.jarrige@armadeus.org>
+ *
+ * Configuration settings for the Armadeus Project motherboard 9328.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * 2005/01/14 Initial version taken from the scb9328 configuration file
+ * 2005/03/10 apf9328 configuration file and trial to improve of
+ *		hardware register control.
+ * 2005/08/16 added APF9328 fpgas and ethernet
+ * 2005/12/02 added filesystem boot over NFS
+ * 2006/11/26 added filesystem boot over NFS
+ * 2010/03/28 U-Boot 2010.03 migration + change timer unit to ms (fixme)
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_ENV_VERSION 	"4.0"
+#define CONFIG_IDENT_STRING	" apf9328 patch 4.0"
+
+#define CONFIG_ARM920T		1	/* this is an ARM920T CPU */
+#define CONFIG_IMX		1	/* in a Motorola MC9328MXL Chip */
+#define CONFIG_apf9328		1	/* on a Armadeus project board */
+#undef	CONFIG_USE_IRQ			/* don't need use IRQ/FIQ */
+#define CONFIG_SYS_DCACHE_OFF		/* fix kernel 2.6.29 boot crash */
+/*
+ * Enable the call to misc_init_r() for miscellaneous platform
+ * dependent initialization.
+ */
+
+#define CONFIG_MISC_INIT_R
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+
+/*
+ * Select serial console configuration
+ */
+#define CONFIG_IMX_SERIAL
+#define CONFIG_IMX_SERIAL1
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_BAUDRATE 	115200
+
+/*
+ * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
+ * neccessary in include/cmd_confdefs.h file. (Un)comment for getting
+ * functionality or size of u-boot code.
+ */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV	/* ask for env variable		*/
+#define CONFIG_CMD_BSP		/* Board Specific functions	*/
+#define CONFIG_CMD_CACHE	/* icache, dcache		*/
+#define CONFIG_CMD_DATE		/* support for RTC, date/time.. */
+#define CONFIG_CMD_DHCP		/* DHCP Support			*/
+#define CONFIG_CMD_DIAG		/* Diagnostics			*/
+#define CONFIG_CMD_EEPROM	/* EEPROM read/write support	*/
+#define CONFIG_CMD_FLASH	/* flinfo, erase, protect	*/
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_IMLS		/* List all found images	*/
+#define CONFIG_CMD_IMMAP	/* IMMR dump support		*/
+#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
+#define CONFIG_CMD_MTDPARTS	/* MTD partition support	*/
+#define CONFIG_CMD_PING		/* ping support			*/
+#define CONFIG_CMD_SAVES	/* save S record dump		*/
+#define CONFIG_CMD_SETEXPR	/* setexpr support		*/
+#define CONFIG_CMD_SNTP		/* SNTP support			*/
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_DNS
+
+#undef CONFIG_DISPLAY_BOARDINFO
+#undef CONFIG_DISPLAY_CPUINFO
+
+/*
+ * Select some advanced features of the commande line parser
+ */
+#define CONFIG_AUTO_COMPLETE 	1	/* Enable auto completion of */
+					/* commands using TAB */
+#define CONFIG_SYS_HUSH_PARSER		1	/* enable the "hush" shell */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "	/* secondary prompt string */
+#define CONFIG_CMDLINE_EDITING	1
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+/*
+ * Boot options. Setting delay to -1 stops autostart count down.
+ */
+#define CONFIG_BOOTDELAY	20
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_BOOTARGS \
+	CONFIG_CONSOLE " root=/dev/mtdblock4 rootfstype=jffs2 " MTDPARTS_DEFAULT
+
+#define CONFIG_CONSOLE	"console=ttySMX0,"MK_STR(CONFIG_BAUDRATE)"n8"
+#define CONFIG_MTDMAP	"physmap-flash.0"
+#define MTDIDS_DEFAULT	"nor0=" CONFIG_MTDMAP
+#define MTDPARTS_DEFAULT "mtdparts=" CONFIG_MTDMAP ":256k(U-boot)ro,"	\
+		"128k(U-boot_env),256k(firmware),2048k(kernel),-(rootfs)"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"env_version="		CONFIG_ENV_VERSION		"\0"	\
+	"fileaddr="		MK_STR(CONFIG_SYS_LOAD_ADDR)	"\0"	\
+	"filesize="		MK_STR(CONFIG_SYS_MONITOR_LEN)	"\0"	\
+	"console="		CONFIG_CONSOLE			"\0"	\
+	"mtdparts="		MTDPARTS_DEFAULT		"\0"	\
+	"partition=		nor0,4\0"				\
+	"uboot_addr="		MK_STR(CONFIG_SYS_MONITOR_BASE)	"\0"	\
+	"uboot_len="		MK_STR(CONFIG_SYS_MONITOR_LEN)	"\0"	\
+	"env_addr="		MK_STR(CONFIG_ENV_ADDR)		"\0"	\
+	"env_len="		MK_STR(CONFIG_ENV_SIZE)		"\0"	\
+	"firmware_addr="	MK_STR(CONFIG_FIRMWARE_ADDR)	"\0"	\
+	"firmware_len="	MK_STR(CONFIG_FIRMWARE_LEN)	"\0"	\
+	"kernel_addr="		MK_STR(CONFIG_KERNEL_ADDR)	"\0"	\
+	"kernel_len="		MK_STR(CONFIG_KERNEL_LEN)	"\0"	\
+	"rootfs_addr="		MK_STR(CONFIG_ROOTFS_ADDR)	"\0"	\
+	"board_name="		MK_STR(CONFIG_BOARD_NAME)	"\0"	\
+	"serverpath="		MK_STR(CONFIG_SRV_PATH)		"\0"	\
+	"ntpserverip=217.147.208.1\0"					\
+	"mmcroot=/dev/mmcblk0p1\0"					\
+	"mmcrootfstype=ext2\0"						\
+	"addnfsargs=setenv bootargs ${bootargs} "			\
+		"root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0"	\
+	"addjffsargs=setenv bootargs ${bootargs} "			\
+		"root=/dev/mtdblock4 rootfstype=jffs2\0"		\
+	"addubifsargs=setenv bootargs ${bootargs} "			\
+		"ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0"	\
+	"addmmcargs=setenv bootargs ${bootargs} "			\
+		"root=${mmcroot} rootfstype=${mmcrootfstype}\0"		\
+	"addipargs=setenv bootargs ${bootargs} "			\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:"	\
+		"${hostname}::off \0"					\
+	"nfsboot=setenv bootargs ${console} ${mtdparts};"		\
+		"run addnfsargs addipargs; bootm ${kernel_addr}\0"	\
+	"jffsboot=setenv bootargs ${console} ${mtdparts};"		\
+		"run addjffsargs addipargs; bootm ${kernel_addr}\0"	\
+	"ubifsboot=setenv bootargs ${console} ${mtdparts};"		\
+		"run addubifsargs addipargs; bootm ${kernel_addr}\0"	\
+	"mmcboot=setenv bootargs ${console} ${mtdparts};"		\
+		"run addmmcargs addipargs; bootm ${kernel_addr}\0"	\
+	"firmware_autoload=0\0"						\
+	"flash_uboot=protect off ${uboot_addr} +${uboot_len};"		\
+		"echo Erasing FLASH;"					\
+		"era ${uboot_addr} +${uboot_len};"			\
+		"if cp.b ${fileaddr} ${uboot_addr} ${filesize};"	\
+			"then protect on ${uboot_addr} +${uboot_len};"	\
+				"echo Flashing of uboot succeed;"	\
+			"else echo Flashing of uboot failed;"		\
+		"fi; \0"						\
+	"flash_firmware=echo Erasing FLASH;"				\
+		"era ${firmware_addr} +${firmware_len};"		\
+		"if cp.b ${fileaddr} ${firmware_addr} ${filesize} ;"	\
+			"then echo Flashing of Firmware succeed;"	\
+			"else echo Flashing of Firmware failed;"	\
+		"fi\0"							\
+	"flash_kernel=echo Erasing FLASH;"				\
+		"era ${kernel_addr} +${kernel_len};"			\
+		"if cp.b ${fileaddr} ${kernel_addr} ${filesize} ;"	\
+			"then echo Flashing of kernel succeed;"		\
+			"else echo Flashing of kernel failed;"		\
+		"fi\0"							\
+	"flash_rootfs=echo Erasing FLASH;"				\
+		"era nor0,4;"			\
+		"if cp.b ${fileaddr} ${rootfs_addr} ${filesize};"	\
+			"then echo Flashing of rootfs succeed;"		\
+			"else echo Flashing of rootfs failed;"		\
+		"fi\0"							\
+	"flash_reset_env=protect off ${env_addr} +${env_len};"		\
+		"era ${env_addr} +${env_len};"				\
+		"echo Erasing of flash environment variables done!\0"	\
+	"download_uboot=tftpboot ${loadaddr} "				\
+		" ${serverpath}${board_name}-u-boot.bin\0"		\
+	"download_kernel=tftpboot ${loadaddr} "				\
+		" ${serverpath}${board_name}-linux.bin\0"		\
+	"download_rootfs=tftpboot ${loadaddr} "				\
+		" ${serverpath}${board_name}-rootfs.jffs2\0"		\
+	"update_uboot=run download_uboot flash_uboot\0"			\
+	"update_kernel=run download_kernel flash_kernel\0"		\
+	"update_rootfs=run download_rootfs flash_rootfs\0"		\
+	"update_all=run download_kernel flash_kernel download_rootfs "	\
+		"flash_rootfs download_uboot flash_uboot\0"		\
+	"unlock_regs=mw 00200008 0; mw 00210008 0\0"			\
+
+#define CONFIG_BOOTCOMMAND	"run jffsboot"
+#define CONFIG_SYS_AUTOLOAD		"no"
+
+#define CONFIG_MACH_TYPE MACH_TYPE_APF9328
+#define CONFIG_BOOT_PARAMS_ADDR	0x08000100
+
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_ETHADDR
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.000.10
+#define CONFIG_BOARD_NAME	"apf9328"
+#define CONFIG_HOSTNAME		"apf9328"
+#define CONFIG_GATEWAYIP	192.168.000.1
+#define CONFIG_SERVERIP		192.168.000.2
+#define CONFIG_SRV_PATH		""
+#define CONFIG_ROOTPATH		"/tftpboot/apf9328-root"
+
+/*
+ * General options for u-boot. Modify to save memory foot print
+ */
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT		"BIOS> "	/* prompt string */
+#define CONFIG_SYS_CBSIZE		2048		/* console I/O buffer */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16		/* max command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* bootargs buf size*/
+
+#define CONFIG_SYS_MEMTEST_START	0x08000000	/* memtest test area */
+#define CONFIG_SYS_MEMTEST_END		0x08700000
+
+#define CONFIG_SYS_HZ			1000000l	/* incrementer freq */
+
+/*
+ * Definitions related to passing arguments to kernel.
+ */
+
+#define CONFIG_CMDLINE_TAG	1	/* send commandline to Kernel	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1	/* send memory definition to kernel */
+#define CONFIG_INITRD_TAG	1	/* send initrd params	*/
+
+/*
+ * Malloc pool need to host env + 128 Kb reserve for other allocations.
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128<<10))
+
+#define CONFIG_STACKSIZE	(120<<10)	/* stack size	*/
+
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4<<10)	/* IRQ stack	*/
+#define CONFIG_STACKSIZE_FIQ	(4<<10)	/* FIQ stack	*/
+#endif
+
+/*
+* Clocks configuration
+*/
+/*
+ * PLL configuration
+ *
+ * f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
+ * f_ref=16,777216MHz
+ * 32768 Hz xtal
+ * 0x07B32DA5: 192.0000173
+ * 0x002a141f: 191,9944MHz
+ * 0x040b2007: 144MHz
+ * 0x0FB32DA5: 96.00000864 MHz
+ * 0x042a141f: 96MHz
+ * 0x0811140d: 64MHz
+ * 0x040e200e: 150MHz
+ * 0x00321431: 200MHz
+ *
+ *16 MHz xtal
+ * 0x08001800: 64MHz mit 16er Quarz
+ * 0x04001800: 96MHz mit 16er Quarz
+ * 0x04002400: 144MHz mit 16er Quarz
+ *
+ * 31	|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
+ *	|XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------|
+ */
+
+#define CONFIG_SYS_OSC32	32768	/* 32768 or 32000 Hz crystal */
+#undef	CONFIG_SYS_OSC16	/* there is no external 16MHz external clock */
+
+/* MPU CLOCK source before PLL	(should be named CONFIG_SYS_SYS_CLK_FREQ) */
+#define CONFIG_SYS_CLK_FREQ	(512*CONFIG_SYS_OSC32)
+#define CONFIG_SYS_MPCTL0_VAL		0x07B32DA5	/* 192.000017 MHz */
+#define CONFIG_SYS_MPCTL1_VAL		0
+
+/* system clock source before PLL (should be named CONFIG_SYS_SYSPLL_CLK_FREQ)*/
+#ifndef CONFIG_SYS_OSC16
+#define CONFIG_SYSPLL_CLK_FREQ		(512*CONFIG_SYS_OSC32)
+#if (CONFIG_SYS_OSC32 == 32000)
+#define CONFIG_SYS_SPCTL0_VAL		0x043F1437	/* 96 MHz */
+#define CONFIG_SYS_SPCTL1_VAL		0
+#define CONFIG_SYS_FREQ			96	/* MHz */
+#else /* CONFIG_SYS_OSC32 == 32768 */
+#define CONFIG_SYS_SPCTL0_VAL		0x0FB32DA5	/* 96.000009 MHz */
+#define CONFIG_SYS_SPCTL1_VAL		0
+#define CONFIG_SYS_FREQ			96	/* MHz */
+#endif /* CONFIG_SYS_OSC32 */
+#else /* CONFIG_SYS_OSC16 in use */
+#define CONFIG_SYSPLL_CLK_FREQ		CONFIG_SYS_OSC16
+#define CONFIG_SYS_SPCTL0_VAL		0x04001401	/* 96 MHz */
+#define CONFIG_SYS_SPCTL1_VAL		0x0C000040
+#define CONFIG_SYS_FREQ			96	/* MHz */
+#endif /* CONFIG_SYS_OSC16 */
+
+/* external bus frequency (have to be a CONFIG_SYS_FREQ ratio) */
+#define CONFIG_SYS_BUS_FREQ 	96	/* 96|48... MHz (BCLOCK and HCLOCK) */
+#define CONFIG_USB_FREQ		48	/* 48 MHz */
+#define CONFIG_PERIF1_FREQ	16	/* 16 MHz UART, Timer PWM */
+#define CONFIG_PERIF2_FREQ 	48	/* 48 MHz LCD SD SPI */
+#define CONFIG_PERIF3_FREQ	16	/* 16 MHz SSI */
+
+/*
+ * SDRAM definition parameter
+ */
+/* we have and support only 1 bank of SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_SYS_SDRAM_MBYTE_SYZE 16
+
+/*
+ * CONFIG_SYS_SDRAM_NUM_COL 8, 9, 10 or 11 column address bits
+ * CONFIG_SYS_SDRAM_NUM_ROW 11, 12 or 13 row address bits
+ * CONFIG_SYS_SDRAM_REFRESH 0=OFF 1=2048 2=4096 3=8192 refresh
+ * CONFIG_SYS_SDRAM_CLOCK_CYCLE_CL_1 X ns clock cycle time when CL=1
+ * CONFIG_SYS_SDRAM_ROW_PRECHARGE_DELAY X ns SRP
+ * CONFIG_SYS_SDRAM_ROW_2_COL_DELAY X ns SRCD
+ * CONFIG_SYS_SDRAM_ROW_CYCLE_DELAY X ns SRC
+ * CONFIG_SYS_SDRAM_BURST_LENGTH 2^N BYTES (N=0..3)
+ * CONFIG_SYS_SDRAM_SINGLE_ACCESS 1= single access; 0 = Burst mode
+ */
+
+#if (CONFIG_SYS_SDRAM_MBYTE_SYZE == 8)
+/* micron 8MB */
+#define CONFIG_SYS_SDRAM_1_BASE	0x08000000	/* SDRAM bank #1 32bits */
+#define CONFIG_SYS_SDRAM_1_SIZE	0x00800000	/* 8 MB	*/
+#define CONFIG_SYS_SDRAM_NUM_COL		8
+#define CONFIG_SYS_SDRAM_NUM_ROW		11
+#define CONFIG_SYS_SDRAM_REFRESH		2
+#define CONFIG_SYS_SDRAM_CLOCK_CYCLE_CL_1	20
+#define CONFIG_SYS_SDRAM_ROW_PRECHARGE_DELAY	20
+#define CONFIG_SYS_SDRAM_ROW_2_COL_DELAY	20
+#define CONFIG_SYS_SDRAM_ROW_CYCLE_DELAY	70
+#define CONFIG_SYS_SDRAM_BURST_LENGTH		3
+#define CONFIG_SYS_SDRAM_SINGLE_ACCESS		0
+#endif
+
+#if (CONFIG_SYS_SDRAM_MBYTE_SYZE == 16)
+/* micron 16MB */
+#define CONFIG_SYS_SDRAM_1_BASE	0x08000000	/* SDRAM bank #1 32bits */
+#define CONFIG_SYS_SDRAM_1_SIZE	0x01000000	/* 16 MB */
+#define CONFIG_SYS_SDRAM_NUM_COL		8
+#define CONFIG_SYS_SDRAM_NUM_ROW		12
+#define CONFIG_SYS_SDRAM_REFRESH		2
+#define CONFIG_SYS_SDRAM_CLOCK_CYCLE_CL_1	20
+#define CONFIG_SYS_SDRAM_ROW_PRECHARGE_DELAY	20
+#define CONFIG_SYS_SDRAM_ROW_2_COL_DELAY	20
+#define CONFIG_SYS_SDRAM_ROW_CYCLE_DELAY	70
+#define CONFIG_SYS_SDRAM_BURST_LENGTH		3
+#define CONFIG_SYS_SDRAM_SINGLE_ACCESS		0
+#endif
+
+#if (CONFIG_SYS_SDRAM_MBYTE_SYZE == 32)
+/* micron 32MB */
+#define CONFIG_SYS_SDRAM_1_BASE	0x08000000	/* SDRAM bank #1 32bits */
+#define CONFIG_SYS_SDRAM_1_SIZE	0x02000000	/* 32 MB */
+#define CONFIG_SYS_SDRAM_NUM_COL		9
+#define CONFIG_SYS_SDRAM_NUM_ROW		12
+#define CONFIG_SYS_SDRAM_REFRESH		2
+#define CONFIG_SYS_SDRAM_CLOCK_CYCLE_CL_1	20
+#define CONFIG_SYS_SDRAM_ROW_PRECHARGE_DELAY	20
+#define CONFIG_SYS_SDRAM_ROW_2_COL_DELAY	20
+#define CONFIG_SYS_SDRAM_ROW_CYCLE_DELAY	70
+#define CONFIG_SYS_SDRAM_BURST_LENGTH		3
+#define CONFIG_SYS_SDRAM_SINGLE_ACCESS		0
+#endif
+
+#if (CONFIG_SYS_SDRAM_MBYTE_SYZE == 64)
+/* micron 64MB */
+#define CONFIG_SYS_SDRAM_1_BASE	0x08000000	/* SDRAM bank #1 32bits */
+#define CONFIG_SYS_SDRAM_1_SIZE	0x04000000	/* 64 MB */
+#define CONFIG_SYS_SDRAM_NUM_COL		9
+#define CONFIG_SYS_SDRAM_NUM_ROW		13
+#define CONFIG_SYS_SDRAM_REFRESH		3
+#define CONFIG_SYS_SDRAM_CLOCK_CYCLE_CL_1	20
+#define CONFIG_SYS_SDRAM_ROW_PRECHARGE_DELAY	20
+#define CONFIG_SYS_SDRAM_ROW_2_COL_DELAY	20
+#define CONFIG_SYS_SDRAM_ROW_CYCLE_DELAY	70
+#define CONFIG_SYS_SDRAM_BURST_LENGTH		3
+#define CONFIG_SYS_SDRAM_SINGLE_ACCESS		0
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE	CONFIG_SYS_SDRAM_1_BASE
+
+/* lowlevel_linit copy U-Boot at CONFIG_SYS_INIT_SP_ADDR  (here in RAM) */
+/* making u-boot runnable from flash and also RAM that is usefull to boot */
+/* from serial port and from flash with only one version of U-Boot */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0x08000000
+#endif
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE	\
+		+ CONFIG_SYS_SDRAM_1_SIZE - 0x0100000)
+
+/*
+ * Configuration for a maximum 32MB of FLASH memory
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* FLASH banks count */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* number of sector in a bank */
+#define CONFIG_SYS_FLASH_BASE		0x10000000 /* location of flash memory*/
+
+/* This should be defined if CFI FLASH device is present. */
+#define	CONFIG_SYS_FLASH_CFI			1
+#define CONFIG_FLASH_CFI_DRIVER			1
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 	1
+#define CONFIG_SYS_FLASH_PROTECTION		1
+#define CONFIG_SYS_DIRECT_FLASH_TFTP		1
+#define CONFIG_FLASH_SHOW_PROGRESS		45
+/*
+ * This is setting for JFFS2 support in u-boot.
+ * NOTE: Enable CONFIG_SYS_CMD_JFFS2 for JFFS2 support.
+ */
+#define CONFIG_SYS_JFFS_CUSTOM_PART
+
+/*
+ * Environment setup. Definitions of monitor location and size with
+ * definition of environment setup ends up in 2 possibilities.
+ * 1. Embeded environment - in u-boot code is space for environment
+ * 2. Environment is read from predefined sector of flash
+ * Right now we support 2. possiblity, but expecting no env placed
+ * on mentioned address right now. This also needs to provide whole
+ * sector for it - for us 256Kb is really waste of memory. U-boot uses
+ * default env. and until kernel parameters could be sent to kernel
+ * env. has no sense to us.
+ */
+
+#define	CONFIG_SYS_MONITOR_BASE	0x10000000
+#define	CONFIG_SYS_MONITOR_LEN	0x00040000	/* 256kB ( 2 flash sector ) */
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_ADDR		0x10040000	/* absolute address for now */
+#define	CONFIG_ENV_SIZE		0x00020000
+#define	CONFIG_ENV_SECT_SIZE	0x00020000
+#define	CONFIG_ENV_OVERWRITE	1		/* env is writable now */
+#define	CONFIG_FIRMWARE_ADDR	0x10060000
+#define	CONFIG_FIRMWARE_LEN	0x00040000	/* 256kB ( 2 flash sector ) */
+#define	CONFIG_KERNEL_ADDR	0x100A0000
+#define	CONFIG_KERNEL_LEN	0x00200000	/* 2MB */
+#define	CONFIG_ROOTFS_ADDR	0x102A0000
+#define	CONFIG_ROOTFS_LEN	/* entire flash if not specified */
+
+/*
+ * Default load address for user programs and kernel
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x08000000
+#define	CONFIG_LOADADDR			0x08000000
+#define CONFIG_SYS_TFTP_LOADADDR	0x08000000
+/*
+ * Hardware drivers
+ */
+
+/* DM9000 ethernet chipset assigned to CS4 */
+/* For the apf board DM9000 base is 0x15C00000 and data is base+2	*/
+/* For the apm board DM9000 base is 0x15C3FFFC and data is base+4	*/
+#define CONFIG_DRIVER_DM9000	1
+#define CONFIG_DM9000_BASE	0x15C00000
+#define DM9000_IO		CONFIG_DM9000_BASE
+#define DM9000_DATA		(CONFIG_DM9000_BASE+2)
+#define CONFIG_NET_MULTI
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+#define CONFIG_FPGA_COUNT	1
+/* only digital value for CONFIG_FPGA is supported (investigation pending) */
+#define CONFIG_FPGA		0x801	/* CONFIG_SYS_XILINX_SPARTAN3 */
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_SPARTAN3
+#define CONFIG_SYS_FPGA_WAIT		250
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_CHECK_CTRLC
+#define CONFIG_SYS_FPGA_CHECK_ERROR
+
+/* FPGA program pin configuration */
+#define CONFIG_SYS_FPGA_PRG	(GPIO_PORTB | 18) /* prog pin (SSI output) */
+#define CONFIG_SYS_FPGA_CLK	(GPIO_PORTB | 19) /* clk pin (SSI output) */
+#define CONFIG_SYS_FPGA_DATA	(GPIO_PORTB | 17) /* data pin (SSI output) */
+#define CONFIG_SYS_FPGA_INIT	(GPIO_PORTB | 15) /* init pin (SSI input) */
+#define CONFIG_SYS_FPGA_DONE	(GPIO_PORTB | 16) /* done pin (SSI input) */
+
+/*
+ * I2C bus
+ */
+
+#define	CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
+
+#define CONFIG_SYS_I2C_SPEED		400000	/* 400 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM 24LC256	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2	/* bytes of address	*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x00*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10 /* takes up to 10 msec */
+
+#define CONFIG_RTC_DS1374
+/*#define CONFIG_MMC		1
+*/
+/*
+ * External interfaces module
+ *
+ * CSxU_VAL:
+ * 63|    x    |x|x x|x x x x|x x| x | x  |x x x x|48
+ *   |DTACK_SEL|0|BCD|  BCS  |PSZ|PME|SYNC|  DOL  |
+ *
+ * 47| x x  | x x x x x x | x | x x x x | x x x x |32
+ *   | CNC  |     WSC     | 0 |   WWS   |   EDC   |
+ *
+ * CSxL_VAL:
+ * 31|  x x x x  | x x x x  | x x x x  | x x x x  |24
+ *   |    OEA    |   OEN    |   WEA    |   WEN    |
+ * 23|x x x x| x | x x x | x x  x x |x x| x |  x  | 0
+ *   |  CSA  |EBC|  DSZ  | 0|SP|0|WP|0 0|PA |CSEN |
+ */
+
+/* CS0 configuration for flash memory Micron MT28F128J3-150 */
+#define CONFIG_SYS_CS0_CHIP_SELECT_ENABLE	1 /* 1 : enable CS0 */
+#define CONFIG_SYS_CS0_DATA_PORT_SIZE		0x5 /* 5=16 bits on D[15:0] */
+					/* 3=8bits on D[7:0] 6=32 bits..*/
+#define CONFIG_SYS_CS0_SUPERVISOR_PROTECT	0 /* 1: user access prohibited*/
+#define CONFIG_SYS_CS0_WRITE_PROTECT		0 /* 1: write prohibited*/
+#define CONFIG_SYS_CS0_EB_SIGNAL_CONTROL_WRITE	1 /* 1 EB is as write signal */
+#define CONFIG_SYS_CS0_READ_CYC_LGTH		150	/* ns */
+#define CONFIG_SYS_CS0_OE_ASSERT_DLY		0	/* ns */
+#define CONFIG_SYS_CS0_OE_NEG_DLY		0	/* ns */
+
+#define CONFIG_SYS_CS0_CS_NEG_LGTH 	0	/* ns CS HIGH to CS LOW : tCWH*/
+#define CONFIG_SYS_CS0_XTRA_DEAD_CYC	35	/* ns from CS HIGH to tristate*/
+
+#define CONFIG_SYS_CS0_WRITE_XTRA_LGTH		0	/* ns */
+#define CONFIG_SYS_CS0_EB_ASSERT_DLY		0	/* ns */
+#define CONFIG_SYS_CS0_EB_NEG_DLY		0	/* ns */
+#define CONFIG_SYS_CS0_CS_ASSERT_NEG_DLY	0	/* ns */
+
+#define CONFIG_SYS_CS0_SYNC_ENABLE		1 /* enable sync burst mode */
+#define CONFIG_SYS_CS0_SYNC_PAGE_MODE_EMUL	1 /* enable page mode emulation*/
+#define CONFIG_SYS_CS0_SYNC_PAGE_SIZE		0 /* 4 words page size (8bytes)*/
+#define CONFIG_SYS_CS0_SYNC_BURST_CLK_START	0 /* 0 ns burst clock delay */
+#define CONFIG_SYS_CS0_SYNC_BURST_CLK_DIV	0 /* 0 : divider is 1 */
+#define CONFIG_SYS_CS0_SYNC_DAT_OUT_LGTH	25	/* ns */
+
+/* CS1 configuration for */
+#define CONFIG_SYS_CS1_CHIP_SELECT_ENABLE	1 /* 1 : enable CS0 peripherals */
+#define CONFIG_SYS_CS1_PIN_ASSERT		0 /* chip select pin state when */
+						/* chip select disabled */
+#define CONFIG_SYS_CS1_DATA_PORT_SIZE		0x5 /* 5=16 bits on D[15:0] pins */
+						/* 3=8bits on D[7:0] 6=32 bits.. */
+#define CONFIG_SYS_CS1_SUPERVISOR_PROTECT	0 /* 1 : user mode access prohibited */
+#define CONFIG_SYS_CS1_WRITE_PROTECT		0 /* 1 : write access prohibited */
+#define CONFIG_SYS_CS1_EB_SIGNAL_CONTROL_WRITE	1 /* 1 when EB is used as write signal */
+
+#define CONFIG_SYS_CS1_READ_CYC_LGTH		50	/* ns */
+#define CONFIG_SYS_CS1_OE_ASSERT_DLY		0	/* ns */
+#define CONFIG_SYS_CS1_OE_NEG_DLY		0	/* ns */
+
+#define CONFIG_SYS_CS1_CS_NEG_LGTH 	0	/* max 30 ns CS HIGH to CS LOW at 100MHz */
+#define CONFIG_SYS_CS1_XTRA_DEAD_CYC	0	/* ns from CS HIGH to tristate bus */
+
+#define CONFIG_SYS_CS1_WRITE_XTRA_LGTH		0	/* ns */
+#define CONFIG_SYS_CS1_EB_ASSERT_DLY		0	/* ns */
+#define CONFIG_SYS_CS1_EB_NEG_DLY		0	/* ns */
+#define CONFIG_SYS_CS1_CS_ASSERT_NEG_DLY	0	/* ns */
+
+#define CONFIG_SYS_CS1_SYNC_ENABLE		0 /* enable synchronous burst mode */
+#define CONFIG_SYS_CS1_SYNC_PAGE_MODE_EMUL	0 /* enable page mode emulation */
+#define CONFIG_SYS_CS1_SYNC_PAGE_SIZE		0 /* 4 words page size (8bytes) */
+#define CONFIG_SYS_CS1_SYNC_BURST_CLK_START	0 /* 0 ns burst clock delay */
+#define CONFIG_SYS_CS1_SYNC_BURST_CLK_DIV	0 /* 0 : divider is 1 */
+#define CONFIG_SYS_CS1_SYNC_DAT_OUT_LGTH	0 /* ns */
+
+/* CS2 configuration for */
+#define CONFIG_SYS_CS2_CHIP_SELECT_ENABLE	0 /* 1 : enable CS0 peripherals */
+#define CONFIG_SYS_CS2_PIN_ASSERT		0 /* chip select pin state when */
+						/*chip select disabled */
+#define CONFIG_SYS_CS2_DATA_PORT_SIZE		0x5 /* 5=16 bits on D[15:0] pins */
+						/* 3=8bits on D[7:0] 6=32 bits.. */
+#define CONFIG_SYS_CS2_SUPERVISOR_PROTECT	0 /* 1 : user mode access prohibited */
+#define CONFIG_SYS_CS2_WRITE_PROTECT		0 /* 1 : write access prohibited */
+#define CONFIG_SYS_CS2_EB_SIGNAL_CONTROL_WRITE	1 /* 1 when EB is used as write signal */
+
+#define CONFIG_SYS_CS2_READ_CYC_LGTH		0	/* ns */
+#define CONFIG_SYS_CS2_OE_ASSERT_DLY		0	/* ns */
+#define CONFIG_SYS_CS2_OE_NEG_DLY		0	/* ns */
+
+#define CONFIG_SYS_CS2_CS_NEG_LGTH 	0	/* max 30 ns CS HIGH to CS LOW at 100MHz */
+#define CONFIG_SYS_CS2_XTRA_DEAD_CYC	0	/* ns from CS HIGH to tristate bus */
+
+#define CONFIG_SYS_CS2_WRITE_XTRA_LGTH		0	/* ns */
+#define CONFIG_SYS_CS2_EB_ASSERT_DLY		0	/* ns */
+#define CONFIG_SYS_CS2_EB_NEG_DLY		0	/* ns */
+#define CONFIG_SYS_CS2_CS_ASSERT_NEG_DLY	0	/* ns */
+
+#define CONFIG_SYS_CS2_SYNC_ENABLE		0 /* enable synchronous burst mode */
+#define CONFIG_SYS_CS2_SYNC_PAGE_MODE_EMUL	0 /* enable page mode emulation */
+#define CONFIG_SYS_CS2_SYNC_PAGE_SIZE		0 /* 4 words page size (8bytes) */
+#define CONFIG_SYS_CS2_SYNC_BURST_CLK_START	0 /* 0 ns burst clock delay */
+#define CONFIG_SYS_CS2_SYNC_BURST_CLK_DIV	0 /* 0 : divider is 1 */
+#define CONFIG_SYS_CS2_SYNC_DAT_OUT_LGTH	0 /* ns */
+
+/* CS3 configuration for ISP1760 */
+#define CONFIG_SYS_CS3_CHIP_SELECT_ENABLE	1 /* 1 : enable CS0 peripherals */
+#define CONFIG_SYS_CS3_PIN_ASSERT		0 /* chip select pin state when */
+						/* chip select disabled */
+#define CONFIG_SYS_CS3_DATA_PORT_SIZE		0x5 /* 5=16 bits on D[15:0] pins */
+						/* 3=8bits on D[7:0] 6=32 bits.. */
+#define CONFIG_SYS_CS3_SUPERVISOR_PROTECT	0 /* 1: user mode access prohibited */
+#define CONFIG_SYS_CS3_WRITE_PROTECT		0 /* 1: write access prohibited */
+#define CONFIG_SYS_CS3_EB_SIGNAL_CONTROL_WRITE	1 /* 1 when EB is used as write signal */
+
+#define CONFIG_SYS_CS3_READ_CYC_LGTH		110	/* ns */
+#define CONFIG_SYS_CS3_OE_ASSERT_DLY		45	/* ns */
+#define CONFIG_SYS_CS3_OE_NEG_DLY		40	/* ns */
+
+#define CONFIG_SYS_CS3_CS_NEG_LGTH 	30	/* max 30 ns CS HIGH to CS LOW at 100MHz */
+#define CONFIG_SYS_CS3_XTRA_DEAD_CYC	0	/* ns from CS HIGH to tristate bus */
+
+#define CONFIG_SYS_CS3_WRITE_XTRA_LGTH		0	/* ns */
+#define CONFIG_SYS_CS3_EB_ASSERT_DLY		45	/* ns */
+#define CONFIG_SYS_CS3_EB_NEG_DLY		45	/* ns */
+#define CONFIG_SYS_CS3_CS_ASSERT_NEG_DLY	35	/* ns */
+
+#define CONFIG_SYS_CS3_SYNC_ENABLE		0 /* enable synchronous burst mode */
+#define CONFIG_SYS_CS3_SYNC_PAGE_MODE_EMUL	0 /* enable page mode emulation */
+#define CONFIG_SYS_CS3_SYNC_PAGE_SIZE		0 /* 4 words page size (8bytes) */
+#define CONFIG_SYS_CS3_SYNC_BURST_CLK_START	0 /* 0 ns burst clock delay */
+#define CONFIG_SYS_CS3_SYNC_BURST_CLK_DIV	0 /* 0 : divider is 1 */
+#define CONFIG_SYS_CS3_SYNC_DAT_OUT_LGTH	0 /* ns */
+
+/* CS4 configuration for DM9000 ethernet chipset */
+#define CONFIG_SYS_CS4_CHIP_SELECT_ENABLE	1 /* 1 : enable CS0 peripherals */
+#define CONFIG_SYS_CS4_PIN_ASSERT		0 /* chip select pin state when */
+						/* chip select disabled */
+#define CONFIG_SYS_CS4_DATA_PORT_SIZE		0x5 /* 5=16 bits on D[15:0] pins */
+						/* 3=8bits on D[7:0] 6=32 bits.. */
+#define CONFIG_SYS_CS4_SUPERVISOR_PROTECT	0 /* 1 : user mode access prohibited */
+#define CONFIG_SYS_CS4_WRITE_PROTECT		0 /* 1 : write access prohibited */
+#define CONFIG_SYS_CS4_EB_SIGNAL_CONTROL_WRITE	1 /* 1 when EB is used as write signal */
+
+#define CONFIG_SYS_CS4_READ_CYC_LGTH		72 /* ns */
+#define CONFIG_SYS_CS4_OE_ASSERT_DLY		5 /* ns */
+#define CONFIG_SYS_CS4_OE_NEG_DLY		45 /* ns */
+
+#define CONFIG_SYS_CS4_CS_NEG_LGTH 	30	/* max 30 ns CS HIGH to CS LOW at 100MHz */
+#define CONFIG_SYS_CS4_XTRA_DEAD_CYC	0	/* ns from CS HIGH to tristate bus */
+
+#define CONFIG_SYS_CS4_WRITE_XTRA_LGTH		0	/* ns */
+#define CONFIG_SYS_CS4_EB_ASSERT_DLY		5	/* ns */
+#define CONFIG_SYS_CS4_EB_NEG_DLY		45	/* ns */
+#define CONFIG_SYS_CS4_CS_ASSERT_NEG_DLY	0	/* ns */
+
+#define CONFIG_SYS_CS4_SYNC_ENABLE		0 /* enable synchronous burst mode */
+#define CONFIG_SYS_CS4_SYNC_PAGE_MODE_EMUL	0 /* enable page mode emulation */
+#define CONFIG_SYS_CS4_SYNC_PAGE_SIZE		0 /* 4 words page size (8bytes) */
+#define CONFIG_SYS_CS4_SYNC_BURST_CLK_START	0 /* 0 ns burst clock delay */
+#define CONFIG_SYS_CS4_SYNC_BURST_CLK_DIV	0 /* 0 : divider is 1 */
+#define CONFIG_SYS_CS4_SYNC_DAT_OUT_LGTH	0 /* ns */
+
+/* CS5 configuration for */
+#define CONFIG_SYS_CS5_CHIP_SELECT_ENABLE	1 /* 1 : enable CS0 peripherals */
+#define CONFIG_SYS_CS5_PIN_ASSERT		0 /* chip select pin state when */
+						/* chip select disabled */
+#define CONFIG_SYS_CS5_DATA_PORT_SIZE		0x5 /* 5=16 bits on D[15:0] pins */
+						/* 3=8bits on D[7:0] 6=32 bits.. */
+#define CONFIG_SYS_CS5_SUPERVISOR_PROTECT	0 /* 1: user mode access prohibited */
+#define CONFIG_SYS_CS5_WRITE_PROTECT		0 /* 1 : write access prohibited */
+#define CONFIG_SYS_CS5_EB_SIGNAL_CONTROL_WRITE	1 /* 1 when EB is used as write signal */
+#define CONFIG_SYS_CS5_DTACK_SELECT		1 /* Activate DTACK fonction */
+						/* (asynchrone bus) */
+
+#define CONFIG_SYS_CS5_READ_CYC_LGTH		-1 /* ns or -1 to DTACK function */
+#define CONFIG_SYS_CS5_OE_ASSERT_DLY		10	/* ns */
+#define CONFIG_SYS_CS5_OE_NEG_DLY		10	/* ns */
+
+#define CONFIG_SYS_CS5_CS_NEG_LGTH 		10 /* max 30 ns CS HIGH to CS LOW@100MHz */
+#define CONFIG_SYS_CS5_XTRA_DEAD_CYC		0 /* ns from CS HIGH to tristate bus */
+
+#define CONFIG_SYS_CS5_WRITE_XTRA_LGTH		0	/* ns */
+#define CONFIG_SYS_CS5_EB_ASSERT_DLY		10	/* ns */
+#define CONFIG_SYS_CS5_EB_NEG_DLY		10	/* ns */
+#define CONFIG_SYS_CS5_CS_ASSERT_NEG_DLY	0	/* ns */
+
+#define CONFIG_SYS_CS5_SYNC_ENABLE		0 /* enable synchron burst mode */
+#define CONFIG_SYS_CS5_SYNC_PAGE_MODE_EMUL	0 /* enable page mode emulation */
+#define CONFIG_SYS_CS5_SYNC_PAGE_SIZE		0 /* 4 words page size (8bytes) */
+#define CONFIG_SYS_CS5_SYNC_BURST_CLK_START	0 /* 0 ns burst clock delay */
+#define CONFIG_SYS_CS5_SYNC_BURST_CLK_DIV	0 /* 0 : divider is 1 */
+#define CONFIG_SYS_CS5_SYNC_DAT_OUT_LGTH	0	/* ns */
+
+/*
+ * Default configuration for GPIOs and peripherals
+ */
+#define CONFIG_SYS_DDIR_A_VAL		0x00000000
+#define CONFIG_SYS_OCR1_A_VAL		0x00000000
+#define CONFIG_SYS_OCR2_A_VAL		0x00000000
+#define CONFIG_SYS_ICFA1_A_VAL		0xFFFFFFFF
+#define CONFIG_SYS_ICFA2_A_VAL		0xFFFFFFFF
+#define CONFIG_SYS_ICFB1_A_VAL		0xFFFFFFFF
+#define CONFIG_SYS_ICFB2_A_VAL		0xFFFFFFFF
+#define CONFIG_SYS_DR_A_VAL		0x00000000
+
+/* Setup for PA23 which is Reset Default PA23 but has to become CS5 */
+#define CONFIG_SYS_GIUS_A_VAL		0x00007FF8
+#define CONFIG_SYS_ICR1_A_VAL		0x00000000
+#define CONFIG_SYS_ICR2_A_VAL		0x00000000
+#define CONFIG_SYS_IMR_A_VAL		0x00000000
+#define CONFIG_SYS_GPR_A_VAL		0x00000000
+#define CONFIG_SYS_PUEN_A_VAL		0xFFFFFFFF
+
+#define CONFIG_SYS_DDIR_B_VAL		0x00000000
+#define CONFIG_SYS_OCR1_B_VAL		0x00000000
+#define CONFIG_SYS_OCR2_B_VAL		0x00000000
+#define CONFIG_SYS_ICFA1_B_VAL		0xFFFFFFFF
+#define CONFIG_SYS_ICFA2_B_VAL		0xFFFFFFFF
+#define CONFIG_SYS_ICFB1_B_VAL		0xFFFFFFFF
+#define CONFIG_SYS_ICFB2_B_VAL		0xFFFFFFFF
+#define CONFIG_SYS_DR_B_VAL		0x00000000
+#define CONFIG_SYS_GIUS_B_VAL		0xFFFFFFFF
+#define CONFIG_SYS_ICR1_B_VAL		0x00000000
+#define CONFIG_SYS_ICR2_B_VAL		0x00000000
+#define CONFIG_SYS_IMR_B_VAL		0x00000000
+#define CONFIG_SYS_GPR_B_VAL		0x00000000
+#define CONFIG_SYS_PUEN_B_VAL		0xFFFFFFFF
+
+#define CONFIG_SYS_DDIR_C_VAL		0x00000000
+#define CONFIG_SYS_OCR1_C_VAL		0x00000000
+#define CONFIG_SYS_OCR2_C_VAL		0x00000000
+#define CONFIG_SYS_ICFA1_C_VAL		0xFFFFFFFF
+#define CONFIG_SYS_ICFA2_C_VAL		0xFFFFFFFF
+#define CONFIG_SYS_ICFB1_C_VAL		0xFFFFFFFF
+#define CONFIG_SYS_ICFB2_C_VAL		0xFFFFFFFF
+#define CONFIG_SYS_DR_C_VAL		0x00000000
+#define CONFIG_SYS_GIUS_C_VAL		0x0007FFFF
+#define CONFIG_SYS_ICR1_C_VAL		0x00000000
+#define CONFIG_SYS_ICR2_C_VAL		0x00000000
+#define CONFIG_SYS_IMR_C_VAL		0x00000000
+#define CONFIG_SYS_GPR_C_VAL		0x00000000
+#define CONFIG_SYS_PUEN_C_VAL		0xF913FFFF
+
+#define CONFIG_SYS_DDIR_D_VAL		0x00000000
+#define CONFIG_SYS_OCR1_D_VAL		0x00000000
+#define CONFIG_SYS_OCR2_D_VAL		0x00000000
+#define CONFIG_SYS_ICFA1_D_VAL		0xFFFFFFFF
+#define CONFIG_SYS_ICFA2_D_VAL		0xFFFFFFFF
+#define CONFIG_SYS_ICFB1_D_VAL		0xFFFFFFFF
+#define CONFIG_SYS_ICFB2_D_VAL		0xFFFFFFFF
+#define CONFIG_SYS_DR_D_VAL		0x00000000
+#define CONFIG_SYS_GIUS_D_VAL		0xFFFFFFFF
+#define CONFIG_SYS_ICR1_D_VAL		0x00000000
+#define CONFIG_SYS_ICR2_D_VAL		0x00000000
+#define CONFIG_SYS_IMR_D_VAL		0x00000000
+#define CONFIG_SYS_GPR_D_VAL		0x00000000
+#define CONFIG_SYS_PUEN_D_VAL		0xFFFFFFFF
+
+#define CONFIG_SYS_GPCR_VAL		0x000003AB
+
+/* FMCR Bit 1 becomes 0 to make CS3 if we have only one sdram bank*/
+#if (CONFIG_NR_DRAM_BANKS == 1)
+#define CONFIG_SYS_FMCR_VAL 0x00000001
+#elif (CONFIG_NR_DRAM_BANKS == 2)
+#define CONFIG_SYS_FMCR_VAL 0x00000003
+#endif
+
+/*
+ * FIXME: From here, there should not be any user configuration.
+ * All Equations are automatic
+ */
+
+#define CONFIG_SYS_HCLK_LGTH		(1000/CONFIG_SYS_BUS_FREQ)	/* ns */
+
+/* USB 48 MHz ; BUS 96MHz*/
+#ifdef CONFIG_SYS_OSC16
+#define CSCR_MASK 0x23030003
+#else
+#define CSCR_MASK 0x23000003
+#endif
+#define CONFIG_SYS_CSCR_VAL\
+	(CSCR_MASK 						\
+	|((((CONFIG_SYS_FREQ/CONFIG_USB_FREQ)-1)&0x07)<<26)	\
+	|((((CONFIG_SYS_FREQ/CONFIG_SYS_BUS_FREQ)-1)&0x0F)<<10))
+
+/* PERCLKx 16MHz */
+#define CONFIG_SYS_PCDR_VAL\
+	(((((CONFIG_SYS_FREQ/CONFIG_PERIF1_FREQ)-1)&0x0F)<<0)	\
+	|((((CONFIG_SYS_FREQ/CONFIG_PERIF2_FREQ)-1)&0x0F)<<4)	\
+	|((((CONFIG_SYS_FREQ/CONFIG_PERIF3_FREQ)-1)&0x7F)<<16))
+
+/* SDRAM controller programming Values */
+#if ((CONFIG_SYS_SDRAM_CLOCK_CYCLE_CL_1 > (3*CONFIG_SYS_HCLK_LGTH))\
+	|| (CONFIG_SYS_SDRAM_CLOCK_CYCLE_CL_1 < 1))
+#define REG_FIELD_SCL_VAL 3
+#else
+#define REG_FIELD_SCL_VAL\
+	((CONFIG_SYS_SDRAM_CLOCK_CYCLE_CL_1+CONFIG_SYS_HCLK_LGTH-1)\
+	/CONFIG_SYS_HCLK_LGTH)
+#endif
+
+#if ((CONFIG_SYS_SDRAM_ROW_PRECHARGE_DELAY > (2*CONFIG_SYS_HCLK_LGTH))\
+	|| (CONFIG_SYS_SDRAM_ROW_PRECHARGE_DELAY < 1))
+#define REG_FIELD_SRP_VAL 0
+#else
+#define REG_FIELD_SRP_VAL 1
+#endif
+
+#if (CONFIG_SYS_SDRAM_ROW_2_COL_DELAY > (3*CONFIG_SYS_HCLK_LGTH))
+#define REG_FIELD_SRCD_VAL 0
+#else
+#define REG_FIELD_SRCD_VAL\
+	((CONFIG_SYS_SDRAM_ROW_2_COL_DELAY+CONFIG_SYS_HCLK_LGTH-1)\
+	/CONFIG_SYS_HCLK_LGTH)
+#endif
+
+#if (CONFIG_SYS_SDRAM_ROW_CYCLE_DELAY > (7*CONFIG_SYS_HCLK_LGTH))
+#define REG_FIELD_SRC_VAL 0
+#else
+#define REG_FIELD_SRC_VAL\
+	((CONFIG_SYS_SDRAM_ROW_CYCLE_DELAY+CONFIG_SYS_HCLK_LGTH-1)\
+	/CONFIG_SYS_HCLK_LGTH)
+#endif
+
+#define REG_SDCTL_BASE_CONFIG (0x800a1000\
+				| (((CONFIG_SYS_SDRAM_NUM_ROW-11)&0x3)<<24)\
+				| (((CONFIG_SYS_SDRAM_NUM_COL-8)&0x3)<<20)\
+				| (((CONFIG_SYS_SDRAM_REFRESH)&0x3)<<14)\
+				| (((REG_FIELD_SCL_VAL)&0x3)<<8)\
+				| (((REG_FIELD_SRP_VAL)&0x1)<<6)\
+				| (((REG_FIELD_SRCD_VAL)&0x3)<<4)\
+				| (((REG_FIELD_SRC_VAL)&0x7)<<0))
+
+#define CONFIG_SYS_NORMAL_RW_CMD	((0x0<<28)+REG_SDCTL_BASE_CONFIG)
+#define CONFIG_SYS_PRECHARGE_CMD	((0x1<<28)+REG_SDCTL_BASE_CONFIG)
+#define CONFIG_SYS_AUTOREFRESH_CMD	((0x2<<28)+REG_SDCTL_BASE_CONFIG)
+#define CONFIG_SYS_SET_MODE_REG_CMD	((0x3<<28)+REG_SDCTL_BASE_CONFIG)
+
+/* Issue Mode register Command to SDRAM*/
+#define CONFIG_SYS_SDRAM_MODE_REGISTER_VAL\
+	((((CONFIG_SYS_SDRAM_BURST_LENGTH)&0x7)<<(CONFIG_SYS_SDRAM_NUM_COL+4))\
+	| (((REG_FIELD_SCL_VAL)&0x3)<<(CONFIG_SYS_SDRAM_NUM_COL+4+4))\
+	| (((CONFIG_SYS_SDRAM_SINGLE_ACCESS)&0x1)\
+		<<(CONFIG_SYS_SDRAM_NUM_COL+4+9)))
+
+/* Issue Precharge all Command to SDRAM*/
+#define CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL\
+	(((CONFIG_SYS_SDRAM_SINGLE_ACCESS)&0x1)<<(CONFIG_SYS_SDRAM_NUM_COL+4+9))
+
+/*
+ * CSxU_VAL:
+ * 63|    x    |x|x x|x x x x|x x| x | x  |x x x x|48
+ *   |DTACK_SEL|0|BCD|  BCS  |PSZ|PME|SYNC|  DOL  |
+ *
+ * 47| x x  | x x x x x x | x | x x x x | x x x x |32
+ *   | CNC  |     WSC     | 0 |   WWS   |   EDC   |
+ *
+ * CSxL_VAL:
+ * 31|  x x x x  | x x x x  | x x x x  | x x x x  |24
+ *   |    OEA    |   OEN    |   WEA    |   WEN    |
+ * 23|x x x x| x | x x x | x x  x x |x x| x |  x  | 0
+ *   |  CSA  |EBC|  DSZ  | 0|SP|0|WP|0 0|PA |CSEN |
+ */
+#define CONFIG_SYS_CS0U_VAL\
+	((((CONFIG_SYS_CS0_XTRA_DEAD_CYC+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)\
+	|((((CONFIG_SYS_CS0_WRITE_XTRA_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<4)\
+	|(((((CONFIG_SYS_CS0_READ_CYC_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)-1)&0x3F)<<8)\
+	|((((CONFIG_SYS_CS0_CS_NEG_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x03)<<14)\
+	|((((CONFIG_SYS_CS0_SYNC_DAT_OUT_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
+	|((CONFIG_SYS_CS0_SYNC_ENABLE&0x01)<<20)\
+	|((CONFIG_SYS_CS0_SYNC_PAGE_MODE_EMUL&0x01)<<21)\
+	|((CONFIG_SYS_CS0_SYNC_PAGE_SIZE&0x03)<<22)\
+	|((((CONFIG_SYS_CS0_SYNC_BURST_CLK_START+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
+	|((CONFIG_SYS_CS0_SYNC_BURST_CLK_DIV&0x03)<<28))
+
+#define CONFIG_SYS_CS0L_VAL\
+	((CONFIG_SYS_CS0_CHIP_SELECT_ENABLE&0x01)\
+	|((CONFIG_SYS_CS0_WRITE_PROTECT&0x01)<<4)\
+	|((CONFIG_SYS_CS0_SUPERVISOR_PROTECT&0x01)<<6)\
+	|((CONFIG_SYS_CS0_DATA_PORT_SIZE&0x07)<<8)\
+	|((CONFIG_SYS_CS0_EB_SIGNAL_CONTROL_WRITE&0x01)<<11)\
+	|((((CONFIG_SYS_CS0_CS_ASSERT_NEG_DLY+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<12)\
+	|(((((CONFIG_SYS_CS0_EB_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
+	|(((((CONFIG_SYS_CS0_EB_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<20)\
+	|(((((CONFIG_SYS_CS0_OE_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
+	|(((((CONFIG_SYS_CS0_OE_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<28))
+
+#define CONFIG_SYS_CS1U_VAL\
+	((((CONFIG_SYS_CS1_XTRA_DEAD_CYC+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)\
+	|((((CONFIG_SYS_CS1_WRITE_XTRA_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<4)\
+	|(((((CONFIG_SYS_CS1_READ_CYC_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)-1)&0x3F)<<8)\
+	|((((CONFIG_SYS_CS1_CS_NEG_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x03)<<14)\
+	|((((CONFIG_SYS_CS1_SYNC_DAT_OUT_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
+	|((CONFIG_SYS_CS1_SYNC_ENABLE&0x01)<<20)\
+	|((CONFIG_SYS_CS1_SYNC_PAGE_MODE_EMUL&0x01)<<21)\
+	|((CONFIG_SYS_CS1_SYNC_PAGE_SIZE&0x03)<<22)\
+	|((((CONFIG_SYS_CS1_SYNC_BURST_CLK_START+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
+	|((CONFIG_SYS_CS1_SYNC_BURST_CLK_DIV&0x03)<<28))
+
+#define CONFIG_SYS_CS1L_VAL\
+	((CONFIG_SYS_CS1_CHIP_SELECT_ENABLE&0x01)\
+	|((CONFIG_SYS_CS1_PIN_ASSERT&0x01)<<1)\
+	|((CONFIG_SYS_CS1_WRITE_PROTECT&0x01)<<4)\
+	|((CONFIG_SYS_CS1_SUPERVISOR_PROTECT&0x01)<<6)\
+	|((CONFIG_SYS_CS1_DATA_PORT_SIZE&0x07)<<8)\
+	|((CONFIG_SYS_CS1_EB_SIGNAL_CONTROL_WRITE&0x01)<<11)\
+	|((((CONFIG_SYS_CS1_CS_ASSERT_NEG_DLY+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<12)\
+	|(((((CONFIG_SYS_CS1_EB_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
+	|(((((CONFIG_SYS_CS1_EB_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<20)\
+	|(((((CONFIG_SYS_CS1_OE_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
+	|(((((CONFIG_SYS_CS1_OE_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<28))
+
+#define CONFIG_SYS_CS2U_VAL\
+	(((((CONFIG_SYS_CS2_XTRA_DEAD_CYC+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)\
+	|((((CONFIG_SYS_CS2_WRITE_XTRA_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<4)\
+	|(((((CONFIG_SYS_CS2_READ_CYC_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)-1)&0x3F)<<8)\
+	|((((CONFIG_SYS_CS2_CS_NEG_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x03)<<14)\
+	|(((CONFIG_SYS_CS2_SYNC_DAT_OUT_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
+	|((CONFIG_SYS_CS2_SYNC_ENABLE&0x01)<<20)\
+	|((CONFIG_SYS_CS2_SYNC_PAGE_MODE_EMUL&0x01)<<21)\
+	|((CONFIG_SYS_CS2_SYNC_PAGE_SIZE&0x03)<<22)\
+	|((((CONFIG_SYS_CS2_SYNC_BURST_CLK_START+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
+	|((CONFIG_SYS_CS2_SYNC_BURST_CLK_DIV&0x03)<<28))
+
+#define CONFIG_SYS_CS2L_VAL\
+	((CONFIG_SYS_CS2_CHIP_SELECT_ENABLE&0x01)\
+	|((CONFIG_SYS_CS2_PIN_ASSERT&0x01)<<1)\
+	|((CONFIG_SYS_CS2_WRITE_PROTECT&0x01)<<4)\
+	|((CONFIG_SYS_CS2_SUPERVISOR_PROTECT&0x01)<<6)\
+	|((CONFIG_SYS_CS2_DATA_PORT_SIZE&0x07)<<8)\
+	|((CONFIG_SYS_CS2_EB_SIGNAL_CONTROL_WRITE&0x01)<<11)\
+	|((((CONFIG_SYS_CS2_CS_ASSERT_NEG_DLY+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<12)\
+	|(((((CONFIG_SYS_CS2_EB_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
+	|(((((CONFIG_SYS_CS2_EB_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<20)\
+	|(((((CONFIG_SYS_CS2_OE_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
+	|(((((CONFIG_SYS_CS2_OE_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<28))
+
+#define CONFIG_SYS_CS3U_VAL\
+	((((CONFIG_SYS_CS3_XTRA_DEAD_CYC+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)\
+	|((((CONFIG_SYS_CS3_WRITE_XTRA_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<4)\
+	|(((((CONFIG_SYS_CS3_READ_CYC_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)-1)&0x3F)<<8)\
+	|((((CONFIG_SYS_CS3_CS_NEG_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x03)<<14)\
+	|((((CONFIG_SYS_CS3_SYNC_DAT_OUT_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
+	|((CONFIG_SYS_CS3_SYNC_ENABLE&0x01)<<20)\
+	|((CONFIG_SYS_CS3_SYNC_PAGE_MODE_EMUL&0x01)<<21)\
+	|((CONFIG_SYS_CS3_SYNC_PAGE_SIZE&0x03)<<22)\
+	|((((CONFIG_SYS_CS3_SYNC_BURST_CLK_START+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
+	|((CONFIG_SYS_CS3_SYNC_BURST_CLK_DIV&0x03)<<28))
+
+#define CONFIG_SYS_CS3L_VAL\
+	((CONFIG_SYS_CS3_CHIP_SELECT_ENABLE&0x01)\
+	|((CONFIG_SYS_CS3_PIN_ASSERT&0x01)<<1)\
+	|((CONFIG_SYS_CS3_WRITE_PROTECT&0x01)<<4)\
+	|((CONFIG_SYS_CS3_SUPERVISOR_PROTECT&0x01)<<6)\
+	|((CONFIG_SYS_CS3_DATA_PORT_SIZE&0x07)<<8)\
+	|((CONFIG_SYS_CS3_EB_SIGNAL_CONTROL_WRITE&0x01)<<11)\
+	|((((CONFIG_SYS_CS3_CS_ASSERT_NEG_DLY+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<12)\
+	|(((((CONFIG_SYS_CS3_EB_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
+	|(((((CONFIG_SYS_CS3_EB_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<20)\
+	|(((((CONFIG_SYS_CS3_OE_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
+	|(((((CONFIG_SYS_CS3_OE_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<28))
+
+#define CONFIG_SYS_CS4U_VAL\
+	(((((CONFIG_SYS_CS4_XTRA_DEAD_CYC+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)\
+	|((((CONFIG_SYS_CS4_WRITE_XTRA_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<4)\
+	|(((((CONFIG_SYS_CS4_READ_CYC_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)-1)&0x3F)<<8)\
+	|((((CONFIG_SYS_CS4_CS_NEG_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x03)<<14)\
+	|((((CONFIG_SYS_CS4_SYNC_DAT_OUT_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<16))\
+	|((CONFIG_SYS_CS4_SYNC_ENABLE&0x01)<<20)\
+	|((CONFIG_SYS_CS4_SYNC_PAGE_MODE_EMUL&0x01)<<21)\
+	|((CONFIG_SYS_CS4_SYNC_PAGE_SIZE&0x03)<<22)\
+	|((((CONFIG_SYS_CS4_SYNC_BURST_CLK_START+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
+	|((CONFIG_SYS_CS4_SYNC_BURST_CLK_DIV&0x03)<<28))
+
+#define CONFIG_SYS_CS4L_VAL\
+	((CONFIG_SYS_CS4_CHIP_SELECT_ENABLE&0x01)\
+	|((CONFIG_SYS_CS4_PIN_ASSERT&0x01)<<1)\
+	|((CONFIG_SYS_CS4_WRITE_PROTECT&0x01)<<4)\
+	|((CONFIG_SYS_CS4_SUPERVISOR_PROTECT&0x01)<<6)\
+	|((CONFIG_SYS_CS4_DATA_PORT_SIZE&0x07)<<8)\
+	|((CONFIG_SYS_CS4_EB_SIGNAL_CONTROL_WRITE&0x01)<<11)\
+	|((((CONFIG_SYS_CS4_CS_ASSERT_NEG_DLY+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<12)\
+	|(((((CONFIG_SYS_CS4_EB_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
+	|(((((CONFIG_SYS_CS4_EB_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<20)\
+	|(((((CONFIG_SYS_CS4_OE_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
+	|(((((CONFIG_SYS_CS4_OE_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<28))
+
+#define CONFIG_SYS_CS5U_VAL\
+	((((CONFIG_SYS_CS5_XTRA_DEAD_CYC+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)\
+	|((((CONFIG_SYS_CS5_WRITE_XTRA_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<4)\
+	|(((((CONFIG_SYS_CS5_READ_CYC_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)-1)&0x3F)<<8)\
+	|((((CONFIG_SYS_CS5_CS_NEG_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x03)<<14)\
+	|((((CONFIG_SYS_CS5_SYNC_DAT_OUT_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
+	|((CONFIG_SYS_CS5_SYNC_ENABLE&0x01)<<20)\
+	|((CONFIG_SYS_CS5_SYNC_PAGE_MODE_EMUL&0x01)<<21)\
+	|((CONFIG_SYS_CS5_SYNC_PAGE_SIZE&0x03)<<22)\
+	|((((CONFIG_SYS_CS5_SYNC_BURST_CLK_START+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
+	|((CONFIG_SYS_CS5_SYNC_BURST_CLK_DIV&0x03)<<28)\
+	|((CONFIG_SYS_CS5_DTACK_SELECT&0x01)<<31))
+
+#define CONFIG_SYS_CS5L_VAL\
+	((CONFIG_SYS_CS5_CHIP_SELECT_ENABLE&0x01)\
+	|((CONFIG_SYS_CS5_PIN_ASSERT&0x01)<<1)\
+	|((CONFIG_SYS_CS5_WRITE_PROTECT&0x01)<<4)\
+	|((CONFIG_SYS_CS5_SUPERVISOR_PROTECT&0x01)<<6)\
+	|((CONFIG_SYS_CS5_DATA_PORT_SIZE&0x07)<<8)\
+	|((CONFIG_SYS_CS5_EB_SIGNAL_CONTROL_WRITE&0x01)<<11)\
+	|((((CONFIG_SYS_CS5_CS_ASSERT_NEG_DLY+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<12)\
+	|(((((CONFIG_SYS_CS5_EB_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
+	|(((((CONFIG_SYS_CS5_EB_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<20)\
+	|(((((CONFIG_SYS_CS5_OE_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
+	|(((((CONFIG_SYS_CS5_OE_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<28))
+
+#endif /* __CONFIG_H */

[U-Boot] [PATCH 5/9] apf9328: add default board configuration file

[Stefano Babic]

On 08/10/2011 10:33 PM, Eric Jarrige wrote:
> Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org>
> ---
>  include/configs/apf9328.h | 1034 +++++++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 1034 insertions(+), 0 deletions(-)
>  create mode 100644 include/configs/apf9328.h

Hi Eric,

> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#define CONFIG_VERSION_VARIABLE
> +#define CONFIG_ENV_VERSION 	"4.0"
> +#define CONFIG_IDENT_STRING	" apf9328 patch 4.0"

You add CONFIG_ without documenting them. If they are specific for your
board, you should use another name, or please add documentation to make
them available for other boards, too.

> +
> +#define CONFIG_ARM920T		1	/* this is an ARM920T CPU */

It is enough to #define a switch, without setting the value. This should
be only:

#define CONFIG_ARM920T	/* this is an ARM920T CPU */

This must be fixed globally.

> +#define CONFIG_IMX		1	/* in a Motorola MC9328MXL Chip */

Ditto, and so on..

> +/*
> + * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
> + * neccessary in include/cmd_confdefs.h file. (Un)comment for getting
> + * functionality or size of u-boot code.
> + */
> +
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_ASKENV	/* ask for env variable		*/
> +#define CONFIG_CMD_BSP		/* Board Specific functions	*/
> +#define CONFIG_CMD_CACHE	/* icache, dcache		*/
> +#define CONFIG_CMD_DATE		/* support for RTC, date/time.. */
> +#define CONFIG_CMD_DHCP		/* DHCP Support			*/
> +#define CONFIG_CMD_DIAG		/* Diagnostics			*/
> +#define CONFIG_CMD_EEPROM	/* EEPROM read/write support	*/
> +#define CONFIG_CMD_FLASH	/* flinfo, erase, protect	*/
> +#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
> +#define CONFIG_CMD_IMLS		/* List all found images	*/

IMLS is already part of default commands

> +#define CONFIG_CMD_IMMAP	/* IMMR dump support		*/

Is this not specific for PowerQuick processor ?

> +#define CONFIG_EXTRA_ENV_SETTINGS \
> +	"env_version="		CONFIG_ENV_VERSION		"\0"	\
> +	"fileaddr="		MK_STR(CONFIG_SYS_LOAD_ADDR)	"\0"	\
> +	"filesize="		MK_STR(CONFIG_SYS_MONITOR_LEN)	"\0"	\

filesize is dynamically computed, you should not add it

> +	"ntpserverip=217.147.208.1\0"					\

No fixed IP address, please, even if they are related to known NTP servers.

> +#define CONFIG_MACH_TYPE MACH_TYPE_APF9328

Why do you need it ? Is it not enough to use directly MACH_TYPE_APF9328 ?

> +#define CONFIG_ETHADDR

Not required, right ?

> +#define CONFIG_NETMASK		255.255.255.0
> +#define CONFIG_IPADDR		192.168.000.10

Please drop fix ip address. They should not be part of mainline,

> +#define CONFIG_BOARD_NAME	"apf9328"
> +#define CONFIG_HOSTNAME		"apf9328"
> +#define CONFIG_GATEWAYIP	192.168.000.1
> +#define CONFIG_SERVERIP		192.168.000.2

Ditto

> +/*
> + * Malloc pool need to host env + 128 Kb reserve for other allocations.
> + */
> +#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128<<10))

I Think checkpatch will complain about missing spaces before and after <<

> +#define CONFIG_STACKSIZE	(120<<10)	/* stack size	*/
> +
> +#ifdef CONFIG_USE_IRQ
> +#define CONFIG_STACKSIZE_IRQ	(4<<10)	/* IRQ stack	*/
> +#define CONFIG_STACKSIZE_FIQ	(4<<10)	/* FIQ stack	*/
> +#endif

Do you need IRQ ? It is undefined, you can drop this part


> +
> +/*
> +* Clocks configuration
> +*/
> +/*
> + * PLL configuration
> + *
> + * f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
> + * f_ref=16,777216MHz
> + * 32768 Hz xtal
> + * 0x07B32DA5: 192.0000173
> + * 0x002a141f: 191,9944MHz
> + * 0x040b2007: 144MHz
> + * 0x0FB32DA5: 96.00000864 MHz
> + * 0x042a141f: 96MHz
> + * 0x0811140d: 64MHz
> + * 0x040e200e: 150MHz
> + * 0x00321431: 200MHz
> + *
> + *16 MHz xtal
> + * 0x08001800: 64MHz mit 16er Quarz
> + * 0x04001800: 96MHz mit 16er Quarz
> + * 0x04002400: 144MHz mit 16er Quarz
> + *
> + * 31	|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
> + *	|XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------|
> + */
> +
> +#define CONFIG_SYS_OSC32	32768	/* 32768 or 32000 Hz crystal */
> +#undef	CONFIG_SYS_OSC16	/* there is no external 16MHz external clock */
> +
> +/* MPU CLOCK source before PLL	(should be named CONFIG_SYS_SYS_CLK_FREQ) */
> +#define CONFIG_SYS_CLK_FREQ	(512*CONFIG_SYS_OSC32)
> +#define CONFIG_SYS_MPCTL0_VAL		0x07B32DA5	/* 192.000017 MHz */
> +#define CONFIG_SYS_MPCTL1_VAL		0
> +
> +/* system clock source before PLL (should be named CONFIG_SYS_SYSPLL_CLK_FREQ)*/
> +#ifndef CONFIG_SYS_OSC16
> +#define CONFIG_SYSPLL_CLK_FREQ		(512*CONFIG_SYS_OSC32)
> +#if (CONFIG_SYS_OSC32 == 32000)
> +#define CONFIG_SYS_SPCTL0_VAL		0x043F1437	/* 96 MHz */
> +#define CONFIG_SYS_SPCTL1_VAL		0
> +#define CONFIG_SYS_FREQ			96	/* MHz */
> +#else /* CONFIG_SYS_OSC32 == 32768 */
> +#define CONFIG_SYS_SPCTL0_VAL		0x0FB32DA5	/* 96.000009 MHz */
> +#define CONFIG_SYS_SPCTL1_VAL		0
> +#define CONFIG_SYS_FREQ			96	/* MHz */
> +#endif /* CONFIG_SYS_OSC32 */
> +#else /* CONFIG_SYS_OSC16 in use */
> +#define CONFIG_SYSPLL_CLK_FREQ		CONFIG_SYS_OSC16
> +#define CONFIG_SYS_SPCTL0_VAL		0x04001401	/* 96 MHz */
> +#define CONFIG_SYS_SPCTL1_VAL		0x0C000040
> +#define CONFIG_SYS_FREQ			96	/* MHz */
> +#endif /* CONFIG_SYS_OSC16 */
> +
> +/* external bus frequency (have to be a CONFIG_SYS_FREQ ratio) */
> +#define CONFIG_SYS_BUS_FREQ 	96	/* 96|48... MHz (BCLOCK and HCLOCK) */
> +#define CONFIG_USB_FREQ		48	/* 48 MHz */
> +#define CONFIG_PERIF1_FREQ	16	/* 16 MHz UART, Timer PWM */
> +#define CONFIG_PERIF2_FREQ 	48	/* 48 MHz LCD SD SPI */
> +#define CONFIG_PERIF3_FREQ	16	/* 16 MHz SSI */
> +
> +/*
> + * SDRAM definition parameter
> + */
> +/* we have and support only 1 bank of SDRAM */
> +#define CONFIG_NR_DRAM_BANKS 1
> +
> +#define CONFIG_SYS_SDRAM_MBYTE_SYZE 16
> +
> +/*
> + * CONFIG_SYS_SDRAM_NUM_COL 8, 9, 10 or 11 column address bits
> + * CONFIG_SYS_SDRAM_NUM_ROW 11, 12 or 13 row address bits
> + * CONFIG_SYS_SDRAM_REFRESH 0=OFF 1=2048 2=4096 3=8192 refresh
> + * CONFIG_SYS_SDRAM_CLOCK_CYCLE_CL_1 X ns clock cycle time when CL=1
> + * CONFIG_SYS_SDRAM_ROW_PRECHARGE_DELAY X ns SRP
> + * CONFIG_SYS_SDRAM_ROW_2_COL_DELAY X ns SRCD
> + * CONFIG_SYS_SDRAM_ROW_CYCLE_DELAY X ns SRC
> + * CONFIG_SYS_SDRAM_BURST_LENGTH 2^N BYTES (N=0..3)
> + * CONFIG_SYS_SDRAM_SINGLE_ACCESS 1= single access; 0 = Burst mode
> + */
> +
> +#if (CONFIG_SYS_SDRAM_MBYTE_SYZE == 8)

Why do we need such a stuff when your configuration is fixed at compile
time with CONFIG_SYS_SDRAM_MBYTE_SYZE 16 ?

> +/* lowlevel_linit copy U-Boot at CONFIG_SYS_INIT_SP_ADDR  (here in RAM) */
> +/* making u-boot runnable from flash and also RAM that is usefull to boot */
> +/* from serial port and from flash with only one version of U-Boot */
> +#ifndef CONFIG_SYS_TEXT_BASE
> +#define CONFIG_SYS_TEXT_BASE	0x08000000
> +#endif
> +
> +#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE	\
> +		+ CONFIG_SYS_SDRAM_1_SIZE - 0x0100000)

You do not use U_Boot macro here (GENERATED_GBL_DATA_SIZE), as it is
usual. Stack pointer is already in RAM before relocation. Is it correct ?

> +/*#define CONFIG_MMC		1
> +*/

Dead code

> +/*
> + * External interfaces module
> + *
> + * CSxU_VAL:
> + * 63|    x    |x|x x|x x x x|x x| x | x  |x x x x|48
> + *   |DTACK_SEL|0|BCD|  BCS  |PSZ|PME|SYNC|  DOL  |
> + *
> + * 47| x x  | x x x x x x | x | x x x x | x x x x |32
> + *   | CNC  |     WSC     | 0 |   WWS   |   EDC   |
> + *
> + * CSxL_VAL:
> + * 31|  x x x x  | x x x x  | x x x x  | x x x x  |24
> + *   |    OEA    |   OEN    |   WEA    |   WEN    |
> + * 23|x x x x| x | x x x | x x  x x |x x| x |  x  | 0
> + *   |  CSA  |EBC|  DSZ  | 0|SP|0|WP|0 0|PA |CSEN |
> + */
> +
> +/* CS0 configuration for flash memory Micron MT28F128J3-150 */
> +#define CONFIG_SYS_CS0_CHIP_SELECT_ENABLE	1 /* 1 : enable CS0 */
> +#define CONFIG_SYS_CS0_DATA_PORT_SIZE		0x5 /* 5=16 bits on D[15:0] */
> +					/* 3=8bits on D[7:0] 6=32 bits..*/
> +#define CONFIG_SYS_CS0_SUPERVISOR_PROTECT	0 /* 1: user access prohibited*/
> +#define CONFIG_SYS_CS0_WRITE_PROTECT		0 /* 1: write prohibited*/
> +#define CONFIG_SYS_CS0_EB_SIGNAL_CONTROL_WRITE	1 /* 1 EB is as write signal */
> +#define CONFIG_SYS_CS0_READ_CYC_LGTH		150	/* ns */
> +#define CONFIG_SYS_CS0_OE_ASSERT_DLY		0	/* ns */
> +#define CONFIG_SYS_CS0_OE_NEG_DLY		0	/* ns */
> +
> +#define CONFIG_SYS_CS0_CS_NEG_LGTH 	0	/* ns CS HIGH to CS LOW : tCWH*/
> +#define CONFIG_SYS_CS0_XTRA_DEAD_CYC	35	/* ns from CS HIGH to tristate*/
> +
> +#define CONFIG_SYS_CS0_WRITE_XTRA_LGTH		0	/* ns */
> +#define CONFIG_SYS_CS0_EB_ASSERT_DLY		0	/* ns */
> +#define CONFIG_SYS_CS0_EB_NEG_DLY		0	/* ns */
> +#define CONFIG_SYS_CS0_CS_ASSERT_NEG_DLY	0	/* ns */
> +

All this stuff seems to me not general, that is they should not have a
CONFIG_SYS_* name. Else they must be documented.

Really I think that all this defines should be put in the code that use
them, and not in the configuration file (if they are not spread with
other boards).

> +#define CONFIG_SYS_CSCR_VAL\
> +	(CSCR_MASK 						\
> +	|((((CONFIG_SYS_FREQ/CONFIG_USB_FREQ)-1)&0x07)<<26)	\
> +	|((((CONFIG_SYS_FREQ/CONFIG_SYS_BUS_FREQ)-1)&0x0F)<<10))
> +

This macro (and the following ones) are related to the IMX processor and
are not specific to the board. They should be available for all IMX
boards, and the right place is arch/arm/include/asm/arch-imx/.

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH 5/9] apf9328: add default board configuration file

[Eric Jarrige]

Hi Stefano,
On 11 ao?t 2011, at 11:21, Stefano Babic wrote:

> On 08/10/2011 10:33 PM, Eric Jarrige wrote:
>> Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org>
>> ---
>> include/configs/apf9328.h | 1034 +++++++++++++++++++++++++++++++++++++++++++++
>> 1 files changed, 1034 insertions(+), 0 deletions(-)
>> create mode 100644 include/configs/apf9328.h
> 
> Hi Eric,
> 
>> +
>> +#ifndef __CONFIG_H
>> +#define __CONFIG_H
>> +
>> +#define CONFIG_VERSION_VARIABLE
>> +#define CONFIG_ENV_VERSION 	"4.0"
>> +#define CONFIG_IDENT_STRING	" apf9328 patch 4.0"
> 
> You add CONFIG_ without documenting them. If they are specific for your
> board, you should use another name, or please add documentation to make
> them available for other boards, too.

Good point. I propose to use a prefix like "APF_" for macros specifics to this board and I will update the documentation to make the generic config available for the other boards.

> 
>> +
>> +#define CONFIG_ARM920T		1	/* this is an ARM920T CPU */
> 
> It is enough to #define a switch, without setting the value. This should
> be only:
> 
> #define CONFIG_ARM920T	/* this is an ARM920T CPU */
> 
> This must be fixed globally.
> 
>> +#define CONFIG_IMX		1	/* in a Motorola MC9328MXL Chip */
> 
> Ditto, and so on..
> 
>> +/*
>> + * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
>> + * neccessary in include/cmd_confdefs.h file. (Un)comment for getting
>> + * functionality or size of u-boot code.
>> + */
>> +
>> +#include <config_cmd_default.h>
>> +
>> +#define CONFIG_CMD_ASKENV	/* ask for env variable		*/
>> +#define CONFIG_CMD_BSP		/* Board Specific functions	*/
>> +#define CONFIG_CMD_CACHE	/* icache, dcache		*/
>> +#define CONFIG_CMD_DATE		/* support for RTC, date/time.. */
>> +#define CONFIG_CMD_DHCP		/* DHCP Support			*/
>> +#define CONFIG_CMD_DIAG		/* Diagnostics			*/
>> +#define CONFIG_CMD_EEPROM	/* EEPROM read/write support	*/
>> +#define CONFIG_CMD_FLASH	/* flinfo, erase, protect	*/
>> +#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
>> +#define CONFIG_CMD_IMLS		/* List all found images	*/
> 
> IMLS is already part of default commands
> 
>> +#define CONFIG_CMD_IMMAP	/* IMMR dump support		*/
> 
> Is this not specific for PowerQuick processor ?

Thx, I ll remove it.

> 
>> +#define CONFIG_EXTRA_ENV_SETTINGS \
>> +	"env_version="		CONFIG_ENV_VERSION		"\0"	\
>> +	"fileaddr="		MK_STR(CONFIG_SYS_LOAD_ADDR)	"\0"	\
>> +	"filesize="		MK_STR(CONFIG_SYS_MONITOR_LEN)	"\0"	\
> 
> filesize is dynamically computed, you should not add it

We need this variable already initialized at boot time to support the specific imx boot mode from serial port when the user lost the full content of the flash.
In such case (that is a stressing situation for the user) he can push U-Boot through the serial port and use directly the script "flash_uboot" to recover the original content of the flash. In such a use case this variable is not dynamically computed.

> 
>> +	"ntpserverip=217.147.208.1\0"					\
> 
> No fixed IP address, please, even if they are related to known NTP servers.
> 
>> +#define CONFIG_MACH_TYPE MACH_TYPE_APF9328
> 
> Why do you need it ? Is it not enough to use directly MACH_TYPE_APF9328 ?

The idea is to have most of the configuration parameters in the config.h files.
So that it become possible to factorize the initialization of the mach_type in a common place.
For the time being it is not needed it and I will remove it.

> 
>> +#define CONFIG_ETHADDR
> 
> Not required, right ?

Right.

> 
>> +#define CONFIG_NETMASK		255.255.255.0
>> +#define CONFIG_IPADDR		192.168.000.10
> 
> Please drop fix ip address. They should not be part of mainline,

Here, I have a problem as our documentation on the wiki armadeus.org is based on this default IP addresses.
We really need a set of default IP addresses for private network to simplify as much as possible the life of the armadeus project developers. 
I never seen such a restriction in U-Boot doc and moreover there is a set CONFIG_XXIP documented in U-BOOT that confusing me,
Is there another solution for a complete usable default configuration?


> 
>> +#define CONFIG_BOARD_NAME	"apf9328"
>> +#define CONFIG_HOSTNAME		"apf9328"
>> +#define CONFIG_GATEWAYIP	192.168.000.1
>> +#define CONFIG_SERVERIP		192.168.000.2
> 
> Ditto
> 
>> +/*
>> + * Malloc pool need to host env + 128 Kb reserve for other allocations.
>> + */
>> +#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128<<10))
> 
> I Think checkpatch will complain about missing spaces before and after <<

checkpatch did not complain. << and >> do not require extra spaces.

> 
>> +#define CONFIG_STACKSIZE	(120<<10)	/* stack size	*/
>> +
>> +#ifdef CONFIG_USE_IRQ
>> +#define CONFIG_STACKSIZE_IRQ	(4<<10)	/* IRQ stack	*/
>> +#define CONFIG_STACKSIZE_FIQ	(4<<10)	/* FIQ stack	*/
>> +#endif
> 
> Do you need IRQ ? It is undefined, you can drop this part

We do not use IRQ. I will drop this part. Thx.

> 
> 
>> +
>> +/*
>> +* Clocks configuration
>> +*/
>> +/*
>> + * PLL configuration
>> + *
>> + * f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
>> + * f_ref=16,777216MHz
>> + * 32768 Hz xtal
>> + * 0x07B32DA5: 192.0000173
>> + * 0x002a141f: 191,9944MHz
>> + * 0x040b2007: 144MHz
>> + * 0x0FB32DA5: 96.00000864 MHz
>> + * 0x042a141f: 96MHz
>> + * 0x0811140d: 64MHz
>> + * 0x040e200e: 150MHz
>> + * 0x00321431: 200MHz
>> + *
>> + *16 MHz xtal
>> + * 0x08001800: 64MHz mit 16er Quarz
>> + * 0x04001800: 96MHz mit 16er Quarz
>> + * 0x04002400: 144MHz mit 16er Quarz
>> + *
>> + * 31	|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
>> + *	|XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------|
>> + */
>> +
>> +#define CONFIG_SYS_OSC32	32768	/* 32768 or 32000 Hz crystal */
>> +#undef	CONFIG_SYS_OSC16	/* there is no external 16MHz external clock */
>> +
>> +/* MPU CLOCK source before PLL	(should be named CONFIG_SYS_SYS_CLK_FREQ) */
>> +#define CONFIG_SYS_CLK_FREQ	(512*CONFIG_SYS_OSC32)
>> +#define CONFIG_SYS_MPCTL0_VAL		0x07B32DA5	/* 192.000017 MHz */
>> +#define CONFIG_SYS_MPCTL1_VAL		0
>> +
>> +/* system clock source before PLL (should be named CONFIG_SYS_SYSPLL_CLK_FREQ)*/
>> +#ifndef CONFIG_SYS_OSC16
>> +#define CONFIG_SYSPLL_CLK_FREQ		(512*CONFIG_SYS_OSC32)
>> +#if (CONFIG_SYS_OSC32 == 32000)
>> +#define CONFIG_SYS_SPCTL0_VAL		0x043F1437	/* 96 MHz */
>> +#define CONFIG_SYS_SPCTL1_VAL		0
>> +#define CONFIG_SYS_FREQ			96	/* MHz */
>> +#else /* CONFIG_SYS_OSC32 == 32768 */
>> +#define CONFIG_SYS_SPCTL0_VAL		0x0FB32DA5	/* 96.000009 MHz */
>> +#define CONFIG_SYS_SPCTL1_VAL		0
>> +#define CONFIG_SYS_FREQ			96	/* MHz */
>> +#endif /* CONFIG_SYS_OSC32 */
>> +#else /* CONFIG_SYS_OSC16 in use */
>> +#define CONFIG_SYSPLL_CLK_FREQ		CONFIG_SYS_OSC16
>> +#define CONFIG_SYS_SPCTL0_VAL		0x04001401	/* 96 MHz */
>> +#define CONFIG_SYS_SPCTL1_VAL		0x0C000040
>> +#define CONFIG_SYS_FREQ			96	/* MHz */
>> +#endif /* CONFIG_SYS_OSC16 */
>> +
>> +/* external bus frequency (have to be a CONFIG_SYS_FREQ ratio) */
>> +#define CONFIG_SYS_BUS_FREQ 	96	/* 96|48... MHz (BCLOCK and HCLOCK) */
>> +#define CONFIG_USB_FREQ		48	/* 48 MHz */
>> +#define CONFIG_PERIF1_FREQ	16	/* 16 MHz UART, Timer PWM */
>> +#define CONFIG_PERIF2_FREQ 	48	/* 48 MHz LCD SD SPI */
>> +#define CONFIG_PERIF3_FREQ	16	/* 16 MHz SSI */
>> +
>> +/*
>> + * SDRAM definition parameter
>> + */
>> +/* we have and support only 1 bank of SDRAM */
>> +#define CONFIG_NR_DRAM_BANKS 1
>> +
>> +#define CONFIG_SYS_SDRAM_MBYTE_SYZE 16
>> +
>> +/*
>> + * CONFIG_SYS_SDRAM_NUM_COL 8, 9, 10 or 11 column address bits
>> + * CONFIG_SYS_SDRAM_NUM_ROW 11, 12 or 13 row address bits
>> + * CONFIG_SYS_SDRAM_REFRESH 0=OFF 1=2048 2=4096 3=8192 refresh
>> + * CONFIG_SYS_SDRAM_CLOCK_CYCLE_CL_1 X ns clock cycle time when CL=1
>> + * CONFIG_SYS_SDRAM_ROW_PRECHARGE_DELAY X ns SRP
>> + * CONFIG_SYS_SDRAM_ROW_2_COL_DELAY X ns SRCD
>> + * CONFIG_SYS_SDRAM_ROW_CYCLE_DELAY X ns SRC
>> + * CONFIG_SYS_SDRAM_BURST_LENGTH 2^N BYTES (N=0..3)
>> + * CONFIG_SYS_SDRAM_SINGLE_ACCESS 1= single access; 0 = Burst mode
>> + */
>> +
>> +#if (CONFIG_SYS_SDRAM_MBYTE_SYZE == 8)
> 
> Why do we need such a stuff when your configuration is fixed at compile
> time with CONFIG_SYS_SDRAM_MBYTE_SYZE 16 ?

16MiB is the regular configuration but there are many configurations of boards with different size of memory.
This set of parameters enables to support every boards at compilation by just changing the value of CONFIG_SYS_SDRAM_MBYTE_SYZE.
So that the binary generated is fully optimized for each board.

> 
>> +/* lowlevel_linit copy U-Boot at CONFIG_SYS_INIT_SP_ADDR  (here in RAM) */
>> +/* making u-boot runnable from flash and also RAM that is usefull to boot */
>> +/* from serial port and from flash with only one version of U-Boot */
>> +#ifndef CONFIG_SYS_TEXT_BASE
>> +#define CONFIG_SYS_TEXT_BASE	0x08000000
>> +#endif
>> +
>> +#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE	\
>> +		+ CONFIG_SYS_SDRAM_1_SIZE - 0x0100000)
> 
> You do not use U_Boot macro here (GENERATED_GBL_DATA_SIZE), as it is
> usual. Stack pointer is already in RAM before relocation. Is it correct ?

Correct. I do have to optimize the location of the initial Stack pointer  for my board so I put the init SP at any safe place in RAM.

> 
>> +/*#define CONFIG_MMC		1
>> +*/
> 
> Dead code
> 
>> +/*
>> + * External interfaces module
>> + *
>> + * CSxU_VAL:
>> + * 63|    x    |x|x x|x x x x|x x| x | x  |x x x x|48
>> + *   |DTACK_SEL|0|BCD|  BCS  |PSZ|PME|SYNC|  DOL  |
>> + *
>> + * 47| x x  | x x x x x x | x | x x x x | x x x x |32
>> + *   | CNC  |     WSC     | 0 |   WWS   |   EDC   |
>> + *
>> + * CSxL_VAL:
>> + * 31|  x x x x  | x x x x  | x x x x  | x x x x  |24
>> + *   |    OEA    |   OEN    |   WEA    |   WEN    |
>> + * 23|x x x x| x | x x x | x x  x x |x x| x |  x  | 0
>> + *   |  CSA  |EBC|  DSZ  | 0|SP|0|WP|0 0|PA |CSEN |
>> + */
>> +
>> +/* CS0 configuration for flash memory Micron MT28F128J3-150 */
>> +#define CONFIG_SYS_CS0_CHIP_SELECT_ENABLE	1 /* 1 : enable CS0 */
>> +#define CONFIG_SYS_CS0_DATA_PORT_SIZE		0x5 /* 5=16 bits on D[15:0] */
>> +					/* 3=8bits on D[7:0] 6=32 bits..*/
>> +#define CONFIG_SYS_CS0_SUPERVISOR_PROTECT	0 /* 1: user access prohibited*/
>> +#define CONFIG_SYS_CS0_WRITE_PROTECT		0 /* 1: write prohibited*/
>> +#define CONFIG_SYS_CS0_EB_SIGNAL_CONTROL_WRITE	1 /* 1 EB is as write signal */
>> +#define CONFIG_SYS_CS0_READ_CYC_LGTH		150	/* ns */
>> +#define CONFIG_SYS_CS0_OE_ASSERT_DLY		0	/* ns */
>> +#define CONFIG_SYS_CS0_OE_NEG_DLY		0	/* ns */
>> +
>> +#define CONFIG_SYS_CS0_CS_NEG_LGTH 	0	/* ns CS HIGH to CS LOW : tCWH*/
>> +#define CONFIG_SYS_CS0_XTRA_DEAD_CYC	35	/* ns from CS HIGH to tristate*/
>> +
>> +#define CONFIG_SYS_CS0_WRITE_XTRA_LGTH		0	/* ns */
>> +#define CONFIG_SYS_CS0_EB_ASSERT_DLY		0	/* ns */
>> +#define CONFIG_SYS_CS0_EB_NEG_DLY		0	/* ns */
>> +#define CONFIG_SYS_CS0_CS_ASSERT_NEG_DLY	0	/* ns */
>> +
> 
> All this stuff seems to me not general, that is they should not have a
> CONFIG_SYS_* name. Else they must be documented.
> 
> Really I think that all this defines should be put in the code that use
> them, and not in the configuration file (if they are not spread with
> other boards).

I will rework all the CONFIG_SYS specific to this board.

> 
>> +#define CONFIG_SYS_CSCR_VAL\
>> +	(CSCR_MASK 						\
>> +	|((((CONFIG_SYS_FREQ/CONFIG_USB_FREQ)-1)&0x07)<<26)	\
>> +	|((((CONFIG_SYS_FREQ/CONFIG_SYS_BUS_FREQ)-1)&0x0F)<<10))
>> +
> 
> This macro (and the following ones) are related to the IMX processor and
> are not specific to the board. They should be available for all IMX
> boards, and the right place is arch/arm/include/asm/arch-imx/.
> 


This macro and some others are specific to the iMX1/L cpu that is not any more recommended for new design by Freescale.
For a technical point of view I am fully is agreement with you but IMHO no maintainer will take the risk to rework deeply its implementation of U-boot for a CPU at the end of life. I apologize if I am wrong and will support the other mx1 board maintainers to improve the iMX1 boards.
For the next boards based on the iMX2 and 5  processors, we will put stuffs at the right place to make it available for the other boards.

Thanks a lot for the your time and all your feedbacks.

Best regards,
Eric


   

[U-Boot] [PATCH 5/9] apf9328: add default board configuration file

[Stefano Babic]

On 08/15/2011 10:25 PM, Eric Jarrige wrote:
> Hi Stefano,

Hi Eric,

sorry for my late answer. I have missed a point.

>>> +#define CONFIG_EXTRA_ENV_SETTINGS \
>>> +	"env_version="		CONFIG_ENV_VERSION		"\0"	\
>>> +	"fileaddr="		MK_STR(CONFIG_SYS_LOAD_ADDR)	"\0"	\
>>> +	"filesize="		MK_STR(CONFIG_SYS_MONITOR_LEN)	"\0"	\
>>
>> filesize is dynamically computed, you should not add it
> 
> We need this variable already initialized at boot time to support the specific imx boot mode from serial port when the user lost the full content of the flash.
> In such case (that is a stressing situation for the user) he can push U-Boot through the serial port and use directly the script "flash_uboot" to recover the original content of the flash. In such a use case this variable is not dynamically computed.

By the way, you reach the same behavior adding a new variable (such as
"monitor_size") with the default value you want and use it in your
scripts. filesize is a special variable in u-boot and it sounds odd to
fix it.

>> Please drop fix ip address. They should not be part of mainline,
> 
> Here, I have a problem as our documentation on the wiki armadeus.org is based on this default IP addresses.
> We really need a set of default IP addresses for private network to simplify as much as possible the life of the armadeus project developers. 
> I never seen such a restriction in U-Boot doc and moreover there is a set CONFIG_XXIP documented in U-BOOT that confusing me,
> Is there another solution for a complete usable default configuration?

Well, you will find a lot of NAK for patches that set fix IP addresses
in the ML. Even if this default address is described in your
documentation, what happens if two users of yours, as you say they are
newbies, attach their board to the same LAN using the same "default"
address ? Is it not better to explain them they need a *correct* ip
address ?

A default IP address simply does not exist and requires to have a
"default" network (192.168.0.x), with "default" netmask...

If you want to simplify the setup for your users, add dhcp.

> 16MiB is the regular configuration but there are many configurations of boards with different size of memory.
> This set of parameters enables to support every boards at compilation by just changing the value of CONFIG_SYS_SDRAM_MBYTE_SYZE.
> So that the binary generated is fully optimized for each board.

Understood, thanks.

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH 5/9] apf9328: add default board configuration file

[Eric Jarrige]

Hi Stefano,

On 23 ao?t 2011, at 11:46, Stefano Babic wrote:

> 
> 
> sorry for my late answer. I have missed a point.

No problem on my side - my answers are sometime even longer.

> 
>>> Please drop fix ip address. They should not be part of mainline,
>> 
>> Here, I have a problem as our documentation on the wiki armadeus.org is based on this default IP addresses.
>> We really need a set of default IP addresses for private network to simplify as much as possible the life of the armadeus project developers. 
>> I never seen such a restriction in U-Boot doc and moreover there is a set CONFIG_XXIP documented in U-BOOT that confusing me,
>> Is there another solution for a complete usable default configuration?
> 
> Well, you will find a lot of NAK for patches that set fix IP addresses
> in the ML. Even if this default address is described in your
> documentation, what happens if two users of yours, as you say they are
> newbies, attach their board to the same LAN using the same "default"
> address ?

Ok, I missed these threads regarding IP address.
My recommendation for two or more developer is (was) to use each one its
own private network for the development using a dedicated
ethernet interface.

> Is it not better to explain them they need a *correct* ip
> address ?

Sure - That's the reason DHCP is also enable

Cheers,
Eric

[U-Boot] [PATCH 5/9] apf9328: add default board configuration file

[Wolfgang Denk]

Dear Eric Jarrige,

can you please mind your line length?  It is strongly recommended that
text lines should not exceed 70 characters or so.  Thanks.

In message <1FAD4112-2A57-415D-9CDF-8FC7A9EDB626@armadeus.org> you wrote:

> >> +#define CONFIG_EXTRA_ENV_SETTINGS \
> >> +	"env_version="		CONFIG_ENV_VERSION		"\0"	\
> >> +	"fileaddr="		MK_STR(CONFIG_SYS_LOAD_ADDR)	"\0"	\
> >> +	"filesize="		MK_STR(CONFIG_SYS_MONITOR_LEN)	"\0"	\
> > 
> > filesize is dynamically computed, you should not add it
> 
> We need this variable already initialized at boot time to support the specific imx boot mode from serial port when the user lost the full content of the flash.

Stefano is right.  "filesize" and "fileaddr" are dynamic variables,
thet get created and updated on the fly. It makes no sense to
pre-define them to any specific value. [Actually I have some changes
in mind that avoid to save such variables with the environment at
all.]

> In such case (that is a stressing situation for the user) he can push U-Boot through the serial port and use directly the script "flash_uboot" to recover the original content of the flash. In such a use case this variable is not dynamically computed.

What do you mean by "push U-Boot through the serial port"?  Any of the
respective commands in U-Boot ("loads", "loadb", "loady") will
automatically update the respective variables.

> >> +#define CONFIG_NETMASK		255.255.255.0
> >> +#define CONFIG_IPADDR		192.168.000.10
> > 
> > Please drop fix ip address. They should not be part of mainline,
> 
> Here, I have a problem as our documentation on the wiki armadeus.org is based on this default IP addresses.

Then fix the documentation?

It is a somewhat bad idea to publish documentation to end users before
the code has passed even the inital code review...

> We really need a set of default IP addresses for private network to simplify as much as possible the life of the armadeus project developers. 

And what makes you think that 192.168.0.10 might be a free IP address
in my network?  Or assume that 255.255.255.0 is the right netmask in
this network?

These addresses may work for you, but they will not work for others,
and thus it makes no sense to use them as defaults.

If you need a reasonable default, then configure the board to use
DHCP.

> I never seen such a restriction in U-Boot doc and moreover there is a set CONFIG_XXIP documented in U-BOOT that confusing me,

There are situations where this cannot be avoided - like when U-Boot
is installed in a ROM, where the environment cannot be changed at all,
and where for some reason DHCP or similar is not possible.  But that
does not mean that this makes sense for the generic case.

> Is there another solution for a complete usable default configuration?

Use DHCP?

> > Why do we need such a stuff when your configuration is fixed at compile
> > time with CONFIG_SYS_SDRAM_MBYTE_SYZE 16 ?
> 
> 16MiB is the regular configuration but there are many configurations of boards with different size of memory.
> This set of parameters enables to support every boards at compilation by just changing the value of CONFIG_SYS_SDRAM_MBYTE_SYZE.
> So that the binary generated is fully optimized for each board.

That's a maintenance nightmage for everybody and not needed at all.

Please use get_ram_size() to have U-Boot auto-adjust to the actual RAM
size of your board and forget about all such static "optimizations".

> >> +#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE	\
> >> +		+ CONFIG_SYS_SDRAM_1_SIZE - 0x0100000)
> > 
> > You do not use U_Boot macro here (GENERATED_GBL_DATA_SIZE), as it is
> > usual. Stack pointer is already in RAM before relocation. Is it correct ?
> 
> Correct. I do have to optimize the location of the initial Stack pointer  for my board so I put the init SP at any safe place in RAM.

I find your answers not really helpful and constructive.  You write
you "have to optimize the location", but you fail to explain why you
think so.  I consider it likely that you are wrong about the optimize
part.  And you are definitely wrong about the rest, as you obviously
did not understand Stefano's comment at all - he was referring to the
magic constant 0x0100000 in above macro.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
: 1.  What is the possibility of this being added in the future?
In the near future, the probability is close to zero. In the  distant
future, I'll be dead, and posterity can do whatever they like... :-)
                                                              - lwall

[U-Boot] [PATCH 5/9] apf9328: add default board configuration file

[Eric Jarrige]

Dear Wolfgang, Dear Stefano,

On 23 ao?t 2011, at 13:26, Wolfgang Denk wrote:

> Dear Eric Jarrige,
> 
> can you please mind your line length?  It is strongly recommended that
> text lines should not exceed 70 characters or so.  Thanks.

I will take care of that. I do apologize for the inconvenient.

> 
> In message <1FAD4112-2A57-415D-9CDF-8FC7A9EDB626@armadeus.org> you wrote:
> 
>>>> +#define CONFIG_EXTRA_ENV_SETTINGS \
>>>> +	"env_version="		CONFIG_ENV_VERSION		"\0"	\
>>>> +	"fileaddr="		MK_STR(CONFIG_SYS_LOAD_ADDR)	"\0"	\
>>>> +	"filesize="		MK_STR(CONFIG_SYS_MONITOR_LEN)	"\0"	\
>>> 
>>> filesize is dynamically computed, you should not add it
>> 
>> We need this variable already initialized at boot time to support the specific imx boot mode from serial port when the user lost the full content of the flash.
> 
> Stefano is right.  "filesize" and "fileaddr" are dynamic variables,
> thet get created and updated on the fly. It makes no sense to
> pre-define them to any specific value. [Actually I have some changes
> in mind that avoid to save such variables with the environment at
> all.]

I understand - It make sense for me to wait for the new interface. 

> 
>> In such case (that is a stressing situation for the user) he can push U-Boot through the serial port and use directly the script "flash_uboot" to recover the original content of the flash. In such a use case this variable is not dynamically computed.
> 
> What do you mean by "push U-Boot through the serial port"?  Any of the
> respective commands in U-Boot ("loads", "loadb", "loady") will
> automatically update the respective variables.

I meant  to boot using the iMX internal bootstrap loader as U-Boot is not
yet running. Alternatively I can download U-Boot a second time to have
the environment variables initialized. 
It is just a longer process than the original one.

> 
>>>> +#define CONFIG_NETMASK		255.255.255.0
>>>> +#define CONFIG_IPADDR		192.168.000.10
>>> 
>>> Please drop fix ip address. They should not be part of mainline,
>> 
>> Here, I have a problem as our documentation on the wiki armadeus.org is based on this default IP addresses.
> 
> Then fix the documentation?

That is something we will do in any case.

> 
> It is a somewhat bad idea to publish documentation to end users before
> the code has passed even the inital code review...

Thanks for the recommendation.

> 
>> We really need a set of default IP addresses for private network to simplify as much as possible the life of the armadeus project developers. 
> 
> And what makes you think that 192.168.0.10 might be a free IP address
> in my network?  Or assume that 255.255.255.0 is the right netmask in
> this network?

http://tools.ietf.org/html/rfc1918#page-4

> 
> These addresses may work for you, but they will not work for others,
> and thus it makes no sense to use them as defaults.

The armadeus BSP provide a user interface to customize the network
parameters according to end user network environment.

> 
> If you need a reasonable default, then configure the board to use
> DHCP.
> 
>> I never seen such a restriction in U-Boot doc and moreover there is a set CONFIG_XXIP documented in U-BOOT that confusing me,
> 
> There are situations where this cannot be avoided - like when U-Boot
> is installed in a ROM, where the environment cannot be changed at all,
> and where for some reason DHCP or similar is not possible.  But that
> does not mean that this makes sense for the generic case.
> 
>> Is there another solution for a complete usable default configuration?
> 
> Use DHCP?

Sure, DHCP is the best *technical* solution.
I meant for static IP address?

> 
>>> Why do we need such a stuff when your configuration is fixed at compile
>>> time with CONFIG_SYS_SDRAM_MBYTE_SYZE 16 ?
>> 
>> 16MiB is the regular configuration but there are many configurations of boards with different size of memory.
>> This set of parameters enables to support every boards at compilation by just changing the value of CONFIG_SYS_SDRAM_MBYTE_SYZE.
>> So that the binary generated is fully optimized for each board.
> 
> That's a maintenance nightmage for everybody and not needed at all.
> 
> Please use get_ram_size() to have U-Boot auto-adjust to the actual RAM
> size of your board and forget about all such static "optimizations".

Thanks for the update. 

> 
>>>> +#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE	\
>>>> +		+ CONFIG_SYS_SDRAM_1_SIZE - 0x0100000)
>>> 
>>> You do not use U_Boot macro here (GENERATED_GBL_DATA_SIZE), as it is
>>> usual. Stack pointer is already in RAM before relocation. Is it correct ?
>> 
>> Correct. I do have to optimize the location of the initial Stack pointer  for my board so I put the init SP at any safe place in RAM.
> 
> I find your answers not really helpful and constructive.  You write
> you "have to optimize the location", but you fail to explain why you
> think so.  I consider it likely that you are wrong about the optimize
> part.  And you are definitely wrong about the rest, as you obviously
> did not understand Stefano's comment at all - he was referring to the
> magic constant 0x0100000 in above macro.

Thanks for the clarification - by pointing the constant 0x0100000 
I understand the message - So forget my previous answer.

For the rest, we will look for the best compromised solution  for everyone.

Best regards,
Eric

[U-Boot] [PATCH 5/9] apf9328: add default board configuration file

[Wolfgang Denk]

Dear Eric Jarrige,

In message <D25738A8-8A7A-475A-95F5-8408C6463F4D@armadeus.org> you wrote:
> 
> > Stefano is right.  "filesize" and "fileaddr" are dynamic variables,
> > thet get created and updated on the fly. It makes no sense to
> > pre-define them to any specific value. [Actually I have some changes
> > in mind that avoid to save such variables with the environment at
> > all.]
> 
> I understand - It make sense for me to wait for the new interface. 

Which new interface do you mean?  And why would waiting for it help
you?

> > What do you mean by "push U-Boot through the serial port"?  Any of the
> > respective commands in U-Boot ("loads", "loadb", "loady") will
> > automatically update the respective variables.
> 
> I meant  to boot using the iMX internal bootstrap loader as U-Boot is
> not
> yet running. Alternatively I can download U-Boot a second time to have
> the environment variables initialized. 
> It is just a longer process than the original one.

Are you aware of things like "env import" etc.?

> > And what makes you think that 192.168.0.10 might be a free IP address
> > in my network?  Or assume that 255.255.255.0 is the right netmask in
> > this network?
> 
> http://tools.ietf.org/html/rfc1918#page-4

This page lists "192.168/16 prefix", i. e. a 255.255.0.0 netmask.
I know many development environments, and 192.168.x.x is used very,
very often there. often with a /24 netmask, sometimes differently (at
DENX we're using it with a /16 netmast, for example).  

And there is absolutely NO guarantee that 192.168.0.10 is free, or
that multiple users of your boards will boot simultaneously, or ...

The _concept_ of such a default address is broken.

> > These addresses may work for you, but they will not work for others,
> > and thus it makes no sense to use them as defaults.
> 
> The armadeus BSP provide a user interface to customize the network
> parameters according to end user network environment.

Do you know the amount of efforts needed in any bigger organization
to set up additional or to change existing network configurations?

> > Use DHCP?
> 
> Sure, DHCP is the best *technical* solution.
> I meant for static IP address?

Why does anybody need static IP addresses for the default case, i. e.
for system bring up?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Prof:        So the American government went to IBM to come up with a
             data encryption standard and they came up with ...
Student:     EBCDIC!

[U-Boot] [PATCH 5/9] apf9328: add default board configuration file

[Wolfgang Denk]

Dear Eric,

In message <20110824054915.0860711F9E75@gemini.denx.de> I wrote:
> 
> > Sure, DHCP is the best *technical* solution.
> > I meant for static IP address?
> 
> Why does anybody need static IP addresses for the default case, i. e.
> for system bring up?

And if you need one, what is the issue with using "setenv ipaddr" at
the serial console?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Don't put off for tomorrow what you can  do  today,  because  if  you
enjoy it today you can do it again tomorrow.

[U-Boot] [PATCH 5/9] apf9328: add default board configuration file

[Eric Jarrige]

Dear Wolfgang,

On 24 ao?t 2011, at 08:34, Wolfgang Denk wrote:

> Dear Eric,
> 
> In message <20110824054915.0860711F9E75@gemini.denx.de> I wrote:
>> 
>>> Sure, DHCP is the best *technical* solution.
>>> I meant for static IP address?
>> 
>> Why does anybody need static IP addresses for the default case, i. e.
>> for system bring up?
> 
> And if you need one, what is the issue with using "setenv ipaddr" at
> the serial console?
> 

The hobbyists working on U-Boot  will ask to have this command
in a their default configuration to simplify their development
process. I will be the first of them to request a user friendly solution.
I will check the 2 solutions: DHCP and "env import" when DHCP
is not applicable.

Thanks for your suggestion.

Best regards,
Eric

[U-Boot] [PATCH 5/9] apf9328: add default board configuration file

[Eric Jarrige]

Dear Wolfgang,

On 24 ao?t 2011, at 07:49, Wolfgang Denk wrote:

> Dear Eric Jarrige,
> 
> In message <D25738A8-8A7A-475A-95F5-8408C6463F4D@armadeus.org> you wrote:
>> 
>>> Stefano is right.  "filesize" and "fileaddr" are dynamic variables,
>>> thet get created and updated on the fly. It makes no sense to
>>> pre-define them to any specific value. [Actually I have some changes
>>> in mind that avoid to save such variables with the environment at
>>> all.]
>> 
>> I understand - It make sense for me to wait for the new interface. 
> 
> Which new interface do you mean?  And why would waiting for it help
> you?

By interface I mean the changes you mentioned to avoid to have "filesize"
and "fileaddr" with the environment variables.


> 
>>> What do you mean by "push U-Boot through the serial port"?  Any of the
>>> respective commands in U-Boot ("loads", "loadb", "loady") will
>>> automatically update the respective variables.
>> 
>> I meant  to boot using the iMX internal bootstrap loader as U-Boot is
>> not
>> yet running. Alternatively I can download U-Boot a second time to have
>> the environment variables initialized. 
>> It is just a longer process than the original one.
> 
> Are you aware of things like "env import" etc.?

That could be the solution. I have to check it.
Thanks for the update.

> 
>>> And what makes you think that 192.168.0.10 might be a free IP address
>>> in my network?  Or assume that 255.255.255.0 is the right netmask in
>>> this network?
>> 
>> http://tools.ietf.org/html/rfc1918#page-4
> 
> This page lists "192.168/16 prefix", i. e. a 255.255.0.0 netmask.
> I know many development environments, and 192.168.x.x is used very,
> very often there. often with a /24 netmask, sometimes differently (at
> DENX we're using it with a /16 netmast, for example).  

"192.168/16 prefix" is only the prefix of the class C private networks.
IMHO that means there are 256 class C networks  (255.255.255.0)  reserved
for private networks as mentioned on the same RFC page by
"..and third block is a set of 256 contiguous class C network numbers"

In the same way, there is another address range 172.16 - 172.31 dedicated class B
private networks for the organization who need /16 netmask.

> 
> And there is absolutely NO guarantee that 192.168.0.10 is free, or
> that multiple users of your boards will boot simultaneously, or ...
> 
> The _concept_ of such a default address is broken.
> 
>>> These addresses may work for you, but they will not work for others,
>>> and thus it makes no sense to use them as defaults.
>> 
>> The armadeus BSP provide a user interface to customize the network
>> parameters according to end user network environment.
> 
> Do you know the amount of efforts needed in any bigger organization
> to set up additional or to change existing network configurations?

I meant our BSP enable to change U-Boot default configuration of the
board to fit the existing networks of the end users/developpers -
not to change the network configuration of any organization. 

> 
>>> Use DHCP?
>> 
>> Sure, DHCP is the best *technical* solution.
>> I meant for static IP address?
> 
> Why does anybody need static IP addresses for the default case, i. e.
> for system bring up?

Well, may be things can be easier to explain with static IP than explaining
how to setup a DHCP server, DNS server....

Anyway we will work more on the DHCP solution if this solution is
acceptable.

Best regards,
Eric



 

[U-Boot] [PATCH 5/9] apf9328: add default board configuration file

[Wolfgang Denk]

Dear Eric Jarrige,

In message <8F000DEB-1AFC-403B-9B00-FA2BFF2E1193@armadeus.org> you wrote:
> 
> > Which new interface do you mean?  And why would waiting for it help
> > you?
>
> By interface I mean the changes you mentioned to avoid to have "filesize"
> and "fileaddr" with the environment variables.

Don't expect this any time soon.  Also, I don't see how this would
have any influence on your situation.

All I want to tell you is that it's not a good idea to rely on
pre-initialization of such dynamically set variables.

> "192.168/16 prefix" is only the prefix of the class C private networks.
> IMHO that means there are 256 class C networks  (255.255.255.0)  reserved
> for private networks as mentioned on the same RFC page by
> "..and third block is a set of 256 contiguous class C network numbers"

I can split the 192.168/16 range in any way I like.  We use it as a
single 255.255.0.0 masked network.  I could as well define it as for 
192.168/18 nets, or whatever comes to my mind.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Mirrors should reflect a little before throwing back images.
- Jean Cocteau

[U-Boot] [PATCH 5/9] apf9328: add default board configuration file

[Stefano Babic]

On 08/24/2011 06:56 AM, Eric Jarrige wrote:
> Dear Wolfgang, Dear Stefano,

Hi Eric,

>>> We really need a set of default IP addresses for private network to simplify as much as possible the life of the armadeus project developers. 
>>
>> And what makes you think that 192.168.0.10 might be a free IP address
>> in my network?  Or assume that 255.255.255.0 is the right netmask in
>> this network?
> 
> http://tools.ietf.org/html/rfc1918#page-4

Really RFC1918 reservs only IP addresses for private use, but there is
nothing regarding a "default" IP address. And nothing different as usual
how to assign the addresses to the hosts.

To set a static IP address when DHCP is not available (a sort of
autoconfiguration without DHCP server), the link-local address range
should be used (169.254.0.0/16), described in
http://tools.ietf.org/html/rfc3927.
It sets a random IP in the range and checks with ARP that the address is
not already used in the network. However, it is outside the goals of a
bootloader ;-)

Best regards,
Stefano babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH 5/9] apf9328: add default board configuration file

[Eric Jarrige]

Hi Stefano,

On 24 ao?t 2011, at 08:22, Stefano Babic wrote:

> On 08/24/2011 06:56 AM, Eric Jarrige wrote:
>> Dear Wolfgang, Dear Stefano,
> 
> Hi Eric,
> 
>>>> We really need a set of default IP addresses for private network to simplify as much as possible the life of the armadeus project developers. 
>>> 
>>> And what makes you think that 192.168.0.10 might be a free IP address
>>> in my network?  Or assume that 255.255.255.0 is the right netmask in
>>> this network?
>> 
>> http://tools.ietf.org/html/rfc1918#page-4
> 
> Really RFC1918 reservs only IP addresses for private use, but there is
> nothing regarding a "default" IP address. And nothing different as usual
> how to assign the addresses to the hosts.
> 
> To set a static IP address when DHCP is not available (a sort of
> autoconfiguration without DHCP server), the link-local address range
> should be used (169.254.0.0/16), described in
> http://tools.ietf.org/html/rfc3927.
> It sets a random IP in the range and checks with ARP that the address is
> not already used in the network. However, it is outside the goals of a
> bootloader ;-)

Correct, U-Boot does not support this protocol that is moreover limited
to devices "directly connected to the same physical/logical link".

Best regards,
Eric

[U-Boot] [PATCH 5/9] apf9328: add default board configuration file

[Wolfgang Denk]

Dear Eric Jarrige,

In message <20110810203325.21204.6037.stgit@shuttle2.etheralp.ch> you wrote:
> Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org>
> ---
>  include/configs/apf9328.h | 1034 +++++++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 1034 insertions(+), 0 deletions(-)
>  create mode 100644 include/configs/apf9328.h

Checkpatch says:

total: 0 errors, 142 warnings, 1034 lines checked

Please clean up and resubmit.  Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Never worry about theory as long as  the  machinery  does  what  it's
supposed to do.                                      - R. A. Heinlein

[U-Boot] [PATCH 6/9] mx1: improve PLL freq computation

[Eric Jarrige]

Improve PLL freq computation by using the full resolution of the PLL registers

Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org>
Cc: Stefano Babic <sbabic@denx.de>
---
 arch/arm/cpu/arm920t/imx/speed.c |   29 +++++++++++------------------
 1 files changed, 11 insertions(+), 18 deletions(-)

diff --git a/arch/arm/cpu/arm920t/imx/speed.c b/arch/arm/cpu/arm920t/imx/speed.c
index 1e29698..b1c2bd6 100644
--- a/arch/arm/cpu/arm920t/imx/speed.c
+++ b/arch/arm/cpu/arm920t/imx/speed.c
@@ -36,33 +36,26 @@
  * the specified bus in HZ.
  */
 /* ------------------------------------------------------------------------- */
-
-ulong get_systemPLLCLK(void)
+static ulong get_PLLCLK(u32 sys_clk_freq, u32 pllctl0)
 {
 	/* FIXME: We assume System_SEL = 0 here */
-	u32 spctl0 = SPCTL0;
-	u32 mfi = (spctl0 >> 10) & 0xf;
-	u32 mfn = spctl0 & 0x3f;
-	u32 mfd = (spctl0 >> 16) & 0x3f;
-	u32 pd =  (spctl0 >> 26) & 0xf;
+	u32 mfi = (pllctl0 >> 10) & 0xf;
+	u32 mfn = pllctl0 & 0x3ff;
+	u32 mfd = (pllctl0 >> 16) & 0x3ff;
+	u32 pd =  (pllctl0 >> 26) & 0xf;
 
 	mfi = mfi<=5 ? 5 : mfi;
+	return (2*(u64)sys_clk_freq * (mfi*(mfd+1) + mfn))/((mfd+1)*(pd+1));
+}
 
-	return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
+ulong get_systemPLLCLK(void)
+{
+	return get_PLLCLK(CONFIG_SYSPLL_CLK_FREQ, SPCTL0);
 }
 
 ulong get_mcuPLLCLK(void)
 {
-	/* FIXME: We assume System_SEL = 0 here */
-	u32 mpctl0 = MPCTL0;
-	u32 mfi = (mpctl0 >> 10) & 0xf;
-	u32 mfn = mpctl0 & 0x3f;
-	u32 mfd = (mpctl0 >> 16) & 0x3f;
-	u32 pd =  (mpctl0 >> 26) & 0xf;
-
-	mfi = mfi<=5 ? 5 : mfi;
-
-	return (2*(CONFIG_SYS_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
+	return get_PLLCLK(CONFIG_SYS_CLK_FREQ, MPCTL0);
 }
 
 ulong get_FCLK(void)

[U-Boot] [PATCH 6/9] mx1: improve PLL freq computation

[Stefano Babic]

On 08/10/2011 10:33 PM, Eric Jarrige wrote:
> Improve PLL freq computation by using the full resolution of the PLL registers

Hi Eric,

> +	return (2*(u64)sys_clk_freq * (mfi*(mfd+1) + mfn))/((mfd+1)*(pd+1));
> +}
>  
> -	return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);

Please run checkpatch on your patches for V2. I have not yet done, but
this line will report missing spaces.

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office@denx.de
=====================================================================

[U-Boot] [PATCH 6/9] mx1: improve PLL freq computation

[Eric Jarrige]

Hi Stefano,

On 11 ao?t 2011, at 11:22, Stefano Babic wrote:

> On 08/10/2011 10:33 PM, Eric Jarrige wrote:
>> Improve PLL freq computation by using the full resolution of the PLL registers
> 
> Hi Eric,
> 
>> +	return (2*(u64)sys_clk_freq * (mfi*(mfd+1) + mfn))/((mfd+1)*(pd+1));
>> +}
>> 
>> -	return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
> 
> Please run checkpatch on your patches for V2. I have not yet done, but
> this line will report missing spaces.
> 
I did it and had no error and no warning:

Here is the ourput of checkpatch.pl:
<
armadeus/buildroot/output/build/linux-3.0.1/scripts/checkpatch.pl ../../../target/u-boot/git/09-arm920t-relocation.patch 
total: 0 errors, 0 warnings, 10 lines checked

../../../target/u-boot/git/09-arm920t-relocation.patch has no obvious style problems and is ready for submission.
>

[U-Boot] [PATCH 6/9] mx1: improve PLL freq computation

[Eric Jarrige]

Hi Stefano,
> 
> On 11 ao?t 2011, at 11:22, Stefano Babic wrote:
> 
>> On 08/10/2011 10:33 PM, Eric Jarrige wrote:
>>> Improve PLL freq computation by using the full resolution of the PLL registers
>> 
>> Hi Eric,
>> 
>>> +	return (2*(u64)sys_clk_freq * (mfi*(mfd+1) + mfn))/((mfd+1)*(pd+1));
>>> +}
>>> 
>>> -	return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
>> 
>> Please run checkpatch on your patches for V2. I have not yet done, but
>> this line will report missing spaces.
>> 
> I did it and had no error and no warning:
> 


Here is the report of checkpatch.pl on [PATCH 6/9] this time :

armadeus/buildroot/output/build/linux-3.0.1/scripts/checkpatch.pl ../../../target/u-boot/git/06-mx1-pllclk.patch 
total: 0 errors, 0 warnings, 44 lines checked

../../../target/u-boot/git/06-mx1-pllclk.patch has no obvious style problems and is ready for submission.


Cheers,
Eric

[U-Boot] [PATCH 6/9] mx1: improve PLL freq computation

[Stefano Babic]

On 08/12/2011 02:03 AM, Eric Jarrige wrote:
> Hi Stefano,
> 
> On 11 ao?t 2011, at 11:22, Stefano Babic wrote:
> 
>> On 08/10/2011 10:33 PM, Eric Jarrige wrote:
>>> Improve PLL freq computation by using the full resolution of the PLL registers
>>
>> Hi Eric,
>>
>>> +	return (2*(u64)sys_clk_freq * (mfi*(mfd+1) + mfn))/((mfd+1)*(pd+1));
>>> +}
>>>
>>> -	return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
>>
>> Please run checkpatch on your patches for V2. I have not yet done, but
>> this line will report missing spaces.
>>
> I did it and had no error and no warning:
> 
> Here is the ourput of checkpatch.pl:
> <
> armadeus/buildroot/output/build/linux-3.0.1/scripts/checkpatch.pl ../../../target/u-boot/git/09-arm920t-relocation.patch 
> total: 0 errors, 0 warnings, 10 lines checked

Then forget my comment. I did not yet run checkpatch on your patches.

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH 7/9] mx1: change a printf in speed.c to use debug instead

[Eric Jarrige]

Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org>
Cc: Stefano Babic <sbabic@denx.de>
---
 arch/arm/cpu/arm920t/imx/speed.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/cpu/arm920t/imx/speed.c b/arch/arm/cpu/arm920t/imx/speed.c
index b1c2bd6..b8e42bf 100644
--- a/arch/arm/cpu/arm920t/imx/speed.c
+++ b/arch/arm/cpu/arm920t/imx/speed.c
@@ -67,7 +67,7 @@ ulong get_FCLK(void)
 ulong get_HCLK(void)
 {
 	u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1;
-	printf("bclkdiv: %d\n", bclkdiv);
+	debug("bclkdiv: %d\n", bclkdiv);
 	return get_systemPLLCLK() / bclkdiv;
 }
 

[U-Boot] [PATCH 8/9] DM9000: change some printf to use debug instead

[Eric Jarrige]

Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org>
Cc: Ben Warren <biggerbadderben@gmail.com>
---
 drivers/net/dm9000x.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c
index b5c5573..9cd0195 100644
--- a/drivers/net/dm9000x.c
+++ b/drivers/net/dm9000x.c
@@ -232,7 +232,7 @@ dm9000_probe(void)
 	id_val |= DM9000_ior(DM9000_PIDL) << 16;
 	id_val |= DM9000_ior(DM9000_PIDH) << 24;
 	if (id_val == DM9000_ID) {
-		printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
+		DM9000_DBG("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
 		       id_val);
 		return 0;
 	} else {
@@ -298,19 +298,19 @@ static int dm9000_init(struct eth_device *dev, bd_t *bd)
 
 	switch (io_mode) {
 	case 0x0:  /* 16-bit mode */
-		printf("DM9000: running in 16 bit mode\n");
+		DM9000_DBG("DM9000: running in 16 bit mode\n");
 		db->outblk    = dm9000_outblk_16bit;
 		db->inblk     = dm9000_inblk_16bit;
 		db->rx_status = dm9000_rx_status_16bit;
 		break;
 	case 0x01:  /* 32-bit mode */
-		printf("DM9000: running in 32 bit mode\n");
+		DM9000_DBG("DM9000: running in 32 bit mode\n");
 		db->outblk    = dm9000_outblk_32bit;
 		db->inblk     = dm9000_inblk_32bit;
 		db->rx_status = dm9000_rx_status_32bit;
 		break;
 	case 0x02: /* 8 bit mode */
-		printf("DM9000: running in 8 bit mode\n");
+		DM9000_DBG("DM9000: running in 8 bit mode\n");
 		db->outblk    = dm9000_outblk_8bit;
 		db->inblk     = dm9000_inblk_8bit;
 		db->rx_status = dm9000_rx_status_8bit;

[U-Boot] [PATCH 8/9] DM9000: change some printf to use debug instead

[Simon Schwarz]

Dear Eric Jarrige,

On 08/10/2011 10:33 PM, Eric Jarrige wrote:
> Signed-off-by: Eric Jarrige<eric.jarrige@armadeus.org>
> Cc: Ben Warren<biggerbadderben@gmail.com>
> ---
>   drivers/net/dm9000x.c |    8 ++++----
>   1 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c
> index b5c5573..9cd0195 100644
> --- a/drivers/net/dm9000x.c
> +++ b/drivers/net/dm9000x.c
> @@ -232,7 +232,7 @@ dm9000_probe(void)
>   	id_val |= DM9000_ior(DM9000_PIDL)<<  16;
>   	id_val |= DM9000_ior(DM9000_PIDH)<<  24;
>   	if (id_val == DM9000_ID) {
> -		printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
> +		DM9000_DBG("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
>   		       id_val);
>   		return 0;
>   	} else {
> @@ -298,19 +298,19 @@ static int dm9000_init(struct eth_device *dev, bd_t *bd)
>
>   	switch (io_mode) {
>   	case 0x0:  /* 16-bit mode */
> -		printf("DM9000: running in 16 bit mode\n");
> +		DM9000_DBG("DM9000: running in 16 bit mode\n");
<snip>

I'am just wondering: I see that DM9000_DBG is used all over dm9000 code 
- do you know the reason why not just use debug()?

Regards
Simon

[U-Boot] [PATCH 8/9] DM9000: change some printf to use debug instead

[Detlev Zundel]

Hi Simon,

> Dear Eric Jarrige,
>
> On 08/10/2011 10:33 PM, Eric Jarrige wrote:
>> Signed-off-by: Eric Jarrige<eric.jarrige@armadeus.org>
>> Cc: Ben Warren<biggerbadderben@gmail.com>
>> ---
>>   drivers/net/dm9000x.c |    8 ++++----
>>   1 files changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c
>> index b5c5573..9cd0195 100644
>> --- a/drivers/net/dm9000x.c
>> +++ b/drivers/net/dm9000x.c
>> @@ -232,7 +232,7 @@ dm9000_probe(void)
>>   	id_val |= DM9000_ior(DM9000_PIDL)<<  16;
>>   	id_val |= DM9000_ior(DM9000_PIDH)<<  24;
>>   	if (id_val == DM9000_ID) {
>> -		printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
>> +		DM9000_DBG("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
>>   		       id_val);
>>   		return 0;
>>   	} else {
>> @@ -298,19 +298,19 @@ static int dm9000_init(struct eth_device *dev, bd_t *bd)
>>
>>   	switch (io_mode) {
>>   	case 0x0:  /* 16-bit mode */
>> -		printf("DM9000: running in 16 bit mode\n");
>> +		DM9000_DBG("DM9000: running in 16 bit mode\n");
> <snip>
>
> I'am just wondering: I see that DM9000_DBG is used all over dm9000 code 
> - do you know the reason why not just use debug()?

Very likely only historical reasons as the code predates the DEBUG best
practice.  Bow that you've identified it, we should change it ;)

Cheers
  Detlev

-- 
It was actually a very beautiful thing to see a sunrise, cause' that's
such a calm time of day. It's a wonderful time of day  to get ready to
go to bed.
                                            -- Richard M. Stallman
--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: dzu at denx.de

[U-Boot] [PATCH 8/9] DM9000: change some printf to use debug instead

[Eric Jarrige]

Hi Simon, Hi Detlev,

> Hi Simon,
> 
>> Dear Eric Jarrige,
>> 
>> On 08/10/2011 10:33 PM, Eric Jarrige wrote:
>>> Signed-off-by: Eric Jarrige<eric.jarrige@armadeus.org>
>>> Cc: Ben Warren<biggerbadderben@gmail.com>
>>> ---
>>>  drivers/net/dm9000x.c |    8 ++++----
>>>  1 files changed, 4 insertions(+), 4 deletions(-)
>>> 
>>> diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c
>>> index b5c5573..9cd0195 100644
>>> --- a/drivers/net/dm9000x.c
>>> +++ b/drivers/net/dm9000x.c
>>> @@ -232,7 +232,7 @@ dm9000_probe(void)
>>>  	id_val |= DM9000_ior(DM9000_PIDL)<<  16;
>>>  	id_val |= DM9000_ior(DM9000_PIDH)<<  24;
>>>  	if (id_val == DM9000_ID) {
>>> -		printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
>>> +		DM9000_DBG("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
>>>  		       id_val);
>>>  		return 0;
>>>  	} else {
>>> @@ -298,19 +298,19 @@ static int dm9000_init(struct eth_device *dev, bd_t *bd)
>>> 
>>>  	switch (io_mode) {
>>>  	case 0x0:  /* 16-bit mode */
>>> -		printf("DM9000: running in 16 bit mode\n");
>>> +		DM9000_DBG("DM9000: running in 16 bit mode\n");
>> <snip>
>> 
>> I'am just wondering: I see that DM9000_DBG is used all over dm9000 code 
>> - do you know the reason why not just use debug()?

dm9000 does not use debug() at all.
That's the reason to fix the printf issues as a first priority by using the DM9000_DBG.

> 
> Very likely only historical reasons as the code predates the DEBUG best
> practice.  Bow that you've identified it, we should change it ;)
> 
Cheers,
Eric

[U-Boot] [PATCH 8/9] DM9000: change some printf to use debug instead

[Wolfgang Denk]

Dear Eric Jarrige,

In message <2B613989-ADDB-43D6-A8C3-A30D5245262A@armadeus.org> you wrote:
> 
> >> I'am just wondering: I see that DM9000_DBG is used all over dm9000 code 
> >> - do you know the reason why not just use debug()?
> 
> dm9000 does not use debug() at all.
> That's the reason to fix the printf issues as a first priority by using the DM9000_DBG.

NAK.

If you touch that, then please do it right: us debug() instead, and
remove DM9000_DBG.  Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
When you say "I wrote a program that crashed  Windows",  people  just
stare  at you blankly and say "Hey, I got those with the system, *for
free*".        - Linus Torvalds in <3itc77$9lj@ninurta.fer.uni-lj.si>

[U-Boot] [PATCH 8/9] DM9000: change some printf to use debug instead

[Eric Jarrige]

Dear Wolfgang,

On 24 ao?t 2011, at 22:20, Wolfgang Denk wrote:

> Dear Eric Jarrige,
> 
> In message <2B613989-ADDB-43D6-A8C3-A30D5245262A@armadeus.org> you wrote:
>> 
>>>> I'am just wondering: I see that DM9000_DBG is used all over dm9000 code 
>>>> - do you know the reason why not just use debug()?
>> 
>> dm9000 does not use debug() at all.
>> That's the reason to fix the printf issues as a first priority by using the DM9000_DBG.
> 
> NAK.
> 
> If you touch that, then please do it right: us debug() instead, and
> remove DM9000_DBG.  Thanks.

Do you mean both changes in one patch?

Best regards,
Eric

[U-Boot] [PATCH 8/9] DM9000: change some printf to use debug instead

[Marek Vasut]

On Thursday, August 25, 2011 01:04:17 AM Eric Jarrige wrote:
> Dear Wolfgang,
> 
> On 24 ao?t 2011, at 22:20, Wolfgang Denk wrote:
> > Dear Eric Jarrige,
> > 
> > In message <2B613989-ADDB-43D6-A8C3-A30D5245262A@armadeus.org> you wrote:
> >>>> I'am just wondering: I see that DM9000_DBG is used all over dm9000
> >>>> code - do you know the reason why not just use debug()?
> >> 
> >> dm9000 does not use debug() at all.
> >> That's the reason to fix the printf issues as a first priority by using
> >> the DM9000_DBG.
> > 
> > NAK.
> > 
> > If you touch that, then please do it right: us debug() instead, and
> > remove DM9000_DBG.  Thanks.
> 
> Do you mean both changes in one patch?

My wild guess would be to FIRST fix the DM9000_DBG and NEXT convert these 
printf()s to debug()s.

Cheers

> 
> Best regards,
> Eric
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 8/9] DM9000: change some printf to use debug instead

[Wolfgang Denk]

Dear Eric Jarrige,

In message <683E266C-CDFB-4310-8145-1926C6FCCBD8@armadeus.org> you wrote:
> 
> > If you touch that, then please do it right: us debug() instead, and
> > remove DM9000_DBG.  Thanks.
> 
> Do you mean both changes in one patch?

Yes, please.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
When the ax entered the forest, the trees said, "The handle is one of
us!"                                               -- Turkish proverb

[U-Boot] [PATCH 8/9] DM9000: change some printf to use debug instead

[Stefano Babic]

On 08/10/2011 10:33 PM, Eric Jarrige wrote:
> Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org>
> Cc: Ben Warren <biggerbadderben@gmail.com>
> ---
>  drivers/net/dm9000x.c |    8 ++++----
>  1 files changed, 4 insertions(+), 4 deletions(-)

Hi Eric,

> -		printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
> +		DM9000_DBG("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
>  		       id_val);

This is a good choice to get rid of nasty DM9000_DBG replacing it with
the general debug() !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH 9/9] arm920t: Fix jump to the relocated board_init_r

[Eric Jarrige]

Jump to the relocated board_init_r according to the initial computation
and remove computation against current PC addr as relocated address is
already known and fixed.
This helps to support CPU that miror flash to different address at
power on boot such as Freescale iMX1/L

Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
---
 arch/arm/cpu/arm920t/start.S |    4 +---
 1 files changed, 1 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S
index c308420..5c75289 100644
--- a/arch/arm/cpu/arm920t/start.S
+++ b/arch/arm/cpu/arm920t/start.S
@@ -292,9 +292,7 @@ _nand_boot_ofs:
 	.word nand_boot
 #else
 	ldr	r0, _board_init_r_ofs
-	adr	r1, _start
-	add	lr, r0, r1
-	add	lr, lr, r9
+	add	lr, r0, r6
 	/* setup parameters for board_init_r */
 	mov	r0, r5		/* gd_t */
 	mov	r1, r6		/* dest_addr */