From: Will Deacon <will.deacon@arm.com> To: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com> Cc: Peter Zijlstra <peterz@infradead.org>, Linus Torvalds <torvalds@linux-foundation.org>, Victor Kaplansky <VICTORK@il.ibm.com>, Oleg Nesterov <oleg@redhat.com>, Anton Blanchard <anton@samba.org>, Benjamin Herrenschmidt <benh@kernel.crashing.org>, Frederic Weisbecker <fweisbec@gmail.com>, LKML <linux-kernel@vger.kernel.org>, Linux PPC dev <linuxppc-dev@ozlabs.org>, Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>, Michael Ellerman <michael@ellerman.id.au>, Michael Neuling <mikey@neuling.org>, "linux@arm.linux.org.uk" <linux@arm.linux.org.uk>, "schwidefsky@de.ibm.com" <schwidefsky@de.ibm.com>, "heiko.carstens@de.ibm.com" <heiko.carstens@de.ibm.com> Subject: Re: [RFC] arch: Introduce new TSO memory barrier smp_tmb() Date: Tue, 5 Nov 2013 14:05:48 +0000 [thread overview] Message-ID: <20131105140548.GD26895@mudshark.cambridge.arm.com> (raw) In-Reply-To: <20131104205344.GW3947@linux.vnet.ibm.com> On Mon, Nov 04, 2013 at 08:53:44PM +0000, Paul E. McKenney wrote: > On Mon, Nov 04, 2013 at 08:11:27PM +0100, Peter Zijlstra wrote: > Some comments below. I believe that opcodes need to be fixed for IA64. > I am unsure of the ifdefs and opcodes for arm64, but the ARM folks should > be able to tell us. [...] > > diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h > > index 60f15e274e6d..a804093d6891 100644 > > --- a/arch/arm/include/asm/barrier.h > > +++ b/arch/arm/include/asm/barrier.h > > @@ -53,10 +53,36 @@ > > #define smp_mb() barrier() > > #define smp_rmb() barrier() > > #define smp_wmb() barrier() > > + > > +#define smp_store_release(p, v) \ > > +do { \ > > + smp_mb(); \ > > + ACCESS_ONCE(p) = (v); \ > > +} while (0) > > + > > +#define smp_load_acquire(p, v) \ > > +do { \ > > + typeof(p) ___p1 = ACCESS_ONCE(p); \ > > + smp_mb(); \ > > + return ___p1; \ > > +} while (0) What data sizes do these accessors operate on? Assuming that we want single-copy atomicity (with respect to interrupts in the UP case), we probably want a check to stop people passing in things like structs. > > #else > > #define smp_mb() dmb(ish) > > #define smp_rmb() smp_mb() > > #define smp_wmb() dmb(ishst) > > + > > Seems like there should be some sort of #ifdef condition to distinguish > between these. My guess is something like: > > #if __LINUX_ARM_ARCH__ > 7 > > But I must defer to the ARM guys. For all I know, they might prefer > arch/arm to stick with smp_mb() and have arch/arm64 do the ldar and stlr. Yes. For arch/arm/, I'd rather we stick with the smp_mb() for the time being. We don't (yet) have any 32-bit ARMv8 support, and the efforts towards a single zImage could do without minor variations like this, not to mention the usual backlash I get whenever introducing something that needs a relatively recent binutils. > > +#define smp_store_release(p, v) \ > > +do { \ > > + asm volatile ("stlr %w0 [%1]" : : "r" (v), "r" (&p) : "memory");\ > > +} while (0) > > + > > +#define smp_load_acquire(p) \ > > +do { \ > > + typeof(p) ___p1; \ > > + asm volatile ("ldar %w0, [%1]" \ > > + : "=r" (___p1) : "r" (&p) : "memory"); \ > > + return ___p1; \ > > +} while (0) > > #endif > > > > #define read_barrier_depends() do { } while(0) > > diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h > > index d4a63338a53c..0da2d4ebb9a8 100644 > > --- a/arch/arm64/include/asm/barrier.h > > +++ b/arch/arm64/include/asm/barrier.h > > @@ -35,10 +35,38 @@ > > #define smp_mb() barrier() > > #define smp_rmb() barrier() > > #define smp_wmb() barrier() > > + > > +#define smp_store_release(p, v) \ > > +do { \ > > + smp_mb(); \ > > + ACCESS_ONCE(p) = (v); \ > > +} while (0) > > + > > +#define smp_load_acquire(p, v) \ > > +do { \ > > + typeof(p) ___p1 = ACCESS_ONCE(p); \ > > + smp_mb(); \ > > + return ___p1; \ > > +} while (0) > > + > > #else > > + > > #define smp_mb() asm volatile("dmb ish" : : : "memory") > > #define smp_rmb() asm volatile("dmb ishld" : : : "memory") > > #define smp_wmb() asm volatile("dmb ishst" : : : "memory") > > + > > +#define smp_store_release(p, v) \ > > +do { \ > > + asm volatile ("stlr %w0 [%1]" : : "r" (v), "r" (&p) : "memory");\ Missing comma between the operands. Also, that 'w' output modifier enforces a 32-bit store (same early question about sizes). Finally, it might be more efficient to use "=Q" for the addressing mode, rather than take the address of p manually. > > +} while (0) > > + > > +#define smp_load_acquire(p) \ > > +do { \ > > + typeof(p) ___p1; \ > > + asm volatile ("ldar %w0, [%1]" \ > > + : "=r" (___p1) : "r" (&p) : "memory"); \ > > + return ___p1; \ Similar comments here wrt Q constraint. Random other question: have you considered how these accessors should behave when presented with __iomem pointers? Will
WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will.deacon@arm.com> To: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com> Cc: Michael Neuling <mikey@neuling.org>, Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>, Peter Zijlstra <peterz@infradead.org>, "heiko.carstens@de.ibm.com" <heiko.carstens@de.ibm.com>, Oleg Nesterov <oleg@redhat.com>, LKML <linux-kernel@vger.kernel.org>, Linux PPC dev <linuxppc-dev@ozlabs.org>, Anton Blanchard <anton@samba.org>, Frederic Weisbecker <fweisbec@gmail.com>, Victor Kaplansky <VICTORK@il.ibm.com>, "linux@arm.linux.org.uk" <linux@arm.linux.org.uk>, Linus Torvalds <torvalds@linux-foundation.org>, "schwidefsky@de.ibm.com" <schwidefsky@de.ibm.com> Subject: Re: [RFC] arch: Introduce new TSO memory barrier smp_tmb() Date: Tue, 5 Nov 2013 14:05:48 +0000 [thread overview] Message-ID: <20131105140548.GD26895@mudshark.cambridge.arm.com> (raw) In-Reply-To: <20131104205344.GW3947@linux.vnet.ibm.com> On Mon, Nov 04, 2013 at 08:53:44PM +0000, Paul E. McKenney wrote: > On Mon, Nov 04, 2013 at 08:11:27PM +0100, Peter Zijlstra wrote: > Some comments below. I believe that opcodes need to be fixed for IA64. > I am unsure of the ifdefs and opcodes for arm64, but the ARM folks should > be able to tell us. [...] > > diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h > > index 60f15e274e6d..a804093d6891 100644 > > --- a/arch/arm/include/asm/barrier.h > > +++ b/arch/arm/include/asm/barrier.h > > @@ -53,10 +53,36 @@ > > #define smp_mb() barrier() > > #define smp_rmb() barrier() > > #define smp_wmb() barrier() > > + > > +#define smp_store_release(p, v) \ > > +do { \ > > + smp_mb(); \ > > + ACCESS_ONCE(p) = (v); \ > > +} while (0) > > + > > +#define smp_load_acquire(p, v) \ > > +do { \ > > + typeof(p) ___p1 = ACCESS_ONCE(p); \ > > + smp_mb(); \ > > + return ___p1; \ > > +} while (0) What data sizes do these accessors operate on? Assuming that we want single-copy atomicity (with respect to interrupts in the UP case), we probably want a check to stop people passing in things like structs. > > #else > > #define smp_mb() dmb(ish) > > #define smp_rmb() smp_mb() > > #define smp_wmb() dmb(ishst) > > + > > Seems like there should be some sort of #ifdef condition to distinguish > between these. My guess is something like: > > #if __LINUX_ARM_ARCH__ > 7 > > But I must defer to the ARM guys. For all I know, they might prefer > arch/arm to stick with smp_mb() and have arch/arm64 do the ldar and stlr. Yes. For arch/arm/, I'd rather we stick with the smp_mb() for the time being. We don't (yet) have any 32-bit ARMv8 support, and the efforts towards a single zImage could do without minor variations like this, not to mention the usual backlash I get whenever introducing something that needs a relatively recent binutils. > > +#define smp_store_release(p, v) \ > > +do { \ > > + asm volatile ("stlr %w0 [%1]" : : "r" (v), "r" (&p) : "memory");\ > > +} while (0) > > + > > +#define smp_load_acquire(p) \ > > +do { \ > > + typeof(p) ___p1; \ > > + asm volatile ("ldar %w0, [%1]" \ > > + : "=r" (___p1) : "r" (&p) : "memory"); \ > > + return ___p1; \ > > +} while (0) > > #endif > > > > #define read_barrier_depends() do { } while(0) > > diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h > > index d4a63338a53c..0da2d4ebb9a8 100644 > > --- a/arch/arm64/include/asm/barrier.h > > +++ b/arch/arm64/include/asm/barrier.h > > @@ -35,10 +35,38 @@ > > #define smp_mb() barrier() > > #define smp_rmb() barrier() > > #define smp_wmb() barrier() > > + > > +#define smp_store_release(p, v) \ > > +do { \ > > + smp_mb(); \ > > + ACCESS_ONCE(p) = (v); \ > > +} while (0) > > + > > +#define smp_load_acquire(p, v) \ > > +do { \ > > + typeof(p) ___p1 = ACCESS_ONCE(p); \ > > + smp_mb(); \ > > + return ___p1; \ > > +} while (0) > > + > > #else > > + > > #define smp_mb() asm volatile("dmb ish" : : : "memory") > > #define smp_rmb() asm volatile("dmb ishld" : : : "memory") > > #define smp_wmb() asm volatile("dmb ishst" : : : "memory") > > + > > +#define smp_store_release(p, v) \ > > +do { \ > > + asm volatile ("stlr %w0 [%1]" : : "r" (v), "r" (&p) : "memory");\ Missing comma between the operands. Also, that 'w' output modifier enforces a 32-bit store (same early question about sizes). Finally, it might be more efficient to use "=Q" for the addressing mode, rather than take the address of p manually. > > +} while (0) > > + > > +#define smp_load_acquire(p) \ > > +do { \ > > + typeof(p) ___p1; \ > > + asm volatile ("ldar %w0, [%1]" \ > > + : "=r" (___p1) : "r" (&p) : "memory"); \ > > + return ___p1; \ Similar comments here wrt Q constraint. Random other question: have you considered how these accessors should behave when presented with __iomem pointers? Will
next prev parent reply other threads:[~2013-11-05 14:05 UTC|newest] Thread overview: 212+ messages / expand[flat|nested] mbox.gz Atom feed top 2013-10-22 23:54 perf events ring buffer memory barrier on powerpc Michael Neuling 2013-10-23 7:39 ` Victor Kaplansky 2013-10-23 7:39 ` Victor Kaplansky 2013-10-23 14:19 ` Frederic Weisbecker 2013-10-23 14:19 ` Frederic Weisbecker 2013-10-23 14:25 ` Frederic Weisbecker 2013-10-23 14:25 ` Frederic Weisbecker 2013-10-25 17:37 ` Peter Zijlstra 2013-10-25 17:37 ` Peter Zijlstra 2013-10-25 20:31 ` Michael Neuling 2013-10-25 20:31 ` Michael Neuling 2013-10-27 9:00 ` Victor Kaplansky 2013-10-27 9:00 ` Victor Kaplansky 2013-10-28 9:22 ` Peter Zijlstra 2013-10-28 9:22 ` Peter Zijlstra 2013-10-28 10:02 ` Frederic Weisbecker 2013-10-28 10:02 ` Frederic Weisbecker 2013-10-28 12:38 ` Victor Kaplansky 2013-10-28 12:38 ` Victor Kaplansky 2013-10-28 13:26 ` Peter Zijlstra 2013-10-28 13:26 ` Peter Zijlstra 2013-10-28 16:34 ` Paul E. McKenney 2013-10-28 16:34 ` Paul E. McKenney 2013-10-28 20:17 ` Oleg Nesterov 2013-10-28 20:17 ` Oleg Nesterov 2013-10-28 20:58 ` Victor Kaplansky 2013-10-28 20:58 ` Victor Kaplansky 2013-10-29 10:21 ` Peter Zijlstra 2013-10-29 10:21 ` Peter Zijlstra 2013-10-29 10:30 ` Peter Zijlstra 2013-10-29 10:30 ` Peter Zijlstra 2013-10-29 10:35 ` Peter Zijlstra 2013-10-29 10:35 ` Peter Zijlstra 2013-10-29 20:15 ` Oleg Nesterov 2013-10-29 20:15 ` Oleg Nesterov 2013-10-29 19:27 ` Vince Weaver 2013-10-29 19:27 ` Vince Weaver 2013-10-30 10:42 ` Peter Zijlstra 2013-10-30 10:42 ` Peter Zijlstra 2013-10-30 11:48 ` James Hogan 2013-10-30 11:48 ` James Hogan 2013-10-30 12:48 ` Peter Zijlstra 2013-10-30 12:48 ` Peter Zijlstra 2013-11-06 13:19 ` [tip:perf/core] tools/perf: Add required memory barriers tip-bot for Peter Zijlstra 2013-11-06 13:50 ` Vince Weaver 2013-11-06 14:00 ` Peter Zijlstra 2013-11-06 14:28 ` Peter Zijlstra 2013-11-06 14:55 ` Vince Weaver 2013-11-06 15:10 ` Peter Zijlstra 2013-11-06 15:23 ` Peter Zijlstra 2013-11-06 14:44 ` Peter Zijlstra 2013-11-06 16:07 ` Peter Zijlstra 2013-11-06 17:31 ` Vince Weaver 2013-11-06 18:24 ` Peter Zijlstra 2013-11-07 8:21 ` Ingo Molnar 2013-11-07 14:27 ` Vince Weaver 2013-11-07 15:55 ` Ingo Molnar 2013-11-11 16:24 ` Peter Zijlstra 2013-11-11 21:10 ` Ingo Molnar 2013-10-29 21:23 ` perf events ring buffer memory barrier on powerpc Michael Neuling 2013-10-29 21:23 ` Michael Neuling 2013-10-30 9:27 ` Paul E. McKenney 2013-10-30 9:27 ` Paul E. McKenney 2013-10-30 11:25 ` Peter Zijlstra 2013-10-30 11:25 ` Peter Zijlstra 2013-10-30 14:52 ` Victor Kaplansky 2013-10-30 14:52 ` Victor Kaplansky 2013-10-30 15:39 ` Peter Zijlstra 2013-10-30 15:39 ` Peter Zijlstra 2013-10-30 17:14 ` Victor Kaplansky 2013-10-30 17:14 ` Victor Kaplansky 2013-10-30 17:44 ` Peter Zijlstra 2013-10-30 17:44 ` Peter Zijlstra 2013-10-31 6:16 ` Paul E. McKenney 2013-10-31 6:16 ` Paul E. McKenney 2013-11-01 13:12 ` Victor Kaplansky 2013-11-01 13:12 ` Victor Kaplansky 2013-11-02 16:36 ` Paul E. McKenney 2013-11-02 16:36 ` Paul E. McKenney 2013-11-02 17:26 ` Paul E. McKenney 2013-11-02 17:26 ` Paul E. McKenney 2013-10-31 6:40 ` Paul E. McKenney 2013-10-31 6:40 ` Paul E. McKenney 2013-11-01 14:25 ` Victor Kaplansky 2013-11-01 14:25 ` Victor Kaplansky 2013-11-02 17:28 ` Paul E. McKenney 2013-11-02 17:28 ` Paul E. McKenney 2013-11-01 14:56 ` Peter Zijlstra 2013-11-01 14:56 ` Peter Zijlstra 2013-11-02 17:32 ` Paul E. McKenney 2013-11-02 17:32 ` Paul E. McKenney 2013-11-03 14:40 ` Paul E. McKenney 2013-11-03 14:40 ` Paul E. McKenney 2013-11-03 15:17 ` [RFC] arch: Introduce new TSO memory barrier smp_tmb() Peter Zijlstra 2013-11-03 15:17 ` Peter Zijlstra 2013-11-03 18:08 ` Linus Torvalds 2013-11-03 18:08 ` Linus Torvalds 2013-11-03 20:01 ` Peter Zijlstra 2013-11-03 20:01 ` Peter Zijlstra 2013-11-03 22:42 ` Paul E. McKenney 2013-11-03 22:42 ` Paul E. McKenney 2013-11-03 23:34 ` Linus Torvalds 2013-11-03 23:34 ` Linus Torvalds 2013-11-04 10:51 ` Paul E. McKenney 2013-11-04 10:51 ` Paul E. McKenney 2013-11-04 11:22 ` Peter Zijlstra 2013-11-04 11:22 ` Peter Zijlstra 2013-11-04 16:27 ` Paul E. McKenney 2013-11-04 16:27 ` Paul E. McKenney 2013-11-04 16:48 ` Peter Zijlstra 2013-11-04 16:48 ` Peter Zijlstra 2013-11-04 19:11 ` Peter Zijlstra 2013-11-04 19:11 ` Peter Zijlstra 2013-11-04 19:18 ` Peter Zijlstra 2013-11-04 19:18 ` Peter Zijlstra 2013-11-04 20:54 ` Paul E. McKenney 2013-11-04 20:54 ` Paul E. McKenney 2013-11-04 20:53 ` Paul E. McKenney 2013-11-04 20:53 ` Paul E. McKenney 2013-11-05 14:05 ` Will Deacon [this message] 2013-11-05 14:05 ` Will Deacon 2013-11-05 14:49 ` Paul E. McKenney 2013-11-05 14:49 ` Paul E. McKenney 2013-11-05 18:49 ` Peter Zijlstra 2013-11-05 18:49 ` Peter Zijlstra 2013-11-06 11:00 ` Will Deacon 2013-11-06 11:00 ` Will Deacon 2013-11-06 12:39 ` Peter Zijlstra 2013-11-06 12:39 ` Peter Zijlstra 2013-11-06 12:51 ` Geert Uytterhoeven 2013-11-06 12:51 ` Geert Uytterhoeven 2013-11-06 13:57 ` Peter Zijlstra 2013-11-06 13:57 ` Peter Zijlstra 2013-11-06 18:48 ` Paul E. McKenney 2013-11-06 18:48 ` Paul E. McKenney 2013-11-06 19:42 ` Peter Zijlstra 2013-11-06 19:42 ` Peter Zijlstra 2013-11-07 11:17 ` Will Deacon 2013-11-07 11:17 ` Will Deacon 2013-11-07 13:36 ` Peter Zijlstra 2013-11-07 13:36 ` Peter Zijlstra 2013-11-07 23:50 ` Mathieu Desnoyers 2013-11-07 23:50 ` Mathieu Desnoyers 2013-11-04 11:05 ` Will Deacon 2013-11-04 11:05 ` Will Deacon 2013-11-04 16:34 ` Paul E. McKenney 2013-11-04 16:34 ` Paul E. McKenney 2013-11-03 20:59 ` Benjamin Herrenschmidt 2013-11-03 20:59 ` Benjamin Herrenschmidt 2013-11-03 22:43 ` Paul E. McKenney 2013-11-03 22:43 ` Paul E. McKenney 2013-11-03 17:07 ` perf events ring buffer memory barrier on powerpc Will Deacon 2013-11-03 22:47 ` Paul E. McKenney 2013-11-04 9:57 ` Will Deacon 2013-11-04 10:52 ` Paul E. McKenney 2013-11-01 16:11 ` Peter Zijlstra 2013-11-01 16:11 ` Peter Zijlstra 2013-11-02 17:46 ` Paul E. McKenney 2013-11-02 17:46 ` Paul E. McKenney 2013-11-01 16:18 ` Peter Zijlstra 2013-11-01 16:18 ` Peter Zijlstra 2013-11-02 17:49 ` Paul E. McKenney 2013-11-02 17:49 ` Paul E. McKenney 2013-10-30 13:28 ` Victor Kaplansky 2013-10-30 13:28 ` Victor Kaplansky 2013-10-30 15:51 ` Peter Zijlstra 2013-10-30 15:51 ` Peter Zijlstra 2013-10-30 18:29 ` Peter Zijlstra 2013-10-30 18:29 ` Peter Zijlstra 2013-10-30 19:11 ` Peter Zijlstra 2013-10-30 19:11 ` Peter Zijlstra 2013-10-31 4:33 ` Paul E. McKenney 2013-10-31 4:33 ` Paul E. McKenney 2013-10-31 4:32 ` Paul E. McKenney 2013-10-31 4:32 ` Paul E. McKenney 2013-10-31 9:04 ` Peter Zijlstra 2013-10-31 9:04 ` Peter Zijlstra 2013-10-31 15:07 ` Paul E. McKenney 2013-10-31 15:07 ` Paul E. McKenney 2013-10-31 15:19 ` Peter Zijlstra 2013-10-31 15:19 ` Peter Zijlstra 2013-11-01 9:28 ` Paul E. McKenney 2013-11-01 9:28 ` Paul E. McKenney 2013-11-01 10:30 ` Peter Zijlstra 2013-11-01 10:30 ` Peter Zijlstra 2013-11-02 15:20 ` Paul E. McKenney 2013-11-02 15:20 ` Paul E. McKenney 2013-11-04 9:07 ` Peter Zijlstra 2013-11-04 9:07 ` Peter Zijlstra 2013-11-04 10:00 ` Paul E. McKenney 2013-11-04 10:00 ` Paul E. McKenney 2013-10-31 9:59 ` Victor Kaplansky 2013-10-31 9:59 ` Victor Kaplansky 2013-10-31 12:28 ` David Laight 2013-10-31 12:28 ` David Laight 2013-10-31 12:55 ` Victor Kaplansky 2013-10-31 12:55 ` Victor Kaplansky 2013-10-31 15:25 ` Paul E. McKenney 2013-10-31 15:25 ` Paul E. McKenney 2013-11-01 16:06 ` Victor Kaplansky 2013-11-01 16:06 ` Victor Kaplansky 2013-11-01 16:25 ` David Laight 2013-11-01 16:25 ` David Laight 2013-11-01 16:30 ` Victor Kaplansky 2013-11-01 16:30 ` Victor Kaplansky 2013-11-03 20:57 ` Benjamin Herrenschmidt 2013-11-03 20:57 ` Benjamin Herrenschmidt 2013-11-02 15:46 ` Paul E. McKenney 2013-11-02 15:46 ` Paul E. McKenney 2013-10-28 19:09 ` Oleg Nesterov 2013-10-28 19:09 ` Oleg Nesterov 2013-10-29 14:06 ` [tip:perf/urgent] perf: Fix perf ring buffer memory ordering tip-bot for Peter Zijlstra
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