From: "Antoine Ténart" <antoine.tenart@free-electrons.com> To: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: tj@kernel.org, alexandre.belloni@free-electrons.com, zmxu@marvell.com, jszhang@marvell.com, linux-arm-kernel@lists.infradead.org, linux-ide@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/6] ata: ahci: add AHCI support for Berlin SoCs Date: Wed, 23 Apr 2014 10:21:00 +0200 [thread overview] Message-ID: <20140423082100.GB24355@kwain> (raw) In-Reply-To: <5356A4F4.6090107@gmail.com> Sebastian, On Tue, Apr 22, 2014 at 07:20:52PM +0200, Sebastian Hesselbarth wrote: > On 04/22/2014 05:38 PM, Antoine Ténart wrote: […] > > +static inline void ahci_berlin_reg_set(void __iomem *reg, u32 val) > > +{ > > + writel(val, reg); > > +} > > Antoine, > > if you really need to rename writel, the above function name should > end with _write. I renamed writel for consistency with ahci_berlin_reg_clear_set() and ahci_berlin_reg_setbits() but I can definitively drop it. > > > +static inline void ahci_berlin_reg_clear_set(void __iomem *reg, u32 clear_val, > > + u32 set_val) > > +{ > > + u32 regval; > > + > > + regval = readl(reg); > > + regval &= ~(clear_val); > > + regval |= set_val; > > + writel(regval, reg); > > +} > > ahci_berlin_reg_setbits(reg, val) == ahci_berlin_reg_clear_set(reg, 0, val); > > Maybe get rid of the latter? Sure. > > > +static void ahci_berlin_init(void __iomem *mmio) > > +{ > > + /* interface select */ > > + ahci_berlin_reg_set(mmio + HOST_VSA_ADDR, BIT(2)); > > + ahci_berlin_reg_set(mmio + HOST_VSA_ADDR, > > + BIT(21) | BIT(18) | BIT(5) | BIT(4) | BIT(2)); > > Any chance we get named #defines for the BIT()s above and below? I'm afraid I can't. I'd love to do so if someone has a clue on this matter. > > + /* force_map is modified only if the property is found */ > > + of_property_read_u32(np, "marvell,force-port-map", &force_map); > > + if (force_map) > > + nports = force_map; > > marvell,force-port-map is undocumented and its name does not reflect > what it is about. Before you just rename it to marvell,nr-ports or > something, how about having one sub-node per port: > > sata_phy0: sata-phy@e90100 { > compatible = "marvell,berlin-sata-phy"; > reg = <0xe90100 0x80>; > status = "disabled"; > }; > > sata_phy1: sata-phy@e90180 { > compatible = "marvell,berlin-sata-phy"; > reg = <0xe90180 0x80>; > status = "disabled"; > }; > > ahci: sata@e90000 { > compatible = "marvell,berlin-ahci"; > reg = <0xe90000 0x100>; > interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; > #address-cells = <1>; > #size-cells = <0>; > status = "disabled"; > > sata-port@0 { > reg = <0>; > sata-phy = <&sata_phy0>; > status = "disabled"; > }; > > sata-port@1 { > reg = <1>; > sata-phy = <&sata_phy1>; > status = "okay"; > }; > }; > > That way you can > (a) separate a PHY driver that has little code but is able to power-down > the PHY even if there is no AHCI driver loaded. > (b) enable/disable each port individually. > (c) enable port1 while port0 is disabled. > (d) disable the PLL if there is no port enabled at all. That would be better, but as of now I'm not sure I have enough information on the PHY to do (a). I guess (b), (c) and (d) can still be done. Thanks for the review! Antoine -- Antoine Ténart, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
WARNING: multiple messages have this Message-ID (diff)
From: antoine.tenart@free-electrons.com (Antoine Ténart) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/6] ata: ahci: add AHCI support for Berlin SoCs Date: Wed, 23 Apr 2014 10:21:00 +0200 [thread overview] Message-ID: <20140423082100.GB24355@kwain> (raw) In-Reply-To: <5356A4F4.6090107@gmail.com> Sebastian, On Tue, Apr 22, 2014 at 07:20:52PM +0200, Sebastian Hesselbarth wrote: > On 04/22/2014 05:38 PM, Antoine T?nart wrote: [?] > > +static inline void ahci_berlin_reg_set(void __iomem *reg, u32 val) > > +{ > > + writel(val, reg); > > +} > > Antoine, > > if you really need to rename writel, the above function name should > end with _write. I renamed writel for consistency with ahci_berlin_reg_clear_set() and ahci_berlin_reg_setbits() but I can definitively drop it. > > > +static inline void ahci_berlin_reg_clear_set(void __iomem *reg, u32 clear_val, > > + u32 set_val) > > +{ > > + u32 regval; > > + > > + regval = readl(reg); > > + regval &= ~(clear_val); > > + regval |= set_val; > > + writel(regval, reg); > > +} > > ahci_berlin_reg_setbits(reg, val) == ahci_berlin_reg_clear_set(reg, 0, val); > > Maybe get rid of the latter? Sure. > > > +static void ahci_berlin_init(void __iomem *mmio) > > +{ > > + /* interface select */ > > + ahci_berlin_reg_set(mmio + HOST_VSA_ADDR, BIT(2)); > > + ahci_berlin_reg_set(mmio + HOST_VSA_ADDR, > > + BIT(21) | BIT(18) | BIT(5) | BIT(4) | BIT(2)); > > Any chance we get named #defines for the BIT()s above and below? I'm afraid I can't. I'd love to do so if someone has a clue on this matter. > > + /* force_map is modified only if the property is found */ > > + of_property_read_u32(np, "marvell,force-port-map", &force_map); > > + if (force_map) > > + nports = force_map; > > marvell,force-port-map is undocumented and its name does not reflect > what it is about. Before you just rename it to marvell,nr-ports or > something, how about having one sub-node per port: > > sata_phy0: sata-phy at e90100 { > compatible = "marvell,berlin-sata-phy"; > reg = <0xe90100 0x80>; > status = "disabled"; > }; > > sata_phy1: sata-phy at e90180 { > compatible = "marvell,berlin-sata-phy"; > reg = <0xe90180 0x80>; > status = "disabled"; > }; > > ahci: sata at e90000 { > compatible = "marvell,berlin-ahci"; > reg = <0xe90000 0x100>; > interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; > #address-cells = <1>; > #size-cells = <0>; > status = "disabled"; > > sata-port at 0 { > reg = <0>; > sata-phy = <&sata_phy0>; > status = "disabled"; > }; > > sata-port at 1 { > reg = <1>; > sata-phy = <&sata_phy1>; > status = "okay"; > }; > }; > > That way you can > (a) separate a PHY driver that has little code but is able to power-down > the PHY even if there is no AHCI driver loaded. > (b) enable/disable each port individually. > (c) enable port1 while port0 is disabled. > (d) disable the PLL if there is no port enabled at all. That would be better, but as of now I'm not sure I have enough information on the PHY to do (a). I guess (b), (c) and (d) can still be done. Thanks for the review! Antoine -- Antoine T?nart, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
next prev parent reply other threads:[~2014-04-23 8:21 UTC|newest] Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-04-22 15:38 [PATCH 0/6] ARM: berlin: add AHCI support Antoine Ténart 2014-04-22 15:38 ` Antoine Ténart 2014-04-22 15:38 ` Antoine Ténart 2014-04-22 15:38 ` [PATCH 1/6] ata: ahci: add AHCI support for Berlin SoCs Antoine Ténart 2014-04-22 15:38 ` Antoine Ténart 2014-04-22 16:54 ` Bartlomiej Zolnierkiewicz 2014-04-22 16:54 ` Bartlomiej Zolnierkiewicz 2014-04-23 8:13 ` Antoine Ténart 2014-04-23 8:13 ` Antoine Ténart 2014-04-22 17:20 ` Sebastian Hesselbarth 2014-04-22 17:20 ` Sebastian Hesselbarth 2014-04-22 17:20 ` Sebastian Hesselbarth 2014-04-23 8:21 ` Antoine Ténart [this message] 2014-04-23 8:21 ` Antoine Ténart 2014-04-22 18:47 ` Rob Herring 2014-04-22 18:47 ` Rob Herring 2014-04-22 18:47 ` Rob Herring 2014-04-22 18:54 ` Rob Herring 2014-04-22 18:54 ` Rob Herring 2014-04-22 18:54 ` Rob Herring 2014-04-23 8:24 ` Antoine Ténart 2014-04-23 8:24 ` Antoine Ténart 2014-04-23 8:24 ` Antoine Ténart 2014-04-23 8:33 ` Antoine Ténart 2014-04-23 8:33 ` Antoine Ténart 2014-04-23 8:33 ` Antoine Ténart 2014-04-22 20:56 ` Andrew Lunn 2014-04-22 20:56 ` Andrew Lunn 2014-04-24 9:50 ` Jisheng Zhang 2014-04-24 9:50 ` Jisheng Zhang 2014-04-24 9:50 ` Jisheng Zhang 2014-04-24 10:26 ` Antoine Ténart 2014-04-24 10:26 ` Antoine Ténart 2014-04-24 10:26 ` Antoine Ténart 2014-04-22 15:38 ` [PATCH 2/6] Documentation: bindings: add the berlin-achi compatible to the ahci platform Antoine Ténart 2014-04-22 15:38 ` Antoine Ténart 2014-04-22 16:27 ` Thomas Petazzoni 2014-04-22 16:27 ` Thomas Petazzoni 2014-04-22 17:21 ` Sebastian Hesselbarth 2014-04-22 17:21 ` Sebastian Hesselbarth 2014-04-22 17:21 ` Sebastian Hesselbarth 2014-04-22 15:38 ` [PATCH 3/6] ARM: berlin: add the AHCI node for the BG2Q Antoine Ténart 2014-04-22 15:38 ` Antoine Ténart 2014-04-22 15:38 ` Antoine Ténart 2014-04-22 16:28 ` Thomas Petazzoni 2014-04-22 16:28 ` Thomas Petazzoni 2014-04-22 17:22 ` Sebastian Hesselbarth 2014-04-22 17:22 ` Sebastian Hesselbarth 2014-04-22 17:22 ` Sebastian Hesselbarth 2014-04-22 16:28 ` Thomas Petazzoni 2014-04-22 16:28 ` Thomas Petazzoni 2014-04-22 15:38 ` [PATCH 4/6] ARM: berlin: enable the eSATA interface on the BG2Q DMP Antoine Ténart 2014-04-22 15:38 ` Antoine Ténart 2014-04-22 15:38 ` Antoine Ténart 2014-04-22 15:38 ` [PATCH 5/6] ARM: berlin: add the AHCI node for the BG2 Antoine Ténart 2014-04-22 15:38 ` Antoine Ténart 2014-04-23 2:45 ` Jisheng Zhang 2014-04-23 2:45 ` Jisheng Zhang 2014-04-23 2:45 ` Jisheng Zhang 2014-04-23 8:58 ` Antoine Ténart 2014-04-23 8:58 ` Antoine Ténart 2014-04-23 8:58 ` Antoine Ténart 2014-04-22 15:38 ` [PATCH 6/6] ARM: berlin: add the AHCI node for the BG2CD Antoine Ténart 2014-04-22 15:38 ` Antoine Ténart 2014-04-22 15:38 ` Antoine Ténart 2014-04-23 2:43 ` Jisheng Zhang 2014-04-23 2:43 ` Jisheng Zhang 2014-04-23 2:43 ` Jisheng Zhang
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