[PATCH 00/71] drm/i915/chv: Add Cherryview support

[PATCH 00/71] drm/i915/chv: Add Cherryview support

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Cherryview (CHV) is the latest Intel(r) Atom(tm) Processor from Intel
containing Intel(r) HD Graphics.

The major GPU hardware features include:
- Gen8 Intel(r) HD Graphics graphics
- three display pipes
- three HDMI/DP/eDP display ports
- two MIPI DSI display ports
- removal of VGA support

This series exposes the basic features for CHV, bringing us to roughly
feature parity with earlier platforms.

The GT side programming follows the path laid out by Broadwell, so the
number of patches dealing with GT functionality is fairly low. By far
the largest amount of new code is added to deal with the new DP/HDMI
display PHY, and the third display pipe. The RC6 and turbo changes were
also fairly substantial.

Big thanks to everyone who contributed! In particular to Chon Ming for
the display PHY support and to Deepak for the RC6 and turbo support.

Chon Ming Lee (8):
  drm/i915/chv: Add DPIO offset for Cherryview. v3
  drm/i915/chv: Update Cherryview DPLL changes to support Port D. v2
  drm/i915/chv: Add vlv_pipe_to_channel
  drm/i915/chv: Trigger phy common lane reset
  drm/i915/chv: find the best divisor for the target clock v4
  drm/i915/chv: Add update and enable pll for Cherryview
  drm/i915/chv: Add phy supports for Cherryview
  drm/i915/chv: Pipe select change for DP and HDMI

Damien Lespiau (1):
  drm/i915/chv: Implement stolen memory size detection

Daniel Vetter (3):
  drm/i915/chv: Preliminary interrupt support for Cherryview
  drm/i915/chv: Add Cherryview PCI IDs
  drm/i915/chv: Add early quirk for stolen

Deepak S (9):
  drm/i915: Enable PM Interrupts for CHV/BDW Platform.
  drm/i915/chv: Enable Render Standby (RC6) for Cheeryview
  drm/i915/chv: Added CHV specific register read and write
  drm/i915/chv: Enable RPS (Turbo) for Cheeryview
  drm/i915/chv: Enable PM interrupts when we in CHV turbo initialize
    sequence.
  drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating
  drm/i915/bdw: Add BDW PM Interrupts support and BDW rps disable
  drm/i915/chv: Fix for verifying PCBR address field.
  drm/i915/chv: Fix for decrementing fw count in chv read/write.

Rafael Barbalho (4):
  drm/i915/chv: Flush caches when programming page tables
  drm/i915/chv: Implement WaDisableSamplerPowerBypass for CHV
  drm/i915/chv: Add plane C support
  drm/i915/chv: Add CHV display support

Ville Syrjälä (46):
  drm/i915/chv: IS_BROADWELL() should not be true for Cherryview
  drm/i915/chv: Add IS_CHERRYVIEW() macro
  drm/i915/chv: PPAT setup for Cherryview
  drm/i915/chv: Enable aliasing PPGTT for CHV
  drm/i915/chv: Add PIPESTAT register bits for Cherryview
  drm/i915/chv: Add DPFLIPSTAT register bits for Cherryview
  drm/i915/chv: Add display interrupt registers bits for Cherryview
  drm/i915/chv: Add DPINVGTT registers defines for Cherryview
  drm/i915/chv: Add Cherryview interrupt registers into debugfs
  drm/i915/chv: Initial clock gating support for Cherryview
  drm/i915/chv: Add DDL register defines for Cherryview
  drm/i915/chv: Add DPLL state readout support
  drm/i915/chv: CHV doesn't have CRT output
  drm/i915/chv: Implement WaDisablePartialInstShootdown:chv
  drm/i915/chv: Implement WaDisableThreadStallDopClockGating:chv
  drm/i915/chv: Implement WaVSRefCountFullforceMissDisable:chv and
    WaDSRefCountFullforceMissDisable:chv
  drm/i915/chv: Implement WaDisableSemaphoreAndSyncFlipWait:chv
  drm/i915/chv: Implement WaDisableCSUnitClockGating:chv
  drm/i915/chv: Implement WaDisableSDEUnitClockGating:chv
  drm/i915/chv: Add some workaround notes
  drm/i915/chv: Add a bunch of pre production workarounds
  drm/i915/chv: Streamline CHV forcewake stuff
  drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0
  drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV
  drm/i915/chv: Clarify VLV/CHV PIPESTAT bits a bit more
  drm/i915/chv: Use valleyview_pipestat_irq_handler() for CHV
  drm/i915/chv: Make CHV irq handler loop until all interrupts are
    consumed
  drm/i915/chv: Configure crtc_mask correctly for CHV
  drm/i915/chv: Fix gmbus for port D
  drm/i915/chv: Add cursor pipe offsets
  drm/i915/chv: Bump num_pipes to 3
  drm/i915/chv: Fix PORT_TO_PIPE for CHV
  drm/i915/chv: Register port D encoders and connectors
  drm/i915/chv: Fix CHV PLL state tracking
  drm/i915/chv: Move data lane deassert to encoder pre_enable
  drm/i915/chv: Turn off dclkp after the PLL has been disabled
  drm/i915/chv: Reset data lanes in encoder .post_disable() hook
  drm/i915/chv: Set soft reset override bit for data lane resets
  drm/i915/chv: Don't use PCS group access reads
  drm/i915/chv: Don't do group access reads from TX lanes either
  drm/i915/chv: Use RMW to toggle swing calc init
  drm/i915/chv: Try to program the PHY used clock channel overrides
  drm/i915/chv: Force clock buffer enables
  drm/i915/chv: Force PHY clock buffers off after PLL disable
  drm/i915: Don't use pipe_offset stuff for DPLL registers
  drm/i915/chv: Handle video DIP registers on CHV

 arch/x86/kernel/early-quirks.c          |  24 +-
 drivers/gpu/drm/i915/i915_debugfs.c     |  51 +++-
 drivers/gpu/drm/i915/i915_drv.c         |  53 +++-
 drivers/gpu/drm/i915/i915_drv.h         |  16 +-
 drivers/gpu/drm/i915/i915_gem.c         |   1 +
 drivers/gpu/drm/i915/i915_gem_context.c |   2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c     |  92 ++++++-
 drivers/gpu/drm/i915/i915_gem_gtt.h     |   1 +
 drivers/gpu/drm/i915/i915_irq.c         | 250 ++++++++++++++++++-
 drivers/gpu/drm/i915/i915_reg.h         | 318 +++++++++++++++++++++---
 drivers/gpu/drm/i915/intel_display.c    | 419 ++++++++++++++++++++++++++++----
 drivers/gpu/drm/i915/intel_dp.c         | 372 +++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_drv.h        |  15 ++
 drivers/gpu/drm/i915/intel_hdmi.c       | 234 +++++++++++++++++-
 drivers/gpu/drm/i915/intel_pm.c         | 331 ++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_ringbuffer.c |   2 +-
 drivers/gpu/drm/i915/intel_sideband.c   |  15 ++
 drivers/gpu/drm/i915/intel_uncore.c     | 126 +++++++++-
 include/drm/i915_pciids.h               |   6 +
 19 files changed, 2190 insertions(+), 138 deletions(-)

-- 
1.8.3.2

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[PATCH 01/71] drm/i915/chv: IS_BROADWELL() should not be true for Cherryview

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e23bb73..41cf429 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1789,7 +1789,7 @@ struct drm_i915_cmd_table {
 				 (dev)->pdev->device == 0x010A)
 #define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
 #define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
-#define IS_BROADWELL(dev)	(INTEL_INFO(dev)->gen == 8)
+#define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
 #define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
 #define IS_HSW_EARLY_SDV(dev)	(IS_HASWELL(dev) && \
 				 ((dev)->pdev->device & 0xFF00) == 0x0C00)
-- 
1.8.3.2

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[PATCH 02/71] drm/i915/chv: Add IS_CHERRYVIEW() macro

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We will treat Cherryview like Valleyview for most parts. Add a macro
for cases when we need to tell the two apart.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 41cf429..f760803 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1788,6 +1788,7 @@ struct drm_i915_cmd_table {
 				 (dev)->pdev->device == 0x0106 || \
 				 (dev)->pdev->device == 0x010A)
 #define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
+#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
 #define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
 #define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
 #define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
-- 
1.8.3.2

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[PATCH 03/71] drm/i915/chv: PPAT setup for Cherryview

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Ignore the cache bits in PPAT and just set the snoop bit where
appropriate. BDW WB is mapped to snooped access, while all other
modes are mapped to non-snooped access.

The hardware supposedly ignores everything except the snoop bit
in the PPAT entries.

Additionally the hardware actually enforces snooping for all
page table accesses, and thus the snoop bit is ignored for PDEs.

v2: Rebased on top of the bdw resume fix to reload the ppat entries.

v3: Rebase on top of the i915_gem_gtt.h header extraction.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1)
Acked-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 43 +++++++++++++++++++++++++++++++++----
 drivers/gpu/drm/i915/i915_gem_gtt.h |  1 +
 2 files changed, 40 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4467974..3e4d1f0 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -30,7 +30,8 @@
 #include "i915_trace.h"
 #include "intel_drv.h"
 
-static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv);
+static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv);
+static void chv_setup_private_ppat(struct drm_i915_private *dev_priv);
 
 bool intel_enable_ppgtt(struct drm_device *dev, bool full)
 {
@@ -1315,7 +1316,11 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
 
 
 	if (INTEL_INFO(dev)->gen >= 8) {
-		gen8_setup_private_ppat(dev_priv);
+		if (IS_CHERRYVIEW(dev))
+			chv_setup_private_ppat(dev_priv);
+		else
+			bdw_setup_private_ppat(dev_priv);
+
 		return;
 	}
 
@@ -1787,7 +1792,7 @@ static int ggtt_probe_common(struct drm_device *dev,
 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
  * bits. When using advanced contexts each context stores its own PAT, but
  * writing this data shouldn't be harmful even in those cases. */
-static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv)
+static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
 {
 	uint64_t pat;
 
@@ -1806,6 +1811,33 @@ static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
 }
 
+static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
+{
+	uint64_t pat;
+
+	/*
+	 * Map WB on BDW to snooped on CHV.
+	 *
+	 * Only the snoop bit has meaning for CHV, the rest is
+	 * ignored.
+	 *
+	 * Note that the harware enforces snooping for all page
+	 * table accesses. The snoop bit is actually ignored for
+	 * PDEs.
+	 */
+	pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
+	      GEN8_PPAT(1, 0) |
+	      GEN8_PPAT(2, 0) |
+	      GEN8_PPAT(3, 0) |
+	      GEN8_PPAT(4, CHV_PPAT_SNOOP) |
+	      GEN8_PPAT(5, CHV_PPAT_SNOOP) |
+	      GEN8_PPAT(6, CHV_PPAT_SNOOP) |
+	      GEN8_PPAT(7, CHV_PPAT_SNOOP);
+
+	I915_WRITE(GEN8_PRIVATE_PAT, pat);
+	I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
+}
+
 static int gen8_gmch_probe(struct drm_device *dev,
 			   size_t *gtt_total,
 			   size_t *stolen,
@@ -1831,7 +1863,10 @@ static int gen8_gmch_probe(struct drm_device *dev,
 	gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
 	*gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
 
-	gen8_setup_private_ppat(dev_priv);
+	if (IS_CHERRYVIEW(dev))
+		chv_setup_private_ppat(dev_priv);
+	else
+		bdw_setup_private_ppat(dev_priv);
 
 	ret = ggtt_probe_common(dev, gtt_size);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index b5e8ac0..cfca023 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -95,6 +95,7 @@ typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
 #define PPAT_CACHED_INDEX		_PAGE_PAT /* WB LLCeLLC */
 #define PPAT_DISPLAY_ELLC_INDEX		_PAGE_PCD /* WT eLLC */
 
+#define CHV_PPAT_SNOOP			(1<<6)
 #define GEN8_PPAT_AGE(x)		(x<<4)
 #define GEN8_PPAT_LLCeLLC		(3<<2)
 #define GEN8_PPAT_LLCELLC		(2<<2)
-- 
1.8.3.2

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[PATCH 04/71] drm/i915/chv: Flush caches when programming page tables

[ville.syrjala]

From: Rafael Barbalho <rafael.barbalho@intel.com>

Page table updates were getting stuck in the CPU cache on chv causing
spurious page faults and strange behaviour.

Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
[vsyrjala: Add !HAS_LLC checks]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 3e4d1f0..ba51901 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -267,6 +267,8 @@ static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
 			num_entries--;
 		}
 
+		if (!HAS_LLC(ppgtt->base.dev))
+			drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
 		kunmap_atomic(pt_vaddr);
 
 		pte = 0;
@@ -303,6 +305,8 @@ static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
 			gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
 					cache_level, true);
 		if (++pte == GEN8_PTES_PER_PAGE) {
+			if (!HAS_LLC(ppgtt->base.dev))
+				drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
 			kunmap_atomic(pt_vaddr);
 			pt_vaddr = NULL;
 			if (++pde == GEN8_PDES_PER_PAGE) {
@@ -312,8 +316,11 @@ static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
 			pte = 0;
 		}
 	}
-	if (pt_vaddr)
+	if (pt_vaddr) {
+		if (!HAS_LLC(ppgtt->base.dev))
+			drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
 		kunmap_atomic(pt_vaddr);
+	}
 }
 
 static void gen8_free_page_tables(struct page **pt_pages)
@@ -576,6 +583,8 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
 			pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
 						      I915_CACHE_LLC);
 		}
+		if (!HAS_LLC(ppgtt->base.dev))
+			drm_clflush_virt_range(pd_vaddr, PAGE_SIZE);
 		kunmap_atomic(pd_vaddr);
 	}
 
-- 
1.8.3.2

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[PATCH 05/71] drm/i915/chv: Enable aliasing PPGTT for CHV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Enable aliasing PPGTT for CHV, but keep full PPGTT still disabled until
it gets enabled for BDW.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f760803..4abaa9e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1831,9 +1831,10 @@ struct drm_i915_cmd_table {
 #define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)
 
 #define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 6)
-#define HAS_ALIASING_PPGTT(dev)	(INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev))
-#define HAS_PPGTT(dev)		(INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) \
-				 && !IS_BROADWELL(dev))
+#define HAS_ALIASING_PPGTT(dev)	(INTEL_INFO(dev)->gen >= 6 && \
+				 (!IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
+#define HAS_PPGTT(dev)		(INTEL_INFO(dev)->gen >= 7 \
+				 && !IS_GEN8(dev))
 #define USES_PPGTT(dev)		intel_enable_ppgtt(dev, false)
 #define USES_FULL_PPGTT(dev)	intel_enable_ppgtt(dev, true)
 
-- 
1.8.3.2

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[PATCH 06/71] drm/i915/chv: Add PIPESTAT register bits for Cherryview

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

FIXME: We probably want to sprinkle _CHV suffixes over these.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b6441da..0fb6b6f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3364,6 +3364,7 @@ enum punit_power_well {
 #define   SPRITE1_FLIP_DONE_INT_EN_VLV		(1UL<<30)
 #define   PIPE_CRC_ERROR_ENABLE			(1UL<<29)
 #define   PIPE_CRC_DONE_ENABLE			(1UL<<28)
+#define   PERF_COUNTER2_INTERRUPT_EN		(1UL<<27)
 #define   PIPE_GMBUS_EVENT_ENABLE		(1UL<<27)
 #define   PLANE_FLIP_DONE_INT_EN_VLV		(1UL<<26)
 #define   PIPE_HOTPLUG_INTERRUPT_ENABLE		(1UL<<26)
@@ -3375,8 +3376,10 @@ enum punit_power_well {
 #define   PIPE_ODD_FIELD_INTERRUPT_ENABLE	(1UL<<21)
 #define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE	(1UL<<20)
 #define   PIPE_B_PSR_INTERRUPT_ENABLE_VLV	(1UL<<19)
+#define   PERF_COUNTER_INTERRUPT_EN		(1UL<<19)
 #define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE	(1UL<<18) /* pre-965 */
 #define   PIPE_START_VBLANK_INTERRUPT_ENABLE	(1UL<<18) /* 965 or later */
+#define   PIPE_FRAMESTART_INTERRUPT_ENABLE	(1UL<<17)
 #define   PIPE_VBLANK_INTERRUPT_ENABLE		(1UL<<17)
 #define   PIPEA_HBLANK_INT_EN_VLV		(1UL<<16)
 #define   PIPE_OVERLAY_UPDATED_ENABLE		(1UL<<16)
@@ -3384,6 +3387,7 @@ enum punit_power_well {
 #define   SPRITE0_FLIP_DONE_INT_STATUS_VLV	(1UL<<14)
 #define   PIPE_CRC_ERROR_INTERRUPT_STATUS	(1UL<<13)
 #define   PIPE_CRC_DONE_INTERRUPT_STATUS	(1UL<<12)
+#define   PERF_COUNTER2_INTERRUPT_STATUS	(1UL<<11)
 #define   PIPE_GMBUS_INTERRUPT_STATUS		(1UL<<11)
 #define   PLANE_FLIP_DONE_INT_STATUS_VLV	(1UL<<10)
 #define   PIPE_HOTPLUG_INTERRUPT_STATUS		(1UL<<10)
@@ -3392,12 +3396,16 @@ enum punit_power_well {
 #define   PIPE_DPST_EVENT_STATUS		(1UL<<7)
 #define   PIPE_LEGACY_BLC_EVENT_STATUS		(1UL<<6)
 #define   PIPE_A_PSR_STATUS_VLV			(1UL<<6)
+#define   PIPE_LEGACY_BLC_EVENT_STATUS		(1UL<<6)
 #define   PIPE_ODD_FIELD_INTERRUPT_STATUS	(1UL<<5)
 #define   PIPE_EVEN_FIELD_INTERRUPT_STATUS	(1UL<<4)
 #define   PIPE_B_PSR_STATUS_VLV			(1UL<<3)
+#define   PERF_COUNTER_INTERRUPT_STATUS		(1UL<<3)
 #define   PIPE_HOTPLUG_TV_INTERRUPT_STATUS	(1UL<<2) /* pre-965 */
 #define   PIPE_START_VBLANK_INTERRUPT_STATUS	(1UL<<2) /* 965 or later */
+#define   PIPE_FRAMESTART_INTERRUPT_STATUS	(1UL<<1)
 #define   PIPE_VBLANK_INTERRUPT_STATUS		(1UL<<1)
+#define   PIPE_HBLANK_INT_STATUS		(1UL<<0)
 #define   PIPE_OVERLAY_UPDATED_STATUS		(1UL<<0)
 
 #define PIPESTAT_INT_ENABLE_MASK		0x7fff0000
-- 
1.8.3.2

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[PATCH 07/71] drm/i915/chv: Add DPFLIPSTAT register bits for Cherryview

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

CHV has pipe C and PSR which cause changes to DPFLIPSTAT.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0fb6b6f..81d4b83 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3451,12 +3451,19 @@ enum punit_power_well {
 #define   SPRITED_FLIP_DONE_INT_EN		(1<<26)
 #define   SPRITEC_FLIP_DONE_INT_EN		(1<<25)
 #define   PLANEB_FLIP_DONE_INT_EN		(1<<24)
+#define   PIPE_PSR_INT_EN			(1<<22)
 #define   PIPEA_LINE_COMPARE_INT_EN		(1<<21)
 #define   PIPEA_HLINE_INT_EN			(1<<20)
 #define   PIPEA_VBLANK_INT_EN			(1<<19)
 #define   SPRITEB_FLIP_DONE_INT_EN		(1<<18)
 #define   SPRITEA_FLIP_DONE_INT_EN		(1<<17)
 #define   PLANEA_FLIPDONE_INT_EN		(1<<16)
+#define   PIPEC_LINE_COMPARE_INT_EN		(1<<13)
+#define   PIPEC_HLINE_INT_EN			(1<<12)
+#define   PIPEC_VBLANK_INT_EN			(1<<11)
+#define   SPRITEF_FLIPDONE_INT_EN		(1<<10)
+#define   SPRITEE_FLIPDONE_INT_EN		(1<<9)
+#define   PLANEC_FLIPDONE_INT_EN		(1<<8)
 
 #define DPINVGTT				(VLV_DISPLAY_BASE + 0x7002c) /* VLV only */
 #define   CURSORB_INVALID_GTT_INT_EN		(1<<23)
-- 
1.8.3.2

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[PATCH 08/71] drm/i915/chv: Add display interrupt registers bits for Cherryview

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

v2: Rebase on top of Ben's GT interrupt shuffling.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 81d4b83..3def0fb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1112,24 +1112,43 @@ enum punit_power_well {
 
 /* These are all the "old" interrupts */
 #define ILK_BSD_USER_INTERRUPT				(1<<5)
+
+#define I915_PM_INTERRUPT				(1<<31)
+#define I915_ISP_INTERRUPT				(1<<22)
+#define I915_LPE_PIPE_B_INTERRUPT			(1<<21)
+#define I915_LPE_PIPE_A_INTERRUPT			(1<<20)
+#define I915_MIPIB_INTERRUPT				(1<<19)
+#define I915_MIPIA_INTERRUPT				(1<<18)
 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1<<18)
 #define I915_DISPLAY_PORT_INTERRUPT			(1<<17)
+#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT		(1<<16)
+#define I915_MASTER_ERROR_INTERRUPT			(1<<15)
 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT	(1<<15)
+#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT		(1<<14)
 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1<<14) /* p-state */
+#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT		(1<<13)
 #define I915_HWB_OOM_INTERRUPT				(1<<13)
+#define I915_LPE_PIPE_C_INTERRUPT			(1<<12)
 #define I915_SYNC_STATUS_INTERRUPT			(1<<12)
+#define I915_MISC_INTERRUPT				(1<<11)
 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1<<11)
+#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT		(1<<10)
 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1<<10)
+#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT		(1<<9)
 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1<<9)
+#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT		(1<<8)
 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1<<8)
 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1<<7)
 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1<<6)
 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1<<5)
 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1<<4)
+#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT		(1<<3)
+#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT		(1<<2)
 #define I915_DEBUG_INTERRUPT				(1<<2)
+#define I915_WINVALID_INTERRUPT				(1<<1)
 #define I915_USER_INTERRUPT				(1<<1)
 #define I915_ASLE_INTERRUPT				(1<<0)
-#define I915_BSD_USER_INTERRUPT				(1 << 25)
+#define I915_BSD_USER_INTERRUPT				(1<<25)
 
 #define GEN6_BSD_RNCID			0x12198
 
-- 
1.8.3.2

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[PATCH 09/71] drm/i915/chv: Add DPINVGTT registers defines for Cherryview

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Due to Pipe C DPINVGTT has more bits on CHV.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3def0fb..98f549a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3485,6 +3485,10 @@ enum punit_power_well {
 #define   PLANEC_FLIPDONE_INT_EN		(1<<8)
 
 #define DPINVGTT				(VLV_DISPLAY_BASE + 0x7002c) /* VLV only */
+#define   SPRITEF_INVALID_GTT_INT_EN		(1<<27)
+#define   SPRITEE_INVALID_GTT_INT_EN		(1<<26)
+#define   PLANEC_INVALID_GTT_INT_EN		(1<<25)
+#define   CURSORC_INVALID_GTT_INT_EN		(1<<24)
 #define   CURSORB_INVALID_GTT_INT_EN		(1<<23)
 #define   CURSORA_INVALID_GTT_INT_EN		(1<<22)
 #define   SPRITED_INVALID_GTT_INT_EN		(1<<21)
@@ -3494,6 +3498,11 @@ enum punit_power_well {
 #define   SPRITEA_INVALID_GTT_INT_EN		(1<<17)
 #define   PLANEA_INVALID_GTT_INT_EN		(1<<16)
 #define   DPINVGTT_EN_MASK			0xff0000
+#define   DPINVGTT_EN_MASK_CHV			0xfff0000
+#define   SPRITEF_INVALID_GTT_STATUS		(1<<11)
+#define   SPRITEE_INVALID_GTT_STATUS		(1<<10)
+#define   PLANEC_INVALID_GTT_STATUS		(1<<9)
+#define   CURSORC_INVALID_GTT_STATUS		(1<<8)
 #define   CURSORB_INVALID_GTT_STATUS		(1<<7)
 #define   CURSORA_INVALID_GTT_STATUS		(1<<6)
 #define   SPRITED_INVALID_GTT_STATUS		(1<<5)
@@ -3503,6 +3512,7 @@ enum punit_power_well {
 #define   SPRITEA_INVALID_GTT_STATUS		(1<<1)
 #define   PLANEA_INVALID_GTT_STATUS		(1<<0)
 #define   DPINVGTT_STATUS_MASK			0xff
+#define   DPINVGTT_STATUS_MASK_CHV		0xfff
 
 #define DSPARB			0x70030
 #define   DSPARB_CSTART_MASK	(0x7f << 7)
-- 
1.8.3.2

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[PATCH 10/71] drm/i915/chv: Preliminary interrupt support for Cherryview

[ville.syrjala]

From: Daniel Vetter <daniel.vetter@ffwll.ch>

CHV has the Gen8 master interrupt register, as well as Gen8
GT/PCU interrupt registers.

The display block is based on VLV, with the main difference
of adding pipe C.

FIXME: Lot of this is copy pasted from either VLV or BDW. We should
probably refactor a bit to share the code better.

v2: Rewrite the order of operations to make more sense
    Don't bail out if MASTER_CTL register doesn't show an interrupt,
    as display interrupts aren't reported there.

v3: Rebase on top of Egbert Eich's hpd irq handling rework by using
the relevant port hotplug logic like for vlv.

v4: Rebase on top of Ben's gt irq #define refactoring.

v5: Squash in gen8_gt_irq_handler refactoring from Zhao Yakui
<yakui.zhao@intel.com>

v6: Adapt to upstream changes, dev_priv->irq_received is gone.

v7: Enable 3 the commented-out 3 pipe support.

v8: Grab irq_lock around i915_enable_pipestat()

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v2)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_irq.c | 249 +++++++++++++++++++++++++++++++++++++++-
 1 file changed, 248 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 407742f..1581b3d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1715,6 +1715,95 @@ out:
 	return ret;
 }
 
+static irqreturn_t cherryview_irq_handler(int irq, void *arg)
+{
+	struct drm_device *dev = (struct drm_device *) arg;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	u32 master_ctl, iir;
+	irqreturn_t ret = IRQ_NONE;
+	unsigned int pipes = 0;
+
+	master_ctl = I915_READ(GEN8_MASTER_IRQ);
+
+	I915_WRITE(GEN8_MASTER_IRQ, 0);
+
+	ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
+
+	iir = I915_READ(VLV_IIR);
+
+	if (iir & (I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT))
+		pipes |= 1 << 0;
+	if (iir & (I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT))
+		pipes |= 1 << 1;
+	if (iir & (I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT | I915_DISPLAY_PIPE_C_EVENT_INTERRUPT))
+		pipes |= 1 << 2;
+
+	if (pipes) {
+		u32 pipe_stats[I915_MAX_PIPES] = {};
+		unsigned long irqflags;
+		int pipe;
+
+		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+		for_each_pipe(pipe) {
+			unsigned int reg;
+
+			if (!(pipes & (1 << pipe)))
+				continue;
+
+			reg = PIPESTAT(pipe);
+			pipe_stats[pipe] = I915_READ(reg);
+
+			/*
+			 * Clear the PIPE*STAT regs before the IIR
+			 */
+			if (pipe_stats[pipe] & 0x8000ffff) {
+				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
+					DRM_DEBUG_DRIVER("pipe %c underrun\n",
+							 pipe_name(pipe));
+				I915_WRITE(reg, pipe_stats[pipe]);
+			}
+		}
+		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+
+		for_each_pipe(pipe) {
+			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
+				drm_handle_vblank(dev, pipe);
+
+			if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
+				intel_prepare_page_flip(dev, pipe);
+				intel_finish_page_flip(dev, pipe);
+			}
+		}
+
+		if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
+			gmbus_irq_handler(dev);
+
+		ret = IRQ_HANDLED;
+	}
+
+	/* Consume port.  Then clear IIR or we'll miss events */
+	if (iir & I915_DISPLAY_PORT_INTERRUPT) {
+		u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
+
+		I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
+
+		DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
+				 hotplug_status);
+		if (hotplug_status & HOTPLUG_INT_STATUS_I915)
+			queue_work(dev_priv->wq,
+				   &dev_priv->hotplug_work);
+
+		ret = IRQ_HANDLED;
+	}
+
+	I915_WRITE(VLV_IIR, iir);
+
+	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
+	POSTING_READ(GEN8_MASTER_IRQ);
+
+	return ret;
+}
+
 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -2985,6 +3074,61 @@ static void gen8_irq_preinstall(struct drm_device *dev)
 	ibx_irq_preinstall(dev);
 }
 
+static void cherryview_irq_preinstall(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	int pipe;
+
+	I915_WRITE(GEN8_MASTER_IRQ, 0);
+	POSTING_READ(GEN8_MASTER_IRQ);
+
+/* IIR can theoretically queue up two events. Be paranoid */
+#define GEN8_IRQ_INIT_NDX(type, which)				\
+do {								\
+	I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff);	\
+	POSTING_READ(GEN8_##type##_IMR(which));			\
+	I915_WRITE(GEN8_##type##_IER(which), 0);		\
+	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff);	\
+	POSTING_READ(GEN8_##type##_IIR(which));			\
+	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff);	\
+} while (0)
+
+#define GEN8_IRQ_INIT(type)					\
+do {								\
+	I915_WRITE(GEN8_##type##_IMR, 0xffffffff);		\
+	POSTING_READ(GEN8_##type##_IMR);			\
+	I915_WRITE(GEN8_##type##_IER, 0);			\
+	I915_WRITE(GEN8_##type##_IIR, 0xffffffff);		\
+	POSTING_READ(GEN8_##type##_IIR);			\
+	I915_WRITE(GEN8_##type##_IIR, 0xffffffff);		\
+} while (0)
+
+	GEN8_IRQ_INIT_NDX(GT, 0);
+	GEN8_IRQ_INIT_NDX(GT, 1);
+	GEN8_IRQ_INIT_NDX(GT, 2);
+	GEN8_IRQ_INIT_NDX(GT, 3);
+
+	GEN8_IRQ_INIT(PCU);
+
+#undef GEN8_IRQ_INIT
+#undef GEN8_IRQ_INIT_NDX
+
+	POSTING_READ(GEN8_PCU_IIR);
+
+	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
+
+	I915_WRITE(PORT_HOTPLUG_EN, 0);
+	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
+
+	for_each_pipe(pipe)
+		I915_WRITE(PIPESTAT(pipe), 0xffff);
+
+	I915_WRITE(VLV_IMR, 0xffffffff);
+	I915_WRITE(VLV_IER, 0x0);
+	I915_WRITE(VLV_IIR, 0xffffffff);
+	POSTING_READ(VLV_IIR);
+}
+
 static void ibx_hpd_irq_setup(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -3326,6 +3470,50 @@ static int gen8_irq_postinstall(struct drm_device *dev)
 	return 0;
 }
 
+static int cherryview_irq_postinstall(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
+		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
+		I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
+		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
+		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT |
+		I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
+		I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT;
+	u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
+	unsigned long irqflags;
+	int pipe;
+
+	/*
+	 * Leave vblank interrupts masked initially.  enable/disable will
+	 * toggle them based on usage.
+	 */
+	dev_priv->irq_mask = ~enable_mask |
+		I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
+		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT |
+		I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT;
+
+	for_each_pipe(pipe)
+		I915_WRITE(PIPESTAT(pipe), 0xffff);
+
+	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+	i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
+	for_each_pipe(pipe)
+		i915_enable_pipestat(dev_priv, pipe, pipestat_enable);
+	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+
+	I915_WRITE(VLV_IIR, 0xffffffff);
+	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
+	I915_WRITE(VLV_IER, enable_mask);
+
+	gen8_gt_irq_postinstall(dev_priv);
+
+	I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
+	POSTING_READ(GEN8_MASTER_IRQ);
+
+	return 0;
+}
+
 static void gen8_irq_uninstall(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3397,6 +3585,57 @@ static void valleyview_irq_uninstall(struct drm_device *dev)
 	POSTING_READ(VLV_IER);
 }
 
+static void cherryview_irq_uninstall(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	int pipe;
+
+	if (!dev_priv)
+		return;
+
+	I915_WRITE(GEN8_MASTER_IRQ, 0);
+	POSTING_READ(GEN8_MASTER_IRQ);
+
+#define GEN8_IRQ_FINI_NDX(type, which)				\
+do {								\
+	I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff);	\
+	I915_WRITE(GEN8_##type##_IER(which), 0);		\
+	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff);	\
+	POSTING_READ(GEN8_##type##_IIR(which));			\
+	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff);	\
+} while (0)
+
+#define GEN8_IRQ_FINI(type)				\
+do {							\
+	I915_WRITE(GEN8_##type##_IMR, 0xffffffff);	\
+	I915_WRITE(GEN8_##type##_IER, 0);		\
+	I915_WRITE(GEN8_##type##_IIR, 0xffffffff);	\
+	POSTING_READ(GEN8_##type##_IIR);		\
+	I915_WRITE(GEN8_##type##_IIR, 0xffffffff);	\
+} while (0)
+
+	GEN8_IRQ_FINI_NDX(GT, 0);
+	GEN8_IRQ_FINI_NDX(GT, 1);
+	GEN8_IRQ_FINI_NDX(GT, 2);
+	GEN8_IRQ_FINI_NDX(GT, 3);
+
+	GEN8_IRQ_FINI(PCU);
+
+#undef GEN8_IRQ_FINI
+#undef GEN8_IRQ_FINI_NDX
+
+	I915_WRITE(PORT_HOTPLUG_EN, 0);
+	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
+
+	for_each_pipe(pipe)
+		I915_WRITE(PIPESTAT(pipe), 0xffff);
+
+	I915_WRITE(VLV_IMR, 0xffffffff);
+	I915_WRITE(VLV_IER, 0x0);
+	I915_WRITE(VLV_IIR, 0xffffffff);
+	POSTING_READ(VLV_IIR);
+}
+
 static void ironlake_irq_uninstall(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -4119,7 +4358,15 @@ void intel_irq_init(struct drm_device *dev)
 		dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
 	}
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_CHERRYVIEW(dev)) {
+		dev->driver->irq_handler = cherryview_irq_handler;
+		dev->driver->irq_preinstall = cherryview_irq_preinstall;
+		dev->driver->irq_postinstall = cherryview_irq_postinstall;
+		dev->driver->irq_uninstall = cherryview_irq_uninstall;
+		dev->driver->enable_vblank = valleyview_enable_vblank;
+		dev->driver->disable_vblank = valleyview_disable_vblank;
+		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
+	} else if (IS_VALLEYVIEW(dev)) {
 		dev->driver->irq_handler = valleyview_irq_handler;
 		dev->driver->irq_preinstall = valleyview_irq_preinstall;
 		dev->driver->irq_postinstall = valleyview_irq_postinstall;
-- 
1.8.3.2

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[PATCH 11/71] drm/i915/chv: Add Cherryview interrupt registers into debugfs

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Make i915_gem_interrupt debugfs file functional on CHV.

FIXME: Extract helpers for gt/display blocks to shrink the function a
bit and avoid duplication between bdw/chv (and other similar cases for
upstream).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 42 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 41 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 506177a..1efb885 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -638,7 +638,47 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
 		return ret;
 	intel_runtime_pm_get(dev_priv);
 
-	if (INTEL_INFO(dev)->gen >= 8) {
+	if (IS_CHERRYVIEW(dev)) {
+		int i;
+		seq_printf(m, "Master Interrupt Control:\t%08x\n",
+			   I915_READ(GEN8_MASTER_IRQ));
+
+		seq_printf(m, "Display IER:\t%08x\n",
+			   I915_READ(VLV_IER));
+		seq_printf(m, "Display IIR:\t%08x\n",
+			   I915_READ(VLV_IIR));
+		seq_printf(m, "Display IIR_RW:\t%08x\n",
+			   I915_READ(VLV_IIR_RW));
+		seq_printf(m, "Display IMR:\t%08x\n",
+			   I915_READ(VLV_IMR));
+		for_each_pipe(pipe)
+			seq_printf(m, "Pipe %c stat:\t%08x\n",
+				   pipe_name(pipe),
+				   I915_READ(PIPESTAT(pipe)));
+
+		seq_printf(m, "Port hotplug:\t%08x\n",
+			   I915_READ(PORT_HOTPLUG_EN));
+		seq_printf(m, "DPFLIPSTAT:\t%08x\n",
+			   I915_READ(VLV_DPFLIPSTAT));
+		seq_printf(m, "DPINVGTT:\t%08x\n",
+			   I915_READ(DPINVGTT));
+
+		for (i = 0; i < 4; i++) {
+			seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
+				   i, I915_READ(GEN8_GT_IMR(i)));
+			seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
+				   i, I915_READ(GEN8_GT_IIR(i)));
+			seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
+				   i, I915_READ(GEN8_GT_IER(i)));
+		}
+
+		seq_printf(m, "PCU interrupt mask:\t%08x\n",
+			   I915_READ(GEN8_PCU_IMR));
+		seq_printf(m, "PCU interrupt identity:\t%08x\n",
+			   I915_READ(GEN8_PCU_IIR));
+		seq_printf(m, "PCU interrupt enable:\t%08x\n",
+			   I915_READ(GEN8_PCU_IER));
+	} else if (INTEL_INFO(dev)->gen >= 8) {
 		seq_printf(m, "Master Interrupt Control:\t%08x\n",
 			   I915_READ(GEN8_MASTER_IRQ));
 
-- 
1.8.3.2

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[PATCH 12/71] drm/i915/chv: Initial clock gating support for Cherryview

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

CHV clock gating isn't identical to VLV, so add a new function
for it. This is only a start, and further changes are needed as
the details become available.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 21cfbc7..0889af7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5122,6 +5122,15 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
 }
 
+static void cherryview_init_clock_gating(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
+
+	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
+}
+
 static void g4x_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6015,6 +6024,10 @@ void intel_init_pm(struct drm_device *dev)
 			dev_priv->display.init_clock_gating = haswell_init_clock_gating;
 		else if (INTEL_INFO(dev)->gen == 8)
 			dev_priv->display.init_clock_gating = gen8_init_clock_gating;
+	} else if (IS_CHERRYVIEW(dev)) {
+		dev_priv->display.update_wm = valleyview_update_wm;
+		dev_priv->display.init_clock_gating =
+			cherryview_init_clock_gating;
 	} else if (IS_VALLEYVIEW(dev)) {
 		dev_priv->display.update_wm = valleyview_update_wm;
 		dev_priv->display.init_clock_gating =
-- 
1.8.3.2

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[PATCH 13/71] drm/i915/chv: Add Cherryview PCI IDs

[ville.syrjala]

From: Daniel Vetter <daniel.vetter@ffwll.ch>

v2: Update to also fill in the new num_pipes field.

v3: Rebase on top of the pciid extraction.

v4: Switch from info->has*ring to info->ring mask. Also add VEBOX support whiel
at it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.c | 12 +++++++++++-
 include/drm/i915_pciids.h       |  6 ++++++
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index fa5d0ed..2415fa2 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -279,6 +279,15 @@ static const struct intel_device_info intel_broadwell_m_info = {
 	GEN_DEFAULT_PIPEOFFSETS,
 };
 
+static const struct intel_device_info intel_cherryview_info = {
+	.is_preliminary = 1,
+	.gen = 8, .num_pipes = 2,
+	.need_gfx_hws = 1, .has_hotplug = 1,
+	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+	.is_valleyview = 1,
+	.display_mmio_offset = VLV_DISPLAY_BASE,
+};
+
 /*
  * Make sure any device matches here are from most specific to most
  * general.  For example, since the Quanta match is based on the subsystem
@@ -312,7 +321,8 @@ static const struct intel_device_info intel_broadwell_m_info = {
 	INTEL_VLV_M_IDS(&intel_valleyview_m_info),	\
 	INTEL_VLV_D_IDS(&intel_valleyview_d_info),	\
 	INTEL_BDW_M_IDS(&intel_broadwell_m_info),	\
-	INTEL_BDW_D_IDS(&intel_broadwell_d_info)
+	INTEL_BDW_D_IDS(&intel_broadwell_d_info),	\
+	INTEL_CHV_PCI_IDS(&intel_cherryview_info)
 
 static const struct pci_device_id pciidlist[] = {		/* aka */
 	INTEL_PCI_IDS,
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 940ece4..c4f03a4 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -233,4 +233,10 @@
 	_INTEL_BDW_D_IDS(2, info), \
 	_INTEL_BDW_D_IDS(3, info)
 
+#define INTEL_CHV_PCI_IDS(info) \
+	INTEL_VGA_DEVICE(0x22b0, info), \
+	INTEL_VGA_DEVICE(0x22b1, info), \
+	INTEL_VGA_DEVICE(0x22b2, info), \
+	INTEL_VGA_DEVICE(0x22b3, info) \
+
 #endif /* _I915_PCIIDS_H */
-- 
1.8.3.2

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[PATCH 14/71] drm/i915/chv: Add early quirk for stolen

[ville.syrjala]

From: Daniel Vetter <daniel.vetter@ffwll.ch>

Same as on other gen8 devices.

Cc: Ingo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 arch/x86/kernel/early-quirks.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index bc4a088..5758f5b 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -347,7 +347,8 @@ static struct pci_device_id intel_stolen_ids[] __initdata = {
 	INTEL_HSW_D_IDS(gen6_stolen_size),
 	INTEL_HSW_M_IDS(gen6_stolen_size),
 	INTEL_BDW_M_IDS(gen8_stolen_size),
-	INTEL_BDW_D_IDS(gen8_stolen_size)
+	INTEL_BDW_D_IDS(gen8_stolen_size),
+	INTEL_CHV_PCI_IDS(gen8_stolen_size)
 };
 
 static void __init intel_graphics_stolen(int num, int slot, int func)
-- 
1.8.3.2

[PATCH 15/71] drm/i915/chv: Add DDL register defines for Cherryview

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Fill in the sprite bits for DDL1/DDL2 registers, and add DDL3.

Still need to write the code to use these...

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 98f549a..c7ec7d6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3552,14 +3552,43 @@ enum punit_power_well {
 #define DDL_CURSORA_PRECISION_32	(1<<31)
 #define DDL_CURSORA_PRECISION_16	(0<<31)
 #define DDL_CURSORA_SHIFT		24
+#define DDL_SPRITEB_PRECISION_32	(1<<23)
+#define DDL_SPRITEB_PRECISION_16	(0<<23)
+#define DDL_SPRITEB_SHIFT		16
+#define DDL_SPRITEA_PRECISION_32	(1<<15)
+#define DDL_SPRITEA_PRECISION_16	(0<<15)
+#define DDL_SPRITEA_SHIFT		8
 #define DDL_PLANEA_PRECISION_32		(1<<7)
 #define DDL_PLANEA_PRECISION_16		(0<<7)
+#define DDL_PLANEA_SHIFT		0
+
 #define VLV_DDL2			(VLV_DISPLAY_BASE + 0x70054)
 #define DDL_CURSORB_PRECISION_32	(1<<31)
 #define DDL_CURSORB_PRECISION_16	(0<<31)
 #define DDL_CURSORB_SHIFT		24
+#define DDL_SPRITED_PRECISION_32	(1<<23)
+#define DDL_SPRITED_PRECISION_16	(0<<23)
+#define DDL_SPRITED_SHIFT		16
+#define DDL_SPRITEC_PRECISION_32	(1<<15)
+#define DDL_SPRITEC_PRECISION_16	(0<<15)
+#define DDL_SPRITEC_SHIFT		8
 #define DDL_PLANEB_PRECISION_32		(1<<7)
 #define DDL_PLANEB_PRECISION_16		(0<<7)
+#define DDL_PLANEB_SHIFT		0
+
+#define VLV_DDL3			(VLV_DISPLAY_BASE + 0x70058)
+#define DDL_CURSORC_PRECISION_32	(1<<31)
+#define DDL_CURSORC_PRECISION_16	(0<<31)
+#define DDL_CURSORC_SHIFT		24
+#define DDL_SPRITEF_PRECISION_32	(1<<23)
+#define DDL_SPRITEF_PRECISION_16	(0<<23)
+#define DDL_SPRITEF_SHIFT		16
+#define DDL_SPRITEE_PRECISION_32	(1<<15)
+#define DDL_SPRITEE_PRECISION_16	(0<<15)
+#define DDL_SPRITEE_SHIFT		8
+#define DDL_PLANEC_PRECISION_32		(1<<7)
+#define DDL_PLANEC_PRECISION_16		(0<<7)
+#define DDL_PLANEC_SHIFT		0
 
 /* FIFO watermark sizes etc */
 #define G4X_FIFO_LINE_SIZE	64
-- 
1.8.3.2

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[PATCH 16/71] drm/i915/chv: Add DPIO offset for Cherryview. v3

[ville.syrjala]

From: Chon Ming Lee <chon.ming.lee@intel.com>

CHV has 2 display phys.  First phy (IOSF offset 0x1A) has two channels,
and second phy (IOSF offset 0x12) has single channel.  The first phy is
used for port B and port C, while second phy is only for port D.

v2: Move the pipe to determine which phy to select for
vlv_dpio_read/vlv_dpio_write to another patch. (Daniel)
v3: Rebase the code based on rework on how to calculate DPIO offset.

Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  2 +-
 drivers/gpu/drm/i915/i915_reg.h      |  1 +
 drivers/gpu/drm/i915/intel_display.c | 12 +++++++++++-
 3 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4abaa9e..07a162c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -92,7 +92,7 @@ enum port {
 };
 #define port_name(p) ((p) + 'A')
 
-#define I915_NUM_PHYS_VLV 1
+#define I915_NUM_PHYS_VLV 2
 
 enum dpio_channel {
 	DPIO_CH0,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c7ec7d6..beb04ab 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -457,6 +457,7 @@
 #define   IOSF_PORT_PUNIT			0x4
 #define   IOSF_PORT_NC				0x11
 #define   IOSF_PORT_DPIO			0x12
+#define   IOSF_PORT_DPIO_2			0x1a
 #define   IOSF_PORT_GPIO_NC			0x13
 #define   IOSF_PORT_CCK				0x14
 #define   IOSF_PORT_CCU				0xA9
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9a50b64..df6732e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1367,7 +1367,17 @@ static void intel_init_dpio(struct drm_device *dev)
 	if (!IS_VALLEYVIEW(dev))
 		return;
 
-	DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
+	/*
+	 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
+	 * CHV x1 PHY (DP/HDMI D)
+	 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
+	 */
+	if (IS_CHERRYVIEW(dev)) {
+		DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
+		DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
+	} else {
+		DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
+	}
 }
 
 static void intel_reset_dpio(struct drm_device *dev)
-- 
1.8.3.2

[PATCH 17/71] drm/i915/chv: Update Cherryview DPLL changes to support Port D. v2

[ville.syrjala]

From: Chon Ming Lee <chon.ming.lee@intel.com>

The additional DPLL registers added to support Port D.  Besides, add
some new PHY control and status registers based on B-spec.

v2: Based on Ville review
	- Corrected DPIO_PHY_STATUS offset and name.
    - Rebase based on upstream change after introduce enum dpio_phy and
      enum dpio_channel.

v3: Rebased on top of Antti's 3-pipe prep patch. Note that the new offsets for
the DPLL registers aren't in place yet, so this introduces a slight regression.
But since 3 pipe support isn't fully enabled yet anyaway in -internal this
shouldn't matter too much.

Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  6 ++++++
 drivers/gpu/drm/i915/intel_display.c | 11 +++++++++--
 drivers/gpu/drm/i915/intel_drv.h     |  1 +
 3 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index beb04ab..8aea092 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -29,6 +29,8 @@
 #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
 
 #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
+#define _PIPE3(pipe, a, b, c) (pipe < 2 ? _PIPE(pipe, a, b) : c)
+#define _PORT3(port, a, b, c) (port < 2 ? _PORT(port, a, b) : c)
 
 #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
 #define _MASKED_BIT_DISABLE(a) ((a) << 16)
@@ -1385,6 +1387,10 @@ enum punit_power_well {
 #define   DPLL_PORTB_READY_MASK		(0xf)
 
 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
+
+/* Additional CHV pll/phy registers */
+#define DPIO_PHY_STATUS			(VLV_DISPLAY_BASE + 0x6240)
+#define   DPLL_PORTD_READY_MASK		(0xf)
 /*
  * The i830 generation, in LVDS mode, defines P1 as the bit number set within
  * this field (only one bit may be set).
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index df6732e..153f244 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1535,21 +1535,28 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 		struct intel_digital_port *dport)
 {
 	u32 port_mask;
+	int dpll_reg;
 
 	switch (dport->port) {
 	case PORT_B:
 		port_mask = DPLL_PORTB_READY_MASK;
+		dpll_reg = DPLL(0);
 		break;
 	case PORT_C:
 		port_mask = DPLL_PORTC_READY_MASK;
+		dpll_reg = DPLL(0);
+		break;
+	case PORT_D:
+		port_mask = DPLL_PORTD_READY_MASK;
+		dpll_reg = DPIO_PHY_STATUS;
 		break;
 	default:
 		BUG();
 	}
 
-	if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
+	if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
 		WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
-		     port_name(dport->port), I915_READ(DPLL(0)));
+		     port_name(dport->port), I915_READ(dpll_reg));
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9002e77..087e471 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -535,6 +535,7 @@ vlv_dport_to_channel(struct intel_digital_port *dport)
 {
 	switch (dport->port) {
 	case PORT_B:
+	case PORT_D:
 		return DPIO_CH0;
 	case PORT_C:
 		return DPIO_CH1;
-- 
1.8.3.2

[PATCH 18/71] drm/i915/chv: Add vlv_pipe_to_channel

[ville.syrjala]

From: Chon Ming Lee <chon.ming.lee@intel.com>

Cherryview has 3 pipes.  Some of the pll dpio offset calculation is
based on pipe number.  Need to use vlv_pipe_to_channel to calculate the
correct phy channel to use for the pipe.

Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 087e471..e572799 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -544,6 +544,20 @@ vlv_dport_to_channel(struct intel_digital_port *dport)
 	}
 }
 
+static inline int
+vlv_pipe_to_channel(enum pipe pipe)
+{
+	switch (pipe) {
+	case PIPE_A:
+	case PIPE_C:
+		return DPIO_CH0;
+	case PIPE_B:
+		return DPIO_CH1;
+	default:
+		BUG();
+	}
+}
+
 static inline struct drm_crtc *
 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 {
-- 
1.8.3.2

[PATCH 19/71] drm/i915/chv: Trigger phy common lane reset

[ville.syrjala]

From: Chon Ming Lee <chon.ming.lee@intel.com>

During cold boot, the display controller needs to deassert the common
lane reset.  Only do it once during intel_init_dpio for both PHYx2 and
PHYx1.

Besides, assert the common lane reset when disable pll.  This still
to be determined whether need to do it by driver.

Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
[vsyrjala: Don't disable DPIO PLL when using DSI]
[vsyrjala: Don't call vlv_disable_pll() by accident on CHV]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  8 +++++
 drivers/gpu/drm/i915/intel_display.c | 66 ++++++++++++++++++++++++++++--------
 2 files changed, 59 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8aea092..8fcf4ea 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1391,6 +1391,14 @@ enum punit_power_well {
 /* Additional CHV pll/phy registers */
 #define DPIO_PHY_STATUS			(VLV_DISPLAY_BASE + 0x6240)
 #define   DPLL_PORTD_READY_MASK		(0xf)
+#define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)
+#define   PHY_COM_LANE_RESET_DEASSERT(phy, val) \
+				((phy == DPIO_PHY0) ? (val | 1) : (val | 2))
+#define   PHY_COM_LANE_RESET_ASSERT(phy, val) \
+				((phy == DPIO_PHY0) ? (val & ~1) : (val & ~2))
+#define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104)
+#define   PHY_POWERGOOD(phy)	((phy == DPIO_PHY0) ? (1<<31) : (1<<30))
+
 /*
  * The i830 generation, in LVDS mode, defines P1 as the bit number set within
  * this field (only one bit may be set).
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 153f244..e33667d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1395,17 +1395,36 @@ static void intel_reset_dpio(struct drm_device *dev)
 		   DPLL_REFA_CLK_ENABLE_VLV |
 		   DPLL_INTEGRATED_CRI_CLK_VLV);
 
-	/*
-	 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
-	 *  6.	De-assert cmn_reset/side_reset. Same as VLV X0.
-	 *   a.	GUnit 0x2110 bit[0] set to 1 (def 0)
-	 *   b.	The other bits such as sfr settings / modesel may all be set
-	 *      to 0.
-	 *
-	 * This should only be done on init and resume from S3 with both
-	 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
-	 */
-	I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
+	if (IS_CHERRYVIEW(dev)) {
+		enum dpio_phy phy;
+		u32 val;
+
+		for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
+			/* Poll for phypwrgood signal */
+			if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
+						PHY_POWERGOOD(phy), 1))
+				DRM_ERROR("Display PHY %d is not power up\n", phy);
+
+			/* Deassert common lane reset for PHY*/
+			val = I915_READ(DISPLAY_PHY_CONTROL);
+			I915_WRITE(DISPLAY_PHY_CONTROL,
+				PHY_COM_LANE_RESET_DEASSERT(phy, val));
+		}
+
+	} else {
+		/*
+		 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
+		 *  6.	De-assert cmn_reset/side_reset. Same as VLV X0.
+		 *   a.	GUnit 0x2110 bit[0] set to 1 (def 0)
+		 *   b.	The other bits such as sfr settings / modesel may all
+		 *	be set to 0.
+		 *
+		 * This should only be done on init and resume from S3 with
+		 * both PLLs disabled, or we risk losing DPIO and PLL
+		 * synchronization.
+		 */
+		I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
+	}
 }
 
 static void vlv_enable_pll(struct intel_crtc *crtc)
@@ -1529,6 +1548,19 @@ static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 		val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
 	I915_WRITE(DPLL(pipe), val);
 	POSTING_READ(DPLL(pipe));
+
+}
+
+static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
+{
+	int dpll = DPLL(pipe);
+	u32 val;
+
+	/* Set PLL en = 0 */
+	val = I915_READ(dpll);
+	val &= ~DPLL_VCO_ENABLE;
+	I915_WRITE(dpll, val);
+
 }
 
 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
@@ -4511,10 +4543,14 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
 		if (encoder->post_disable)
 			encoder->post_disable(encoder);
 
-	if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
-		vlv_disable_pll(dev_priv, pipe);
-	else if (!IS_VALLEYVIEW(dev))
-		i9xx_disable_pll(dev_priv, pipe);
+	if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
+		if (IS_CHERRYVIEW(dev))
+			chv_disable_pll(dev_priv, pipe);
+		else if (IS_VALLEYVIEW(dev))
+			vlv_disable_pll(dev_priv, pipe);
+		else
+			i9xx_disable_pll(dev_priv, pipe);
+	}
 
 	intel_crtc->active = false;
 	intel_update_watermarks(crtc);
-- 
1.8.3.2

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[PATCH 20/71] drm/i915/chv: find the best divisor for the target clock v4

[ville.syrjala]

From: Chon Ming Lee <chon.ming.lee@intel.com>

Based on the chv clock limit, find the best divisor.

The divisor data has been verified with this spreadsheet.
P1273_DPLL_Programming Spreadsheet.

v2: Rebase the code and change the chv_find_best_dpll based on new
standard way to use intel_PLL_is_valid.  Besides, clean up some extra
variables.

v3: Ville suggest better fixed point for m2 calculation.

v4: -Add comment for the limit is compute using fast clock. (Ville)
	-Don't pass the request clock to chv_clock, as the same function will
	 be use clock readout, which doens't have request clock. (Ville)
	-Add and use DIV_ROUND_CLOSEST_ULL to consistent with other clock
	calculation. (Ville)
	-Fix the dp m2 after m2 has stored fixed point. (Ville)

Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
[vsyrjala: Avoid div-by-zero in chv_clock()]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 86 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_dp.c      | 21 +++++++++
 2 files changed, 107 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e33667d..d73fec5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -41,6 +41,9 @@
 #include <drm/drm_crtc_helper.h>
 #include <linux/dma_remapping.h>
 
+#define DIV_ROUND_CLOSEST_ULL(ll, d)	\
+	({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
+
 static void intel_increase_pllclock(struct drm_crtc *crtc);
 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
 
@@ -328,6 +331,22 @@ static const intel_limit_t intel_limits_vlv = {
 	.p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 };
 
+static const intel_limit_t intel_limits_chv = {
+	/*
+	 * These are the data rate limits (measured in fast clocks)
+	 * since those are the strictest limits we have.  The fast
+	 * clock and actual rate limits are more relaxed, so checking
+	 * them would make no difference.
+	 */
+	.dot = { .min = 25000 * 5, .max = 540000 * 5},
+	.vco = { .min = 4860000, .max = 6700000 },
+	.n = { .min = 1, .max = 1 },
+	.m1 = { .min = 2, .max = 2 },
+	.m2 = { .min = 24 << 22, .max = 175 << 22 },
+	.p1 = { .min = 2, .max = 4 },
+	.p2 = {	.p2_slow = 1, .p2_fast = 14 },
+};
+
 static void vlv_clock(int refclk, intel_clock_t *clock)
 {
 	clock->m = clock->m1 * clock->m2;
@@ -412,6 +431,8 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 			limit = &intel_limits_pineview_lvds;
 		else
 			limit = &intel_limits_pineview_sdvo;
+	} else if (IS_CHERRYVIEW(dev)) {
+		limit = &intel_limits_chv;
 	} else if (IS_VALLEYVIEW(dev)) {
 		limit = &intel_limits_vlv;
 	} else if (!IS_GEN2(dev)) {
@@ -456,6 +477,17 @@ static void i9xx_clock(int refclk, intel_clock_t *clock)
 	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 }
 
+static void chv_clock(int refclk, intel_clock_t *clock)
+{
+	clock->m = clock->m1 * clock->m2;
+	clock->p = clock->p1 * clock->p2;
+	if (WARN_ON(clock->n == 0 || clock->p == 0))
+		return;
+	clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
+			clock->n << 22);
+	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
+}
+
 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 /**
  * Returns whether the given set of divisors are valid for a given refclk with
@@ -731,6 +763,58 @@ vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 	return found;
 }
 
+static bool
+chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
+		   int target, int refclk, intel_clock_t *match_clock,
+		   intel_clock_t *best_clock)
+{
+	struct drm_device *dev = crtc->dev;
+	intel_clock_t clock;
+	uint64_t m2;
+	int found = false;
+
+	memset(best_clock, 0, sizeof(*best_clock));
+
+	/*
+	 * Based on hardware doc, the n always set to 1, and m1 always
+	 * set to 2.  If requires to support 200Mhz refclk, we need to
+	 * revisit this because n may not 1 anymore.
+	 */
+	clock.n = 1, clock.m1 = 2;
+	target *= 5;	/* fast clock */
+
+	for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
+		for (clock.p2 = limit->p2.p2_fast;
+				clock.p2 >= limit->p2.p2_slow;
+				clock.p2 -= clock.p2 > 10 ? 2 : 1) {
+
+			clock.p = clock.p1 * clock.p2;
+
+			m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
+					clock.n) << 22, refclk * clock.m1);
+
+			if (m2 > INT_MAX/clock.m1)
+				continue;
+
+			clock.m2 = m2;
+
+			chv_clock(refclk, &clock);
+
+			if (!intel_PLL_is_valid(dev, limit, &clock))
+				continue;
+
+			/* based on hardware requirement, prefer bigger p
+			 */
+			if (clock.p > best_clock->p) {
+				*best_clock = clock;
+				found = true;
+			}
+		}
+	}
+
+	return found;
+}
+
 bool intel_crtc_active(struct drm_crtc *crtc)
 {
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -11031,6 +11115,8 @@ static void intel_init_display(struct drm_device *dev)
 
 	if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
 		dev_priv->display.find_dpll = g4x_find_best_dpll;
+	else if (IS_CHERRYVIEW(dev))
+		dev_priv->display.find_dpll = chv_find_best_dpll;
 	else if (IS_VALLEYVIEW(dev))
 		dev_priv->display.find_dpll = vlv_find_best_dpll;
 	else if (IS_PINEVIEW(dev))
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c33971e..6be7b35 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -64,6 +64,24 @@ static const struct dp_link_dpll vlv_dpll[] = {
 		{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
 };
 
+/*
+ * CHV supports eDP 1.4 that have  more link rates.
+ * Below only provides the fixed rate but exclude variable rate.
+ */
+static const struct dp_link_dpll chv_dpll[] = {
+	/*
+	 * CHV requires to program fractional division for m2.
+	 * m2 is stored in fixed point format using formula below
+	 * (m2_int << 22) | m2_fraction
+	 */
+	{ DP_LINK_BW_1_62,	/* m2_int = 32, m2_fraction = 1677722 */
+		{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
+	{ DP_LINK_BW_2_7,	/* m2_int = 27, m2_fraction = 0 */
+		{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
+	{ DP_LINK_BW_5_4,	/* m2_int = 27, m2_fraction = 0 */
+		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
+};
+
 /**
  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  * @intel_dp: DP struct
@@ -720,6 +738,9 @@ intel_dp_set_clock(struct intel_encoder *encoder,
 	} else if (HAS_PCH_SPLIT(dev)) {
 		divisor = pch_dpll;
 		count = ARRAY_SIZE(pch_dpll);
+	} else if (IS_CHERRYVIEW(dev)) {
+		divisor = chv_dpll;
+		count = ARRAY_SIZE(chv_dpll);
 	} else if (IS_VALLEYVIEW(dev)) {
 		divisor = vlv_dpll;
 		count = ARRAY_SIZE(vlv_dpll);
-- 
1.8.3.2

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[PATCH 21/71] drm/i915/chv: Add update and enable pll for Cherryview

[ville.syrjala]

From: Chon Ming Lee <chon.ming.lee@intel.com>

Added programming PLL for CHV based on "Application note for 1273 CHV
Display phy".

v2:  -Break the common lane reset into another patch.
     -Break the clock calculation into another patch.

    -The changes are based on Ville review.
    -Rework based on DPIO register define naming convention change.
    -Break the dpio write into few lines to improve readability.
    -Correct the udelay during chv_enable_pll.
    -clean up some magic numbers with some new define.
    -program the afc recal bit which was missed.

v3: Based on Ville review
	-  minor correction of the bit defination
    - add deassert/propagate data lane reset

v4: Corrected the udelay between dclkp enable and pll enable.
	Minor comment and better way to clear the TX lane reset.

v5: Squash in fixup from Rafael Barbalho.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  70 ++++++++++++++++++
 drivers/gpu/drm/i915/intel_display.c | 133 ++++++++++++++++++++++++++++++++++-
 2 files changed, 201 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8fcf4ea..75f31f5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -668,6 +668,12 @@ enum punit_power_well {
 #define _VLV_PCS_DW9_CH1		0x8424
 #define	VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
 
+#define _CHV_PCS_DW10_CH0		0x8228
+#define _CHV_PCS_DW10_CH1		0x8428
+#define   DPIO_PCS_SWING_CALC_TX0_TX2	(1<<30)
+#define   DPIO_PCS_SWING_CALC_TX1_TX3	(1<<31)
+#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
+
 #define _VLV_PCS_DW11_CH0		0x822c
 #define _VLV_PCS_DW11_CH1		0x842c
 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
@@ -686,14 +692,21 @@ enum punit_power_well {
 
 #define _VLV_TX_DW2_CH0			0x8288
 #define _VLV_TX_DW2_CH1			0x8488
+#define   DPIO_UNIQ_TRANS_SCALE_SHIFT	8
+#define   DPIO_SWING_MARGIN_SHIFT	16
+#define   DPIO_SWING_MARGIN_MASK	(0xff << DPIO_SWING_MARGIN_SHIFT)
 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
 
 #define _VLV_TX_DW3_CH0			0x828c
 #define _VLV_TX_DW3_CH1			0x848c
+/* The following bit for CHV phy */
+#define   DPIO_TX_UNIQ_TRANS_SCALE_EN	(1<<27)
 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
 
 #define _VLV_TX_DW4_CH0			0x8290
 #define _VLV_TX_DW4_CH1			0x8490
+#define   DPIO_SWING_DEEMPH9P5_SHIFT	24
+#define   DPIO_SWING_DEEMPH9P5_MASK	(0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
 
 #define _VLV_TX3_DW4_CH0		0x690
@@ -713,6 +726,62 @@ enum punit_power_well {
 #define _VLV_TX_DW14_CH1		0x84b8
 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
 
+/* CHV dpPhy registers */
+#define _CHV_PLL_DW0_CH0		0x8000
+#define _CHV_PLL_DW0_CH1		0x8180
+#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
+
+#define _CHV_PLL_DW1_CH0		0x8004
+#define _CHV_PLL_DW1_CH1		0x8184
+#define   DPIO_CHV_M1_DIV_BY_2		(0 << 0)
+#define   DPIO_CHV_N_DIV_SHIFT		(8)
+#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
+
+#define _CHV_PLL_DW2_CH0		0x8008
+#define _CHV_PLL_DW2_CH1		0x8188
+#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
+
+#define _CHV_PLL_DW3_CH0		0x800c
+#define _CHV_PLL_DW3_CH1		0x818c
+#define  DPIO_CHV_FEEDFWD_GAIN		2
+#define  DPIO_CHV_FIRST_MOD		(0 << 8)
+#define  DPIO_CHV_SECOND_MOD		(1 << 8)
+#define  DPIO_CHV_FRAC_DIV_EN		(1 << 16)
+#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
+
+#define _CHV_PLL_DW6_CH0		0x8018
+#define _CHV_PLL_DW6_CH1		0x8198
+#define   DPIO_CHV_PROP_COEFF		(5 << 0)
+#define   DPIO_CHV_GAIN_CTRL		(2 << 16)
+#define	  DPIO_CHV_INT_COEFF_SHIFT	8
+#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
+
+#define _CHV_CMN_DW13_CH0		0x8134
+#define _CHV_CMN_DW0_CH1		0x8080
+#define   DPIO_CHV_S1_DIV_SELECT	(21)
+#define   DPIO_CHV_P1_SHIFT		(13) /* 3 bits */
+#define   DPIO_CHV_P2_SHIFT		(8)  /* 5 bits */
+#define   DPIO_CHV_K_DIV_SHIFT		(4)
+#define   DPIO_PLL_LOCK			0x1
+#define   DPIO_PLL_FREQLOCK		0x2
+#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
+
+#define _CHV_CMN_DW14_CH0		0x8138
+#define _CHV_CMN_DW1_CH1		0x8084
+#define   DPIO_AFC_RECAL		(1 << 14)
+#define   DPIO_DCLKP_EN			(1 << 13)
+#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
+
+#define CHV_CMN_DW30			0x8178
+#define   DPIO_LRC_BYPASS		(1 << 3)
+
+#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
+					(lane) * 0x200 + (offset))
+
+#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
+#define   DPIO_FRC_LATENCY_SHFIT	(8)
+#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
+#define   DPIO_UPAR_SHIFT		(30)
 /*
  * Fence registers
  */
@@ -1383,6 +1452,7 @@ enum punit_power_well {
 #define   DPLL_LOCK_VLV			(1<<15)
 #define   DPLL_INTEGRATED_CRI_CLK_VLV	(1<<14)
 #define   DPLL_INTEGRATED_CLOCK_VLV	(1<<13)
+#define   DPLL_SSC_REF_CLOCK_CHV	(1<<13)
 #define   DPLL_PORTC_READY_MASK		(0xf << 4)
 #define   DPLL_PORTB_READY_MASK		(0xf)
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d73fec5..36d6e212 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1549,6 +1549,49 @@ static void vlv_enable_pll(struct intel_crtc *crtc)
 	udelay(150); /* wait for warmup */
 }
 
+static void chv_enable_pll(struct intel_crtc *crtc)
+{
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int pipe = crtc->pipe;
+	enum dpio_channel port = vlv_pipe_to_channel(pipe);
+	int dpll = DPLL(crtc->pipe);
+	u32 tmp;
+
+	assert_pipe_disabled(dev_priv, crtc->pipe);
+
+	BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
+
+	mutex_lock(&dev_priv->dpio_lock);
+
+	/* Enable back the 10bit clock to display controller */
+	tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
+	tmp |= DPIO_DCLKP_EN;
+	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
+
+	/*
+	 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
+	 */
+	udelay(1);
+
+	/* Enable PLL */
+	tmp = I915_READ(dpll);
+	tmp |= DPLL_VCO_ENABLE;
+	I915_WRITE(dpll, tmp);
+
+	/* Check PLL is locked */
+	if (wait_for(((I915_READ(dpll) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
+		DRM_ERROR("PLL %d failed to lock\n", pipe);
+
+	/* Deassert soft data lane reset*/
+	tmp = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
+	tmp |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), tmp);
+
+
+	mutex_unlock(&dev_priv->dpio_lock);
+}
+
 static void i9xx_enable_pll(struct intel_crtc *crtc)
 {
 	struct drm_device *dev = crtc->base.dev;
@@ -4503,8 +4546,12 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 
 	is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
 
-	if (!is_dsi)
-		vlv_enable_pll(intel_crtc);
+	if (!is_dsi) {
+		if (IS_CHERRYVIEW(dev))
+			chv_enable_pll(intel_crtc);
+		else
+			vlv_enable_pll(intel_crtc);
+	}
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->pre_enable)
@@ -5385,6 +5432,86 @@ static void vlv_update_pll(struct intel_crtc *crtc)
 	mutex_unlock(&dev_priv->dpio_lock);
 }
 
+static void chv_update_pll(struct intel_crtc *crtc)
+{
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int pipe = crtc->pipe;
+	int dpll_reg = DPLL(crtc->pipe);
+	enum dpio_channel port = vlv_pipe_to_channel(pipe);
+	u32 val, loopfilter, intcoeff;
+	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
+	int refclk;
+
+	mutex_lock(&dev_priv->dpio_lock);
+
+	bestn = crtc->config.dpll.n;
+	bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
+	bestm1 = crtc->config.dpll.m1;
+	bestm2 = crtc->config.dpll.m2 >> 22;
+	bestp1 = crtc->config.dpll.p1;
+	bestp2 = crtc->config.dpll.p2;
+
+	/*
+	 * Enable Refclk and SSC
+	 */
+	val = I915_READ(dpll_reg);
+	val |= (DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV);
+	I915_WRITE(dpll_reg, val);
+
+	/* Propagate soft reset to data lane reset */
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
+	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), val);
+
+	/* Disable 10bit clock to display controller */
+	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
+	val &= ~DPIO_DCLKP_EN;
+	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
+
+	/* p1 and p2 divider */
+	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
+			5 << DPIO_CHV_S1_DIV_SELECT |
+			bestp1 << DPIO_CHV_P1_SHIFT |
+			bestp2 << DPIO_CHV_P2_SHIFT |
+			1 << DPIO_CHV_K_DIV_SHIFT);
+
+	/* Feedback post-divider - m2 */
+	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
+
+	/* Feedback refclk divider - n and m1 */
+	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
+			DPIO_CHV_M1_DIV_BY_2 |
+			1 << DPIO_CHV_N_DIV_SHIFT);
+
+	/* M2 fraction division */
+	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
+
+	/* M2 fraction division enable */
+	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
+			DPIO_CHV_FRAC_DIV_EN |
+			DPIO_CHV_FEEDFWD_GAIN);
+
+	/* Loop filter */
+	refclk = i9xx_get_refclk(&crtc->base, 0);
+	loopfilter = DPIO_CHV_PROP_COEFF | DPIO_CHV_GAIN_CTRL;
+	if (refclk == 100000)
+		intcoeff = 11;
+	else if (refclk == 38400)
+		intcoeff = 10;
+	else
+		intcoeff = 9;
+	loopfilter |= (intcoeff << DPIO_CHV_INT_COEFF_SHIFT);
+	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
+
+	/* AFC Recal */
+	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
+			vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
+			DPIO_AFC_RECAL);
+
+	mutex_unlock(&dev_priv->dpio_lock);
+}
+
 static void i9xx_update_pll(struct intel_crtc *crtc,
 			    intel_clock_t *reduced_clock,
 			    int num_connectors)
@@ -5768,6 +5895,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 		i8xx_update_pll(intel_crtc,
 				has_reduced_clock ? &reduced_clock : NULL,
 				num_connectors);
+	} else if (IS_CHERRYVIEW(dev)) {
+		chv_update_pll(intel_crtc);
 	} else if (IS_VALLEYVIEW(dev)) {
 		vlv_update_pll(intel_crtc);
 	} else {
-- 
1.8.3.2

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[PATCH 22/71] drm/i915/chv: Add phy supports for Cherryview

[ville.syrjala]

From: Chon Ming Lee <chon.ming.lee@intel.com>

Added programming phy layer for CHV based on "Application note for 1273
CHV Display phy".

v2: Rebase the code and do some cleanup.
v3: Rework based on Ville review.
    -Fix the macro where the ch info need to swap, and add parens to ?
	 operator.
	-Fix wrong bit define for DPIO_PCS_SWING_CALC_0 and
	 DPIO_PCS_SWING_CALC_1 and rename for meaningful.
    -Add some comments for CHV specific DPIO registers.
    -Change the dp margin registery value to decimal to align with the
	 doc.
	-Fix the not clearing some value in vlv_dpio_read before write again.
    -Create new hdmi/dp encoder function for chv instead of share with
	valleyview.
v4: Rebase the code after rename the DPIO registers define and upstream
	change.
    Based on Ville review.
    -For unique transition scale selection, after Ville point out, look
	 like the doc might wrong for the bit 26.  Use bit 27 for ch0 and
	 ch1.
	-Break up some dpio write value into two/three steps for readability.
	-Remove unrelated change.
    -Add some shift define for some registers instead just give the hex
	value.
    -Fix a bug where write to wrong VLV_TX_DW3.
v5: Based on Ville review.
	- Move tx lane latency optimal setting from chv_dp_pre_pll_enable to
	  chv_pre_enable_dp, and chv_hdmi_pre_pll_enable to
	  chv_hdmi_pre_enable respectively.
 	- Fix typo in one margin_reg_value for DP_TRAIN_VOLTAGE_SWING_400.
	- Clear DPIO_TX_UNIQ_TRANS_SCALE_EN for DP and HDMI.
	- Mask the old deemph and swing bits for hdmi.
v6: Remove stub for pre_pll_enable for dp and hdmi.

Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[vsyrjala: Don't touch panel power sequencing on DP]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c   | 188 +++++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_hdmi.c |  84 ++++++++++++++++-
 2 files changed, 270 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6be7b35..71a4fa2 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1932,6 +1932,50 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
 	mutex_unlock(&dev_priv->dpio_lock);
 }
 
+static void chv_pre_enable_dp(struct intel_encoder *encoder)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct edp_power_seq power_seq;
+	struct intel_crtc *intel_crtc =
+		to_intel_crtc(encoder->base.crtc);
+	enum dpio_channel ch = vlv_dport_to_channel(dport);
+	int pipe = intel_crtc->pipe;
+	int data, i;
+
+	/* Program Tx lane latency optimal setting*/
+	mutex_lock(&dev_priv->dpio_lock);
+	for (i = 0; i < 4; i++) {
+		/* Set the latency optimal bit */
+		data = (i == 1) ? 0x0 : 0x6;
+		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
+				data << DPIO_FRC_LATENCY_SHFIT);
+
+		/* Set the upar bit */
+		data = (i == 1) ? 0x0 : 0x1;
+		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
+				data << DPIO_UPAR_SHIFT);
+	}
+
+	/* Data lane stagger programming */
+	/* FIXME: Fix up value only after power analysis */
+
+	mutex_unlock(&dev_priv->dpio_lock);
+
+	if (is_edp(intel_dp)) {
+		/* init power sequencer on this pipe and port */
+		intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
+		intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
+							      &power_seq);
+	}
+
+	intel_enable_dp(encoder);
+
+	vlv_wait_port_ready(dev_priv, dport);
+}
+
 /*
  * Native read with retry for link status and receiver capability reads for
  * cases where the sink may still be asleep.
@@ -2156,6 +2200,142 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
 	return 0;
 }
 
+static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
+{
+	struct drm_device *dev = intel_dp_to_dev(intel_dp);
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
+	struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
+	u32 deemph_reg_value, margin_reg_value, val, tx_dw2;
+	uint8_t train_set = intel_dp->train_set[0];
+	enum dpio_channel ch = vlv_dport_to_channel(dport);
+	int pipe = intel_crtc->pipe;
+
+	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
+	case DP_TRAIN_PRE_EMPHASIS_0:
+		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
+		case DP_TRAIN_VOLTAGE_SWING_400:
+			deemph_reg_value = 128;
+			margin_reg_value = 52;
+			break;
+		case DP_TRAIN_VOLTAGE_SWING_600:
+			deemph_reg_value = 128;
+			margin_reg_value = 77;
+			break;
+		case DP_TRAIN_VOLTAGE_SWING_800:
+			deemph_reg_value = 128;
+			margin_reg_value = 102;
+			break;
+		case DP_TRAIN_VOLTAGE_SWING_1200:
+			deemph_reg_value = 128;
+			margin_reg_value = 154;
+			/* FIXME extra to set for 1200 */
+			break;
+		default:
+			return 0;
+		}
+		break;
+	case DP_TRAIN_PRE_EMPHASIS_3_5:
+		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
+		case DP_TRAIN_VOLTAGE_SWING_400:
+			deemph_reg_value = 85;
+			margin_reg_value = 78;
+			break;
+		case DP_TRAIN_VOLTAGE_SWING_600:
+			deemph_reg_value = 85;
+			margin_reg_value = 116;
+			break;
+		case DP_TRAIN_VOLTAGE_SWING_800:
+			deemph_reg_value = 85;
+			margin_reg_value = 154;
+			break;
+		default:
+			return 0;
+		}
+		break;
+	case DP_TRAIN_PRE_EMPHASIS_6:
+		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
+		case DP_TRAIN_VOLTAGE_SWING_400:
+			deemph_reg_value = 64;
+			margin_reg_value = 104;
+			break;
+		case DP_TRAIN_VOLTAGE_SWING_600:
+			deemph_reg_value = 64;
+			margin_reg_value = 154;
+			break;
+		default:
+			return 0;
+		}
+		break;
+	case DP_TRAIN_PRE_EMPHASIS_9_5:
+		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
+		case DP_TRAIN_VOLTAGE_SWING_400:
+			deemph_reg_value = 43;
+			margin_reg_value = 154;
+			break;
+		default:
+			return 0;
+		}
+		break;
+	default:
+		return 0;
+	}
+
+	mutex_lock(&dev_priv->dpio_lock);
+
+	/* Clear calc init */
+	vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), 0);
+
+	/* Program swing deemph */
+	val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW4(ch));
+	val &= ~DPIO_SWING_DEEMPH9P5_MASK;
+	val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
+	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(ch), val);
+
+	/* Program swing margin */
+	tx_dw2 = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch));
+	tx_dw2 &= ~DPIO_SWING_MARGIN_MASK;
+	tx_dw2 |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
+	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), tx_dw2);
+
+	/* Disable unique transition scale */
+	val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
+	val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
+	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
+
+	if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
+			== DP_TRAIN_PRE_EMPHASIS_0) &&
+		((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
+			== DP_TRAIN_VOLTAGE_SWING_1200)) {
+
+		/*
+		 * The document said it needs to set bit 27 for ch0 and bit 26
+		 * for ch1. Might be a typo in the doc.
+		 * For now, for this unique transition scale selection, set bit
+		 * 27 for ch0 and ch1.
+		 */
+		val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
+		val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
+		vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
+
+		tx_dw2 |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
+		vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), tx_dw2);
+	}
+
+	/* Start swing calculation */
+	vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch),
+		(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3));
+
+	/* LRC Bypass */
+	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
+	val |= DPIO_LRC_BYPASS;
+	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
+
+	mutex_unlock(&dev_priv->dpio_lock);
+
+	return 0;
+}
+
 static void
 intel_get_adjust_train(struct intel_dp *intel_dp,
 		       const uint8_t link_status[DP_LINK_STATUS_SIZE])
@@ -2370,6 +2550,9 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
 	} else if (IS_HASWELL(dev)) {
 		signal_levels = intel_hsw_signal_levels(train_set);
 		mask = DDI_BUF_EMP_MASK;
+	} else if (IS_CHERRYVIEW(dev)) {
+		signal_levels = intel_chv_signal_levels(intel_dp);
+		mask = 0;
 	} else if (IS_VALLEYVIEW(dev)) {
 		signal_levels = intel_vlv_signal_levels(intel_dp);
 		mask = 0;
@@ -3865,7 +4048,10 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
 	intel_encoder->disable = intel_disable_dp;
 	intel_encoder->get_hw_state = intel_dp_get_hw_state;
 	intel_encoder->get_config = intel_dp_get_config;
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_CHERRYVIEW(dev)) {
+		intel_encoder->pre_enable = chv_pre_enable_dp;
+		intel_encoder->enable = vlv_enable_dp;
+	} else if (IS_VALLEYVIEW(dev)) {
 		intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
 		intel_encoder->pre_enable = vlv_pre_enable_dp;
 		intel_encoder->enable = vlv_enable_dp;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index b0413e1..bbda011 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1198,6 +1198,85 @@ static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
 	mutex_unlock(&dev_priv->dpio_lock);
 }
 
+static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
+{
+	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
+	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc =
+		to_intel_crtc(encoder->base.crtc);
+	enum dpio_channel ch = vlv_dport_to_channel(dport);
+	int pipe = intel_crtc->pipe;
+	int data, i;
+	u32 val;
+
+	/* Program Tx latency optimal setting */
+	mutex_lock(&dev_priv->dpio_lock);
+	for (i = 0; i < 4; i++) {
+		/* Set the latency optimal bit */
+		data = (i == 1) ? 0x0 : 0x6;
+		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
+				data << DPIO_FRC_LATENCY_SHFIT);
+
+		/* Set the upar bit */
+		data = (i == 1) ? 0x0 : 0x1;
+		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
+				data << DPIO_UPAR_SHIFT);
+	}
+
+	/* Data lane stagger programming */
+	/* FIXME: Fix up value only after power analysis */
+
+	/* Clear calc init */
+	vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), 0);
+
+	/* FIXME: Program the support xxx V-dB */
+	/* Use 800mV-0dB */
+	val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW4(ch));
+	val &= ~DPIO_SWING_DEEMPH9P5_MASK;
+	val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
+	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch));
+	val &= ~DPIO_SWING_MARGIN_MASK;
+	val |= 102 << DPIO_SWING_MARGIN_SHIFT;
+	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), val);
+
+	/* Disable unique transition scale */
+	val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
+	val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
+	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
+
+	/* Additional steps for 1200mV-0dB */
+#if 0
+	val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
+	if (ch)
+		val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1;
+	else
+		val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0;
+	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
+
+	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch),
+			vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) |
+				(0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT));
+#endif
+	/* Start swing calculation */
+	vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch),
+			DPIO_PCS_SWING_CALC_TX0_TX2 |
+			DPIO_PCS_SWING_CALC_TX1_TX3);
+
+	/* LRC Bypass */
+	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
+	val |= DPIO_LRC_BYPASS;
+	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
+
+	mutex_unlock(&dev_priv->dpio_lock);
+
+	intel_enable_hdmi(encoder);
+
+	vlv_wait_port_ready(dev_priv, dport);
+}
+
 static void intel_hdmi_destroy(struct drm_connector *connector)
 {
 	drm_connector_cleanup(connector);
@@ -1332,7 +1411,10 @@ void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
 	intel_encoder->disable = intel_disable_hdmi;
 	intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
 	intel_encoder->get_config = intel_hdmi_get_config;
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_CHERRYVIEW(dev)) {
+		intel_encoder->pre_enable = chv_hdmi_pre_enable;
+		intel_encoder->enable = vlv_enable_hdmi;
+	} else if (IS_VALLEYVIEW(dev)) {
 		intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
 		intel_encoder->pre_enable = vlv_hdmi_pre_enable;
 		intel_encoder->enable = vlv_enable_hdmi;
-- 
1.8.3.2

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[PATCH 23/71] drm/i915/chv: Pipe select change for DP and HDMI

[ville.syrjala]

From: Chon Ming Lee <chon.ming.lee@intel.com>

With additional of pipe C, current 1 bit registers for pipe select
for HDMI and DP are no longer able to gather for 3 pipes. As a result,
new bits location in the same registers are added.

For HDMI, VLV uses bit 30, CHV uses bit 24-25.

For DP, VLV uses bit 30, CHV uses bit 16-17.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      | 6 ++++++
 drivers/gpu/drm/i915/intel_display.c | 6 ++++++
 drivers/gpu/drm/i915/intel_dp.c      | 8 ++++++--
 drivers/gpu/drm/i915/intel_hdmi.c    | 2 ++
 4 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 75f31f5..91c8fac 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2478,6 +2478,10 @@ enum punit_power_well {
 #define   SDVO_PIPE_SEL_CPT(pipe)		((pipe) << 29)
 #define   SDVO_PIPE_SEL_MASK_CPT		(3 << 29)
 
+/* CHV SDVO/HDMI bits: */
+#define   SDVO_PIPE_SEL_CHV(pipe)		((pipe) << 24)
+#define   SDVO_PIPE_SEL_MASK_CHV		(3 << 24)
+
 
 /* DVO port control */
 #define DVOA			0x61120
@@ -3235,6 +3239,8 @@ enum punit_power_well {
 #define   DP_PORT_EN			(1 << 31)
 #define   DP_PIPEB_SELECT		(1 << 30)
 #define   DP_PIPE_MASK			(1 << 30)
+#define   DP_PIPE_SELECT_CHV(pipe)	((pipe) << 16)
+#define   DP_PIPE_MASK_CHV		(3 << 16)
 
 /* Link training mode - select a suitable mode for each stage */
 #define   DP_LINK_TRAIN_PAT_1		(0 << 28)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 36d6e212..f849c65 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1337,6 +1337,9 @@ static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
 		u32	trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
 		if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
 			return false;
+	} else if (IS_CHERRYVIEW(dev_priv->dev)) {
+		if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
+			return false;
 	} else {
 		if ((val & DP_PIPE_MASK) != (pipe << 30))
 			return false;
@@ -1353,6 +1356,9 @@ static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
 	if (HAS_PCH_CPT(dev_priv->dev)) {
 		if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
 			return false;
+	} else if (IS_CHERRYVIEW(dev_priv->dev)) {
+		if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
+			return false;
 	} else {
 		if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
 			return false;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 71a4fa2..21ac845 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -964,8 +964,12 @@ static void intel_dp_mode_set(struct intel_encoder *encoder)
 		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 			intel_dp->DP |= DP_ENHANCED_FRAMING;
 
-		if (crtc->pipe == 1)
-			intel_dp->DP |= DP_PIPEB_SELECT;
+		if (!IS_CHERRYVIEW(dev)) {
+			if (crtc->pipe == 1)
+				intel_dp->DP |= DP_PIPEB_SELECT;
+		} else {
+			intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
+		}
 	} else {
 		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 	}
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index bbda011..9f868f4 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -652,6 +652,8 @@ static void intel_hdmi_mode_set(struct intel_encoder *encoder)
 
 	if (HAS_PCH_CPT(dev))
 		hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
+	else if (IS_CHERRYVIEW(dev))
+		hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
 	else
 		hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
 
-- 
1.8.3.2

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[PATCH 24/71] drm/i915/chv: Add DPLL state readout support

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add chv_crtc_clock_get() to read out the DPLL settings.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 34 +++++++++++++++++++++++++++++++++-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f849c65..266d8fe 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6062,6 +6062,36 @@ static void i9xx_get_plane_config(struct intel_crtc *crtc,
 
 }
 
+static void chv_crtc_clock_get(struct intel_crtc *crtc,
+			       struct intel_crtc_config *pipe_config)
+{
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int pipe = pipe_config->cpu_transcoder;
+	enum dpio_channel port = vlv_pipe_to_channel(pipe);
+	intel_clock_t clock;
+	u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
+	int refclk = 100000;
+
+	mutex_lock(&dev_priv->dpio_lock);
+	cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
+	pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
+	pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
+	pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
+	mutex_unlock(&dev_priv->dpio_lock);
+
+	clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
+	clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
+	clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
+	clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_SHIFT) & 0x7;
+	clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_SHIFT) & 0x1f;
+
+	chv_clock(refclk, &clock);
+
+	/* clock.dot is the fast clock */
+	pipe_config->port_clock = clock.dot / 5;
+}
+
 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 				 struct intel_crtc_config *pipe_config)
 {
@@ -6131,7 +6161,9 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 						     DPLL_PORTB_READY_MASK);
 	}
 
-	if (IS_VALLEYVIEW(dev))
+	if (IS_CHERRYVIEW(dev))
+		chv_crtc_clock_get(crtc, pipe_config);
+	else if (IS_VALLEYVIEW(dev))
 		vlv_crtc_clock_get(crtc, pipe_config);
 	else
 		i9xx_crtc_clock_get(crtc, pipe_config);
-- 
1.8.3.2

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[PATCH 25/71] drm/i915/chv: CHV doesn't have CRT output

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

No CRT output on CHV, so don't call intel_crt_init().

v2: Don't disable CRT on HAS.

FIXME: Split out the is_simulator check again, we need it for now to keep HAS
going.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 266d8fe..9b65a04 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10989,7 +10989,7 @@ static void intel_setup_outputs(struct drm_device *dev)
 
 	intel_lvds_init(dev);
 
-	if (!IS_ULT(dev))
+	if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev))
 		intel_crt_init(dev);
 
 	if (HAS_DDI(dev)) {
-- 
1.8.3.2

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[PATCH 26/71] drm/i915: Enable PM Interrupts for CHV/BDW Platform.

[ville.syrjala]

From: Deepak S <deepak.s@intel.com>

v2: Remove vfuncs and add if else block to differentiate platform
(Daniel)

Signed-off-by: Deepak S <deepak.s@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 49 +++++++++++++++++++++++++++++++++++++++--
 1 file changed, 47 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1581b3d..6cf97c4 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -37,6 +37,9 @@
 #include "i915_trace.h"
 #include "intel_drv.h"
 
+
+static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
+
 static const u32 hpd_ibx[] = {
 	[HPD_CRT] = SDE_CRT_HOTPLUG,
 	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
@@ -154,6 +157,32 @@ void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 }
 
 /**
+ * gen8_update_pm_irq - update GEN8_GT_IMR
+ * @dev_priv: driver private
+ * @interrupt_mask: mask of interrupt bits to update
+ * @enabled_irq_mask: mask of interrupt bits to enable
+ * */
+
+static void gen8_update_pm_irq(struct drm_i915_private *dev_priv,
+					uint32_t interrupt_mask,
+					uint32_t enabled_irq_mask)
+{
+	uint32_t new_val;
+
+	assert_spin_locked(&dev_priv->irq_lock);
+
+	new_val = dev_priv->pm_irq_mask;
+	new_val &= ~interrupt_mask;
+	new_val |= (~enabled_irq_mask & interrupt_mask);
+
+	if (new_val != dev_priv->pm_irq_mask) {
+		dev_priv->pm_irq_mask = new_val;
+		I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask);
+		POSTING_READ(GEN8_GT_IMR(2));
+	}
+}
+
+/**
   * snb_update_pm_irq - update GEN6_PMIMR
   * @dev_priv: driver private
   * @interrupt_mask: mask of interrupt bits to update
@@ -188,12 +217,18 @@ static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 
 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 {
-	snb_update_pm_irq(dev_priv, mask, mask);
+	if (IS_GEN8(dev_priv->dev))
+		gen8_update_pm_irq(dev_priv, mask, mask);
+	else
+		snb_update_pm_irq(dev_priv, mask, mask);
 }
 
 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 {
-	snb_update_pm_irq(dev_priv, mask, 0);
+	if (IS_GEN8(dev_priv->dev))
+		gen8_update_pm_irq(dev_priv, mask, 0);
+	else
+		snb_update_pm_irq(dev_priv, mask, 0);
 }
 
 static bool ivb_can_enable_err_int(struct drm_device *dev)
@@ -1341,6 +1376,9 @@ static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
 	u32 rcs, bcs, vcs;
 	uint32_t tmp = 0;
 	irqreturn_t ret = IRQ_NONE;
+	u32 pm_iir;
+
+	pm_iir = I915_READ(GEN8_GT_IIR(2));
 
 	if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
 		tmp = I915_READ(GEN8_GT_IIR(0));
@@ -1381,6 +1419,12 @@ static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
 			DRM_ERROR("The master control interrupt lied (GT3)!\n");
 	}
 
+
+	if (pm_iir)
+		gen6_rps_irq_handler(dev_priv, pm_iir);
+
+	I915_WRITE(GEN8_GT_IIR(2), pm_iir);
+
 	return ret;
 }
 
@@ -1796,6 +1840,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 		ret = IRQ_HANDLED;
 	}
 
+
 	I915_WRITE(VLV_IIR, iir);
 
 	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
-- 
1.8.3.2

[PATCH 27/71] drm/i915/chv: Enable Render Standby (RC6) for Cheeryview

[ville.syrjala]

From: Deepak S <deepak.s@intel.com>

v2: Configure PCBR if BIOS fails allocate pcbr (deepak)

Signed-off-by: Deepak S <deepak.s@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 101 ++++++++++++++++++++++++++++++++++++++--
 1 file changed, 98 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0889af7..909cc0a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3184,6 +3184,18 @@ static void gen6_disable_rps(struct drm_device *dev)
 	gen6_disable_rps_interrupts(dev);
 }
 
+static void cherryview_disable_rps(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	I915_WRITE(GEN6_RC_CONTROL, 0);
+
+	if (dev_priv->vlv_pctx) {
+		drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
+		dev_priv->vlv_pctx = NULL;
+	}
+}
+
 static void valleyview_disable_rps(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3551,6 +3563,29 @@ int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
 	return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
 }
 
+static void cherryview_setup_pctx(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	unsigned long pctx_paddr;
+	struct i915_gtt *gtt = &dev_priv->gtt;
+	u32 pcbr;
+	int pctx_size = 32*1024;
+
+	pcbr = I915_READ(VLV_PCBR);
+	if (pcbr >> 12 == 0) {
+		/*
+		 * From the Gunit register HAS:
+		 * The Gfx driver is expected to program this register and ensure
+		 * proper allocation within Gfx stolen memory.  For example, this
+		 * register should be programmed such than the PCBR range does not
+		 * overlap with other relevant ranges.
+		 */
+		pctx_paddr = (dev_priv->mm.stolen_base + gtt->stolen_size - pctx_size);
+		I915_WRITE(VLV_PCBR, pctx_paddr);
+	}
+}
+
+
 static void valleyview_setup_pctx(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3595,6 +3630,61 @@ out:
 	dev_priv->vlv_pctx = pctx;
 }
 
+static void cherryview_enable_rps(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_ring_buffer *ring;
+	u32 gtfifodbg, rc6_mode = 0, pcbr;
+	int i;
+
+	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+	if ((gtfifodbg = I915_READ(GTFIFODBG))) {
+		DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
+				 gtfifodbg);
+		I915_WRITE(GTFIFODBG, gtfifodbg);
+	}
+
+	cherryview_setup_pctx(dev);
+
+	/* 1a & 1b: Get forcewake during program sequence. Although the driver
+	 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
+	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+
+	/* 2a: Program RC6 thresholds.*/
+	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
+	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
+	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
+
+	for_each_ring(ring, dev_priv, i)
+		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
+
+	I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
+
+	/* allows RC6 residency counter to work */
+	I915_WRITE(VLV_COUNTER_CONTROL,
+		   _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
+				      VLV_MEDIA_RC6_COUNT_EN |
+				      VLV_RENDER_RC6_COUNT_EN));
+
+	/* Todo: If BIOS has not configured PCBR
+	 *       then allocate in BIOS Reserved */
+
+	/* For now we assume BIOS is allocating and populating the PCBR  */
+	pcbr = I915_READ(VLV_PCBR);
+
+	DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
+
+	/* 3: Enable RC6 */
+	if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE & (pcbr >> 12))
+		rc6_mode = GEN6_RC_CTL_EI_MODE(1) | VLV_RC_CTL_CTX_RST_PARALLEL;
+
+	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
+
+	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
+}
+
+
 static void valleyview_enable_rps(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4437,7 +4527,9 @@ void intel_disable_gt_powersave(struct drm_device *dev)
 		cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
 		cancel_work_sync(&dev_priv->rps.work);
 		mutex_lock(&dev_priv->rps.hw_lock);
-		if (IS_VALLEYVIEW(dev))
+		if (IS_CHERRYVIEW(dev))
+			cherryview_disable_rps(dev);
+		else if (IS_VALLEYVIEW(dev))
 			valleyview_disable_rps(dev);
 		else
 			gen6_disable_rps(dev);
@@ -4455,7 +4547,9 @@ static void intel_gen6_powersave_work(struct work_struct *work)
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_CHERRYVIEW(dev)) {
+		cherryview_enable_rps(dev);
+	} else if (IS_VALLEYVIEW(dev)) {
 		valleyview_enable_rps(dev);
 	} else if (IS_BROADWELL(dev)) {
 		gen8_enable_rps(dev);
@@ -4476,7 +4570,7 @@ void intel_enable_gt_powersave(struct drm_device *dev)
 		ironlake_enable_drps(dev);
 		ironlake_enable_rc6(dev);
 		intel_init_emon(dev);
-	} else if (IS_GEN6(dev) || IS_GEN7(dev)) {
+	} else if (INTEL_INFO(dev)->gen >= 6) {
 		if (IS_VALLEYVIEW(dev))
 			valleyview_setup_pctx(dev);
 		/*
@@ -5051,6 +5145,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 		dev_priv->mem_freq = 1333;
 		break;
 	}
+
 	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
 
 	dev_priv->vlv_cdclk_freq = valleyview_cur_cdclk(dev_priv);
-- 
1.8.3.2

[PATCH 28/71] drm/i915/chv: Added CHV specific register read and write

[ville.syrjala]

From: Deepak S <deepak.s@intel.com>

Support to individually control Media/Render well based on the register access.
Add CHV specific write function to habdle difference between registers
that are sadowed vs those that need forcewake even for writes.

v2: Drop write FIFO for CHV and add comman well forcewake (Ville)

Signed-off-by: Deepak S <deepak.s@intel.com>
[vsyrjala: Move the register range macros into intel_uncore.c]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 139 +++++++++++++++++++++++++++++++++---
 1 file changed, 131 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 823d699..8e3c686 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -495,6 +495,31 @@ void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
 	((reg) >= 0x22000 && (reg) < 0x24000) ||\
 	((reg) >= 0x30000 && (reg) < 0x40000))
 
+#define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
+	(((reg) >= 0x2000 && (reg) < 0x4000) ||\
+	((reg) >= 0x5000 && (reg) < 0x8000) ||\
+	((reg) >= 0x8300 && (reg) < 0x8500) ||\
+	((reg) >= 0xB000 && (reg) < 0xC000) ||\
+	((reg) >= 0xE000 && (reg) < 0xE800))
+
+#define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)\
+	(((reg) >= 0x8800 && (reg) < 0x8900) ||\
+	((reg) >= 0xD000 && (reg) < 0xD800) ||\
+	((reg) >= 0x12000 && (reg) < 0x14000) ||\
+	((reg) >= 0x1A000 && (reg) < 0x1C000) ||\
+	((reg) >= 0x1E800 && (reg) < 0x1EA00) ||\
+	((reg) >= 0x30000 && (reg) < 0x40000))
+
+#define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)\
+	(((reg) >= 0x4000 && (reg) < 0x5000) ||\
+	((reg) >= 0x8000 && (reg) < 0x8300) ||\
+	((reg) >= 0x8500 && (reg) < 0x8600) ||\
+	((reg) >= 0x9000 && (reg) < 0xB000) ||\
+	((reg) >= 0xC000 && (reg) < 0xc800) ||\
+	((reg) >= 0xF000 && (reg) < 0x10000) ||\
+	((reg) >= 0x14000 && (reg) < 0x14400) ||\
+	((reg) >= 0x22000 && (reg) < 0x24000))
+
 static void
 ilk_dummy_write(struct drm_i915_private *dev_priv)
 {
@@ -587,7 +612,48 @@ vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 	REG_READ_FOOTER; \
 }
 
+#define __chv_read(x) \
+static u##x \
+chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
+	unsigned fwengine = 0; \
+	REG_READ_HEADER(x); \
+	if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
+		fwengine = FORCEWAKE_RENDER; \
+	} \
+	else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
+		fwengine = FORCEWAKE_MEDIA; \
+	} \
+	else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
+		fwengine = FORCEWAKE_ALL; \
+	} \
+	if (FORCEWAKE_RENDER & fwengine) { \
+		if (dev_priv->uncore.fw_rendercount++ == 0) \
+			(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
+								fwengine); \
+	} \
+	if (FORCEWAKE_MEDIA & fwengine) { \
+		if (dev_priv->uncore.fw_mediacount++ == 0) \
+			(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
+								fwengine); \
+	} \
+	val = __raw_i915_read##x(dev_priv, reg); \
+	if (FORCEWAKE_RENDER & fwengine) { \
+		if (dev_priv->uncore.fw_rendercount++ == 0) \
+			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
+								fwengine); \
+	} \
+	if (FORCEWAKE_MEDIA & fwengine) { \
+		if (dev_priv->uncore.fw_mediacount++ == 0) \
+			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
+								fwengine); \
+	} \
+	REG_READ_FOOTER; \
+}
 
+__chv_read(8)
+__chv_read(16)
+__chv_read(32)
+__chv_read(64)
 __vlv_read(8)
 __vlv_read(16)
 __vlv_read(32)
@@ -605,6 +671,7 @@ __gen4_read(16)
 __gen4_read(32)
 __gen4_read(64)
 
+#undef __chv_read
 #undef __vlv_read
 #undef __gen6_read
 #undef __gen5_read
@@ -709,6 +776,49 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
 	REG_WRITE_FOOTER; \
 }
 
+#define __chv_write(x) \
+static void \
+chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
+	unsigned fwengine = 0; \
+	bool __needs_put = !is_gen8_shadowed(dev_priv, reg); \
+	REG_WRITE_HEADER; \
+	if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
+		fwengine = FORCEWAKE_RENDER; \
+	} \
+	else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
+		fwengine = FORCEWAKE_MEDIA; \
+	} \
+	else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
+		fwengine = FORCEWAKE_ALL; \
+	} \
+	if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \
+			if (dev_priv->uncore.fw_rendercount++ == 0) \
+				(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
+									fwengine); \
+	} \
+	if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \
+		if (dev_priv->uncore.fw_mediacount++ == 0) \
+			(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
+								fwengine); \
+	} \
+	__raw_i915_write##x(dev_priv, reg, val); \
+	if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \
+			if (dev_priv->uncore.fw_rendercount++ == 0) \
+				(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
+									fwengine); \
+	} \
+	if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \
+		if (dev_priv->uncore.fw_mediacount++ == 0) \
+			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
+								fwengine); \
+	} \
+	REG_WRITE_FOOTER; \
+}
+
+__chv_write(8)
+__chv_write(16)
+__chv_write(32)
+__chv_write(64)
 __gen8_write(8)
 __gen8_write(16)
 __gen8_write(32)
@@ -730,6 +840,7 @@ __gen4_write(16)
 __gen4_write(32)
 __gen4_write(64)
 
+#undef __chv_write
 #undef __gen8_write
 #undef __hsw_write
 #undef __gen6_write
@@ -793,14 +904,26 @@ void intel_uncore_init(struct drm_device *dev)
 
 	switch (INTEL_INFO(dev)->gen) {
 	default:
-		dev_priv->uncore.funcs.mmio_writeb  = gen8_write8;
-		dev_priv->uncore.funcs.mmio_writew  = gen8_write16;
-		dev_priv->uncore.funcs.mmio_writel  = gen8_write32;
-		dev_priv->uncore.funcs.mmio_writeq  = gen8_write64;
-		dev_priv->uncore.funcs.mmio_readb  = gen6_read8;
-		dev_priv->uncore.funcs.mmio_readw  = gen6_read16;
-		dev_priv->uncore.funcs.mmio_readl  = gen6_read32;
-		dev_priv->uncore.funcs.mmio_readq  = gen6_read64;
+		if (IS_CHERRYVIEW(dev)) {
+			dev_priv->uncore.funcs.mmio_writeb  = chv_write8;
+			dev_priv->uncore.funcs.mmio_writew  = chv_write16;
+			dev_priv->uncore.funcs.mmio_writel  = chv_write32;
+			dev_priv->uncore.funcs.mmio_writeq  = chv_write64;
+			dev_priv->uncore.funcs.mmio_readb  = chv_read8;
+			dev_priv->uncore.funcs.mmio_readw  = chv_read16;
+			dev_priv->uncore.funcs.mmio_readl  = chv_read32;
+			dev_priv->uncore.funcs.mmio_readq  = chv_read64;
+
+		} else {
+			dev_priv->uncore.funcs.mmio_writeb  = gen8_write8;
+			dev_priv->uncore.funcs.mmio_writew  = gen8_write16;
+			dev_priv->uncore.funcs.mmio_writel  = gen8_write32;
+			dev_priv->uncore.funcs.mmio_writeq  = gen8_write64;
+			dev_priv->uncore.funcs.mmio_readb  = gen6_read8;
+			dev_priv->uncore.funcs.mmio_readw  = gen6_read16;
+			dev_priv->uncore.funcs.mmio_readl  = gen6_read32;
+			dev_priv->uncore.funcs.mmio_readq  = gen6_read64;
+		}
 		break;
 	case 7:
 	case 6:
-- 
1.8.3.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 29/71] drm/i915/chv: Enable RPS (Turbo) for Cheeryview

[ville.syrjala]

From: Deepak S <deepak.s@intel.com>

v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)

v3: Mass rename of the dev_priv->rps variables in upstream.

Signed-off-by: Deepak S <deepak.s@intel.com> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.h       |  1 +
 drivers/gpu/drm/i915/i915_reg.h       | 10 +++++
 drivers/gpu/drm/i915/intel_pm.c       | 82 ++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_sideband.c | 15 +++++++
 4 files changed, 107 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 07a162c..a67f18f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2521,6 +2521,7 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
+u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 91c8fac..e67b4a6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -468,6 +468,7 @@
 #define VLV_IOSF_DATA				(VLV_DISPLAY_BASE + 0x2104)
 #define VLV_IOSF_ADDR				(VLV_DISPLAY_BASE + 0x2108)
 
+#define   CHV_IOSF_PORT_NC			0x04
 /* See configdb bunit SB addr map */
 #define BUNIT_REG_BISOC				0x11
 
@@ -513,6 +514,14 @@ enum punit_power_well {
 #define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */
 #define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
 
+#define CHV_IOSF_NC_FB_GFX_FREQ_FUSE		0xdb
+#define CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT		16
+#define CHV_FB_GFX_MAX_FREQ_FUSE_MASK		0xff
+
+#define CHV_IOSF_NC_FB_GFX_RPE_FUSE		0xdf
+#define CHV_FB_RPE_FREQ_SHIFT			8
+#define CHV_FB_RPE_FREQ_MASK			0xff
+
 #define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c
 #define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3
 #define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8
@@ -809,6 +818,7 @@ enum punit_power_well {
 #define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
 #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
 
+
 /* control register for cpu gtt access */
 #define TILECTL				0x101000
 #define   TILECTL_SWZCTL			(1 << 0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 909cc0a..4217576 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3533,6 +3533,38 @@ void gen6_update_ring_freq(struct drm_device *dev)
 	}
 }
 
+int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
+{
+	u32 val, rp0;
+
+	val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
+
+	rp0 = (val >> CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT) &
+					CHV_FB_GFX_MAX_FREQ_FUSE_MASK;
+
+	return rp0;
+}
+
+static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
+{
+	u32 val, rpe;
+
+	val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_RPE_FUSE);
+	rpe = (val >> CHV_FB_RPE_FREQ_SHIFT) & CHV_FB_RPE_FREQ_MASK;
+
+	return rpe;
+}
+
+int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
+{
+	u32 val, rpn;
+
+	val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
+	rpn = (val >> CHV_FB_RPE_FREQ_SHIFT) & CHV_FB_RPE_FREQ_MASK;
+
+	return rpn;
+}
+
 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
 {
 	u32 val, rp0;
@@ -3634,7 +3666,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_ring_buffer *ring;
-	u32 gtfifodbg, rc6_mode = 0, pcbr;
+	u32 gtfifodbg, val, rc6_mode = 0, pcbr;
 	int i;
 
 	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
@@ -3681,6 +3713,54 @@ static void cherryview_enable_rps(struct drm_device *dev)
 
 	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
 
+	/* 4 Program defaults and thresholds for RPS*/
+	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
+	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
+	I915_WRITE(GEN6_RP_UP_EI, 66000);
+	I915_WRITE(GEN6_RP_DOWN_EI, 350000);
+
+	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
+
+	/* 5: Enable RPS */
+	I915_WRITE(GEN6_RP_CONTROL,
+		   GEN6_RP_MEDIA_HW_NORMAL_MODE |
+		   GEN6_RP_MEDIA_IS_GFX |
+		   GEN6_RP_ENABLE |
+		   GEN6_RP_UP_BUSY_AVG |
+		   GEN6_RP_DOWN_IDLE_AVG);
+
+	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+
+	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
+	DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
+
+	dev_priv->rps.cur_freq = (val >> 8) & 0xff;
+	DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
+			 dev_priv->rps.cur_freq);
+
+	dev_priv->rps.max_freq_softlimit = cherryview_rps_max_freq(dev_priv);
+	dev_priv->rps.max_freq = dev_priv->rps.max_freq_softlimit;
+	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
+			 dev_priv->rps.max_freq_softlimit);
+
+	dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
+	DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+			 dev_priv->rps.efficient_freq);
+
+	dev_priv->rps.min_freq_softlimit = cherryview_rps_min_freq(dev_priv);
+	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
+			 dev_priv->rps.min_freq_softlimit);
+
+	DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+			 dev_priv->rps.efficient_freq);
+
+	valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
+
 	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index c1e56f5..771e904 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -106,6 +106,21 @@ void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
 			PUNIT_OPCODE_REG_WRITE, reg, &val);
 }
 
+u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
+{
+	u32 val = 0;
+
+	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+	mutex_lock(&dev_priv->dpio_lock);
+	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), CHV_IOSF_PORT_NC,
+			PUNIT_OPCODE_REG_READ, addr, &val);
+	mutex_unlock(&dev_priv->dpio_lock);
+
+	return val;
+}
+
+
 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
 {
 	u32 val = 0;
-- 
1.8.3.2

[PATCH 30/71] drm/i915/chv: Enable PM interrupts when we in CHV turbo initialize sequence.

[ville.syrjala]

From: Deepak S <deepak.s@intel.com>

v2: Mass rename of the dev_priv->rps variables in upstream.

Signed-off-by: Deepak S <deepak.s@intel.com> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_pm.c | 43 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4217576..392731a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3155,6 +3155,28 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
 	trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
 }
 
+static void gen8_disable_rps_interrupts(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
+	I915_WRITE(GEN8_GT_IER(2),
+			I915_READ(GEN8_GT_IER(2)) & ~GEN6_PM_RPS_EVENTS);
+
+	spin_lock_irq(&dev_priv->irq_lock);
+	dev_priv->rps.pm_iir = 0;
+	spin_unlock_irq(&dev_priv->irq_lock);
+
+	I915_WRITE(GEN8_GT_IIR(2), I915_READ(GEN8_GT_IIR(2)));
+
+	/* Disable Turbo in control register */
+	I915_WRITE(GEN6_RP_CONTROL, 0);
+
+	/* Set the Freq to RPe */
+	valleyview_set_rps(dev, dev_priv->rps.efficient_freq);
+
+}
+
 static void gen6_disable_rps_interrupts(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3190,6 +3212,8 @@ static void cherryview_disable_rps(struct drm_device *dev)
 
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 
+	gen8_disable_rps_interrupts(dev);
+
 	if (dev_priv->vlv_pctx) {
 		drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
 		dev_priv->vlv_pctx = NULL;
@@ -3238,6 +3262,23 @@ int intel_enable_rc6(const struct drm_device *dev)
 	return INTEL_RC6_ENABLE;
 }
 
+static void gen8_enable_rps_interrupts(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	/* Clear out any stale interrupts first */
+	spin_lock_irq(&dev_priv->irq_lock);
+	WARN_ON(dev_priv->rps.pm_iir);
+	I915_WRITE(GEN8_GT_IIR(2), I915_READ(GEN8_GT_IIR(2)));
+	dev_priv->pm_irq_mask &= ~GEN6_PM_RPS_EVENTS;
+	I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask);
+	spin_unlock_irq(&dev_priv->irq_lock);
+
+	I915_WRITE(GEN8_GT_IER(2), GEN6_PM_RPS_EVENTS);
+	/* only unmask PM interrupts we need. Mask all others. */
+	I915_WRITE(GEN6_PMINTRMSK, ~GEN6_PM_RPS_EVENTS);
+}
+
 static void gen6_enable_rps_interrupts(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3761,6 +3802,8 @@ static void cherryview_enable_rps(struct drm_device *dev)
 
 	valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
 
+	gen8_enable_rps_interrupts(dev);
+
 	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
 }
 
-- 
1.8.3.2

[PATCH 31/71] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating

[ville.syrjala]

From: Deepak S <deepak.s@intel.com>

v2: Added chv support for opcode to freq conversion and viceversa (Deepak)

Signed-off-by: Deepak S <deepak.s@intel.com>
[vsyrjala: Fix merge fubmle where the code ended up in
g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 392731a..2aa65ce 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5343,6 +5343,23 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 static void cherryview_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 val;
+
+	mutex_lock(&dev_priv->rps.hw_lock);
+	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+	mutex_unlock(&dev_priv->rps.hw_lock);
+
+	/* ToDo: Update the mem freq once the DDR rate is finalized [CHV] */
+	switch ((val >> 6) & 3) {
+	case 0:
+		dev_priv->mem_freq = 1600;
+		break;
+	case 1:
+		dev_priv->mem_freq = 2000;
+		break;
+	}
+
+	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
 
 	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
 
@@ -6359,6 +6376,12 @@ int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
 	case 1333:
 		div = 16;
 		break;
+	case 1600:
+		div = 16;
+		break;
+	case 2000:
+		div = 16;
+		break;
 	default:
 		return -1;
 	}
@@ -6381,6 +6404,12 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
 	case 1333:
 		mul = 16;
 		break;
+	case 1600:
+		mul = 16;
+		break;
+	case 2000:
+		mul = 16;
+		break;
 	default:
 		return -1;
 	}
-- 
1.8.3.2

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[PATCH 32/71] drm/i915/bdw: Add BDW PM Interrupts support and BDW rps disable

[ville.syrjala]

From: Deepak S <deepak.s@intel.com>

Signed-off-by: Deepak S <deepak.s@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2aa65ce..fb533a3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3206,6 +3206,18 @@ static void gen6_disable_rps(struct drm_device *dev)
 	gen6_disable_rps_interrupts(dev);
 }
 
+static void gen8_disable_rps(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	I915_WRITE(GEN6_RC_CONTROL, 0);
+	I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
+
+	gen8_disable_rps_interrupts(dev);
+}
+
+
+
 static void cherryview_disable_rps(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3369,7 +3381,7 @@ static void gen8_enable_rps(struct drm_device *dev)
 
 	gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
 
-	gen6_enable_rps_interrupts(dev);
+	gen8_enable_rps_interrupts(dev);
 
 	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
 }
@@ -4652,6 +4664,8 @@ void intel_disable_gt_powersave(struct drm_device *dev)
 		mutex_lock(&dev_priv->rps.hw_lock);
 		if (IS_CHERRYVIEW(dev))
 			cherryview_disable_rps(dev);
+		else if (IS_BROADWELL(dev))
+			gen8_disable_rps(dev);
 		else if (IS_VALLEYVIEW(dev))
 			valleyview_disable_rps(dev);
 		else
-- 
1.8.3.2

[PATCH 33/71] drm/i915/chv: Fix for verifying PCBR address field.

[ville.syrjala]

From: Deepak S <deepak.s@intel.com>

This was fumbled in PCBR condition check during CHV RC6 Enable flag set

Issue introduced in

commit cb26b06c20094d69bcba191738960d053ac2c645
Author: Deepak S <deepak.s@intel.com>
Date:   Mon Dec 16 12:16:53 2013 +0530
Subject: drm/i915/chv: Enable Render Standby (RC6) for Cheeryview

v2: Commit message change (Jani)

v3: Mention the subject and author of the patch which introduced
the bug (Daniel)

v4: Use VLV_PCBR_ADDR_SHIFT instead of MASK (Jani)

v5: Commit message change. Add subject of the patch which introduced
the bug (Ville)

Signed-off-by: Deepak S <deepak.s@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 5 +++--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e67b4a6..ac5047b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5294,6 +5294,7 @@ enum punit_power_well {
 #define GEN6_GT_GFX_RC6				0x138108
 #define GEN6_GT_GFX_RC6p			0x13810C
 #define GEN6_GT_GFX_RC6pp			0x138110
+#define VLV_PCBR_ADDR_SHIFT			12
 
 #define GEN6_PCODE_MAILBOX			0x138124
 #define   GEN6_PCODE_READY			(1<<31)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fb533a3..acaa1cf 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3657,7 +3657,7 @@ static void cherryview_setup_pctx(struct drm_device *dev)
 	int pctx_size = 32*1024;
 
 	pcbr = I915_READ(VLV_PCBR);
-	if (pcbr >> 12 == 0) {
+	if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
 		/*
 		 * From the Gunit register HAS:
 		 * The Gfx driver is expected to program this register and ensure
@@ -3761,7 +3761,8 @@ static void cherryview_enable_rps(struct drm_device *dev)
 	DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
 
 	/* 3: Enable RC6 */
-	if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE & (pcbr >> 12))
+	if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
+						(pcbr >> VLV_PCBR_ADDR_SHIFT))
 		rc6_mode = GEN6_RC_CTL_EI_MODE(1) | VLV_RC_CTL_CTX_RST_PARALLEL;
 
 	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
-- 
1.8.3.2

[PATCH 34/71] drm/i915/chv: Implement stolen memory size detection

[ville.syrjala]

From: Damien Lespiau <damien.lespiau@intel.com>

CHV uses the same bits as SNB/VLV to code the Graphics Mode Select field
(GFX stolen memory size) with the addition of finer granularity modes:
4MB increments from 0x11 (8MB) to 0x1d.

Values strictly above 0x1d are either reserved or not supported.

v2: 4MB increments, not 8MB. 32MB has been omitted from the list of new
    values (Ville Syrjälä)

v3: Also correctly interpret GGMS (GTT Graphics Memory Size) (Ville
    Syrjälä)

v4: Don't assign a value that needs 20bits or more to a u16 (Rafael
    Barbalho)

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>
Tested-by: Rafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 arch/x86/kernel/early-quirks.c      | 23 +++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_gem_gtt.c | 38 +++++++++++++++++++++++++++++++++++--
 2 files changed, 58 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 5758f5b..46ce15c 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -323,6 +323,27 @@ static inline size_t gen8_stolen_size(int num, int slot, int func)
 	return gmch_ctrl << 25; /* 32 MB units */
 }
 
+static size_t __init chv_stolen_size(int num, int slot, int func)
+{
+	u16 gmch_ctrl;
+
+	gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
+	gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
+	gmch_ctrl &= SNB_GMCH_GMS_MASK;
+
+	/*
+	 * 0x0  to 0x10: 32MB increments starting at 0MB
+	 * 0x11 to 0x16: 4MB increments starting at 8MB
+	 * 0x17 to 0x1d: 4MB increments start at 36MB
+	 */
+	if (gmch_ctrl < 0x11)
+		return gmch_ctrl << 25;
+	else if (gmch_ctrl < 0x17)
+		return (gmch_ctrl - 0x11 + 2) << 22;
+	else
+		return (gmch_ctrl - 0x17 + 9) << 22;
+}
+
 typedef size_t (*stolen_size_fn)(int num, int slot, int func);
 
 static struct pci_device_id intel_stolen_ids[] __initdata = {
@@ -348,7 +369,7 @@ static struct pci_device_id intel_stolen_ids[] __initdata = {
 	INTEL_HSW_M_IDS(gen6_stolen_size),
 	INTEL_BDW_M_IDS(gen8_stolen_size),
 	INTEL_BDW_D_IDS(gen8_stolen_size),
-	INTEL_CHV_PCI_IDS(gen8_stolen_size)
+	INTEL_CHV_PCI_IDS(chv_stolen_size),
 };
 
 static void __init intel_graphics_stolen(int num, int slot, int func)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ba51901..97f52fc 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1757,6 +1757,17 @@ static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
 	return bdw_gmch_ctl << 20;
 }
 
+static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
+{
+	gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
+	gmch_ctrl &= SNB_GMCH_GGMS_MASK;
+
+	if (gmch_ctrl)
+		return 1 << (20 + gmch_ctrl);
+
+	return 0;
+}
+
 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
 {
 	snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
@@ -1771,6 +1782,24 @@ static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
 	return bdw_gmch_ctl << 25; /* 32 MB units */
 }
 
+static size_t chv_get_stolen_size(u16 gmch_ctrl)
+{
+	gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
+	gmch_ctrl &= SNB_GMCH_GMS_MASK;
+
+	/*
+	 * 0x0  to 0x10: 32MB increments starting at 0MB
+	 * 0x11 to 0x16: 4MB increments starting at 8MB
+	 * 0x17 to 0x1d: 4MB increments start at 36MB
+	 */
+	if (gmch_ctrl < 0x11)
+		return gmch_ctrl << 25;
+	else if (gmch_ctrl < 0x17)
+		return (gmch_ctrl - 0x11 + 2) << 22;
+	else
+		return (gmch_ctrl - 0x17 + 9) << 22;
+}
+
 static int ggtt_probe_common(struct drm_device *dev,
 			     size_t gtt_size)
 {
@@ -1867,9 +1896,14 @@ static int gen8_gmch_probe(struct drm_device *dev,
 
 	pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 
-	*stolen = gen8_get_stolen_size(snb_gmch_ctl);
+	if (IS_CHERRYVIEW(dev)) {
+		*stolen = chv_get_stolen_size(snb_gmch_ctl);
+		gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
+	} else {
+		*stolen = gen8_get_stolen_size(snb_gmch_ctl);
+		gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
+	}
 
-	gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
 	*gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
 
 	if (IS_CHERRYVIEW(dev))
-- 
1.8.3.2

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[PATCH 35/71] drm/i915/chv: Implement WaDisablePartialInstShootdown:chv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index acaa1cf..9c4beb4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5379,6 +5379,10 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
 
 	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
+
+	/* WaDisablePartialInstShootdown:chv */
+	I915_WRITE(GEN8_ROW_CHICKEN,
+		   _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
 }
 
 static void g4x_init_clock_gating(struct drm_device *dev)
-- 
1.8.3.2

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[PATCH 36/71] drm/i915/chv: Implement WaDisableThreadStallDopClockGating:chv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9c4beb4..1be39c8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5383,6 +5383,10 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
 	/* WaDisablePartialInstShootdown:chv */
 	I915_WRITE(GEN8_ROW_CHICKEN,
 		   _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
+
+	/* WaDisableThreadStallDopClockGating:chv */
+	I915_WRITE(GEN8_ROW_CHICKEN,
+		   _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
 }
 
 static void g4x_init_clock_gating(struct drm_device *dev)
-- 
1.8.3.2

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[PATCH 37/71] drm/i915/chv: Implement WaVSRefCountFullforceMissDisable:chv and WaDSRefCountFullforceMissDisable:chv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1be39c8..0a33be2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5387,6 +5387,12 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
 	/* WaDisableThreadStallDopClockGating:chv */
 	I915_WRITE(GEN8_ROW_CHICKEN,
 		   _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
+
+	/* WaVSRefCountFullforceMissDisable:chv */
+	/* WaDSRefCountFullforceMissDisable:chv */
+	I915_WRITE(GEN7_FF_THREAD_MODE,
+		   I915_READ(GEN7_FF_THREAD_MODE) &
+		   ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
 }
 
 static void g4x_init_clock_gating(struct drm_device *dev)
-- 
1.8.3.2

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[PATCH 38/71] drm/i915/chv: Implement WaDisableSemaphoreAndSyncFlipWait:chv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

BDW has the same requirement but the w/a database doens't list
this w/a for BDW. Seems to be another one of those "stick a bunch
of known workarounds into this bag and write something on the label"
type of things.

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0a33be2..53db89b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5393,6 +5393,10 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(GEN7_FF_THREAD_MODE,
 		   I915_READ(GEN7_FF_THREAD_MODE) &
 		   ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
+
+	/* WaDisableSemaphoreAndSyncFlipWait:chv */
+	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
+		   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
 }
 
 static void g4x_init_clock_gating(struct drm_device *dev)
-- 
1.8.3.2

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[PATCH 39/71] drm/i915/chv: Implement WaDisableCSUnitClockGating:chv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

This workaround is listed for CHV, but not for BDW. However BSpec notes
that on BDW CSunit clock gating is always disabled irrespective of the
relevant bit in the GEN6_UGCTL1 registers. For CHV however, such text
is not present in BSpec, so it seems safer to just set the bit.

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 53db89b..de9510e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5397,6 +5397,10 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
 	/* WaDisableSemaphoreAndSyncFlipWait:chv */
 	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
 		   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
+
+	/* WaDisableCSUnitClockGating:chv */
+	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
+		   GEN6_CSUNIT_CLOCK_GATE_DISABLE);
 }
 
 static void g4x_init_clock_gating(struct drm_device *dev)
-- 
1.8.3.2

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[PATCH 40/71] drm/i915/chv: Implement WaDisableSDEUnitClockGating:chv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index de9510e..468fe37 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5401,6 +5401,10 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
 	/* WaDisableCSUnitClockGating:chv */
 	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
 		   GEN6_CSUNIT_CLOCK_GATE_DISABLE);
+
+	/* WaDisableSDEUnitClockGating:chv */
+	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
+		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 }
 
 static void g4x_init_clock_gating(struct drm_device *dev)
-- 
1.8.3.2

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[PATCH 41/71] drm/i915/chv: Add some workaround notes

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We implement the following workarounds:
* WaDisableAsyncFlipPerfMode:chv
* WaDisableSemaphoreAndSyncFlipWait:chv (at least partially)
* WaProgramMiArbOnOffAroundMiSetContext:chv

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c         | 1 +
 drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 84a7171..a9c33ec 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4376,6 +4376,7 @@ static int i915_gem_init_rings(struct drm_device *dev)
 		struct intel_ring_buffer *ring;
 		int i;
 
+		/* WaDisableSemaphoreAndSyncFlipWait:chv */
 		for_each_ring(ring, dev_priv, i)
 			I915_WRITE(RING_RC_PSMI_CONTROL(ring),
 				   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 28a2b15..142df90 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -606,7 +606,7 @@ mi_set_context(struct intel_ring_buffer *ring,
 	if (ret)
 		return ret;
 
-	/* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw */
+	/* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
 	if (INTEL_INFO(ring->dev)->gen >= 7)
 		intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
 	else
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 913b8ab..24022c5 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -581,7 +581,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
 	 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 	 * programmed to '1' on all products.
 	 *
-	 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw
+	 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
 	 */
 	if (INTEL_INFO(dev)->gen >= 6)
 		I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
-- 
1.8.3.2

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[PATCH 42/71] drm/i915/chv: Implement WaDisableSamplerPowerBypass for CHV

[ville.syrjala]

From: Rafael Barbalho <rafael.barbalho@intel.com>

Cherryview also needs this WA.

Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
[vsyrjala: Looks like it's for pre-prodution hw only]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 468fe37..60f876c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5405,6 +5405,10 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
 	/* WaDisableSDEUnitClockGating:chv */
 	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+
+	/* WaDisableSamplerPowerBypass:chv (pre-production hw) */
+	I915_WRITE(HALF_SLICE_CHICKEN3,
+		   _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
 }
 
 static void g4x_init_clock_gating(struct drm_device *dev)
-- 
1.8.3.2

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[PATCH 43/71] drm/i915/chv: Add a bunch of pre production workarounds

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The following workarounds should be needed for pre-production hardware
only:
* WaDisablePwrmtrEvent:chv
* WaSetMaskForGfxBusyness:chv
* WaDisableGunitClockGating:chv
* WaDisableFfDopClockGating:chv
* WaDisableDopClockGating:chv

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  3 +++
 drivers/gpu/drm/i915/intel_pm.c | 20 +++++++++++++++++++-
 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ac5047b..7587752 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1024,6 +1024,7 @@ enum punit_power_well {
 #define IMR		0x020a8
 #define ISR		0x020ac
 #define VLV_GUNIT_CLOCK_GATE	(VLV_DISPLAY_BASE + 0x2060)
+#define   GINT_DIS		(1<<22)
 #define   GCFG_DIS		(1<<8)
 #define VLV_IIR_RW	(VLV_DISPLAY_BASE + 0x2084)
 #define VLV_IER		(VLV_DISPLAY_BASE + 0x20a0)
@@ -1154,6 +1155,7 @@ enum punit_power_well {
 
 #define GEN6_RC_SLEEP_PSMI_CONTROL	0x2050
 #define   GEN8_RC_SEMA_IDLE_MSG_DISABLE	(1 << 12)
+#define   GEN8_FF_DOP_CLOCK_GATE_DISABLE	(1<<10)
 
 #define GEN6_BSD_SLEEP_PSMI_CONTROL	0x12050
 #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
@@ -5186,6 +5188,7 @@ enum punit_power_well {
 #define  HSW_EDRAM_PRESENT			0x120010
 
 #define GEN6_UCGCTL1				0x9400
+# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE		(1 << 16)
 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE		(1 << 5)
 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 60f876c..587d32f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3775,10 +3775,14 @@ static void cherryview_enable_rps(struct drm_device *dev)
 
 	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
 
+	/* WaDisablePwrmtrEvent:chv (pre-production hw) */
+	I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
+	I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
+
 	/* 5: Enable RPS */
 	I915_WRITE(GEN6_RP_CONTROL,
 		   GEN6_RP_MEDIA_HW_NORMAL_MODE |
-		   GEN6_RP_MEDIA_IS_GFX |
+		   GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
 		   GEN6_RP_ENABLE |
 		   GEN6_RP_UP_BUSY_AVG |
 		   GEN6_RP_DOWN_IDLE_AVG);
@@ -5409,6 +5413,20 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
 	/* WaDisableSamplerPowerBypass:chv (pre-production hw) */
 	I915_WRITE(HALF_SLICE_CHICKEN3,
 		   _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
+
+	/* WaDisableGunitClockGating:chv (pre-production hw) */
+	I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
+		   GINT_DIS);
+
+	/* WaDisableFfDopClockGating:chv (pre-production hw) */
+	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
+		   _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
+
+	/* WaDisableDopClockGating:chv (pre-production hw) */
+	I915_WRITE(GEN7_ROW_CHICKEN2,
+		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
+	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
+		   GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
 }
 
 static void g4x_init_clock_gating(struct drm_device *dev)
-- 
1.8.3.2

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[PATCH 44/71] drm/i915/chv: Fix for decrementing fw count in chv read/write.

[ville.syrjala]

From: Deepak S <deepak.s@intel.com>

This was fumbled in chv specific forcewake count during mmio reg read/write.

Issue introduced in

commit 95cf8b69f647322048929baffa8c7865aa6df2ad
Author: Deepak S <deepak.s@intel.com>
Date:   Mon Dec 16 12:16:54 2013 +0530
Subject: drm/i915/chv: Added CHV specific register read and write

Signed-off-by: Deepak S <deepak.s@intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 8e3c686..ccad770 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -638,12 +638,12 @@ chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 	} \
 	val = __raw_i915_read##x(dev_priv, reg); \
 	if (FORCEWAKE_RENDER & fwengine) { \
-		if (dev_priv->uncore.fw_rendercount++ == 0) \
+		if (--dev_priv->uncore.fw_rendercount == 0) \
 			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
 								fwengine); \
 	} \
 	if (FORCEWAKE_MEDIA & fwengine) { \
-		if (dev_priv->uncore.fw_mediacount++ == 0) \
+		if (--dev_priv->uncore.fw_mediacount == 0) \
 			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
 								fwengine); \
 	} \
@@ -803,12 +803,12 @@ chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace)
 	} \
 	__raw_i915_write##x(dev_priv, reg, val); \
 	if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \
-			if (dev_priv->uncore.fw_rendercount++ == 0) \
+			if (--dev_priv->uncore.fw_rendercount == 0) \
 				(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
 									fwengine); \
 	} \
 	if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \
-		if (dev_priv->uncore.fw_mediacount++ == 0) \
+		if (--dev_priv->uncore.fw_mediacount == 0) \
 			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
 								fwengine); \
 	} \
-- 
1.8.3.2

[PATCH 45/71] drm/i915/chv: Streamline CHV forcewake stuff

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Streamline the CHV forcewake functions just like was done for VLV.

This will also fix a bug in accessing the common well registers,
where we'd end up trying to wake up the wells too many times
since we'd call force_wake_get/put twice per register access, with
FORCEFAKE_ALL both times.

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 88 ++++++++++++++-----------------------
 1 file changed, 32 insertions(+), 56 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index ccad770..59293b3 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -618,35 +618,22 @@ chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 	unsigned fwengine = 0; \
 	REG_READ_HEADER(x); \
 	if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
-		fwengine = FORCEWAKE_RENDER; \
-	} \
-	else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
-		fwengine = FORCEWAKE_MEDIA; \
-	} \
-	else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
-		fwengine = FORCEWAKE_ALL; \
-	} \
-	if (FORCEWAKE_RENDER & fwengine) { \
-		if (dev_priv->uncore.fw_rendercount++ == 0) \
-			(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
-								fwengine); \
-	} \
-	if (FORCEWAKE_MEDIA & fwengine) { \
-		if (dev_priv->uncore.fw_mediacount++ == 0) \
-			(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
-								fwengine); \
+		if (dev_priv->uncore.fw_rendercount == 0) \
+			fwengine = FORCEWAKE_RENDER; \
+	} else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
+		if (dev_priv->uncore.fw_mediacount == 0) \
+			fwengine = FORCEWAKE_MEDIA; \
+	} else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
+		if (dev_priv->uncore.fw_rendercount == 0) \
+			fwengine |= FORCEWAKE_RENDER; \
+		if (dev_priv->uncore.fw_mediacount == 0) \
+			fwengine |= FORCEWAKE_MEDIA; \
 	} \
+	if (fwengine) \
+		dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
 	val = __raw_i915_read##x(dev_priv, reg); \
-	if (FORCEWAKE_RENDER & fwengine) { \
-		if (--dev_priv->uncore.fw_rendercount == 0) \
-			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
-								fwengine); \
-	} \
-	if (FORCEWAKE_MEDIA & fwengine) { \
-		if (--dev_priv->uncore.fw_mediacount == 0) \
-			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
-								fwengine); \
-	} \
+	if (fwengine) \
+		dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
 	REG_READ_FOOTER; \
 }
 
@@ -780,38 +767,27 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
 static void \
 chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 	unsigned fwengine = 0; \
-	bool __needs_put = !is_gen8_shadowed(dev_priv, reg); \
+	bool shadowed = is_gen8_shadowed(dev_priv, reg); \
 	REG_WRITE_HEADER; \
-	if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
-		fwengine = FORCEWAKE_RENDER; \
-	} \
-	else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
-		fwengine = FORCEWAKE_MEDIA; \
-	} \
-	else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
-		fwengine = FORCEWAKE_ALL; \
-	} \
-	if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \
-			if (dev_priv->uncore.fw_rendercount++ == 0) \
-				(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
-									fwengine); \
-	} \
-	if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \
-		if (dev_priv->uncore.fw_mediacount++ == 0) \
-			(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
-								fwengine); \
+	if (!shadowed) { \
+		if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
+			if (dev_priv->uncore.fw_rendercount == 0) \
+				fwengine = FORCEWAKE_RENDER; \
+		} else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
+			if (dev_priv->uncore.fw_mediacount == 0) \
+				fwengine = FORCEWAKE_MEDIA; \
+		} else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
+			if (dev_priv->uncore.fw_rendercount == 0) \
+				fwengine |= FORCEWAKE_RENDER; \
+			if (dev_priv->uncore.fw_mediacount == 0) \
+				fwengine |= FORCEWAKE_MEDIA; \
+		} \
 	} \
+	if (fwengine) \
+		dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
 	__raw_i915_write##x(dev_priv, reg, val); \
-	if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \
-			if (--dev_priv->uncore.fw_rendercount == 0) \
-				(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
-									fwengine); \
-	} \
-	if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \
-		if (--dev_priv->uncore.fw_mediacount == 0) \
-			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
-								fwengine); \
-	} \
+	if (fwengine) \
+		dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
 	REG_WRITE_FOOTER; \
 }
 
-- 
1.8.3.2

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[PATCH 46/71] drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Skip __gen6_gt_wait_for_thread_c0() on CHV.

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 59293b3..e4d0b97 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -229,8 +229,8 @@ static void __vlv_force_wake_get(struct drm_i915_private *dev_priv,
 	}
 
 	/* WaRsForcewakeWaitTC0:vlv */
-	__gen6_gt_wait_for_thread_c0(dev_priv);
-
+	if (!IS_CHERRYVIEW(dev_priv->dev))
+		__gen6_gt_wait_for_thread_c0(dev_priv);
 }
 
 static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
-- 
1.8.3.2

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[PATCH 47/71] drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

CHV uses the gen8 shadow register mechanism so we shouldn't be
checking the GT FIFO status.

This effectively removes the posting read, so add an explicit
posting read using FORCEWAKE_ACK_VLV (which is what use in
vlv_forcewake_reset()).

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index e4d0b97..b321c4e 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -248,9 +248,10 @@ static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
 		__raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
 				_MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 
-	/* The below doubles as a POSTING_READ */
-	gen6_gt_check_fifodbg(dev_priv);
-
+	/* something from same cacheline, but !FORCEWAKE_VLV */
+	__raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
+	if (!IS_CHERRYVIEW(dev_priv->dev))
+		gen6_gt_check_fifodbg(dev_priv);
 }
 
 static void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
-- 
1.8.3.2

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[PATCH 48/71] drm/i915/chv: Add plane C support

[ville.syrjala]

From: Rafael Barbalho <rafael.barbalho@intel.com>

The i9xx_update_plane function was rejecting plane C when it is now a
valid plane.

Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
[vsyrjala: Use PLANE_C instead of the number 2]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9b65a04..51d9079 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2351,6 +2351,7 @@ static int i9xx_update_primary_plane(struct drm_crtc *crtc,
 	switch (plane) {
 	case PLANE_A:
 	case PLANE_B:
+	case PLANE_C:
 		break;
 	default:
 		DRM_ERROR("Can't update plane %c\n", plane_name(plane));
-- 
1.8.3.2

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[PATCH 49/71] drm/i915/chv: Add CHV display support

[ville.syrjala]

From: Rafael Barbalho <rafael.barbalho@intel.com>

Add support for the third pipe in cherrview

Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
[vsyrjala: slightly massaged the patch]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c |  7 +++++++
 drivers/gpu/drm/i915/i915_reg.h | 11 ++++++++---
 2 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 2415fa2..c5e9fa8 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,12 @@ static struct drm_driver driver;
 	.dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \
 	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
 
+#define GEN_CHV_PIPEOFFSETS \
+       .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, CHV_PIPE_C_OFFSET }, \
+       .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, CHV_TRANSCODER_C_OFFSET, }, \
+       .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET, CHV_DPLL_C_OFFSET }, \
+       .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET, CHV_DPLL_C_MD_OFFSET }, \
+       .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, CHV_PALETTE_C_OFFSET }
 
 static const struct intel_device_info intel_i830_info = {
 	.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
@@ -286,6 +292,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 	.is_valleyview = 1,
 	.display_mmio_offset = VLV_DISPLAY_BASE,
+	GEN_CHV_PIPEOFFSETS,
 };
 
 /*
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7587752..3831d84 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1430,6 +1430,7 @@ enum punit_power_well {
  */
 #define DPLL_A_OFFSET 0x6014
 #define DPLL_B_OFFSET 0x6018
+#define CHV_DPLL_C_OFFSET 0x6030
 #define DPLL(pipe) (dev_priv->info.dpll_offsets[pipe] + \
 		    dev_priv->info.display_mmio_offset)
 
@@ -1521,6 +1522,7 @@ enum punit_power_well {
 
 #define DPLL_A_MD_OFFSET 0x601c /* 965+ only */
 #define DPLL_B_MD_OFFSET 0x6020 /* 965+ only */
+#define CHV_DPLL_C_MD_OFFSET 0x603c
 #define DPLL_MD(pipe) (dev_priv->info.dpll_md_offsets[pipe] + \
 		       dev_priv->info.display_mmio_offset)
 
@@ -1717,6 +1719,7 @@ enum punit_power_well {
  */
 #define PALETTE_A_OFFSET 0xa000
 #define PALETTE_B_OFFSET 0xa800
+#define CHV_PALETTE_C_OFFSET 0xc000
 #define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \
 		       dev_priv->info.display_mmio_offset)
 
@@ -2206,6 +2209,7 @@ enum punit_power_well {
 #define TRANSCODER_A_OFFSET 0x60000
 #define TRANSCODER_B_OFFSET 0x61000
 #define TRANSCODER_C_OFFSET 0x62000
+#define CHV_TRANSCODER_C_OFFSET 0x63000
 #define TRANSCODER_EDP_OFFSET 0x6f000
 
 #define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
@@ -3533,9 +3537,10 @@ enum punit_power_well {
 #define PIPESTAT_INT_ENABLE_MASK		0x7fff0000
 #define PIPESTAT_INT_STATUS_MASK		0x0000ffff
 
-#define PIPE_A_OFFSET	0x70000
-#define PIPE_B_OFFSET	0x71000
-#define PIPE_C_OFFSET	0x72000
+#define PIPE_A_OFFSET		0x70000
+#define PIPE_B_OFFSET		0x71000
+#define PIPE_C_OFFSET		0x72000
+#define CHV_PIPE_C_OFFSET	0x74000
 /*
  * There's actually no pipe EDP. Some pipe registers have
  * simply shifted from the pipe to the transcoder, while
-- 
1.8.3.2

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[PATCH 50/71] drm/i915/chv: Clarify VLV/CHV PIPESTAT bits a bit more

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6cf97c4..9c18a47 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -585,11 +585,17 @@ static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
 	u32 enable_mask = status_mask << 16;
 
 	/*
-	 * On pipe A we don't support the PSR interrupt yet, on pipe B the
-	 * same bit MBZ.
+	 * On pipe A we don't support the PSR interrupt yet,
+	 * on pipe B and C the same bit MBZ.
 	 */
 	if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
 		return 0;
+	/*
+	 * On pipe B and C we don't support the PSR interrupt yet, on pipe
+	 * A the same bit is for perf counters which we don't use either.
+	 */
+	if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
+		return 0;
 
 	enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 			 SPRITE0_FLIP_DONE_INT_EN_VLV |
-- 
1.8.3.2

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[PATCH 51/71] drm/i915/chv: Use valleyview_pipestat_irq_handler() for CHV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 91 ++++++++---------------------------------
 1 file changed, 17 insertions(+), 74 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9c18a47..9702fde 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1660,6 +1660,9 @@ static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
 		case PIPE_B:
 			iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
 			break;
+		case PIPE_C:
+			iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
+			break;
 		}
 		if (iir & iir_bit)
 			mask |= dev_priv->pipestat_irq_mask[pipe];
@@ -1771,87 +1774,32 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	u32 master_ctl, iir;
 	irqreturn_t ret = IRQ_NONE;
-	unsigned int pipes = 0;
-
-	master_ctl = I915_READ(GEN8_MASTER_IRQ);
-
-	I915_WRITE(GEN8_MASTER_IRQ, 0);
-
-	ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
 
+	master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~DE_MASTER_IRQ_CONTROL;
 	iir = I915_READ(VLV_IIR);
 
-	if (iir & (I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT))
-		pipes |= 1 << 0;
-	if (iir & (I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT))
-		pipes |= 1 << 1;
-	if (iir & (I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT | I915_DISPLAY_PIPE_C_EVENT_INTERRUPT))
-		pipes |= 1 << 2;
-
-	if (pipes) {
-		u32 pipe_stats[I915_MAX_PIPES] = {};
-		unsigned long irqflags;
-		int pipe;
-
-		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-		for_each_pipe(pipe) {
-			unsigned int reg;
-
-			if (!(pipes & (1 << pipe)))
-				continue;
-
-			reg = PIPESTAT(pipe);
-			pipe_stats[pipe] = I915_READ(reg);
-
-			/*
-			 * Clear the PIPE*STAT regs before the IIR
-			 */
-			if (pipe_stats[pipe] & 0x8000ffff) {
-				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
-					DRM_DEBUG_DRIVER("pipe %c underrun\n",
-							 pipe_name(pipe));
-				I915_WRITE(reg, pipe_stats[pipe]);
-			}
-		}
-		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
-
-		for_each_pipe(pipe) {
-			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
-				drm_handle_vblank(dev, pipe);
+	if (master_ctl == 0 && iir == 0)
+		return IRQ_NONE;
 
-			if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
-				intel_prepare_page_flip(dev, pipe);
-				intel_finish_page_flip(dev, pipe);
-			}
-		}
+	I915_WRITE(GEN8_MASTER_IRQ, 0);
 
-		if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
-			gmbus_irq_handler(dev);
+	gen8_gt_irq_handler(dev, dev_priv, master_ctl);
 
-		ret = IRQ_HANDLED;
-	}
+	valleyview_pipestat_irq_handler(dev, iir);
 
 	/* Consume port.  Then clear IIR or we'll miss events */
 	if (iir & I915_DISPLAY_PORT_INTERRUPT) {
-		u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
-
-		I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
-
-		DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
-				 hotplug_status);
-		if (hotplug_status & HOTPLUG_INT_STATUS_I915)
-			queue_work(dev_priv->wq,
-				   &dev_priv->hotplug_work);
-
+		i9xx_hpd_irq_handler(dev, iir);
 		ret = IRQ_HANDLED;
 	}
 
-
 	I915_WRITE(VLV_IIR, iir);
 
 	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
 	POSTING_READ(GEN8_MASTER_IRQ);
 
+	ret = IRQ_HANDLED;
+
 	return ret;
 }
 
@@ -3526,12 +3474,10 @@ static int cherryview_irq_postinstall(struct drm_device *dev)
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
 		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
-		I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
 		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
-		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT |
-		I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
-		I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT;
-	u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
+		I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
+	u32 pipestat_enable = PLANE_FLIP_DONE_INT_STATUS_VLV |
+		PIPE_CRC_DONE_INTERRUPT_STATUS;
 	unsigned long irqflags;
 	int pipe;
 
@@ -3539,16 +3485,13 @@ static int cherryview_irq_postinstall(struct drm_device *dev)
 	 * Leave vblank interrupts masked initially.  enable/disable will
 	 * toggle them based on usage.
 	 */
-	dev_priv->irq_mask = ~enable_mask |
-		I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
-		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT |
-		I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT;
+	dev_priv->irq_mask = ~enable_mask;
 
 	for_each_pipe(pipe)
 		I915_WRITE(PIPESTAT(pipe), 0xffff);
 
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-	i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
+	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
 	for_each_pipe(pipe)
 		i915_enable_pipestat(dev_priv, pipe, pipestat_enable);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
-- 
1.8.3.2

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[PATCH 52/71] drm/i915/chv: Make CHV irq handler loop until all interrupts are consumed

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 29 ++++++++++++++---------------
 1 file changed, 14 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9702fde..fc9b7e6 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1775,30 +1775,29 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 	u32 master_ctl, iir;
 	irqreturn_t ret = IRQ_NONE;
 
-	master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~DE_MASTER_IRQ_CONTROL;
-	iir = I915_READ(VLV_IIR);
+	for (;;) {
+		master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
+		iir = I915_READ(VLV_IIR);
 
-	if (master_ctl == 0 && iir == 0)
-		return IRQ_NONE;
+		if (master_ctl == 0 && iir == 0)
+			break;
 
-	I915_WRITE(GEN8_MASTER_IRQ, 0);
+		I915_WRITE(GEN8_MASTER_IRQ, 0);
 
-	gen8_gt_irq_handler(dev, dev_priv, master_ctl);
+		gen8_gt_irq_handler(dev, dev_priv, master_ctl);
 
-	valleyview_pipestat_irq_handler(dev, iir);
+		valleyview_pipestat_irq_handler(dev, iir);
 
-	/* Consume port.  Then clear IIR or we'll miss events */
-	if (iir & I915_DISPLAY_PORT_INTERRUPT) {
+		/* Consume port.  Then clear IIR or we'll miss events */
 		i9xx_hpd_irq_handler(dev, iir);
-		ret = IRQ_HANDLED;
-	}
 
-	I915_WRITE(VLV_IIR, iir);
+		I915_WRITE(VLV_IIR, iir);
 
-	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
-	POSTING_READ(GEN8_MASTER_IRQ);
+		I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
+		POSTING_READ(GEN8_MASTER_IRQ);
 
-	ret = IRQ_HANDLED;
+		ret = IRQ_HANDLED;
+	}
 
 	return ret;
 }
-- 
1.8.3.2

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[PATCH 53/71] drm/i915/chv: Configure crtc_mask correctly for CHV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On CHV pipe C can driver only port D, and pipes A and B can drivbe only
ports B and C. Configure the crtc_mask appropriately to reflect that.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c   | 8 +++++++-
 drivers/gpu/drm/i915/intel_hdmi.c | 8 +++++++-
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 21ac845..6ae4d28 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4070,7 +4070,13 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
 	intel_dig_port->dp.output_reg = output_reg;
 
 	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
-	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
+	if (IS_CHERRYVIEW(dev)) {
+		if (port == PORT_D)
+			intel_encoder->crtc_mask = 1 << 2;
+		else
+			intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
+	} else
+		intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 	intel_encoder->cloneable = 0;
 	intel_encoder->hot_plug = intel_dp_hot_plug;
 
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 9f868f4..349374b 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1426,7 +1426,13 @@ void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
 	}
 
 	intel_encoder->type = INTEL_OUTPUT_HDMI;
-	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
+	if (IS_CHERRYVIEW(dev)) {
+		if (port == PORT_D)
+			intel_encoder->crtc_mask = 1 << 2;
+		else
+			intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
+	} else
+		intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 	intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
 	/*
 	 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
-- 
1.8.3.2

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[PATCH 54/71] drm/i915/chv: Fix gmbus for port D

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On CHV the GMBUS port for port D is different from other gmch platforms
which have port D. Fix it up.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   | 1 +
 drivers/gpu/drm/i915/intel_hdmi.c | 5 ++++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3831d84..92de47b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1389,6 +1389,7 @@ enum punit_power_well {
 #define   GMBUS_PORT_SSC	1
 #define   GMBUS_PORT_VGADDC	2
 #define   GMBUS_PORT_PANEL	3
+#define   GMBUS_PORT_DPD_CHV	3 /* HDMID_CHV */
 #define   GMBUS_PORT_DPC	4 /* HDMIC */
 #define   GMBUS_PORT_DPB	5 /* SDVO, HDMIB */
 #define   GMBUS_PORT_DPD	6 /* HDMID */
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 349374b..ba57edd 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1339,7 +1339,10 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 		intel_encoder->hpd_pin = HPD_PORT_C;
 		break;
 	case PORT_D:
-		intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
+		if (IS_CHERRYVIEW(dev))
+			intel_hdmi->ddc_bus = GMBUS_PORT_DPD_CHV;
+		else
+			intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
 		intel_encoder->hpd_pin = HPD_PORT_D;
 		break;
 	case PORT_A:
-- 
1.8.3.2

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[PATCH 55/71] drm/i915/chv: Add cursor pipe offsets

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Unsurprisingly the cursor C regiters are also at a weird offset on CHV.
Add more pipe offsets to handle them.

This also gets rid of most of the differences between the i9xx vs. ivb
cursor code. We can unify the remaining code as well, but I'll leave
that for another patch.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  9 ++------
 drivers/gpu/drm/i915/i915_drv.c      | 34 +++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h      |  1 +
 drivers/gpu/drm/i915/i915_reg.h      | 30 +++++++++++++++-----------
 drivers/gpu/drm/i915/intel_display.c | 42 ++++++++++++++----------------------
 5 files changed, 71 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 1efb885..ee8b94b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2339,10 +2339,8 @@ static bool cursor_active(struct drm_device *dev, int pipe)
 
 	if (IS_845G(dev) || IS_I865G(dev))
 		state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
-	else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
-		state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
 	else
-		state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
+		state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
 
 	return state;
 }
@@ -2352,10 +2350,7 @@ static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 pos;
 
-	if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
-		pos = I915_READ(CURPOS_IVB(pipe));
-	else
-		pos = I915_READ(CURPOS(pipe));
+	pos = I915_READ(CURPOS(pipe));
 
 	*x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
 	if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c5e9fa8..66cff97 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -56,11 +56,18 @@ static struct drm_driver driver;
        .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET, CHV_DPLL_C_MD_OFFSET }, \
        .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, CHV_PALETTE_C_OFFSET }
 
+#define CURSOR_OFFSETS \
+	.cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
+
+#define IVB_CURSOR_OFFSETS \
+	.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
+
 static const struct intel_device_info intel_i830_info = {
 	.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 	.has_overlay = 1, .overlay_needs_physical = 1,
 	.ring_mask = RENDER_RING,
 	GEN_DEFAULT_PIPEOFFSETS,
+	CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_845g_info = {
@@ -68,6 +75,7 @@ static const struct intel_device_info intel_845g_info = {
 	.has_overlay = 1, .overlay_needs_physical = 1,
 	.ring_mask = RENDER_RING,
 	GEN_DEFAULT_PIPEOFFSETS,
+	CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_i85x_info = {
@@ -77,6 +85,7 @@ static const struct intel_device_info intel_i85x_info = {
 	.has_fbc = 1,
 	.ring_mask = RENDER_RING,
 	GEN_DEFAULT_PIPEOFFSETS,
+	CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_i865g_info = {
@@ -84,6 +93,7 @@ static const struct intel_device_info intel_i865g_info = {
 	.has_overlay = 1, .overlay_needs_physical = 1,
 	.ring_mask = RENDER_RING,
 	GEN_DEFAULT_PIPEOFFSETS,
+	CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_i915g_info = {
@@ -91,6 +101,7 @@ static const struct intel_device_info intel_i915g_info = {
 	.has_overlay = 1, .overlay_needs_physical = 1,
 	.ring_mask = RENDER_RING,
 	GEN_DEFAULT_PIPEOFFSETS,
+	CURSOR_OFFSETS,
 };
 static const struct intel_device_info intel_i915gm_info = {
 	.gen = 3, .is_mobile = 1, .num_pipes = 2,
@@ -100,12 +111,14 @@ static const struct intel_device_info intel_i915gm_info = {
 	.has_fbc = 1,
 	.ring_mask = RENDER_RING,
 	GEN_DEFAULT_PIPEOFFSETS,
+	CURSOR_OFFSETS,
 };
 static const struct intel_device_info intel_i945g_info = {
 	.gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 	.has_overlay = 1, .overlay_needs_physical = 1,
 	.ring_mask = RENDER_RING,
 	GEN_DEFAULT_PIPEOFFSETS,
+	CURSOR_OFFSETS,
 };
 static const struct intel_device_info intel_i945gm_info = {
 	.gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
@@ -115,6 +128,7 @@ static const struct intel_device_info intel_i945gm_info = {
 	.has_fbc = 1,
 	.ring_mask = RENDER_RING,
 	GEN_DEFAULT_PIPEOFFSETS,
+	CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_i965g_info = {
@@ -123,6 +137,7 @@ static const struct intel_device_info intel_i965g_info = {
 	.has_overlay = 1,
 	.ring_mask = RENDER_RING,
 	GEN_DEFAULT_PIPEOFFSETS,
+	CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_i965gm_info = {
@@ -132,6 +147,7 @@ static const struct intel_device_info intel_i965gm_info = {
 	.supports_tv = 1,
 	.ring_mask = RENDER_RING,
 	GEN_DEFAULT_PIPEOFFSETS,
+	CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_g33_info = {
@@ -140,6 +156,7 @@ static const struct intel_device_info intel_g33_info = {
 	.has_overlay = 1,
 	.ring_mask = RENDER_RING,
 	GEN_DEFAULT_PIPEOFFSETS,
+	CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_g45_info = {
@@ -147,6 +164,7 @@ static const struct intel_device_info intel_g45_info = {
 	.has_pipe_cxsr = 1, .has_hotplug = 1,
 	.ring_mask = RENDER_RING | BSD_RING,
 	GEN_DEFAULT_PIPEOFFSETS,
+	CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_gm45_info = {
@@ -156,6 +174,7 @@ static const struct intel_device_info intel_gm45_info = {
 	.supports_tv = 1,
 	.ring_mask = RENDER_RING | BSD_RING,
 	GEN_DEFAULT_PIPEOFFSETS,
+	CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_pineview_info = {
@@ -163,6 +182,7 @@ static const struct intel_device_info intel_pineview_info = {
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.has_overlay = 1,
 	GEN_DEFAULT_PIPEOFFSETS,
+	CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_ironlake_d_info = {
@@ -170,6 +190,7 @@ static const struct intel_device_info intel_ironlake_d_info = {
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.ring_mask = RENDER_RING | BSD_RING,
 	GEN_DEFAULT_PIPEOFFSETS,
+	CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_ironlake_m_info = {
@@ -178,6 +199,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
 	.has_fbc = 1,
 	.ring_mask = RENDER_RING | BSD_RING,
 	GEN_DEFAULT_PIPEOFFSETS,
+	CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_sandybridge_d_info = {
@@ -187,6 +209,7 @@ static const struct intel_device_info intel_sandybridge_d_info = {
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 	.has_llc = 1,
 	GEN_DEFAULT_PIPEOFFSETS,
+	CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_sandybridge_m_info = {
@@ -196,6 +219,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 	.has_llc = 1,
 	GEN_DEFAULT_PIPEOFFSETS,
+	CURSOR_OFFSETS,
 };
 
 #define GEN7_FEATURES  \
@@ -209,6 +233,7 @@ static const struct intel_device_info intel_ivybridge_d_info = {
 	GEN7_FEATURES,
 	.is_ivybridge = 1,
 	GEN_DEFAULT_PIPEOFFSETS,
+	IVB_CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_ivybridge_m_info = {
@@ -216,6 +241,7 @@ static const struct intel_device_info intel_ivybridge_m_info = {
 	.is_ivybridge = 1,
 	.is_mobile = 1,
 	GEN_DEFAULT_PIPEOFFSETS,
+	IVB_CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_ivybridge_q_info = {
@@ -223,6 +249,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
 	.is_ivybridge = 1,
 	.num_pipes = 0, /* legal, last one wins */
 	GEN_DEFAULT_PIPEOFFSETS,
+	IVB_CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_valleyview_m_info = {
@@ -234,6 +261,7 @@ static const struct intel_device_info intel_valleyview_m_info = {
 	.has_fbc = 0, /* legal, last one wins */
 	.has_llc = 0, /* legal, last one wins */
 	GEN_DEFAULT_PIPEOFFSETS,
+	CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_valleyview_d_info = {
@@ -244,6 +272,7 @@ static const struct intel_device_info intel_valleyview_d_info = {
 	.has_fbc = 0, /* legal, last one wins */
 	.has_llc = 0, /* legal, last one wins */
 	GEN_DEFAULT_PIPEOFFSETS,
+	CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_haswell_d_info = {
@@ -253,6 +282,7 @@ static const struct intel_device_info intel_haswell_d_info = {
 	.has_fpga_dbg = 1,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 	GEN_DEFAULT_PIPEOFFSETS,
+	IVB_CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_haswell_m_info = {
@@ -263,6 +293,7 @@ static const struct intel_device_info intel_haswell_m_info = {
 	.has_fpga_dbg = 1,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 	GEN_DEFAULT_PIPEOFFSETS,
+	IVB_CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_broadwell_d_info = {
@@ -273,6 +304,7 @@ static const struct intel_device_info intel_broadwell_d_info = {
 	.has_ddi = 1,
 	.has_fbc = 1,
 	GEN_DEFAULT_PIPEOFFSETS,
+	IVB_CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_broadwell_m_info = {
@@ -283,6 +315,7 @@ static const struct intel_device_info intel_broadwell_m_info = {
 	.has_ddi = 1,
 	.has_fbc = 1,
 	GEN_DEFAULT_PIPEOFFSETS,
+	IVB_CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_cherryview_info = {
@@ -293,6 +326,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.is_valleyview = 1,
 	.display_mmio_offset = VLV_DISPLAY_BASE,
 	GEN_CHV_PIPEOFFSETS,
+	CURSOR_OFFSETS,
 };
 
 /*
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a67f18f..b1191cf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -558,6 +558,7 @@ struct intel_device_info {
 	int dpll_offsets[I915_MAX_PIPES];
 	int dpll_md_offsets[I915_MAX_PIPES];
 	int palette_offsets[I915_MAX_PIPES];
+	int cursor_offsets[I915_MAX_PIPES];
 };
 
 #undef DEFINE_FLAG
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 92de47b..3367d5e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3810,7 +3810,7 @@ enum punit_power_well {
 #define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45)
 
 /* Cursor A & B regs */
-#define _CURACNTR		(dev_priv->info.display_mmio_offset + 0x70080)
+#define _CURACNTR		0x70080
 /* Old style CUR*CNTR flags (desktop 8xx) */
 #define   CURSOR_ENABLE		0x80000000
 #define   CURSOR_GAMMA_ENABLE	0x40000000
@@ -3837,28 +3837,34 @@ enum punit_power_well {
 #define   MCURSOR_PIPE_B	(1 << 28)
 #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
 #define   CURSOR_TRICKLE_FEED_DISABLE	(1 << 14)
-#define _CURABASE		(dev_priv->info.display_mmio_offset + 0x70084)
-#define _CURAPOS		(dev_priv->info.display_mmio_offset + 0x70088)
+#define _CURABASE		0x70084
+#define _CURAPOS		0x70088
 #define   CURSOR_POS_MASK       0x007FF
 #define   CURSOR_POS_SIGN       0x8000
 #define   CURSOR_X_SHIFT        0
 #define   CURSOR_Y_SHIFT        16
 #define CURSIZE			0x700a0
-#define _CURBCNTR		(dev_priv->info.display_mmio_offset + 0x700c0)
-#define _CURBBASE		(dev_priv->info.display_mmio_offset + 0x700c4)
-#define _CURBPOS		(dev_priv->info.display_mmio_offset + 0x700c8)
+#define _CURBCNTR		0x700c0
+#define _CURBBASE		0x700c4
+#define _CURBPOS		0x700c8
 
 #define _CURBCNTR_IVB		0x71080
 #define _CURBBASE_IVB		0x71084
 #define _CURBPOS_IVB		0x71088
 
-#define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
-#define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
-#define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
+#define _CURSOR2(pipe, reg) (dev_priv->info.cursor_offsets[(pipe)] - \
+	dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
+	dev_priv->info.display_mmio_offset)
+
+#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
+#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
+#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
 
-#define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB)
-#define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB)
-#define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
+#define CURSOR_A_OFFSET 0x70080
+#define CURSOR_B_OFFSET 0x700c0
+#define CHV_CURSOR_C_OFFSET 0x700e0
+#define IVB_CURSOR_B_OFFSET 0x71080
+#define IVB_CURSOR_C_OFFSET 0x72080
 
 /* Display A control */
 #define _DSPACNTR				0x70180
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 51d9079..798d91f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1181,10 +1181,8 @@ static void assert_cursor(struct drm_i915_private *dev_priv,
 
 	if (IS_845G(dev) || IS_I865G(dev))
 		cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
-	else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
-		cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
 	else
-		cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
+		cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
 
 	WARN(cur_state != state,
 	     "cursor on pipe %c assertion failure (expected %s, current %s)\n",
@@ -7955,7 +7953,7 @@ static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
 
 	if (intel_crtc->cursor_visible != visible) {
 		int16_t width = intel_crtc->cursor_width;
-		uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
+		uint32_t cntl = I915_READ(CURCNTR(pipe));
 		if (base) {
 			cntl &= ~CURSOR_MODE;
 			cntl |= MCURSOR_GAMMA_ENABLE;
@@ -7981,14 +7979,14 @@ static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
 			cntl |= CURSOR_PIPE_CSC_ENABLE;
 			cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
 		}
-		I915_WRITE(CURCNTR_IVB(pipe), cntl);
+		I915_WRITE(CURCNTR(pipe), cntl);
 
 		intel_crtc->cursor_visible = visible;
 	}
 	/* and commit changes on next vblank */
-	POSTING_READ(CURCNTR_IVB(pipe));
-	I915_WRITE(CURBASE_IVB(pipe), base);
-	POSTING_READ(CURBASE_IVB(pipe));
+	POSTING_READ(CURCNTR(pipe));
+	I915_WRITE(CURBASE(pipe), base);
+	POSTING_READ(CURBASE(pipe));
 }
 
 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
@@ -8035,16 +8033,14 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
 	if (!visible && !intel_crtc->cursor_visible)
 		return;
 
-	if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
-		I915_WRITE(CURPOS_IVB(pipe), pos);
+	I915_WRITE(CURPOS(pipe), pos);
+
+	if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
 		ivb_update_cursor(crtc, base);
-	} else {
-		I915_WRITE(CURPOS(pipe), pos);
-		if (IS_845G(dev) || IS_I865G(dev))
-			i845_update_cursor(crtc, base);
-		else
-			i9xx_update_cursor(crtc, base);
-	}
+	else if (IS_845G(dev) || IS_I865G(dev))
+		i845_update_cursor(crtc, base);
+	else
+		i9xx_update_cursor(crtc, base);
 }
 
 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
@@ -12270,15 +12266,9 @@ intel_display_capture_error_state(struct drm_device *dev)
 		if (!error->pipe[i].power_domain_on)
 			continue;
 
-		if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
-			error->cursor[i].control = I915_READ(CURCNTR(i));
-			error->cursor[i].position = I915_READ(CURPOS(i));
-			error->cursor[i].base = I915_READ(CURBASE(i));
-		} else {
-			error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
-			error->cursor[i].position = I915_READ(CURPOS_IVB(i));
-			error->cursor[i].base = I915_READ(CURBASE_IVB(i));
-		}
+		error->cursor[i].control = I915_READ(CURCNTR(i));
+		error->cursor[i].position = I915_READ(CURPOS(i));
+		error->cursor[i].base = I915_READ(CURBASE(i));
 
 		error->plane[i].control = I915_READ(DSPCNTR(i));
 		error->plane[i].stride = I915_READ(DSPSTRIDE(i));
-- 
1.8.3.2

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[PATCH 56/71] drm/i915/chv: Bump num_pipes to 3

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

CHV has three pipes so let's expose them all.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 66cff97..2aeca7e 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -320,7 +320,7 @@ static const struct intel_device_info intel_broadwell_m_info = {
 
 static const struct intel_device_info intel_cherryview_info = {
 	.is_preliminary = 1,
-	.gen = 8, .num_pipes = 2,
+	.gen = 8, .num_pipes = 3,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 	.is_valleyview = 1,
-- 
1.8.3.2

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[PATCH 57/71] drm/i915/chv: Fix PORT_TO_PIPE for CHV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Fix the encoder .get_config hooks to report the correct active pipe for
CHV.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   | 2 ++
 drivers/gpu/drm/i915/intel_dp.c   | 2 ++
 drivers/gpu/drm/i915/intel_hdmi.c | 2 ++
 3 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3367d5e..a3957c7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5108,6 +5108,8 @@ enum punit_power_well {
 #define  PORT_TRANS_SEL_CPT(pipe)	((pipe) << 29)
 #define  PORT_TO_PIPE(val)	(((val) & (1<<30)) >> 30)
 #define  PORT_TO_PIPE_CPT(val)	(((val) & PORT_TRANS_SEL_MASK) >> 29)
+#define  SDVO_PORT_TO_PIPE_CHV(val)	(((val) & (3<<24)) >> 24)
+#define  DP_PORT_TO_PIPE_CHV(val)	(((val) & (3<<16)) >> 16)
 
 #define TRANS_DP_CTL_A		0xe0300
 #define TRANS_DP_CTL_B		0xe1300
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6ae4d28..7c4047b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1423,6 +1423,8 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
 
 	if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 		*pipe = PORT_TO_PIPE_CPT(tmp);
+	} else if (IS_CHERRYVIEW(dev)) {
+		*pipe = DP_PORT_TO_PIPE_CHV(tmp);
 	} else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
 		*pipe = PORT_TO_PIPE(tmp);
 	} else {
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index ba57edd..4f8deba 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -683,6 +683,8 @@ static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 
 	if (HAS_PCH_CPT(dev))
 		*pipe = PORT_TO_PIPE_CPT(tmp);
+	else if (IS_CHERRYVIEW(dev))
+		*pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
 	else
 		*pipe = PORT_TO_PIPE(tmp);
 
-- 
1.8.3.2

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[PATCH 58/71] drm/i915/chv: Register port D encoders and connectors

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      | 1 +
 drivers/gpu/drm/i915/intel_display.c | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a3957c7..4c0edb8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2435,6 +2435,7 @@ enum punit_power_well {
 #define GEN3_SDVOC	0x61160
 #define GEN4_HDMIB	GEN3_SDVOB
 #define GEN4_HDMIC	GEN3_SDVOC
+#define CHV_HDMID	0x6116C
 #define PCH_SDVOB	0xe1140
 #define PCH_HDMIB	PCH_SDVOB
 #define PCH_HDMIC	0xe1150
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 798d91f..bf64e9d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11050,6 +11050,15 @@ static void intel_setup_outputs(struct drm_device *dev)
 				intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
 		}
 
+		if (IS_CHERRYVIEW(dev)) {
+			if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
+				intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
+						PORT_D);
+				if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
+					intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
+			}
+		}
+
 		intel_dsi_init(dev);
 	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
 		bool found = false;
-- 
1.8.3.2

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[PATCH 59/71] drm/i915/chv: Fix CHV PLL state tracking

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Setup the pipe config dpll state correctly for CHV. Also add
a assert_pipe_disabled() to chv_disable_pll(), and program the
DPLL_MD registers in chv_enable_pll().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 41 +++++++++++++++++++++++-------------
 1 file changed, 26 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index bf64e9d..d531c9d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1559,7 +1559,6 @@ static void chv_enable_pll(struct intel_crtc *crtc)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int pipe = crtc->pipe;
 	enum dpio_channel port = vlv_pipe_to_channel(pipe);
-	int dpll = DPLL(crtc->pipe);
 	u32 tmp;
 
 	assert_pipe_disabled(dev_priv, crtc->pipe);
@@ -1579,20 +1578,21 @@ static void chv_enable_pll(struct intel_crtc *crtc)
 	udelay(1);
 
 	/* Enable PLL */
-	tmp = I915_READ(dpll);
-	tmp |= DPLL_VCO_ENABLE;
-	I915_WRITE(dpll, tmp);
+	I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
 
 	/* Check PLL is locked */
-	if (wait_for(((I915_READ(dpll) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
+	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
 		DRM_ERROR("PLL %d failed to lock\n", pipe);
 
+	/* not sure when this should be written */
+	I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
+	POSTING_READ(DPLL_MD(pipe));
+
 	/* Deassert soft data lane reset*/
 	tmp = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
 	tmp |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), tmp);
 
-
 	mutex_unlock(&dev_priv->dpio_lock);
 }
 
@@ -1684,14 +1684,17 @@ static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 
 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 {
-	int dpll = DPLL(pipe);
 	u32 val;
 
-	/* Set PLL en = 0 */
-	val = I915_READ(dpll);
-	val &= ~DPLL_VCO_ENABLE;
-	I915_WRITE(dpll, val);
+	/* Make sure the pipe isn't still relying on us */
+	assert_pipe_disabled(dev_priv, pipe);
 
+	/* Set PLL en = 0 */
+	val = DPLL_SSC_REF_CLOCK_CHV;
+	if (pipe != PIPE_A)
+		val |= DPLL_INTEGRATED_CRI_CLK_VLV;
+	I915_WRITE(DPLL(pipe), val);
+	POSTING_READ(DPLL(pipe));
 }
 
 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
@@ -5448,7 +5451,14 @@ static void chv_update_pll(struct intel_crtc *crtc)
 	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
 	int refclk;
 
-	mutex_lock(&dev_priv->dpio_lock);
+	crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
+		DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
+		DPLL_VCO_ENABLE;
+	if (pipe != PIPE_A)
+		crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
+
+	crtc->config.dpll_hw_state.dpll_md =
+		(crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
 
 	bestn = crtc->config.dpll.n;
 	bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
@@ -5460,9 +5470,10 @@ static void chv_update_pll(struct intel_crtc *crtc)
 	/*
 	 * Enable Refclk and SSC
 	 */
-	val = I915_READ(dpll_reg);
-	val |= (DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV);
-	I915_WRITE(dpll_reg, val);
+	I915_WRITE(dpll_reg,
+		   crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
+
+	mutex_lock(&dev_priv->dpio_lock);
 
 	/* Propagate soft reset to data lane reset */
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
-- 
1.8.3.2

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[PATCH 60/71] drm/i915/chv: Move data lane deassert to encoder pre_enable

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We need to pick the correct data lanes based on the port not the
pipe, so move the data lane deassert into the encoder .pre_enable()
hook from the chv_enable_pll().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 5 -----
 drivers/gpu/drm/i915/intel_dp.c      | 9 ++++++++-
 drivers/gpu/drm/i915/intel_hdmi.c    | 8 +++++++-
 3 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d531c9d..39be658 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1588,11 +1588,6 @@ static void chv_enable_pll(struct intel_crtc *crtc)
 	I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
 	POSTING_READ(DPLL_MD(pipe));
 
-	/* Deassert soft data lane reset*/
-	tmp = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
-	tmp |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), tmp);
-
 	mutex_unlock(&dev_priv->dpio_lock);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7c4047b..ad56cac 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1950,9 +1950,16 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
 	enum dpio_channel ch = vlv_dport_to_channel(dport);
 	int pipe = intel_crtc->pipe;
 	int data, i;
+	u32 val;
 
-	/* Program Tx lane latency optimal setting*/
 	mutex_lock(&dev_priv->dpio_lock);
+
+	/* Deassert soft data lane reset*/
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
+	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
+
+	/* Program Tx lane latency optimal setting*/
 	for (i = 0; i < 4; i++) {
 		/* Set the latency optimal bit */
 		data = (i == 1) ? 0x0 : 0x6;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 4f8deba..fbba669 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1214,8 +1214,14 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
 	int data, i;
 	u32 val;
 
-	/* Program Tx latency optimal setting */
 	mutex_lock(&dev_priv->dpio_lock);
+
+	/* Deassert soft data lane reset*/
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
+	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
+
+	/* Program Tx latency optimal setting */
 	for (i = 0; i < 4; i++) {
 		/* Set the latency optimal bit */
 		data = (i == 1) ? 0x0 : 0x6;
-- 
1.8.3.2

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[PATCH 61/71] drm/i915/chv: Turn off dclkp after the PLL has been disabled

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

During the enable sequence we first enable the dclkp output to the
display controller, and then enable the PLL. Do the opposite during
the disable sequence.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 39be658..2033ffc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1679,6 +1679,7 @@ static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 
 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 {
+	enum dpio_channel port = vlv_pipe_to_channel(pipe);
 	u32 val;
 
 	/* Make sure the pipe isn't still relying on us */
@@ -1690,6 +1691,15 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 		val |= DPLL_INTEGRATED_CRI_CLK_VLV;
 	I915_WRITE(DPLL(pipe), val);
 	POSTING_READ(DPLL(pipe));
+
+	mutex_lock(&dev_priv->dpio_lock);
+
+	/* Disable 10bit clock to display controller */
+	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
+	val &= ~DPIO_DCLKP_EN;
+	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
+
+	mutex_unlock(&dev_priv->dpio_lock);
 }
 
 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
@@ -5475,11 +5485,6 @@ static void chv_update_pll(struct intel_crtc *crtc)
 	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), val);
 
-	/* Disable 10bit clock to display controller */
-	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
-	val &= ~DPIO_DCLKP_EN;
-	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
-
 	/* p1 and p2 divider */
 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
 			5 << DPIO_CHV_S1_DIV_SELECT |
-- 
1.8.3.2

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[PATCH 62/71] drm/i915/chv: Reset data lanes in encoder .post_disable() hook

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Seems like we shouldn't leave the data lane resert deasserted when
the port if disabled. So propagate the reset the data lanes in
the encoder .post_disable() hook.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |  7 +------
 drivers/gpu/drm/i915/intel_dp.c      | 25 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c    | 22 ++++++++++++++++++++++
 3 files changed, 48 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2033ffc..602bfa3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5452,7 +5452,7 @@ static void chv_update_pll(struct intel_crtc *crtc)
 	int pipe = crtc->pipe;
 	int dpll_reg = DPLL(crtc->pipe);
 	enum dpio_channel port = vlv_pipe_to_channel(pipe);
-	u32 val, loopfilter, intcoeff;
+	u32 loopfilter, intcoeff;
 	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
 	int refclk;
 
@@ -5480,11 +5480,6 @@ static void chv_update_pll(struct intel_crtc *crtc)
 
 	mutex_lock(&dev_priv->dpio_lock);
 
-	/* Propagate soft reset to data lane reset */
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
-	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), val);
-
 	/* p1 and p2 divider */
 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
 			5 << DPIO_CHV_S1_DIV_SELECT |
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ad56cac..3feec9d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1828,6 +1828,30 @@ static void vlv_post_disable_dp(struct intel_encoder *encoder)
 	intel_dp_link_down(intel_dp);
 }
 
+static void chv_post_disable_dp(struct intel_encoder *encoder)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc =
+		to_intel_crtc(encoder->base.crtc);
+	enum dpio_channel ch = vlv_dport_to_channel(dport);
+	enum pipe pipe = intel_crtc->pipe;
+	u32 val;
+
+	intel_dp_link_down(intel_dp);
+
+	mutex_lock(&dev_priv->dpio_lock);
+
+	/* Propagate soft reset to data lane reset */
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
+	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
+
+	mutex_unlock(&dev_priv->dpio_lock);
+}
+
 static void intel_enable_dp(struct intel_encoder *encoder)
 {
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
@@ -4064,6 +4088,7 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
 	if (IS_CHERRYVIEW(dev)) {
 		intel_encoder->pre_enable = chv_pre_enable_dp;
 		intel_encoder->enable = vlv_enable_dp;
+		intel_encoder->post_disable = chv_post_disable_dp;
 	} else if (IS_VALLEYVIEW(dev)) {
 		intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
 		intel_encoder->pre_enable = vlv_pre_enable_dp;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index fbba669..670e02e 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1202,6 +1202,27 @@ static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
 	mutex_unlock(&dev_priv->dpio_lock);
 }
 
+static void chv_hdmi_post_disable(struct intel_encoder *encoder)
+{
+	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
+	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc =
+		to_intel_crtc(encoder->base.crtc);
+	enum dpio_channel ch = vlv_dport_to_channel(dport);
+	enum pipe pipe = intel_crtc->pipe;
+	u32 val;
+
+	mutex_lock(&dev_priv->dpio_lock);
+
+	/* Propagate soft reset to data lane reset */
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
+	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
+
+	mutex_unlock(&dev_priv->dpio_lock);
+}
+
 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
 {
 	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
@@ -1427,6 +1448,7 @@ void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
 	if (IS_CHERRYVIEW(dev)) {
 		intel_encoder->pre_enable = chv_hdmi_pre_enable;
 		intel_encoder->enable = vlv_enable_hdmi;
+		intel_encoder->post_disable = chv_hdmi_post_disable;
 	} else if (IS_VALLEYVIEW(dev)) {
 		intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
 		intel_encoder->pre_enable = vlv_hdmi_pre_enable;
-- 
1.8.3.2

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[PATCH 63/71] drm/i915/chv: Set soft reset override bit for data lane resets

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The bits we've been setting so far only progagate the reset singal to
the data lanes. To actaully force the reset signal we need to set another
override bit.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   | 1 +
 drivers/gpu/drm/i915/intel_dp.c   | 8 ++++++++
 drivers/gpu/drm/i915/intel_hdmi.c | 8 ++++++++
 3 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4c0edb8..4617fb3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -656,6 +656,7 @@ enum punit_power_well {
 
 #define _VLV_PCS_DW1_CH0		0x8204
 #define _VLV_PCS_DW1_CH1		0x8404
+#define   CHV_PCS_REQ_SOFTRESET_EN	(1<<23)
 #define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN	(1<<22)
 #define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
 #define   DPIO_PCS_CLK_DATAWIDTH_SHIFT	(6)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3feec9d..079e0e3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1845,6 +1845,10 @@ static void chv_post_disable_dp(struct intel_encoder *encoder)
 	mutex_lock(&dev_priv->dpio_lock);
 
 	/* Propagate soft reset to data lane reset */
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+	val |= CHV_PCS_REQ_SOFTRESET_EN;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
+
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
 	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
@@ -1979,6 +1983,10 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
 	mutex_lock(&dev_priv->dpio_lock);
 
 	/* Deassert soft data lane reset*/
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+	val |= CHV_PCS_REQ_SOFTRESET_EN;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
+
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
 	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 670e02e..6a2152b 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1216,6 +1216,10 @@ static void chv_hdmi_post_disable(struct intel_encoder *encoder)
 	mutex_lock(&dev_priv->dpio_lock);
 
 	/* Propagate soft reset to data lane reset */
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+	val |= CHV_PCS_REQ_SOFTRESET_EN;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val)
+;
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
 	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
@@ -1238,6 +1242,10 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
 	mutex_lock(&dev_priv->dpio_lock);
 
 	/* Deassert soft data lane reset*/
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+	val |= CHV_PCS_REQ_SOFTRESET_EN;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
+
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
 	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
-- 
1.8.3.2

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[PATCH 64/71] drm/i915/chv: Don't use PCS group access reads

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

All PCS groups access reads return 0xffffffff, so we can't use group
access for RMW cycles. Instead target each spline separately.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   | 14 ++++++++++++++
 drivers/gpu/drm/i915/intel_dp.c   | 32 ++++++++++++++++++++++++--------
 drivers/gpu/drm/i915/intel_hdmi.c | 34 +++++++++++++++++++++++++---------
 3 files changed, 63 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4617fb3..ffed03e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -654,6 +654,13 @@ enum punit_power_well {
 #define   DPIO_PCS_TX_LANE1_RESET	(1<<7)
 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
 
+#define _VLV_PCS01_DW0_CH0		0x200
+#define _VLV_PCS23_DW0_CH0		0x400
+#define _VLV_PCS01_DW0_CH1		0x2600
+#define _VLV_PCS23_DW0_CH1		0x2800
+#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
+#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
+
 #define _VLV_PCS_DW1_CH0		0x8204
 #define _VLV_PCS_DW1_CH1		0x8404
 #define   CHV_PCS_REQ_SOFTRESET_EN	(1<<23)
@@ -663,6 +670,13 @@ enum punit_power_well {
 #define   DPIO_PCS_CLK_SOFT_RESET	(1<<5)
 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
 
+#define _VLV_PCS01_DW1_CH0		0x204
+#define _VLV_PCS23_DW1_CH0		0x404
+#define _VLV_PCS01_DW1_CH1		0x2604
+#define _VLV_PCS23_DW1_CH1		0x2804
+#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
+#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
+
 #define _VLV_PCS_DW8_CH0		0x8220
 #define _VLV_PCS_DW8_CH1		0x8420
 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 079e0e3..cc7bccd3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1845,13 +1845,21 @@ static void chv_post_disable_dp(struct intel_encoder *encoder)
 	mutex_lock(&dev_priv->dpio_lock);
 
 	/* Propagate soft reset to data lane reset */
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
 	val |= CHV_PCS_REQ_SOFTRESET_EN;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
 
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
+	val |= CHV_PCS_REQ_SOFTRESET_EN;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
+	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
 	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
 
 	mutex_unlock(&dev_priv->dpio_lock);
 }
@@ -1983,13 +1991,21 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
 	mutex_lock(&dev_priv->dpio_lock);
 
 	/* Deassert soft data lane reset*/
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
 	val |= CHV_PCS_REQ_SOFTRESET_EN;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
+	val |= CHV_PCS_REQ_SOFTRESET_EN;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
+	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
 
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
 	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
 
 	/* Program Tx lane latency optimal setting*/
 	for (i = 0; i < 4; i++) {
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 6a2152b..c3896b0 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1216,13 +1216,21 @@ static void chv_hdmi_post_disable(struct intel_encoder *encoder)
 	mutex_lock(&dev_priv->dpio_lock);
 
 	/* Propagate soft reset to data lane reset */
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
 	val |= CHV_PCS_REQ_SOFTRESET_EN;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val)
-;
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
+	val |= CHV_PCS_REQ_SOFTRESET_EN;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
+	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
 	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
 
 	mutex_unlock(&dev_priv->dpio_lock);
 }
@@ -1242,13 +1250,21 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
 	mutex_lock(&dev_priv->dpio_lock);
 
 	/* Deassert soft data lane reset*/
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
 	val |= CHV_PCS_REQ_SOFTRESET_EN;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
+	val |= CHV_PCS_REQ_SOFTRESET_EN;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
+	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
 
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
 	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
 
 	/* Program Tx latency optimal setting */
 	for (i = 0; i < 4; i++) {
-- 
1.8.3.2

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[PATCH 65/71] drm/i915/chv: Don't do group access reads from TX lanes either

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Like PCS, TX group reads return 0xffffffff. So we need to target each
lane separately if we want to use RMW cycles to update the registers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   | 11 +++++++++
 drivers/gpu/drm/i915/intel_dp.c   | 49 +++++++++++++++++++++++++--------------
 drivers/gpu/drm/i915/intel_hdmi.c | 28 +++++++++++++---------
 3 files changed, 59 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ffed03e..b91232f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -802,6 +802,17 @@ enum punit_power_well {
 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
 					(lane) * 0x200 + (offset))
 
+#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
+#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
+#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
+#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
+#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
+#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
+#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
+#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
+#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
+#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
+#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
 #define   DPIO_FRC_LATENCY_SHFIT	(8)
 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index cc7bccd3..4c54930 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2267,10 +2267,11 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
 	struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
-	u32 deemph_reg_value, margin_reg_value, val, tx_dw2;
+	u32 deemph_reg_value, margin_reg_value, val;
 	uint8_t train_set = intel_dp->train_set[0];
 	enum dpio_channel ch = vlv_dport_to_channel(dport);
-	int pipe = intel_crtc->pipe;
+	enum pipe pipe = intel_crtc->pipe;
+	int i;
 
 	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
 	case DP_TRAIN_PRE_EMPHASIS_0:
@@ -2348,21 +2349,27 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
 	vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), 0);
 
 	/* Program swing deemph */
-	val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW4(ch));
-	val &= ~DPIO_SWING_DEEMPH9P5_MASK;
-	val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(ch), val);
+	for (i = 0; i < 4; i++) {
+		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
+		val &= ~DPIO_SWING_DEEMPH9P5_MASK;
+		val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
+		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
+	}
 
 	/* Program swing margin */
-	tx_dw2 = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch));
-	tx_dw2 &= ~DPIO_SWING_MARGIN_MASK;
-	tx_dw2 |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), tx_dw2);
+	for (i = 0; i < 4; i++) {
+		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
+		val &= ~DPIO_SWING_MARGIN_MASK;
+		val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
+		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
+	}
 
 	/* Disable unique transition scale */
-	val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
-	val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
+	for (i = 0; i < 4; i++) {
+		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
+		val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
+		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
+	}
 
 	if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
 			== DP_TRAIN_PRE_EMPHASIS_0) &&
@@ -2375,12 +2382,18 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
 		 * For now, for this unique transition scale selection, set bit
 		 * 27 for ch0 and ch1.
 		 */
-		val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
-		val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
-		vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
+		for (i = 0; i < 4; i++) {
+			val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
+			val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
+			vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
+		}
 
-		tx_dw2 |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
-		vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), tx_dw2);
+		for (i = 0; i < 4; i++) {
+			val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
+			val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
+			val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
+			vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
+		}
 	}
 
 	/* Start swing calculation */
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index c3896b0..e912554 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1287,20 +1287,26 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
 
 	/* FIXME: Program the support xxx V-dB */
 	/* Use 800mV-0dB */
-	val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW4(ch));
-	val &= ~DPIO_SWING_DEEMPH9P5_MASK;
-	val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(ch), val);
+	for (i = 0; i < 4; i++) {
+		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
+		val &= ~DPIO_SWING_DEEMPH9P5_MASK;
+		val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
+		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
+	}
 
-	val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch));
-	val &= ~DPIO_SWING_MARGIN_MASK;
-	val |= 102 << DPIO_SWING_MARGIN_SHIFT;
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), val);
+	for (i = 0; i < 4; i++) {
+		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
+		val &= ~DPIO_SWING_MARGIN_MASK;
+		val |= 102 << DPIO_SWING_MARGIN_SHIFT;
+		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
+	}
 
 	/* Disable unique transition scale */
-	val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
-	val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
+	for (i = 0; i < 4; i++) {
+		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
+		val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
+		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
+	}
 
 	/* Additional steps for 1200mV-0dB */
 #if 0
-- 
1.8.3.2

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[PATCH 66/71] drm/i915/chv: Use RMW to toggle swing calc init

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The spec only tells us to set individual bits here and there. So we use
RMW for most things. Do the same for the swing calc init.

Eventually we should optimize things to just blast the final value in
with group access whenever possible. But to do that someone needs to
take a good look at what's the reset value for each registers, and
possibly if the BIOS manages to frob with some of them. For now
use RMW access always.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   |  7 +++++++
 drivers/gpu/drm/i915/intel_dp.c   | 17 ++++++++++++++---
 drivers/gpu/drm/i915/intel_hdmi.c | 18 ++++++++++++++----
 3 files changed, 35 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b91232f..7056994 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -698,6 +698,13 @@ enum punit_power_well {
 #define   DPIO_PCS_SWING_CALC_TX1_TX3	(1<<31)
 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
 
+#define _VLV_PCS01_DW10_CH0		0x0228
+#define _VLV_PCS23_DW10_CH0		0x0428
+#define _VLV_PCS01_DW10_CH1		0x2628
+#define _VLV_PCS23_DW10_CH1		0x2828
+#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
+#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
+
 #define _VLV_PCS_DW11_CH0		0x822c
 #define _VLV_PCS_DW11_CH1		0x842c
 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4c54930..9cbd702 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2346,7 +2346,13 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
 	mutex_lock(&dev_priv->dpio_lock);
 
 	/* Clear calc init */
-	vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), 0);
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
+	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
+	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
 
 	/* Program swing deemph */
 	for (i = 0; i < 4; i++) {
@@ -2397,8 +2403,13 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
 	}
 
 	/* Start swing calculation */
-	vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch),
-		(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3));
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
+	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
+	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
 
 	/* LRC Bypass */
 	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index e912554..d2b1186 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1283,7 +1283,13 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
 	/* FIXME: Fix up value only after power analysis */
 
 	/* Clear calc init */
-	vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), 0);
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
+	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
+	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
 
 	/* FIXME: Program the support xxx V-dB */
 	/* Use 800mV-0dB */
@@ -1322,9 +1328,13 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
 				(0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT));
 #endif
 	/* Start swing calculation */
-	vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch),
-			DPIO_PCS_SWING_CALC_TX0_TX2 |
-			DPIO_PCS_SWING_CALC_TX1_TX3);
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
+	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
+	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
 
 	/* LRC Bypass */
 	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
-- 
1.8.3.2

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[PATCH 67/71] drm/i915/chv: Try to program the PHY used clock channel overrides

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

These should make it possible to feed port C from pipe A or port B from
pipe B. Didn't quite seem to work though.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   |  7 ++++++
 drivers/gpu/drm/i915/intel_dp.c   | 46 +++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c | 46 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 99 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7056994..4bb733b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -679,6 +679,8 @@ enum punit_power_well {
 
 #define _VLV_PCS_DW8_CH0		0x8220
 #define _VLV_PCS_DW8_CH1		0x8420
+#define   CHV_PCS_USEDCLKCHANNEL_OVRRIDE	(1 << 20)
+#define   CHV_PCS_USEDCLKCHANNEL		(1 << 21)
 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
 
 #define _VLV_PCS01_DW8_CH0		0x0220
@@ -803,6 +805,11 @@ enum punit_power_well {
 #define   DPIO_DCLKP_EN			(1 << 13)
 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
 
+#define _CHV_CMN_DW19_CH0		0x814c
+#define _CHV_CMN_DW6_CH1		0x8098
+#define   CHV_CMN_USEDCLKCHANNEL	(1 << 13)
+#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
+
 #define CHV_CMN_DW30			0x8178
 #define   DPIO_LRC_BYPASS		(1 << 3)
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9cbd702..9d6982e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2037,6 +2037,51 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
 	vlv_wait_port_ready(dev_priv, dport);
 }
 
+static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
+{
+	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
+	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc =
+		to_intel_crtc(encoder->base.crtc);
+	enum dpio_channel ch = vlv_dport_to_channel(dport);
+	enum pipe pipe = intel_crtc->pipe;
+	u32 val;
+
+	mutex_lock(&dev_priv->dpio_lock);
+
+	/* program clock channel usage */
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
+	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
+	if (pipe != PIPE_B)
+		val &= ~CHV_PCS_USEDCLKCHANNEL;
+	else
+		val |= CHV_PCS_USEDCLKCHANNEL;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
+	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
+	if (pipe != PIPE_B)
+		val &= ~CHV_PCS_USEDCLKCHANNEL;
+	else
+		val |= CHV_PCS_USEDCLKCHANNEL;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
+
+	/*
+	 * This a a bit weird since generally CL
+	 * matches the pipe, but here we need to
+	 * pick the CL based on the port.
+	 */
+	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
+	if (pipe != PIPE_B)
+		val &= ~CHV_CMN_USEDCLKCHANNEL;
+	else
+		val |= CHV_CMN_USEDCLKCHANNEL;
+	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
+
+	mutex_unlock(&dev_priv->dpio_lock);
+}
+
 /*
  * Native read with retry for link status and receiver capability reads for
  * cases where the sink may still be asleep.
@@ -4134,6 +4179,7 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
 	intel_encoder->get_hw_state = intel_dp_get_hw_state;
 	intel_encoder->get_config = intel_dp_get_config;
 	if (IS_CHERRYVIEW(dev)) {
+		intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
 		intel_encoder->pre_enable = chv_pre_enable_dp;
 		intel_encoder->enable = vlv_enable_dp;
 		intel_encoder->post_disable = chv_post_disable_dp;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index d2b1186..d36f74c 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1186,6 +1186,51 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
 	mutex_unlock(&dev_priv->dpio_lock);
 }
 
+static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
+{
+	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
+	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc =
+		to_intel_crtc(encoder->base.crtc);
+	enum dpio_channel ch = vlv_dport_to_channel(dport);
+	enum pipe pipe = intel_crtc->pipe;
+	u32 val;
+
+	mutex_lock(&dev_priv->dpio_lock);
+
+	/* program clock channel usage */
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
+	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
+	if (pipe != PIPE_B)
+		val &= ~CHV_PCS_USEDCLKCHANNEL;
+	else
+		val |= CHV_PCS_USEDCLKCHANNEL;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
+	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
+	if (pipe != PIPE_B)
+		val &= ~CHV_PCS_USEDCLKCHANNEL;
+	else
+		val |= CHV_PCS_USEDCLKCHANNEL;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
+
+	/*
+	 * This a a bit weird since generally CL
+	 * matches the pipe, but here we need to
+	 * pick the CL based on the port.
+	 */
+	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
+	if (pipe != PIPE_B)
+		val &= ~CHV_CMN_USEDCLKCHANNEL;
+	else
+		val |= CHV_CMN_USEDCLKCHANNEL;
+	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
+
+	mutex_unlock(&dev_priv->dpio_lock);
+}
+
 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
 {
 	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
@@ -1486,6 +1531,7 @@ void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
 	intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
 	intel_encoder->get_config = intel_hdmi_get_config;
 	if (IS_CHERRYVIEW(dev)) {
+		intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
 		intel_encoder->pre_enable = chv_hdmi_pre_enable;
 		intel_encoder->enable = vlv_enable_hdmi;
 		intel_encoder->post_disable = chv_hdmi_post_disable;
-- 
1.8.3.2

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[PATCH 68/71] drm/i915/chv: Force clock buffer enables

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Try to force the PHY clock buffer enables to make the clock routing
work.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   | 18 ++++++++++++++++++
 drivers/gpu/drm/i915/intel_dp.c   | 19 +++++++++++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c | 19 +++++++++++++++++++
 3 files changed, 56 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4bb733b..66231dd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -789,6 +789,16 @@ enum punit_power_well {
 #define	  DPIO_CHV_INT_COEFF_SHIFT	8
 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
 
+#define _CHV_CMN_DW5_CH0               0x8114
+#define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
+#define   CHV_BUFRIGHTENA1_NORMAL	(1 << 20)
+#define   CHV_BUFRIGHTENA1_FORCE	(3 << 20)
+#define   CHV_BUFRIGHTENA1_MASK		(3 << 20)
+#define   CHV_BUFLEFTENA1_DISABLE	(0 << 22)
+#define   CHV_BUFLEFTENA1_NORMAL	(1 << 22)
+#define   CHV_BUFLEFTENA1_FORCE		(3 << 22)
+#define   CHV_BUFLEFTENA1_MASK		(3 << 22)
+
 #define _CHV_CMN_DW13_CH0		0x8134
 #define _CHV_CMN_DW0_CH1		0x8080
 #define   DPIO_CHV_S1_DIV_SELECT	(21)
@@ -803,6 +813,14 @@ enum punit_power_well {
 #define _CHV_CMN_DW1_CH1		0x8084
 #define   DPIO_AFC_RECAL		(1 << 14)
 #define   DPIO_DCLKP_EN			(1 << 13)
+#define   CHV_BUFLEFTENA2_DISABLE	(0 << 17) /* CL2 DW1 only */
+#define   CHV_BUFLEFTENA2_NORMAL	(1 << 17) /* CL2 DW1 only */
+#define   CHV_BUFLEFTENA2_FORCE		(3 << 17) /* CL2 DW1 only */
+#define   CHV_BUFLEFTENA2_MASK		(3 << 17) /* CL2 DW1 only */
+#define   CHV_BUFRIGHTENA2_DISABLE	(0 << 19) /* CL2 DW1 only */
+#define   CHV_BUFRIGHTENA2_NORMAL	(1 << 19) /* CL2 DW1 only */
+#define   CHV_BUFRIGHTENA2_FORCE	(3 << 19) /* CL2 DW1 only */
+#define   CHV_BUFRIGHTENA2_MASK		(3 << 19) /* CL2 DW1 only */
 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
 
 #define _CHV_CMN_DW19_CH0		0x814c
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9d6982e..77e9e47 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2050,6 +2050,25 @@ static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
 
 	mutex_lock(&dev_priv->dpio_lock);
 
+	/* program left/right clock distribution */
+	if (pipe != PIPE_B) {
+		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
+		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
+		if (ch == DPIO_CH0)
+			val |= CHV_BUFLEFTENA1_FORCE;
+		if (ch == DPIO_CH1)
+			val |= CHV_BUFRIGHTENA1_FORCE;
+		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
+	} else {
+		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
+		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
+		if (ch == DPIO_CH1)
+			val |= CHV_BUFLEFTENA2_FORCE;
+		if (ch == DPIO_CH1)
+			val |= CHV_BUFRIGHTENA2_FORCE;
+		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
+	}
+
 	/* program clock channel usage */
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
 	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index d36f74c..8e3cc24 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1199,6 +1199,25 @@ static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
 
 	mutex_lock(&dev_priv->dpio_lock);
 
+	/* program left/right clock distribution */
+	if (pipe != PIPE_B) {
+		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
+		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
+		if (ch == DPIO_CH0)
+			val |= CHV_BUFLEFTENA1_FORCE;
+		if (ch == DPIO_CH1)
+			val |= CHV_BUFRIGHTENA1_FORCE;
+		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
+	} else {
+		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
+		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
+		if (ch == DPIO_CH1)
+			val |= CHV_BUFLEFTENA2_FORCE;
+		if (ch == DPIO_CH1)
+			val |= CHV_BUFRIGHTENA2_FORCE;
+		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
+	}
+
 	/* program clock channel usage */
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
 	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
-- 
1.8.3.2

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[PATCH 69/71] drm/i915/chv: Force PHY clock buffers off after PLL disable

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Now that we forced the clock buffers on in .pre_pll_enable() we
should probably undo the damage after we've turned the PLL off. So
add new .post_pll_disable() hooks where we do that.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 602bfa3..f8f023d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1699,6 +1699,17 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 	val &= ~DPIO_DCLKP_EN;
 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
 
+	/* disable left/right clock distribution */
+	if (pipe != PIPE_B) {
+		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
+		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
+		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
+	} else {
+		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
+		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
+		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
+	}
+
 	mutex_unlock(&dev_priv->dpio_lock);
 }
 
-- 
1.8.3.2

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[PATCH 70/71] drm/i915: Don't use pipe_offset stuff for DPLL registers

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

These are just single registers so wasting space for the pipe offsets
seems a bit pointless. So just use the _PIPE3() macro instead.

Also rewrite the _PIPE3() macro to be more obvious, and protect the
arguments properly.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c |  4 ----
 drivers/gpu/drm/i915/i915_drv.h |  2 --
 drivers/gpu/drm/i915/i915_reg.h | 26 ++++++++++----------------
 3 files changed, 10 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 2aeca7e..61d66cc 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -45,15 +45,11 @@ static struct drm_driver driver;
 			  PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
 	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
 			   TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
-	.dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET }, \
-	.dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \
 	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
 
 #define GEN_CHV_PIPEOFFSETS \
        .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, CHV_PIPE_C_OFFSET }, \
        .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, CHV_TRANSCODER_C_OFFSET, }, \
-       .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET, CHV_DPLL_C_OFFSET }, \
-       .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET, CHV_DPLL_C_MD_OFFSET }, \
        .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, CHV_PALETTE_C_OFFSET }
 
 #define CURSOR_OFFSETS \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b1191cf..6844d9a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -555,8 +555,6 @@ struct intel_device_info {
 	/* Register offsets for the various display pipes and transcoders */
 	int pipe_offsets[I915_MAX_TRANSCODERS];
 	int trans_offsets[I915_MAX_TRANSCODERS];
-	int dpll_offsets[I915_MAX_PIPES];
-	int dpll_md_offsets[I915_MAX_PIPES];
 	int palette_offsets[I915_MAX_PIPES];
 	int cursor_offsets[I915_MAX_PIPES];
 };
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 66231dd..9fed8ca 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -29,8 +29,8 @@
 #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
 
 #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
-#define _PIPE3(pipe, a, b, c) (pipe < 2 ? _PIPE(pipe, a, b) : c)
-#define _PORT3(port, a, b, c) (port < 2 ? _PORT(port, a, b) : c)
+#define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \
+			       (pipe) == PIPE_B ? (b) : (c))
 
 #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
 #define _MASKED_BIT_DISABLE(a) ((a) << 16)
@@ -1487,11 +1487,10 @@ enum punit_power_well {
 /*
  * Clock control & power management
  */
-#define DPLL_A_OFFSET 0x6014
-#define DPLL_B_OFFSET 0x6018
-#define CHV_DPLL_C_OFFSET 0x6030
-#define DPLL(pipe) (dev_priv->info.dpll_offsets[pipe] + \
-		    dev_priv->info.display_mmio_offset)
+#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
+#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
+#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
+#define DPLL(pipe) _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
 
 #define VGA0	0x6000
 #define VGA1	0x6004
@@ -1579,11 +1578,10 @@ enum punit_power_well {
 #define   SDVO_MULTIPLIER_SHIFT_HIRES		4
 #define   SDVO_MULTIPLIER_SHIFT_VGA		0
 
-#define DPLL_A_MD_OFFSET 0x601c /* 965+ only */
-#define DPLL_B_MD_OFFSET 0x6020 /* 965+ only */
-#define CHV_DPLL_C_MD_OFFSET 0x603c
-#define DPLL_MD(pipe) (dev_priv->info.dpll_md_offsets[pipe] + \
-		       dev_priv->info.display_mmio_offset)
+#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
+#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
+#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
+#define DPLL_MD(pipe) _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
 
 /*
  * UDI pixel divider, controlling how many pixels are stuffed into a packet.
@@ -6296,9 +6294,5 @@ enum punit_power_well {
 /* For UMS only (deprecated): */
 #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
 #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
-#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
-#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
-#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
-#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
 
 #endif /* _I915_REG_H_ */
-- 
1.8.3.2

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[PATCH 71/71] drm/i915/chv: Handle video DIP registers on CHV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The DIP registers are a mess on VLV and CHV. The register block on pipe
A is different than the register block on pipes B and C. In order to
handle that using the pipe offsets, we'd need a new pipe offset per
register, which seems wasteful. So instead just use the _PIPE3() macro
to handle these registers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9fed8ca..14e8de3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4784,8 +4784,7 @@ enum punit_power_well {
 #define _PCH_TRANSA_LINK_M2	0xe0048
 #define _PCH_TRANSA_LINK_N2	0xe004c
 
-/* Per-transcoder DIP controls */
-
+/* Per-transcoder DIP controls (PCH) */
 #define _VIDEO_DIP_CTL_A         0xe0200
 #define _VIDEO_DIP_DATA_A        0xe0208
 #define _VIDEO_DIP_GCP_A         0xe0210
@@ -4798,6 +4797,7 @@ enum punit_power_well {
 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
 
+/* Per-transcoder DIP controls (VLV) */
 #define VLV_VIDEO_DIP_CTL_A		(VLV_DISPLAY_BASE + 0x60200)
 #define VLV_VIDEO_DIP_DATA_A		(VLV_DISPLAY_BASE + 0x60208)
 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A	(VLV_DISPLAY_BASE + 0x60210)
@@ -4806,12 +4806,19 @@ enum punit_power_well {
 #define VLV_VIDEO_DIP_DATA_B		(VLV_DISPLAY_BASE + 0x61174)
 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B	(VLV_DISPLAY_BASE + 0x61178)
 
+#define CHV_VIDEO_DIP_CTL_C		(VLV_DISPLAY_BASE + 0x611f0)
+#define CHV_VIDEO_DIP_DATA_C		(VLV_DISPLAY_BASE + 0x611f4)
+#define CHV_VIDEO_DIP_GDCP_PAYLOAD_C	(VLV_DISPLAY_BASE + 0x611f8)
+
 #define VLV_TVIDEO_DIP_CTL(pipe) \
-	 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
+	_PIPE3((pipe), VLV_VIDEO_DIP_CTL_A, \
+	       VLV_VIDEO_DIP_CTL_B, CHV_VIDEO_DIP_CTL_C)
 #define VLV_TVIDEO_DIP_DATA(pipe) \
-	 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
+	_PIPE3((pipe), VLV_VIDEO_DIP_DATA_A, \
+	       VLV_VIDEO_DIP_DATA_B, CHV_VIDEO_DIP_DATA_C)
 #define VLV_TVIDEO_DIP_GCP(pipe) \
-	_PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
+	_PIPE3((pipe), VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
+		VLV_VIDEO_DIP_GDCP_PAYLOAD_B, CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
 
 /* Haswell DIP controls */
 #define HSW_VIDEO_DIP_CTL_A		0x60200
-- 
1.8.3.2

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Re: [PATCH 30/71] drm/i915/chv: Enable PM interrupts when we in CHV turbo initialize sequence.

[Chris Wilson]

On Wed, Apr 09, 2014 at 01:28:28PM +0300, ville.syrjala@linux.intel.com wrote:
> +static void gen8_enable_rps_interrupts(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	/* Clear out any stale interrupts first */
> +	spin_lock_irq(&dev_priv->irq_lock);
> +	WARN_ON(dev_priv->rps.pm_iir);
> +	I915_WRITE(GEN8_GT_IIR(2), I915_READ(GEN8_GT_IIR(2)));
> +	dev_priv->pm_irq_mask &= ~GEN6_PM_RPS_EVENTS;
> +	I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask);
> +	spin_unlock_irq(&dev_priv->irq_lock);
> +
> +	I915_WRITE(GEN8_GT_IER(2), GEN6_PM_RPS_EVENTS);
> +	/* only unmask PM interrupts we need. Mask all others. */
> +	I915_WRITE(GEN6_PMINTRMSK, ~GEN6_PM_RPS_EVENTS);

PMINTRMSK handling is now a part of set_rps (and so this line is
redundant).
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 30/71] drm/i915/chv: Enable PM interrupts when we in CHV turbo initialize sequence.

[Ville Syrjälä]

On Wed, Apr 09, 2014 at 02:06:54PM +0100, Chris Wilson wrote:
> On Wed, Apr 09, 2014 at 01:28:28PM +0300, ville.syrjala@linux.intel.com wrote:
> > +static void gen8_enable_rps_interrupts(struct drm_device *dev)
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +
> > +	/* Clear out any stale interrupts first */
> > +	spin_lock_irq(&dev_priv->irq_lock);
> > +	WARN_ON(dev_priv->rps.pm_iir);
> > +	I915_WRITE(GEN8_GT_IIR(2), I915_READ(GEN8_GT_IIR(2)));
> > +	dev_priv->pm_irq_mask &= ~GEN6_PM_RPS_EVENTS;
> > +	I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask);
> > +	spin_unlock_irq(&dev_priv->irq_lock);
> > +
> > +	I915_WRITE(GEN8_GT_IER(2), GEN6_PM_RPS_EVENTS);
> > +	/* only unmask PM interrupts we need. Mask all others. */
> > +	I915_WRITE(GEN6_PMINTRMSK, ~GEN6_PM_RPS_EVENTS);
> 
> PMINTRMSK handling is now a part of set_rps (and so this line is
> redundant).

Yeah there's been a lot of churn in this area recently and these patches
were written quite a while ago. I must admit I've not followed the recent
changes too closely, so I'm hoping Deepak will take the ball here and
massage this stuff until it fits in with the current code.

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 28/71] drm/i915/chv: Added CHV specific register read and write

[Chris Wilson]

On Wed, Apr 09, 2014 at 01:28:26PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Deepak S <deepak.s@intel.com>
> 
> Support to individually control Media/Render well based on the register access.
> Add CHV specific write function to habdle difference between registers
> that are sadowed vs those that need forcewake even for writes.
> 
> v2: Drop write FIFO for CHV and add comman well forcewake (Ville)
> 
> Signed-off-by: Deepak S <deepak.s@intel.com>
> [vsyrjala: Move the register range macros into intel_uncore.c]
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 139 +++++++++++++++++++++++++++++++++---
>  1 file changed, 131 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 823d699..8e3c686 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -495,6 +495,31 @@ void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
>  	((reg) >= 0x22000 && (reg) < 0x24000) ||\
>  	((reg) >= 0x30000 && (reg) < 0x40000))
>  
> +#define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
> +	(((reg) >= 0x2000 && (reg) < 0x4000) ||\
> +	((reg) >= 0x5000 && (reg) < 0x8000) ||\
> +	((reg) >= 0x8300 && (reg) < 0x8500) ||\
> +	((reg) >= 0xB000 && (reg) < 0xC000) ||\
> +	((reg) >= 0xE000 && (reg) < 0xE800))
> +
> +#define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)\
> +	(((reg) >= 0x8800 && (reg) < 0x8900) ||\
> +	((reg) >= 0xD000 && (reg) < 0xD800) ||\
> +	((reg) >= 0x12000 && (reg) < 0x14000) ||\
> +	((reg) >= 0x1A000 && (reg) < 0x1C000) ||\
> +	((reg) >= 0x1E800 && (reg) < 0x1EA00) ||\
> +	((reg) >= 0x30000 && (reg) < 0x40000))
> +
> +#define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)\
> +	(((reg) >= 0x4000 && (reg) < 0x5000) ||\
> +	((reg) >= 0x8000 && (reg) < 0x8300) ||\
> +	((reg) >= 0x8500 && (reg) < 0x8600) ||\
> +	((reg) >= 0x9000 && (reg) < 0xB000) ||\
> +	((reg) >= 0xC000 && (reg) < 0xc800) ||\
> +	((reg) >= 0xF000 && (reg) < 0x10000) ||\
> +	((reg) >= 0x14000 && (reg) < 0x14400) ||\
> +	((reg) >= 0x22000 && (reg) < 0x24000))

You could write this as a single stanza of

if (reg < foo) fwengine = BAR; 
else if (reg < baz) ...

which I think would not only help with us reviewing it, but wouldn't
generate so nearly as bad code.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 00/71] drm/i915/chv: Add Cherryview support

[Ville Syrjälä]

As you may have noticed some of this stuf may need a bit of work still
to fit in better with the more recent upstream changes.

So I think we need a few people to do some work here to the the patches
into a really good shape. So some division of labor would in order. I'm
proposing the following:
rc6/turbo -> Deepak as he's written the code anyway
interrupts -> Imre since he worked on the VLV interrupts recently

The rest of the patches should be fairly OK I think. So for the rest we
probably just need reviews mostly, and maybe we want to squash some of
the more trivial patches.

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 28/71] drm/i915/chv: Added CHV specific register read and write

[Ville Syrjälä]

On Wed, Apr 09, 2014 at 02:16:04PM +0100, Chris Wilson wrote:
> On Wed, Apr 09, 2014 at 01:28:26PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Deepak S <deepak.s@intel.com>
> > 
> > Support to individually control Media/Render well based on the register access.
> > Add CHV specific write function to habdle difference between registers
> > that are sadowed vs those that need forcewake even for writes.
> > 
> > v2: Drop write FIFO for CHV and add comman well forcewake (Ville)
> > 
> > Signed-off-by: Deepak S <deepak.s@intel.com>
> > [vsyrjala: Move the register range macros into intel_uncore.c]
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_uncore.c | 139 +++++++++++++++++++++++++++++++++---
> >  1 file changed, 131 insertions(+), 8 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> > index 823d699..8e3c686 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -495,6 +495,31 @@ void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
> >  	((reg) >= 0x22000 && (reg) < 0x24000) ||\
> >  	((reg) >= 0x30000 && (reg) < 0x40000))
> >  
> > +#define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
> > +	(((reg) >= 0x2000 && (reg) < 0x4000) ||\
> > +	((reg) >= 0x5000 && (reg) < 0x8000) ||\
> > +	((reg) >= 0x8300 && (reg) < 0x8500) ||\
> > +	((reg) >= 0xB000 && (reg) < 0xC000) ||\
> > +	((reg) >= 0xE000 && (reg) < 0xE800))
> > +
> > +#define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)\
> > +	(((reg) >= 0x8800 && (reg) < 0x8900) ||\
> > +	((reg) >= 0xD000 && (reg) < 0xD800) ||\
> > +	((reg) >= 0x12000 && (reg) < 0x14000) ||\
> > +	((reg) >= 0x1A000 && (reg) < 0x1C000) ||\
> > +	((reg) >= 0x1E800 && (reg) < 0x1EA00) ||\
> > +	((reg) >= 0x30000 && (reg) < 0x40000))
> > +
> > +#define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)\
> > +	(((reg) >= 0x4000 && (reg) < 0x5000) ||\
> > +	((reg) >= 0x8000 && (reg) < 0x8300) ||\
> > +	((reg) >= 0x8500 && (reg) < 0x8600) ||\
> > +	((reg) >= 0x9000 && (reg) < 0xB000) ||\
> > +	((reg) >= 0xC000 && (reg) < 0xc800) ||\
> > +	((reg) >= 0xF000 && (reg) < 0x10000) ||\
> > +	((reg) >= 0x14000 && (reg) < 0x14400) ||\
> > +	((reg) >= 0x22000 && (reg) < 0x24000))
> 
> You could write this as a single stanza of
> 
> if (reg < foo) fwengine = BAR; 
> else if (reg < baz) ...
> 
> which I think would not only help with us reviewing it, but wouldn't
> generate so nearly as bad code.

For me that looks harder to read as you can't see each range neatly on
one line anymore. But you may be right about getting better code out of
it. I must admit I've never checked what kind of code gcc generates
for these things.

Another idea would be to use a switch statement with case ranges, but
that doesn't seem really different to the current approach.

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 13/71] drm/i915/chv: Add Cherryview PCI IDs

[Chris Wilson]

On Wed, Apr 09, 2014 at 01:28:11PM +0300, ville.syrjala@linux.intel.com wrote:
> +#define INTEL_CHV_PCI_IDS(info) \

This name breaks the pattern.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 00/71] drm/i915/chv: Add Cherryview support

[S, Deepak]

Hi Ville,

I am Ok with  cleaning up and pushing the Code. Can you please tell me when we need to start pushing the code and branch to use (drm-intel-next)?

Thanks
Deepak

-----Original Message-----
From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com] 
Sent: Wednesday, April 9, 2014 6:55 PM
To: intel-gfx@lists.freedesktop.org
Cc: S, Deepak; Deak, Imre
Subject: Re: [PATCH 00/71] drm/i915/chv: Add Cherryview support

As you may have noticed some of this stuf may need a bit of work still to fit in better with the more recent upstream changes.

So I think we need a few people to do some work here to the the patches into a really good shape. So some division of labor would in order. I'm proposing the following:
rc6/turbo -> Deepak as he's written the code anyway interrupts -> Imre since he worked on the VLV interrupts recently

The rest of the patches should be fairly OK I think. So for the rest we probably just need reviews mostly, and maybe we want to squash some of the more trivial patches.

--
Ville Syrjälä
Intel OTC

Re: [PATCH 00/71] drm/i915/chv: Add Cherryview support

[Ville Syrjälä]

On Wed, Apr 09, 2014 at 02:30:52PM +0000, S, Deepak wrote:
> Hi Ville,
> 
> I am Ok with  cleaning up and pushing the Code. Can you please tell me when we need to start pushing the code and branch to use (drm-intel-next)?

Well you can consider it pushed now that it's in the open. The patches
just need a bit of extra polish I think. Well, unless you're planning
a full blown rewrite of the code ;)

I guess you need to take into consideration whatever bdw rc6/rps patches
are still in flight, but since you've been doing some review there I
think you have a better idea than I do how things are progressing.

I always work on top of nightly, so I guess that's a good choice :)

> 
> Thanks
> Deepak
> 
> -----Original Message-----
> From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com] 
> Sent: Wednesday, April 9, 2014 6:55 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: S, Deepak; Deak, Imre
> Subject: Re: [PATCH 00/71] drm/i915/chv: Add Cherryview support
> 
> As you may have noticed some of this stuf may need a bit of work still to fit in better with the more recent upstream changes.
> 
> So I think we need a few people to do some work here to the the patches into a really good shape. So some division of labor would in order. I'm proposing the following:
> rc6/turbo -> Deepak as he's written the code anyway interrupts -> Imre since he worked on the VLV interrupts recently
> 
> The rest of the patches should be fairly OK I think. So for the rest we probably just need reviews mostly, and maybe we want to squash some of the more trivial patches.
> 
> --
> Ville Syrjälä
> Intel OTC

-- 
Ville Syrjälä
Intel OTC

[PATCH v5 13/71] drm/i915/chv: Add Cherryview PCI IDs

[ville.syrjala]

From: Daniel Vetter <daniel.vetter@ffwll.ch>

v2: Update to also fill in the new num_pipes field.

v3: Rebase on top of the pciid extraction.

v4: Switch from info->has*ring to info->ring mask. Also add VEBOX support whiel
at it.

v5: s/CHV_PCI_IDS/CHV_IDS/, and drop the trailing '\'

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.c | 12 +++++++++++-
 include/drm/i915_pciids.h       |  6 ++++++
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index fa5d0ed..5a55131 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -279,6 +279,15 @@ static const struct intel_device_info intel_broadwell_m_info = {
 	GEN_DEFAULT_PIPEOFFSETS,
 };
 
+static const struct intel_device_info intel_cherryview_info = {
+	.is_preliminary = 1,
+	.gen = 8, .num_pipes = 2,
+	.need_gfx_hws = 1, .has_hotplug = 1,
+	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+	.is_valleyview = 1,
+	.display_mmio_offset = VLV_DISPLAY_BASE,
+};
+
 /*
  * Make sure any device matches here are from most specific to most
  * general.  For example, since the Quanta match is based on the subsystem
@@ -312,7 +321,8 @@ static const struct intel_device_info intel_broadwell_m_info = {
 	INTEL_VLV_M_IDS(&intel_valleyview_m_info),	\
 	INTEL_VLV_D_IDS(&intel_valleyview_d_info),	\
 	INTEL_BDW_M_IDS(&intel_broadwell_m_info),	\
-	INTEL_BDW_D_IDS(&intel_broadwell_d_info)
+	INTEL_BDW_D_IDS(&intel_broadwell_d_info),	\
+	INTEL_CHV_IDS(&intel_cherryview_info)
 
 static const struct pci_device_id pciidlist[] = {		/* aka */
 	INTEL_PCI_IDS,
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 940ece4..73274f9 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -233,4 +233,10 @@
 	_INTEL_BDW_D_IDS(2, info), \
 	_INTEL_BDW_D_IDS(3, info)
 
+#define INTEL_CHV_IDS(info) \
+	INTEL_VGA_DEVICE(0x22b0, info), \
+	INTEL_VGA_DEVICE(0x22b1, info), \
+	INTEL_VGA_DEVICE(0x22b2, info), \
+	INTEL_VGA_DEVICE(0x22b3, info)
+
 #endif /* _I915_PCIIDS_H */
-- 
1.8.3.2

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Re: [PATCH 02/71] drm/i915/chv: Add IS_CHERRYVIEW() macro

[Daniel Vetter]

On Wed, Apr 09, 2014 at 01:28:00PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We will treat Cherryview like Valleyview for most parts. Add a macro
> for cases when we need to tell the two apart.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Merged first 2 patches to dinq.
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_drv.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 41cf429..f760803 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1788,6 +1788,7 @@ struct drm_i915_cmd_table {
>  				 (dev)->pdev->device == 0x0106 || \
>  				 (dev)->pdev->device == 0x010A)
>  #define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
> +#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
>  #define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
>  #define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
>  #define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
> -- 
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 10/71] drm/i915/chv: Preliminary interrupt support for Cherryview

[Daniel Vetter]

On Wed, Apr 09, 2014 at 01:28:08PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Daniel Vetter <daniel.vetter@ffwll.ch>
> 
> CHV has the Gen8 master interrupt register, as well as Gen8
> GT/PCU interrupt registers.
> 
> The display block is based on VLV, with the main difference
> of adding pipe C.
> 
> FIXME: Lot of this is copy pasted from either VLV or BDW. We should
> probably refactor a bit to share the code better.
> 
> v2: Rewrite the order of operations to make more sense
>     Don't bail out if MASTER_CTL register doesn't show an interrupt,
>     as display interrupts aren't reported there.
> 
> v3: Rebase on top of Egbert Eich's hpd irq handling rework by using
> the relevant port hotplug logic like for vlv.
> 
> v4: Rebase on top of Ben's gt irq #define refactoring.
> 
> v5: Squash in gen8_gt_irq_handler refactoring from Zhao Yakui
> <yakui.zhao@intel.com>
> 
> v6: Adapt to upstream changes, dev_priv->irq_received is gone.
> 
> v7: Enable 3 the commented-out 3 pipe support.
> 
> v8: Grab irq_lock around i915_enable_pipestat()
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v2)
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Internal has a rebased version of this one here. Can you please fish it
out of there?
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_irq.c | 249 +++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 248 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 407742f..1581b3d 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1715,6 +1715,95 @@ out:
>  	return ret;
>  }
>  
> +static irqreturn_t cherryview_irq_handler(int irq, void *arg)
> +{
> +	struct drm_device *dev = (struct drm_device *) arg;
> +	drm_i915_private_t *dev_priv = dev->dev_private;
> +	u32 master_ctl, iir;
> +	irqreturn_t ret = IRQ_NONE;
> +	unsigned int pipes = 0;
> +
> +	master_ctl = I915_READ(GEN8_MASTER_IRQ);
> +
> +	I915_WRITE(GEN8_MASTER_IRQ, 0);
> +
> +	ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
> +
> +	iir = I915_READ(VLV_IIR);
> +
> +	if (iir & (I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT))
> +		pipes |= 1 << 0;
> +	if (iir & (I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT))
> +		pipes |= 1 << 1;
> +	if (iir & (I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT | I915_DISPLAY_PIPE_C_EVENT_INTERRUPT))
> +		pipes |= 1 << 2;
> +
> +	if (pipes) {
> +		u32 pipe_stats[I915_MAX_PIPES] = {};
> +		unsigned long irqflags;
> +		int pipe;
> +
> +		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> +		for_each_pipe(pipe) {
> +			unsigned int reg;
> +
> +			if (!(pipes & (1 << pipe)))
> +				continue;
> +
> +			reg = PIPESTAT(pipe);
> +			pipe_stats[pipe] = I915_READ(reg);
> +
> +			/*
> +			 * Clear the PIPE*STAT regs before the IIR
> +			 */
> +			if (pipe_stats[pipe] & 0x8000ffff) {
> +				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
> +					DRM_DEBUG_DRIVER("pipe %c underrun\n",
> +							 pipe_name(pipe));
> +				I915_WRITE(reg, pipe_stats[pipe]);
> +			}
> +		}
> +		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> +
> +		for_each_pipe(pipe) {
> +			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
> +				drm_handle_vblank(dev, pipe);
> +
> +			if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
> +				intel_prepare_page_flip(dev, pipe);
> +				intel_finish_page_flip(dev, pipe);
> +			}
> +		}
> +
> +		if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
> +			gmbus_irq_handler(dev);
> +
> +		ret = IRQ_HANDLED;
> +	}
> +
> +	/* Consume port.  Then clear IIR or we'll miss events */
> +	if (iir & I915_DISPLAY_PORT_INTERRUPT) {
> +		u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
> +
> +		I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
> +
> +		DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
> +				 hotplug_status);
> +		if (hotplug_status & HOTPLUG_INT_STATUS_I915)
> +			queue_work(dev_priv->wq,
> +				   &dev_priv->hotplug_work);
> +
> +		ret = IRQ_HANDLED;
> +	}
> +
> +	I915_WRITE(VLV_IIR, iir);
> +
> +	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
> +	POSTING_READ(GEN8_MASTER_IRQ);
> +
> +	return ret;
> +}
> +
>  static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
>  {
>  	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
> @@ -2985,6 +3074,61 @@ static void gen8_irq_preinstall(struct drm_device *dev)
>  	ibx_irq_preinstall(dev);
>  }
>  
> +static void cherryview_irq_preinstall(struct drm_device *dev)
> +{
> +	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
> +	int pipe;
> +
> +	I915_WRITE(GEN8_MASTER_IRQ, 0);
> +	POSTING_READ(GEN8_MASTER_IRQ);
> +
> +/* IIR can theoretically queue up two events. Be paranoid */
> +#define GEN8_IRQ_INIT_NDX(type, which)				\
> +do {								\
> +	I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff);	\
> +	POSTING_READ(GEN8_##type##_IMR(which));			\
> +	I915_WRITE(GEN8_##type##_IER(which), 0);		\
> +	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff);	\
> +	POSTING_READ(GEN8_##type##_IIR(which));			\
> +	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff);	\
> +} while (0)
> +
> +#define GEN8_IRQ_INIT(type)					\
> +do {								\
> +	I915_WRITE(GEN8_##type##_IMR, 0xffffffff);		\
> +	POSTING_READ(GEN8_##type##_IMR);			\
> +	I915_WRITE(GEN8_##type##_IER, 0);			\
> +	I915_WRITE(GEN8_##type##_IIR, 0xffffffff);		\
> +	POSTING_READ(GEN8_##type##_IIR);			\
> +	I915_WRITE(GEN8_##type##_IIR, 0xffffffff);		\
> +} while (0)
> +
> +	GEN8_IRQ_INIT_NDX(GT, 0);
> +	GEN8_IRQ_INIT_NDX(GT, 1);
> +	GEN8_IRQ_INIT_NDX(GT, 2);
> +	GEN8_IRQ_INIT_NDX(GT, 3);
> +
> +	GEN8_IRQ_INIT(PCU);
> +
> +#undef GEN8_IRQ_INIT
> +#undef GEN8_IRQ_INIT_NDX
> +
> +	POSTING_READ(GEN8_PCU_IIR);
> +
> +	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
> +
> +	I915_WRITE(PORT_HOTPLUG_EN, 0);
> +	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
> +
> +	for_each_pipe(pipe)
> +		I915_WRITE(PIPESTAT(pipe), 0xffff);
> +
> +	I915_WRITE(VLV_IMR, 0xffffffff);
> +	I915_WRITE(VLV_IER, 0x0);
> +	I915_WRITE(VLV_IIR, 0xffffffff);
> +	POSTING_READ(VLV_IIR);
> +}
> +
>  static void ibx_hpd_irq_setup(struct drm_device *dev)
>  {
>  	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
> @@ -3326,6 +3470,50 @@ static int gen8_irq_postinstall(struct drm_device *dev)
>  	return 0;
>  }
>  
> +static int cherryview_irq_postinstall(struct drm_device *dev)
> +{
> +	drm_i915_private_t *dev_priv = dev->dev_private;
> +	u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
> +		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
> +		I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
> +		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
> +		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT |
> +		I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
> +		I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT;
> +	u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
> +	unsigned long irqflags;
> +	int pipe;
> +
> +	/*
> +	 * Leave vblank interrupts masked initially.  enable/disable will
> +	 * toggle them based on usage.
> +	 */
> +	dev_priv->irq_mask = ~enable_mask |
> +		I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
> +		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT |
> +		I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT;
> +
> +	for_each_pipe(pipe)
> +		I915_WRITE(PIPESTAT(pipe), 0xffff);
> +
> +	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> +	i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
> +	for_each_pipe(pipe)
> +		i915_enable_pipestat(dev_priv, pipe, pipestat_enable);
> +	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> +
> +	I915_WRITE(VLV_IIR, 0xffffffff);
> +	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
> +	I915_WRITE(VLV_IER, enable_mask);
> +
> +	gen8_gt_irq_postinstall(dev_priv);
> +
> +	I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
> +	POSTING_READ(GEN8_MASTER_IRQ);
> +
> +	return 0;
> +}
> +
>  static void gen8_irq_uninstall(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -3397,6 +3585,57 @@ static void valleyview_irq_uninstall(struct drm_device *dev)
>  	POSTING_READ(VLV_IER);
>  }
>  
> +static void cherryview_irq_uninstall(struct drm_device *dev)
> +{
> +	drm_i915_private_t *dev_priv = dev->dev_private;
> +	int pipe;
> +
> +	if (!dev_priv)
> +		return;
> +
> +	I915_WRITE(GEN8_MASTER_IRQ, 0);
> +	POSTING_READ(GEN8_MASTER_IRQ);
> +
> +#define GEN8_IRQ_FINI_NDX(type, which)				\
> +do {								\
> +	I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff);	\
> +	I915_WRITE(GEN8_##type##_IER(which), 0);		\
> +	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff);	\
> +	POSTING_READ(GEN8_##type##_IIR(which));			\
> +	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff);	\
> +} while (0)
> +
> +#define GEN8_IRQ_FINI(type)				\
> +do {							\
> +	I915_WRITE(GEN8_##type##_IMR, 0xffffffff);	\
> +	I915_WRITE(GEN8_##type##_IER, 0);		\
> +	I915_WRITE(GEN8_##type##_IIR, 0xffffffff);	\
> +	POSTING_READ(GEN8_##type##_IIR);		\
> +	I915_WRITE(GEN8_##type##_IIR, 0xffffffff);	\
> +} while (0)
> +
> +	GEN8_IRQ_FINI_NDX(GT, 0);
> +	GEN8_IRQ_FINI_NDX(GT, 1);
> +	GEN8_IRQ_FINI_NDX(GT, 2);
> +	GEN8_IRQ_FINI_NDX(GT, 3);
> +
> +	GEN8_IRQ_FINI(PCU);
> +
> +#undef GEN8_IRQ_FINI
> +#undef GEN8_IRQ_FINI_NDX
> +
> +	I915_WRITE(PORT_HOTPLUG_EN, 0);
> +	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
> +
> +	for_each_pipe(pipe)
> +		I915_WRITE(PIPESTAT(pipe), 0xffff);
> +
> +	I915_WRITE(VLV_IMR, 0xffffffff);
> +	I915_WRITE(VLV_IER, 0x0);
> +	I915_WRITE(VLV_IIR, 0xffffffff);
> +	POSTING_READ(VLV_IIR);
> +}
> +
>  static void ironlake_irq_uninstall(struct drm_device *dev)
>  {
>  	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
> @@ -4119,7 +4358,15 @@ void intel_irq_init(struct drm_device *dev)
>  		dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
>  	}
>  
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_CHERRYVIEW(dev)) {
> +		dev->driver->irq_handler = cherryview_irq_handler;
> +		dev->driver->irq_preinstall = cherryview_irq_preinstall;
> +		dev->driver->irq_postinstall = cherryview_irq_postinstall;
> +		dev->driver->irq_uninstall = cherryview_irq_uninstall;
> +		dev->driver->enable_vblank = valleyview_enable_vblank;
> +		dev->driver->disable_vblank = valleyview_disable_vblank;
> +		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
> +	} else if (IS_VALLEYVIEW(dev)) {
>  		dev->driver->irq_handler = valleyview_irq_handler;
>  		dev->driver->irq_preinstall = valleyview_irq_preinstall;
>  		dev->driver->irq_postinstall = valleyview_irq_postinstall;
> -- 
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 27/71] drm/i915/chv: Enable Render Standby (RC6) for Cheeryview

[Imre Deak]

On Wed, 2014-04-09 at 13:28 +0300, ville.syrjala@linux.intel.com wrote:
> From: Deepak S <deepak.s@intel.com>
> 
> v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
> 
> Signed-off-by: Deepak S <deepak.s@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 101 ++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 98 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0889af7..909cc0a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3184,6 +3184,18 @@ static void gen6_disable_rps(struct drm_device *dev)
>  	gen6_disable_rps_interrupts(dev);
>  }
>  
> +static void cherryview_disable_rps(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	I915_WRITE(GEN6_RC_CONTROL, 0);
> +
> +	if (dev_priv->vlv_pctx) {
> +		drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
> +		dev_priv->vlv_pctx = NULL;
> +	}
> +}
> +
>  static void valleyview_disable_rps(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -3551,6 +3563,29 @@ int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
>  	return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
>  }
>  
> +static void cherryview_setup_pctx(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	unsigned long pctx_paddr;
> +	struct i915_gtt *gtt = &dev_priv->gtt;
> +	u32 pcbr;
> +	int pctx_size = 32*1024;
> +
> +	pcbr = I915_READ(VLV_PCBR);
> +	if (pcbr >> 12 == 0) {
> +		/*
> +		 * From the Gunit register HAS:
> +		 * The Gfx driver is expected to program this register and ensure
> +		 * proper allocation within Gfx stolen memory.  For example, this
> +		 * register should be programmed such than the PCBR range does not
> +		 * overlap with other relevant ranges.
> +		 */
> +		pctx_paddr = (dev_priv->mm.stolen_base + gtt->stolen_size - pctx_size);
> +		I915_WRITE(VLV_PCBR, pctx_paddr);
> +	}
> +}
> +
> +
>  static void valleyview_setup_pctx(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -3595,6 +3630,61 @@ out:
>  	dev_priv->vlv_pctx = pctx;
>  }
>  
> +static void cherryview_enable_rps(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_ring_buffer *ring;
> +	u32 gtfifodbg, rc6_mode = 0, pcbr;
> +	int i;
> +
> +	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> +
> +	if ((gtfifodbg = I915_READ(GTFIFODBG))) {
> +		DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
> +				 gtfifodbg);
> +		I915_WRITE(GTFIFODBG, gtfifodbg);
> +	}
> +
> +	cherryview_setup_pctx(dev);

The pctx setup/cleanup for VLV was moved to driver init/cleanup time
recently, probably you want the same for CHV too.

--Imre

> +
> +	/* 1a & 1b: Get forcewake during program sequence. Although the driver
> +	 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
> +	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
> +
> +	/* 2a: Program RC6 thresholds.*/
> +	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
> +	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
> +	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> +
> +	for_each_ring(ring, dev_priv, i)
> +		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
> +
> +	I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
> +
> +	/* allows RC6 residency counter to work */
> +	I915_WRITE(VLV_COUNTER_CONTROL,
> +		   _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
> +				      VLV_MEDIA_RC6_COUNT_EN |
> +				      VLV_RENDER_RC6_COUNT_EN));
> +
> +	/* Todo: If BIOS has not configured PCBR
> +	 *       then allocate in BIOS Reserved */
> +
> +	/* For now we assume BIOS is allocating and populating the PCBR  */
> +	pcbr = I915_READ(VLV_PCBR);
> +
> +	DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
> +
> +	/* 3: Enable RC6 */
> +	if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE & (pcbr >> 12))
> +		rc6_mode = GEN6_RC_CTL_EI_MODE(1) | VLV_RC_CTL_CTX_RST_PARALLEL;
> +
> +	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
> +
> +	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
> +}
> +
> +
>  static void valleyview_enable_rps(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -4437,7 +4527,9 @@ void intel_disable_gt_powersave(struct drm_device *dev)
>  		cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
>  		cancel_work_sync(&dev_priv->rps.work);
>  		mutex_lock(&dev_priv->rps.hw_lock);
> -		if (IS_VALLEYVIEW(dev))
> +		if (IS_CHERRYVIEW(dev))
> +			cherryview_disable_rps(dev);
> +		else if (IS_VALLEYVIEW(dev))
>  			valleyview_disable_rps(dev);
>  		else
>  			gen6_disable_rps(dev);
> @@ -4455,7 +4547,9 @@ static void intel_gen6_powersave_work(struct work_struct *work)
>  
>  	mutex_lock(&dev_priv->rps.hw_lock);
>  
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_CHERRYVIEW(dev)) {
> +		cherryview_enable_rps(dev);
> +	} else if (IS_VALLEYVIEW(dev)) {
>  		valleyview_enable_rps(dev);
>  	} else if (IS_BROADWELL(dev)) {
>  		gen8_enable_rps(dev);
> @@ -4476,7 +4570,7 @@ void intel_enable_gt_powersave(struct drm_device *dev)
>  		ironlake_enable_drps(dev);
>  		ironlake_enable_rc6(dev);
>  		intel_init_emon(dev);
> -	} else if (IS_GEN6(dev) || IS_GEN7(dev)) {
> +	} else if (INTEL_INFO(dev)->gen >= 6) {
>  		if (IS_VALLEYVIEW(dev))
>  			valleyview_setup_pctx(dev);
>  		/*
> @@ -5051,6 +5145,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>  		dev_priv->mem_freq = 1333;
>  		break;
>  	}
> +
>  	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
>  
>  	dev_priv->vlv_cdclk_freq = valleyview_cur_cdclk(dev_priv);

Re: [PATCH 25/71] drm/i915/chv: CHV doesn't have CRT output

[Daniel Vetter]

On Wed, Apr 09, 2014 at 01:28:23PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> No CRT output on CHV, so don't call intel_crt_init().
> 
> v2: Don't disable CRT on HAS.
> 
> FIXME: Split out the is_simulator check again, we need it for now to keep HAS
> going.

Fixme can be dropped, this is something I need to sort out when rebasing
internal.
-Daniel

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1)
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 266d8fe..9b65a04 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10989,7 +10989,7 @@ static void intel_setup_outputs(struct drm_device *dev)
>  
>  	intel_lvds_init(dev);
>  
> -	if (!IS_ULT(dev))
> +	if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev))
>  		intel_crt_init(dev);
>  
>  	if (HAS_DDI(dev)) {
> -- 
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 26/71] drm/i915: Enable PM Interrupts for CHV/BDW Platform.

[Daniel Vetter]

On Wed, Apr 09, 2014 at 01:28:24PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Deepak S <deepak.s@intel.com>
> 
> v2: Remove vfuncs and add if else block to differentiate platform
> (Daniel)
> 
> Signed-off-by: Deepak S <deepak.s@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 49 +++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 47 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 1581b3d..6cf97c4 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -37,6 +37,9 @@
>  #include "i915_trace.h"
>  #include "intel_drv.h"
>  
> +
> +static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
> +
>  static const u32 hpd_ibx[] = {
>  	[HPD_CRT] = SDE_CRT_HOTPLUG,
>  	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
> @@ -154,6 +157,32 @@ void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
>  }
>  
>  /**
> + * gen8_update_pm_irq - update GEN8_GT_IMR
> + * @dev_priv: driver private
> + * @interrupt_mask: mask of interrupt bits to update
> + * @enabled_irq_mask: mask of interrupt bits to enable
> + * */
> +
> +static void gen8_update_pm_irq(struct drm_i915_private *dev_priv,
> +					uint32_t interrupt_mask,
> +					uint32_t enabled_irq_mask)
> +{
> +	uint32_t new_val;
> +
> +	assert_spin_locked(&dev_priv->irq_lock);
> +
> +	new_val = dev_priv->pm_irq_mask;
> +	new_val &= ~interrupt_mask;
> +	new_val |= (~enabled_irq_mask & interrupt_mask);
> +
> +	if (new_val != dev_priv->pm_irq_mask) {
> +		dev_priv->pm_irq_mask = new_val;
> +		I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask);
> +		POSTING_READ(GEN8_GT_IMR(2));
> +	}
> +}
> +
> +/**
>    * snb_update_pm_irq - update GEN6_PMIMR
>    * @dev_priv: driver private
>    * @interrupt_mask: mask of interrupt bits to update
> @@ -188,12 +217,18 @@ static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
>  
>  void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
>  {
> -	snb_update_pm_irq(dev_priv, mask, mask);
> +	if (IS_GEN8(dev_priv->dev))
> +		gen8_update_pm_irq(dev_priv, mask, mask);
> +	else
> +		snb_update_pm_irq(dev_priv, mask, mask);
>  }
>  
>  void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
>  {
> -	snb_update_pm_irq(dev_priv, mask, 0);
> +	if (IS_GEN8(dev_priv->dev))
> +		gen8_update_pm_irq(dev_priv, mask, 0);
> +	else
> +		snb_update_pm_irq(dev_priv, mask, 0);
>  }
>  
>  static bool ivb_can_enable_err_int(struct drm_device *dev)
> @@ -1341,6 +1376,9 @@ static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
>  	u32 rcs, bcs, vcs;
>  	uint32_t tmp = 0;
>  	irqreturn_t ret = IRQ_NONE;
> +	u32 pm_iir;
> +
> +	pm_iir = I915_READ(GEN8_GT_IIR(2));
>  
>  	if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
>  		tmp = I915_READ(GEN8_GT_IIR(0));
> @@ -1381,6 +1419,12 @@ static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
>  			DRM_ERROR("The master control interrupt lied (GT3)!\n");
>  	}
>  
> +
> +	if (pm_iir)
> +		gen6_rps_irq_handler(dev_priv, pm_iir);
> +
> +	I915_WRITE(GEN8_GT_IIR(2), pm_iir);
> +
>  	return ret;
>  }
>  
> @@ -1796,6 +1840,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
>  		ret = IRQ_HANDLED;
>  	}
>  
> +
>  	I915_WRITE(VLV_IIR, iir);
>  
>  	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);

Spurious hunk.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 33/71] drm/i915/chv: Fix for verifying PCBR address field.

[Daniel Vetter]

On Wed, Apr 09, 2014 at 01:28:31PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Deepak S <deepak.s@intel.com>
> 
> This was fumbled in PCBR condition check during CHV RC6 Enable flag set
> 
> Issue introduced in
> 
> commit cb26b06c20094d69bcba191738960d053ac2c645
> Author: Deepak S <deepak.s@intel.com>
> Date:   Mon Dec 16 12:16:53 2013 +0530
> Subject: drm/i915/chv: Enable Render Standby (RC6) for Cheeryview

Squash into relevant patch earlier in the series?
-Daniel

> 
> v2: Commit message change (Jani)
> 
> v3: Mention the subject and author of the patch which introduced
> the bug (Daniel)
> 
> v4: Use VLV_PCBR_ADDR_SHIFT instead of MASK (Jani)
> 
> v5: Commit message change. Add subject of the patch which introduced
> the bug (Ville)
> 
> Signed-off-by: Deepak S <deepak.s@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 1 +
>  drivers/gpu/drm/i915/intel_pm.c | 5 +++--
>  2 files changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e67b4a6..ac5047b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5294,6 +5294,7 @@ enum punit_power_well {
>  #define GEN6_GT_GFX_RC6				0x138108
>  #define GEN6_GT_GFX_RC6p			0x13810C
>  #define GEN6_GT_GFX_RC6pp			0x138110
> +#define VLV_PCBR_ADDR_SHIFT			12
>  
>  #define GEN6_PCODE_MAILBOX			0x138124
>  #define   GEN6_PCODE_READY			(1<<31)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index fb533a3..acaa1cf 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3657,7 +3657,7 @@ static void cherryview_setup_pctx(struct drm_device *dev)
>  	int pctx_size = 32*1024;
>  
>  	pcbr = I915_READ(VLV_PCBR);
> -	if (pcbr >> 12 == 0) {
> +	if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
>  		/*
>  		 * From the Gunit register HAS:
>  		 * The Gfx driver is expected to program this register and ensure
> @@ -3761,7 +3761,8 @@ static void cherryview_enable_rps(struct drm_device *dev)
>  	DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
>  
>  	/* 3: Enable RC6 */
> -	if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE & (pcbr >> 12))
> +	if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
> +						(pcbr >> VLV_PCBR_ADDR_SHIFT))
>  		rc6_mode = GEN6_RC_CTL_EI_MODE(1) | VLV_RC_CTL_CTX_RST_PARALLEL;
>  
>  	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
> -- 
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 44/71] drm/i915/chv: Fix for decrementing fw count in chv read/write.

[Daniel Vetter]

On Wed, Apr 09, 2014 at 01:28:42PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Deepak S <deepak.s@intel.com>
> 
> This was fumbled in chv specific forcewake count during mmio reg read/write.
> 
> Issue introduced in
> 
> commit 95cf8b69f647322048929baffa8c7865aa6df2ad
> Author: Deepak S <deepak.s@intel.com>
> Date:   Mon Dec 16 12:16:54 2013 +0530
> Subject: drm/i915/chv: Added CHV specific register read and write

Again please squash in as a fixup.
-Daniel

> 
> Signed-off-by: Deepak S <deepak.s@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 8e3c686..ccad770 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -638,12 +638,12 @@ chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
>  	} \
>  	val = __raw_i915_read##x(dev_priv, reg); \
>  	if (FORCEWAKE_RENDER & fwengine) { \
> -		if (dev_priv->uncore.fw_rendercount++ == 0) \
> +		if (--dev_priv->uncore.fw_rendercount == 0) \
>  			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
>  								fwengine); \
>  	} \
>  	if (FORCEWAKE_MEDIA & fwengine) { \
> -		if (dev_priv->uncore.fw_mediacount++ == 0) \
> +		if (--dev_priv->uncore.fw_mediacount == 0) \
>  			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
>  								fwengine); \
>  	} \
> @@ -803,12 +803,12 @@ chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace)
>  	} \
>  	__raw_i915_write##x(dev_priv, reg, val); \
>  	if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \
> -			if (dev_priv->uncore.fw_rendercount++ == 0) \
> +			if (--dev_priv->uncore.fw_rendercount == 0) \
>  				(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
>  									fwengine); \
>  	} \
>  	if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \
> -		if (dev_priv->uncore.fw_mediacount++ == 0) \
> +		if (--dev_priv->uncore.fw_mediacount == 0) \
>  			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
>  								fwengine); \
>  	} \
> -- 
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 48/71] drm/i915/chv: Add plane C support

[Daniel Vetter]

On Wed, Apr 09, 2014 at 01:28:46PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Rafael Barbalho <rafael.barbalho@intel.com>
> 
> The i9xx_update_plane function was rejecting plane C when it is now a
> valid plane.
> 
> Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
> [vsyrjala: Use PLANE_C instead of the number 2]
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

We've just recently nuked this, it's a remnant from the sarea update code.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_display.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9b65a04..51d9079 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2351,6 +2351,7 @@ static int i9xx_update_primary_plane(struct drm_crtc *crtc,
>  	switch (plane) {
>  	case PLANE_A:
>  	case PLANE_B:
> +	case PLANE_C:
>  		break;
>  	default:
>  		DRM_ERROR("Can't update plane %c\n", plane_name(plane));
> -- 
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 45/71] drm/i915/chv: Streamline CHV forcewake stuff

[Daniel Vetter]

On Wed, Apr 09, 2014 at 01:28:43PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Streamline the CHV forcewake functions just like was done for VLV.
> 
> This will also fix a bug in accessing the common well registers,
> where we'd end up trying to wake up the wells too many times
> since we'd call force_wake_get/put twice per register access, with
> FORCEFAKE_ALL both times.
> 
> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Ugh ... any chance this would make sense squashed in as a fixup into an
earlier patch? If it's too hairy I'm ok with this as-is.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 88 ++++++++++++++-----------------------
>  1 file changed, 32 insertions(+), 56 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index ccad770..59293b3 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -618,35 +618,22 @@ chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
>  	unsigned fwengine = 0; \
>  	REG_READ_HEADER(x); \
>  	if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
> -		fwengine = FORCEWAKE_RENDER; \
> -	} \
> -	else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
> -		fwengine = FORCEWAKE_MEDIA; \
> -	} \
> -	else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
> -		fwengine = FORCEWAKE_ALL; \
> -	} \
> -	if (FORCEWAKE_RENDER & fwengine) { \
> -		if (dev_priv->uncore.fw_rendercount++ == 0) \
> -			(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
> -								fwengine); \
> -	} \
> -	if (FORCEWAKE_MEDIA & fwengine) { \
> -		if (dev_priv->uncore.fw_mediacount++ == 0) \
> -			(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
> -								fwengine); \
> +		if (dev_priv->uncore.fw_rendercount == 0) \
> +			fwengine = FORCEWAKE_RENDER; \
> +	} else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
> +		if (dev_priv->uncore.fw_mediacount == 0) \
> +			fwengine = FORCEWAKE_MEDIA; \
> +	} else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
> +		if (dev_priv->uncore.fw_rendercount == 0) \
> +			fwengine |= FORCEWAKE_RENDER; \
> +		if (dev_priv->uncore.fw_mediacount == 0) \
> +			fwengine |= FORCEWAKE_MEDIA; \
>  	} \
> +	if (fwengine) \
> +		dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
>  	val = __raw_i915_read##x(dev_priv, reg); \
> -	if (FORCEWAKE_RENDER & fwengine) { \
> -		if (--dev_priv->uncore.fw_rendercount == 0) \
> -			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
> -								fwengine); \
> -	} \
> -	if (FORCEWAKE_MEDIA & fwengine) { \
> -		if (--dev_priv->uncore.fw_mediacount == 0) \
> -			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
> -								fwengine); \
> -	} \
> +	if (fwengine) \
> +		dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
>  	REG_READ_FOOTER; \
>  }
>  
> @@ -780,38 +767,27 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
>  static void \
>  chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
>  	unsigned fwengine = 0; \
> -	bool __needs_put = !is_gen8_shadowed(dev_priv, reg); \
> +	bool shadowed = is_gen8_shadowed(dev_priv, reg); \
>  	REG_WRITE_HEADER; \
> -	if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
> -		fwengine = FORCEWAKE_RENDER; \
> -	} \
> -	else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
> -		fwengine = FORCEWAKE_MEDIA; \
> -	} \
> -	else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
> -		fwengine = FORCEWAKE_ALL; \
> -	} \
> -	if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \
> -			if (dev_priv->uncore.fw_rendercount++ == 0) \
> -				(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
> -									fwengine); \
> -	} \
> -	if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \
> -		if (dev_priv->uncore.fw_mediacount++ == 0) \
> -			(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
> -								fwengine); \
> +	if (!shadowed) { \
> +		if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
> +			if (dev_priv->uncore.fw_rendercount == 0) \
> +				fwengine = FORCEWAKE_RENDER; \
> +		} else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
> +			if (dev_priv->uncore.fw_mediacount == 0) \
> +				fwengine = FORCEWAKE_MEDIA; \
> +		} else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
> +			if (dev_priv->uncore.fw_rendercount == 0) \
> +				fwengine |= FORCEWAKE_RENDER; \
> +			if (dev_priv->uncore.fw_mediacount == 0) \
> +				fwengine |= FORCEWAKE_MEDIA; \
> +		} \
>  	} \
> +	if (fwengine) \
> +		dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
>  	__raw_i915_write##x(dev_priv, reg, val); \
> -	if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \
> -			if (--dev_priv->uncore.fw_rendercount == 0) \
> -				(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
> -									fwengine); \
> -	} \
> -	if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \
> -		if (--dev_priv->uncore.fw_mediacount == 0) \
> -			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
> -								fwengine); \
> -	} \
> +	if (fwengine) \
> +		dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
>  	REG_WRITE_FOOTER; \
>  }
>  
> -- 
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 52/71] drm/i915/chv: Make CHV irq handler loop until all interrupts are consumed

[Daniel Vetter]

On Wed, Apr 09, 2014 at 01:28:50PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Really, this is what the hw guys tell us to do? I mean we've never had a
gmch based platform which didn't need this, but I've thought with all the
gen8 irq restructuring they'd finally fix this ...

/me cries

Cheers, Daniel

> ---
>  drivers/gpu/drm/i915/i915_irq.c | 29 ++++++++++++++---------------
>  1 file changed, 14 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 9702fde..fc9b7e6 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1775,30 +1775,29 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
>  	u32 master_ctl, iir;
>  	irqreturn_t ret = IRQ_NONE;
>  
> -	master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~DE_MASTER_IRQ_CONTROL;
> -	iir = I915_READ(VLV_IIR);
> +	for (;;) {
> +		master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
> +		iir = I915_READ(VLV_IIR);
>  
> -	if (master_ctl == 0 && iir == 0)
> -		return IRQ_NONE;
> +		if (master_ctl == 0 && iir == 0)
> +			break;
>  
> -	I915_WRITE(GEN8_MASTER_IRQ, 0);
> +		I915_WRITE(GEN8_MASTER_IRQ, 0);
>  
> -	gen8_gt_irq_handler(dev, dev_priv, master_ctl);
> +		gen8_gt_irq_handler(dev, dev_priv, master_ctl);
>  
> -	valleyview_pipestat_irq_handler(dev, iir);
> +		valleyview_pipestat_irq_handler(dev, iir);
>  
> -	/* Consume port.  Then clear IIR or we'll miss events */
> -	if (iir & I915_DISPLAY_PORT_INTERRUPT) {
> +		/* Consume port.  Then clear IIR or we'll miss events */
>  		i9xx_hpd_irq_handler(dev, iir);
> -		ret = IRQ_HANDLED;
> -	}
>  
> -	I915_WRITE(VLV_IIR, iir);
> +		I915_WRITE(VLV_IIR, iir);
>  
> -	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
> -	POSTING_READ(GEN8_MASTER_IRQ);
> +		I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
> +		POSTING_READ(GEN8_MASTER_IRQ);
>  
> -	ret = IRQ_HANDLED;
> +		ret = IRQ_HANDLED;
> +	}
>  
>  	return ret;
>  }
> -- 
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 53/71] drm/i915/chv: Configure crtc_mask correctly for CHV

[Daniel Vetter]

On Wed, Apr 09, 2014 at 01:28:51PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> On CHV pipe C can driver only port D, and pipes A and B can drivbe only
> ports B and C. Configure the crtc_mask appropriately to reflect that.

I'm impressed ;-)

But well, hooray for the resurrection of arbitrary pipe limits. I'll crank
up fixing the gen2/3 bug in igt_kms a few notches now since suddenly it's
relevant again ...

Cheers, Daniel
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c   | 8 +++++++-
>  drivers/gpu/drm/i915/intel_hdmi.c | 8 +++++++-
>  2 files changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 21ac845..6ae4d28 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4070,7 +4070,13 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
>  	intel_dig_port->dp.output_reg = output_reg;
>  
>  	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
> -	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
> +	if (IS_CHERRYVIEW(dev)) {
> +		if (port == PORT_D)
> +			intel_encoder->crtc_mask = 1 << 2;
> +		else
> +			intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
> +	} else
> +		intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
>  	intel_encoder->cloneable = 0;
>  	intel_encoder->hot_plug = intel_dp_hot_plug;
>  
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 9f868f4..349374b 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1426,7 +1426,13 @@ void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
>  	}
>  
>  	intel_encoder->type = INTEL_OUTPUT_HDMI;
> -	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
> +	if (IS_CHERRYVIEW(dev)) {
> +		if (port == PORT_D)
> +			intel_encoder->crtc_mask = 1 << 2;
> +		else
> +			intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
> +	} else
> +		intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
>  	intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
>  	/*
>  	 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
> -- 
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 64/71] drm/i915/chv: Don't use PCS group access reads

[Daniel Vetter]

On Wed, Apr 09, 2014 at 01:29:02PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> All PCS groups access reads return 0xffffffff, so we can't use group
> access for RMW cycles. Instead target each spline separately.

I have no idea what PCS means here and spline ... Can you please expand
for those who haven't yet lost their souls in chv docs? Just so we have a
commonly-understood jargon for talking about this stuff.

Thanks, Daniel

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h   | 14 ++++++++++++++
>  drivers/gpu/drm/i915/intel_dp.c   | 32 ++++++++++++++++++++++++--------
>  drivers/gpu/drm/i915/intel_hdmi.c | 34 +++++++++++++++++++++++++---------
>  3 files changed, 63 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4617fb3..ffed03e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -654,6 +654,13 @@ enum punit_power_well {
>  #define   DPIO_PCS_TX_LANE1_RESET	(1<<7)
>  #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
>  
> +#define _VLV_PCS01_DW0_CH0		0x200
> +#define _VLV_PCS23_DW0_CH0		0x400
> +#define _VLV_PCS01_DW0_CH1		0x2600
> +#define _VLV_PCS23_DW0_CH1		0x2800
> +#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
> +#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
> +
>  #define _VLV_PCS_DW1_CH0		0x8204
>  #define _VLV_PCS_DW1_CH1		0x8404
>  #define   CHV_PCS_REQ_SOFTRESET_EN	(1<<23)
> @@ -663,6 +670,13 @@ enum punit_power_well {
>  #define   DPIO_PCS_CLK_SOFT_RESET	(1<<5)
>  #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
>  
> +#define _VLV_PCS01_DW1_CH0		0x204
> +#define _VLV_PCS23_DW1_CH0		0x404
> +#define _VLV_PCS01_DW1_CH1		0x2604
> +#define _VLV_PCS23_DW1_CH1		0x2804
> +#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
> +#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
> +
>  #define _VLV_PCS_DW8_CH0		0x8220
>  #define _VLV_PCS_DW8_CH1		0x8420
>  #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 079e0e3..cc7bccd3 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1845,13 +1845,21 @@ static void chv_post_disable_dp(struct intel_encoder *encoder)
>  	mutex_lock(&dev_priv->dpio_lock);
>  
>  	/* Propagate soft reset to data lane reset */
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
>  	val |= CHV_PCS_REQ_SOFTRESET_EN;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
>  
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> +	val |= CHV_PCS_REQ_SOFTRESET_EN;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> +	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
>  	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
>  
>  	mutex_unlock(&dev_priv->dpio_lock);
>  }
> @@ -1983,13 +1991,21 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
>  	mutex_lock(&dev_priv->dpio_lock);
>  
>  	/* Deassert soft data lane reset*/
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
>  	val |= CHV_PCS_REQ_SOFTRESET_EN;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> +	val |= CHV_PCS_REQ_SOFTRESET_EN;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> +	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
>  
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
>  	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
>  
>  	/* Program Tx lane latency optimal setting*/
>  	for (i = 0; i < 4; i++) {
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 6a2152b..c3896b0 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1216,13 +1216,21 @@ static void chv_hdmi_post_disable(struct intel_encoder *encoder)
>  	mutex_lock(&dev_priv->dpio_lock);
>  
>  	/* Propagate soft reset to data lane reset */
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
>  	val |= CHV_PCS_REQ_SOFTRESET_EN;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val)
> -;
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> +	val |= CHV_PCS_REQ_SOFTRESET_EN;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> +	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
>  	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
>  
>  	mutex_unlock(&dev_priv->dpio_lock);
>  }
> @@ -1242,13 +1250,21 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
>  	mutex_lock(&dev_priv->dpio_lock);
>  
>  	/* Deassert soft data lane reset*/
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
>  	val |= CHV_PCS_REQ_SOFTRESET_EN;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> +	val |= CHV_PCS_REQ_SOFTRESET_EN;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> +	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
>  
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
>  	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
>  
>  	/* Program Tx latency optimal setting */
>  	for (i = 0; i < 4; i++) {
> -- 
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 66/71] drm/i915/chv: Use RMW to toggle swing calc init

[Daniel Vetter]

On Wed, Apr 09, 2014 at 01:29:04PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The spec only tells us to set individual bits here and there. So we use
> RMW for most things. Do the same for the swing calc init.
> 
> Eventually we should optimize things to just blast the final value in
> with group access whenever possible. But to do that someone needs to
> take a good look at what's the reset value for each registers, and
> possibly if the BIOS manages to frob with some of them. For now
> use RMW access always.

Usual sermon: I strongly suggest to do that transformation asap - we've
alwas gotten burned in really interesting ways when relying too much on
the implicit state in the hw registers ...
-Daniel
 
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h   |  7 +++++++
>  drivers/gpu/drm/i915/intel_dp.c   | 17 ++++++++++++++---
>  drivers/gpu/drm/i915/intel_hdmi.c | 18 ++++++++++++++----
>  3 files changed, 35 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b91232f..7056994 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -698,6 +698,13 @@ enum punit_power_well {
>  #define   DPIO_PCS_SWING_CALC_TX1_TX3	(1<<31)
>  #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
>  
> +#define _VLV_PCS01_DW10_CH0		0x0228
> +#define _VLV_PCS23_DW10_CH0		0x0428
> +#define _VLV_PCS01_DW10_CH1		0x2628
> +#define _VLV_PCS23_DW10_CH1		0x2828
> +#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
> +#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
> +
>  #define _VLV_PCS_DW11_CH0		0x822c
>  #define _VLV_PCS_DW11_CH1		0x842c
>  #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 4c54930..9cbd702 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2346,7 +2346,13 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
>  	mutex_lock(&dev_priv->dpio_lock);
>  
>  	/* Clear calc init */
> -	vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), 0);
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
> +	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
> +	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
>  
>  	/* Program swing deemph */
>  	for (i = 0; i < 4; i++) {
> @@ -2397,8 +2403,13 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
>  	}
>  
>  	/* Start swing calculation */
> -	vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch),
> -		(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3));
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
> +	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
> +	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
>  
>  	/* LRC Bypass */
>  	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index e912554..d2b1186 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1283,7 +1283,13 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
>  	/* FIXME: Fix up value only after power analysis */
>  
>  	/* Clear calc init */
> -	vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), 0);
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
> +	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
> +	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
>  
>  	/* FIXME: Program the support xxx V-dB */
>  	/* Use 800mV-0dB */
> @@ -1322,9 +1328,13 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
>  				(0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT));
>  #endif
>  	/* Start swing calculation */
> -	vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch),
> -			DPIO_PCS_SWING_CALC_TX0_TX2 |
> -			DPIO_PCS_SWING_CALC_TX1_TX3);
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
> +	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
> +	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
>  
>  	/* LRC Bypass */
>  	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
> -- 
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 00/71] drm/i915/chv: Add Cherryview support

[S, Deepak]

Thanks Ville. I agree patches need polishing :). I might rewrite some of 
the patches based on testing :)

Most of the BDW Rc6/Rps patches are in. I guess some of the interrupt 
related patch are pending.

Thanks
Deepak

On 4/9/2014 8:35 PM, Ville Syrjälä wrote:
> On Wed, Apr 09, 2014 at 02:30:52PM +0000, S, Deepak wrote:
>> Hi Ville,
>>
>> I am Ok with  cleaning up and pushing the Code. Can you please tell me when we need to start pushing the code and branch to use (drm-intel-next)?
>
> Well you can consider it pushed now that it's in the open. The patches
> just need a bit of extra polish I think. Well, unless you're planning
> a full blown rewrite of the code ;)
>
> I guess you need to take into consideration whatever bdw rc6/rps patches
> are still in flight, but since you've been doing some review there I
> think you have a better idea than I do how things are progressing.
>
> I always work on top of nightly, so I guess that's a good choice :)
>
>>
>> Thanks
>> Deepak
>>
>> -----Original Message-----
>> From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com]
>> Sent: Wednesday, April 9, 2014 6:55 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: S, Deepak; Deak, Imre
>> Subject: Re: [PATCH 00/71] drm/i915/chv: Add Cherryview support
>>
>> As you may have noticed some of this stuf may need a bit of work still to fit in better with the more recent upstream changes.
>>
>> So I think we need a few people to do some work here to the the patches into a really good shape. So some division of labor would in order. I'm proposing the following:
>> rc6/turbo -> Deepak as he's written the code anyway interrupts -> Imre since he worked on the VLV interrupts recently
>>
>> The rest of the patches should be fairly OK I think. So for the rest we probably just need reviews mostly, and maybe we want to squash some of the more trivial patches.
>>
>> --
>> Ville Syrjälä
>> Intel OTC
>

Re: [PATCH 52/71] drm/i915/chv: Make CHV irq handler loop until all interrupts are consumed

[Ville Syrjälä]

On Wed, Apr 09, 2014 at 06:05:01PM +0200, Daniel Vetter wrote:
> On Wed, Apr 09, 2014 at 01:28:50PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Really, this is what the hw guys tell us to do? I mean we've never had a
> gmch based platform which didn't need this, but I've thought with all the
> gen8 irq restructuring they'd finally fix this ...

This came from Rafael's observations. I was hoping re-enabling the
master interrupt bit would have retriggered the CPU interrupt if any
IIR bits were still high, but I guess that's not the case :(

> 
> /me cries
> 
> Cheers, Daniel
> 
> > ---
> >  drivers/gpu/drm/i915/i915_irq.c | 29 ++++++++++++++---------------
> >  1 file changed, 14 insertions(+), 15 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index 9702fde..fc9b7e6 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -1775,30 +1775,29 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
> >  	u32 master_ctl, iir;
> >  	irqreturn_t ret = IRQ_NONE;
> >  
> > -	master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~DE_MASTER_IRQ_CONTROL;
> > -	iir = I915_READ(VLV_IIR);
> > +	for (;;) {
> > +		master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
> > +		iir = I915_READ(VLV_IIR);
> >  
> > -	if (master_ctl == 0 && iir == 0)
> > -		return IRQ_NONE;
> > +		if (master_ctl == 0 && iir == 0)
> > +			break;
> >  
> > -	I915_WRITE(GEN8_MASTER_IRQ, 0);
> > +		I915_WRITE(GEN8_MASTER_IRQ, 0);
> >  
> > -	gen8_gt_irq_handler(dev, dev_priv, master_ctl);
> > +		gen8_gt_irq_handler(dev, dev_priv, master_ctl);
> >  
> > -	valleyview_pipestat_irq_handler(dev, iir);
> > +		valleyview_pipestat_irq_handler(dev, iir);
> >  
> > -	/* Consume port.  Then clear IIR or we'll miss events */
> > -	if (iir & I915_DISPLAY_PORT_INTERRUPT) {
> > +		/* Consume port.  Then clear IIR or we'll miss events */
> >  		i9xx_hpd_irq_handler(dev, iir);
> > -		ret = IRQ_HANDLED;
> > -	}
> >  
> > -	I915_WRITE(VLV_IIR, iir);
> > +		I915_WRITE(VLV_IIR, iir);
> >  
> > -	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
> > -	POSTING_READ(GEN8_MASTER_IRQ);
> > +		I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
> > +		POSTING_READ(GEN8_MASTER_IRQ);
> >  
> > -	ret = IRQ_HANDLED;
> > +		ret = IRQ_HANDLED;
> > +	}
> >  
> >  	return ret;
> >  }
> > -- 
> > 1.8.3.2
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 00/71] drm/i915/chv: Add Cherryview support

[Daniel Vetter]

On Wed, Apr 09, 2014 at 06:05:27PM +0300, Ville Syrjälä wrote:
> On Wed, Apr 09, 2014 at 02:30:52PM +0000, S, Deepak wrote:
> > Hi Ville,
> > 
> > I am Ok with  cleaning up and pushing the Code. Can you please tell me
> > when we need to start pushing the code and branch to use
> > (drm-intel-next)?
> 
> Well you can consider it pushed now that it's in the open. The patches
> just need a bit of extra polish I think. Well, unless you're planning
> a full blown rewrite of the code ;)
> 
> I guess you need to take into consideration whatever bdw rc6/rps patches
> are still in flight, but since you've been doing some review there I
> think you have a better idea than I do how things are progressing.
> 
> I always work on top of nightly, so I guess that's a good choice :)

Yes, -nightly is always the recommended branch to base upstream patches
on. I'll sort out the conflict mess (or well, try to) if it doesn't apply
to plain dinq or some other branch. drm-intel-next tends to be too
outdated ;-)
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 64/71] drm/i915/chv: Don't use PCS group access reads

[Ville Syrjälä]

On Wed, Apr 09, 2014 at 06:18:38PM +0200, Daniel Vetter wrote:
> On Wed, Apr 09, 2014 at 01:29:02PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > All PCS groups access reads return 0xffffffff, so we can't use group
> > access for RMW cycles. Instead target each spline separately.
> 
> I have no idea what PCS means here and spline ... Can you please expand
> for those who haven't yet lost their souls in chv docs? Just so we have a
> commonly-understood jargon for talking about this stuff.

I guess we should have that somewhere as a comment. The same terminology
applies to VLV as well.

> 
> Thanks, Daniel
> 
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h   | 14 ++++++++++++++
> >  drivers/gpu/drm/i915/intel_dp.c   | 32 ++++++++++++++++++++++++--------
> >  drivers/gpu/drm/i915/intel_hdmi.c | 34 +++++++++++++++++++++++++---------
> >  3 files changed, 63 insertions(+), 17 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 4617fb3..ffed03e 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -654,6 +654,13 @@ enum punit_power_well {
> >  #define   DPIO_PCS_TX_LANE1_RESET	(1<<7)
> >  #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
> >  
> > +#define _VLV_PCS01_DW0_CH0		0x200
> > +#define _VLV_PCS23_DW0_CH0		0x400
> > +#define _VLV_PCS01_DW0_CH1		0x2600
> > +#define _VLV_PCS23_DW0_CH1		0x2800
> > +#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
> > +#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
> > +
> >  #define _VLV_PCS_DW1_CH0		0x8204
> >  #define _VLV_PCS_DW1_CH1		0x8404
> >  #define   CHV_PCS_REQ_SOFTRESET_EN	(1<<23)
> > @@ -663,6 +670,13 @@ enum punit_power_well {
> >  #define   DPIO_PCS_CLK_SOFT_RESET	(1<<5)
> >  #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
> >  
> > +#define _VLV_PCS01_DW1_CH0		0x204
> > +#define _VLV_PCS23_DW1_CH0		0x404
> > +#define _VLV_PCS01_DW1_CH1		0x2604
> > +#define _VLV_PCS23_DW1_CH1		0x2804
> > +#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
> > +#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
> > +
> >  #define _VLV_PCS_DW8_CH0		0x8220
> >  #define _VLV_PCS_DW8_CH1		0x8420
> >  #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 079e0e3..cc7bccd3 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1845,13 +1845,21 @@ static void chv_post_disable_dp(struct intel_encoder *encoder)
> >  	mutex_lock(&dev_priv->dpio_lock);
> >  
> >  	/* Propagate soft reset to data lane reset */
> > -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
> >  	val |= CHV_PCS_REQ_SOFTRESET_EN;
> > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
> >  
> > -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> > +	val |= CHV_PCS_REQ_SOFTRESET_EN;
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
> > +
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> > +	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
> > +
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> >  	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
> >  
> >  	mutex_unlock(&dev_priv->dpio_lock);
> >  }
> > @@ -1983,13 +1991,21 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
> >  	mutex_lock(&dev_priv->dpio_lock);
> >  
> >  	/* Deassert soft data lane reset*/
> > -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
> >  	val |= CHV_PCS_REQ_SOFTRESET_EN;
> > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
> > +
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> > +	val |= CHV_PCS_REQ_SOFTRESET_EN;
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
> > +
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> > +	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
> >  
> > -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> >  	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
> >  
> >  	/* Program Tx lane latency optimal setting*/
> >  	for (i = 0; i < 4; i++) {
> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> > index 6a2152b..c3896b0 100644
> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > @@ -1216,13 +1216,21 @@ static void chv_hdmi_post_disable(struct intel_encoder *encoder)
> >  	mutex_lock(&dev_priv->dpio_lock);
> >  
> >  	/* Propagate soft reset to data lane reset */
> > -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
> >  	val |= CHV_PCS_REQ_SOFTRESET_EN;
> > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val)
> > -;
> > -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
> > +
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> > +	val |= CHV_PCS_REQ_SOFTRESET_EN;
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
> > +
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> > +	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
> > +
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> >  	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
> >  
> >  	mutex_unlock(&dev_priv->dpio_lock);
> >  }
> > @@ -1242,13 +1250,21 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
> >  	mutex_lock(&dev_priv->dpio_lock);
> >  
> >  	/* Deassert soft data lane reset*/
> > -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
> >  	val |= CHV_PCS_REQ_SOFTRESET_EN;
> > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
> > +
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> > +	val |= CHV_PCS_REQ_SOFTRESET_EN;
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
> > +
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> > +	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
> >  
> > -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> >  	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
> >  
> >  	/* Program Tx latency optimal setting */
> >  	for (i = 0; i < 4; i++) {
> > -- 
> > 1.8.3.2
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel OTC

[PATCH v9 10/71] drm/i915/chv: Preliminary interrupt support for Cherryview

[ville.syrjala]

From: Daniel Vetter <daniel.vetter@ffwll.ch>

CHV has the Gen8 master interrupt register, as well as Gen8
GT/PCU interrupt registers.

The display block is based on VLV, with the main difference
of adding pipe C.

FIXME: Lot of this is copy pasted from either VLV or BDW. We should
probably refactor a bit to share the code better.

v2: Rewrite the order of operations to make more sense
    Don't bail out if MASTER_CTL register doesn't show an interrupt,
    as display interrupts aren't reported there.

v3: Rebase on top of Egbert Eich's hpd irq handling rework by using
the relevant port hotplug logic like for vlv.

v4: Rebase on top of Ben's gt irq #define refactoring.

v5: Squash in gen8_gt_irq_handler refactoring from Zhao Yakui
<yakui.zhao@intel.com>

v6: Adapt to upstream changes, dev_priv->irq_received is gone.

v7: Enable 3 the commented-out 3 pipe support.

v8: Rebase on top of Paulo's irq setup rework, use the renamed macros from
upstream.

v9: Grab irq_lock around i915_enable_pipestat()

FIXME: There's probably some potential for more shared code between bdw and chv.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v2)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_irq.c | 225 +++++++++++++++++++++++++++++++++++++++-
 1 file changed, 224 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7a4d3ae..475089e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1705,6 +1705,95 @@ out:
 	return ret;
 }
 
+static irqreturn_t cherryview_irq_handler(int irq, void *arg)
+{
+	struct drm_device *dev = (struct drm_device *) arg;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 master_ctl, iir;
+	irqreturn_t ret = IRQ_NONE;
+	unsigned int pipes = 0;
+
+	master_ctl = I915_READ(GEN8_MASTER_IRQ);
+
+	I915_WRITE(GEN8_MASTER_IRQ, 0);
+
+	ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
+
+	iir = I915_READ(VLV_IIR);
+
+	if (iir & (I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT))
+		pipes |= 1 << 0;
+	if (iir & (I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT))
+		pipes |= 1 << 1;
+	if (iir & (I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT | I915_DISPLAY_PIPE_C_EVENT_INTERRUPT))
+		pipes |= 1 << 2;
+
+	if (pipes) {
+		u32 pipe_stats[I915_MAX_PIPES] = {};
+		unsigned long irqflags;
+		int pipe;
+
+		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+		for_each_pipe(pipe) {
+			unsigned int reg;
+
+			if (!(pipes & (1 << pipe)))
+				continue;
+
+			reg = PIPESTAT(pipe);
+			pipe_stats[pipe] = I915_READ(reg);
+
+			/*
+			 * Clear the PIPE*STAT regs before the IIR
+			 */
+			if (pipe_stats[pipe] & 0x8000ffff) {
+				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
+					DRM_DEBUG_DRIVER("pipe %c underrun\n",
+							 pipe_name(pipe));
+				I915_WRITE(reg, pipe_stats[pipe]);
+			}
+		}
+		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+
+		for_each_pipe(pipe) {
+			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
+				drm_handle_vblank(dev, pipe);
+
+			if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
+				intel_prepare_page_flip(dev, pipe);
+				intel_finish_page_flip(dev, pipe);
+			}
+		}
+
+		if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
+			gmbus_irq_handler(dev);
+
+		ret = IRQ_HANDLED;
+	}
+
+	/* Consume port.  Then clear IIR or we'll miss events */
+	if (iir & I915_DISPLAY_PORT_INTERRUPT) {
+		u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
+
+		I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
+
+		DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
+				 hotplug_status);
+		if (hotplug_status & HOTPLUG_INT_STATUS_I915)
+			queue_work(dev_priv->wq,
+				   &dev_priv->hotplug_work);
+
+		ret = IRQ_HANDLED;
+	}
+
+	I915_WRITE(VLV_IIR, iir);
+
+	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
+	POSTING_READ(GEN8_MASTER_IRQ);
+
+	return ret;
+}
+
 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2967,6 +3056,37 @@ static void gen8_irq_preinstall(struct drm_device *dev)
 	gen8_irq_reset(dev);
 }
 
+static void cherryview_irq_preinstall(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
+	int pipe;
+
+	I915_WRITE(GEN8_MASTER_IRQ, 0);
+	POSTING_READ(GEN8_MASTER_IRQ);
+
+	GEN8_IRQ_RESET_NDX(GT, 0);
+	GEN8_IRQ_RESET_NDX(GT, 1);
+	GEN8_IRQ_RESET_NDX(GT, 2);
+	GEN8_IRQ_RESET_NDX(GT, 3);
+
+	GEN5_IRQ_RESET(GEN8_PCU_);
+
+	POSTING_READ(GEN8_PCU_IIR);
+
+	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
+
+	I915_WRITE(PORT_HOTPLUG_EN, 0);
+	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
+
+	for_each_pipe(pipe)
+		I915_WRITE(PIPESTAT(pipe), 0xffff);
+
+	I915_WRITE(VLV_IMR, 0xffffffff);
+	I915_WRITE(VLV_IER, 0x0);
+	I915_WRITE(VLV_IIR, 0xffffffff);
+	POSTING_READ(VLV_IIR);
+}
+
 static void ibx_hpd_irq_setup(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3284,6 +3404,50 @@ static int gen8_irq_postinstall(struct drm_device *dev)
 	return 0;
 }
 
+static int cherryview_irq_postinstall(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
+		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
+		I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
+		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
+		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT |
+		I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
+		I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT;
+	u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
+	unsigned long irqflags;
+	int pipe;
+
+	/*
+	 * Leave vblank interrupts masked initially.  enable/disable will
+	 * toggle them based on usage.
+	 */
+	dev_priv->irq_mask = ~enable_mask |
+		I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
+		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT |
+		I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT;
+
+	for_each_pipe(pipe)
+		I915_WRITE(PIPESTAT(pipe), 0xffff);
+
+	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+	i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
+	for_each_pipe(pipe)
+		i915_enable_pipestat(dev_priv, pipe, pipestat_enable);
+	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+
+	I915_WRITE(VLV_IIR, 0xffffffff);
+	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
+	I915_WRITE(VLV_IER, enable_mask);
+
+	gen8_gt_irq_postinstall(dev_priv);
+
+	I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
+	POSTING_READ(GEN8_MASTER_IRQ);
+
+	return 0;
+}
+
 static void gen8_irq_uninstall(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3327,6 +3491,57 @@ static void valleyview_irq_uninstall(struct drm_device *dev)
 	POSTING_READ(VLV_IER);
 }
 
+static void cherryview_irq_uninstall(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int pipe;
+
+	if (!dev_priv)
+		return;
+
+	I915_WRITE(GEN8_MASTER_IRQ, 0);
+	POSTING_READ(GEN8_MASTER_IRQ);
+
+#define GEN8_IRQ_FINI_NDX(type, which)				\
+do {								\
+	I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff);	\
+	I915_WRITE(GEN8_##type##_IER(which), 0);		\
+	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff);	\
+	POSTING_READ(GEN8_##type##_IIR(which));			\
+	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff);	\
+} while (0)
+
+#define GEN8_IRQ_FINI(type)				\
+do {							\
+	I915_WRITE(GEN8_##type##_IMR, 0xffffffff);	\
+	I915_WRITE(GEN8_##type##_IER, 0);		\
+	I915_WRITE(GEN8_##type##_IIR, 0xffffffff);	\
+	POSTING_READ(GEN8_##type##_IIR);		\
+	I915_WRITE(GEN8_##type##_IIR, 0xffffffff);	\
+} while (0)
+
+	GEN8_IRQ_FINI_NDX(GT, 0);
+	GEN8_IRQ_FINI_NDX(GT, 1);
+	GEN8_IRQ_FINI_NDX(GT, 2);
+	GEN8_IRQ_FINI_NDX(GT, 3);
+
+	GEN8_IRQ_FINI(PCU);
+
+#undef GEN8_IRQ_FINI
+#undef GEN8_IRQ_FINI_NDX
+
+	I915_WRITE(PORT_HOTPLUG_EN, 0);
+	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
+
+	for_each_pipe(pipe)
+		I915_WRITE(PIPESTAT(pipe), 0xffff);
+
+	I915_WRITE(VLV_IMR, 0xffffffff);
+	I915_WRITE(VLV_IER, 0x0);
+	I915_WRITE(VLV_IIR, 0xffffffff);
+	POSTING_READ(VLV_IIR);
+}
+
 static void ironlake_irq_uninstall(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4032,7 +4247,15 @@ void intel_irq_init(struct drm_device *dev)
 		dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
 	}
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_CHERRYVIEW(dev)) {
+		dev->driver->irq_handler = cherryview_irq_handler;
+		dev->driver->irq_preinstall = cherryview_irq_preinstall;
+		dev->driver->irq_postinstall = cherryview_irq_postinstall;
+		dev->driver->irq_uninstall = cherryview_irq_uninstall;
+		dev->driver->enable_vblank = valleyview_enable_vblank;
+		dev->driver->disable_vblank = valleyview_disable_vblank;
+		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
+	} else if (IS_VALLEYVIEW(dev)) {
 		dev->driver->irq_handler = valleyview_irq_handler;
 		dev->driver->irq_preinstall = valleyview_irq_preinstall;
 		dev->driver->irq_postinstall = valleyview_irq_postinstall;
-- 
1.8.3.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 45/71] drm/i915/chv: Streamline CHV forcewake stuff

[Ville Syrjälä]

On Wed, Apr 09, 2014 at 06:02:36PM +0200, Daniel Vetter wrote:
> On Wed, Apr 09, 2014 at 01:28:43PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Streamline the CHV forcewake functions just like was done for VLV.
> > 
> > This will also fix a bug in accessing the common well registers,
> > where we'd end up trying to wake up the wells too many times
> > since we'd call force_wake_get/put twice per register access, with
> > FORCEFAKE_ALL both times.
> > 
> > Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Ugh ... any chance this would make sense squashed in as a fixup into an
> earlier patch? If it's too hairy I'm ok with this as-is.

It could be squashed into patch 28 which introduces this code. I don't
think there were other patches that touch this piece code. I have no
objection to squashing. Deepak, any objections?

> -Daniel
> 
> > ---
> >  drivers/gpu/drm/i915/intel_uncore.c | 88 ++++++++++++++-----------------------
> >  1 file changed, 32 insertions(+), 56 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> > index ccad770..59293b3 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -618,35 +618,22 @@ chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
> >  	unsigned fwengine = 0; \
> >  	REG_READ_HEADER(x); \
> >  	if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
> > -		fwengine = FORCEWAKE_RENDER; \
> > -	} \
> > -	else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
> > -		fwengine = FORCEWAKE_MEDIA; \
> > -	} \
> > -	else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
> > -		fwengine = FORCEWAKE_ALL; \
> > -	} \
> > -	if (FORCEWAKE_RENDER & fwengine) { \
> > -		if (dev_priv->uncore.fw_rendercount++ == 0) \
> > -			(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
> > -								fwengine); \
> > -	} \
> > -	if (FORCEWAKE_MEDIA & fwengine) { \
> > -		if (dev_priv->uncore.fw_mediacount++ == 0) \
> > -			(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
> > -								fwengine); \
> > +		if (dev_priv->uncore.fw_rendercount == 0) \
> > +			fwengine = FORCEWAKE_RENDER; \
> > +	} else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
> > +		if (dev_priv->uncore.fw_mediacount == 0) \
> > +			fwengine = FORCEWAKE_MEDIA; \
> > +	} else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
> > +		if (dev_priv->uncore.fw_rendercount == 0) \
> > +			fwengine |= FORCEWAKE_RENDER; \
> > +		if (dev_priv->uncore.fw_mediacount == 0) \
> > +			fwengine |= FORCEWAKE_MEDIA; \
> >  	} \
> > +	if (fwengine) \
> > +		dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
> >  	val = __raw_i915_read##x(dev_priv, reg); \
> > -	if (FORCEWAKE_RENDER & fwengine) { \
> > -		if (--dev_priv->uncore.fw_rendercount == 0) \
> > -			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
> > -								fwengine); \
> > -	} \
> > -	if (FORCEWAKE_MEDIA & fwengine) { \
> > -		if (--dev_priv->uncore.fw_mediacount == 0) \
> > -			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
> > -								fwengine); \
> > -	} \
> > +	if (fwengine) \
> > +		dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
> >  	REG_READ_FOOTER; \
> >  }
> >  
> > @@ -780,38 +767,27 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
> >  static void \
> >  chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
> >  	unsigned fwengine = 0; \
> > -	bool __needs_put = !is_gen8_shadowed(dev_priv, reg); \
> > +	bool shadowed = is_gen8_shadowed(dev_priv, reg); \
> >  	REG_WRITE_HEADER; \
> > -	if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
> > -		fwengine = FORCEWAKE_RENDER; \
> > -	} \
> > -	else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
> > -		fwengine = FORCEWAKE_MEDIA; \
> > -	} \
> > -	else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
> > -		fwengine = FORCEWAKE_ALL; \
> > -	} \
> > -	if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \
> > -			if (dev_priv->uncore.fw_rendercount++ == 0) \
> > -				(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
> > -									fwengine); \
> > -	} \
> > -	if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \
> > -		if (dev_priv->uncore.fw_mediacount++ == 0) \
> > -			(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
> > -								fwengine); \
> > +	if (!shadowed) { \
> > +		if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
> > +			if (dev_priv->uncore.fw_rendercount == 0) \
> > +				fwengine = FORCEWAKE_RENDER; \
> > +		} else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
> > +			if (dev_priv->uncore.fw_mediacount == 0) \
> > +				fwengine = FORCEWAKE_MEDIA; \
> > +		} else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
> > +			if (dev_priv->uncore.fw_rendercount == 0) \
> > +				fwengine |= FORCEWAKE_RENDER; \
> > +			if (dev_priv->uncore.fw_mediacount == 0) \
> > +				fwengine |= FORCEWAKE_MEDIA; \
> > +		} \
> >  	} \
> > +	if (fwengine) \
> > +		dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
> >  	__raw_i915_write##x(dev_priv, reg, val); \
> > -	if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \
> > -			if (--dev_priv->uncore.fw_rendercount == 0) \
> > -				(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
> > -									fwengine); \
> > -	} \
> > -	if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \
> > -		if (--dev_priv->uncore.fw_mediacount == 0) \
> > -			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
> > -								fwengine); \
> > -	} \
> > +	if (fwengine) \
> > +		dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
> >  	REG_WRITE_FOOTER; \
> >  }
> >  
> > -- 
> > 1.8.3.2
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 44/71] drm/i915/chv: Fix for decrementing fw count in chv read/write.

[Ville Syrjälä]

On Wed, Apr 09, 2014 at 05:59:21PM +0200, Daniel Vetter wrote:
> On Wed, Apr 09, 2014 at 01:28:42PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Deepak S <deepak.s@intel.com>
> > 
> > This was fumbled in chv specific forcewake count during mmio reg read/write.
> > 
> > Issue introduced in
> > 
> > commit 95cf8b69f647322048929baffa8c7865aa6df2ad
> > Author: Deepak S <deepak.s@intel.com>
> > Date:   Mon Dec 16 12:16:54 2013 +0530
> > Subject: drm/i915/chv: Added CHV specific register read and write
> 
> Again please squash in as a fixup.

Oh there was this patch too that touches the forcewake. Yeah this should
definitely be squashed.

> -Daniel
> 
> > 
> > Signed-off-by: Deepak S <deepak.s@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_uncore.c | 8 ++++----
> >  1 file changed, 4 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> > index 8e3c686..ccad770 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -638,12 +638,12 @@ chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
> >  	} \
> >  	val = __raw_i915_read##x(dev_priv, reg); \
> >  	if (FORCEWAKE_RENDER & fwengine) { \
> > -		if (dev_priv->uncore.fw_rendercount++ == 0) \
> > +		if (--dev_priv->uncore.fw_rendercount == 0) \
> >  			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
> >  								fwengine); \
> >  	} \
> >  	if (FORCEWAKE_MEDIA & fwengine) { \
> > -		if (dev_priv->uncore.fw_mediacount++ == 0) \
> > +		if (--dev_priv->uncore.fw_mediacount == 0) \
> >  			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
> >  								fwengine); \
> >  	} \
> > @@ -803,12 +803,12 @@ chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace)
> >  	} \
> >  	__raw_i915_write##x(dev_priv, reg, val); \
> >  	if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \
> > -			if (dev_priv->uncore.fw_rendercount++ == 0) \
> > +			if (--dev_priv->uncore.fw_rendercount == 0) \
> >  				(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
> >  									fwengine); \
> >  	} \
> >  	if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \
> > -		if (dev_priv->uncore.fw_mediacount++ == 0) \
> > +		if (--dev_priv->uncore.fw_mediacount == 0) \
> >  			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
> >  								fwengine); \
> >  	} \
> > -- 
> > 1.8.3.2
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 45/71] drm/i915/chv: Streamline CHV forcewake stuff

[Deepak S]

On Wednesday 09 April 2014 11:17 PM, Ville Syrjälä wrote:
> On Wed, Apr 09, 2014 at 06:02:36PM +0200, Daniel Vetter wrote:
>> On Wed, Apr 09, 2014 at 01:28:43PM +0300, ville.syrjala@linux.intel.com wrote:
>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>
>>> Streamline the CHV forcewake functions just like was done for VLV.
>>>
>>> This will also fix a bug in accessing the common well registers,
>>> where we'd end up trying to wake up the wells too many times
>>> since we'd call force_wake_get/put twice per register access, with
>>> FORCEFAKE_ALL both times.
>>>
>>> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Ugh ... any chance this would make sense squashed in as a fixup into an
>> earlier patch? If it's too hairy I'm ok with this as-is.
> It could be squashed into patch 28 which introduces this code. I don't
> think there were other patches that touch this piece code. I have no
> objection to squashing. Deepak, any objections?

Nope. I am Ok with squashing the patch.

>> -Daniel
>>
>>> ---
>>>   drivers/gpu/drm/i915/intel_uncore.c | 88 ++++++++++++++-----------------------
>>>   1 file changed, 32 insertions(+), 56 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
>>> index ccad770..59293b3 100644
>>> --- a/drivers/gpu/drm/i915/intel_uncore.c
>>> +++ b/drivers/gpu/drm/i915/intel_uncore.c
>>> @@ -618,35 +618,22 @@ chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
>>>   	unsigned fwengine = 0; \
>>>   	REG_READ_HEADER(x); \
>>>   	if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
>>> -		fwengine = FORCEWAKE_RENDER; \
>>> -	} \
>>> -	else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
>>> -		fwengine = FORCEWAKE_MEDIA; \
>>> -	} \
>>> -	else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
>>> -		fwengine = FORCEWAKE_ALL; \
>>> -	} \
>>> -	if (FORCEWAKE_RENDER & fwengine) { \
>>> -		if (dev_priv->uncore.fw_rendercount++ == 0) \
>>> -			(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
>>> -								fwengine); \
>>> -	} \
>>> -	if (FORCEWAKE_MEDIA & fwengine) { \
>>> -		if (dev_priv->uncore.fw_mediacount++ == 0) \
>>> -			(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
>>> -								fwengine); \
>>> +		if (dev_priv->uncore.fw_rendercount == 0) \
>>> +			fwengine = FORCEWAKE_RENDER; \
>>> +	} else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
>>> +		if (dev_priv->uncore.fw_mediacount == 0) \
>>> +			fwengine = FORCEWAKE_MEDIA; \
>>> +	} else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
>>> +		if (dev_priv->uncore.fw_rendercount == 0) \
>>> +			fwengine |= FORCEWAKE_RENDER; \
>>> +		if (dev_priv->uncore.fw_mediacount == 0) \
>>> +			fwengine |= FORCEWAKE_MEDIA; \
>>>   	} \
>>> +	if (fwengine) \
>>> +		dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
>>>   	val = __raw_i915_read##x(dev_priv, reg); \
>>> -	if (FORCEWAKE_RENDER & fwengine) { \
>>> -		if (--dev_priv->uncore.fw_rendercount == 0) \
>>> -			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
>>> -								fwengine); \
>>> -	} \
>>> -	if (FORCEWAKE_MEDIA & fwengine) { \
>>> -		if (--dev_priv->uncore.fw_mediacount == 0) \
>>> -			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
>>> -								fwengine); \
>>> -	} \
>>> +	if (fwengine) \
>>> +		dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
>>>   	REG_READ_FOOTER; \
>>>   }
>>>   
>>> @@ -780,38 +767,27 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
>>>   static void \
>>>   chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
>>>   	unsigned fwengine = 0; \
>>> -	bool __needs_put = !is_gen8_shadowed(dev_priv, reg); \
>>> +	bool shadowed = is_gen8_shadowed(dev_priv, reg); \
>>>   	REG_WRITE_HEADER; \
>>> -	if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
>>> -		fwengine = FORCEWAKE_RENDER; \
>>> -	} \
>>> -	else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
>>> -		fwengine = FORCEWAKE_MEDIA; \
>>> -	} \
>>> -	else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
>>> -		fwengine = FORCEWAKE_ALL; \
>>> -	} \
>>> -	if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \
>>> -			if (dev_priv->uncore.fw_rendercount++ == 0) \
>>> -				(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
>>> -									fwengine); \
>>> -	} \
>>> -	if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \
>>> -		if (dev_priv->uncore.fw_mediacount++ == 0) \
>>> -			(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
>>> -								fwengine); \
>>> +	if (!shadowed) { \
>>> +		if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
>>> +			if (dev_priv->uncore.fw_rendercount == 0) \
>>> +				fwengine = FORCEWAKE_RENDER; \
>>> +		} else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
>>> +			if (dev_priv->uncore.fw_mediacount == 0) \
>>> +				fwengine = FORCEWAKE_MEDIA; \
>>> +		} else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
>>> +			if (dev_priv->uncore.fw_rendercount == 0) \
>>> +				fwengine |= FORCEWAKE_RENDER; \
>>> +			if (dev_priv->uncore.fw_mediacount == 0) \
>>> +				fwengine |= FORCEWAKE_MEDIA; \
>>> +		} \
>>>   	} \
>>> +	if (fwengine) \
>>> +		dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
>>>   	__raw_i915_write##x(dev_priv, reg, val); \
>>> -	if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \
>>> -			if (--dev_priv->uncore.fw_rendercount == 0) \
>>> -				(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
>>> -									fwengine); \
>>> -	} \
>>> -	if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \
>>> -		if (--dev_priv->uncore.fw_mediacount == 0) \
>>> -			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
>>> -								fwengine); \
>>> -	} \
>>> +	if (fwengine) \
>>> +		dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
>>>   	REG_WRITE_FOOTER; \
>>>   }
>>>   
>>> -- 
>>> 1.8.3.2
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> -- 
>> Daniel Vetter
>> Software Engineer, Intel Corporation
>> +41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 71/71] drm/i915/chv: Handle video DIP registers on CHV

[Damien Lespiau]

On Wed, Apr 09, 2014 at 01:29:09PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The DIP registers are a mess on VLV and CHV. The register block on pipe
> A is different than the register block on pipes B and C. In order to
> handle that using the pipe offsets, we'd need a new pipe offset per
> register, which seems wasteful. So instead just use the _PIPE3() macro
> to handle these registers.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 17 ++++++++++++-----
>  1 file changed, 12 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9fed8ca..14e8de3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4784,8 +4784,7 @@ enum punit_power_well {
>  #define _PCH_TRANSA_LINK_M2	0xe0048
>  #define _PCH_TRANSA_LINK_N2	0xe004c
>  
> -/* Per-transcoder DIP controls */
> -
> +/* Per-transcoder DIP controls (PCH) */
>  #define _VIDEO_DIP_CTL_A         0xe0200
>  #define _VIDEO_DIP_DATA_A        0xe0208
>  #define _VIDEO_DIP_GCP_A         0xe0210
> @@ -4798,6 +4797,7 @@ enum punit_power_well {
>  #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
>  #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
>  
> +/* Per-transcoder DIP controls (VLV) */
>  #define VLV_VIDEO_DIP_CTL_A		(VLV_DISPLAY_BASE + 0x60200)
>  #define VLV_VIDEO_DIP_DATA_A		(VLV_DISPLAY_BASE + 0x60208)
>  #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A	(VLV_DISPLAY_BASE + 0x60210)
> @@ -4806,12 +4806,19 @@ enum punit_power_well {
>  #define VLV_VIDEO_DIP_DATA_B		(VLV_DISPLAY_BASE + 0x61174)
>  #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B	(VLV_DISPLAY_BASE + 0x61178)
>  
> +#define CHV_VIDEO_DIP_CTL_C		(VLV_DISPLAY_BASE + 0x611f0)
> +#define CHV_VIDEO_DIP_DATA_C		(VLV_DISPLAY_BASE + 0x611f4)
> +#define CHV_VIDEO_DIP_GDCP_PAYLOAD_C	(VLV_DISPLAY_BASE + 0x611f8)
> +
>  #define VLV_TVIDEO_DIP_CTL(pipe) \
> -	 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
> +	_PIPE3((pipe), VLV_VIDEO_DIP_CTL_A, \
> +	       VLV_VIDEO_DIP_CTL_B, CHV_VIDEO_DIP_CTL_C)
>  #define VLV_TVIDEO_DIP_DATA(pipe) \
> -	 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
> +	_PIPE3((pipe), VLV_VIDEO_DIP_DATA_A, \
> +	       VLV_VIDEO_DIP_DATA_B, CHV_VIDEO_DIP_DATA_C)
>  #define VLV_TVIDEO_DIP_GCP(pipe) \
> -	_PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
> +	_PIPE3((pipe), VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
> +		VLV_VIDEO_DIP_GDCP_PAYLOAD_B, CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
>  
>  /* Haswell DIP controls */
>  #define HSW_VIDEO_DIP_CTL_A		0x60200
> -- 
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 00/71] drm/i915/chv: Add Cherryview support

[S, Deepak]

On 4/9/2014 10:23 PM, Daniel Vetter wrote:
> On Wed, Apr 09, 2014 at 06:05:27PM +0300, Ville Syrjälä wrote:
>> On Wed, Apr 09, 2014 at 02:30:52PM +0000, S, Deepak wrote:
>>> Hi Ville,
>>>
>>> I am Ok with  cleaning up and pushing the Code. Can you please tell me
>>> when we need to start pushing the code and branch to use
>>> (drm-intel-next)?
>>
>> Well you can consider it pushed now that it's in the open. The patches
>> just need a bit of extra polish I think. Well, unless you're planning
>> a full blown rewrite of the code ;)
>>
>> I guess you need to take into consideration whatever bdw rc6/rps patches
>> are still in flight, but since you've been doing some review there I
>> think you have a better idea than I do how things are progressing.
>>
>> I always work on top of nightly, so I guess that's a good choice :)
>
> Yes, -nightly is always the recommended branch to base upstream patches
> on. I'll sort out the conflict mess (or well, try to) if it doesn't apply
> to plain dinq or some other branch. drm-intel-next tends to be too
> outdated ;-)
> -Daniel

Hi Daniel/Ville.

Some of the patches are lined up for squashing right? So you want me to 
work on this patches to align to upstream code and resubmit it to same 
email thread?

Thanks
Deepak

Re: [PATCH 30/71] drm/i915/chv: Enable PM interrupts when we in CHV turbo initialize sequence.

[Deepak S]

On Wednesday 09 April 2014 06:36 PM, Chris Wilson wrote:
> On Wed, Apr 09, 2014 at 01:28:28PM +0300, ville.syrjala@linux.intel.com wrote:
>> +static void gen8_enable_rps_interrupts(struct drm_device *dev)
>> +{
>> +	struct drm_i915_private *dev_priv = dev->dev_private;
>> +
>> +	/* Clear out any stale interrupts first */
>> +	spin_lock_irq(&dev_priv->irq_lock);
>> +	WARN_ON(dev_priv->rps.pm_iir);
>> +	I915_WRITE(GEN8_GT_IIR(2), I915_READ(GEN8_GT_IIR(2)));
>> +	dev_priv->pm_irq_mask &= ~GEN6_PM_RPS_EVENTS;
>> +	I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask);
>> +	spin_unlock_irq(&dev_priv->irq_lock);
>> +
>> +	I915_WRITE(GEN8_GT_IER(2), GEN6_PM_RPS_EVENTS);
>> +	/* only unmask PM interrupts we need. Mask all others. */
>> +	I915_WRITE(GEN6_PMINTRMSK, ~GEN6_PM_RPS_EVENTS);
> PMINTRMSK handling is now a part of set_rps (and so this line is
> redundant).
> -Chris

Thanks Chris. I will make the changes based on the current nightly code

Re: [PATCH 70/71] drm/i915: Don't use pipe_offset stuff for DPLL registers

[Damien Lespiau]

On Wed, Apr 09, 2014 at 01:29:08PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> These are just single registers so wasting space for the pipe offsets
> seems a bit pointless. So just use the _PIPE3() macro instead.
> 
> Also rewrite the _PIPE3() macro to be more obvious, and protect the
> arguments properly.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

Re: [PATCH 00/71] drm/i915/chv: Add Cherryview support

[Daniel Vetter]

On Thu, Apr 10, 2014 at 12:42:42AM +0530, S, Deepak wrote:
> 
> 
> On 4/9/2014 10:23 PM, Daniel Vetter wrote:
> >On Wed, Apr 09, 2014 at 06:05:27PM +0300, Ville Syrjälä wrote:
> >>On Wed, Apr 09, 2014 at 02:30:52PM +0000, S, Deepak wrote:
> >>>Hi Ville,
> >>>
> >>>I am Ok with  cleaning up and pushing the Code. Can you please tell me
> >>>when we need to start pushing the code and branch to use
> >>>(drm-intel-next)?
> >>
> >>Well you can consider it pushed now that it's in the open. The patches
> >>just need a bit of extra polish I think. Well, unless you're planning
> >>a full blown rewrite of the code ;)
> >>
> >>I guess you need to take into consideration whatever bdw rc6/rps patches
> >>are still in flight, but since you've been doing some review there I
> >>think you have a better idea than I do how things are progressing.
> >>
> >>I always work on top of nightly, so I guess that's a good choice :)
> >
> >Yes, -nightly is always the recommended branch to base upstream patches
> >on. I'll sort out the conflict mess (or well, try to) if it doesn't apply
> >to plain dinq or some other branch. drm-intel-next tends to be too
> >outdated ;-)
> >-Daniel
> 
> Hi Daniel/Ville.
> 
> Some of the patches are lined up for squashing right? So you want me
> to work on this patches to align to upstream code and resubmit it to
> same email thread?

Hm, I expect this chv thread to become a bit mess really quickly tbh ;-)
And since we don't have chv merged yet there's not really a baseline to do
this on top.

I guess the simplest approach would be for you to grab ville's chv tree,
squash in the patches as discussed and then just starting on polishing
your chv patches. Then as I pull in patches from this series you can drop
them from yours. A bit messy, but I don't see any other approach really.

Note that a pile of people are signed up to review this, so maybe hold off
a bit until the review for your patches have been done.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 30/71] drm/i915/chv: Enable PM interrupts when we in CHV turbo initialize sequence.

[Ben Widawsky]

On Thu, Apr 10, 2014 at 12:47:01AM +0530, Deepak S wrote:
> 
> On Wednesday 09 April 2014 06:36 PM, Chris Wilson wrote:
> >On Wed, Apr 09, 2014 at 01:28:28PM +0300, ville.syrjala@linux.intel.com wrote:
> >>+static void gen8_enable_rps_interrupts(struct drm_device *dev)
> >>+{
> >>+	struct drm_i915_private *dev_priv = dev->dev_private;
> >>+
> >>+	/* Clear out any stale interrupts first */
> >>+	spin_lock_irq(&dev_priv->irq_lock);
> >>+	WARN_ON(dev_priv->rps.pm_iir);
> >>+	I915_WRITE(GEN8_GT_IIR(2), I915_READ(GEN8_GT_IIR(2)));
> >>+	dev_priv->pm_irq_mask &= ~GEN6_PM_RPS_EVENTS;
> >>+	I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask);
> >>+	spin_unlock_irq(&dev_priv->irq_lock);
> >>+
> >>+	I915_WRITE(GEN8_GT_IER(2), GEN6_PM_RPS_EVENTS);
> >>+	/* only unmask PM interrupts we need. Mask all others. */
> >>+	I915_WRITE(GEN6_PMINTRMSK, ~GEN6_PM_RPS_EVENTS);
> >PMINTRMSK handling is now a part of set_rps (and so this line is
> >redundant).
> >-Chris
> 
> Thanks Chris. I will make the changes based on the current nightly code
> 
> 

I think my patch kept up with this, but I too am not sure. In either
case feel free to reuse, copy, or review that one.

I don't think I've mailed out the very latest version, but I am pretty
sure I mailed out after the last painful rebase (and it's tested on
BDW).

http://cgit.freedesktop.org/~bwidawsk/drm-intel/commit/?h=bdw-rc6&id=80fbe001fc4ba38c41db3cec177c9157b2613c3c

-- 
Ben Widawsky, Intel Open Source Technology Center

Re: [PATCH 00/71] drm/i915/chv: Add Cherryview support

[S, Deepak]

On 4/10/2014 1:30 AM, Daniel Vetter wrote:
> On Thu, Apr 10, 2014 at 12:42:42AM +0530, S, Deepak wrote:
>>
>>
>> On 4/9/2014 10:23 PM, Daniel Vetter wrote:
>>> On Wed, Apr 09, 2014 at 06:05:27PM +0300, Ville Syrjälä wrote:
>>>> On Wed, Apr 09, 2014 at 02:30:52PM +0000, S, Deepak wrote:
>>>>> Hi Ville,
>>>>>
>>>>> I am Ok with  cleaning up and pushing the Code. Can you please tell me
>>>>> when we need to start pushing the code and branch to use
>>>>> (drm-intel-next)?
>>>>
>>>> Well you can consider it pushed now that it's in the open. The patches
>>>> just need a bit of extra polish I think. Well, unless you're planning
>>>> a full blown rewrite of the code ;)
>>>>
>>>> I guess you need to take into consideration whatever bdw rc6/rps patches
>>>> are still in flight, but since you've been doing some review there I
>>>> think you have a better idea than I do how things are progressing.
>>>>
>>>> I always work on top of nightly, so I guess that's a good choice :)
>>>
>>> Yes, -nightly is always the recommended branch to base upstream patches
>>> on. I'll sort out the conflict mess (or well, try to) if it doesn't apply
>>> to plain dinq or some other branch. drm-intel-next tends to be too
>>> outdated ;-)
>>> -Daniel
>>
>> Hi Daniel/Ville.
>>
>> Some of the patches are lined up for squashing right? So you want me
>> to work on this patches to align to upstream code and resubmit it to
>> same email thread?
>
> Hm, I expect this chv thread to become a bit mess really quickly tbh ;-)
> And since we don't have chv merged yet there's not really a baseline to do
> this on top.
>
> I guess the simplest approach would be for you to grab ville's chv tree,
> squash in the patches as discussed and then just starting on polishing
> your chv patches. Then as I pull in patches from this series you can drop
> them from yours. A bit messy, but I don't see any other approach really.
>
> Note that a pile of people are signed up to review this, so maybe hold off
> a bit until the review for your patches have been done.
> -Daniel

Thanks Daniel.
Ville can you please share your chv tree details?

Re: [PATCH 30/71] drm/i915/chv: Enable PM interrupts when we in CHV turbo initialize sequence.

[Daniel Vetter]

On Wed, Apr 09, 2014 at 03:33:04PM -0700, Ben Widawsky wrote:
> On Thu, Apr 10, 2014 at 12:47:01AM +0530, Deepak S wrote:
> > 
> > On Wednesday 09 April 2014 06:36 PM, Chris Wilson wrote:
> > >On Wed, Apr 09, 2014 at 01:28:28PM +0300, ville.syrjala@linux.intel.com wrote:
> > >>+static void gen8_enable_rps_interrupts(struct drm_device *dev)
> > >>+{
> > >>+	struct drm_i915_private *dev_priv = dev->dev_private;
> > >>+
> > >>+	/* Clear out any stale interrupts first */
> > >>+	spin_lock_irq(&dev_priv->irq_lock);
> > >>+	WARN_ON(dev_priv->rps.pm_iir);
> > >>+	I915_WRITE(GEN8_GT_IIR(2), I915_READ(GEN8_GT_IIR(2)));
> > >>+	dev_priv->pm_irq_mask &= ~GEN6_PM_RPS_EVENTS;
> > >>+	I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask);
> > >>+	spin_unlock_irq(&dev_priv->irq_lock);
> > >>+
> > >>+	I915_WRITE(GEN8_GT_IER(2), GEN6_PM_RPS_EVENTS);
> > >>+	/* only unmask PM interrupts we need. Mask all others. */
> > >>+	I915_WRITE(GEN6_PMINTRMSK, ~GEN6_PM_RPS_EVENTS);
> > >PMINTRMSK handling is now a part of set_rps (and so this line is
> > >redundant).
> > >-Chris
> > 
> > Thanks Chris. I will make the changes based on the current nightly code
> > 
> > 
> 
> I think my patch kept up with this, but I too am not sure. In either
> case feel free to reuse, copy, or review that one.
> 
> I don't think I've mailed out the very latest version, but I am pretty
> sure I mailed out after the last painful rebase (and it's tested on
> BDW).
> 
> http://cgit.freedesktop.org/~bwidawsk/drm-intel/commit/?h=bdw-rc6&id=80fbe001fc4ba38c41db3cec177c9157b2613c3c

Oh right we have some duplication in the gen8 rps/rc6 support story and
never worked that out while the patches where still in internal.
Deepak/Ben can you pls sort this out? Imo best if we just combine the
patches so that we have one series for both bdw and chv, tested on both
ofc.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 00/71] drm/i915/chv: Add Cherryview support

[Ville Syrjälä]

On Wed, Apr 09, 2014 at 04:25:16PM +0300, Ville Syrjälä wrote:
> As you may have noticed some of this stuf may need a bit of work still
> to fit in better with the more recent upstream changes.
> 
> So I think we need a few people to do some work here to the the patches
> into a really good shape. So some division of labor would in order. I'm
> proposing the following:
> rc6/turbo -> Deepak as he's written the code anyway
> interrupts -> Imre since he worked on the VLV interrupts recently
> 
> The rest of the patches should be fairly OK I think. So for the rest we
> probably just need reviews mostly, and maybe we want to squash some of
> the more trivial patches.

I've signeed up people for the reviews as follows:
01-09: Rodrigo
10-15,25,34: Jani
18-24: Jesse
26-33: Ben
35-43: Paulo
44-49: Imre
50-58: Antti
59-69: Mika
70-71: Damien

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 00/71] drm/i915/chv: Add Cherryview support

[Ville Syrjälä]

On Thu, Apr 10, 2014 at 09:31:39AM +0530, S, Deepak wrote:
> 
> 
> On 4/10/2014 1:30 AM, Daniel Vetter wrote:
> > On Thu, Apr 10, 2014 at 12:42:42AM +0530, S, Deepak wrote:
> >>
> >>
> >> On 4/9/2014 10:23 PM, Daniel Vetter wrote:
> >>> On Wed, Apr 09, 2014 at 06:05:27PM +0300, Ville Syrjälä wrote:
> >>>> On Wed, Apr 09, 2014 at 02:30:52PM +0000, S, Deepak wrote:
> >>>>> Hi Ville,
> >>>>>
> >>>>> I am Ok with  cleaning up and pushing the Code. Can you please tell me
> >>>>> when we need to start pushing the code and branch to use
> >>>>> (drm-intel-next)?
> >>>>
> >>>> Well you can consider it pushed now that it's in the open. The patches
> >>>> just need a bit of extra polish I think. Well, unless you're planning
> >>>> a full blown rewrite of the code ;)
> >>>>
> >>>> I guess you need to take into consideration whatever bdw rc6/rps patches
> >>>> are still in flight, but since you've been doing some review there I
> >>>> think you have a better idea than I do how things are progressing.
> >>>>
> >>>> I always work on top of nightly, so I guess that's a good choice :)
> >>>
> >>> Yes, -nightly is always the recommended branch to base upstream patches
> >>> on. I'll sort out the conflict mess (or well, try to) if it doesn't apply
> >>> to plain dinq or some other branch. drm-intel-next tends to be too
> >>> outdated ;-)
> >>> -Daniel
> >>
> >> Hi Daniel/Ville.
> >>
> >> Some of the patches are lined up for squashing right? So you want me
> >> to work on this patches to align to upstream code and resubmit it to
> >> same email thread?
> >
> > Hm, I expect this chv thread to become a bit mess really quickly tbh ;-)
> > And since we don't have chv merged yet there's not really a baseline to do
> > this on top.
> >
> > I guess the simplest approach would be for you to grab ville's chv tree,
> > squash in the patches as discussed and then just starting on polishing
> > your chv patches. Then as I pull in patches from this series you can drop
> > them from yours. A bit messy, but I don't see any other approach really.
> >
> > Note that a pile of people are signed up to review this, so maybe hold off
> > a bit until the review for your patches have been done.
> > -Daniel
> 
> Thanks Daniel.
> Ville can you please share your chv tree details?

I rebased the lot and pushed here:
git://gitorious.org/vsyrjala/linux.git chv_rebase

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 00/71] drm/i915/chv: Add Cherryview support

[Jani Nikula]

On Thu, 10 Apr 2014, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Apr 10, 2014 at 09:31:39AM +0530, S, Deepak wrote:
>> 
>> 
>> On 4/10/2014 1:30 AM, Daniel Vetter wrote:
>> > On Thu, Apr 10, 2014 at 12:42:42AM +0530, S, Deepak wrote:
>> >>
>> >>
>> >> On 4/9/2014 10:23 PM, Daniel Vetter wrote:
>> >>> On Wed, Apr 09, 2014 at 06:05:27PM +0300, Ville Syrjälä wrote:
>> >>>> On Wed, Apr 09, 2014 at 02:30:52PM +0000, S, Deepak wrote:
>> >>>>> Hi Ville,
>> >>>>>
>> >>>>> I am Ok with  cleaning up and pushing the Code. Can you please tell me
>> >>>>> when we need to start pushing the code and branch to use
>> >>>>> (drm-intel-next)?
>> >>>>
>> >>>> Well you can consider it pushed now that it's in the open. The patches
>> >>>> just need a bit of extra polish I think. Well, unless you're planning
>> >>>> a full blown rewrite of the code ;)
>> >>>>
>> >>>> I guess you need to take into consideration whatever bdw rc6/rps patches
>> >>>> are still in flight, but since you've been doing some review there I
>> >>>> think you have a better idea than I do how things are progressing.
>> >>>>
>> >>>> I always work on top of nightly, so I guess that's a good choice :)
>> >>>
>> >>> Yes, -nightly is always the recommended branch to base upstream patches
>> >>> on. I'll sort out the conflict mess (or well, try to) if it doesn't apply
>> >>> to plain dinq or some other branch. drm-intel-next tends to be too
>> >>> outdated ;-)
>> >>> -Daniel
>> >>
>> >> Hi Daniel/Ville.
>> >>
>> >> Some of the patches are lined up for squashing right? So you want me
>> >> to work on this patches to align to upstream code and resubmit it to
>> >> same email thread?
>> >
>> > Hm, I expect this chv thread to become a bit mess really quickly tbh ;-)
>> > And since we don't have chv merged yet there's not really a baseline to do
>> > this on top.
>> >
>> > I guess the simplest approach would be for you to grab ville's chv tree,
>> > squash in the patches as discussed and then just starting on polishing
>> > your chv patches. Then as I pull in patches from this series you can drop
>> > them from yours. A bit messy, but I don't see any other approach really.
>> >
>> > Note that a pile of people are signed up to review this, so maybe hold off
>> > a bit until the review for your patches have been done.
>> > -Daniel
>> 
>> Thanks Daniel.
>> Ville can you please share your chv tree details?
>
> I rebased the lot and pushed here:
> git://gitorious.org/vsyrjala/linux.git chv_rebase

/me being lazy, did you squash/reorder patches, i.e. do the patch #
assignments [1] for review still apply?

Jani.


[1] http://mid.gmane.org/20140410110857.GW18465@intel.com

>
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 00/71] drm/i915/chv: Add Cherryview support

[Ville Syrjälä]

On Thu, Apr 10, 2014 at 04:41:10PM +0300, Jani Nikula wrote:
> On Thu, 10 Apr 2014, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Thu, Apr 10, 2014 at 09:31:39AM +0530, S, Deepak wrote:
> >> 
> >> 
> >> On 4/10/2014 1:30 AM, Daniel Vetter wrote:
> >> > On Thu, Apr 10, 2014 at 12:42:42AM +0530, S, Deepak wrote:
> >> >>
> >> >>
> >> >> On 4/9/2014 10:23 PM, Daniel Vetter wrote:
> >> >>> On Wed, Apr 09, 2014 at 06:05:27PM +0300, Ville Syrjälä wrote:
> >> >>>> On Wed, Apr 09, 2014 at 02:30:52PM +0000, S, Deepak wrote:
> >> >>>>> Hi Ville,
> >> >>>>>
> >> >>>>> I am Ok with  cleaning up and pushing the Code. Can you please tell me
> >> >>>>> when we need to start pushing the code and branch to use
> >> >>>>> (drm-intel-next)?
> >> >>>>
> >> >>>> Well you can consider it pushed now that it's in the open. The patches
> >> >>>> just need a bit of extra polish I think. Well, unless you're planning
> >> >>>> a full blown rewrite of the code ;)
> >> >>>>
> >> >>>> I guess you need to take into consideration whatever bdw rc6/rps patches
> >> >>>> are still in flight, but since you've been doing some review there I
> >> >>>> think you have a better idea than I do how things are progressing.
> >> >>>>
> >> >>>> I always work on top of nightly, so I guess that's a good choice :)
> >> >>>
> >> >>> Yes, -nightly is always the recommended branch to base upstream patches
> >> >>> on. I'll sort out the conflict mess (or well, try to) if it doesn't apply
> >> >>> to plain dinq or some other branch. drm-intel-next tends to be too
> >> >>> outdated ;-)
> >> >>> -Daniel
> >> >>
> >> >> Hi Daniel/Ville.
> >> >>
> >> >> Some of the patches are lined up for squashing right? So you want me
> >> >> to work on this patches to align to upstream code and resubmit it to
> >> >> same email thread?
> >> >
> >> > Hm, I expect this chv thread to become a bit mess really quickly tbh ;-)
> >> > And since we don't have chv merged yet there's not really a baseline to do
> >> > this on top.
> >> >
> >> > I guess the simplest approach would be for you to grab ville's chv tree,
> >> > squash in the patches as discussed and then just starting on polishing
> >> > your chv patches. Then as I pull in patches from this series you can drop
> >> > them from yours. A bit messy, but I don't see any other approach really.
> >> >
> >> > Note that a pile of people are signed up to review this, so maybe hold off
> >> > a bit until the review for your patches have been done.
> >> > -Daniel
> >> 
> >> Thanks Daniel.
> >> Ville can you please share your chv tree details?
> >
> > I rebased the lot and pushed here:
> > git://gitorious.org/vsyrjala/linux.git chv_rebase
> 
> /me being lazy, did you squash/reorder patches, i.e. do the patch #
> assignments [1] for review still apply?

The numbers would get shifted around a bit due to two these two patches
already getting merged:
 drm/i915/chv: IS_BROADWELL() should not be true for Cherryview
 drm/i915/chv: Add IS_CHERRYVIEW() macro

And this patch got dropped as it no longer applies:
 drm/i915/chv: Add plane C support

Apart from that no reordering/squashing.

> 
> Jani.
> 
> 
> [1] http://mid.gmane.org/20140410110857.GW18465@intel.com
> 
> >
> > -- 
> > Ville Syrjälä
> > Intel OTC
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 27/71] drm/i915/chv: Enable Render Standby (RC6) for Cheeryview

[Chris Wilson]

On Wed, Apr 09, 2014 at 01:28:25PM +0300, ville.syrjala@linux.intel.com wrote:
> +static void cherryview_setup_pctx(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	unsigned long pctx_paddr;
> +	struct i915_gtt *gtt = &dev_priv->gtt;
> +	u32 pcbr;
> +	int pctx_size = 32*1024;
> +
> +	pcbr = I915_READ(VLV_PCBR);
> +	if (pcbr >> 12 == 0) {
> +		/*
> +		 * From the Gunit register HAS:
> +		 * The Gfx driver is expected to program this register and ensure
> +		 * proper allocation within Gfx stolen memory.  For example, this
> +		 * register should be programmed such than the PCBR range does not
> +		 * overlap with other relevant ranges.
> +		 */
> +		pctx_paddr = (dev_priv->mm.stolen_base + gtt->stolen_size - pctx_size);

Erm. Isn't the comment missing a FIXME? After all it explains exactly
what you are doing wrong here.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 27/71] drm/i915/chv: Enable Render Standby (RC6) for Cheeryview

[Jani Nikula]

On Wed, 09 Apr 2014, ville.syrjala@linux.intel.com wrote:
> From: Deepak S <deepak.s@intel.com>
>
> v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
>
> Signed-off-by: Deepak S <deepak.s@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 101 ++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 98 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0889af7..909cc0a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3184,6 +3184,18 @@ static void gen6_disable_rps(struct drm_device *dev)
>  	gen6_disable_rps_interrupts(dev);
>  }
>  
> +static void cherryview_disable_rps(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	I915_WRITE(GEN6_RC_CONTROL, 0);
> +
> +	if (dev_priv->vlv_pctx) {
> +		drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
> +		dev_priv->vlv_pctx = NULL;
> +	}
> +}
> +
>  static void valleyview_disable_rps(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -3551,6 +3563,29 @@ int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
>  	return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
>  }
>  
> +static void cherryview_setup_pctx(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	unsigned long pctx_paddr;
> +	struct i915_gtt *gtt = &dev_priv->gtt;
> +	u32 pcbr;
> +	int pctx_size = 32*1024;
> +
> +	pcbr = I915_READ(VLV_PCBR);
> +	if (pcbr >> 12 == 0) {
> +		/*
> +		 * From the Gunit register HAS:
> +		 * The Gfx driver is expected to program this register and ensure
> +		 * proper allocation within Gfx stolen memory.  For example, this
> +		 * register should be programmed such than the PCBR range does not
> +		 * overlap with other relevant ranges.
> +		 */
> +		pctx_paddr = (dev_priv->mm.stolen_base + gtt->stolen_size - pctx_size);
> +		I915_WRITE(VLV_PCBR, pctx_paddr);
> +	}
> +}
> +
> +
>  static void valleyview_setup_pctx(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -3595,6 +3630,61 @@ out:
>  	dev_priv->vlv_pctx = pctx;
>  }
>  
> +static void cherryview_enable_rps(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_ring_buffer *ring;
> +	u32 gtfifodbg, rc6_mode = 0, pcbr;
> +	int i;
> +
> +	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> +
> +	if ((gtfifodbg = I915_READ(GTFIFODBG))) {

Please no assignment within if; this one's easy to split.

There's a bunch of other checkpatch issues in the series; I don't
personally care about most of them but you might want to run it and see
if you want to do something about it.

BR,
Jani.


> +		DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
> +				 gtfifodbg);
> +		I915_WRITE(GTFIFODBG, gtfifodbg);
> +	}
> +
> +	cherryview_setup_pctx(dev);
> +
> +	/* 1a & 1b: Get forcewake during program sequence. Although the driver
> +	 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
> +	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
> +
> +	/* 2a: Program RC6 thresholds.*/
> +	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
> +	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
> +	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> +
> +	for_each_ring(ring, dev_priv, i)
> +		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
> +
> +	I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
> +
> +	/* allows RC6 residency counter to work */
> +	I915_WRITE(VLV_COUNTER_CONTROL,
> +		   _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
> +				      VLV_MEDIA_RC6_COUNT_EN |
> +				      VLV_RENDER_RC6_COUNT_EN));
> +
> +	/* Todo: If BIOS has not configured PCBR
> +	 *       then allocate in BIOS Reserved */
> +
> +	/* For now we assume BIOS is allocating and populating the PCBR  */
> +	pcbr = I915_READ(VLV_PCBR);
> +
> +	DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
> +
> +	/* 3: Enable RC6 */
> +	if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE & (pcbr >> 12))
> +		rc6_mode = GEN6_RC_CTL_EI_MODE(1) | VLV_RC_CTL_CTX_RST_PARALLEL;
> +
> +	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
> +
> +	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
> +}
> +
> +
>  static void valleyview_enable_rps(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -4437,7 +4527,9 @@ void intel_disable_gt_powersave(struct drm_device *dev)
>  		cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
>  		cancel_work_sync(&dev_priv->rps.work);
>  		mutex_lock(&dev_priv->rps.hw_lock);
> -		if (IS_VALLEYVIEW(dev))
> +		if (IS_CHERRYVIEW(dev))
> +			cherryview_disable_rps(dev);
> +		else if (IS_VALLEYVIEW(dev))
>  			valleyview_disable_rps(dev);
>  		else
>  			gen6_disable_rps(dev);
> @@ -4455,7 +4547,9 @@ static void intel_gen6_powersave_work(struct work_struct *work)
>  
>  	mutex_lock(&dev_priv->rps.hw_lock);
>  
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_CHERRYVIEW(dev)) {
> +		cherryview_enable_rps(dev);
> +	} else if (IS_VALLEYVIEW(dev)) {
>  		valleyview_enable_rps(dev);
>  	} else if (IS_BROADWELL(dev)) {
>  		gen8_enable_rps(dev);
> @@ -4476,7 +4570,7 @@ void intel_enable_gt_powersave(struct drm_device *dev)
>  		ironlake_enable_drps(dev);
>  		ironlake_enable_rc6(dev);
>  		intel_init_emon(dev);
> -	} else if (IS_GEN6(dev) || IS_GEN7(dev)) {
> +	} else if (INTEL_INFO(dev)->gen >= 6) {
>  		if (IS_VALLEYVIEW(dev))
>  			valleyview_setup_pctx(dev);
>  		/*
> @@ -5051,6 +5145,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>  		dev_priv->mem_freq = 1333;
>  		break;
>  	}
> +
>  	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
>  
>  	dev_priv->vlv_cdclk_freq = valleyview_cur_cdclk(dev_priv);
> -- 
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center

Re: [PATCH 49/71] drm/i915/chv: Add CHV display support

[Jani Nikula]

On Wed, 09 Apr 2014, ville.syrjala@linux.intel.com wrote:
> From: Rafael Barbalho <rafael.barbalho@intel.com>
>
> Add support for the third pipe in cherrview
>
> Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
> [vsyrjala: slightly massaged the patch]
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c |  7 +++++++
>  drivers/gpu/drm/i915/i915_reg.h | 11 ++++++++---
>  2 files changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 2415fa2..c5e9fa8 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -49,6 +49,12 @@ static struct drm_driver driver;
>  	.dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \
>  	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
>  
> +#define GEN_CHV_PIPEOFFSETS \
> +       .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, CHV_PIPE_C_OFFSET }, \
> +       .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, CHV_TRANSCODER_C_OFFSET, }, \
> +       .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET, CHV_DPLL_C_OFFSET }, \
> +       .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET, CHV_DPLL_C_MD_OFFSET }, \
> +       .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, CHV_PALETTE_C_OFFSET }
>  
>  static const struct intel_device_info intel_i830_info = {
>  	.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
> @@ -286,6 +292,7 @@ static const struct intel_device_info intel_cherryview_info = {
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
>  	.is_valleyview = 1,
>  	.display_mmio_offset = VLV_DISPLAY_BASE,
> +	GEN_CHV_PIPEOFFSETS,

These use spaces for indentation. Please fix.

BR,
Jani.


>  };
>  
>  /*
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7587752..3831d84 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1430,6 +1430,7 @@ enum punit_power_well {
>   */
>  #define DPLL_A_OFFSET 0x6014
>  #define DPLL_B_OFFSET 0x6018
> +#define CHV_DPLL_C_OFFSET 0x6030
>  #define DPLL(pipe) (dev_priv->info.dpll_offsets[pipe] + \
>  		    dev_priv->info.display_mmio_offset)
>  
> @@ -1521,6 +1522,7 @@ enum punit_power_well {
>  
>  #define DPLL_A_MD_OFFSET 0x601c /* 965+ only */
>  #define DPLL_B_MD_OFFSET 0x6020 /* 965+ only */
> +#define CHV_DPLL_C_MD_OFFSET 0x603c
>  #define DPLL_MD(pipe) (dev_priv->info.dpll_md_offsets[pipe] + \
>  		       dev_priv->info.display_mmio_offset)
>  
> @@ -1717,6 +1719,7 @@ enum punit_power_well {
>   */
>  #define PALETTE_A_OFFSET 0xa000
>  #define PALETTE_B_OFFSET 0xa800
> +#define CHV_PALETTE_C_OFFSET 0xc000
>  #define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \
>  		       dev_priv->info.display_mmio_offset)
>  
> @@ -2206,6 +2209,7 @@ enum punit_power_well {
>  #define TRANSCODER_A_OFFSET 0x60000
>  #define TRANSCODER_B_OFFSET 0x61000
>  #define TRANSCODER_C_OFFSET 0x62000
> +#define CHV_TRANSCODER_C_OFFSET 0x63000
>  #define TRANSCODER_EDP_OFFSET 0x6f000
>  
>  #define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
> @@ -3533,9 +3537,10 @@ enum punit_power_well {
>  #define PIPESTAT_INT_ENABLE_MASK		0x7fff0000
>  #define PIPESTAT_INT_STATUS_MASK		0x0000ffff
>  
> -#define PIPE_A_OFFSET	0x70000
> -#define PIPE_B_OFFSET	0x71000
> -#define PIPE_C_OFFSET	0x72000
> +#define PIPE_A_OFFSET		0x70000
> +#define PIPE_B_OFFSET		0x71000
> +#define PIPE_C_OFFSET		0x72000
> +#define CHV_PIPE_C_OFFSET	0x74000
>  /*
>   * There's actually no pipe EDP. Some pipe registers have
>   * simply shifted from the pipe to the transcoder, while
> -- 
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 53/71] drm/i915/chv: Configure crtc_mask correctly for CHV

[Jani Nikula]

On Wed, 09 Apr 2014, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> On CHV pipe C can driver only port D, and pipes A and B can drivbe only
> ports B and C. Configure the crtc_mask appropriately to reflect that.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c   | 8 +++++++-
>  drivers/gpu/drm/i915/intel_hdmi.c | 8 +++++++-
>  2 files changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 21ac845..6ae4d28 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4070,7 +4070,13 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
>  	intel_dig_port->dp.output_reg = output_reg;
>  
>  	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
> -	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
> +	if (IS_CHERRYVIEW(dev)) {
> +		if (port == PORT_D)
> +			intel_encoder->crtc_mask = 1 << 2;
> +		else
> +			intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
> +	} else
> +		intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);

Per CodingStyle, if one branch requires braces, they all do.

>  	intel_encoder->cloneable = 0;
>  	intel_encoder->hot_plug = intel_dp_hot_plug;
>  
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 9f868f4..349374b 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1426,7 +1426,13 @@ void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
>  	}
>  
>  	intel_encoder->type = INTEL_OUTPUT_HDMI;
> -	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
> +	if (IS_CHERRYVIEW(dev)) {
> +		if (port == PORT_D)
> +			intel_encoder->crtc_mask = 1 << 2;
> +		else
> +			intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
> +	} else
> +		intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);

Ditto.

>  	intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
>  	/*
>  	 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
> -- 
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 29/71] drm/i915/chv: Enable RPS (Turbo) for Cheeryview

[Jani Nikula]

On Wed, 09 Apr 2014, ville.syrjala@linux.intel.com wrote:
> From: Deepak S <deepak.s@intel.com>
>
> v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
>
> v3: Mass rename of the dev_priv->rps variables in upstream.
>
> Signed-off-by: Deepak S <deepak.s@intel.com> (v1)
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/i915_drv.h       |  1 +
>  drivers/gpu/drm/i915/i915_reg.h       | 10 +++++
>  drivers/gpu/drm/i915/intel_pm.c       | 82 ++++++++++++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/intel_sideband.c | 15 +++++++
>  4 files changed, 107 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 07a162c..a67f18f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2521,6 +2521,7 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
>  u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
>  void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
>  u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
> +u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
>  u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
>  void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>  u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 91c8fac..e67b4a6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -468,6 +468,7 @@
>  #define VLV_IOSF_DATA				(VLV_DISPLAY_BASE + 0x2104)
>  #define VLV_IOSF_ADDR				(VLV_DISPLAY_BASE + 0x2108)
>  
> +#define   CHV_IOSF_PORT_NC			0x04
>  /* See configdb bunit SB addr map */
>  #define BUNIT_REG_BISOC				0x11
>  
> @@ -513,6 +514,14 @@ enum punit_power_well {
>  #define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */
>  #define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
>  
> +#define CHV_IOSF_NC_FB_GFX_FREQ_FUSE		0xdb
> +#define CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT		16
> +#define CHV_FB_GFX_MAX_FREQ_FUSE_MASK		0xff
> +
> +#define CHV_IOSF_NC_FB_GFX_RPE_FUSE		0xdf
> +#define CHV_FB_RPE_FREQ_SHIFT			8
> +#define CHV_FB_RPE_FREQ_MASK			0xff
> +
>  #define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c
>  #define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3
>  #define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8
> @@ -809,6 +818,7 @@ enum punit_power_well {
>  #define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
>  #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
>  
> +
>  /* control register for cpu gtt access */
>  #define TILECTL				0x101000
>  #define   TILECTL_SWZCTL			(1 << 0)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 909cc0a..4217576 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3533,6 +3533,38 @@ void gen6_update_ring_freq(struct drm_device *dev)
>  	}
>  }
>  
> +int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)

static

> +{
> +	u32 val, rp0;
> +
> +	val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
> +
> +	rp0 = (val >> CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT) &
> +					CHV_FB_GFX_MAX_FREQ_FUSE_MASK;
> +
> +	return rp0;
> +}
> +
> +static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
> +{
> +	u32 val, rpe;
> +
> +	val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_RPE_FUSE);
> +	rpe = (val >> CHV_FB_RPE_FREQ_SHIFT) & CHV_FB_RPE_FREQ_MASK;
> +
> +	return rpe;
> +}
> +
> +int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)

static

BR,
Jani.

> +{
> +	u32 val, rpn;
> +
> +	val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
> +	rpn = (val >> CHV_FB_RPE_FREQ_SHIFT) & CHV_FB_RPE_FREQ_MASK;
> +
> +	return rpn;
> +}
> +
>  int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
>  {
>  	u32 val, rp0;
> @@ -3634,7 +3666,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_ring_buffer *ring;
> -	u32 gtfifodbg, rc6_mode = 0, pcbr;
> +	u32 gtfifodbg, val, rc6_mode = 0, pcbr;
>  	int i;
>  
>  	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> @@ -3681,6 +3713,54 @@ static void cherryview_enable_rps(struct drm_device *dev)
>  
>  	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
>  
> +	/* 4 Program defaults and thresholds for RPS*/
> +	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
> +	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
> +	I915_WRITE(GEN6_RP_UP_EI, 66000);
> +	I915_WRITE(GEN6_RP_DOWN_EI, 350000);
> +
> +	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
> +
> +	/* 5: Enable RPS */
> +	I915_WRITE(GEN6_RP_CONTROL,
> +		   GEN6_RP_MEDIA_HW_NORMAL_MODE |
> +		   GEN6_RP_MEDIA_IS_GFX |
> +		   GEN6_RP_ENABLE |
> +		   GEN6_RP_UP_BUSY_AVG |
> +		   GEN6_RP_DOWN_IDLE_AVG);
> +
> +	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> +
> +	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
> +	DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
> +
> +	dev_priv->rps.cur_freq = (val >> 8) & 0xff;
> +	DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
> +			 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
> +			 dev_priv->rps.cur_freq);
> +
> +	dev_priv->rps.max_freq_softlimit = cherryview_rps_max_freq(dev_priv);
> +	dev_priv->rps.max_freq = dev_priv->rps.max_freq_softlimit;
> +	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
> +			 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
> +			 dev_priv->rps.max_freq_softlimit);
> +
> +	dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
> +	DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
> +			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> +			 dev_priv->rps.efficient_freq);
> +
> +	dev_priv->rps.min_freq_softlimit = cherryview_rps_min_freq(dev_priv);
> +	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
> +			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
> +			 dev_priv->rps.min_freq_softlimit);
> +
> +	DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
> +			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> +			 dev_priv->rps.efficient_freq);
> +
> +	valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
> +
>  	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index c1e56f5..771e904 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -106,6 +106,21 @@ void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
>  			PUNIT_OPCODE_REG_WRITE, reg, &val);
>  }
>  
> +u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
> +{
> +	u32 val = 0;
> +
> +	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> +
> +	mutex_lock(&dev_priv->dpio_lock);
> +	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), CHV_IOSF_PORT_NC,
> +			PUNIT_OPCODE_REG_READ, addr, &val);
> +	mutex_unlock(&dev_priv->dpio_lock);
> +
> +	return val;
> +}
> +
> +
>  u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
>  {
>  	u32 val = 0;
> -- 
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center

Re: [PATCH 27/71] drm/i915/chv: Enable Render Standby (RC6) for Cheeryview

[Ville Syrjälä]

On Thu, Apr 10, 2014 at 07:51:03PM +0300, Jani Nikula wrote:
> On Wed, 09 Apr 2014, ville.syrjala@linux.intel.com wrote:
> > From: Deepak S <deepak.s@intel.com>
> >
> > v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
> >
> > Signed-off-by: Deepak S <deepak.s@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 101 ++++++++++++++++++++++++++++++++++++++--
> >  1 file changed, 98 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 0889af7..909cc0a 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3184,6 +3184,18 @@ static void gen6_disable_rps(struct drm_device *dev)
> >  	gen6_disable_rps_interrupts(dev);
> >  }
> >  
> > +static void cherryview_disable_rps(struct drm_device *dev)
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +
> > +	I915_WRITE(GEN6_RC_CONTROL, 0);
> > +
> > +	if (dev_priv->vlv_pctx) {
> > +		drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
> > +		dev_priv->vlv_pctx = NULL;
> > +	}
> > +}
> > +
> >  static void valleyview_disable_rps(struct drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -3551,6 +3563,29 @@ int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
> >  	return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
> >  }
> >  
> > +static void cherryview_setup_pctx(struct drm_device *dev)
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	unsigned long pctx_paddr;
> > +	struct i915_gtt *gtt = &dev_priv->gtt;
> > +	u32 pcbr;
> > +	int pctx_size = 32*1024;
> > +
> > +	pcbr = I915_READ(VLV_PCBR);
> > +	if (pcbr >> 12 == 0) {
> > +		/*
> > +		 * From the Gunit register HAS:
> > +		 * The Gfx driver is expected to program this register and ensure
> > +		 * proper allocation within Gfx stolen memory.  For example, this
> > +		 * register should be programmed such than the PCBR range does not
> > +		 * overlap with other relevant ranges.
> > +		 */
> > +		pctx_paddr = (dev_priv->mm.stolen_base + gtt->stolen_size - pctx_size);
> > +		I915_WRITE(VLV_PCBR, pctx_paddr);
> > +	}
> > +}
> > +
> > +
> >  static void valleyview_setup_pctx(struct drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -3595,6 +3630,61 @@ out:
> >  	dev_priv->vlv_pctx = pctx;
> >  }
> >  
> > +static void cherryview_enable_rps(struct drm_device *dev)
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	struct intel_ring_buffer *ring;
> > +	u32 gtfifodbg, rc6_mode = 0, pcbr;
> > +	int i;
> > +
> > +	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> > +
> > +	if ((gtfifodbg = I915_READ(GTFIFODBG))) {
> 
> Please no assignment within if; this one's easy to split.
> 
> There's a bunch of other checkpatch issues in the series; I don't
> personally care about most of them but you might want to run it and see
> if you want to do something about it.

Looks like it's a straight up copy-paste from the gen6 and vlv code. So
someone might want to clean those out as well.

And maybe we should just drop this check for CHV since the GT wake FIFO
isn't used anymore. But I'm not sure if the register still hold something
sensible or not.

> 
> BR,
> Jani.
> 
> 
> > +		DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
> > +				 gtfifodbg);
> > +		I915_WRITE(GTFIFODBG, gtfifodbg);
> > +	}
> > +
> > +	cherryview_setup_pctx(dev);
> > +
> > +	/* 1a & 1b: Get forcewake during program sequence. Although the driver
> > +	 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
> > +	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
> > +
> > +	/* 2a: Program RC6 thresholds.*/
> > +	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
> > +	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
> > +	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> > +
> > +	for_each_ring(ring, dev_priv, i)
> > +		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
> > +
> > +	I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
> > +
> > +	/* allows RC6 residency counter to work */
> > +	I915_WRITE(VLV_COUNTER_CONTROL,
> > +		   _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
> > +				      VLV_MEDIA_RC6_COUNT_EN |
> > +				      VLV_RENDER_RC6_COUNT_EN));
> > +
> > +	/* Todo: If BIOS has not configured PCBR
> > +	 *       then allocate in BIOS Reserved */
> > +
> > +	/* For now we assume BIOS is allocating and populating the PCBR  */
> > +	pcbr = I915_READ(VLV_PCBR);
> > +
> > +	DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
> > +
> > +	/* 3: Enable RC6 */
> > +	if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE & (pcbr >> 12))
> > +		rc6_mode = GEN6_RC_CTL_EI_MODE(1) | VLV_RC_CTL_CTX_RST_PARALLEL;
> > +
> > +	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
> > +
> > +	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
> > +}
> > +
> > +
> >  static void valleyview_enable_rps(struct drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -4437,7 +4527,9 @@ void intel_disable_gt_powersave(struct drm_device *dev)
> >  		cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
> >  		cancel_work_sync(&dev_priv->rps.work);
> >  		mutex_lock(&dev_priv->rps.hw_lock);
> > -		if (IS_VALLEYVIEW(dev))
> > +		if (IS_CHERRYVIEW(dev))
> > +			cherryview_disable_rps(dev);
> > +		else if (IS_VALLEYVIEW(dev))
> >  			valleyview_disable_rps(dev);
> >  		else
> >  			gen6_disable_rps(dev);
> > @@ -4455,7 +4547,9 @@ static void intel_gen6_powersave_work(struct work_struct *work)
> >  
> >  	mutex_lock(&dev_priv->rps.hw_lock);
> >  
> > -	if (IS_VALLEYVIEW(dev)) {
> > +	if (IS_CHERRYVIEW(dev)) {
> > +		cherryview_enable_rps(dev);
> > +	} else if (IS_VALLEYVIEW(dev)) {
> >  		valleyview_enable_rps(dev);
> >  	} else if (IS_BROADWELL(dev)) {
> >  		gen8_enable_rps(dev);
> > @@ -4476,7 +4570,7 @@ void intel_enable_gt_powersave(struct drm_device *dev)
> >  		ironlake_enable_drps(dev);
> >  		ironlake_enable_rc6(dev);
> >  		intel_init_emon(dev);
> > -	} else if (IS_GEN6(dev) || IS_GEN7(dev)) {
> > +	} else if (INTEL_INFO(dev)->gen >= 6) {
> >  		if (IS_VALLEYVIEW(dev))
> >  			valleyview_setup_pctx(dev);
> >  		/*
> > @@ -5051,6 +5145,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
> >  		dev_priv->mem_freq = 1333;
> >  		break;
> >  	}
> > +
> >  	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
> >  
> >  	dev_priv->vlv_cdclk_freq = valleyview_cur_cdclk(dev_priv);
> > -- 
> > 1.8.3.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 25/71] drm/i915/chv: CHV doesn't have CRT output

[Jani Nikula]

On Wed, 09 Apr 2014, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Wed, Apr 09, 2014 at 01:28:23PM +0300, ville.syrjala@linux.intel.com wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> 
>> No CRT output on CHV, so don't call intel_crt_init().
>> 
>> v2: Don't disable CRT on HAS.
>> 
>> FIXME: Split out the is_simulator check again, we need it for now to keep HAS
>> going.
>
> Fixme can be dropped, this is something I need to sort out when rebasing
> internal.

FWIW, with that fixed,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>



> -Daniel
>
>> 
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1)
>> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>> ---
>>  drivers/gpu/drm/i915/intel_display.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 266d8fe..9b65a04 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -10989,7 +10989,7 @@ static void intel_setup_outputs(struct drm_device *dev)
>>  
>>  	intel_lvds_init(dev);
>>  
>> -	if (!IS_ULT(dev))
>> +	if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev))
>>  		intel_crt_init(dev);
>>  
>>  	if (HAS_DDI(dev)) {
>> -- 
>> 1.8.3.2
>> 
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 27/71] drm/i915/chv: Enable Render Standby (RC6) for Cheeryview

[Deepak S]

Thanks for the feedback. I will address all the comments
and I will post cherryview rc6/turbo updated patches within couple of days.

I think the patches need little bit of cleanup.

Thanks
Deepak


On Thursday 10 April 2014 10:36 PM, Ville Syrjälä wrote:
> On Thu, Apr 10, 2014 at 07:51:03PM +0300, Jani Nikula wrote:
>> On Wed, 09 Apr 2014, ville.syrjala@linux.intel.com wrote:
>>> From: Deepak S <deepak.s@intel.com>
>>>
>>> v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
>>>
>>> Signed-off-by: Deepak S <deepak.s@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/intel_pm.c | 101 ++++++++++++++++++++++++++++++++++++++--
>>>   1 file changed, 98 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>>> index 0889af7..909cc0a 100644
>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>> @@ -3184,6 +3184,18 @@ static void gen6_disable_rps(struct drm_device *dev)
>>>   	gen6_disable_rps_interrupts(dev);
>>>   }
>>>   
>>> +static void cherryview_disable_rps(struct drm_device *dev)
>>> +{
>>> +	struct drm_i915_private *dev_priv = dev->dev_private;
>>> +
>>> +	I915_WRITE(GEN6_RC_CONTROL, 0);
>>> +
>>> +	if (dev_priv->vlv_pctx) {
>>> +		drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
>>> +		dev_priv->vlv_pctx = NULL;
>>> +	}
>>> +}
>>> +
>>>   static void valleyview_disable_rps(struct drm_device *dev)
>>>   {
>>>   	struct drm_i915_private *dev_priv = dev->dev_private;
>>> @@ -3551,6 +3563,29 @@ int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
>>>   	return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
>>>   }
>>>   
>>> +static void cherryview_setup_pctx(struct drm_device *dev)
>>> +{
>>> +	struct drm_i915_private *dev_priv = dev->dev_private;
>>> +	unsigned long pctx_paddr;
>>> +	struct i915_gtt *gtt = &dev_priv->gtt;
>>> +	u32 pcbr;
>>> +	int pctx_size = 32*1024;
>>> +
>>> +	pcbr = I915_READ(VLV_PCBR);
>>> +	if (pcbr >> 12 == 0) {
>>> +		/*
>>> +		 * From the Gunit register HAS:
>>> +		 * The Gfx driver is expected to program this register and ensure
>>> +		 * proper allocation within Gfx stolen memory.  For example, this
>>> +		 * register should be programmed such than the PCBR range does not
>>> +		 * overlap with other relevant ranges.
>>> +		 */
>>> +		pctx_paddr = (dev_priv->mm.stolen_base + gtt->stolen_size - pctx_size);
>>> +		I915_WRITE(VLV_PCBR, pctx_paddr);
>>> +	}
>>> +}
>>> +
>>> +
>>>   static void valleyview_setup_pctx(struct drm_device *dev)
>>>   {
>>>   	struct drm_i915_private *dev_priv = dev->dev_private;
>>> @@ -3595,6 +3630,61 @@ out:
>>>   	dev_priv->vlv_pctx = pctx;
>>>   }
>>>   
>>> +static void cherryview_enable_rps(struct drm_device *dev)
>>> +{
>>> +	struct drm_i915_private *dev_priv = dev->dev_private;
>>> +	struct intel_ring_buffer *ring;
>>> +	u32 gtfifodbg, rc6_mode = 0, pcbr;
>>> +	int i;
>>> +
>>> +	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
>>> +
>>> +	if ((gtfifodbg = I915_READ(GTFIFODBG))) {
>> Please no assignment within if; this one's easy to split.
>>
>> There's a bunch of other checkpatch issues in the series; I don't
>> personally care about most of them but you might want to run it and see
>> if you want to do something about it.
> Looks like it's a straight up copy-paste from the gen6 and vlv code. So
> someone might want to clean those out as well.
>
> And maybe we should just drop this check for CHV since the GT wake FIFO
> isn't used anymore. But I'm not sure if the register still hold something
> sensible or not.
>
>> BR,
>> Jani.
>>
>>
>>> +		DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
>>> +				 gtfifodbg);
>>> +		I915_WRITE(GTFIFODBG, gtfifodbg);
>>> +	}
>>> +
>>> +	cherryview_setup_pctx(dev);
>>> +
>>> +	/* 1a & 1b: Get forcewake during program sequence. Although the driver
>>> +	 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
>>> +	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
>>> +
>>> +	/* 2a: Program RC6 thresholds.*/
>>> +	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
>>> +	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
>>> +	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
>>> +
>>> +	for_each_ring(ring, dev_priv, i)
>>> +		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
>>> +
>>> +	I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
>>> +
>>> +	/* allows RC6 residency counter to work */
>>> +	I915_WRITE(VLV_COUNTER_CONTROL,
>>> +		   _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
>>> +				      VLV_MEDIA_RC6_COUNT_EN |
>>> +				      VLV_RENDER_RC6_COUNT_EN));
>>> +
>>> +	/* Todo: If BIOS has not configured PCBR
>>> +	 *       then allocate in BIOS Reserved */
>>> +
>>> +	/* For now we assume BIOS is allocating and populating the PCBR  */
>>> +	pcbr = I915_READ(VLV_PCBR);
>>> +
>>> +	DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
>>> +
>>> +	/* 3: Enable RC6 */
>>> +	if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE & (pcbr >> 12))
>>> +		rc6_mode = GEN6_RC_CTL_EI_MODE(1) | VLV_RC_CTL_CTX_RST_PARALLEL;
>>> +
>>> +	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
>>> +
>>> +	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
>>> +}
>>> +
>>> +
>>>   static void valleyview_enable_rps(struct drm_device *dev)
>>>   {
>>>   	struct drm_i915_private *dev_priv = dev->dev_private;
>>> @@ -4437,7 +4527,9 @@ void intel_disable_gt_powersave(struct drm_device *dev)
>>>   		cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
>>>   		cancel_work_sync(&dev_priv->rps.work);
>>>   		mutex_lock(&dev_priv->rps.hw_lock);
>>> -		if (IS_VALLEYVIEW(dev))
>>> +		if (IS_CHERRYVIEW(dev))
>>> +			cherryview_disable_rps(dev);
>>> +		else if (IS_VALLEYVIEW(dev))
>>>   			valleyview_disable_rps(dev);
>>>   		else
>>>   			gen6_disable_rps(dev);
>>> @@ -4455,7 +4547,9 @@ static void intel_gen6_powersave_work(struct work_struct *work)
>>>   
>>>   	mutex_lock(&dev_priv->rps.hw_lock);
>>>   
>>> -	if (IS_VALLEYVIEW(dev)) {
>>> +	if (IS_CHERRYVIEW(dev)) {
>>> +		cherryview_enable_rps(dev);
>>> +	} else if (IS_VALLEYVIEW(dev)) {
>>>   		valleyview_enable_rps(dev);
>>>   	} else if (IS_BROADWELL(dev)) {
>>>   		gen8_enable_rps(dev);
>>> @@ -4476,7 +4570,7 @@ void intel_enable_gt_powersave(struct drm_device *dev)
>>>   		ironlake_enable_drps(dev);
>>>   		ironlake_enable_rc6(dev);
>>>   		intel_init_emon(dev);
>>> -	} else if (IS_GEN6(dev) || IS_GEN7(dev)) {
>>> +	} else if (INTEL_INFO(dev)->gen >= 6) {
>>>   		if (IS_VALLEYVIEW(dev))
>>>   			valleyview_setup_pctx(dev);
>>>   		/*
>>> @@ -5051,6 +5145,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>>>   		dev_priv->mem_freq = 1333;
>>>   		break;
>>>   	}
>>> +
>>>   	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
>>>   
>>>   	dev_priv->vlv_cdclk_freq = valleyview_cur_cdclk(dev_priv);
>>> -- 
>>> 1.8.3.2
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> -- 
>> Jani Nikula, Intel Open Source Technology Center

Re: [PATCH 30/71] drm/i915/chv: Enable PM interrupts when we in CHV turbo initialize sequence.

[Deepak S]

On Thursday 10 April 2014 04:03 AM, Ben Widawsky wrote:
> On Thu, Apr 10, 2014 at 12:47:01AM +0530, Deepak S wrote:
>> On Wednesday 09 April 2014 06:36 PM, Chris Wilson wrote:
>>> On Wed, Apr 09, 2014 at 01:28:28PM +0300, ville.syrjala@linux.intel.com wrote:
>>>> +static void gen8_enable_rps_interrupts(struct drm_device *dev)
>>>> +{
>>>> +	struct drm_i915_private *dev_priv = dev->dev_private;
>>>> +
>>>> +	/* Clear out any stale interrupts first */
>>>> +	spin_lock_irq(&dev_priv->irq_lock);
>>>> +	WARN_ON(dev_priv->rps.pm_iir);
>>>> +	I915_WRITE(GEN8_GT_IIR(2), I915_READ(GEN8_GT_IIR(2)));
>>>> +	dev_priv->pm_irq_mask &= ~GEN6_PM_RPS_EVENTS;
>>>> +	I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask);
>>>> +	spin_unlock_irq(&dev_priv->irq_lock);
>>>> +
>>>> +	I915_WRITE(GEN8_GT_IER(2), GEN6_PM_RPS_EVENTS);
>>>> +	/* only unmask PM interrupts we need. Mask all others. */
>>>> +	I915_WRITE(GEN6_PMINTRMSK, ~GEN6_PM_RPS_EVENTS);
>>> PMINTRMSK handling is now a part of set_rps (and so this line is
>>> redundant).
>>> -Chris
>> Thanks Chris. I will make the changes based on the current nightly code
>>
>>
> I think my patch kept up with this, but I too am not sure. In either
> case feel free to reuse, copy, or review that one.
>
> I don't think I've mailed out the very latest version, but I am pretty
> sure I mailed out after the last painful rebase (and it's tested on
> BDW).
>
> http://cgit.freedesktop.org/~bwidawsk/drm-intel/commit/?h=bdw-rc6&id=80fbe001fc4ba38c41db3cec177c9157b2613c3c
>
Thanks Ben. I will reuse the patches submitted by you

Re: [PATCH 00/71] drm/i915/chv: Add Cherryview support

[S, Deepak]

On 4/10/2014 7:34 PM, Ville Syrjälä wrote:
> On Thu, Apr 10, 2014 at 04:41:10PM +0300, Jani Nikula wrote:
>> On Thu, 10 Apr 2014, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
>>> On Thu, Apr 10, 2014 at 09:31:39AM +0530, S, Deepak wrote:
>>>>
>>>>
>>>> On 4/10/2014 1:30 AM, Daniel Vetter wrote:
>>>>> On Thu, Apr 10, 2014 at 12:42:42AM +0530, S, Deepak wrote:
>>>>>>
>>>>>>
>>>>>> On 4/9/2014 10:23 PM, Daniel Vetter wrote:
>>>>>>> On Wed, Apr 09, 2014 at 06:05:27PM +0300, Ville Syrjälä wrote:
>>>>>>>> On Wed, Apr 09, 2014 at 02:30:52PM +0000, S, Deepak wrote:
>>>>>>>>> Hi Ville,
>>>>>>>>>
>>>>>>>>> I am Ok with  cleaning up and pushing the Code. Can you please tell me
>>>>>>>>> when we need to start pushing the code and branch to use
>>>>>>>>> (drm-intel-next)?
>>>>>>>>
>>>>>>>> Well you can consider it pushed now that it's in the open. The patches
>>>>>>>> just need a bit of extra polish I think. Well, unless you're planning
>>>>>>>> a full blown rewrite of the code ;)
>>>>>>>>
>>>>>>>> I guess you need to take into consideration whatever bdw rc6/rps patches
>>>>>>>> are still in flight, but since you've been doing some review there I
>>>>>>>> think you have a better idea than I do how things are progressing.
>>>>>>>>
>>>>>>>> I always work on top of nightly, so I guess that's a good choice :)
>>>>>>>
>>>>>>> Yes, -nightly is always the recommended branch to base upstream patches
>>>>>>> on. I'll sort out the conflict mess (or well, try to) if it doesn't apply
>>>>>>> to plain dinq or some other branch. drm-intel-next tends to be too
>>>>>>> outdated ;-)
>>>>>>> -Daniel
>>>>>>
>>>>>> Hi Daniel/Ville.
>>>>>>
>>>>>> Some of the patches are lined up for squashing right? So you want me
>>>>>> to work on this patches to align to upstream code and resubmit it to
>>>>>> same email thread?
>>>>>
>>>>> Hm, I expect this chv thread to become a bit mess really quickly tbh ;-)
>>>>> And since we don't have chv merged yet there's not really a baseline to do
>>>>> this on top.
>>>>>
>>>>> I guess the simplest approach would be for you to grab ville's chv tree,
>>>>> squash in the patches as discussed and then just starting on polishing
>>>>> your chv patches. Then as I pull in patches from this series you can drop
>>>>> them from yours. A bit messy, but I don't see any other approach really.
>>>>>
>>>>> Note that a pile of people are signed up to review this, so maybe hold off
>>>>> a bit until the review for your patches have been done.
>>>>> -Daniel
>>>>
>>>> Thanks Daniel.
>>>> Ville can you please share your chv tree details?
>>>
>>> I rebased the lot and pushed here:
>>> git://gitorious.org/vsyrjala/linux.git chv_rebase
>>
>> /me being lazy, did you squash/reorder patches, i.e. do the patch #
>> assignments [1] for review still apply?
>
> The numbers would get shifted around a bit due to two these two patches
> already getting merged:
>   drm/i915/chv: IS_BROADWELL() should not be true for Cherryview
>   drm/i915/chv: Add IS_CHERRYVIEW() macro
>
> And this patch got dropped as it no longer applies:
>   drm/i915/chv: Add plane C support
>
> Apart from that no reordering/squashing.
>
>>
>> Jani.
>>
>>
>> [1] http://mid.gmane.org/20140410110857.GW18465@intel.com
>>
>>>
>>> --
>>> Ville Syrjälä
>>> Intel OTC
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>> --
>> Jani Nikula, Intel Open Source Technology Center

Hi Ville,

Have you already squashed some of the RC6/turbo patches? Or you want me 
to do it as part of RC6/RPS rework patches submission.

Thanks
Deepak

Re: [PATCH 49/71] drm/i915/chv: Add CHV display support

[Imre Deak]

[-- Attachment #1.1: Type: text/plain, Size: 3836 bytes --]

On Wed, 2014-04-09 at 13:28 +0300, ville.syrjala@linux.intel.com wrote:
> From: Rafael Barbalho <rafael.barbalho@intel.com>
> 
> Add support for the third pipe in cherrview
> 
> Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
> [vsyrjala: slightly massaged the patch]
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

With the formatting fix from Jani:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.c |  7 +++++++
>  drivers/gpu/drm/i915/i915_reg.h | 11 ++++++++---
>  2 files changed, 15 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 2415fa2..c5e9fa8 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -49,6 +49,12 @@ static struct drm_driver driver;
>  	.dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \
>  	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
>  
> +#define GEN_CHV_PIPEOFFSETS \
> +       .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, CHV_PIPE_C_OFFSET }, \
> +       .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, CHV_TRANSCODER_C_OFFSET, }, \
> +       .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET, CHV_DPLL_C_OFFSET }, \
> +       .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET, CHV_DPLL_C_MD_OFFSET }, \
> +       .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, CHV_PALETTE_C_OFFSET }
>  
>  static const struct intel_device_info intel_i830_info = {
>  	.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
> @@ -286,6 +292,7 @@ static const struct intel_device_info intel_cherryview_info = {
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
>  	.is_valleyview = 1,
>  	.display_mmio_offset = VLV_DISPLAY_BASE,
> +	GEN_CHV_PIPEOFFSETS,
>  };
>  
>  /*
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7587752..3831d84 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1430,6 +1430,7 @@ enum punit_power_well {
>   */
>  #define DPLL_A_OFFSET 0x6014
>  #define DPLL_B_OFFSET 0x6018
> +#define CHV_DPLL_C_OFFSET 0x6030
>  #define DPLL(pipe) (dev_priv->info.dpll_offsets[pipe] + \
>  		    dev_priv->info.display_mmio_offset)
>  
> @@ -1521,6 +1522,7 @@ enum punit_power_well {
>  
>  #define DPLL_A_MD_OFFSET 0x601c /* 965+ only */
>  #define DPLL_B_MD_OFFSET 0x6020 /* 965+ only */
> +#define CHV_DPLL_C_MD_OFFSET 0x603c
>  #define DPLL_MD(pipe) (dev_priv->info.dpll_md_offsets[pipe] + \
>  		       dev_priv->info.display_mmio_offset)
>  
> @@ -1717,6 +1719,7 @@ enum punit_power_well {
>   */
>  #define PALETTE_A_OFFSET 0xa000
>  #define PALETTE_B_OFFSET 0xa800
> +#define CHV_PALETTE_C_OFFSET 0xc000
>  #define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \
>  		       dev_priv->info.display_mmio_offset)
>  
> @@ -2206,6 +2209,7 @@ enum punit_power_well {
>  #define TRANSCODER_A_OFFSET 0x60000
>  #define TRANSCODER_B_OFFSET 0x61000
>  #define TRANSCODER_C_OFFSET 0x62000
> +#define CHV_TRANSCODER_C_OFFSET 0x63000
>  #define TRANSCODER_EDP_OFFSET 0x6f000
>  
>  #define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
> @@ -3533,9 +3537,10 @@ enum punit_power_well {
>  #define PIPESTAT_INT_ENABLE_MASK		0x7fff0000
>  #define PIPESTAT_INT_STATUS_MASK		0x0000ffff
>  
> -#define PIPE_A_OFFSET	0x70000
> -#define PIPE_B_OFFSET	0x71000
> -#define PIPE_C_OFFSET	0x72000
> +#define PIPE_A_OFFSET		0x70000
> +#define PIPE_B_OFFSET		0x71000
> +#define PIPE_C_OFFSET		0x72000
> +#define CHV_PIPE_C_OFFSET	0x74000
>  /*
>   * There's actually no pipe EDP. Some pipe registers have
>   * simply shifted from the pipe to the transcoder, while


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_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 00/71] drm/i915/chv: Add Cherryview support

[Ville Syrjälä]

On Tue, Apr 15, 2014 at 09:19:27PM +0530, S, Deepak wrote:
> 
> 
> On 4/10/2014 7:34 PM, Ville Syrjälä wrote:
> > On Thu, Apr 10, 2014 at 04:41:10PM +0300, Jani Nikula wrote:
> >> On Thu, 10 Apr 2014, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> >>> On Thu, Apr 10, 2014 at 09:31:39AM +0530, S, Deepak wrote:
> >>>>
> >>>>
> >>>> On 4/10/2014 1:30 AM, Daniel Vetter wrote:
> >>>>> On Thu, Apr 10, 2014 at 12:42:42AM +0530, S, Deepak wrote:
> >>>>>>
> >>>>>>
> >>>>>> On 4/9/2014 10:23 PM, Daniel Vetter wrote:
> >>>>>>> On Wed, Apr 09, 2014 at 06:05:27PM +0300, Ville Syrjälä wrote:
> >>>>>>>> On Wed, Apr 09, 2014 at 02:30:52PM +0000, S, Deepak wrote:
> >>>>>>>>> Hi Ville,
> >>>>>>>>>
> >>>>>>>>> I am Ok with  cleaning up and pushing the Code. Can you please tell me
> >>>>>>>>> when we need to start pushing the code and branch to use
> >>>>>>>>> (drm-intel-next)?
> >>>>>>>>
> >>>>>>>> Well you can consider it pushed now that it's in the open. The patches
> >>>>>>>> just need a bit of extra polish I think. Well, unless you're planning
> >>>>>>>> a full blown rewrite of the code ;)
> >>>>>>>>
> >>>>>>>> I guess you need to take into consideration whatever bdw rc6/rps patches
> >>>>>>>> are still in flight, but since you've been doing some review there I
> >>>>>>>> think you have a better idea than I do how things are progressing.
> >>>>>>>>
> >>>>>>>> I always work on top of nightly, so I guess that's a good choice :)
> >>>>>>>
> >>>>>>> Yes, -nightly is always the recommended branch to base upstream patches
> >>>>>>> on. I'll sort out the conflict mess (or well, try to) if it doesn't apply
> >>>>>>> to plain dinq or some other branch. drm-intel-next tends to be too
> >>>>>>> outdated ;-)
> >>>>>>> -Daniel
> >>>>>>
> >>>>>> Hi Daniel/Ville.
> >>>>>>
> >>>>>> Some of the patches are lined up for squashing right? So you want me
> >>>>>> to work on this patches to align to upstream code and resubmit it to
> >>>>>> same email thread?
> >>>>>
> >>>>> Hm, I expect this chv thread to become a bit mess really quickly tbh ;-)
> >>>>> And since we don't have chv merged yet there's not really a baseline to do
> >>>>> this on top.
> >>>>>
> >>>>> I guess the simplest approach would be for you to grab ville's chv tree,
> >>>>> squash in the patches as discussed and then just starting on polishing
> >>>>> your chv patches. Then as I pull in patches from this series you can drop
> >>>>> them from yours. A bit messy, but I don't see any other approach really.
> >>>>>
> >>>>> Note that a pile of people are signed up to review this, so maybe hold off
> >>>>> a bit until the review for your patches have been done.
> >>>>> -Daniel
> >>>>
> >>>> Thanks Daniel.
> >>>> Ville can you please share your chv tree details?
> >>>
> >>> I rebased the lot and pushed here:
> >>> git://gitorious.org/vsyrjala/linux.git chv_rebase
> >>
> >> /me being lazy, did you squash/reorder patches, i.e. do the patch #
> >> assignments [1] for review still apply?
> >
> > The numbers would get shifted around a bit due to two these two patches
> > already getting merged:
> >   drm/i915/chv: IS_BROADWELL() should not be true for Cherryview
> >   drm/i915/chv: Add IS_CHERRYVIEW() macro
> >
> > And this patch got dropped as it no longer applies:
> >   drm/i915/chv: Add plane C support
> >
> > Apart from that no reordering/squashing.
> >
> >>
> >> Jani.
> >>
> >>
> >> [1] http://mid.gmane.org/20140410110857.GW18465@intel.com
> >>
> >>>
> >>> --
> >>> Ville Syrjälä
> >>> Intel OTC
> >>> _______________________________________________
> >>> Intel-gfx mailing list
> >>> Intel-gfx@lists.freedesktop.org
> >>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >>
> >> --
> >> Jani Nikula, Intel Open Source Technology Center
> 
> Hi Ville,
> 
> Have you already squashed some of the RC6/turbo patches? Or you want me 
> to do it as part of RC6/RPS rework patches submission.

No, I didn't do it. If you can take care of it that'd be great.

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 00/71] drm/i915/chv: Add Cherryview support

[S, Deepak]

On 4/15/2014 9:46 PM, Ville Syrjälä wrote:
> On Tue, Apr 15, 2014 at 09:19:27PM +0530, S, Deepak wrote:
>>
>>
>> On 4/10/2014 7:34 PM, Ville Syrjälä wrote:
>>> On Thu, Apr 10, 2014 at 04:41:10PM +0300, Jani Nikula wrote:
>>>> On Thu, 10 Apr 2014, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
>>>>> On Thu, Apr 10, 2014 at 09:31:39AM +0530, S, Deepak wrote:
>>>>>>
>>>>>>
>>>>>> On 4/10/2014 1:30 AM, Daniel Vetter wrote:
>>>>>>> On Thu, Apr 10, 2014 at 12:42:42AM +0530, S, Deepak wrote:
>>>>>>>>
>>>>>>>>
>>>>>>>> On 4/9/2014 10:23 PM, Daniel Vetter wrote:
>>>>>>>>> On Wed, Apr 09, 2014 at 06:05:27PM +0300, Ville Syrjälä wrote:
>>>>>>>>>> On Wed, Apr 09, 2014 at 02:30:52PM +0000, S, Deepak wrote:
>>>>>>>>>>> Hi Ville,
>>>>>>>>>>>
>>>>>>>>>>> I am Ok with  cleaning up and pushing the Code. Can you please tell me
>>>>>>>>>>> when we need to start pushing the code and branch to use
>>>>>>>>>>> (drm-intel-next)?
>>>>>>>>>>
>>>>>>>>>> Well you can consider it pushed now that it's in the open. The patches
>>>>>>>>>> just need a bit of extra polish I think. Well, unless you're planning
>>>>>>>>>> a full blown rewrite of the code ;)
>>>>>>>>>>
>>>>>>>>>> I guess you need to take into consideration whatever bdw rc6/rps patches
>>>>>>>>>> are still in flight, but since you've been doing some review there I
>>>>>>>>>> think you have a better idea than I do how things are progressing.
>>>>>>>>>>
>>>>>>>>>> I always work on top of nightly, so I guess that's a good choice :)
>>>>>>>>>
>>>>>>>>> Yes, -nightly is always the recommended branch to base upstream patches
>>>>>>>>> on. I'll sort out the conflict mess (or well, try to) if it doesn't apply
>>>>>>>>> to plain dinq or some other branch. drm-intel-next tends to be too
>>>>>>>>> outdated ;-)
>>>>>>>>> -Daniel
>>>>>>>>
>>>>>>>> Hi Daniel/Ville.
>>>>>>>>
>>>>>>>> Some of the patches are lined up for squashing right? So you want me
>>>>>>>> to work on this patches to align to upstream code and resubmit it to
>>>>>>>> same email thread?
>>>>>>>
>>>>>>> Hm, I expect this chv thread to become a bit mess really quickly tbh ;-)
>>>>>>> And since we don't have chv merged yet there's not really a baseline to do
>>>>>>> this on top.
>>>>>>>
>>>>>>> I guess the simplest approach would be for you to grab ville's chv tree,
>>>>>>> squash in the patches as discussed and then just starting on polishing
>>>>>>> your chv patches. Then as I pull in patches from this series you can drop
>>>>>>> them from yours. A bit messy, but I don't see any other approach really.
>>>>>>>
>>>>>>> Note that a pile of people are signed up to review this, so maybe hold off
>>>>>>> a bit until the review for your patches have been done.
>>>>>>> -Daniel
>>>>>>
>>>>>> Thanks Daniel.
>>>>>> Ville can you please share your chv tree details?
>>>>>
>>>>> I rebased the lot and pushed here:
>>>>> git://gitorious.org/vsyrjala/linux.git chv_rebase
>>>>
>>>> /me being lazy, did you squash/reorder patches, i.e. do the patch #
>>>> assignments [1] for review still apply?
>>>
>>> The numbers would get shifted around a bit due to two these two patches
>>> already getting merged:
>>>    drm/i915/chv: IS_BROADWELL() should not be true for Cherryview
>>>    drm/i915/chv: Add IS_CHERRYVIEW() macro
>>>
>>> And this patch got dropped as it no longer applies:
>>>    drm/i915/chv: Add plane C support
>>>
>>> Apart from that no reordering/squashing.
>>>
>>>>
>>>> Jani.
>>>>
>>>>
>>>> [1] http://mid.gmane.org/20140410110857.GW18465@intel.com
>>>>
>>>>>
>>>>> --
>>>>> Ville Syrjälä
>>>>> Intel OTC
>>>>> _______________________________________________
>>>>> Intel-gfx mailing list
>>>>> Intel-gfx@lists.freedesktop.org
>>>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>>>
>>>> --
>>>> Jani Nikula, Intel Open Source Technology Center
>>
>> Hi Ville,
>>
>> Have you already squashed some of the RC6/turbo patches? Or you want me
>> to do it as part of RC6/RPS rework patches submission.
>
> No, I didn't do it. If you can take care of it that'd be great.
Ok, I will take care of squashing the patch. I will submit all rc6/rps 
patches after cleanup.

Re: [PATCH 28/71] drm/i915/chv: Added CHV specific register read and write

[Ben Widawsky]

On Wed, Apr 09, 2014 at 01:28:26PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Deepak S <deepak.s@intel.com>
> 
> Support to individually control Media/Render well based on the register access.
> Add CHV specific write function to habdle difference between registers
> that are sadowed vs those that need forcewake even for writes.
> 
> v2: Drop write FIFO for CHV and add comman well forcewake (Ville)
> 
> Signed-off-by: Deepak S <deepak.s@intel.com>
> [vsyrjala: Move the register range macros into intel_uncore.c]
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 139 +++++++++++++++++++++++++++++++++---
>  1 file changed, 131 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 823d699..8e3c686 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -495,6 +495,31 @@ void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
>  	((reg) >= 0x22000 && (reg) < 0x24000) ||\
>  	((reg) >= 0x30000 && (reg) < 0x40000))
>  
> +#define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
> +	(((reg) >= 0x2000 && (reg) < 0x4000) ||\
> +	((reg) >= 0x5000 && (reg) < 0x8000) ||\
> +	((reg) >= 0x8300 && (reg) < 0x8500) ||\
> +	((reg) >= 0xB000 && (reg) < 0xC000) ||\
> +	((reg) >= 0xE000 && (reg) < 0xE800))
> +
> +#define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)\
> +	(((reg) >= 0x8800 && (reg) < 0x8900) ||\
> +	((reg) >= 0xD000 && (reg) < 0xD800) ||\
> +	((reg) >= 0x12000 && (reg) < 0x14000) ||\
> +	((reg) >= 0x1A000 && (reg) < 0x1C000) ||\
> +	((reg) >= 0x1E800 && (reg) < 0x1EA00) ||\
> +	((reg) >= 0x30000 && (reg) < 0x40000))
> +
> +#define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)\
> +	(((reg) >= 0x4000 && (reg) < 0x5000) ||\
> +	((reg) >= 0x8000 && (reg) < 0x8300) ||\
> +	((reg) >= 0x8500 && (reg) < 0x8600) ||\
> +	((reg) >= 0x9000 && (reg) < 0xB000) ||\
> +	((reg) >= 0xC000 && (reg) < 0xc800) ||\
> +	((reg) >= 0xF000 && (reg) < 0x10000) ||\
> +	((reg) >= 0x14000 && (reg) < 0x14400) ||\
> +	((reg) >= 0x22000 && (reg) < 0x24000))
> +

To satisfy both Chris, and Ville, how about:
#define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < 0x5000)
	REG_RANGE(reg, 0x4000, 0x5000) || \
	REG_RANGE(reg, 0x8000, 0x8300) || \
	...

By the way, I spent my due diligence trying to find where these ranges
come from, and have been unable. Doc name? I should have all the docs
from Ville.

I can't speak for the code generated, either.

>  static void
>  ilk_dummy_write(struct drm_i915_private *dev_priv)
>  {
> @@ -587,7 +612,48 @@ vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
>  	REG_READ_FOOTER; \
>  }
>  
> +#define __chv_read(x) \
> +static u##x \
> +chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
> +	unsigned fwengine = 0; \
> +	REG_READ_HEADER(x); \
> +	if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
> +		fwengine = FORCEWAKE_RENDER; \
> +	} \
> +	else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
> +		fwengine = FORCEWAKE_MEDIA; \
> +	} \
> +	else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
> +		fwengine = FORCEWAKE_ALL; \
> +	} \
> +	if (FORCEWAKE_RENDER & fwengine) { \
> +		if (dev_priv->uncore.fw_rendercount++ == 0) \
> +			(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
> +								fwengine); \
> +	} \
> +	if (FORCEWAKE_MEDIA & fwengine) { \
> +		if (dev_priv->uncore.fw_mediacount++ == 0) \
> +			(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
> +								fwengine); \
> +	} \
> +	val = __raw_i915_read##x(dev_priv, reg); \
> +	if (FORCEWAKE_RENDER & fwengine) { \
> +		if (dev_priv->uncore.fw_rendercount++ == 0) \
> +			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
> +								fwengine); \
> +	} \
> +	if (FORCEWAKE_MEDIA & fwengine) { \
> +		if (dev_priv->uncore.fw_mediacount++ == 0) \
> +			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
> +								fwengine); \
> +	} \
> +	REG_READ_FOOTER; \
> +}
>  
> +__chv_read(8)
> +__chv_read(16)
> +__chv_read(32)
> +__chv_read(64)
>  __vlv_read(8)
>  __vlv_read(16)
>  __vlv_read(32)
> @@ -605,6 +671,7 @@ __gen4_read(16)
>  __gen4_read(32)
>  __gen4_read(64)
>  
> +#undef __chv_read
>  #undef __vlv_read
>  #undef __gen6_read
>  #undef __gen5_read
> @@ -709,6 +776,49 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
>  	REG_WRITE_FOOTER; \
>  }
>  
> +#define __chv_write(x) \
> +static void \
> +chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
> +	unsigned fwengine = 0; \
> +	bool __needs_put = !is_gen8_shadowed(dev_priv, reg); \
> +	REG_WRITE_HEADER; \
> +	if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
> +		fwengine = FORCEWAKE_RENDER; \
> +	} \
> +	else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
> +		fwengine = FORCEWAKE_MEDIA; \
> +	} \
> +	else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
> +		fwengine = FORCEWAKE_ALL; \
> +	} \
> +	if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \
> +			if (dev_priv->uncore.fw_rendercount++ == 0) \
> +				(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
> +									fwengine); \
> +	} \
> +	if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \
> +		if (dev_priv->uncore.fw_mediacount++ == 0) \
> +			(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
> +								fwengine); \
> +	} \
> +	__raw_i915_write##x(dev_priv, reg, val); \
> +	if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \
> +			if (dev_priv->uncore.fw_rendercount++ == 0) \
> +				(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
> +									fwengine); \
> +	} \
> +	if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \
> +		if (dev_priv->uncore.fw_mediacount++ == 0) \
> +			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
> +								fwengine); \
> +	} \
> +	REG_WRITE_FOOTER; \
> +}

Feels like this would be a lot neater if you let force_wake_put() handle
this complexity. I guess our force_wake_funcs can't handle count. In
that case we could even share the gen8_write family of functions. Was
there some reason this can't work? (Again, forgive laziness)

> +
> +__chv_write(8)
> +__chv_write(16)
> +__chv_write(32)
> +__chv_write(64)

Similar to broadwell (my bad, I know), we probably only actually want to
do this for read/write32. So we potentially could reduce the obj size by
only doing it for that.

>  __gen8_write(8)
>  __gen8_write(16)
>  __gen8_write(32)
> @@ -730,6 +840,7 @@ __gen4_write(16)
>  __gen4_write(32)
>  __gen4_write(64)
>  
> +#undef __chv_write
>  #undef __gen8_write
>  #undef __hsw_write
>  #undef __gen6_write
> @@ -793,14 +904,26 @@ void intel_uncore_init(struct drm_device *dev)
>  
>  	switch (INTEL_INFO(dev)->gen) {
>  	default:
> -		dev_priv->uncore.funcs.mmio_writeb  = gen8_write8;
> -		dev_priv->uncore.funcs.mmio_writew  = gen8_write16;
> -		dev_priv->uncore.funcs.mmio_writel  = gen8_write32;
> -		dev_priv->uncore.funcs.mmio_writeq  = gen8_write64;
> -		dev_priv->uncore.funcs.mmio_readb  = gen6_read8;
> -		dev_priv->uncore.funcs.mmio_readw  = gen6_read16;
> -		dev_priv->uncore.funcs.mmio_readl  = gen6_read32;
> -		dev_priv->uncore.funcs.mmio_readq  = gen6_read64;
> +		if (IS_CHERRYVIEW(dev)) {
> +			dev_priv->uncore.funcs.mmio_writeb  = chv_write8;
> +			dev_priv->uncore.funcs.mmio_writew  = chv_write16;
> +			dev_priv->uncore.funcs.mmio_writel  = chv_write32;
> +			dev_priv->uncore.funcs.mmio_writeq  = chv_write64;
> +			dev_priv->uncore.funcs.mmio_readb  = chv_read8;
> +			dev_priv->uncore.funcs.mmio_readw  = chv_read16;
> +			dev_priv->uncore.funcs.mmio_readl  = chv_read32;
> +			dev_priv->uncore.funcs.mmio_readq  = chv_read64;
> +
> +		} else {
> +			dev_priv->uncore.funcs.mmio_writeb  = gen8_write8;
> +			dev_priv->uncore.funcs.mmio_writew  = gen8_write16;
> +			dev_priv->uncore.funcs.mmio_writel  = gen8_write32;
> +			dev_priv->uncore.funcs.mmio_writeq  = gen8_write64;
> +			dev_priv->uncore.funcs.mmio_readb  = gen6_read8;
> +			dev_priv->uncore.funcs.mmio_readw  = gen6_read16;
> +			dev_priv->uncore.funcs.mmio_readl  = gen6_read32;
> +			dev_priv->uncore.funcs.mmio_readq  = gen6_read64;
> +		}
>  		break;
>  	case 7:
>  	case 6:
> -- 
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ben Widawsky, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 28/71] drm/i915/chv: Added CHV specific register read and write

[Deepak S]

On Friday 18 April 2014 05:58 AM, Ben Widawsky wrote:
> On Wed, Apr 09, 2014 at 01:28:26PM +0300, ville.syrjala@linux.intel.com wrote:
>> From: Deepak S <deepak.s@intel.com>
>>
>> Support to individually control Media/Render well based on the register access.
>> Add CHV specific write function to habdle difference between registers
>> that are sadowed vs those that need forcewake even for writes.
>>
>> v2: Drop write FIFO for CHV and add comman well forcewake (Ville)
>>
>> Signed-off-by: Deepak S <deepak.s@intel.com>
>> [vsyrjala: Move the register range macros into intel_uncore.c]
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_uncore.c | 139 +++++++++++++++++++++++++++++++++---
>>   1 file changed, 131 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
>> index 823d699..8e3c686 100644
>> --- a/drivers/gpu/drm/i915/intel_uncore.c
>> +++ b/drivers/gpu/drm/i915/intel_uncore.c
>> @@ -495,6 +495,31 @@ void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
>>   	((reg) >= 0x22000 && (reg) < 0x24000) ||\
>>   	((reg) >= 0x30000 && (reg) < 0x40000))
>>   
>> +#define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
>> +	(((reg) >= 0x2000 && (reg) < 0x4000) ||\
>> +	((reg) >= 0x5000 && (reg) < 0x8000) ||\
>> +	((reg) >= 0x8300 && (reg) < 0x8500) ||\
>> +	((reg) >= 0xB000 && (reg) < 0xC000) ||\
>> +	((reg) >= 0xE000 && (reg) < 0xE800))
>> +
>> +#define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)\
>> +	(((reg) >= 0x8800 && (reg) < 0x8900) ||\
>> +	((reg) >= 0xD000 && (reg) < 0xD800) ||\
>> +	((reg) >= 0x12000 && (reg) < 0x14000) ||\
>> +	((reg) >= 0x1A000 && (reg) < 0x1C000) ||\
>> +	((reg) >= 0x1E800 && (reg) < 0x1EA00) ||\
>> +	((reg) >= 0x30000 && (reg) < 0x40000))
>> +
>> +#define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)\
>> +	(((reg) >= 0x4000 && (reg) < 0x5000) ||\
>> +	((reg) >= 0x8000 && (reg) < 0x8300) ||\
>> +	((reg) >= 0x8500 && (reg) < 0x8600) ||\
>> +	((reg) >= 0x9000 && (reg) < 0xB000) ||\
>> +	((reg) >= 0xC000 && (reg) < 0xc800) ||\
>> +	((reg) >= 0xF000 && (reg) < 0x10000) ||\
>> +	((reg) >= 0x14000 && (reg) < 0x14400) ||\
>> +	((reg) >= 0x22000 && (reg) < 0x24000))
>> +
> To satisfy both Chris, and Ville, how about:
> #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < 0x5000)
> 	REG_RANGE(reg, 0x4000, 0x5000) || \
> 	REG_RANGE(reg, 0x8000, 0x8300) || \
> 	...
>
> By the way, I spent my due diligence trying to find where these ranges
> come from, and have been unable. Doc name? I should have all the docs
> from Ville.
>
> I can't speak for the code generated, either.
>
hmm Ok, I will try to re factor this code. I will send the doc name

>>   static void
>>   ilk_dummy_write(struct drm_i915_private *dev_priv)
>>   {
>> @@ -587,7 +612,48 @@ vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
>>   	REG_READ_FOOTER; \
>>   }
>>   
>> +#define __chv_read(x) \
>> +static u##x \
>> +chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
>> +	unsigned fwengine = 0; \
>> +	REG_READ_HEADER(x); \
>> +	if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
>> +		fwengine = FORCEWAKE_RENDER; \
>> +	} \
>> +	else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
>> +		fwengine = FORCEWAKE_MEDIA; \
>> +	} \
>> +	else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
>> +		fwengine = FORCEWAKE_ALL; \
>> +	} \
>> +	if (FORCEWAKE_RENDER & fwengine) { \
>> +		if (dev_priv->uncore.fw_rendercount++ == 0) \
>> +			(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
>> +								fwengine); \
>> +	} \
>> +	if (FORCEWAKE_MEDIA & fwengine) { \
>> +		if (dev_priv->uncore.fw_mediacount++ == 0) \
>> +			(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
>> +								fwengine); \
>> +	} \
>> +	val = __raw_i915_read##x(dev_priv, reg); \
>> +	if (FORCEWAKE_RENDER & fwengine) { \
>> +		if (dev_priv->uncore.fw_rendercount++ == 0) \
>> +			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
>> +								fwengine); \
>> +	} \
>> +	if (FORCEWAKE_MEDIA & fwengine) { \
>> +		if (dev_priv->uncore.fw_mediacount++ == 0) \
>> +			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
>> +								fwengine); \
>> +	} \
>> +	REG_READ_FOOTER; \
>> +}
>>   
>> +__chv_read(8)
>> +__chv_read(16)
>> +__chv_read(32)
>> +__chv_read(64)
>>   __vlv_read(8)
>>   __vlv_read(16)
>>   __vlv_read(32)
>> @@ -605,6 +671,7 @@ __gen4_read(16)
>>   __gen4_read(32)
>>   __gen4_read(64)
>>   
>> +#undef __chv_read
>>   #undef __vlv_read
>>   #undef __gen6_read
>>   #undef __gen5_read
>> @@ -709,6 +776,49 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
>>   	REG_WRITE_FOOTER; \
>>   }
>>   
>> +#define __chv_write(x) \
>> +static void \
>> +chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
>> +	unsigned fwengine = 0; \
>> +	bool __needs_put = !is_gen8_shadowed(dev_priv, reg); \
>> +	REG_WRITE_HEADER; \
>> +	if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
>> +		fwengine = FORCEWAKE_RENDER; \
>> +	} \
>> +	else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
>> +		fwengine = FORCEWAKE_MEDIA; \
>> +	} \
>> +	else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
>> +		fwengine = FORCEWAKE_ALL; \
>> +	} \
>> +	if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \
>> +			if (dev_priv->uncore.fw_rendercount++ == 0) \
>> +				(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
>> +									fwengine); \
>> +	} \
>> +	if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \
>> +		if (dev_priv->uncore.fw_mediacount++ == 0) \
>> +			(dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
>> +								fwengine); \
>> +	} \
>> +	__raw_i915_write##x(dev_priv, reg, val); \
>> +	if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \
>> +			if (dev_priv->uncore.fw_rendercount++ == 0) \
>> +				(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
>> +									fwengine); \
>> +	} \
>> +	if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \
>> +		if (dev_priv->uncore.fw_mediacount++ == 0) \
>> +			(dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
>> +								fwengine); \
>> +	} \
>> +	REG_WRITE_FOOTER; \
>> +}
> Feels like this would be a lot neater if you let force_wake_put() handle
> this complexity. I guess our force_wake_funcs can't handle count. In
> that case we could even share the gen8_write family of functions. Was
> there some reason this can't work? (Again, forgive laziness)

I agree, but in gen8, we have only one well, But in CHV, we want to handle the Render and Media well up/down separately which helps in power saving.

>> +
>> +__chv_write(8)
>> +__chv_write(16)
>> +__chv_write(32)
>> +__chv_write(64)
> Similar to broadwell (my bad, I know), we probably only actually want to
> do this for read/write32. So we potentially could reduce the obj size by
> only doing it for that.

we might have the 64 bit read/write also? may be for Batch buffer address read?

>>   __gen8_write(8)
>>   __gen8_write(16)
>>   __gen8_write(32)
>> @@ -730,6 +840,7 @@ __gen4_write(16)
>>   __gen4_write(32)
>>   __gen4_write(64)
>>   
>> +#undef __chv_write
>>   #undef __gen8_write
>>   #undef __hsw_write
>>   #undef __gen6_write
>> @@ -793,14 +904,26 @@ void intel_uncore_init(struct drm_device *dev)
>>   
>>   	switch (INTEL_INFO(dev)->gen) {
>>   	default:
>> -		dev_priv->uncore.funcs.mmio_writeb  = gen8_write8;
>> -		dev_priv->uncore.funcs.mmio_writew  = gen8_write16;
>> -		dev_priv->uncore.funcs.mmio_writel  = gen8_write32;
>> -		dev_priv->uncore.funcs.mmio_writeq  = gen8_write64;
>> -		dev_priv->uncore.funcs.mmio_readb  = gen6_read8;
>> -		dev_priv->uncore.funcs.mmio_readw  = gen6_read16;
>> -		dev_priv->uncore.funcs.mmio_readl  = gen6_read32;
>> -		dev_priv->uncore.funcs.mmio_readq  = gen6_read64;
>> +		if (IS_CHERRYVIEW(dev)) {
>> +			dev_priv->uncore.funcs.mmio_writeb  = chv_write8;
>> +			dev_priv->uncore.funcs.mmio_writew  = chv_write16;
>> +			dev_priv->uncore.funcs.mmio_writel  = chv_write32;
>> +			dev_priv->uncore.funcs.mmio_writeq  = chv_write64;
>> +			dev_priv->uncore.funcs.mmio_readb  = chv_read8;
>> +			dev_priv->uncore.funcs.mmio_readw  = chv_read16;
>> +			dev_priv->uncore.funcs.mmio_readl  = chv_read32;
>> +			dev_priv->uncore.funcs.mmio_readq  = chv_read64;
>> +
>> +		} else {
>> +			dev_priv->uncore.funcs.mmio_writeb  = gen8_write8;
>> +			dev_priv->uncore.funcs.mmio_writew  = gen8_write16;
>> +			dev_priv->uncore.funcs.mmio_writel  = gen8_write32;
>> +			dev_priv->uncore.funcs.mmio_writeq  = gen8_write64;
>> +			dev_priv->uncore.funcs.mmio_readb  = gen6_read8;
>> +			dev_priv->uncore.funcs.mmio_readw  = gen6_read16;
>> +			dev_priv->uncore.funcs.mmio_readl  = gen6_read32;
>> +			dev_priv->uncore.funcs.mmio_readq  = gen6_read64;
>> +		}
>>   		break;
>>   	case 7:
>>   	case 6:
>> -- 
>> 1.8.3.2

Thanks for the review. I will address the comments


>> _______________________________________________
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>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH 58/71] drm/i915/chv: Register port D encoders and connectors

[Antti Koskipää]

For 50-58, with Jani's coding style fix:

Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>

-- 
- Antti

On 04/09/2014 01:28 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      | 1 +
>  drivers/gpu/drm/i915/intel_display.c | 9 +++++++++
>  2 files changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a3957c7..4c0edb8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2435,6 +2435,7 @@ enum punit_power_well {
>  #define GEN3_SDVOC	0x61160
>  #define GEN4_HDMIB	GEN3_SDVOB
>  #define GEN4_HDMIC	GEN3_SDVOC
> +#define CHV_HDMID	0x6116C
>  #define PCH_SDVOB	0xe1140
>  #define PCH_HDMIB	PCH_SDVOB
>  #define PCH_HDMIC	0xe1150
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 798d91f..bf64e9d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11050,6 +11050,15 @@ static void intel_setup_outputs(struct drm_device *dev)
>  				intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
>  		}
>  
> +		if (IS_CHERRYVIEW(dev)) {
> +			if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
> +				intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
> +						PORT_D);
> +				if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
> +					intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
> +			}
> +		}
> +
>  		intel_dsi_init(dev);
>  	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
>  		bool found = false;
> 

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Re: [PATCH 59/71] drm/i915/chv: Fix CHV PLL state tracking

[Mika Kuoppala]

ville.syrjala@linux.intel.com writes:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Setup the pipe config dpll state correctly for CHV. Also add
> a assert_pipe_disabled() to chv_disable_pll(), and program the
> DPLL_MD registers in chv_enable_pll().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 41 +++++++++++++++++++++++-------------
>  1 file changed, 26 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index bf64e9d..d531c9d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1559,7 +1559,6 @@ static void chv_enable_pll(struct intel_crtc *crtc)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	int pipe = crtc->pipe;
>  	enum dpio_channel port = vlv_pipe_to_channel(pipe);
> -	int dpll = DPLL(crtc->pipe);
>  	u32 tmp;
>  
>  	assert_pipe_disabled(dev_priv, crtc->pipe);
> @@ -1579,20 +1578,21 @@ static void chv_enable_pll(struct intel_crtc *crtc)
>  	udelay(1);
>  
>  	/* Enable PLL */
> -	tmp = I915_READ(dpll);
> -	tmp |= DPLL_VCO_ENABLE;
> -	I915_WRITE(dpll, tmp);
> +	I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
>  
>  	/* Check PLL is locked */
> -	if (wait_for(((I915_READ(dpll) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
> +	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
>  		DRM_ERROR("PLL %d failed to lock\n", pipe);
>  
> +	/* not sure when this should be written */
> +	I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
> +	POSTING_READ(DPLL_MD(pipe));
> +
>  	/* Deassert soft data lane reset*/
>  	tmp = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
>  	tmp |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
>  	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), tmp);
>  
> -
>  	mutex_unlock(&dev_priv->dpio_lock);
>  }
>  
> @@ -1684,14 +1684,17 @@ static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
>  
>  static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
>  {
> -	int dpll = DPLL(pipe);
>  	u32 val;
>  
> -	/* Set PLL en = 0 */
> -	val = I915_READ(dpll);
> -	val &= ~DPLL_VCO_ENABLE;
> -	I915_WRITE(dpll, val);
> +	/* Make sure the pipe isn't still relying on us */
> +	assert_pipe_disabled(dev_priv, pipe);
>  
> +	/* Set PLL en = 0 */
> +	val = DPLL_SSC_REF_CLOCK_CHV;
> +	if (pipe != PIPE_A)
> +		val |= DPLL_INTEGRATED_CRI_CLK_VLV;
> +	I915_WRITE(DPLL(pipe), val);
> +	POSTING_READ(DPLL(pipe));
>  }
>  
>  void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
> @@ -5448,7 +5451,14 @@ static void chv_update_pll(struct intel_crtc *crtc)
>  	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
>  	int refclk;
>  
> -	mutex_lock(&dev_priv->dpio_lock);
> +	crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
> +		DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
> +		DPLL_VCO_ENABLE;
> +	if (pipe != PIPE_A)
> +		crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
> +
> +	crtc->config.dpll_hw_state.dpll_md =
> +		(crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
>  
>  	bestn = crtc->config.dpll.n;
>  	bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
> @@ -5460,9 +5470,10 @@ static void chv_update_pll(struct intel_crtc *crtc)
>  	/*
>  	 * Enable Refclk and SSC
>  	 */
> -	val = I915_READ(dpll_reg);
> -	val |= (DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV);
> -	I915_WRITE(dpll_reg, val);
> +	I915_WRITE(dpll_reg,
> +		   crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
> +
> +	mutex_lock(&dev_priv->dpio_lock);
>  
>  	/* Propagate soft reset to data lane reset */
>  	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
> -- 
> 1.8.3.2
>
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Re: [PATCH 64/71] drm/i915/chv: Don't use PCS group access reads

[Mika Kuoppala]

ville.syrjala@linux.intel.com writes:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Minor formatting issue in this one, newline before ';'
And next one in series fixes it.

Patches 60 - 64
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> All PCS groups access reads return 0xffffffff, so we can't use group
> access for RMW cycles. Instead target each spline separately.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h   | 14 ++++++++++++++
>  drivers/gpu/drm/i915/intel_dp.c   | 32 ++++++++++++++++++++++++--------
>  drivers/gpu/drm/i915/intel_hdmi.c | 34 +++++++++++++++++++++++++---------
>  3 files changed, 63 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4617fb3..ffed03e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -654,6 +654,13 @@ enum punit_power_well {
>  #define   DPIO_PCS_TX_LANE1_RESET	(1<<7)
>  #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
>  
> +#define _VLV_PCS01_DW0_CH0		0x200
> +#define _VLV_PCS23_DW0_CH0		0x400
> +#define _VLV_PCS01_DW0_CH1		0x2600
> +#define _VLV_PCS23_DW0_CH1		0x2800
> +#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
> +#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
> +
>  #define _VLV_PCS_DW1_CH0		0x8204
>  #define _VLV_PCS_DW1_CH1		0x8404
>  #define   CHV_PCS_REQ_SOFTRESET_EN	(1<<23)
> @@ -663,6 +670,13 @@ enum punit_power_well {
>  #define   DPIO_PCS_CLK_SOFT_RESET	(1<<5)
>  #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
>  
> +#define _VLV_PCS01_DW1_CH0		0x204
> +#define _VLV_PCS23_DW1_CH0		0x404
> +#define _VLV_PCS01_DW1_CH1		0x2604
> +#define _VLV_PCS23_DW1_CH1		0x2804
> +#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
> +#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
> +
>  #define _VLV_PCS_DW8_CH0		0x8220
>  #define _VLV_PCS_DW8_CH1		0x8420
>  #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 079e0e3..cc7bccd3 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1845,13 +1845,21 @@ static void chv_post_disable_dp(struct intel_encoder *encoder)
>  	mutex_lock(&dev_priv->dpio_lock);
>  
>  	/* Propagate soft reset to data lane reset */
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
>  	val |= CHV_PCS_REQ_SOFTRESET_EN;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
>  
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> +	val |= CHV_PCS_REQ_SOFTRESET_EN;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> +	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
>  	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
>  
>  	mutex_unlock(&dev_priv->dpio_lock);
>  }
> @@ -1983,13 +1991,21 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
>  	mutex_lock(&dev_priv->dpio_lock);
>  
>  	/* Deassert soft data lane reset*/
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
>  	val |= CHV_PCS_REQ_SOFTRESET_EN;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> +	val |= CHV_PCS_REQ_SOFTRESET_EN;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> +	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
>  
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
>  	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
>  
>  	/* Program Tx lane latency optimal setting*/
>  	for (i = 0; i < 4; i++) {
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 6a2152b..c3896b0 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1216,13 +1216,21 @@ static void chv_hdmi_post_disable(struct intel_encoder *encoder)
>  	mutex_lock(&dev_priv->dpio_lock);
>  
>  	/* Propagate soft reset to data lane reset */
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
>  	val |= CHV_PCS_REQ_SOFTRESET_EN;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val)
> -;
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> +	val |= CHV_PCS_REQ_SOFTRESET_EN;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> +	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
>  	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
>  
>  	mutex_unlock(&dev_priv->dpio_lock);
>  }
> @@ -1242,13 +1250,21 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
>  	mutex_lock(&dev_priv->dpio_lock);
>  
>  	/* Deassert soft data lane reset*/
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
>  	val |= CHV_PCS_REQ_SOFTRESET_EN;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> +	val |= CHV_PCS_REQ_SOFTRESET_EN;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> +	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
>  
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
>  	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
>  
>  	/* Program Tx latency optimal setting */
>  	for (i = 0; i < 4; i++) {
> -- 
> 1.8.3.2
>
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Re: [PATCH 41/71] drm/i915/chv: Add some workaround notes

[Paulo Zanoni]

2014-04-09 7:28 GMT-03:00  <ville.syrjala@linux.intel.com>:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We implement the following workarounds:
> * WaDisableAsyncFlipPerfMode:chv
> * WaDisableSemaphoreAndSyncFlipWait:chv (at least partially)

In the rebased version (on your gitorious tree, chv_rebase branch),
the chunk for this WA got removed. I don't know if this was an
accident or not. We need to, at least, fix the commit message.


> * WaProgramMiArbOnOffAroundMiSetContext:chv
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem.c         | 1 +
>  drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
>  3 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 84a7171..a9c33ec 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4376,6 +4376,7 @@ static int i915_gem_init_rings(struct drm_device *dev)
>                 struct intel_ring_buffer *ring;
>                 int i;
>
> +               /* WaDisableSemaphoreAndSyncFlipWait:chv */
>                 for_each_ring(ring, dev_priv, i)
>                         I915_WRITE(RING_RC_PSMI_CONTROL(ring),
>                                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 28a2b15..142df90 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -606,7 +606,7 @@ mi_set_context(struct intel_ring_buffer *ring,
>         if (ret)
>                 return ret;
>
> -       /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw */
> +       /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */

Do we really need this WA for BDW and CHV? I couldn't find them on my
docs for gen8...

Thanks,
Paulo


>         if (INTEL_INFO(ring->dev)->gen >= 7)
>                 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
>         else
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 913b8ab..24022c5 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -581,7 +581,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
>          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
>          * programmed to '1' on all products.
>          *
> -        * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw
> +        * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
>          */
>         if (INTEL_INFO(dev)->gen >= 6)
>                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
> --
> 1.8.3.2
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
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Re: [PATCH 42/71] drm/i915/chv: Implement WaDisableSamplerPowerBypass for CHV

[Paulo Zanoni]

2014-04-09 7:28 GMT-03:00  <ville.syrjala@linux.intel.com>:
> From: Rafael Barbalho <rafael.barbalho@intel.com>
>
> Cherryview also needs this WA.

At least on the chv_rebase tree, this WA is implemented for BDW but it
is not documented as pre-prod only, and its name is not there. We
should probably add a comment documenting the name and the fact that
it is also pre-prod on BDW.


>
> Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
> [vsyrjala: Looks like it's for pre-prodution hw only]
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 468fe37..60f876c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5405,6 +5405,10 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
>         /* WaDisableSDEUnitClockGating:chv */
>         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
>                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> +
> +       /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
> +       I915_WRITE(HALF_SLICE_CHICKEN3,
> +                  _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));

I could not find information anywhere if this is the correct
implementation. Can you please provide me pointers to the doc you
used? The links on Collab seem broken.

Thanks,
Paulo

>  }
>
>  static void g4x_init_clock_gating(struct drm_device *dev)
> --
> 1.8.3.2
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



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Re: [PATCH 42/71] drm/i915/chv: Implement WaDisableSamplerPowerBypass for CHV

[Ville Syrjälä]

On Fri, Apr 25, 2014 at 05:55:38PM -0300, Paulo Zanoni wrote:
> 2014-04-09 7:28 GMT-03:00  <ville.syrjala@linux.intel.com>:
> > From: Rafael Barbalho <rafael.barbalho@intel.com>
> >
> > Cherryview also needs this WA.
> 
> At least on the chv_rebase tree, this WA is implemented for BDW but it
> is not documented as pre-prod only, and its name is not there. We
> should probably add a comment documenting the name and the fact that
> it is also pre-prod on BDW.

IIRC BDW will need it even on production steppings.

I think I have a patch somewhere that add the w/a note for BDW, but I guess
I didn't post it yet.

> 
> 
> >
> > Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
> > [vsyrjala: Looks like it's for pre-prodution hw only]
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 468fe37..60f876c 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5405,6 +5405,10 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
> >         /* WaDisableSDEUnitClockGating:chv */
> >         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> >                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> > +
> > +       /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
> > +       I915_WRITE(HALF_SLICE_CHICKEN3,
> > +                  _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
> 
> I could not find information anywhere if this is the correct
> implementation. Can you please provide me pointers to the doc you
> used? The links on Collab seem broken.

Just w/a database + bspec are enough for this one.

> 
> Thanks,
> Paulo
> 
> >  }
> >
> >  static void g4x_init_clock_gating(struct drm_device *dev)
> > --
> > 1.8.3.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Paulo Zanoni

-- 
Ville Syrjälä
Intel OTC

[PATCH v2 49/71] drm/i915/chv: Add CHV display support

[ville.syrjala]

From: Rafael Barbalho <rafael.barbalho@intel.com>

Add support for the third pipe in cherrview

v2: Don't use spaces for indentation (Jani)
    Wrap long lines

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
[vsyrjala: slightly massaged the patch]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 12 ++++++++++++
 drivers/gpu/drm/i915/i915_reg.h | 11 ++++++++---
 2 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 3f57237..0fd3046 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,17 @@ static struct drm_driver driver;
 	.dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \
 	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
 
+#define GEN_CHV_PIPEOFFSETS \
+	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
+			  CHV_PIPE_C_OFFSET }, \
+	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
+			   CHV_TRANSCODER_C_OFFSET, }, \
+	.dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET, \
+			  CHV_DPLL_C_OFFSET }, \
+	.dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET, \
+			     CHV_DPLL_C_MD_OFFSET }, \
+	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
+			     CHV_PALETTE_C_OFFSET }
 
 static const struct intel_device_info intel_i830_info = {
 	.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
@@ -286,6 +297,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 	.is_valleyview = 1,
 	.display_mmio_offset = VLV_DISPLAY_BASE,
+	GEN_CHV_PIPEOFFSETS,
 };
 
 /*
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 74ac1c2..9138eff 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1440,6 +1440,7 @@ enum punit_power_well {
  */
 #define DPLL_A_OFFSET 0x6014
 #define DPLL_B_OFFSET 0x6018
+#define CHV_DPLL_C_OFFSET 0x6030
 #define DPLL(pipe) (dev_priv->info.dpll_offsets[pipe] + \
 		    dev_priv->info.display_mmio_offset)
 
@@ -1531,6 +1532,7 @@ enum punit_power_well {
 
 #define DPLL_A_MD_OFFSET 0x601c /* 965+ only */
 #define DPLL_B_MD_OFFSET 0x6020 /* 965+ only */
+#define CHV_DPLL_C_MD_OFFSET 0x603c
 #define DPLL_MD(pipe) (dev_priv->info.dpll_md_offsets[pipe] + \
 		       dev_priv->info.display_mmio_offset)
 
@@ -1727,6 +1729,7 @@ enum punit_power_well {
  */
 #define PALETTE_A_OFFSET 0xa000
 #define PALETTE_B_OFFSET 0xa800
+#define CHV_PALETTE_C_OFFSET 0xc000
 #define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \
 		       dev_priv->info.display_mmio_offset)
 
@@ -2216,6 +2219,7 @@ enum punit_power_well {
 #define TRANSCODER_A_OFFSET 0x60000
 #define TRANSCODER_B_OFFSET 0x61000
 #define TRANSCODER_C_OFFSET 0x62000
+#define CHV_TRANSCODER_C_OFFSET 0x63000
 #define TRANSCODER_EDP_OFFSET 0x6f000
 
 #define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
@@ -3543,9 +3547,10 @@ enum punit_power_well {
 #define PIPESTAT_INT_ENABLE_MASK		0x7fff0000
 #define PIPESTAT_INT_STATUS_MASK		0x0000ffff
 
-#define PIPE_A_OFFSET	0x70000
-#define PIPE_B_OFFSET	0x71000
-#define PIPE_C_OFFSET	0x72000
+#define PIPE_A_OFFSET		0x70000
+#define PIPE_B_OFFSET		0x71000
+#define PIPE_C_OFFSET		0x72000
+#define CHV_PIPE_C_OFFSET	0x74000
 /*
  * There's actually no pipe EDP. Some pipe registers have
  * simply shifted from the pipe to the transcoder, while
-- 
1.8.3.2

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[PATCH v2 53/71] drm/i915/chv: Configure crtc_mask correctly for CHV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On CHV pipe C can driver only port D, and pipes A and B can drivbe only
ports B and C. Configure the crtc_mask appropriately to reflect that.

v2: Moar braces (Jani)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c   | 9 ++++++++-
 drivers/gpu/drm/i915/intel_hdmi.c | 9 ++++++++-
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 27e0c86..a3cb9d8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4079,7 +4079,14 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
 	intel_dig_port->dp.output_reg = output_reg;
 
 	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
-	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
+	if (IS_CHERRYVIEW(dev)) {
+		if (port == PORT_D)
+			intel_encoder->crtc_mask = 1 << 2;
+		else
+			intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
+	} else {
+		intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
+	}
 	intel_encoder->cloneable = 0;
 	intel_encoder->hot_plug = intel_dp_hot_plug;
 
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 1e8d2a9..d4e020e 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1452,7 +1452,14 @@ void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
 	}
 
 	intel_encoder->type = INTEL_OUTPUT_HDMI;
-	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
+	if (IS_CHERRYVIEW(dev)) {
+		if (port == PORT_D)
+			intel_encoder->crtc_mask = 1 << 2;
+		else
+			intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
+	} else {
+		intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
+	}
 	intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
 	/*
 	 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
-- 
1.8.3.2

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[PATCH v2 63/71] drm/i915/chv: Set soft reset override bit for data lane resets

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The bits we've been setting so far only progagate the reset singal to
the data lanes. To actaully force the reset signal we need to set another
override bit.

v2: Fix mispalced ';' (Mika)

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   | 1 +
 drivers/gpu/drm/i915/intel_dp.c   | 8 ++++++++
 drivers/gpu/drm/i915/intel_hdmi.c | 8 ++++++++
 3 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 206d600..3c2c8b1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -665,6 +665,7 @@ enum punit_power_well {
 
 #define _VLV_PCS_DW1_CH0		0x8204
 #define _VLV_PCS_DW1_CH1		0x8404
+#define   CHV_PCS_REQ_SOFTRESET_EN	(1<<23)
 #define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN	(1<<22)
 #define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
 #define   DPIO_PCS_CLK_DATAWIDTH_SHIFT	(6)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 23a8b21..811e1e8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1854,6 +1854,10 @@ static void chv_post_disable_dp(struct intel_encoder *encoder)
 	mutex_lock(&dev_priv->dpio_lock);
 
 	/* Propagate soft reset to data lane reset */
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+	val |= CHV_PCS_REQ_SOFTRESET_EN;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
+
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
 	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
@@ -1988,6 +1992,10 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
 	mutex_lock(&dev_priv->dpio_lock);
 
 	/* Deassert soft data lane reset*/
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+	val |= CHV_PCS_REQ_SOFTRESET_EN;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
+
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
 	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 6d86bde..e04b1ae 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1241,6 +1241,10 @@ static void chv_hdmi_post_disable(struct intel_encoder *encoder)
 	mutex_lock(&dev_priv->dpio_lock);
 
 	/* Propagate soft reset to data lane reset */
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+	val |= CHV_PCS_REQ_SOFTRESET_EN;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
+
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
 	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
@@ -1263,6 +1267,10 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
 	mutex_lock(&dev_priv->dpio_lock);
 
 	/* Deassert soft data lane reset*/
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+	val |= CHV_PCS_REQ_SOFTRESET_EN;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
+
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
 	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
-- 
1.8.3.2

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Re: [PATCH 41/71] drm/i915/chv: Add some workaround notes

[Ville Syrjälä]

On Fri, Apr 25, 2014 at 05:43:55PM -0300, Paulo Zanoni wrote:
> 2014-04-09 7:28 GMT-03:00  <ville.syrjala@linux.intel.com>:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > We implement the following workarounds:
> > * WaDisableAsyncFlipPerfMode:chv
> > * WaDisableSemaphoreAndSyncFlipWait:chv (at least partially)
> 
> In the rebased version (on your gitorious tree, chv_rebase branch),
> the chunk for this WA got removed. I don't know if this was an
> accident or not. We need to, at least, fix the commit message.

Yeah I misread the spec and though that the idle msg disable bit is
there for all rings. But after rechecking I noticed that it was only
valid for the render ring.

I'll resend this patch with the WaDisableSemaphoreAndSyncFlipWait
comment dropped.

> 
> 
> > * WaProgramMiArbOnOffAroundMiSetContext:chv
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_gem.c         | 1 +
> >  drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
> >  drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
> >  3 files changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > index 84a7171..a9c33ec 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -4376,6 +4376,7 @@ static int i915_gem_init_rings(struct drm_device *dev)
> >                 struct intel_ring_buffer *ring;
> >                 int i;
> >
> > +               /* WaDisableSemaphoreAndSyncFlipWait:chv */
> >                 for_each_ring(ring, dev_priv, i)
> >                         I915_WRITE(RING_RC_PSMI_CONTROL(ring),
> >                                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
> > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> > index 28a2b15..142df90 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> > @@ -606,7 +606,7 @@ mi_set_context(struct intel_ring_buffer *ring,
> >         if (ret)
> >                 return ret;
> >
> > -       /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw */
> > +       /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
> 
> Do we really need this WA for BDW and CHV? I couldn't find them on my
> docs for gen8...

It's listed in bspec.

> 
> Thanks,
> Paulo
> 
> 
> >         if (INTEL_INFO(ring->dev)->gen >= 7)
> >                 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
> >         else
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 913b8ab..24022c5 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -581,7 +581,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
> >          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
> >          * programmed to '1' on all products.
> >          *
> > -        * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw
> > +        * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
> >          */
> >         if (INTEL_INFO(dev)->gen >= 6)
> >                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
> > --
> > 1.8.3.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Paulo Zanoni

-- 
Ville Syrjälä
Intel OTC

[PATCH v2 41/71] drm/i915/chv: Add some workaround notes

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We implement the following workarounds:
* WaDisableAsyncFlipPerfMode:chv
* WaProgramMiArbOnOffAroundMiSetContext:chv

v2: Drop WaDisableSemaphoreAndSyncFlipWait note

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 30b355a..37dc36d 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -614,7 +614,7 @@ mi_set_context(struct intel_ring_buffer *ring,
 	if (ret)
 		return ret;
 
-	/* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw */
+	/* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
 	if (INTEL_INFO(ring->dev)->gen >= 7)
 		intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
 	else
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index eb3dd26..b025a51 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -599,7 +599,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
 	 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 	 * programmed to '1' on all products.
 	 *
-	 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw
+	 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
 	 */
 	if (INTEL_INFO(dev)->gen >= 6)
 		I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
-- 
1.8.3.2

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Re: [PATCH 18/71] drm/i915/chv: Add vlv_pipe_to_channel

[Imre Deak]

[-- Attachment #1.1: Type: text/plain, Size: 1171 bytes --]

On Wed, 2014-04-09 at 13:28 +0300, ville.syrjala@linux.intel.com wrote:
> From: Chon Ming Lee <chon.ming.lee@intel.com>
> 
> Cherryview has 3 pipes.  Some of the pll dpio offset calculation is
> based on pipe number.  Need to use vlv_pipe_to_channel to calculate the
> correct phy channel to use for the pipe.
> 
> Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_drv.h | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 087e471..e572799 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -544,6 +544,20 @@ vlv_dport_to_channel(struct intel_digital_port *dport)
>  	}
>  }
>  
> +static inline int
> +vlv_pipe_to_channel(enum pipe pipe)
> +{
> +	switch (pipe) {
> +	case PIPE_A:
> +	case PIPE_C:
> +		return DPIO_CH0;
> +	case PIPE_B:
> +		return DPIO_CH1;
> +	default:
> +		BUG();
> +	}
> +}
> +
>  static inline struct drm_crtc *
>  intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
>  {


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Re: [PATCH 66/71] drm/i915/chv: Use RMW to toggle swing calc init

[Mika Kuoppala]

ville.syrjala@linux.intel.com writes:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The spec only tells us to set individual bits here and there. So we use
> RMW for most things. Do the same for the swing calc init.
>
> Eventually we should optimize things to just blast the final value in
> with group access whenever possible. But to do that someone needs to
> take a good look at what's the reset value for each registers, and
> possibly if the BIOS manages to frob with some of them. For now
> use RMW access always.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Some accesses use define masks, some hardcoded ones.
But as they were there to begin with, not a problem of
these patches.

For future work, I think we could get rid of
quite amount of DWXX_CHXX definitions if we
would build macros that setup the function,lane/group
and broadcast.

Patches 65 and 66,
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h   |  7 +++++++
>  drivers/gpu/drm/i915/intel_dp.c   | 17 ++++++++++++++---
>  drivers/gpu/drm/i915/intel_hdmi.c | 18 ++++++++++++++----
>  3 files changed, 35 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b91232f..7056994 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -698,6 +698,13 @@ enum punit_power_well {
>  #define   DPIO_PCS_SWING_CALC_TX1_TX3	(1<<31)
>  #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
>  
> +#define _VLV_PCS01_DW10_CH0		0x0228
> +#define _VLV_PCS23_DW10_CH0		0x0428
> +#define _VLV_PCS01_DW10_CH1		0x2628
> +#define _VLV_PCS23_DW10_CH1		0x2828
> +#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
> +#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
> +
>  #define _VLV_PCS_DW11_CH0		0x822c
>  #define _VLV_PCS_DW11_CH1		0x842c
>  #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 4c54930..9cbd702 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2346,7 +2346,13 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
>  	mutex_lock(&dev_priv->dpio_lock);
>  
>  	/* Clear calc init */
> -	vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), 0);
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
> +	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
> +	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
>  
>  	/* Program swing deemph */
>  	for (i = 0; i < 4; i++) {
> @@ -2397,8 +2403,13 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
>  	}
>  
>  	/* Start swing calculation */
> -	vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch),
> -		(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3));
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
> +	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
> +	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
>  
>  	/* LRC Bypass */
>  	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index e912554..d2b1186 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1283,7 +1283,13 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
>  	/* FIXME: Fix up value only after power analysis */
>  
>  	/* Clear calc init */
> -	vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), 0);
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
> +	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
> +	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
>  
>  	/* FIXME: Program the support xxx V-dB */
>  	/* Use 800mV-0dB */
> @@ -1322,9 +1328,13 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
>  				(0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT));
>  #endif
>  	/* Start swing calculation */
> -	vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch),
> -			DPIO_PCS_SWING_CALC_TX0_TX2 |
> -			DPIO_PCS_SWING_CALC_TX1_TX3);
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
> +	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
> +	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
>  
>  	/* LRC Bypass */
>  	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
> -- 
> 1.8.3.2
>
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Re: [PATCH 19/71] drm/i915/chv: Trigger phy common lane reset

[Imre Deak]

[-- Attachment #1.1: Type: text/plain, Size: 5467 bytes --]

On Wed, 2014-04-09 at 13:28 +0300, ville.syrjala@linux.intel.com wrote:
> From: Chon Ming Lee <chon.ming.lee@intel.com>
> 
> During cold boot, the display controller needs to deassert the common
> lane reset.  Only do it once during intel_init_dpio for both PHYx2 and
> PHYx1.
> 
> Besides, assert the common lane reset when disable pll.  This still
> to be determined whether need to do it by driver.
> 
> Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
> [vsyrjala: Don't disable DPIO PLL when using DSI]
> [vsyrjala: Don't call vlv_disable_pll() by accident on CHV]
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |  8 +++++
>  drivers/gpu/drm/i915/intel_display.c | 66 ++++++++++++++++++++++++++++--------
>  2 files changed, 59 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8aea092..8fcf4ea 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1391,6 +1391,14 @@ enum punit_power_well {
>  /* Additional CHV pll/phy registers */
>  #define DPIO_PHY_STATUS			(VLV_DISPLAY_BASE + 0x6240)
>  #define   DPLL_PORTD_READY_MASK		(0xf)
> +#define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)
> +#define   PHY_COM_LANE_RESET_DEASSERT(phy, val) \
> +				((phy == DPIO_PHY0) ? (val | 1) : (val | 2))
> +#define   PHY_COM_LANE_RESET_ASSERT(phy, val) \
> +				((phy == DPIO_PHY0) ? (val & ~1) : (val & ~2))
> +#define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104)
> +#define   PHY_POWERGOOD(phy)	((phy == DPIO_PHY0) ? (1<<31) : (1<<30))
> +
>  /*
>   * The i830 generation, in LVDS mode, defines P1 as the bit number set within
>   * this field (only one bit may be set).
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 153f244..e33667d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1395,17 +1395,36 @@ static void intel_reset_dpio(struct drm_device *dev)
>  		   DPLL_REFA_CLK_ENABLE_VLV |
>  		   DPLL_INTEGRATED_CRI_CLK_VLV);
>  
> -	/*
> -	 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
> -	 *  6.	De-assert cmn_reset/side_reset. Same as VLV X0.
> -	 *   a.	GUnit 0x2110 bit[0] set to 1 (def 0)
> -	 *   b.	The other bits such as sfr settings / modesel may all be set
> -	 *      to 0.

This is VLV specific, so ok to be moved,

> -	 *
> -	 * This should only be done on init and resume from S3 with both
> -	 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
> -	 */

but this is also true for CHV, so should stay.

> -	I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
> +	if (IS_CHERRYVIEW(dev)) {
> +		enum dpio_phy phy;
> +		u32 val;
> +
> +		for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
> +			/* Poll for phypwrgood signal */
> +			if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
> +						PHY_POWERGOOD(phy), 1))
> +				DRM_ERROR("Display PHY %d is not power up\n", phy);
> +
> +			/* Deassert common lane reset for PHY*/
> +			val = I915_READ(DISPLAY_PHY_CONTROL);
> +			I915_WRITE(DISPLAY_PHY_CONTROL,
> +				PHY_COM_LANE_RESET_DEASSERT(phy, val));

Would be clearer not to hide the 'or' in the macro and let
PHY_COM_LANE_RESET_DEASSERT be just the flag itself and do here
I915_WRITE(DISPLAY_PHY_CONTROL, val | PHY_COM_LANE_RESET_DEASSERT(phy));

The above issues are minor, so even without fixing them this patch is
Reviewed-by: Imre Deak <imre.deak@intel.com>

> +		}
> +
> +	} else {
> +		/*
> +		 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
> +		 *  6.	De-assert cmn_reset/side_reset. Same as VLV X0.
> +		 *   a.	GUnit 0x2110 bit[0] set to 1 (def 0)
> +		 *   b.	The other bits such as sfr settings / modesel may all
> +		 *	be set to 0.
> +		 *
> +		 * This should only be done on init and resume from S3 with
> +		 * both PLLs disabled, or we risk losing DPIO and PLL
> +		 * synchronization.
> +		 */
> +		I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
> +	}
>  }
>  
>  static void vlv_enable_pll(struct intel_crtc *crtc)
> @@ -1529,6 +1548,19 @@ static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
>  		val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
>  	I915_WRITE(DPLL(pipe), val);
>  	POSTING_READ(DPLL(pipe));
> +
> +}
> +
> +static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
> +{
> +	int dpll = DPLL(pipe);
> +	u32 val;
> +
> +	/* Set PLL en = 0 */
> +	val = I915_READ(dpll);
> +	val &= ~DPLL_VCO_ENABLE;
> +	I915_WRITE(dpll, val);
> +
>  }
>  
>  void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
> @@ -4511,10 +4543,14 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
>  		if (encoder->post_disable)
>  			encoder->post_disable(encoder);
>  
> -	if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
> -		vlv_disable_pll(dev_priv, pipe);
> -	else if (!IS_VALLEYVIEW(dev))
> -		i9xx_disable_pll(dev_priv, pipe);
> +	if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
> +		if (IS_CHERRYVIEW(dev))
> +			chv_disable_pll(dev_priv, pipe);
> +		else if (IS_VALLEYVIEW(dev))
> +			vlv_disable_pll(dev_priv, pipe);
> +		else
> +			i9xx_disable_pll(dev_priv, pipe);
> +	}
>  
>  	intel_crtc->active = false;
>  	intel_update_watermarks(crtc);


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Re: [PATCH v2 41/71] drm/i915/chv: Add some workaround notes

[Paulo Zanoni]

2014-04-28 8:31 GMT-03:00  <ville.syrjala@linux.intel.com>:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We implement the following workarounds:
> * WaDisableAsyncFlipPerfMode:chv
> * WaProgramMiArbOnOffAroundMiSetContext:chv
>
> v2: Drop WaDisableSemaphoreAndSyncFlipWait note

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 30b355a..37dc36d 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -614,7 +614,7 @@ mi_set_context(struct intel_ring_buffer *ring,
>         if (ret)
>                 return ret;
>
> -       /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw */
> +       /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
>         if (INTEL_INFO(ring->dev)->gen >= 7)
>                 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
>         else
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index eb3dd26..b025a51 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -599,7 +599,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
>          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
>          * programmed to '1' on all products.
>          *
> -        * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw
> +        * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
>          */
>         if (INTEL_INFO(dev)->gen >= 6)
>                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
> --
> 1.8.3.2
>



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Re: [PATCH 42/71] drm/i915/chv: Implement WaDisableSamplerPowerBypass for CHV

[Paulo Zanoni]

2014-04-28 5:23 GMT-03:00 Ville Syrjälä <ville.syrjala@linux.intel.com>:
> On Fri, Apr 25, 2014 at 05:55:38PM -0300, Paulo Zanoni wrote:
>> 2014-04-09 7:28 GMT-03:00  <ville.syrjala@linux.intel.com>:
>> > From: Rafael Barbalho <rafael.barbalho@intel.com>
>> >
>> > Cherryview also needs this WA.
>>
>> At least on the chv_rebase tree, this WA is implemented for BDW but it
>> is not documented as pre-prod only, and its name is not there. We
>> should probably add a comment documenting the name and the fact that
>> it is also pre-prod on BDW.
>
> IIRC BDW will need it even on production steppings.

Hmmm the register documentation says one thing while the WA lists say
others... I'll let you discover which one is correct :)

>
> I think I have a patch somewhere that add the w/a note for BDW, but I guess
> I didn't post it yet.
>
>>
>>
>> >
>> > Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
>> > [vsyrjala: Looks like it's for pre-prodution hw only]
>> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/intel_pm.c | 4 ++++
>> >  1 file changed, 4 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> > index 468fe37..60f876c 100644
>> > --- a/drivers/gpu/drm/i915/intel_pm.c
>> > +++ b/drivers/gpu/drm/i915/intel_pm.c
>> > @@ -5405,6 +5405,10 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
>> >         /* WaDisableSDEUnitClockGating:chv */
>> >         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
>> >                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>> > +
>> > +       /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
>> > +       I915_WRITE(HALF_SLICE_CHICKEN3,
>> > +                  _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
>>
>> I could not find information anywhere if this is the correct
>> implementation. Can you please provide me pointers to the doc you
>> used? The links on Collab seem broken.
>
> Just w/a database + bspec are enough for this one.

Found it :)

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

>
>>
>> Thanks,
>> Paulo
>>
>> >  }
>> >
>> >  static void g4x_init_clock_gating(struct drm_device *dev)
>> > --
>> > 1.8.3.2
>> >
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>>
>>
>> --
>> Paulo Zanoni
>
> --
> Ville Syrjälä
> Intel OTC



-- 
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Re: [PATCH 20/71] drm/i915/chv: find the best divisor for the target clock v4

[Imre Deak]

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On Wed, 2014-04-09 at 13:28 +0300, ville.syrjala@linux.intel.com wrote:
> From: Chon Ming Lee <chon.ming.lee@intel.com>
> 
> Based on the chv clock limit, find the best divisor.
> 
> The divisor data has been verified with this spreadsheet.
> P1273_DPLL_Programming Spreadsheet.
> 
> v2: Rebase the code and change the chv_find_best_dpll based on new
> standard way to use intel_PLL_is_valid.  Besides, clean up some extra
> variables.
> 
> v3: Ville suggest better fixed point for m2 calculation.
> 
> v4: -Add comment for the limit is compute using fast clock. (Ville)
> 	-Don't pass the request clock to chv_clock, as the same function will
> 	 be use clock readout, which doens't have request clock. (Ville)
> 	-Add and use DIV_ROUND_CLOSEST_ULL to consistent with other clock
> 	calculation. (Ville)
> 	-Fix the dp m2 after m2 has stored fixed point. (Ville)
> 
> Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
> [vsyrjala: Avoid div-by-zero in chv_clock()]
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Took a while to understand all the different clock rates along the path,
but it looks ok:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 86 ++++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_dp.c      | 21 +++++++++
>  2 files changed, 107 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index e33667d..d73fec5 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -41,6 +41,9 @@
>  #include <drm/drm_crtc_helper.h>
>  #include <linux/dma_remapping.h>
>  
> +#define DIV_ROUND_CLOSEST_ULL(ll, d)	\
> +	({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
> +
>  static void intel_increase_pllclock(struct drm_crtc *crtc);
>  static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
>  
> @@ -328,6 +331,22 @@ static const intel_limit_t intel_limits_vlv = {
>  	.p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
>  };
>  
> +static const intel_limit_t intel_limits_chv = {
> +	/*
> +	 * These are the data rate limits (measured in fast clocks)
> +	 * since those are the strictest limits we have.  The fast
> +	 * clock and actual rate limits are more relaxed, so checking
> +	 * them would make no difference.
> +	 */
> +	.dot = { .min = 25000 * 5, .max = 540000 * 5},
> +	.vco = { .min = 4860000, .max = 6700000 },
> +	.n = { .min = 1, .max = 1 },
> +	.m1 = { .min = 2, .max = 2 },
> +	.m2 = { .min = 24 << 22, .max = 175 << 22 },
> +	.p1 = { .min = 2, .max = 4 },
> +	.p2 = {	.p2_slow = 1, .p2_fast = 14 },
> +};
> +
>  static void vlv_clock(int refclk, intel_clock_t *clock)
>  {
>  	clock->m = clock->m1 * clock->m2;
> @@ -412,6 +431,8 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
>  			limit = &intel_limits_pineview_lvds;
>  		else
>  			limit = &intel_limits_pineview_sdvo;
> +	} else if (IS_CHERRYVIEW(dev)) {
> +		limit = &intel_limits_chv;
>  	} else if (IS_VALLEYVIEW(dev)) {
>  		limit = &intel_limits_vlv;
>  	} else if (!IS_GEN2(dev)) {
> @@ -456,6 +477,17 @@ static void i9xx_clock(int refclk, intel_clock_t *clock)
>  	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
>  }
>  
> +static void chv_clock(int refclk, intel_clock_t *clock)
> +{
> +	clock->m = clock->m1 * clock->m2;
> +	clock->p = clock->p1 * clock->p2;
> +	if (WARN_ON(clock->n == 0 || clock->p == 0))
> +		return;
> +	clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
> +			clock->n << 22);
> +	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
> +}
> +
>  #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
>  /**
>   * Returns whether the given set of divisors are valid for a given refclk with
> @@ -731,6 +763,58 @@ vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
>  	return found;
>  }
>  
> +static bool
> +chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
> +		   int target, int refclk, intel_clock_t *match_clock,
> +		   intel_clock_t *best_clock)
> +{
> +	struct drm_device *dev = crtc->dev;
> +	intel_clock_t clock;
> +	uint64_t m2;
> +	int found = false;
> +
> +	memset(best_clock, 0, sizeof(*best_clock));
> +
> +	/*
> +	 * Based on hardware doc, the n always set to 1, and m1 always
> +	 * set to 2.  If requires to support 200Mhz refclk, we need to
> +	 * revisit this because n may not 1 anymore.
> +	 */
> +	clock.n = 1, clock.m1 = 2;
> +	target *= 5;	/* fast clock */
> +
> +	for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
> +		for (clock.p2 = limit->p2.p2_fast;
> +				clock.p2 >= limit->p2.p2_slow;
> +				clock.p2 -= clock.p2 > 10 ? 2 : 1) {
> +
> +			clock.p = clock.p1 * clock.p2;
> +
> +			m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
> +					clock.n) << 22, refclk * clock.m1);
> +
> +			if (m2 > INT_MAX/clock.m1)
> +				continue;
> +
> +			clock.m2 = m2;
> +
> +			chv_clock(refclk, &clock);
> +
> +			if (!intel_PLL_is_valid(dev, limit, &clock))
> +				continue;
> +
> +			/* based on hardware requirement, prefer bigger p
> +			 */
> +			if (clock.p > best_clock->p) {
> +				*best_clock = clock;
> +				found = true;
> +			}
> +		}
> +	}
> +
> +	return found;
> +}
> +
>  bool intel_crtc_active(struct drm_crtc *crtc)
>  {
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> @@ -11031,6 +11115,8 @@ static void intel_init_display(struct drm_device *dev)
>  
>  	if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
>  		dev_priv->display.find_dpll = g4x_find_best_dpll;
> +	else if (IS_CHERRYVIEW(dev))
> +		dev_priv->display.find_dpll = chv_find_best_dpll;
>  	else if (IS_VALLEYVIEW(dev))
>  		dev_priv->display.find_dpll = vlv_find_best_dpll;
>  	else if (IS_PINEVIEW(dev))
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index c33971e..6be7b35 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -64,6 +64,24 @@ static const struct dp_link_dpll vlv_dpll[] = {
>  		{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
>  };
>  
> +/*
> + * CHV supports eDP 1.4 that have  more link rates.
> + * Below only provides the fixed rate but exclude variable rate.
> + */
> +static const struct dp_link_dpll chv_dpll[] = {
> +	/*
> +	 * CHV requires to program fractional division for m2.
> +	 * m2 is stored in fixed point format using formula below
> +	 * (m2_int << 22) | m2_fraction
> +	 */
> +	{ DP_LINK_BW_1_62,	/* m2_int = 32, m2_fraction = 1677722 */
> +		{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
> +	{ DP_LINK_BW_2_7,	/* m2_int = 27, m2_fraction = 0 */
> +		{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
> +	{ DP_LINK_BW_5_4,	/* m2_int = 27, m2_fraction = 0 */
> +		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
> +};
> +
>  /**
>   * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
>   * @intel_dp: DP struct
> @@ -720,6 +738,9 @@ intel_dp_set_clock(struct intel_encoder *encoder,
>  	} else if (HAS_PCH_SPLIT(dev)) {
>  		divisor = pch_dpll;
>  		count = ARRAY_SIZE(pch_dpll);
> +	} else if (IS_CHERRYVIEW(dev)) {
> +		divisor = chv_dpll;
> +		count = ARRAY_SIZE(chv_dpll);
>  	} else if (IS_VALLEYVIEW(dev)) {
>  		divisor = vlv_dpll;
>  		count = ARRAY_SIZE(vlv_dpll);


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Re: [PATCH 21/71] drm/i915/chv: Add update and enable pll for Cherryview

[Imre Deak]

On Wed, 2014-04-09 at 13:28 +0300, ville.syrjala@linux.intel.com wrote:
> From: Chon Ming Lee <chon.ming.lee@intel.com>
> 
> Added programming PLL for CHV based on "Application note for 1273 CHV
> Display phy".
> 
> v2:  -Break the common lane reset into another patch.
>      -Break the clock calculation into another patch.
> 
>     -The changes are based on Ville review.
>     -Rework based on DPIO register define naming convention change.
>     -Break the dpio write into few lines to improve readability.
>     -Correct the udelay during chv_enable_pll.
>     -clean up some magic numbers with some new define.
>     -program the afc recal bit which was missed.
> 
> v3: Based on Ville review
> 	-  minor correction of the bit defination
>     - add deassert/propagate data lane reset
> 
> v4: Corrected the udelay between dclkp enable and pll enable.
> 	Minor comment and better way to clear the TX lane reset.
> 
> v5: Squash in fixup from Rafael Barbalho.
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>

A couple of nitpicks below, fixing any/all of those is optional. This
patch is
Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h      |  70 ++++++++++++++++++
>  drivers/gpu/drm/i915/intel_display.c | 133 ++++++++++++++++++++++++++++++++++-
>  2 files changed, 201 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8fcf4ea..75f31f5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -668,6 +668,12 @@ enum punit_power_well {
>  #define _VLV_PCS_DW9_CH1		0x8424
>  #define	VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
>  
> +#define _CHV_PCS_DW10_CH0		0x8228
> +#define _CHV_PCS_DW10_CH1		0x8428

Note that these are atm unused (the code uses instead the single
addressing versions), although these group addressing versions could be
used too.

> +#define   DPIO_PCS_SWING_CALC_TX0_TX2	(1<<30)
> +#define   DPIO_PCS_SWING_CALC_TX1_TX3	(1<<31)
> +#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
> +
>  #define _VLV_PCS_DW11_CH0		0x822c
>  #define _VLV_PCS_DW11_CH1		0x842c
>  #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
> @@ -686,14 +692,21 @@ enum punit_power_well {
>  
>  #define _VLV_TX_DW2_CH0			0x8288
>  #define _VLV_TX_DW2_CH1			0x8488
> +#define   DPIO_UNIQ_TRANS_SCALE_SHIFT	8
> +#define   DPIO_SWING_MARGIN_SHIFT	16
> +#define   DPIO_SWING_MARGIN_MASK	(0xff << DPIO_SWING_MARGIN_SHIFT)
>  #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
>  
>  #define _VLV_TX_DW3_CH0			0x828c
>  #define _VLV_TX_DW3_CH1			0x848c
> +/* The following bit for CHV phy */
> +#define   DPIO_TX_UNIQ_TRANS_SCALE_EN	(1<<27)
>  #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
>  
>  #define _VLV_TX_DW4_CH0			0x8290
>  #define _VLV_TX_DW4_CH1			0x8490
> +#define   DPIO_SWING_DEEMPH9P5_SHIFT	24
> +#define   DPIO_SWING_DEEMPH9P5_MASK	(0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
>  #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
>  
>  #define _VLV_TX3_DW4_CH0		0x690
> @@ -713,6 +726,62 @@ enum punit_power_well {
>  #define _VLV_TX_DW14_CH1		0x84b8
>  #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
>  
> +/* CHV dpPhy registers */
> +#define _CHV_PLL_DW0_CH0		0x8000
> +#define _CHV_PLL_DW0_CH1		0x8180
> +#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
> +
> +#define _CHV_PLL_DW1_CH0		0x8004
> +#define _CHV_PLL_DW1_CH1		0x8184
> +#define   DPIO_CHV_M1_DIV_BY_2		(0 << 0)
> +#define   DPIO_CHV_N_DIV_SHIFT		(8)

Here and below for simple constants, no need for the (). 

> +#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
> +
> +#define _CHV_PLL_DW2_CH0		0x8008
> +#define _CHV_PLL_DW2_CH1		0x8188
> +#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
> +
> +#define _CHV_PLL_DW3_CH0		0x800c
> +#define _CHV_PLL_DW3_CH1		0x818c
> +#define  DPIO_CHV_FEEDFWD_GAIN		2
> +#define  DPIO_CHV_FIRST_MOD		(0 << 8)
> +#define  DPIO_CHV_SECOND_MOD		(1 << 8)
> +#define  DPIO_CHV_FRAC_DIV_EN		(1 << 16)
> +#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
> +
> +#define _CHV_PLL_DW6_CH0		0x8018
> +#define _CHV_PLL_DW6_CH1		0x8198
> +#define   DPIO_CHV_PROP_COEFF		(5 << 0)
> +#define   DPIO_CHV_GAIN_CTRL		(2 << 16)

These macros combine the field shift and field value, for consistency
I'd define here only the field shift and use the field value inlined in
the code. 

> +#define	  DPIO_CHV_INT_COEFF_SHIFT	8
> +#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
> +
> +#define _CHV_CMN_DW13_CH0		0x8134
> +#define _CHV_CMN_DW0_CH1		0x8080
> +#define   DPIO_CHV_S1_DIV_SELECT	(21)
> +#define   DPIO_CHV_P1_SHIFT		(13) /* 3 bits */
> +#define   DPIO_CHV_P2_SHIFT		(8)  /* 5 bits */
> +#define   DPIO_CHV_K_DIV_SHIFT		(4)
> +#define   DPIO_PLL_LOCK			0x1

(1 << 0) for consistency.

> +#define   DPIO_PLL_FREQLOCK		0x2

(1 << 1)

> +#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
> +
> +#define _CHV_CMN_DW14_CH0		0x8138
> +#define _CHV_CMN_DW1_CH1		0x8084
> +#define   DPIO_AFC_RECAL		(1 << 14)
> +#define   DPIO_DCLKP_EN			(1 << 13)
> +#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
> +
> +#define CHV_CMN_DW30			0x8178
> +#define   DPIO_LRC_BYPASS		(1 << 3)
> +
> +#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
> +					(lane) * 0x200 + (offset))

This works too, but according to the PHY spec the base addresses would
be more precisely written as
((ch ? 0x2480 : 0x80) + (lane) * 0x200 + (offset))

... and then

> +
> +#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)

_TXLANE(ch, lane, 0x2c)

> +#define   DPIO_FRC_LATENCY_SHFIT	(8)
> +#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)

_TXLANE(ch, lane, 0x38)

--Imre

> +#define   DPIO_UPAR_SHIFT		(30)

>  /*
>   * Fence registers
>   */
> @@ -1383,6 +1452,7 @@ enum punit_power_well {
>  #define   DPLL_LOCK_VLV			(1<<15)
>  #define   DPLL_INTEGRATED_CRI_CLK_VLV	(1<<14)
>  #define   DPLL_INTEGRATED_CLOCK_VLV	(1<<13)
> +#define   DPLL_SSC_REF_CLOCK_CHV	(1<<13)
>  #define   DPLL_PORTC_READY_MASK		(0xf << 4)
>  #define   DPLL_PORTB_READY_MASK		(0xf)
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d73fec5..36d6e212 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1549,6 +1549,49 @@ static void vlv_enable_pll(struct intel_crtc *crtc)
>  	udelay(150); /* wait for warmup */
>  }
>  
> +static void chv_enable_pll(struct intel_crtc *crtc)
> +{
> +	struct drm_device *dev = crtc->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int pipe = crtc->pipe;
> +	enum dpio_channel port = vlv_pipe_to_channel(pipe);
> +	int dpll = DPLL(crtc->pipe);
> +	u32 tmp;
> +
> +	assert_pipe_disabled(dev_priv, crtc->pipe);
> +
> +	BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
> +
> +	mutex_lock(&dev_priv->dpio_lock);
> +
> +	/* Enable back the 10bit clock to display controller */
> +	tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
> +	tmp |= DPIO_DCLKP_EN;
> +	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
> +
> +	/*
> +	 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
> +	 */
> +	udelay(1);
> +
> +	/* Enable PLL */
> +	tmp = I915_READ(dpll);
> +	tmp |= DPLL_VCO_ENABLE;
> +	I915_WRITE(dpll, tmp);
> +
> +	/* Check PLL is locked */
> +	if (wait_for(((I915_READ(dpll) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
> +		DRM_ERROR("PLL %d failed to lock\n", pipe);
> +
> +	/* Deassert soft data lane reset*/
> +	tmp = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
> +	tmp |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), tmp);
> +
> +
> +	mutex_unlock(&dev_priv->dpio_lock);
> +}
> +
>  static void i9xx_enable_pll(struct intel_crtc *crtc)
>  {
>  	struct drm_device *dev = crtc->base.dev;
> @@ -4503,8 +4546,12 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
>  
>  	is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
>  
> -	if (!is_dsi)
> -		vlv_enable_pll(intel_crtc);
> +	if (!is_dsi) {
> +		if (IS_CHERRYVIEW(dev))
> +			chv_enable_pll(intel_crtc);
> +		else
> +			vlv_enable_pll(intel_crtc);
> +	}
>  
>  	for_each_encoder_on_crtc(dev, crtc, encoder)
>  		if (encoder->pre_enable)
> @@ -5385,6 +5432,86 @@ static void vlv_update_pll(struct intel_crtc *crtc)
>  	mutex_unlock(&dev_priv->dpio_lock);
>  }
>  
> +static void chv_update_pll(struct intel_crtc *crtc)
> +{
> +	struct drm_device *dev = crtc->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int pipe = crtc->pipe;
> +	int dpll_reg = DPLL(crtc->pipe);
> +	enum dpio_channel port = vlv_pipe_to_channel(pipe);
> +	u32 val, loopfilter, intcoeff;
> +	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
> +	int refclk;
> +
> +	mutex_lock(&dev_priv->dpio_lock);
> +
> +	bestn = crtc->config.dpll.n;
> +	bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
> +	bestm1 = crtc->config.dpll.m1;
> +	bestm2 = crtc->config.dpll.m2 >> 22;
> +	bestp1 = crtc->config.dpll.p1;
> +	bestp2 = crtc->config.dpll.p2;
> +
> +	/*
> +	 * Enable Refclk and SSC
> +	 */
> +	val = I915_READ(dpll_reg);
> +	val |= (DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV);
> +	I915_WRITE(dpll_reg, val);
> +
> +	/* Propagate soft reset to data lane reset */
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
> +	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), val);
> +
> +	/* Disable 10bit clock to display controller */
> +	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
> +	val &= ~DPIO_DCLKP_EN;
> +	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
> +
> +	/* p1 and p2 divider */
> +	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
> +			5 << DPIO_CHV_S1_DIV_SELECT |
> +			bestp1 << DPIO_CHV_P1_SHIFT |
> +			bestp2 << DPIO_CHV_P2_SHIFT |
> +			1 << DPIO_CHV_K_DIV_SHIFT);
> +
> +	/* Feedback post-divider - m2 */
> +	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
> +
> +	/* Feedback refclk divider - n and m1 */
> +	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
> +			DPIO_CHV_M1_DIV_BY_2 |
> +			1 << DPIO_CHV_N_DIV_SHIFT);
> +
> +	/* M2 fraction division */
> +	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
> +
> +	/* M2 fraction division enable */
> +	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
> +			DPIO_CHV_FRAC_DIV_EN |
> +			DPIO_CHV_FEEDFWD_GAIN);
> +
> +	/* Loop filter */
> +	refclk = i9xx_get_refclk(&crtc->base, 0);
> +	loopfilter = DPIO_CHV_PROP_COEFF | DPIO_CHV_GAIN_CTRL;
> +	if (refclk == 100000)
> +		intcoeff = 11;
> +	else if (refclk == 38400)
> +		intcoeff = 10;
> +	else
> +		intcoeff = 9;
> +	loopfilter |= (intcoeff << DPIO_CHV_INT_COEFF_SHIFT);
> +	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
> +
> +	/* AFC Recal */
> +	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
> +			vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
> +			DPIO_AFC_RECAL);
> +
> +	mutex_unlock(&dev_priv->dpio_lock);
> +}
> +
>  static void i9xx_update_pll(struct intel_crtc *crtc,
>  			    intel_clock_t *reduced_clock,
>  			    int num_connectors)
> @@ -5768,6 +5895,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  		i8xx_update_pll(intel_crtc,
>  				has_reduced_clock ? &reduced_clock : NULL,
>  				num_connectors);
> +	} else if (IS_CHERRYVIEW(dev)) {
> +		chv_update_pll(intel_crtc);
>  	} else if (IS_VALLEYVIEW(dev)) {
>  		vlv_update_pll(intel_crtc);
>  	} else {


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Re: [PATCH 22/71] drm/i915/chv: Add phy supports for Cherryview

[Imre Deak]

[-- Attachment #1.1: Type: text/plain, Size: 13991 bytes --]

On Wed, 2014-04-09 at 13:28 +0300, ville.syrjala@linux.intel.com wrote:
> From: Chon Ming Lee <chon.ming.lee@intel.com>
> 
> Added programming phy layer for CHV based on "Application note for 1273
> CHV Display phy".
> 
> v2: Rebase the code and do some cleanup.
> v3: Rework based on Ville review.
>     -Fix the macro where the ch info need to swap, and add parens to ?
> 	 operator.
> 	-Fix wrong bit define for DPIO_PCS_SWING_CALC_0 and
> 	 DPIO_PCS_SWING_CALC_1 and rename for meaningful.
>     -Add some comments for CHV specific DPIO registers.
>     -Change the dp margin registery value to decimal to align with the
> 	 doc.
> 	-Fix the not clearing some value in vlv_dpio_read before write again.
>     -Create new hdmi/dp encoder function for chv instead of share with
> 	valleyview.
> v4: Rebase the code after rename the DPIO registers define and upstream
> 	change.
>     Based on Ville review.
>     -For unique transition scale selection, after Ville point out, look
> 	 like the doc might wrong for the bit 26.  Use bit 27 for ch0 and
> 	 ch1.
> 	-Break up some dpio write value into two/three steps for readability.
> 	-Remove unrelated change.
>     -Add some shift define for some registers instead just give the hex
> 	value.
>     -Fix a bug where write to wrong VLV_TX_DW3.
> v5: Based on Ville review.
> 	- Move tx lane latency optimal setting from chv_dp_pre_pll_enable to
> 	  chv_pre_enable_dp, and chv_hdmi_pre_pll_enable to
> 	  chv_hdmi_pre_enable respectively.
>  	- Fix typo in one margin_reg_value for DP_TRAIN_VOLTAGE_SWING_400.
> 	- Clear DPIO_TX_UNIQ_TRANS_SCALE_EN for DP and HDMI.
> 	- Mask the old deemph and swing bits for hdmi.
> v6: Remove stub for pre_pll_enable for dp and hdmi.
> 
> Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> [vsyrjala: Don't touch panel power sequencing on DP]
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Looks ok, so:
Reviewed-by: Imre Deak <imre.deak@intel.com>

Some nitpicks follow, fixing them is optional.

> ---
>  drivers/gpu/drm/i915/intel_dp.c   | 188 +++++++++++++++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/intel_hdmi.c |  84 ++++++++++++++++-
>  2 files changed, 270 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 6be7b35..71a4fa2 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1932,6 +1932,50 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
>  	mutex_unlock(&dev_priv->dpio_lock);
>  }
>  
> +static void chv_pre_enable_dp(struct intel_encoder *encoder)
> +{
> +	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> +	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> +	struct drm_device *dev = encoder->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct edp_power_seq power_seq;
> +	struct intel_crtc *intel_crtc =
> +		to_intel_crtc(encoder->base.crtc);
> +	enum dpio_channel ch = vlv_dport_to_channel(dport);
> +	int pipe = intel_crtc->pipe;
> +	int data, i;
> +
> +	/* Program Tx lane latency optimal setting*/
> +	mutex_lock(&dev_priv->dpio_lock);
> +	for (i = 0; i < 4; i++) {
> +		/* Set the latency optimal bit */
> +		data = (i == 1) ? 0x0 : 0x6;
> +		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
> +				data << DPIO_FRC_LATENCY_SHFIT);
> +
> +		/* Set the upar bit */
> +		data = (i == 1) ? 0x0 : 0x1;
> +		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
> +				data << DPIO_UPAR_SHIFT);
> +	}
> +
> +	/* Data lane stagger programming */
> +	/* FIXME: Fix up value only after power analysis */
> +
> +	mutex_unlock(&dev_priv->dpio_lock);
> +
> +	if (is_edp(intel_dp)) {
> +		/* init power sequencer on this pipe and port */
> +		intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
> +		intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
> +							      &power_seq);
> +	}
> +
> +	intel_enable_dp(encoder);
> +
> +	vlv_wait_port_ready(dev_priv, dport);
> +}
> +
>  /*
>   * Native read with retry for link status and receiver capability reads for
>   * cases where the sink may still be asleep.
> @@ -2156,6 +2200,142 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
>  	return 0;
>  }
>  
> +static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
> +{
> +	struct drm_device *dev = intel_dp_to_dev(intel_dp);
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> +	struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
> +	u32 deemph_reg_value, margin_reg_value, val, tx_dw2;
> +	uint8_t train_set = intel_dp->train_set[0];
> +	enum dpio_channel ch = vlv_dport_to_channel(dport);
> +	int pipe = intel_crtc->pipe;
> +
> +	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
> +	case DP_TRAIN_PRE_EMPHASIS_0:
> +		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
> +		case DP_TRAIN_VOLTAGE_SWING_400:
> +			deemph_reg_value = 128;
> +			margin_reg_value = 52;
> +			break;
> +		case DP_TRAIN_VOLTAGE_SWING_600:
> +			deemph_reg_value = 128;
> +			margin_reg_value = 77;
> +			break;
> +		case DP_TRAIN_VOLTAGE_SWING_800:
> +			deemph_reg_value = 128;
> +			margin_reg_value = 102;
> +			break;
> +		case DP_TRAIN_VOLTAGE_SWING_1200:
> +			deemph_reg_value = 128;
> +			margin_reg_value = 154;
> +			/* FIXME extra to set for 1200 */
> +			break;
> +		default:

We could throw a WARN at these spots, as they would all point to a bug
in the driver.

> +			return 0;
> +		}
> +		break;
> +	case DP_TRAIN_PRE_EMPHASIS_3_5:
> +		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
> +		case DP_TRAIN_VOLTAGE_SWING_400:
> +			deemph_reg_value = 85;
> +			margin_reg_value = 78;
> +			break;
> +		case DP_TRAIN_VOLTAGE_SWING_600:
> +			deemph_reg_value = 85;
> +			margin_reg_value = 116;
> +			break;
> +		case DP_TRAIN_VOLTAGE_SWING_800:
> +			deemph_reg_value = 85;
> +			margin_reg_value = 154;
> +			break;
> +		default:
> +			return 0;
> +		}
> +		break;
> +	case DP_TRAIN_PRE_EMPHASIS_6:
> +		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
> +		case DP_TRAIN_VOLTAGE_SWING_400:
> +			deemph_reg_value = 64;
> +			margin_reg_value = 104;
> +			break;
> +		case DP_TRAIN_VOLTAGE_SWING_600:
> +			deemph_reg_value = 64;
> +			margin_reg_value = 154;
> +			break;
> +		default:
> +			return 0;
> +		}
> +		break;
> +	case DP_TRAIN_PRE_EMPHASIS_9_5:
> +		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
> +		case DP_TRAIN_VOLTAGE_SWING_400:
> +			deemph_reg_value = 43;
> +			margin_reg_value = 154;
> +			break;
> +		default:
> +			return 0;
> +		}
> +		break;
> +	default:
> +		return 0;
> +	}
> +
> +	mutex_lock(&dev_priv->dpio_lock);
> +
> +	/* Clear calc init */
> +	vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), 0);
> +
> +	/* Program swing deemph */
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW4(ch));
> +	val &= ~DPIO_SWING_DEEMPH9P5_MASK;
> +	val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
> +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(ch), val);
> +
> +	/* Program swing margin */
> +	tx_dw2 = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch));
> +	tx_dw2 &= ~DPIO_SWING_MARGIN_MASK;
> +	tx_dw2 |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
> +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), tx_dw2);
> +
> +	/* Disable unique transition scale */
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
> +	val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
> +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
> +
> +	if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
> +			== DP_TRAIN_PRE_EMPHASIS_0) &&
> +		((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
> +			== DP_TRAIN_VOLTAGE_SWING_1200)) {

It works, but the check for pre-emphasis is redundant.

> +
> +		/*
> +		 * The document said it needs to set bit 27 for ch0 and bit 26
> +		 * for ch1. Might be a typo in the doc.
> +		 * For now, for this unique transition scale selection, set bit
> +		 * 27 for ch0 and ch1.
> +		 */
> +		val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
> +		val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
> +		vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
> +
> +		tx_dw2 |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
> +		vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), tx_dw2);
> +	}
> +
> +	/* Start swing calculation */
> +	vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch),
> +		(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3));
> +
> +	/* LRC Bypass */
> +	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
> +	val |= DPIO_LRC_BYPASS;
> +	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
> +
> +	mutex_unlock(&dev_priv->dpio_lock);
> +
> +	return 0;
> +}
> +
>  static void
>  intel_get_adjust_train(struct intel_dp *intel_dp,
>  		       const uint8_t link_status[DP_LINK_STATUS_SIZE])
> @@ -2370,6 +2550,9 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
>  	} else if (IS_HASWELL(dev)) {
>  		signal_levels = intel_hsw_signal_levels(train_set);
>  		mask = DDI_BUF_EMP_MASK;
> +	} else if (IS_CHERRYVIEW(dev)) {
> +		signal_levels = intel_chv_signal_levels(intel_dp);
> +		mask = 0;
>  	} else if (IS_VALLEYVIEW(dev)) {
>  		signal_levels = intel_vlv_signal_levels(intel_dp);
>  		mask = 0;
> @@ -3865,7 +4048,10 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
>  	intel_encoder->disable = intel_disable_dp;
>  	intel_encoder->get_hw_state = intel_dp_get_hw_state;
>  	intel_encoder->get_config = intel_dp_get_config;
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_CHERRYVIEW(dev)) {
> +		intel_encoder->pre_enable = chv_pre_enable_dp;
> +		intel_encoder->enable = vlv_enable_dp;
> +	} else if (IS_VALLEYVIEW(dev)) {
>  		intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
>  		intel_encoder->pre_enable = vlv_pre_enable_dp;
>  		intel_encoder->enable = vlv_enable_dp;
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index b0413e1..bbda011 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1198,6 +1198,85 @@ static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
>  	mutex_unlock(&dev_priv->dpio_lock);
>  }
>  
> +static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
> +{
> +	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> +	struct drm_device *dev = encoder->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc =
> +		to_intel_crtc(encoder->base.crtc);
> +	enum dpio_channel ch = vlv_dport_to_channel(dport);
> +	int pipe = intel_crtc->pipe;
> +	int data, i;
> +	u32 val;
> +
> +	/* Program Tx latency optimal setting */
> +	mutex_lock(&dev_priv->dpio_lock);
> +	for (i = 0; i < 4; i++) {
> +		/* Set the latency optimal bit */
> +		data = (i == 1) ? 0x0 : 0x6;
> +		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
> +				data << DPIO_FRC_LATENCY_SHFIT);
> +
> +		/* Set the upar bit */
> +		data = (i == 1) ? 0x0 : 0x1;
> +		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
> +				data << DPIO_UPAR_SHIFT);
> +	}
> +
> +	/* Data lane stagger programming */
> +	/* FIXME: Fix up value only after power analysis */
> +
> +	/* Clear calc init */
> +	vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), 0);
> +
> +	/* FIXME: Program the support xxx V-dB */
> +	/* Use 800mV-0dB */
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW4(ch));
> +	val &= ~DPIO_SWING_DEEMPH9P5_MASK;
> +	val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
> +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch));
> +	val &= ~DPIO_SWING_MARGIN_MASK;
> +	val |= 102 << DPIO_SWING_MARGIN_SHIFT;
> +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), val);
> +
> +	/* Disable unique transition scale */
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
> +	val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
> +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
> +
> +	/* Additional steps for 1200mV-0dB */
> +#if 0
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
> +	if (ch)
> +		val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1;
> +	else
> +		val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0;
> +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
> +
> +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch),
> +			vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) |
> +				(0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT));
> +#endif

Could remove this chunk.

> +	/* Start swing calculation */
> +	vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch),
> +			DPIO_PCS_SWING_CALC_TX0_TX2 |
> +			DPIO_PCS_SWING_CALC_TX1_TX3);
> +
> +	/* LRC Bypass */
> +	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
> +	val |= DPIO_LRC_BYPASS;
> +	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
> +
> +	mutex_unlock(&dev_priv->dpio_lock);
> +
> +	intel_enable_hdmi(encoder);
> +
> +	vlv_wait_port_ready(dev_priv, dport);
> +}
> +
>  static void intel_hdmi_destroy(struct drm_connector *connector)
>  {
>  	drm_connector_cleanup(connector);
> @@ -1332,7 +1411,10 @@ void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
>  	intel_encoder->disable = intel_disable_hdmi;
>  	intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
>  	intel_encoder->get_config = intel_hdmi_get_config;
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_CHERRYVIEW(dev)) {
> +		intel_encoder->pre_enable = chv_hdmi_pre_enable;
> +		intel_encoder->enable = vlv_enable_hdmi;
> +	} else if (IS_VALLEYVIEW(dev)) {
>  		intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
>  		intel_encoder->pre_enable = vlv_hdmi_pre_enable;
>  		intel_encoder->enable = vlv_enable_hdmi;


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Re: [PATCH 23/71] drm/i915/chv: Pipe select change for DP and HDMI

[Imre Deak]

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On Wed, 2014-04-09 at 13:28 +0300, ville.syrjala@linux.intel.com wrote:
> From: Chon Ming Lee <chon.ming.lee@intel.com>
> 
> With additional of pipe C, current 1 bit registers for pipe select
> for HDMI and DP are no longer able to gather for 3 pipes. As a result,
> new bits location in the same registers are added.
> 
> For HDMI, VLV uses bit 30, CHV uses bit 24-25.
> 
> For DP, VLV uses bit 30, CHV uses bit 16-17.
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h      | 6 ++++++
>  drivers/gpu/drm/i915/intel_display.c | 6 ++++++
>  drivers/gpu/drm/i915/intel_dp.c      | 8 ++++++--
>  drivers/gpu/drm/i915/intel_hdmi.c    | 2 ++
>  4 files changed, 20 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 75f31f5..91c8fac 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2478,6 +2478,10 @@ enum punit_power_well {
>  #define   SDVO_PIPE_SEL_CPT(pipe)		((pipe) << 29)
>  #define   SDVO_PIPE_SEL_MASK_CPT		(3 << 29)
>  
> +/* CHV SDVO/HDMI bits: */
> +#define   SDVO_PIPE_SEL_CHV(pipe)		((pipe) << 24)
> +#define   SDVO_PIPE_SEL_MASK_CHV		(3 << 24)
> +
>  
>  /* DVO port control */
>  #define DVOA			0x61120
> @@ -3235,6 +3239,8 @@ enum punit_power_well {
>  #define   DP_PORT_EN			(1 << 31)
>  #define   DP_PIPEB_SELECT		(1 << 30)
>  #define   DP_PIPE_MASK			(1 << 30)
> +#define   DP_PIPE_SELECT_CHV(pipe)	((pipe) << 16)
> +#define   DP_PIPE_MASK_CHV		(3 << 16)
>  
>  /* Link training mode - select a suitable mode for each stage */
>  #define   DP_LINK_TRAIN_PAT_1		(0 << 28)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 36d6e212..f849c65 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1337,6 +1337,9 @@ static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
>  		u32	trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
>  		if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
>  			return false;
> +	} else if (IS_CHERRYVIEW(dev_priv->dev)) {
> +		if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
> +			return false;
>  	} else {
>  		if ((val & DP_PIPE_MASK) != (pipe << 30))
>  			return false;
> @@ -1353,6 +1356,9 @@ static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
>  	if (HAS_PCH_CPT(dev_priv->dev)) {
>  		if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
>  			return false;
> +	} else if (IS_CHERRYVIEW(dev_priv->dev)) {
> +		if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
> +			return false;
>  	} else {
>  		if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
>  			return false;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 71a4fa2..21ac845 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -964,8 +964,12 @@ static void intel_dp_mode_set(struct intel_encoder *encoder)
>  		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
>  			intel_dp->DP |= DP_ENHANCED_FRAMING;
>  
> -		if (crtc->pipe == 1)
> -			intel_dp->DP |= DP_PIPEB_SELECT;
> +		if (!IS_CHERRYVIEW(dev)) {
> +			if (crtc->pipe == 1)
> +				intel_dp->DP |= DP_PIPEB_SELECT;
> +		} else {
> +			intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
> +		}
>  	} else {
>  		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
>  	}
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index bbda011..9f868f4 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -652,6 +652,8 @@ static void intel_hdmi_mode_set(struct intel_encoder *encoder)
>  
>  	if (HAS_PCH_CPT(dev))
>  		hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
> +	else if (IS_CHERRYVIEW(dev))
> +		hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
>  	else
>  		hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
>  


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Re: [PATCH 24/71] drm/i915/chv: Add DPLL state readout support

[Imre Deak]

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On Wed, 2014-04-09 at 13:28 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add chv_crtc_clock_get() to read out the DPLL settings.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 34 +++++++++++++++++++++++++++++++++-
>  1 file changed, 33 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f849c65..266d8fe 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6062,6 +6062,36 @@ static void i9xx_get_plane_config(struct intel_crtc *crtc,
>  
>  }
>  
> +static void chv_crtc_clock_get(struct intel_crtc *crtc,
> +			       struct intel_crtc_config *pipe_config)
> +{
> +	struct drm_device *dev = crtc->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int pipe = pipe_config->cpu_transcoder;
> +	enum dpio_channel port = vlv_pipe_to_channel(pipe);

'ch' would be clearer.

> +	intel_clock_t clock;
> +	u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
> +	int refclk = 100000;
> +
> +	mutex_lock(&dev_priv->dpio_lock);
> +	cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
> +	pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
> +	pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
> +	pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
> +	mutex_unlock(&dev_priv->dpio_lock);
> +
> +	clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
> +	clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
> +	clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
> +	clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_SHIFT) & 0x7;
> +	clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_SHIFT) & 0x1f;

We could throw in a check here for the rest of the dividers that we
assume fixed (S1, K, div_by2, div_by4).

With or without the above changes:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> +
> +	chv_clock(refclk, &clock);
> +
> +	/* clock.dot is the fast clock */
> +	pipe_config->port_clock = clock.dot / 5;
> +}
> +
>  static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>  				 struct intel_crtc_config *pipe_config)
>  {
> @@ -6131,7 +6161,9 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>  						     DPLL_PORTB_READY_MASK);
>  	}
>  
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_CHERRYVIEW(dev))
> +		chv_crtc_clock_get(crtc, pipe_config);
> +	else if (IS_VALLEYVIEW(dev))
>  		vlv_crtc_clock_get(crtc, pipe_config);
>  	else
>  		i9xx_crtc_clock_get(crtc, pipe_config);


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Re: [PATCH 01/71] drm/i915/chv: IS_BROADWELL() should not be true for Cherryview

[Barbalho, Rafael]

> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf
> Of ville.syrjala@linux.intel.com
> Sent: Wednesday, April 09, 2014 11:28 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 01/71] drm/i915/chv: IS_BROADWELL() should
> not be true for Cherryview
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Reviewed-by:  Rafael Barbalho <rafael.barbalho@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index e23bb73..41cf429 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1789,7 +1789,7 @@ struct drm_i915_cmd_table {
>  				 (dev)->pdev->device == 0x010A)
>  #define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
>  #define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
> -#define IS_BROADWELL(dev)	(INTEL_INFO(dev)->gen == 8)
> +#define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_valleyview &&
> IS_GEN8(dev))
>  #define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
>  #define IS_HSW_EARLY_SDV(dev)	(IS_HASWELL(dev) && \
>  				 ((dev)->pdev->device & 0xFF00) == 0x0C00)
> --
> 1.8.3.2
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH 02/71] drm/i915/chv: Add IS_CHERRYVIEW() macro

[Barbalho, Rafael]

> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf
> Of ville.syrjala@linux.intel.com
> Sent: Wednesday, April 09, 2014 11:28 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 02/71] drm/i915/chv: Add IS_CHERRYVIEW()
> macro
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We will treat Cherryview like Valleyview for most parts. Add a macro for
> cases when we need to tell the two apart.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by:  Rafael Barbalho <rafael.barbalho@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index 41cf429..f760803 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1788,6 +1788,7 @@ struct drm_i915_cmd_table {
>  				 (dev)->pdev->device == 0x0106 || \
>  				 (dev)->pdev->device == 0x010A)
>  #define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
> +#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview &&
> IS_GEN8(dev))
>  #define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
>  #define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_valleyview &&
> IS_GEN8(dev))
>  #define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
> --
> 1.8.3.2
> 
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Re: [PATCH 03/71] drm/i915/chv: PPAT setup for Cherryview

[Barbalho, Rafael]

> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf
> Of ville.syrjala@linux.intel.com
> Sent: Wednesday, April 09, 2014 11:28 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 03/71] drm/i915/chv: PPAT setup for Cherryview
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Ignore the cache bits in PPAT and just set the snoop bit where appropriate.
> BDW WB is mapped to snooped access, while all other modes are mapped to
> non-snooped access.
> 
> The hardware supposedly ignores everything except the snoop bit in the
> PPAT entries.
> 
> Additionally the hardware actually enforces snooping for all page table
> accesses, and thus the snoop bit is ignored for PDEs.
> 
> v2: Rebased on top of the bdw resume fix to reload the ppat entries.
> 
> v3: Rebase on top of the i915_gem_gtt.h header extraction.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1)
> Acked-by: Ben Widawsky <ben@bwidawsk.net>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---

Reviewed-by:  Rafael Barbalho <rafael.barbalho@intel.com>

>  drivers/gpu/drm/i915/i915_gem_gtt.c | 43
> +++++++++++++++++++++++++++++++++----
>  drivers/gpu/drm/i915/i915_gem_gtt.h |  1 +
>  2 files changed, 40 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 4467974..3e4d1f0 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -30,7 +30,8 @@
>  #include "i915_trace.h"
>  #include "intel_drv.h"
> 
> -static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv);
> +static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv);
> +static void chv_setup_private_ppat(struct drm_i915_private *dev_priv);
> 
>  bool intel_enable_ppgtt(struct drm_device *dev, bool full)  { @@ -1315,7
> +1316,11 @@ void i915_gem_restore_gtt_mappings(struct drm_device
> *dev)
> 
> 
>  	if (INTEL_INFO(dev)->gen >= 8) {
> -		gen8_setup_private_ppat(dev_priv);
> +		if (IS_CHERRYVIEW(dev))
> +			chv_setup_private_ppat(dev_priv);
> +		else
> +			bdw_setup_private_ppat(dev_priv);
> +
>  		return;
>  	}
> 
> @@ -1787,7 +1792,7 @@ static int ggtt_probe_common(struct drm_device
> *dev,
>  /* The GGTT and PPGTT need a private PPAT setup in order to handle
> cacheability
>   * bits. When using advanced contexts each context stores its own PAT, but
>   * writing this data shouldn't be harmful even in those cases. */ -static void
> gen8_setup_private_ppat(struct drm_i915_private *dev_priv)
> +static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
>  {
>  	uint64_t pat;
> 
> @@ -1806,6 +1811,33 @@ static void gen8_setup_private_ppat(struct
> drm_i915_private *dev_priv)
>  	I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);  }
> 
> +static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) {
> +	uint64_t pat;
> +
> +	/*
> +	 * Map WB on BDW to snooped on CHV.
> +	 *
> +	 * Only the snoop bit has meaning for CHV, the rest is
> +	 * ignored.
> +	 *
> +	 * Note that the harware enforces snooping for all page
> +	 * table accesses. The snoop bit is actually ignored for
> +	 * PDEs.
> +	 */
> +	pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
> +	      GEN8_PPAT(1, 0) |
> +	      GEN8_PPAT(2, 0) |
> +	      GEN8_PPAT(3, 0) |
> +	      GEN8_PPAT(4, CHV_PPAT_SNOOP) |
> +	      GEN8_PPAT(5, CHV_PPAT_SNOOP) |
> +	      GEN8_PPAT(6, CHV_PPAT_SNOOP) |
> +	      GEN8_PPAT(7, CHV_PPAT_SNOOP);
> +
> +	I915_WRITE(GEN8_PRIVATE_PAT, pat);
> +	I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); }
> +
>  static int gen8_gmch_probe(struct drm_device *dev,
>  			   size_t *gtt_total,
>  			   size_t *stolen,
> @@ -1831,7 +1863,10 @@ static int gen8_gmch_probe(struct drm_device
> *dev,
>  	gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
>  	*gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
> 
> -	gen8_setup_private_ppat(dev_priv);
> +	if (IS_CHERRYVIEW(dev))
> +		chv_setup_private_ppat(dev_priv);
> +	else
> +		bdw_setup_private_ppat(dev_priv);
> 
>  	ret = ggtt_probe_common(dev, gtt_size);
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
> b/drivers/gpu/drm/i915/i915_gem_gtt.h
> index b5e8ac0..cfca023 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> @@ -95,6 +95,7 @@ typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
>  #define PPAT_CACHED_INDEX		_PAGE_PAT /* WB LLCeLLC */
>  #define PPAT_DISPLAY_ELLC_INDEX		_PAGE_PCD /* WT eLLC */
> 
> +#define CHV_PPAT_SNOOP			(1<<6)
>  #define GEN8_PPAT_AGE(x)		(x<<4)
>  #define GEN8_PPAT_LLCeLLC		(3<<2)
>  #define GEN8_PPAT_LLCELLC		(2<<2)
> --
> 1.8.3.2
> 
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Re: [PATCH 05/71] drm/i915/chv: Enable aliasing PPGTT for CHV

[Barbalho, Rafael]

> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf
> Of ville.syrjala@linux.intel.com
> Sent: Wednesday, April 09, 2014 11:28 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 05/71] drm/i915/chv: Enable aliasing PPGTT for
> CHV
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Enable aliasing PPGTT for CHV, but keep full PPGTT still disabled until it gets
> enabled for BDW.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index f760803..4abaa9e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1831,9 +1831,10 @@ struct drm_i915_cmd_table {
>  #define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)
> 
>  #define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 6)
> -#define HAS_ALIASING_PPGTT(dev)	(INTEL_INFO(dev)->gen >= 6 &&
> !IS_VALLEYVIEW(dev))
> -#define HAS_PPGTT(dev)		(INTEL_INFO(dev)->gen >= 7 &&
> !IS_VALLEYVIEW(dev) \
> -				 && !IS_BROADWELL(dev))
> +#define HAS_ALIASING_PPGTT(dev)	(INTEL_INFO(dev)->gen >= 6 && \
> +				 (!IS_VALLEYVIEW(dev) ||
> IS_CHERRYVIEW(dev)))
> +#define HAS_PPGTT(dev)		(INTEL_INFO(dev)->gen >= 7 \
> +				 && !IS_GEN8(dev))
>  #define USES_PPGTT(dev)		intel_enable_ppgtt(dev, false)
>  #define USES_FULL_PPGTT(dev)	intel_enable_ppgtt(dev, true)
> 
> --
> 1.8.3.2
> 
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Re: [PATCH 06/71] drm/i915/chv: Add PIPESTAT register bits for Cherryview

[Barbalho, Rafael]

> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf
> Of ville.syrjala@linux.intel.com
> Sent: Wednesday, April 09, 2014 11:28 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 06/71] drm/i915/chv: Add PIPESTAT register bits
> for Cherryview
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> FIXME: We probably want to sprinkle _CHV suffixes over these.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index b6441da..0fb6b6f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3364,6 +3364,7 @@ enum punit_power_well {
>  #define   SPRITE1_FLIP_DONE_INT_EN_VLV		(1UL<<30)
>  #define   PIPE_CRC_ERROR_ENABLE			(1UL<<29)
>  #define   PIPE_CRC_DONE_ENABLE			(1UL<<28)
> +#define   PERF_COUNTER2_INTERRUPT_EN		(1UL<<27)
>  #define   PIPE_GMBUS_EVENT_ENABLE		(1UL<<27)
>  #define   PLANE_FLIP_DONE_INT_EN_VLV		(1UL<<26)
>  #define   PIPE_HOTPLUG_INTERRUPT_ENABLE		(1UL<<26)
> @@ -3375,8 +3376,10 @@ enum punit_power_well {
>  #define   PIPE_ODD_FIELD_INTERRUPT_ENABLE	(1UL<<21)
>  #define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE	(1UL<<20)
>  #define   PIPE_B_PSR_INTERRUPT_ENABLE_VLV	(1UL<<19)
> +#define   PERF_COUNTER_INTERRUPT_EN		(1UL<<19)
>  #define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE	(1UL<<18) /* pre-965
> */
>  #define   PIPE_START_VBLANK_INTERRUPT_ENABLE	(1UL<<18) /* 965 or
> later */
> +#define   PIPE_FRAMESTART_INTERRUPT_ENABLE	(1UL<<17)
>  #define   PIPE_VBLANK_INTERRUPT_ENABLE		(1UL<<17)
>  #define   PIPEA_HBLANK_INT_EN_VLV		(1UL<<16)
>  #define   PIPE_OVERLAY_UPDATED_ENABLE		(1UL<<16)
> @@ -3384,6 +3387,7 @@ enum punit_power_well {
>  #define   SPRITE0_FLIP_DONE_INT_STATUS_VLV	(1UL<<14)
>  #define   PIPE_CRC_ERROR_INTERRUPT_STATUS	(1UL<<13)
>  #define   PIPE_CRC_DONE_INTERRUPT_STATUS	(1UL<<12)
> +#define   PERF_COUNTER2_INTERRUPT_STATUS	(1UL<<11)
>  #define   PIPE_GMBUS_INTERRUPT_STATUS		(1UL<<11)
>  #define   PLANE_FLIP_DONE_INT_STATUS_VLV	(1UL<<10)
>  #define   PIPE_HOTPLUG_INTERRUPT_STATUS		(1UL<<10)
> @@ -3392,12 +3396,16 @@ enum punit_power_well {
>  #define   PIPE_DPST_EVENT_STATUS		(1UL<<7)
>  #define   PIPE_LEGACY_BLC_EVENT_STATUS		(1UL<<6)
>  #define   PIPE_A_PSR_STATUS_VLV			(1UL<<6)
> +#define   PIPE_LEGACY_BLC_EVENT_STATUS		(1UL<<6)
>  #define   PIPE_ODD_FIELD_INTERRUPT_STATUS	(1UL<<5)
>  #define   PIPE_EVEN_FIELD_INTERRUPT_STATUS	(1UL<<4)
>  #define   PIPE_B_PSR_STATUS_VLV			(1UL<<3)
> +#define   PERF_COUNTER_INTERRUPT_STATUS		(1UL<<3)
>  #define   PIPE_HOTPLUG_TV_INTERRUPT_STATUS	(1UL<<2) /* pre-965
> */
>  #define   PIPE_START_VBLANK_INTERRUPT_STATUS	(1UL<<2) /* 965 or
> later */
> +#define   PIPE_FRAMESTART_INTERRUPT_STATUS	(1UL<<1)
>  #define   PIPE_VBLANK_INTERRUPT_STATUS		(1UL<<1)
> +#define   PIPE_HBLANK_INT_STATUS		(1UL<<0)
>  #define   PIPE_OVERLAY_UPDATED_STATUS		(1UL<<0)
> 
>  #define PIPESTAT_INT_ENABLE_MASK		0x7fff0000
> --
> 1.8.3.2
> 
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Re: [PATCH 07/71] drm/i915/chv: Add DPFLIPSTAT register bits for Cherryview

[Barbalho, Rafael]

> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf
> Of ville.syrjala@linux.intel.com
> Sent: Wednesday, April 09, 2014 11:28 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 07/71] drm/i915/chv: Add DPFLIPSTAT register
> bits for Cherryview
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> CHV has pipe C and PSR which cause changes to DPFLIPSTAT.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

If we add the _CHV to some of the bitfield defines would you also add them to here? These are also CHV specific.

Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index 0fb6b6f..81d4b83 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3451,12 +3451,19 @@ enum punit_power_well {
>  #define   SPRITED_FLIP_DONE_INT_EN		(1<<26)
>  #define   SPRITEC_FLIP_DONE_INT_EN		(1<<25)
>  #define   PLANEB_FLIP_DONE_INT_EN		(1<<24)
> +#define   PIPE_PSR_INT_EN			(1<<22)
>  #define   PIPEA_LINE_COMPARE_INT_EN		(1<<21)
>  #define   PIPEA_HLINE_INT_EN			(1<<20)
>  #define   PIPEA_VBLANK_INT_EN			(1<<19)
>  #define   SPRITEB_FLIP_DONE_INT_EN		(1<<18)
>  #define   SPRITEA_FLIP_DONE_INT_EN		(1<<17)
>  #define   PLANEA_FLIPDONE_INT_EN		(1<<16)
> +#define   PIPEC_LINE_COMPARE_INT_EN		(1<<13)
> +#define   PIPEC_HLINE_INT_EN			(1<<12)
> +#define   PIPEC_VBLANK_INT_EN			(1<<11)
> +#define   SPRITEF_FLIPDONE_INT_EN		(1<<10)
> +#define   SPRITEE_FLIPDONE_INT_EN		(1<<9)
> +#define   PLANEC_FLIPDONE_INT_EN		(1<<8)
> 
>  #define DPINVGTT				(VLV_DISPLAY_BASE +
> 0x7002c) /* VLV only */
>  #define   CURSORB_INVALID_GTT_INT_EN		(1<<23)
> --
> 1.8.3.2
> 
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Re: [PATCH 09/71] drm/i915/chv: Add DPINVGTT registers defines for Cherryview

[Barbalho, Rafael]

> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf
> Of ville.syrjala@linux.intel.com
> Sent: Wednesday, April 09, 2014 11:28 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 09/71] drm/i915/chv: Add DPINVGTT registers
> defines for Cherryview
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Due to Pipe C DPINVGTT has more bits on CHV.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index 3def0fb..98f549a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3485,6 +3485,10 @@ enum punit_power_well {
>  #define   PLANEC_FLIPDONE_INT_EN		(1<<8)
> 
>  #define DPINVGTT				(VLV_DISPLAY_BASE +
> 0x7002c) /* VLV only */

The VLV only comment is not true anymore, it's in CHV also. With that small clean-up:
Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>

> +#define   SPRITEF_INVALID_GTT_INT_EN		(1<<27)
> +#define   SPRITEE_INVALID_GTT_INT_EN		(1<<26)
> +#define   PLANEC_INVALID_GTT_INT_EN		(1<<25)
> +#define   CURSORC_INVALID_GTT_INT_EN		(1<<24)
>  #define   CURSORB_INVALID_GTT_INT_EN		(1<<23)
>  #define   CURSORA_INVALID_GTT_INT_EN		(1<<22)
>  #define   SPRITED_INVALID_GTT_INT_EN		(1<<21)
> @@ -3494,6 +3498,11 @@ enum punit_power_well {
>  #define   SPRITEA_INVALID_GTT_INT_EN		(1<<17)
>  #define   PLANEA_INVALID_GTT_INT_EN		(1<<16)
>  #define   DPINVGTT_EN_MASK			0xff0000
> +#define   DPINVGTT_EN_MASK_CHV			0xfff0000
> +#define   SPRITEF_INVALID_GTT_STATUS		(1<<11)
> +#define   SPRITEE_INVALID_GTT_STATUS		(1<<10)
> +#define   PLANEC_INVALID_GTT_STATUS		(1<<9)
> +#define   CURSORC_INVALID_GTT_STATUS		(1<<8)
>  #define   CURSORB_INVALID_GTT_STATUS		(1<<7)
>  #define   CURSORA_INVALID_GTT_STATUS		(1<<6)
>  #define   SPRITED_INVALID_GTT_STATUS		(1<<5)
> @@ -3503,6 +3512,7 @@ enum punit_power_well {
>  #define   SPRITEA_INVALID_GTT_STATUS		(1<<1)
>  #define   PLANEA_INVALID_GTT_STATUS		(1<<0)
>  #define   DPINVGTT_STATUS_MASK			0xff
> +#define   DPINVGTT_STATUS_MASK_CHV		0xfff
> 
>  #define DSPARB			0x70030
>  #define   DSPARB_CSTART_MASK	(0x7f << 7)
> --
> 1.8.3.2
> 
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Re: [PATCH 08/71] drm/i915/chv: Add display interrupt registers bits for Cherryview

[Barbalho, Rafael]

> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf
> Of ville.syrjala@linux.intel.com
> Sent: Wednesday, April 09, 2014 11:28 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 08/71] drm/i915/chv: Add display interrupt
> registers bits for Cherryview
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> v2: Rebase on top of Ben's GT interrupt shuffling.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 21 ++++++++++++++++++++-
>  1 file changed, 20 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index 81d4b83..3def0fb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1112,24 +1112,43 @@ enum punit_power_well {
> 
>  /* These are all the "old" interrupts */
>  #define ILK_BSD_USER_INTERRUPT				(1<<5)
> +
> +#define I915_PM_INTERRUPT				(1<<31)
> +#define I915_ISP_INTERRUPT				(1<<22)
> +#define I915_LPE_PIPE_B_INTERRUPT			(1<<21)
> +#define I915_LPE_PIPE_A_INTERRUPT			(1<<20)
> +#define I915_MIPIB_INTERRUPT				(1<<19)
> +#define I915_MIPIA_INTERRUPT				(1<<18)
>  #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1<<18)
>  #define I915_DISPLAY_PORT_INTERRUPT			(1<<17)
> +#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT		(1<<16)
> +#define I915_MASTER_ERROR_INTERRUPT			(1<<15)
>  #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
> 	(1<<15)
> +#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT		(1<<14)
>  #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1<<14) /* p-
> state */
> +#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT		(1<<13)
>  #define I915_HWB_OOM_INTERRUPT				(1<<13)
> +#define I915_LPE_PIPE_C_INTERRUPT			(1<<12)
>  #define I915_SYNC_STATUS_INTERRUPT			(1<<12)
> +#define I915_MISC_INTERRUPT				(1<<11)
>  #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1<<11)
> +#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT		(1<<10)
>  #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1<<10)
> +#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT		(1<<9)
>  #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1<<9)
> +#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT		(1<<8)
>  #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1<<8)
>  #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1<<7)
>  #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1<<6)
>  #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1<<5)
>  #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1<<4)
> +#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT		(1<<3)
> +#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT		(1<<2)
>  #define I915_DEBUG_INTERRUPT				(1<<2)
> +#define I915_WINVALID_INTERRUPT				(1<<1)
>  #define I915_USER_INTERRUPT				(1<<1)
>  #define I915_ASLE_INTERRUPT				(1<<0)
> -#define I915_BSD_USER_INTERRUPT				(1 << 25)
> +#define I915_BSD_USER_INTERRUPT				(1<<25)
> 
>  #define GEN6_BSD_RNCID			0x12198
> 
> --
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH 07/71] drm/i915/chv: Add DPFLIPSTAT register bits for Cherryview

[Ville Syrjälä]

On Thu, May 01, 2014 at 01:55:23PM +0000, Barbalho, Rafael wrote:
> > -----Original Message-----
> > From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf
> > Of ville.syrjala@linux.intel.com
> > Sent: Wednesday, April 09, 2014 11:28 AM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [Intel-gfx] [PATCH 07/71] drm/i915/chv: Add DPFLIPSTAT register
> > bits for Cherryview
> > 
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > CHV has pipe C and PSR which cause changes to DPFLIPSTAT.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> If we add the _CHV to some of the bitfield defines would you also add them to here? These are also CHV specific.

I figured these are pretty clear even w/o the suffix. Everyone ought to
know VLV has two pipes and CHV has three.

> 
> Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>
> 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
> >  1 file changed, 7 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 0fb6b6f..81d4b83 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3451,12 +3451,19 @@ enum punit_power_well {
> >  #define   SPRITED_FLIP_DONE_INT_EN		(1<<26)
> >  #define   SPRITEC_FLIP_DONE_INT_EN		(1<<25)
> >  #define   PLANEB_FLIP_DONE_INT_EN		(1<<24)
> > +#define   PIPE_PSR_INT_EN			(1<<22)
> >  #define   PIPEA_LINE_COMPARE_INT_EN		(1<<21)
> >  #define   PIPEA_HLINE_INT_EN			(1<<20)
> >  #define   PIPEA_VBLANK_INT_EN			(1<<19)
> >  #define   SPRITEB_FLIP_DONE_INT_EN		(1<<18)
> >  #define   SPRITEA_FLIP_DONE_INT_EN		(1<<17)
> >  #define   PLANEA_FLIPDONE_INT_EN		(1<<16)
> > +#define   PIPEC_LINE_COMPARE_INT_EN		(1<<13)
> > +#define   PIPEC_HLINE_INT_EN			(1<<12)
> > +#define   PIPEC_VBLANK_INT_EN			(1<<11)
> > +#define   SPRITEF_FLIPDONE_INT_EN		(1<<10)
> > +#define   SPRITEE_FLIPDONE_INT_EN		(1<<9)
> > +#define   PLANEC_FLIPDONE_INT_EN		(1<<8)
> > 
> >  #define DPINVGTT				(VLV_DISPLAY_BASE +
> > 0x7002c) /* VLV only */
> >  #define   CURSORB_INVALID_GTT_INT_EN		(1<<23)
> > --
> > 1.8.3.2
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

[PATCH v2 09/71] drm/i915/chv: Add DPINVGTT registers defines for Cherryview

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Due to Pipe C DPINVGTT has more bits on CHV.

v2: Fix comment to say VLV/CHV (Rafael)

Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 12fa93a..666c1d0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3494,7 +3494,11 @@ enum punit_power_well {
 #define   SPRITEE_FLIPDONE_INT_EN		(1<<9)
 #define   PLANEC_FLIPDONE_INT_EN		(1<<8)
 
-#define DPINVGTT				(VLV_DISPLAY_BASE + 0x7002c) /* VLV only */
+#define DPINVGTT				(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
+#define   SPRITEF_INVALID_GTT_INT_EN		(1<<27)
+#define   SPRITEE_INVALID_GTT_INT_EN		(1<<26)
+#define   PLANEC_INVALID_GTT_INT_EN		(1<<25)
+#define   CURSORC_INVALID_GTT_INT_EN		(1<<24)
 #define   CURSORB_INVALID_GTT_INT_EN		(1<<23)
 #define   CURSORA_INVALID_GTT_INT_EN		(1<<22)
 #define   SPRITED_INVALID_GTT_INT_EN		(1<<21)
@@ -3504,6 +3508,11 @@ enum punit_power_well {
 #define   SPRITEA_INVALID_GTT_INT_EN		(1<<17)
 #define   PLANEA_INVALID_GTT_INT_EN		(1<<16)
 #define   DPINVGTT_EN_MASK			0xff0000
+#define   DPINVGTT_EN_MASK_CHV			0xfff0000
+#define   SPRITEF_INVALID_GTT_STATUS		(1<<11)
+#define   SPRITEE_INVALID_GTT_STATUS		(1<<10)
+#define   PLANEC_INVALID_GTT_STATUS		(1<<9)
+#define   CURSORC_INVALID_GTT_STATUS		(1<<8)
 #define   CURSORB_INVALID_GTT_STATUS		(1<<7)
 #define   CURSORA_INVALID_GTT_STATUS		(1<<6)
 #define   SPRITED_INVALID_GTT_STATUS		(1<<5)
@@ -3513,6 +3522,7 @@ enum punit_power_well {
 #define   SPRITEA_INVALID_GTT_STATUS		(1<<1)
 #define   PLANEA_INVALID_GTT_STATUS		(1<<0)
 #define   DPINVGTT_STATUS_MASK			0xff
+#define   DPINVGTT_STATUS_MASK_CHV		0xfff
 
 #define DSPARB			0x70030
 #define   DSPARB_CSTART_MASK	(0x7f << 7)
-- 
1.8.3.2

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[PATCH v6 21/71] drm/i915/chv: Add update and enable pll for Cherryview

[ville.syrjala]

From: Chon Ming Lee <chon.ming.lee@intel.com>

Added programming PLL for CHV based on "Application note for 1273 CHV
Display phy".

v2:  -Break the common lane reset into another patch.
     -Break the clock calculation into another patch.

    -The changes are based on Ville review.
    -Rework based on DPIO register define naming convention change.
    -Break the dpio write into few lines to improve readability.
    -Correct the udelay during chv_enable_pll.
    -clean up some magic numbers with some new define.
    -program the afc recal bit which was missed.

v3: Based on Ville review
	-  minor correction of the bit defination
    - add deassert/propagate data lane reset

v4: Corrected the udelay between dclkp enable and pll enable.
	Minor comment and better way to clear the TX lane reset.

v5: Squash in fixup from Rafael Barbalho.

[vsyrjala: v6: Polish the defines (Imre)]

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  70 ++++++++++++++++++
 drivers/gpu/drm/i915/intel_display.c | 134 ++++++++++++++++++++++++++++++++++-
 2 files changed, 202 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e4ea252..35a4df8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -677,6 +677,12 @@ enum punit_power_well {
 #define _VLV_PCS_DW9_CH1		0x8424
 #define	VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
 
+#define _CHV_PCS_DW10_CH0		0x8228
+#define _CHV_PCS_DW10_CH1		0x8428
+#define   DPIO_PCS_SWING_CALC_TX0_TX2	(1<<30)
+#define   DPIO_PCS_SWING_CALC_TX1_TX3	(1<<31)
+#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
+
 #define _VLV_PCS_DW11_CH0		0x822c
 #define _VLV_PCS_DW11_CH1		0x842c
 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
@@ -695,14 +701,21 @@ enum punit_power_well {
 
 #define _VLV_TX_DW2_CH0			0x8288
 #define _VLV_TX_DW2_CH1			0x8488
+#define   DPIO_SWING_MARGIN_SHIFT	16
+#define   DPIO_SWING_MARGIN_MASK	(0xff << DPIO_SWING_MARGIN_SHIFT)
+#define   DPIO_UNIQ_TRANS_SCALE_SHIFT	8
 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
 
 #define _VLV_TX_DW3_CH0			0x828c
 #define _VLV_TX_DW3_CH1			0x848c
+/* The following bit for CHV phy */
+#define   DPIO_TX_UNIQ_TRANS_SCALE_EN	(1<<27)
 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
 
 #define _VLV_TX_DW4_CH0			0x8290
 #define _VLV_TX_DW4_CH1			0x8490
+#define   DPIO_SWING_DEEMPH9P5_SHIFT	24
+#define   DPIO_SWING_DEEMPH9P5_MASK	(0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
 
 #define _VLV_TX3_DW4_CH0		0x690
@@ -722,6 +735,62 @@ enum punit_power_well {
 #define _VLV_TX_DW14_CH1		0x84b8
 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
 
+/* CHV dpPhy registers */
+#define _CHV_PLL_DW0_CH0		0x8000
+#define _CHV_PLL_DW0_CH1		0x8180
+#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
+
+#define _CHV_PLL_DW1_CH0		0x8004
+#define _CHV_PLL_DW1_CH1		0x8184
+#define   DPIO_CHV_N_DIV_SHIFT		8
+#define   DPIO_CHV_M1_DIV_BY_2		(0 << 0)
+#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
+
+#define _CHV_PLL_DW2_CH0		0x8008
+#define _CHV_PLL_DW2_CH1		0x8188
+#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
+
+#define _CHV_PLL_DW3_CH0		0x800c
+#define _CHV_PLL_DW3_CH1		0x818c
+#define  DPIO_CHV_FRAC_DIV_EN		(1 << 16)
+#define  DPIO_CHV_FIRST_MOD		(0 << 8)
+#define  DPIO_CHV_SECOND_MOD		(1 << 8)
+#define  DPIO_CHV_FEEDFWD_GAIN_SHIFT	0
+#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
+
+#define _CHV_PLL_DW6_CH0		0x8018
+#define _CHV_PLL_DW6_CH1		0x8198
+#define   DPIO_CHV_GAIN_CTRL_SHIFT	16
+#define	  DPIO_CHV_INT_COEFF_SHIFT	8
+#define   DPIO_CHV_PROP_COEFF_SHIFT	0
+#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
+
+#define _CHV_CMN_DW13_CH0		0x8134
+#define _CHV_CMN_DW0_CH1		0x8080
+#define   DPIO_CHV_S1_DIV_SHIFT		21
+#define   DPIO_CHV_P1_DIV_SHIFT		13 /* 3 bits */
+#define   DPIO_CHV_P2_DIV_SHIFT		8  /* 5 bits */
+#define   DPIO_CHV_K_DIV_SHIFT		4
+#define   DPIO_PLL_FREQLOCK		(1 << 1)
+#define   DPIO_PLL_LOCK			(1 << 0)
+#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
+
+#define _CHV_CMN_DW14_CH0		0x8138
+#define _CHV_CMN_DW1_CH1		0x8084
+#define   DPIO_AFC_RECAL		(1 << 14)
+#define   DPIO_DCLKP_EN			(1 << 13)
+#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
+
+#define CHV_CMN_DW30			0x8178
+#define   DPIO_LRC_BYPASS		(1 << 3)
+
+#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
+					(lane) * 0x200 + (offset))
+
+#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
+#define   DPIO_FRC_LATENCY_SHFIT	8
+#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
+#define   DPIO_UPAR_SHIFT		30
 /*
  * Fence registers
  */
@@ -1393,6 +1462,7 @@ enum punit_power_well {
 #define   DPLL_LOCK_VLV			(1<<15)
 #define   DPLL_INTEGRATED_CRI_CLK_VLV	(1<<14)
 #define   DPLL_INTEGRATED_CLOCK_VLV	(1<<13)
+#define   DPLL_SSC_REF_CLOCK_CHV	(1<<13)
 #define   DPLL_PORTC_READY_MASK		(0xf << 4)
 #define   DPLL_PORTB_READY_MASK		(0xf)
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3b03e71..ff19d88 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1549,6 +1549,49 @@ static void vlv_enable_pll(struct intel_crtc *crtc)
 	udelay(150); /* wait for warmup */
 }
 
+static void chv_enable_pll(struct intel_crtc *crtc)
+{
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int pipe = crtc->pipe;
+	enum dpio_channel port = vlv_pipe_to_channel(pipe);
+	int dpll = DPLL(crtc->pipe);
+	u32 tmp;
+
+	assert_pipe_disabled(dev_priv, crtc->pipe);
+
+	BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
+
+	mutex_lock(&dev_priv->dpio_lock);
+
+	/* Enable back the 10bit clock to display controller */
+	tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
+	tmp |= DPIO_DCLKP_EN;
+	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
+
+	/*
+	 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
+	 */
+	udelay(1);
+
+	/* Enable PLL */
+	tmp = I915_READ(dpll);
+	tmp |= DPLL_VCO_ENABLE;
+	I915_WRITE(dpll, tmp);
+
+	/* Check PLL is locked */
+	if (wait_for(((I915_READ(dpll) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
+		DRM_ERROR("PLL %d failed to lock\n", pipe);
+
+	/* Deassert soft data lane reset*/
+	tmp = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
+	tmp |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), tmp);
+
+
+	mutex_unlock(&dev_priv->dpio_lock);
+}
+
 static void i9xx_enable_pll(struct intel_crtc *crtc)
 {
 	struct drm_device *dev = crtc->base.dev;
@@ -4490,8 +4533,12 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 
 	is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
 
-	if (!is_dsi)
-		vlv_enable_pll(intel_crtc);
+	if (!is_dsi) {
+		if (IS_CHERRYVIEW(dev))
+			chv_enable_pll(intel_crtc);
+		else
+			vlv_enable_pll(intel_crtc);
+	}
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->pre_enable)
@@ -5372,6 +5419,87 @@ static void vlv_update_pll(struct intel_crtc *crtc)
 	mutex_unlock(&dev_priv->dpio_lock);
 }
 
+static void chv_update_pll(struct intel_crtc *crtc)
+{
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int pipe = crtc->pipe;
+	int dpll_reg = DPLL(crtc->pipe);
+	enum dpio_channel port = vlv_pipe_to_channel(pipe);
+	u32 val, loopfilter, intcoeff;
+	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
+	int refclk;
+
+	mutex_lock(&dev_priv->dpio_lock);
+
+	bestn = crtc->config.dpll.n;
+	bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
+	bestm1 = crtc->config.dpll.m1;
+	bestm2 = crtc->config.dpll.m2 >> 22;
+	bestp1 = crtc->config.dpll.p1;
+	bestp2 = crtc->config.dpll.p2;
+
+	/*
+	 * Enable Refclk and SSC
+	 */
+	val = I915_READ(dpll_reg);
+	val |= (DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV);
+	I915_WRITE(dpll_reg, val);
+
+	/* Propagate soft reset to data lane reset */
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
+	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), val);
+
+	/* Disable 10bit clock to display controller */
+	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
+	val &= ~DPIO_DCLKP_EN;
+	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
+
+	/* p1 and p2 divider */
+	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
+			5 << DPIO_CHV_S1_DIV_SHIFT |
+			bestp1 << DPIO_CHV_P1_DIV_SHIFT |
+			bestp2 << DPIO_CHV_P2_DIV_SHIFT |
+			1 << DPIO_CHV_K_DIV_SHIFT);
+
+	/* Feedback post-divider - m2 */
+	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
+
+	/* Feedback refclk divider - n and m1 */
+	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
+			DPIO_CHV_M1_DIV_BY_2 |
+			1 << DPIO_CHV_N_DIV_SHIFT);
+
+	/* M2 fraction division */
+	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
+
+	/* M2 fraction division enable */
+	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
+		       DPIO_CHV_FRAC_DIV_EN |
+		       (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
+
+	/* Loop filter */
+	refclk = i9xx_get_refclk(&crtc->base, 0);
+	loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
+		2 << DPIO_CHV_GAIN_CTRL_SHIFT;
+	if (refclk == 100000)
+		intcoeff = 11;
+	else if (refclk == 38400)
+		intcoeff = 10;
+	else
+		intcoeff = 9;
+	loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
+	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
+
+	/* AFC Recal */
+	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
+			vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
+			DPIO_AFC_RECAL);
+
+	mutex_unlock(&dev_priv->dpio_lock);
+}
+
 static void i9xx_update_pll(struct intel_crtc *crtc,
 			    intel_clock_t *reduced_clock,
 			    int num_connectors)
@@ -5755,6 +5883,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 		i8xx_update_pll(intel_crtc,
 				has_reduced_clock ? &reduced_clock : NULL,
 				num_connectors);
+	} else if (IS_CHERRYVIEW(dev)) {
+		chv_update_pll(intel_crtc);
 	} else if (IS_VALLEYVIEW(dev)) {
 		vlv_update_pll(intel_crtc);
 	} else {
-- 
1.8.3.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 07/71] drm/i915/chv: Add DPFLIPSTAT register bits for Cherryview

[Daniel Vetter]

On Fri, May 02, 2014 at 11:29:16AM +0300, Ville Syrjälä wrote:
> On Thu, May 01, 2014 at 01:55:23PM +0000, Barbalho, Rafael wrote:
> > > -----Original Message-----
> > > From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf
> > > Of ville.syrjala@linux.intel.com
> > > Sent: Wednesday, April 09, 2014 11:28 AM
> > > To: intel-gfx@lists.freedesktop.org
> > > Subject: [Intel-gfx] [PATCH 07/71] drm/i915/chv: Add DPFLIPSTAT register
> > > bits for Cherryview
> > > 
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > CHV has pipe C and PSR which cause changes to DPFLIPSTAT.
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > If we add the _CHV to some of the bitfield defines would you also add them to here? These are also CHV specific.
> 
> I figured these are pretty clear even w/o the suffix. Everyone ought to
> know VLV has two pipes and CHV has three.

I agree with Ville here - if the bitfields are just evenly laid out
extensions of previously reserved fields then adding a suffix just
confuses. Otoh if the bits are all over the place and reuse bits from
older generations the suffix is good as a signal to the reader to pay
closer attention.

In the end it's about what reads easier and conveys more useful
information to the reader.
-Daniel

> 
> > 
> > Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>
> > 
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
> > >  1 file changed, 7 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h index 0fb6b6f..81d4b83 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -3451,12 +3451,19 @@ enum punit_power_well {
> > >  #define   SPRITED_FLIP_DONE_INT_EN		(1<<26)
> > >  #define   SPRITEC_FLIP_DONE_INT_EN		(1<<25)
> > >  #define   PLANEB_FLIP_DONE_INT_EN		(1<<24)
> > > +#define   PIPE_PSR_INT_EN			(1<<22)
> > >  #define   PIPEA_LINE_COMPARE_INT_EN		(1<<21)
> > >  #define   PIPEA_HLINE_INT_EN			(1<<20)
> > >  #define   PIPEA_VBLANK_INT_EN			(1<<19)
> > >  #define   SPRITEB_FLIP_DONE_INT_EN		(1<<18)
> > >  #define   SPRITEA_FLIP_DONE_INT_EN		(1<<17)
> > >  #define   PLANEA_FLIPDONE_INT_EN		(1<<16)
> > > +#define   PIPEC_LINE_COMPARE_INT_EN		(1<<13)
> > > +#define   PIPEC_HLINE_INT_EN			(1<<12)
> > > +#define   PIPEC_VBLANK_INT_EN			(1<<11)
> > > +#define   SPRITEF_FLIPDONE_INT_EN		(1<<10)
> > > +#define   SPRITEE_FLIPDONE_INT_EN		(1<<9)
> > > +#define   PLANEC_FLIPDONE_INT_EN		(1<<8)
> > > 
> > >  #define DPINVGTT				(VLV_DISPLAY_BASE +
> > > 0x7002c) /* VLV only */
> > >  #define   CURSORB_INVALID_GTT_INT_EN		(1<<23)
> > > --
> > > 1.8.3.2
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 04/71] drm/i915/chv: Flush caches when programming page tables

[Daniel Vetter]

On Wed, Apr 09, 2014 at 01:28:02PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Rafael Barbalho <rafael.barbalho@intel.com>
> 
> Page table updates were getting stuck in the CPU cache on chv causing
> spurious page faults and strange behaviour.
> 
> Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
> [vsyrjala: Add !HAS_LLC checks]
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed this myself. Poke for the gen7/byt version of this ...
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 3e4d1f0..ba51901 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -267,6 +267,8 @@ static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
>  			num_entries--;
>  		}
>  
> +		if (!HAS_LLC(ppgtt->base.dev))
> +			drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
>  		kunmap_atomic(pt_vaddr);
>  
>  		pte = 0;
> @@ -303,6 +305,8 @@ static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
>  			gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
>  					cache_level, true);
>  		if (++pte == GEN8_PTES_PER_PAGE) {
> +			if (!HAS_LLC(ppgtt->base.dev))
> +				drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
>  			kunmap_atomic(pt_vaddr);
>  			pt_vaddr = NULL;
>  			if (++pde == GEN8_PDES_PER_PAGE) {
> @@ -312,8 +316,11 @@ static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
>  			pte = 0;
>  		}
>  	}
> -	if (pt_vaddr)
> +	if (pt_vaddr) {
> +		if (!HAS_LLC(ppgtt->base.dev))
> +			drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
>  		kunmap_atomic(pt_vaddr);
> +	}
>  }
>  
>  static void gen8_free_page_tables(struct page **pt_pages)
> @@ -576,6 +583,8 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
>  			pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
>  						      I915_CACHE_LLC);
>  		}
> +		if (!HAS_LLC(ppgtt->base.dev))
> +			drm_clflush_virt_range(pd_vaddr, PAGE_SIZE);
>  		kunmap_atomic(pd_vaddr);
>  	}
>  
> -- 
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH v2 09/71] drm/i915/chv: Add DPINVGTT registers defines for Cherryview

[Daniel Vetter]

On Fri, May 02, 2014 at 11:35:51AM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Due to Pipe C DPINVGTT has more bits on CHV.
> 
> v2: Fix comment to say VLV/CHV (Rafael)
> 
> Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Merged up to this one to dinq.
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 12fa93a..666c1d0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3494,7 +3494,11 @@ enum punit_power_well {
>  #define   SPRITEE_FLIPDONE_INT_EN		(1<<9)
>  #define   PLANEC_FLIPDONE_INT_EN		(1<<8)
>  
> -#define DPINVGTT				(VLV_DISPLAY_BASE + 0x7002c) /* VLV only */
> +#define DPINVGTT				(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
> +#define   SPRITEF_INVALID_GTT_INT_EN		(1<<27)
> +#define   SPRITEE_INVALID_GTT_INT_EN		(1<<26)
> +#define   PLANEC_INVALID_GTT_INT_EN		(1<<25)
> +#define   CURSORC_INVALID_GTT_INT_EN		(1<<24)
>  #define   CURSORB_INVALID_GTT_INT_EN		(1<<23)
>  #define   CURSORA_INVALID_GTT_INT_EN		(1<<22)
>  #define   SPRITED_INVALID_GTT_INT_EN		(1<<21)
> @@ -3504,6 +3508,11 @@ enum punit_power_well {
>  #define   SPRITEA_INVALID_GTT_INT_EN		(1<<17)
>  #define   PLANEA_INVALID_GTT_INT_EN		(1<<16)
>  #define   DPINVGTT_EN_MASK			0xff0000
> +#define   DPINVGTT_EN_MASK_CHV			0xfff0000
> +#define   SPRITEF_INVALID_GTT_STATUS		(1<<11)
> +#define   SPRITEE_INVALID_GTT_STATUS		(1<<10)
> +#define   PLANEC_INVALID_GTT_STATUS		(1<<9)
> +#define   CURSORC_INVALID_GTT_STATUS		(1<<8)
>  #define   CURSORB_INVALID_GTT_STATUS		(1<<7)
>  #define   CURSORA_INVALID_GTT_STATUS		(1<<6)
>  #define   SPRITED_INVALID_GTT_STATUS		(1<<5)
> @@ -3513,6 +3522,7 @@ enum punit_power_well {
>  #define   SPRITEA_INVALID_GTT_STATUS		(1<<1)
>  #define   PLANEA_INVALID_GTT_STATUS		(1<<0)
>  #define   DPINVGTT_STATUS_MASK			0xff
> +#define   DPINVGTT_STATUS_MASK_CHV		0xfff
>  
>  #define DSPARB			0x70030
>  #define   DSPARB_CSTART_MASK	(0x7f << 7)
> -- 
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 11/71] drm/i915/chv: Add Cherryview interrupt registers into debugfs

[Jani Nikula]

On Wed, 09 Apr 2014, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Make i915_gem_interrupt debugfs file functional on CHV.
>
> FIXME: Extract helpers for gt/display blocks to shrink the function a
> bit and avoid duplication between bdw/chv (and other similar cases for
> upstream).

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 42 ++++++++++++++++++++++++++++++++++++-
>  1 file changed, 41 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 506177a..1efb885 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -638,7 +638,47 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
>  		return ret;
>  	intel_runtime_pm_get(dev_priv);
>  
> -	if (INTEL_INFO(dev)->gen >= 8) {
> +	if (IS_CHERRYVIEW(dev)) {
> +		int i;
> +		seq_printf(m, "Master Interrupt Control:\t%08x\n",
> +			   I915_READ(GEN8_MASTER_IRQ));
> +
> +		seq_printf(m, "Display IER:\t%08x\n",
> +			   I915_READ(VLV_IER));
> +		seq_printf(m, "Display IIR:\t%08x\n",
> +			   I915_READ(VLV_IIR));
> +		seq_printf(m, "Display IIR_RW:\t%08x\n",
> +			   I915_READ(VLV_IIR_RW));
> +		seq_printf(m, "Display IMR:\t%08x\n",
> +			   I915_READ(VLV_IMR));
> +		for_each_pipe(pipe)
> +			seq_printf(m, "Pipe %c stat:\t%08x\n",
> +				   pipe_name(pipe),
> +				   I915_READ(PIPESTAT(pipe)));
> +
> +		seq_printf(m, "Port hotplug:\t%08x\n",
> +			   I915_READ(PORT_HOTPLUG_EN));
> +		seq_printf(m, "DPFLIPSTAT:\t%08x\n",
> +			   I915_READ(VLV_DPFLIPSTAT));
> +		seq_printf(m, "DPINVGTT:\t%08x\n",
> +			   I915_READ(DPINVGTT));
> +
> +		for (i = 0; i < 4; i++) {
> +			seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
> +				   i, I915_READ(GEN8_GT_IMR(i)));
> +			seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
> +				   i, I915_READ(GEN8_GT_IIR(i)));
> +			seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
> +				   i, I915_READ(GEN8_GT_IER(i)));
> +		}
> +
> +		seq_printf(m, "PCU interrupt mask:\t%08x\n",
> +			   I915_READ(GEN8_PCU_IMR));
> +		seq_printf(m, "PCU interrupt identity:\t%08x\n",
> +			   I915_READ(GEN8_PCU_IIR));
> +		seq_printf(m, "PCU interrupt enable:\t%08x\n",
> +			   I915_READ(GEN8_PCU_IER));
> +	} else if (INTEL_INFO(dev)->gen >= 8) {
>  		seq_printf(m, "Master Interrupt Control:\t%08x\n",
>  			   I915_READ(GEN8_MASTER_IRQ));
>  
> -- 
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v5 13/71] drm/i915/chv: Add Cherryview PCI IDs

[Jani Nikula]

On Wed, 09 Apr 2014, ville.syrjala@linux.intel.com wrote:
> From: Daniel Vetter <daniel.vetter@ffwll.ch>
>
> v2: Update to also fill in the new num_pipes field.
>
> v3: Rebase on top of the pciid extraction.
>
> v4: Switch from info->has*ring to info->ring mask. Also add VEBOX support whiel
> at it.
>
> v5: s/CHV_PCI_IDS/CHV_IDS/, and drop the trailing '\'
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 12 +++++++++++-
>  include/drm/i915_pciids.h       |  6 ++++++
>  2 files changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index fa5d0ed..5a55131 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -279,6 +279,15 @@ static const struct intel_device_info intel_broadwell_m_info = {
>  	GEN_DEFAULT_PIPEOFFSETS,
>  };
>  
> +static const struct intel_device_info intel_cherryview_info = {
> +	.is_preliminary = 1,
> +	.gen = 8, .num_pipes = 2,
> +	.need_gfx_hws = 1, .has_hotplug = 1,
> +	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
> +	.is_valleyview = 1,

I hope we're not going to regret this... gotta be careful at each
IS_VALLEYVIEW()!

Reviewed-by: Jani Nikula <jani.nikula@intel.com>



> +	.display_mmio_offset = VLV_DISPLAY_BASE,
> +};
> +
>  /*
>   * Make sure any device matches here are from most specific to most
>   * general.  For example, since the Quanta match is based on the subsystem
> @@ -312,7 +321,8 @@ static const struct intel_device_info intel_broadwell_m_info = {
>  	INTEL_VLV_M_IDS(&intel_valleyview_m_info),	\
>  	INTEL_VLV_D_IDS(&intel_valleyview_d_info),	\
>  	INTEL_BDW_M_IDS(&intel_broadwell_m_info),	\
> -	INTEL_BDW_D_IDS(&intel_broadwell_d_info)
> +	INTEL_BDW_D_IDS(&intel_broadwell_d_info),	\
> +	INTEL_CHV_IDS(&intel_cherryview_info)
>  
>  static const struct pci_device_id pciidlist[] = {		/* aka */
>  	INTEL_PCI_IDS,
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 940ece4..73274f9 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -233,4 +233,10 @@
>  	_INTEL_BDW_D_IDS(2, info), \
>  	_INTEL_BDW_D_IDS(3, info)
>  
> +#define INTEL_CHV_IDS(info) \
> +	INTEL_VGA_DEVICE(0x22b0, info), \
> +	INTEL_VGA_DEVICE(0x22b1, info), \
> +	INTEL_VGA_DEVICE(0x22b2, info), \
> +	INTEL_VGA_DEVICE(0x22b3, info)
> +
>  #endif /* _I915_PCIIDS_H */
> -- 
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 14/71] drm/i915/chv: Add early quirk for stolen

[Jani Nikula]

On Wed, 09 Apr 2014, ville.syrjala@linux.intel.com wrote:
> From: Daniel Vetter <daniel.vetter@ffwll.ch>
>
> Same as on other gen8 devices.
>
> Cc: Ingo Molnar <mingo@kernel.org>
> Cc: H. Peter Anvin <hpa@zytor.com>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  arch/x86/kernel/early-quirks.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index bc4a088..5758f5b 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -347,7 +347,8 @@ static struct pci_device_id intel_stolen_ids[] __initdata = {
>  	INTEL_HSW_D_IDS(gen6_stolen_size),
>  	INTEL_HSW_M_IDS(gen6_stolen_size),
>  	INTEL_BDW_M_IDS(gen8_stolen_size),
> -	INTEL_BDW_D_IDS(gen8_stolen_size)
> +	INTEL_BDW_D_IDS(gen8_stolen_size),
> +	INTEL_CHV_PCI_IDS(gen8_stolen_size)

Needs refresh after the update to the #define.

Otherwise,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>  };
>  
>  static void __init intel_graphics_stolen(int num, int slot, int func)
> -- 
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center

Re: [PATCH 12/71] drm/i915/chv: Initial clock gating support for Cherryview

[Jani Nikula]

On Wed, 09 Apr 2014, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> CHV clock gating isn't identical to VLV, so add a new function
> for it. This is only a start, and further changes are needed as
> the details become available.
>

I'm a bit on thin ice here, but with the "Reviewer's statement of
oversight" in mind,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>




> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 21cfbc7..0889af7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5122,6 +5122,15 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
>  }
>  
> +static void cherryview_init_clock_gating(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
> +
> +	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
> +}
> +
>  static void g4x_init_clock_gating(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -6015,6 +6024,10 @@ void intel_init_pm(struct drm_device *dev)
>  			dev_priv->display.init_clock_gating = haswell_init_clock_gating;
>  		else if (INTEL_INFO(dev)->gen == 8)
>  			dev_priv->display.init_clock_gating = gen8_init_clock_gating;
> +	} else if (IS_CHERRYVIEW(dev)) {
> +		dev_priv->display.update_wm = valleyview_update_wm;
> +		dev_priv->display.init_clock_gating =
> +			cherryview_init_clock_gating;
>  	} else if (IS_VALLEYVIEW(dev)) {
>  		dev_priv->display.update_wm = valleyview_update_wm;
>  		dev_priv->display.init_clock_gating =
> -- 
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
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Re: [PATCH 15/71] drm/i915/chv: Add DDL register defines for Cherryview

[Jani Nikula]

On Wed, 09 Apr 2014, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Fill in the sprite bits for DDL1/DDL2 registers, and add DDL3.
>
> Still need to write the code to use these...
>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>



> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 29 +++++++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 98f549a..c7ec7d6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3552,14 +3552,43 @@ enum punit_power_well {
>  #define DDL_CURSORA_PRECISION_32	(1<<31)
>  #define DDL_CURSORA_PRECISION_16	(0<<31)
>  #define DDL_CURSORA_SHIFT		24
> +#define DDL_SPRITEB_PRECISION_32	(1<<23)
> +#define DDL_SPRITEB_PRECISION_16	(0<<23)
> +#define DDL_SPRITEB_SHIFT		16
> +#define DDL_SPRITEA_PRECISION_32	(1<<15)
> +#define DDL_SPRITEA_PRECISION_16	(0<<15)
> +#define DDL_SPRITEA_SHIFT		8
>  #define DDL_PLANEA_PRECISION_32		(1<<7)
>  #define DDL_PLANEA_PRECISION_16		(0<<7)
> +#define DDL_PLANEA_SHIFT		0
> +
>  #define VLV_DDL2			(VLV_DISPLAY_BASE + 0x70054)
>  #define DDL_CURSORB_PRECISION_32	(1<<31)
>  #define DDL_CURSORB_PRECISION_16	(0<<31)
>  #define DDL_CURSORB_SHIFT		24
> +#define DDL_SPRITED_PRECISION_32	(1<<23)
> +#define DDL_SPRITED_PRECISION_16	(0<<23)
> +#define DDL_SPRITED_SHIFT		16
> +#define DDL_SPRITEC_PRECISION_32	(1<<15)
> +#define DDL_SPRITEC_PRECISION_16	(0<<15)
> +#define DDL_SPRITEC_SHIFT		8
>  #define DDL_PLANEB_PRECISION_32		(1<<7)
>  #define DDL_PLANEB_PRECISION_16		(0<<7)
> +#define DDL_PLANEB_SHIFT		0
> +
> +#define VLV_DDL3			(VLV_DISPLAY_BASE + 0x70058)
> +#define DDL_CURSORC_PRECISION_32	(1<<31)
> +#define DDL_CURSORC_PRECISION_16	(0<<31)
> +#define DDL_CURSORC_SHIFT		24
> +#define DDL_SPRITEF_PRECISION_32	(1<<23)
> +#define DDL_SPRITEF_PRECISION_16	(0<<23)
> +#define DDL_SPRITEF_SHIFT		16
> +#define DDL_SPRITEE_PRECISION_32	(1<<15)
> +#define DDL_SPRITEE_PRECISION_16	(0<<15)
> +#define DDL_SPRITEE_SHIFT		8
> +#define DDL_PLANEC_PRECISION_32		(1<<7)
> +#define DDL_PLANEC_PRECISION_16		(0<<7)
> +#define DDL_PLANEC_SHIFT		0
>  
>  /* FIFO watermark sizes etc */
>  #define G4X_FIFO_LINE_SIZE	64
> -- 
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
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Re: [PATCH 14/71] drm/i915/chv: Add early quirk for stolen

[Ville Syrjälä]

On Thu, May 08, 2014 at 05:32:21PM +0300, Jani Nikula wrote:
> On Wed, 09 Apr 2014, ville.syrjala@linux.intel.com wrote:
> > From: Daniel Vetter <daniel.vetter@ffwll.ch>
> >
> > Same as on other gen8 devices.
> >
> > Cc: Ingo Molnar <mingo@kernel.org>
> > Cc: H. Peter Anvin <hpa@zytor.com>
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > ---
> >  arch/x86/kernel/early-quirks.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> > index bc4a088..5758f5b 100644
> > --- a/arch/x86/kernel/early-quirks.c
> > +++ b/arch/x86/kernel/early-quirks.c
> > @@ -347,7 +347,8 @@ static struct pci_device_id intel_stolen_ids[] __initdata = {
> >  	INTEL_HSW_D_IDS(gen6_stolen_size),
> >  	INTEL_HSW_M_IDS(gen6_stolen_size),
> >  	INTEL_BDW_M_IDS(gen8_stolen_size),
> > -	INTEL_BDW_D_IDS(gen8_stolen_size)
> > +	INTEL_BDW_D_IDS(gen8_stolen_size),
> > +	INTEL_CHV_PCI_IDS(gen8_stolen_size)
> 
> Needs refresh after the update to the #define.

This patch is actually wrong. We need CHV specific stolen size detection
here. And in fact we get it as part of patch 34/71. I'll go and split
that up into i915 and x86 specific parts and pretend that this patch
never existed.

> 
> Otherwise,
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> 
> >  };
> >  
> >  static void __init intel_graphics_stolen(int num, int slot, int func)
> > -- 
> > 1.8.3.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 14/71] drm/i915/chv: Add early quirk for stolen

[Jani Nikula]

On Thu, 08 May 2014, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, May 08, 2014 at 05:32:21PM +0300, Jani Nikula wrote:
>> On Wed, 09 Apr 2014, ville.syrjala@linux.intel.com wrote:
>> > From: Daniel Vetter <daniel.vetter@ffwll.ch>
>> >
>> > Same as on other gen8 devices.
>> >
>> > Cc: Ingo Molnar <mingo@kernel.org>
>> > Cc: H. Peter Anvin <hpa@zytor.com>
>> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>> > ---
>> >  arch/x86/kernel/early-quirks.c | 3 ++-
>> >  1 file changed, 2 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
>> > index bc4a088..5758f5b 100644
>> > --- a/arch/x86/kernel/early-quirks.c
>> > +++ b/arch/x86/kernel/early-quirks.c
>> > @@ -347,7 +347,8 @@ static struct pci_device_id intel_stolen_ids[] __initdata = {
>> >  	INTEL_HSW_D_IDS(gen6_stolen_size),
>> >  	INTEL_HSW_M_IDS(gen6_stolen_size),
>> >  	INTEL_BDW_M_IDS(gen8_stolen_size),
>> > -	INTEL_BDW_D_IDS(gen8_stolen_size)
>> > +	INTEL_BDW_D_IDS(gen8_stolen_size),
>> > +	INTEL_CHV_PCI_IDS(gen8_stolen_size)
>> 
>> Needs refresh after the update to the #define.
>
> This patch is actually wrong. We need CHV specific stolen size detection
> here. And in fact we get it as part of patch 34/71. I'll go and split
> that up into i915 and x86 specific parts and pretend that this patch
> never existed.

Right, I'm actually looking at 34 now.

>
>> 
>> Otherwise,
>> 
>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>> 
>> 
>> >  };
>> >  
>> >  static void __init intel_graphics_stolen(int num, int slot, int func)
>> > -- 
>> > 1.8.3.2
>> >
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> 
>> -- 
>> Jani Nikula, Intel Open Source Technology Center
>
> -- 
> Ville Syrjälä
> Intel OTC

-- 
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Re: [PATCH 34/71] drm/i915/chv: Implement stolen memory size detection

[Jani Nikula]

On Wed, 09 Apr 2014, ville.syrjala@linux.intel.com wrote:
> From: Damien Lespiau <damien.lespiau@intel.com>
>
> CHV uses the same bits as SNB/VLV to code the Graphics Mode Select field
> (GFX stolen memory size) with the addition of finer granularity modes:
> 4MB increments from 0x11 (8MB) to 0x1d.
>
> Values strictly above 0x1d are either reserved or not supported.
>
> v2: 4MB increments, not 8MB. 32MB has been omitted from the list of new
>     values (Ville Syrjälä)
>
> v3: Also correctly interpret GGMS (GTT Graphics Memory Size) (Ville
>     Syrjälä)
>
> v4: Don't assign a value that needs 20bits or more to a u16 (Rafael
>     Barbalho)
>

Folded to patch 14, and fixed to use INTEL_CHV_IDS,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>
> Tested-by: Rafael Barbalho <rafael.barbalho@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  arch/x86/kernel/early-quirks.c      | 23 +++++++++++++++++++++-
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 38 +++++++++++++++++++++++++++++++++++--
>  2 files changed, 58 insertions(+), 3 deletions(-)
>
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index 5758f5b..46ce15c 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -323,6 +323,27 @@ static inline size_t gen8_stolen_size(int num, int slot, int func)
>  	return gmch_ctrl << 25; /* 32 MB units */
>  }
>  
> +static size_t __init chv_stolen_size(int num, int slot, int func)
> +{
> +	u16 gmch_ctrl;
> +
> +	gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
> +	gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
> +	gmch_ctrl &= SNB_GMCH_GMS_MASK;
> +
> +	/*
> +	 * 0x0  to 0x10: 32MB increments starting at 0MB
> +	 * 0x11 to 0x16: 4MB increments starting at 8MB
> +	 * 0x17 to 0x1d: 4MB increments start at 36MB
> +	 */
> +	if (gmch_ctrl < 0x11)
> +		return gmch_ctrl << 25;
> +	else if (gmch_ctrl < 0x17)
> +		return (gmch_ctrl - 0x11 + 2) << 22;
> +	else
> +		return (gmch_ctrl - 0x17 + 9) << 22;
> +}
> +
>  typedef size_t (*stolen_size_fn)(int num, int slot, int func);
>  
>  static struct pci_device_id intel_stolen_ids[] __initdata = {
> @@ -348,7 +369,7 @@ static struct pci_device_id intel_stolen_ids[] __initdata = {
>  	INTEL_HSW_M_IDS(gen6_stolen_size),
>  	INTEL_BDW_M_IDS(gen8_stolen_size),
>  	INTEL_BDW_D_IDS(gen8_stolen_size),
> -	INTEL_CHV_PCI_IDS(gen8_stolen_size)
> +	INTEL_CHV_PCI_IDS(chv_stolen_size),
>  };
>  
>  static void __init intel_graphics_stolen(int num, int slot, int func)
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index ba51901..97f52fc 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1757,6 +1757,17 @@ static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
>  	return bdw_gmch_ctl << 20;
>  }
>  
> +static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
> +{
> +	gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
> +	gmch_ctrl &= SNB_GMCH_GGMS_MASK;
> +
> +	if (gmch_ctrl)
> +		return 1 << (20 + gmch_ctrl);
> +
> +	return 0;
> +}
> +
>  static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
>  {
>  	snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
> @@ -1771,6 +1782,24 @@ static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
>  	return bdw_gmch_ctl << 25; /* 32 MB units */
>  }
>  
> +static size_t chv_get_stolen_size(u16 gmch_ctrl)
> +{
> +	gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
> +	gmch_ctrl &= SNB_GMCH_GMS_MASK;
> +
> +	/*
> +	 * 0x0  to 0x10: 32MB increments starting at 0MB
> +	 * 0x11 to 0x16: 4MB increments starting at 8MB
> +	 * 0x17 to 0x1d: 4MB increments start at 36MB
> +	 */
> +	if (gmch_ctrl < 0x11)
> +		return gmch_ctrl << 25;
> +	else if (gmch_ctrl < 0x17)
> +		return (gmch_ctrl - 0x11 + 2) << 22;
> +	else
> +		return (gmch_ctrl - 0x17 + 9) << 22;
> +}
> +
>  static int ggtt_probe_common(struct drm_device *dev,
>  			     size_t gtt_size)
>  {
> @@ -1867,9 +1896,14 @@ static int gen8_gmch_probe(struct drm_device *dev,
>  
>  	pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
>  
> -	*stolen = gen8_get_stolen_size(snb_gmch_ctl);
> +	if (IS_CHERRYVIEW(dev)) {
> +		*stolen = chv_get_stolen_size(snb_gmch_ctl);
> +		gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
> +	} else {
> +		*stolen = gen8_get_stolen_size(snb_gmch_ctl);
> +		gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
> +	}
>  
> -	gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
>  	*gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
>  
>  	if (IS_CHERRYVIEW(dev))
> -- 
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
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Re: [PATCH v9 10/71] drm/i915/chv: Preliminary interrupt support for Cherryview

[Jani Nikula]

On Wed, 09 Apr 2014, ville.syrjala@linux.intel.com wrote:
> From: Daniel Vetter <daniel.vetter@ffwll.ch>
>
> CHV has the Gen8 master interrupt register, as well as Gen8
> GT/PCU interrupt registers.
>
> The display block is based on VLV, with the main difference
> of adding pipe C.
>
> FIXME: Lot of this is copy pasted from either VLV or BDW. We should
> probably refactor a bit to share the code better.
>
> v2: Rewrite the order of operations to make more sense
>     Don't bail out if MASTER_CTL register doesn't show an interrupt,
>     as display interrupts aren't reported there.
>
> v3: Rebase on top of Egbert Eich's hpd irq handling rework by using
> the relevant port hotplug logic like for vlv.
>
> v4: Rebase on top of Ben's gt irq #define refactoring.
>
> v5: Squash in gen8_gt_irq_handler refactoring from Zhao Yakui
> <yakui.zhao@intel.com>
>
> v6: Adapt to upstream changes, dev_priv->irq_received is gone.
>
> v7: Enable 3 the commented-out 3 pipe support.
>
> v8: Rebase on top of Paulo's irq setup rework, use the renamed macros from
> upstream.
>
> v9: Grab irq_lock around i915_enable_pipestat()
>
> FIXME: There's probably some potential for more shared code between bdw and chv.
>

I did not spot anything out of the ordinary here (one irrelevant nitpick
inline) but frankly I don't have huge confidence in me catching all the
details either. With that disclaimer,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v2)
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 225 +++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 224 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 7a4d3ae..475089e 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1705,6 +1705,95 @@ out:
>  	return ret;
>  }
>  
> +static irqreturn_t cherryview_irq_handler(int irq, void *arg)
> +{
> +	struct drm_device *dev = (struct drm_device *) arg;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 master_ctl, iir;
> +	irqreturn_t ret = IRQ_NONE;
> +	unsigned int pipes = 0;
> +
> +	master_ctl = I915_READ(GEN8_MASTER_IRQ);
> +
> +	I915_WRITE(GEN8_MASTER_IRQ, 0);
> +
> +	ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
> +
> +	iir = I915_READ(VLV_IIR);
> +
> +	if (iir & (I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT))
> +		pipes |= 1 << 0;
> +	if (iir & (I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT))
> +		pipes |= 1 << 1;
> +	if (iir & (I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT | I915_DISPLAY_PIPE_C_EVENT_INTERRUPT))
> +		pipes |= 1 << 2;
> +
> +	if (pipes) {
> +		u32 pipe_stats[I915_MAX_PIPES] = {};
> +		unsigned long irqflags;
> +		int pipe;
> +
> +		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> +		for_each_pipe(pipe) {
> +			unsigned int reg;
> +
> +			if (!(pipes & (1 << pipe)))
> +				continue;
> +
> +			reg = PIPESTAT(pipe);
> +			pipe_stats[pipe] = I915_READ(reg);
> +
> +			/*
> +			 * Clear the PIPE*STAT regs before the IIR
> +			 */
> +			if (pipe_stats[pipe] & 0x8000ffff) {
> +				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
> +					DRM_DEBUG_DRIVER("pipe %c underrun\n",
> +							 pipe_name(pipe));
> +				I915_WRITE(reg, pipe_stats[pipe]);
> +			}
> +		}
> +		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> +
> +		for_each_pipe(pipe) {
> +			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
> +				drm_handle_vblank(dev, pipe);
> +
> +			if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
> +				intel_prepare_page_flip(dev, pipe);
> +				intel_finish_page_flip(dev, pipe);
> +			}
> +		}
> +
> +		if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
> +			gmbus_irq_handler(dev);
> +
> +		ret = IRQ_HANDLED;
> +	}
> +
> +	/* Consume port.  Then clear IIR or we'll miss events */
> +	if (iir & I915_DISPLAY_PORT_INTERRUPT) {
> +		u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
> +
> +		I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
> +
> +		DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
> +				 hotplug_status);
> +		if (hotplug_status & HOTPLUG_INT_STATUS_I915)
> +			queue_work(dev_priv->wq,
> +				   &dev_priv->hotplug_work);
> +
> +		ret = IRQ_HANDLED;
> +	}
> +
> +	I915_WRITE(VLV_IIR, iir);
> +
> +	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
> +	POSTING_READ(GEN8_MASTER_IRQ);
> +
> +	return ret;
> +}
> +
>  static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -2967,6 +3056,37 @@ static void gen8_irq_preinstall(struct drm_device *dev)
>  	gen8_irq_reset(dev);
>  }
>  
> +static void cherryview_irq_preinstall(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;

Unnecessary cast.

> +	int pipe;
> +
> +	I915_WRITE(GEN8_MASTER_IRQ, 0);
> +	POSTING_READ(GEN8_MASTER_IRQ);
> +
> +	GEN8_IRQ_RESET_NDX(GT, 0);
> +	GEN8_IRQ_RESET_NDX(GT, 1);
> +	GEN8_IRQ_RESET_NDX(GT, 2);
> +	GEN8_IRQ_RESET_NDX(GT, 3);
> +
> +	GEN5_IRQ_RESET(GEN8_PCU_);
> +
> +	POSTING_READ(GEN8_PCU_IIR);
> +
> +	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
> +
> +	I915_WRITE(PORT_HOTPLUG_EN, 0);
> +	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
> +
> +	for_each_pipe(pipe)
> +		I915_WRITE(PIPESTAT(pipe), 0xffff);
> +
> +	I915_WRITE(VLV_IMR, 0xffffffff);
> +	I915_WRITE(VLV_IER, 0x0);
> +	I915_WRITE(VLV_IIR, 0xffffffff);
> +	POSTING_READ(VLV_IIR);
> +}
> +
>  static void ibx_hpd_irq_setup(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -3284,6 +3404,50 @@ static int gen8_irq_postinstall(struct drm_device *dev)
>  	return 0;
>  }
>  
> +static int cherryview_irq_postinstall(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
> +		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
> +		I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
> +		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
> +		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT |
> +		I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
> +		I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT;
> +	u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
> +	unsigned long irqflags;
> +	int pipe;
> +
> +	/*
> +	 * Leave vblank interrupts masked initially.  enable/disable will
> +	 * toggle them based on usage.
> +	 */
> +	dev_priv->irq_mask = ~enable_mask |
> +		I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
> +		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT |
> +		I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT;
> +
> +	for_each_pipe(pipe)
> +		I915_WRITE(PIPESTAT(pipe), 0xffff);
> +
> +	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> +	i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
> +	for_each_pipe(pipe)
> +		i915_enable_pipestat(dev_priv, pipe, pipestat_enable);
> +	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> +
> +	I915_WRITE(VLV_IIR, 0xffffffff);
> +	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
> +	I915_WRITE(VLV_IER, enable_mask);
> +
> +	gen8_gt_irq_postinstall(dev_priv);
> +
> +	I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
> +	POSTING_READ(GEN8_MASTER_IRQ);
> +
> +	return 0;
> +}
> +
>  static void gen8_irq_uninstall(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -3327,6 +3491,57 @@ static void valleyview_irq_uninstall(struct drm_device *dev)
>  	POSTING_READ(VLV_IER);
>  }
>  
> +static void cherryview_irq_uninstall(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int pipe;
> +
> +	if (!dev_priv)
> +		return;
> +
> +	I915_WRITE(GEN8_MASTER_IRQ, 0);
> +	POSTING_READ(GEN8_MASTER_IRQ);
> +
> +#define GEN8_IRQ_FINI_NDX(type, which)				\
> +do {								\
> +	I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff);	\
> +	I915_WRITE(GEN8_##type##_IER(which), 0);		\
> +	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff);	\
> +	POSTING_READ(GEN8_##type##_IIR(which));			\
> +	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff);	\
> +} while (0)
> +
> +#define GEN8_IRQ_FINI(type)				\
> +do {							\
> +	I915_WRITE(GEN8_##type##_IMR, 0xffffffff);	\
> +	I915_WRITE(GEN8_##type##_IER, 0);		\
> +	I915_WRITE(GEN8_##type##_IIR, 0xffffffff);	\
> +	POSTING_READ(GEN8_##type##_IIR);		\
> +	I915_WRITE(GEN8_##type##_IIR, 0xffffffff);	\
> +} while (0)
> +
> +	GEN8_IRQ_FINI_NDX(GT, 0);
> +	GEN8_IRQ_FINI_NDX(GT, 1);
> +	GEN8_IRQ_FINI_NDX(GT, 2);
> +	GEN8_IRQ_FINI_NDX(GT, 3);
> +
> +	GEN8_IRQ_FINI(PCU);
> +
> +#undef GEN8_IRQ_FINI
> +#undef GEN8_IRQ_FINI_NDX
> +
> +	I915_WRITE(PORT_HOTPLUG_EN, 0);
> +	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
> +
> +	for_each_pipe(pipe)
> +		I915_WRITE(PIPESTAT(pipe), 0xffff);
> +
> +	I915_WRITE(VLV_IMR, 0xffffffff);
> +	I915_WRITE(VLV_IER, 0x0);
> +	I915_WRITE(VLV_IIR, 0xffffffff);
> +	POSTING_READ(VLV_IIR);
> +}
> +
>  static void ironlake_irq_uninstall(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -4032,7 +4247,15 @@ void intel_irq_init(struct drm_device *dev)
>  		dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
>  	}
>  
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_CHERRYVIEW(dev)) {
> +		dev->driver->irq_handler = cherryview_irq_handler;
> +		dev->driver->irq_preinstall = cherryview_irq_preinstall;
> +		dev->driver->irq_postinstall = cherryview_irq_postinstall;
> +		dev->driver->irq_uninstall = cherryview_irq_uninstall;
> +		dev->driver->enable_vblank = valleyview_enable_vblank;
> +		dev->driver->disable_vblank = valleyview_disable_vblank;
> +		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
> +	} else if (IS_VALLEYVIEW(dev)) {
>  		dev->driver->irq_handler = valleyview_irq_handler;
>  		dev->driver->irq_preinstall = valleyview_irq_preinstall;
>  		dev->driver->irq_postinstall = valleyview_irq_postinstall;
> -- 
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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[PATCH v5 34.1/71] drm/i915/chv: Implement stolen memory size detection

[ville.syrjala]

From: Damien Lespiau <damien.lespiau@intel.com>

CHV uses the same bits as SNB/VLV to code the Graphics Mode Select field
(GFX stolen memory size) with the addition of finer granularity modes:
4MB increments from 0x11 (8MB) to 0x1d.

Values strictly above 0x1d are either reserved or not supported.

v2: 4MB increments, not 8MB. 32MB has been omitted from the list of new
    values (Ville Syrjälä)

v3: Also correctly interpret GGMS (GTT Graphics Memory Size) (Ville
    Syrjälä)

v4: Don't assign a value that needs 20bits or more to a u16 (Rafael
    Barbalho)

[vsyrjala: v5: Split the early quirks to another patch]

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>
Tested-by: Rafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 38 +++++++++++++++++++++++++++++++++++--
 1 file changed, 36 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 72b1bf8..afd4eef 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1776,6 +1776,17 @@ static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
 	return bdw_gmch_ctl << 20;
 }
 
+static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
+{
+	gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
+	gmch_ctrl &= SNB_GMCH_GGMS_MASK;
+
+	if (gmch_ctrl)
+		return 1 << (20 + gmch_ctrl);
+
+	return 0;
+}
+
 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
 {
 	snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
@@ -1790,6 +1801,24 @@ static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
 	return bdw_gmch_ctl << 25; /* 32 MB units */
 }
 
+static size_t chv_get_stolen_size(u16 gmch_ctrl)
+{
+	gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
+	gmch_ctrl &= SNB_GMCH_GMS_MASK;
+
+	/*
+	 * 0x0  to 0x10: 32MB increments starting at 0MB
+	 * 0x11 to 0x16: 4MB increments starting at 8MB
+	 * 0x17 to 0x1d: 4MB increments start at 36MB
+	 */
+	if (gmch_ctrl < 0x11)
+		return gmch_ctrl << 25;
+	else if (gmch_ctrl < 0x17)
+		return (gmch_ctrl - 0x11 + 2) << 22;
+	else
+		return (gmch_ctrl - 0x17 + 9) << 22;
+}
+
 static int ggtt_probe_common(struct drm_device *dev,
 			     size_t gtt_size)
 {
@@ -1886,9 +1915,14 @@ static int gen8_gmch_probe(struct drm_device *dev,
 
 	pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 
-	*stolen = gen8_get_stolen_size(snb_gmch_ctl);
+	if (IS_CHERRYVIEW(dev)) {
+		*stolen = chv_get_stolen_size(snb_gmch_ctl);
+		gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
+	} else {
+		*stolen = gen8_get_stolen_size(snb_gmch_ctl);
+		gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
+	}
 
-	gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
 	*gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
 
 	if (IS_CHERRYVIEW(dev))
-- 
1.8.3.2

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[PATCH v5 34.2/71] x86/gpu: Implement stolen memory size early quirk for CHV

[ville.syrjala]

From: Damien Lespiau <damien.lespiau@intel.com>

CHV uses the same bits as SNB/VLV to code the Graphics Mode Select field
(GFX stolen memory size) with the addition of finer granularity modes:
4MB increments from 0x11 (8MB) to 0x1d.

Values strictly above 0x1d are either reserved or not supported.

v2: 4MB increments, not 8MB. 32MB has been omitted from the list of new
    values (Ville Syrjälä)

v3: Also correctly interpret GGMS (GTT Graphics Memory Size) (Ville
    Syrjälä)

v4: Don't assign a value that needs 20bits or more to a u16 (Rafael
    Barbalho)

[vsyrjala: v5: Split from i915 changes and add chv_stolen_funcs]

Cc: Ingo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>
Tested-by: Rafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---

Note to x86 folks: This depends on INTEL_CHV_IDS() which is part of some
other i915 patch, so I think it would be easiest to merge this through
Daniel's tree.

 arch/x86/kernel/early-quirks.c | 28 +++++++++++++++++++++++++++-
 1 file changed, 27 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 6e2537c..8323575 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -428,6 +428,26 @@ static size_t gen8_stolen_size(int num, int slot, int func)
 	return gmch_ctrl << 25; /* 32 MB units */
 }
 
+static size_t __init chv_stolen_size(int num, int slot, int func)
+{
+	u16 gmch_ctrl;
+
+	gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
+	gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
+	gmch_ctrl &= SNB_GMCH_GMS_MASK;
+
+	/*
+	 * 0x0  to 0x10: 32MB increments starting at 0MB
+	 * 0x11 to 0x16: 4MB increments starting at 8MB
+	 * 0x17 to 0x1d: 4MB increments start at 36MB
+	 */
+	if (gmch_ctrl < 0x11)
+		return gmch_ctrl << 25;
+	else if (gmch_ctrl < 0x17)
+		return (gmch_ctrl - 0x11 + 2) << 22;
+	else
+		return (gmch_ctrl - 0x17 + 9) << 22;
+}
 
 struct intel_stolen_funcs {
 	size_t (*size)(int num, int slot, int func);
@@ -469,6 +489,11 @@ static const struct intel_stolen_funcs gen8_stolen_funcs = {
 	.size = gen8_stolen_size,
 };
 
+static const struct intel_stolen_funcs chv_stolen_funcs = {
+	.base = intel_stolen_base,
+	.size = chv_stolen_size,
+};
+
 static struct pci_device_id intel_stolen_ids[] __initdata = {
 	INTEL_I830_IDS(&i830_stolen_funcs),
 	INTEL_I845G_IDS(&i845_stolen_funcs),
@@ -495,7 +520,8 @@ static struct pci_device_id intel_stolen_ids[] __initdata = {
 	INTEL_HSW_D_IDS(&gen6_stolen_funcs),
 	INTEL_HSW_M_IDS(&gen6_stolen_funcs),
 	INTEL_BDW_M_IDS(&gen8_stolen_funcs),
-	INTEL_BDW_D_IDS(&gen8_stolen_funcs)
+	INTEL_BDW_D_IDS(&gen8_stolen_funcs),
+	INTEL_CHV_IDS(&chv_stolen_funcs),
 };
 
 static void __init intel_graphics_stolen(int num, int slot, int func)
-- 
1.8.3.2

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[PATCH 34.3/71] x86/gpu: Sprinkle const, __init and __initconst to stolen memory quirks

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

gen8_stolen_size() is missing __init, so add it.

Also all the intel_stolen_funcs structures can be marked
__initconst.

intel_stolen_ids[] can also be made const if we replace the
__initdata with __initconst.

Cc: Ingo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 arch/x86/kernel/early-quirks.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 8323575..f96098f 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -418,7 +418,7 @@ static size_t __init gen6_stolen_size(int num, int slot, int func)
 	return gmch_ctrl << 25; /* 32 MB units */
 }
 
-static size_t gen8_stolen_size(int num, int slot, int func)
+static size_t __init gen8_stolen_size(int num, int slot, int func)
 {
 	u16 gmch_ctrl;
 
@@ -454,47 +454,47 @@ struct intel_stolen_funcs {
 	u32 (*base)(int num, int slot, int func, size_t size);
 };
 
-static const struct intel_stolen_funcs i830_stolen_funcs = {
+static const struct intel_stolen_funcs i830_stolen_funcs __initconst = {
 	.base = i830_stolen_base,
 	.size = i830_stolen_size,
 };
 
-static const struct intel_stolen_funcs i845_stolen_funcs = {
+static const struct intel_stolen_funcs i845_stolen_funcs __initconst = {
 	.base = i845_stolen_base,
 	.size = i830_stolen_size,
 };
 
-static const struct intel_stolen_funcs i85x_stolen_funcs = {
+static const struct intel_stolen_funcs i85x_stolen_funcs __initconst = {
 	.base = i85x_stolen_base,
 	.size = gen3_stolen_size,
 };
 
-static const struct intel_stolen_funcs i865_stolen_funcs = {
+static const struct intel_stolen_funcs i865_stolen_funcs __initconst = {
 	.base = i865_stolen_base,
 	.size = gen3_stolen_size,
 };
 
-static const struct intel_stolen_funcs gen3_stolen_funcs = {
+static const struct intel_stolen_funcs gen3_stolen_funcs __initconst = {
 	.base = intel_stolen_base,
 	.size = gen3_stolen_size,
 };
 
-static const struct intel_stolen_funcs gen6_stolen_funcs = {
+static const struct intel_stolen_funcs gen6_stolen_funcs __initconst = {
 	.base = intel_stolen_base,
 	.size = gen6_stolen_size,
 };
 
-static const struct intel_stolen_funcs gen8_stolen_funcs = {
+static const struct intel_stolen_funcs gen8_stolen_funcs __initconst = {
 	.base = intel_stolen_base,
 	.size = gen8_stolen_size,
 };
 
-static const struct intel_stolen_funcs chv_stolen_funcs = {
+static const struct intel_stolen_funcs chv_stolen_funcs __initconst = {
 	.base = intel_stolen_base,
 	.size = chv_stolen_size,
 };
 
-static struct pci_device_id intel_stolen_ids[] __initdata = {
+static const struct pci_device_id intel_stolen_ids[] __initconst = {
 	INTEL_I830_IDS(&i830_stolen_funcs),
 	INTEL_I845G_IDS(&i845_stolen_funcs),
 	INTEL_I85X_IDS(&i85x_stolen_funcs),
-- 
1.8.3.2

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Re: [PATCH 18/71] drm/i915/chv: Add vlv_pipe_to_channel

[Imre Deak]

[-- Attachment #1.1: Type: text/plain, Size: 1171 bytes --]

On Wed, 2014-04-09 at 13:28 +0300, ville.syrjala@linux.intel.com wrote:
> From: Chon Ming Lee <chon.ming.lee@intel.com>
> 
> Cherryview has 3 pipes.  Some of the pll dpio offset calculation is
> based on pipe number.  Need to use vlv_pipe_to_channel to calculate the
> correct phy channel to use for the pipe.
> 
> Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_drv.h | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 087e471..e572799 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -544,6 +544,20 @@ vlv_dport_to_channel(struct intel_digital_port *dport)
>  	}
>  }
>  
> +static inline int
> +vlv_pipe_to_channel(enum pipe pipe)
> +{
> +	switch (pipe) {
> +	case PIPE_A:
> +	case PIPE_C:
> +		return DPIO_CH0;
> +	case PIPE_B:
> +		return DPIO_CH1;
> +	default:
> +		BUG();
> +	}
> +}
> +
>  static inline struct drm_crtc *
>  intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
>  {


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Re: [PATCH 16/71] drm/i915/chv: Add DPIO offset for Cherryview. v3

[Imre Deak]

[-- Attachment #1.1: Type: text/plain, Size: 2595 bytes --]

On Wed, 2014-04-09 at 13:28 +0300, ville.syrjala@linux.intel.com wrote:
> From: Chon Ming Lee <chon.ming.lee@intel.com>
> 
> CHV has 2 display phys.  First phy (IOSF offset 0x1A) has two channels,
> and second phy (IOSF offset 0x12) has single channel.  The first phy is
> used for port B and port C, while second phy is only for port D.
> 
> v2: Move the pipe to determine which phy to select for
> vlv_dpio_read/vlv_dpio_write to another patch. (Daniel)
> v3: Rebase the code based on rework on how to calculate DPIO offset.
> 
> Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h      |  2 +-
>  drivers/gpu/drm/i915/i915_reg.h      |  1 +
>  drivers/gpu/drm/i915/intel_display.c | 12 +++++++++++-
>  3 files changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4abaa9e..07a162c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -92,7 +92,7 @@ enum port {
>  };
>  #define port_name(p) ((p) + 'A')
>  
> -#define I915_NUM_PHYS_VLV 1
> +#define I915_NUM_PHYS_VLV 2
>  
>  enum dpio_channel {
>  	DPIO_CH0,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c7ec7d6..beb04ab 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -457,6 +457,7 @@
>  #define   IOSF_PORT_PUNIT			0x4
>  #define   IOSF_PORT_NC				0x11
>  #define   IOSF_PORT_DPIO			0x12
> +#define   IOSF_PORT_DPIO_2			0x1a
>  #define   IOSF_PORT_GPIO_NC			0x13
>  #define   IOSF_PORT_CCK				0x14
>  #define   IOSF_PORT_CCU				0xA9
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9a50b64..df6732e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1367,7 +1367,17 @@ static void intel_init_dpio(struct drm_device *dev)
>  	if (!IS_VALLEYVIEW(dev))
>  		return;
>  
> -	DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
> +	/*
> +	 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
> +	 * CHV x1 PHY (DP/HDMI D)
> +	 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
> +	 */
> +	if (IS_CHERRYVIEW(dev)) {
> +		DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
> +		DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
> +	} else {
> +		DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
> +	}
>  }
>  
>  static void intel_reset_dpio(struct drm_device *dev)


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Re: [PATCH 17/71] drm/i915/chv: Update Cherryview DPLL changes to support Port D. v2

[Imre Deak]

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On Wed, 2014-04-09 at 13:28 +0300, ville.syrjala@linux.intel.com wrote:
> From: Chon Ming Lee <chon.ming.lee@intel.com>
> 
> The additional DPLL registers added to support Port D.  Besides, add
> some new PHY control and status registers based on B-spec.
> 
> v2: Based on Ville review
> 	- Corrected DPIO_PHY_STATUS offset and name.
>     - Rebase based on upstream change after introduce enum dpio_phy and
>       enum dpio_channel.
> 
> v3: Rebased on top of Antti's 3-pipe prep patch. Note that the new offsets for
> the DPLL registers aren't in place yet, so this introduces a slight regression.
> But since 3 pipe support isn't fully enabled yet anyaway in -internal this
> shouldn't matter too much.
> 
> Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |  6 ++++++
>  drivers/gpu/drm/i915/intel_display.c | 11 +++++++++--
>  drivers/gpu/drm/i915/intel_drv.h     |  1 +
>  3 files changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index beb04ab..8aea092 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -29,6 +29,8 @@
>  #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
>  
>  #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
> +#define _PIPE3(pipe, a, b, c) (pipe < 2 ? _PIPE(pipe, a, b) : c)
> +#define _PORT3(port, a, b, c) (port < 2 ? _PORT(port, a, b) : c)

These could go to patch 71, where they're first used. Either way:
Reviewed-by: Imre Deak <imre.deak@intel.com>

>  
>  #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
>  #define _MASKED_BIT_DISABLE(a) ((a) << 16)
> @@ -1385,6 +1387,10 @@ enum punit_power_well {
>  #define   DPLL_PORTB_READY_MASK		(0xf)
>  
>  #define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
> +
> +/* Additional CHV pll/phy registers */
> +#define DPIO_PHY_STATUS			(VLV_DISPLAY_BASE + 0x6240)
> +#define   DPLL_PORTD_READY_MASK		(0xf)
>  /*
>   * The i830 generation, in LVDS mode, defines P1 as the bit number set within
>   * this field (only one bit may be set).
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index df6732e..153f244 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1535,21 +1535,28 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
>  		struct intel_digital_port *dport)
>  {
>  	u32 port_mask;
> +	int dpll_reg;
>  
>  	switch (dport->port) {
>  	case PORT_B:
>  		port_mask = DPLL_PORTB_READY_MASK;
> +		dpll_reg = DPLL(0);
>  		break;
>  	case PORT_C:
>  		port_mask = DPLL_PORTC_READY_MASK;
> +		dpll_reg = DPLL(0);
> +		break;
> +	case PORT_D:
> +		port_mask = DPLL_PORTD_READY_MASK;
> +		dpll_reg = DPIO_PHY_STATUS;
>  		break;
>  	default:
>  		BUG();
>  	}
>  
> -	if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
> +	if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
>  		WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
> -		     port_name(dport->port), I915_READ(DPLL(0)));
> +		     port_name(dport->port), I915_READ(dpll_reg));
>  }
>  
>  /**
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 9002e77..087e471 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -535,6 +535,7 @@ vlv_dport_to_channel(struct intel_digital_port *dport)
>  {
>  	switch (dport->port) {
>  	case PORT_B:
> +	case PORT_D:
>  		return DPIO_CH0;
>  	case PORT_C:
>  		return DPIO_CH1;


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Re: [PATCH 14/71] drm/i915/chv: Add early quirk for stolen

[Daniel Vetter]

On Thu, May 08, 2014 at 06:10:45PM +0300, Jani Nikula wrote:
> On Thu, 08 May 2014, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Thu, May 08, 2014 at 05:32:21PM +0300, Jani Nikula wrote:
> >> On Wed, 09 Apr 2014, ville.syrjala@linux.intel.com wrote:
> >> > From: Daniel Vetter <daniel.vetter@ffwll.ch>
> >> >
> >> > Same as on other gen8 devices.
> >> >
> >> > Cc: Ingo Molnar <mingo@kernel.org>
> >> > Cc: H. Peter Anvin <hpa@zytor.com>
> >> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> >> > ---
> >> >  arch/x86/kernel/early-quirks.c | 3 ++-
> >> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >> >
> >> > diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> >> > index bc4a088..5758f5b 100644
> >> > --- a/arch/x86/kernel/early-quirks.c
> >> > +++ b/arch/x86/kernel/early-quirks.c
> >> > @@ -347,7 +347,8 @@ static struct pci_device_id intel_stolen_ids[] __initdata = {
> >> >  	INTEL_HSW_D_IDS(gen6_stolen_size),
> >> >  	INTEL_HSW_M_IDS(gen6_stolen_size),
> >> >  	INTEL_BDW_M_IDS(gen8_stolen_size),
> >> > -	INTEL_BDW_D_IDS(gen8_stolen_size)
> >> > +	INTEL_BDW_D_IDS(gen8_stolen_size),
> >> > +	INTEL_CHV_PCI_IDS(gen8_stolen_size)
> >> 
> >> Needs refresh after the update to the #define.
> >
> > This patch is actually wrong. We need CHV specific stolen size detection
> > here. And in fact we get it as part of patch 34/71. I'll go and split
> > that up into i915 and x86 specific parts and pretend that this patch
> > never existed.
> 
> Right, I'm actually looking at 34 now.

Ok, I'll ignore this one here.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 19/71] drm/i915/chv: Trigger phy common lane reset

[Daniel Vetter]

On Mon, Apr 28, 2014 at 05:54:24PM +0300, Imre Deak wrote:
> On Wed, 2014-04-09 at 13:28 +0300, ville.syrjala@linux.intel.com wrote:
> > From: Chon Ming Lee <chon.ming.lee@intel.com>
> > 
> > During cold boot, the display controller needs to deassert the common
> > lane reset.  Only do it once during intel_init_dpio for both PHYx2 and
> > PHYx1.
> > 
> > Besides, assert the common lane reset when disable pll.  This still
> > to be determined whether need to do it by driver.
> > 
> > Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
> > [vsyrjala: Don't disable DPIO PLL when using DSI]
> > [vsyrjala: Don't call vlv_disable_pll() by accident on CHV]
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h      |  8 +++++
> >  drivers/gpu/drm/i915/intel_display.c | 66 ++++++++++++++++++++++++++++--------
> >  2 files changed, 59 insertions(+), 15 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 8aea092..8fcf4ea 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1391,6 +1391,14 @@ enum punit_power_well {
> >  /* Additional CHV pll/phy registers */
> >  #define DPIO_PHY_STATUS			(VLV_DISPLAY_BASE + 0x6240)
> >  #define   DPLL_PORTD_READY_MASK		(0xf)
> > +#define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)
> > +#define   PHY_COM_LANE_RESET_DEASSERT(phy, val) \
> > +				((phy == DPIO_PHY0) ? (val | 1) : (val | 2))
> > +#define   PHY_COM_LANE_RESET_ASSERT(phy, val) \
> > +				((phy == DPIO_PHY0) ? (val & ~1) : (val & ~2))
> > +#define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104)
> > +#define   PHY_POWERGOOD(phy)	((phy == DPIO_PHY0) ? (1<<31) : (1<<30))
> > +
> >  /*
> >   * The i830 generation, in LVDS mode, defines P1 as the bit number set within
> >   * this field (only one bit may be set).
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 153f244..e33667d 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1395,17 +1395,36 @@ static void intel_reset_dpio(struct drm_device *dev)
> >  		   DPLL_REFA_CLK_ENABLE_VLV |
> >  		   DPLL_INTEGRATED_CRI_CLK_VLV);
> >  
> > -	/*
> > -	 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
> > -	 *  6.	De-assert cmn_reset/side_reset. Same as VLV X0.
> > -	 *   a.	GUnit 0x2110 bit[0] set to 1 (def 0)
> > -	 *   b.	The other bits such as sfr settings / modesel may all be set
> > -	 *      to 0.
> 
> This is VLV specific, so ok to be moved,
> 
> > -	 *
> > -	 * This should only be done on init and resume from S3 with both
> > -	 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
> > -	 */
> 
> but this is also true for CHV, so should stay.

I've copypasted this block to the chv comment while merging.
-Daniel

> 
> > -	I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
> > +	if (IS_CHERRYVIEW(dev)) {
> > +		enum dpio_phy phy;
> > +		u32 val;
> > +
> > +		for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
> > +			/* Poll for phypwrgood signal */
> > +			if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
> > +						PHY_POWERGOOD(phy), 1))
> > +				DRM_ERROR("Display PHY %d is not power up\n", phy);
> > +
> > +			/* Deassert common lane reset for PHY*/
> > +			val = I915_READ(DISPLAY_PHY_CONTROL);
> > +			I915_WRITE(DISPLAY_PHY_CONTROL,
> > +				PHY_COM_LANE_RESET_DEASSERT(phy, val));
> 
> Would be clearer not to hide the 'or' in the macro and let
> PHY_COM_LANE_RESET_DEASSERT be just the flag itself and do here
> I915_WRITE(DISPLAY_PHY_CONTROL, val | PHY_COM_LANE_RESET_DEASSERT(phy));
> 
> The above issues are minor, so even without fixing them this patch is
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> > +		}
> > +
> > +	} else {
> > +		/*
> > +		 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
> > +		 *  6.	De-assert cmn_reset/side_reset. Same as VLV X0.
> > +		 *   a.	GUnit 0x2110 bit[0] set to 1 (def 0)
> > +		 *   b.	The other bits such as sfr settings / modesel may all
> > +		 *	be set to 0.
> > +		 *
> > +		 * This should only be done on init and resume from S3 with
> > +		 * both PLLs disabled, or we risk losing DPIO and PLL
> > +		 * synchronization.
> > +		 */
> > +		I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
> > +	}
> >  }
> >  
> >  static void vlv_enable_pll(struct intel_crtc *crtc)
> > @@ -1529,6 +1548,19 @@ static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
> >  		val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
> >  	I915_WRITE(DPLL(pipe), val);
> >  	POSTING_READ(DPLL(pipe));
> > +
> > +}
> > +
> > +static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
> > +{
> > +	int dpll = DPLL(pipe);
> > +	u32 val;
> > +
> > +	/* Set PLL en = 0 */
> > +	val = I915_READ(dpll);
> > +	val &= ~DPLL_VCO_ENABLE;
> > +	I915_WRITE(dpll, val);
> > +
> >  }
> >  
> >  void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
> > @@ -4511,10 +4543,14 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
> >  		if (encoder->post_disable)
> >  			encoder->post_disable(encoder);
> >  
> > -	if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
> > -		vlv_disable_pll(dev_priv, pipe);
> > -	else if (!IS_VALLEYVIEW(dev))
> > -		i9xx_disable_pll(dev_priv, pipe);
> > +	if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
> > +		if (IS_CHERRYVIEW(dev))
> > +			chv_disable_pll(dev_priv, pipe);
> > +		else if (IS_VALLEYVIEW(dev))
> > +			vlv_disable_pll(dev_priv, pipe);
> > +		else
> > +			i9xx_disable_pll(dev_priv, pipe);
> > +	}
> >  
> >  	intel_crtc->active = false;
> >  	intel_update_watermarks(crtc);
> 



> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx


-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 22/71] drm/i915/chv: Add phy supports for Cherryview

[Daniel Vetter]

On Wed, Apr 30, 2014 at 03:13:53PM +0300, Imre Deak wrote:
> On Wed, 2014-04-09 at 13:28 +0300, ville.syrjala@linux.intel.com wrote:
> > From: Chon Ming Lee <chon.ming.lee@intel.com>
> > 
> > Added programming phy layer for CHV based on "Application note for 1273
> > CHV Display phy".
> > 
> > v2: Rebase the code and do some cleanup.
> > v3: Rework based on Ville review.
> >     -Fix the macro where the ch info need to swap, and add parens to ?
> > 	 operator.
> > 	-Fix wrong bit define for DPIO_PCS_SWING_CALC_0 and
> > 	 DPIO_PCS_SWING_CALC_1 and rename for meaningful.
> >     -Add some comments for CHV specific DPIO registers.
> >     -Change the dp margin registery value to decimal to align with the
> > 	 doc.
> > 	-Fix the not clearing some value in vlv_dpio_read before write again.
> >     -Create new hdmi/dp encoder function for chv instead of share with
> > 	valleyview.
> > v4: Rebase the code after rename the DPIO registers define and upstream
> > 	change.
> >     Based on Ville review.
> >     -For unique transition scale selection, after Ville point out, look
> > 	 like the doc might wrong for the bit 26.  Use bit 27 for ch0 and
> > 	 ch1.
> > 	-Break up some dpio write value into two/three steps for readability.
> > 	-Remove unrelated change.
> >     -Add some shift define for some registers instead just give the hex
> > 	value.
> >     -Fix a bug where write to wrong VLV_TX_DW3.
> > v5: Based on Ville review.
> > 	- Move tx lane latency optimal setting from chv_dp_pre_pll_enable to
> > 	  chv_pre_enable_dp, and chv_hdmi_pre_pll_enable to
> > 	  chv_hdmi_pre_enable respectively.
> >  	- Fix typo in one margin_reg_value for DP_TRAIN_VOLTAGE_SWING_400.
> > 	- Clear DPIO_TX_UNIQ_TRANS_SCALE_EN for DP and HDMI.
> > 	- Mask the old deemph and swing bits for hdmi.
> > v6: Remove stub for pre_pll_enable for dp and hdmi.
> > 
> > Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > [vsyrjala: Don't touch panel power sequencing on DP]
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Looks ok, so:
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> Some nitpicks follow, fixing them is optional.

Ok I've merged this, but I think the nitpicks are valid. Ville, can you
please throw a quick follow-up patch on top to address these?

Thanks, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 25/71] drm/i915/chv: CHV doesn't have CRT output

[Daniel Vetter]

On Thu, Apr 10, 2014 at 08:56:46PM +0300, Jani Nikula wrote:
> On Wed, 09 Apr 2014, Daniel Vetter <daniel@ffwll.ch> wrote:
> > On Wed, Apr 09, 2014 at 01:28:23PM +0300, ville.syrjala@linux.intel.com wrote:
> >> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> 
> >> No CRT output on CHV, so don't call intel_crt_init().
> >> 
> >> v2: Don't disable CRT on HAS.
> >> 
> >> FIXME: Split out the is_simulator check again, we need it for now to keep HAS
> >> going.
> >
> > Fixme can be dropped, this is something I need to sort out when rebasing
> > internal.
> 
> FWIW, with that fixed,
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Ok, merged up to this patch here for now.
-Daniel
> 
> 
> 
> > -Daniel
> >
> >> 
> >> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1)
> >> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> >> ---
> >>  drivers/gpu/drm/i915/intel_display.c | 2 +-
> >>  1 file changed, 1 insertion(+), 1 deletion(-)
> >> 
> >> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> >> index 266d8fe..9b65a04 100644
> >> --- a/drivers/gpu/drm/i915/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/intel_display.c
> >> @@ -10989,7 +10989,7 @@ static void intel_setup_outputs(struct drm_device *dev)
> >>  
> >>  	intel_lvds_init(dev);
> >>  
> >> -	if (!IS_ULT(dev))
> >> +	if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev))
> >>  		intel_crt_init(dev);
> >>  
> >>  	if (HAS_DDI(dev)) {
> >> -- 
> >> 1.8.3.2
> >> 
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > -- 
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > +41 (0) 79 365 57 48 - http://blog.ffwll.ch
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 24/71] drm/i915/chv: Add DPLL state readout support

[Daniel Vetter]

On Wed, Apr 30, 2014 at 04:11:27PM +0300, Imre Deak wrote:
> On Wed, 2014-04-09 at 13:28 +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Add chv_crtc_clock_get() to read out the DPLL settings.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 34 +++++++++++++++++++++++++++++++++-
> >  1 file changed, 33 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index f849c65..266d8fe 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -6062,6 +6062,36 @@ static void i9xx_get_plane_config(struct intel_crtc *crtc,
> >  
> >  }
> >  
> > +static void chv_crtc_clock_get(struct intel_crtc *crtc,
> > +			       struct intel_crtc_config *pipe_config)
> > +{
> > +	struct drm_device *dev = crtc->base.dev;
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	int pipe = pipe_config->cpu_transcoder;
> > +	enum dpio_channel port = vlv_pipe_to_channel(pipe);
> 
> 'ch' would be clearer.
> 
> > +	intel_clock_t clock;
> > +	u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
> > +	int refclk = 100000;
> > +
> > +	mutex_lock(&dev_priv->dpio_lock);
> > +	cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
> > +	pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
> > +	pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
> > +	pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
> > +	mutex_unlock(&dev_priv->dpio_lock);
> > +
> > +	clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
> > +	clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
> > +	clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
> > +	clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_SHIFT) & 0x7;
> > +	clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_SHIFT) & 0x1f;

These changed to P._DIV_SHIFT due to a bikeshed in an earlier patch. Fixed
while merging.
-Daniel

> 
> We could throw in a check here for the rest of the dividers that we
> assume fixed (S1, K, div_by2, div_by4).
> 
> With or without the above changes:
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> > +
> > +	chv_clock(refclk, &clock);
> > +
> > +	/* clock.dot is the fast clock */
> > +	pipe_config->port_clock = clock.dot / 5;
> > +}
> > +
> >  static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> >  				 struct intel_crtc_config *pipe_config)
> >  {
> > @@ -6131,7 +6161,9 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> >  						     DPLL_PORTB_READY_MASK);
> >  	}
> >  
> > -	if (IS_VALLEYVIEW(dev))
> > +	if (IS_CHERRYVIEW(dev))
> > +		chv_crtc_clock_get(crtc, pipe_config);
> > +	else if (IS_VALLEYVIEW(dev))
> >  		vlv_crtc_clock_get(crtc, pipe_config);
> >  	else
> >  		i9xx_crtc_clock_get(crtc, pipe_config);
> 



> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx


-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 34.3/71] x86/gpu: Sprinkle const, __init and __initconst to stolen memory quirks

[Daniel Vetter]

On Thu, May 08, 2014 at 10:19:42PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> gen8_stolen_size() is missing __init, so add it.
> 
> Also all the intel_stolen_funcs structures can be marked
> __initconst.
> 
> intel_stolen_ids[] can also be made const if we replace the
> __initdata with __initconst.
> 
> Cc: Ingo Molnar <mingo@kernel.org>
> Cc: H. Peter Anvin <hpa@zytor.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

All three patches in the chv stolen reservation series merged to
drm-intel-next queue, thanks.
-Daniel

> ---
>  arch/x86/kernel/early-quirks.c | 20 ++++++++++----------
>  1 file changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index 8323575..f96098f 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -418,7 +418,7 @@ static size_t __init gen6_stolen_size(int num, int slot, int func)
>  	return gmch_ctrl << 25; /* 32 MB units */
>  }
>  
> -static size_t gen8_stolen_size(int num, int slot, int func)
> +static size_t __init gen8_stolen_size(int num, int slot, int func)
>  {
>  	u16 gmch_ctrl;
>  
> @@ -454,47 +454,47 @@ struct intel_stolen_funcs {
>  	u32 (*base)(int num, int slot, int func, size_t size);
>  };
>  
> -static const struct intel_stolen_funcs i830_stolen_funcs = {
> +static const struct intel_stolen_funcs i830_stolen_funcs __initconst = {
>  	.base = i830_stolen_base,
>  	.size = i830_stolen_size,
>  };
>  
> -static const struct intel_stolen_funcs i845_stolen_funcs = {
> +static const struct intel_stolen_funcs i845_stolen_funcs __initconst = {
>  	.base = i845_stolen_base,
>  	.size = i830_stolen_size,
>  };
>  
> -static const struct intel_stolen_funcs i85x_stolen_funcs = {
> +static const struct intel_stolen_funcs i85x_stolen_funcs __initconst = {
>  	.base = i85x_stolen_base,
>  	.size = gen3_stolen_size,
>  };
>  
> -static const struct intel_stolen_funcs i865_stolen_funcs = {
> +static const struct intel_stolen_funcs i865_stolen_funcs __initconst = {
>  	.base = i865_stolen_base,
>  	.size = gen3_stolen_size,
>  };
>  
> -static const struct intel_stolen_funcs gen3_stolen_funcs = {
> +static const struct intel_stolen_funcs gen3_stolen_funcs __initconst = {
>  	.base = intel_stolen_base,
>  	.size = gen3_stolen_size,
>  };
>  
> -static const struct intel_stolen_funcs gen6_stolen_funcs = {
> +static const struct intel_stolen_funcs gen6_stolen_funcs __initconst = {
>  	.base = intel_stolen_base,
>  	.size = gen6_stolen_size,
>  };
>  
> -static const struct intel_stolen_funcs gen8_stolen_funcs = {
> +static const struct intel_stolen_funcs gen8_stolen_funcs __initconst = {
>  	.base = intel_stolen_base,
>  	.size = gen8_stolen_size,
>  };
>  
> -static const struct intel_stolen_funcs chv_stolen_funcs = {
> +static const struct intel_stolen_funcs chv_stolen_funcs __initconst = {
>  	.base = intel_stolen_base,
>  	.size = chv_stolen_size,
>  };
>  
> -static struct pci_device_id intel_stolen_ids[] __initdata = {
> +static const struct pci_device_id intel_stolen_ids[] __initconst = {
>  	INTEL_I830_IDS(&i830_stolen_funcs),
>  	INTEL_I845G_IDS(&i845_stolen_funcs),
>  	INTEL_I85X_IDS(&i85x_stolen_funcs),
> -- 
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 42/71] drm/i915/chv: Implement WaDisableSamplerPowerBypass for CHV

[Daniel Vetter]

On Mon, Apr 28, 2014 at 07:19:50PM -0300, Paulo Zanoni wrote:
> 2014-04-28 5:23 GMT-03:00 Ville Syrjälä <ville.syrjala@linux.intel.com>:
> > On Fri, Apr 25, 2014 at 05:55:38PM -0300, Paulo Zanoni wrote:
> >> 2014-04-09 7:28 GMT-03:00  <ville.syrjala@linux.intel.com>:
> >> > From: Rafael Barbalho <rafael.barbalho@intel.com>
> >> >
> >> > Cherryview also needs this WA.
> >>
> >> At least on the chv_rebase tree, this WA is implemented for BDW but it
> >> is not documented as pre-prod only, and its name is not there. We
> >> should probably add a comment documenting the name and the fact that
> >> it is also pre-prod on BDW.
> >
> > IIRC BDW will need it even on production steppings.
> 
> Hmmm the register documentation says one thing while the WA lists say
> others... I'll let you discover which one is correct :)
> 
> >
> > I think I have a patch somewhere that add the w/a note for BDW, but I guess
> > I didn't post it yet.
> >
> >>
> >>
> >> >
> >> > Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
> >> > [vsyrjala: Looks like it's for pre-prodution hw only]
> >> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> > ---
> >> >  drivers/gpu/drm/i915/intel_pm.c | 4 ++++
> >> >  1 file changed, 4 insertions(+)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >> > index 468fe37..60f876c 100644
> >> > --- a/drivers/gpu/drm/i915/intel_pm.c
> >> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> >> > @@ -5405,6 +5405,10 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
> >> >         /* WaDisableSDEUnitClockGating:chv */
> >> >         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> >> >                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> >> > +
> >> > +       /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
> >> > +       I915_WRITE(HALF_SLICE_CHICKEN3,
> >> > +                  _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
> >>
> >> I could not find information anywhere if this is the correct
> >> implementation. Can you please provide me pointers to the doc you
> >> used? The links on Collab seem broken.
> >
> > Just w/a database + bspec are enough for this one.
> 
> Found it :)
> 
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Merged up to this patch (except for the rps patches).
-Daniel

> 
> >
> >>
> >> Thanks,
> >> Paulo
> >>
> >> >  }
> >> >
> >> >  static void g4x_init_clock_gating(struct drm_device *dev)
> >> > --
> >> > 1.8.3.2
> >> >
> >> > _______________________________________________
> >> > Intel-gfx mailing list
> >> > Intel-gfx@lists.freedesktop.org
> >> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >>
> >>
> >>
> >> --
> >> Paulo Zanoni
> >
> > --
> > Ville Syrjälä
> > Intel OTC
> 
> 
> 
> -- 
> Paulo Zanoni
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH v2 49/71] drm/i915/chv: Add CHV display support

[Daniel Vetter]

On Mon, Apr 28, 2014 at 02:00:42PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Rafael Barbalho <rafael.barbalho@intel.com>
> 
> Add support for the third pipe in cherrview
> 
> v2: Don't use spaces for indentation (Jani)
>     Wrap long lines
> 
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
> [vsyrjala: slightly massaged the patch]
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Queued for -next, thanks for the patch.
-Daniel
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 12 ++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h | 11 ++++++++---
>  2 files changed, 20 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 3f57237..0fd3046 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -49,6 +49,17 @@ static struct drm_driver driver;
>  	.dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \
>  	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
>  
> +#define GEN_CHV_PIPEOFFSETS \
> +	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
> +			  CHV_PIPE_C_OFFSET }, \
> +	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
> +			   CHV_TRANSCODER_C_OFFSET, }, \
> +	.dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET, \
> +			  CHV_DPLL_C_OFFSET }, \
> +	.dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET, \
> +			     CHV_DPLL_C_MD_OFFSET }, \
> +	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
> +			     CHV_PALETTE_C_OFFSET }
>  
>  static const struct intel_device_info intel_i830_info = {
>  	.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
> @@ -286,6 +297,7 @@ static const struct intel_device_info intel_cherryview_info = {
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
>  	.is_valleyview = 1,
>  	.display_mmio_offset = VLV_DISPLAY_BASE,
> +	GEN_CHV_PIPEOFFSETS,
>  };
>  
>  /*
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 74ac1c2..9138eff 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1440,6 +1440,7 @@ enum punit_power_well {
>   */
>  #define DPLL_A_OFFSET 0x6014
>  #define DPLL_B_OFFSET 0x6018
> +#define CHV_DPLL_C_OFFSET 0x6030
>  #define DPLL(pipe) (dev_priv->info.dpll_offsets[pipe] + \
>  		    dev_priv->info.display_mmio_offset)
>  
> @@ -1531,6 +1532,7 @@ enum punit_power_well {
>  
>  #define DPLL_A_MD_OFFSET 0x601c /* 965+ only */
>  #define DPLL_B_MD_OFFSET 0x6020 /* 965+ only */
> +#define CHV_DPLL_C_MD_OFFSET 0x603c
>  #define DPLL_MD(pipe) (dev_priv->info.dpll_md_offsets[pipe] + \
>  		       dev_priv->info.display_mmio_offset)
>  
> @@ -1727,6 +1729,7 @@ enum punit_power_well {
>   */
>  #define PALETTE_A_OFFSET 0xa000
>  #define PALETTE_B_OFFSET 0xa800
> +#define CHV_PALETTE_C_OFFSET 0xc000
>  #define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \
>  		       dev_priv->info.display_mmio_offset)
>  
> @@ -2216,6 +2219,7 @@ enum punit_power_well {
>  #define TRANSCODER_A_OFFSET 0x60000
>  #define TRANSCODER_B_OFFSET 0x61000
>  #define TRANSCODER_C_OFFSET 0x62000
> +#define CHV_TRANSCODER_C_OFFSET 0x63000
>  #define TRANSCODER_EDP_OFFSET 0x6f000
>  
>  #define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
> @@ -3543,9 +3547,10 @@ enum punit_power_well {
>  #define PIPESTAT_INT_ENABLE_MASK		0x7fff0000
>  #define PIPESTAT_INT_STATUS_MASK		0x0000ffff
>  
> -#define PIPE_A_OFFSET	0x70000
> -#define PIPE_B_OFFSET	0x71000
> -#define PIPE_C_OFFSET	0x72000
> +#define PIPE_A_OFFSET		0x70000
> +#define PIPE_B_OFFSET		0x71000
> +#define PIPE_C_OFFSET		0x72000
> +#define CHV_PIPE_C_OFFSET	0x74000
>  /*
>   * There's actually no pipe EDP. Some pipe registers have
>   * simply shifted from the pipe to the transcoder, while
> -- 
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 43/71] drm/i915/chv: Add a bunch of pre production workarounds

[Damien Lespiau]

On Wed, Apr 09, 2014 at 01:28:41PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The following workarounds should be needed for pre-production hardware
> only:
> * WaDisablePwrmtrEvent:chv
> * WaSetMaskForGfxBusyness:chv
> * WaDisableGunitClockGating:chv
> * WaDisableFfDopClockGating:chv
> * WaDisableDopClockGating:chv
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

What about that hunk?

> +	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> +		   GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);

I couldn't find a W/A in the db nor in BSpec. The rest looks good
though.

-- 
Damien

> ---
>  drivers/gpu/drm/i915/i915_reg.h |  3 +++
>  drivers/gpu/drm/i915/intel_pm.c | 20 +++++++++++++++++++-
>  2 files changed, 22 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ac5047b..7587752 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1024,6 +1024,7 @@ enum punit_power_well {
>  #define IMR		0x020a8
>  #define ISR		0x020ac
>  #define VLV_GUNIT_CLOCK_GATE	(VLV_DISPLAY_BASE + 0x2060)
> +#define   GINT_DIS		(1<<22)
>  #define   GCFG_DIS		(1<<8)
>  #define VLV_IIR_RW	(VLV_DISPLAY_BASE + 0x2084)
>  #define VLV_IER		(VLV_DISPLAY_BASE + 0x20a0)
> @@ -1154,6 +1155,7 @@ enum punit_power_well {
>  
>  #define GEN6_RC_SLEEP_PSMI_CONTROL	0x2050
>  #define   GEN8_RC_SEMA_IDLE_MSG_DISABLE	(1 << 12)
> +#define   GEN8_FF_DOP_CLOCK_GATE_DISABLE	(1<<10)
>  
>  #define GEN6_BSD_SLEEP_PSMI_CONTROL	0x12050
>  #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
> @@ -5186,6 +5188,7 @@ enum punit_power_well {
>  #define  HSW_EDRAM_PRESENT			0x120010
>  
>  #define GEN6_UCGCTL1				0x9400
> +# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE		(1 << 16)
>  # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE		(1 << 5)
>  # define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 60f876c..587d32f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3775,10 +3775,14 @@ static void cherryview_enable_rps(struct drm_device *dev)
>  
>  	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
>  
> +	/* WaDisablePwrmtrEvent:chv (pre-production hw) */
> +	I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
> +	I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
> +
>  	/* 5: Enable RPS */
>  	I915_WRITE(GEN6_RP_CONTROL,
>  		   GEN6_RP_MEDIA_HW_NORMAL_MODE |
> -		   GEN6_RP_MEDIA_IS_GFX |
> +		   GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
>  		   GEN6_RP_ENABLE |
>  		   GEN6_RP_UP_BUSY_AVG |
>  		   GEN6_RP_DOWN_IDLE_AVG);
> @@ -5409,6 +5413,20 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
>  	/* WaDisableSamplerPowerBypass:chv (pre-production hw) */
>  	I915_WRITE(HALF_SLICE_CHICKEN3,
>  		   _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
> +
> +	/* WaDisableGunitClockGating:chv (pre-production hw) */
> +	I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
> +		   GINT_DIS);
> +
> +	/* WaDisableFfDopClockGating:chv (pre-production hw) */
> +	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
> +		   _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
> +
> +	/* WaDisableDopClockGating:chv (pre-production hw) */
> +	I915_WRITE(GEN7_ROW_CHICKEN2,
> +		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> +	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> +		   GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
>  }
>  
>  static void g4x_init_clock_gating(struct drm_device *dev)
> -- 
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 51/71] drm/i915/chv: Use valleyview_pipestat_irq_handler() for CHV

[Daniel Vetter]

On Wed, Apr 09, 2014 at 01:28:49PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 91 ++++++++---------------------------------
>  1 file changed, 17 insertions(+), 74 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 9c18a47..9702fde 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1660,6 +1660,9 @@ static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
>  		case PIPE_B:
>  			iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
>  			break;
> +		case PIPE_C:
> +			iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
> +			break;
>  		}
>  		if (iir & iir_bit)
>  			mask |= dev_priv->pipestat_irq_mask[pipe];
> @@ -1771,87 +1774,32 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
>  	drm_i915_private_t *dev_priv = dev->dev_private;
>  	u32 master_ctl, iir;
>  	irqreturn_t ret = IRQ_NONE;
> -	unsigned int pipes = 0;
> -
> -	master_ctl = I915_READ(GEN8_MASTER_IRQ);
> -
> -	I915_WRITE(GEN8_MASTER_IRQ, 0);
> -
> -	ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
>  
> +	master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~DE_MASTER_IRQ_CONTROL;
>  	iir = I915_READ(VLV_IIR);
>  
> -	if (iir & (I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT))
> -		pipes |= 1 << 0;
> -	if (iir & (I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT))
> -		pipes |= 1 << 1;
> -	if (iir & (I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT | I915_DISPLAY_PIPE_C_EVENT_INTERRUPT))
> -		pipes |= 1 << 2;
> -
> -	if (pipes) {
> -		u32 pipe_stats[I915_MAX_PIPES] = {};
> -		unsigned long irqflags;
> -		int pipe;
> -
> -		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> -		for_each_pipe(pipe) {
> -			unsigned int reg;
> -
> -			if (!(pipes & (1 << pipe)))
> -				continue;
> -
> -			reg = PIPESTAT(pipe);
> -			pipe_stats[pipe] = I915_READ(reg);
> -
> -			/*
> -			 * Clear the PIPE*STAT regs before the IIR
> -			 */
> -			if (pipe_stats[pipe] & 0x8000ffff) {
> -				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
> -					DRM_DEBUG_DRIVER("pipe %c underrun\n",
> -							 pipe_name(pipe));
> -				I915_WRITE(reg, pipe_stats[pipe]);
> -			}
> -		}
> -		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> -
> -		for_each_pipe(pipe) {
> -			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
> -				drm_handle_vblank(dev, pipe);
> +	if (master_ctl == 0 && iir == 0)
> +		return IRQ_NONE;
>  
> -			if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
> -				intel_prepare_page_flip(dev, pipe);
> -				intel_finish_page_flip(dev, pipe);
> -			}
> -		}
> +	I915_WRITE(GEN8_MASTER_IRQ, 0);
>  
> -		if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
> -			gmbus_irq_handler(dev);
> +	gen8_gt_irq_handler(dev, dev_priv, master_ctl);
>  
> -		ret = IRQ_HANDLED;
> -	}
> +	valleyview_pipestat_irq_handler(dev, iir);
>  
>  	/* Consume port.  Then clear IIR or we'll miss events */
>  	if (iir & I915_DISPLAY_PORT_INTERRUPT) {
> -		u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
> -
> -		I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
> -
> -		DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
> -				 hotplug_status);
> -		if (hotplug_status & HOTPLUG_INT_STATUS_I915)
> -			queue_work(dev_priv->wq,
> -				   &dev_priv->hotplug_work);
> -
> +		i9xx_hpd_irq_handler(dev, iir);

Fun conflict here - my version of i9xx_hpd_irq_handler doesn't want an iir
argument. Please sanity-check, thanks.
-Daniel

>  		ret = IRQ_HANDLED;
>  	}
>  
> -
>  	I915_WRITE(VLV_IIR, iir);
>  
>  	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
>  	POSTING_READ(GEN8_MASTER_IRQ);
>  
> +	ret = IRQ_HANDLED;
> +
>  	return ret;
>  }
>  
> @@ -3526,12 +3474,10 @@ static int cherryview_irq_postinstall(struct drm_device *dev)
>  	drm_i915_private_t *dev_priv = dev->dev_private;
>  	u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
>  		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
> -		I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
>  		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
> -		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT |
> -		I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
> -		I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT;
> -	u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
> +		I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
> +	u32 pipestat_enable = PLANE_FLIP_DONE_INT_STATUS_VLV |
> +		PIPE_CRC_DONE_INTERRUPT_STATUS;
>  	unsigned long irqflags;
>  	int pipe;
>  
> @@ -3539,16 +3485,13 @@ static int cherryview_irq_postinstall(struct drm_device *dev)
>  	 * Leave vblank interrupts masked initially.  enable/disable will
>  	 * toggle them based on usage.
>  	 */
> -	dev_priv->irq_mask = ~enable_mask |
> -		I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
> -		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT |
> -		I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT;
> +	dev_priv->irq_mask = ~enable_mask;
>  
>  	for_each_pipe(pipe)
>  		I915_WRITE(PIPESTAT(pipe), 0xffff);
>  
>  	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> -	i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
> +	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
>  	for_each_pipe(pipe)
>  		i915_enable_pipestat(dev_priv, pipe, pipestat_enable);
>  	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> -- 
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx


-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 52/71] drm/i915/chv: Make CHV irq handler loop until all interrupts are consumed

[Daniel Vetter]

On Wed, Apr 09, 2014 at 01:28:50PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Same cautious note about conflicts here ...
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_irq.c | 29 ++++++++++++++---------------
>  1 file changed, 14 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 9702fde..fc9b7e6 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1775,30 +1775,29 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
>  	u32 master_ctl, iir;
>  	irqreturn_t ret = IRQ_NONE;
>  
> -	master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~DE_MASTER_IRQ_CONTROL;
> -	iir = I915_READ(VLV_IIR);
> +	for (;;) {
> +		master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
> +		iir = I915_READ(VLV_IIR);
>  
> -	if (master_ctl == 0 && iir == 0)
> -		return IRQ_NONE;
> +		if (master_ctl == 0 && iir == 0)
> +			break;
>  
> -	I915_WRITE(GEN8_MASTER_IRQ, 0);
> +		I915_WRITE(GEN8_MASTER_IRQ, 0);
>  
> -	gen8_gt_irq_handler(dev, dev_priv, master_ctl);
> +		gen8_gt_irq_handler(dev, dev_priv, master_ctl);
>  
> -	valleyview_pipestat_irq_handler(dev, iir);
> +		valleyview_pipestat_irq_handler(dev, iir);
>  
> -	/* Consume port.  Then clear IIR or we'll miss events */
> -	if (iir & I915_DISPLAY_PORT_INTERRUPT) {
> +		/* Consume port.  Then clear IIR or we'll miss events */
>  		i9xx_hpd_irq_handler(dev, iir);
> -		ret = IRQ_HANDLED;
> -	}
>  
> -	I915_WRITE(VLV_IIR, iir);
> +		I915_WRITE(VLV_IIR, iir);
>  
> -	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
> -	POSTING_READ(GEN8_MASTER_IRQ);
> +		I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
> +		POSTING_READ(GEN8_MASTER_IRQ);
>  
> -	ret = IRQ_HANDLED;
> +		ret = IRQ_HANDLED;
> +	}
>  
>  	return ret;
>  }
> -- 
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx


-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 43/71] drm/i915/chv: Add a bunch of pre production workarounds

[Ville Syrjälä]

On Tue, May 20, 2014 at 02:22:51PM +0100, Damien Lespiau wrote:
> On Wed, Apr 09, 2014 at 01:28:41PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > The following workarounds should be needed for pre-production hardware
> > only:
> > * WaDisablePwrmtrEvent:chv
> > * WaSetMaskForGfxBusyness:chv
> > * WaDisableGunitClockGating:chv
> > * WaDisableFfDopClockGating:chv
> > * WaDisableDopClockGating:chv
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> What about that hunk?
> 
> > +	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> > +		   GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
> 
> I couldn't find a W/A in the db nor in BSpec. The rest looks good
> though.

It was mentioned in the hsd for the WaDisableDopClockGating w/a. I think
we already merged the same w/a for bdw but without the tcunit bit even
though I had questioned the fate of the tcunit bit during review.

> 
> -- 
> Damien
> 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h |  3 +++
> >  drivers/gpu/drm/i915/intel_pm.c | 20 +++++++++++++++++++-
> >  2 files changed, 22 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index ac5047b..7587752 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1024,6 +1024,7 @@ enum punit_power_well {
> >  #define IMR		0x020a8
> >  #define ISR		0x020ac
> >  #define VLV_GUNIT_CLOCK_GATE	(VLV_DISPLAY_BASE + 0x2060)
> > +#define   GINT_DIS		(1<<22)
> >  #define   GCFG_DIS		(1<<8)
> >  #define VLV_IIR_RW	(VLV_DISPLAY_BASE + 0x2084)
> >  #define VLV_IER		(VLV_DISPLAY_BASE + 0x20a0)
> > @@ -1154,6 +1155,7 @@ enum punit_power_well {
> >  
> >  #define GEN6_RC_SLEEP_PSMI_CONTROL	0x2050
> >  #define   GEN8_RC_SEMA_IDLE_MSG_DISABLE	(1 << 12)
> > +#define   GEN8_FF_DOP_CLOCK_GATE_DISABLE	(1<<10)
> >  
> >  #define GEN6_BSD_SLEEP_PSMI_CONTROL	0x12050
> >  #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
> > @@ -5186,6 +5188,7 @@ enum punit_power_well {
> >  #define  HSW_EDRAM_PRESENT			0x120010
> >  
> >  #define GEN6_UCGCTL1				0x9400
> > +# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE		(1 << 16)
> >  # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE		(1 << 5)
> >  # define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 60f876c..587d32f 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3775,10 +3775,14 @@ static void cherryview_enable_rps(struct drm_device *dev)
> >  
> >  	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
> >  
> > +	/* WaDisablePwrmtrEvent:chv (pre-production hw) */
> > +	I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
> > +	I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
> > +
> >  	/* 5: Enable RPS */
> >  	I915_WRITE(GEN6_RP_CONTROL,
> >  		   GEN6_RP_MEDIA_HW_NORMAL_MODE |
> > -		   GEN6_RP_MEDIA_IS_GFX |
> > +		   GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
> >  		   GEN6_RP_ENABLE |
> >  		   GEN6_RP_UP_BUSY_AVG |
> >  		   GEN6_RP_DOWN_IDLE_AVG);
> > @@ -5409,6 +5413,20 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
> >  	/* WaDisableSamplerPowerBypass:chv (pre-production hw) */
> >  	I915_WRITE(HALF_SLICE_CHICKEN3,
> >  		   _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
> > +
> > +	/* WaDisableGunitClockGating:chv (pre-production hw) */
> > +	I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
> > +		   GINT_DIS);
> > +
> > +	/* WaDisableFfDopClockGating:chv (pre-production hw) */
> > +	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
> > +		   _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
> > +
> > +	/* WaDisableDopClockGating:chv (pre-production hw) */
> > +	I915_WRITE(GEN7_ROW_CHICKEN2,
> > +		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> > +	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> > +		   GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
> >  }
> >  
> >  static void g4x_init_clock_gating(struct drm_device *dev)
> > -- 
> > 1.8.3.2
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 64/71] drm/i915/chv: Don't use PCS group access reads

[Daniel Vetter]

On Wed, Apr 09, 2014 at 07:56:50PM +0300, Ville Syrjälä wrote:
> On Wed, Apr 09, 2014 at 06:18:38PM +0200, Daniel Vetter wrote:
> > On Wed, Apr 09, 2014 at 01:29:02PM +0300, ville.syrjala@linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > All PCS groups access reads return 0xffffffff, so we can't use group
> > > access for RMW cycles. Instead target each spline separately.
> > 
> > I have no idea what PCS means here and spline ... Can you please expand
> > for those who haven't yet lost their souls in chv docs? Just so we have a
> > commonly-understood jargon for talking about this stuff.
> 
> I guess we should have that somewhere as a comment. The same terminology
> applies to VLV as well.

Haven't seen the promised patch yet.
-Daniel

> 
> > 
> > Thanks, Daniel
> > 
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h   | 14 ++++++++++++++
> > >  drivers/gpu/drm/i915/intel_dp.c   | 32 ++++++++++++++++++++++++--------
> > >  drivers/gpu/drm/i915/intel_hdmi.c | 34 +++++++++++++++++++++++++---------
> > >  3 files changed, 63 insertions(+), 17 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 4617fb3..ffed03e 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -654,6 +654,13 @@ enum punit_power_well {
> > >  #define   DPIO_PCS_TX_LANE1_RESET	(1<<7)
> > >  #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
> > >  
> > > +#define _VLV_PCS01_DW0_CH0		0x200
> > > +#define _VLV_PCS23_DW0_CH0		0x400
> > > +#define _VLV_PCS01_DW0_CH1		0x2600
> > > +#define _VLV_PCS23_DW0_CH1		0x2800
> > > +#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
> > > +#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
> > > +
> > >  #define _VLV_PCS_DW1_CH0		0x8204
> > >  #define _VLV_PCS_DW1_CH1		0x8404
> > >  #define   CHV_PCS_REQ_SOFTRESET_EN	(1<<23)
> > > @@ -663,6 +670,13 @@ enum punit_power_well {
> > >  #define   DPIO_PCS_CLK_SOFT_RESET	(1<<5)
> > >  #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
> > >  
> > > +#define _VLV_PCS01_DW1_CH0		0x204
> > > +#define _VLV_PCS23_DW1_CH0		0x404
> > > +#define _VLV_PCS01_DW1_CH1		0x2604
> > > +#define _VLV_PCS23_DW1_CH1		0x2804
> > > +#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
> > > +#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
> > > +
> > >  #define _VLV_PCS_DW8_CH0		0x8220
> > >  #define _VLV_PCS_DW8_CH1		0x8420
> > >  #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > > index 079e0e3..cc7bccd3 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -1845,13 +1845,21 @@ static void chv_post_disable_dp(struct intel_encoder *encoder)
> > >  	mutex_lock(&dev_priv->dpio_lock);
> > >  
> > >  	/* Propagate soft reset to data lane reset */
> > > -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
> > > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
> > >  	val |= CHV_PCS_REQ_SOFTRESET_EN;
> > > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
> > > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
> > >  
> > > -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
> > > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> > > +	val |= CHV_PCS_REQ_SOFTRESET_EN;
> > > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
> > > +
> > > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> > > +	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> > > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
> > > +
> > > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> > >  	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> > > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
> > > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
> > >  
> > >  	mutex_unlock(&dev_priv->dpio_lock);
> > >  }
> > > @@ -1983,13 +1991,21 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
> > >  	mutex_lock(&dev_priv->dpio_lock);
> > >  
> > >  	/* Deassert soft data lane reset*/
> > > -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
> > > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
> > >  	val |= CHV_PCS_REQ_SOFTRESET_EN;
> > > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
> > > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
> > > +
> > > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> > > +	val |= CHV_PCS_REQ_SOFTRESET_EN;
> > > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
> > > +
> > > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> > > +	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> > > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
> > >  
> > > -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
> > > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> > >  	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> > > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
> > > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
> > >  
> > >  	/* Program Tx lane latency optimal setting*/
> > >  	for (i = 0; i < 4; i++) {
> > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> > > index 6a2152b..c3896b0 100644
> > > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > > @@ -1216,13 +1216,21 @@ static void chv_hdmi_post_disable(struct intel_encoder *encoder)
> > >  	mutex_lock(&dev_priv->dpio_lock);
> > >  
> > >  	/* Propagate soft reset to data lane reset */
> > > -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
> > > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
> > >  	val |= CHV_PCS_REQ_SOFTRESET_EN;
> > > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val)
> > > -;
> > > -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
> > > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
> > > +
> > > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> > > +	val |= CHV_PCS_REQ_SOFTRESET_EN;
> > > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
> > > +
> > > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> > > +	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> > > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
> > > +
> > > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> > >  	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> > > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
> > > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
> > >  
> > >  	mutex_unlock(&dev_priv->dpio_lock);
> > >  }
> > > @@ -1242,13 +1250,21 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
> > >  	mutex_lock(&dev_priv->dpio_lock);
> > >  
> > >  	/* Deassert soft data lane reset*/
> > > -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
> > > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
> > >  	val |= CHV_PCS_REQ_SOFTRESET_EN;
> > > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
> > > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
> > > +
> > > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> > > +	val |= CHV_PCS_REQ_SOFTRESET_EN;
> > > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
> > > +
> > > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> > > +	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> > > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
> > >  
> > > -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
> > > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> > >  	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> > > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
> > > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
> > >  
> > >  	/* Program Tx latency optimal setting */
> > >  	for (i = 0; i < 4; i++) {
> > > -- 
> > > 1.8.3.2
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > +41 (0) 79 365 57 48 - http://blog.ffwll.ch
> 
> -- 
> Ville Syrjälä
> Intel OTC

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 43/71] drm/i915/chv: Add a bunch of pre production workarounds

[Damien Lespiau]

On Tue, May 20, 2014 at 04:41:13PM +0300, Ville Syrjälä wrote:
> On Tue, May 20, 2014 at 02:22:51PM +0100, Damien Lespiau wrote:
> > On Wed, Apr 09, 2014 at 01:28:41PM +0300, ville.syrjala@linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > The following workarounds should be needed for pre-production hardware
> > > only:
> > > * WaDisablePwrmtrEvent:chv
> > > * WaSetMaskForGfxBusyness:chv
> > > * WaDisableGunitClockGating:chv
> > > * WaDisableFfDopClockGating:chv
> > > * WaDisableDopClockGating:chv
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > What about that hunk?
> > 
> > > +	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> > > +		   GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
> > 
> > I couldn't find a W/A in the db nor in BSpec. The rest looks good
> > though.
> 
> It was mentioned in the hsd for the WaDisableDopClockGating w/a. I think
> we already merged the same w/a for bdw but without the tcunit bit even
> though I had questioned the fate of the tcunit bit during review.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

Re: [PATCH 64/71] drm/i915/chv: Don't use PCS group access reads

[Ville Syrjälä]

On Tue, May 20, 2014 at 03:50:02PM +0200, Daniel Vetter wrote:
> On Wed, Apr 09, 2014 at 07:56:50PM +0300, Ville Syrjälä wrote:
> > On Wed, Apr 09, 2014 at 06:18:38PM +0200, Daniel Vetter wrote:
> > > On Wed, Apr 09, 2014 at 01:29:02PM +0300, ville.syrjala@linux.intel.com wrote:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > 
> > > > All PCS groups access reads return 0xffffffff, so we can't use group
> > > > access for RMW cycles. Instead target each spline separately.
> > > 
> > > I have no idea what PCS means here and spline ... Can you please expand
> > > for those who haven't yet lost their souls in chv docs? Just so we have a
> > > commonly-understood jargon for talking about this stuff.
> > 
> > I guess we should have that somewhere as a comment. The same terminology
> > applies to VLV as well.
> 
> Haven't seen the promised patch yet.

"[PATCH] drm/i915: Add a brief description of the VLV display PHY internals" & co.

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 64/71] drm/i915/chv: Don't use PCS group access reads

[Daniel Vetter]

On Tue, May 20, 2014 at 4:11 PM, Ville Syrjälä
<ville.syrjala@linux.intel.com> wrote:
> On Tue, May 20, 2014 at 03:50:02PM +0200, Daniel Vetter wrote:
>> On Wed, Apr 09, 2014 at 07:56:50PM +0300, Ville Syrjälä wrote:
>> > On Wed, Apr 09, 2014 at 06:18:38PM +0200, Daniel Vetter wrote:
>> > > On Wed, Apr 09, 2014 at 01:29:02PM +0300, ville.syrjala@linux.intel.com wrote:
>> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > > >
>> > > > All PCS groups access reads return 0xffffffff, so we can't use group
>> > > > access for RMW cycles. Instead target each spline separately.
>> > >
>> > > I have no idea what PCS means here and spline ... Can you please expand
>> > > for those who haven't yet lost their souls in chv docs? Just so we have a
>> > > commonly-understood jargon for talking about this stuff.
>> >
>> > I guess we should have that somewhere as a comment. The same terminology
>> > applies to VLV as well.
>>
>> Haven't seen the promised patch yet.
>
> "[PATCH] drm/i915: Add a brief description of the VLV display PHY internals" & co.

Indeed, but fell through the review cracks :(
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 67/71] drm/i915/chv: Try to program the PHY used clock channel overrides

[Mika Kuoppala]

ville.syrjala@linux.intel.com writes:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> These should make it possible to feed port C from pipe A or port B from
> pipe B. Didn't quite seem to work though.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h   |  7 ++++++
>  drivers/gpu/drm/i915/intel_dp.c   | 46 +++++++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_hdmi.c | 46 +++++++++++++++++++++++++++++++++++++++
>  3 files changed, 99 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7056994..4bb733b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -679,6 +679,8 @@ enum punit_power_well {
>  
>  #define _VLV_PCS_DW8_CH0		0x8220
>  #define _VLV_PCS_DW8_CH1		0x8420
> +#define   CHV_PCS_USEDCLKCHANNEL_OVRRIDE	(1 << 20)
> +#define   CHV_PCS_USEDCLKCHANNEL		(1 << 21)
>  #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
>  
>  #define _VLV_PCS01_DW8_CH0		0x0220
> @@ -803,6 +805,11 @@ enum punit_power_well {
>  #define   DPIO_DCLKP_EN			(1 << 13)
>  #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
>  
> +#define _CHV_CMN_DW19_CH0		0x814c
> +#define _CHV_CMN_DW6_CH1		0x8098
> +#define   CHV_CMN_USEDCLKCHANNEL	(1 << 13)
> +#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
> +
>  #define CHV_CMN_DW30			0x8178
>  #define   DPIO_LRC_BYPASS		(1 << 3)
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 9cbd702..9d6982e 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2037,6 +2037,51 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
>  	vlv_wait_port_ready(dev_priv, dport);
>  }
>  
> +static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
> +{
> +	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> +	struct drm_device *dev = encoder->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc =
> +		to_intel_crtc(encoder->base.crtc);
> +	enum dpio_channel ch = vlv_dport_to_channel(dport);
> +	enum pipe pipe = intel_crtc->pipe;
> +	u32 val;
> +
> +	mutex_lock(&dev_priv->dpio_lock);
> +
> +	/* program clock channel usage */
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
> +	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
> +	if (pipe != PIPE_B)
> +		val &= ~CHV_PCS_USEDCLKCHANNEL;
> +	else
> +		val |= CHV_PCS_USEDCLKCHANNEL;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
> +	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
> +	if (pipe != PIPE_B)
> +		val &= ~CHV_PCS_USEDCLKCHANNEL;
> +	else
> +		val |= CHV_PCS_USEDCLKCHANNEL;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
> +
> +	/*
> +	 * This a a bit weird since generally CL
> +	 * matches the pipe, but here we need to
> +	 * pick the CL based on the port.
> +	 */
> +	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));

Should we add setting bit 15 always in here?

-Mika

> +	if (pipe != PIPE_B)
> +		val &= ~CHV_CMN_USEDCLKCHANNEL;
> +	else
> +		val |= CHV_CMN_USEDCLKCHANNEL;
> +	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
> +
> +	mutex_unlock(&dev_priv->dpio_lock);
> +}
> +
>  /*
>   * Native read with retry for link status and receiver capability reads for
>   * cases where the sink may still be asleep.
> @@ -4134,6 +4179,7 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
>  	intel_encoder->get_hw_state = intel_dp_get_hw_state;
>  	intel_encoder->get_config = intel_dp_get_config;
>  	if (IS_CHERRYVIEW(dev)) {
> +		intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
>  		intel_encoder->pre_enable = chv_pre_enable_dp;
>  		intel_encoder->enable = vlv_enable_dp;
>  		intel_encoder->post_disable = chv_post_disable_dp;
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index d2b1186..d36f74c 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1186,6 +1186,51 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
>  	mutex_unlock(&dev_priv->dpio_lock);
>  }
>  
> +static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
> +{
> +	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> +	struct drm_device *dev = encoder->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc =
> +		to_intel_crtc(encoder->base.crtc);
> +	enum dpio_channel ch = vlv_dport_to_channel(dport);
> +	enum pipe pipe = intel_crtc->pipe;
> +	u32 val;
> +
> +	mutex_lock(&dev_priv->dpio_lock);
> +
> +	/* program clock channel usage */
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
> +	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
> +	if (pipe != PIPE_B)
> +		val &= ~CHV_PCS_USEDCLKCHANNEL;
> +	else
> +		val |= CHV_PCS_USEDCLKCHANNEL;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
> +	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
> +	if (pipe != PIPE_B)
> +		val &= ~CHV_PCS_USEDCLKCHANNEL;
> +	else
> +		val |= CHV_PCS_USEDCLKCHANNEL;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
> +
> +	/*
> +	 * This a a bit weird since generally CL
> +	 * matches the pipe, but here we need to
> +	 * pick the CL based on the port.
> +	 */
> +	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
> +	if (pipe != PIPE_B)
> +		val &= ~CHV_CMN_USEDCLKCHANNEL;
> +	else
> +		val |= CHV_CMN_USEDCLKCHANNEL;
> +	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
> +
> +	mutex_unlock(&dev_priv->dpio_lock);
> +}
> +
>  static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
>  {
>  	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> @@ -1486,6 +1531,7 @@ void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
>  	intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
>  	intel_encoder->get_config = intel_hdmi_get_config;
>  	if (IS_CHERRYVIEW(dev)) {
> +		intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
>  		intel_encoder->pre_enable = chv_hdmi_pre_enable;
>  		intel_encoder->enable = vlv_enable_hdmi;
>  		intel_encoder->post_disable = chv_hdmi_post_disable;
> -- 
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 67/71] drm/i915/chv: Try to program the PHY used clock channel overrides

[Mika Kuoppala]

Mika Kuoppala <mika.kuoppala@linux.intel.com> writes:

> ville.syrjala@linux.intel.com writes:
>
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> These should make it possible to feed port C from pipe A or port B from
>> pipe B. Didn't quite seem to work though.
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h   |  7 ++++++
>>  drivers/gpu/drm/i915/intel_dp.c   | 46 +++++++++++++++++++++++++++++++++++++++
>>  drivers/gpu/drm/i915/intel_hdmi.c | 46 +++++++++++++++++++++++++++++++++++++++
>>  3 files changed, 99 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 7056994..4bb733b 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -679,6 +679,8 @@ enum punit_power_well {
>>  
>>  #define _VLV_PCS_DW8_CH0		0x8220
>>  #define _VLV_PCS_DW8_CH1		0x8420
>> +#define   CHV_PCS_USEDCLKCHANNEL_OVRRIDE	(1 << 20)
>> +#define   CHV_PCS_USEDCLKCHANNEL		(1 << 21)
>>  #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
>>  
>>  #define _VLV_PCS01_DW8_CH0		0x0220
>> @@ -803,6 +805,11 @@ enum punit_power_well {
>>  #define   DPIO_DCLKP_EN			(1 << 13)
>>  #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
>>  
>> +#define _CHV_CMN_DW19_CH0		0x814c
>> +#define _CHV_CMN_DW6_CH1		0x8098
>> +#define   CHV_CMN_USEDCLKCHANNEL	(1 << 13)
>> +#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
>> +
>>  #define CHV_CMN_DW30			0x8178
>>  #define   DPIO_LRC_BYPASS		(1 << 3)
>>  
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 9cbd702..9d6982e 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -2037,6 +2037,51 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
>>  	vlv_wait_port_ready(dev_priv, dport);
>>  }
>>  
>> +static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
>> +{
>> +	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
>> +	struct drm_device *dev = encoder->base.dev;
>> +	struct drm_i915_private *dev_priv = dev->dev_private;
>> +	struct intel_crtc *intel_crtc =
>> +		to_intel_crtc(encoder->base.crtc);
>> +	enum dpio_channel ch = vlv_dport_to_channel(dport);
>> +	enum pipe pipe = intel_crtc->pipe;
>> +	u32 val;
>> +
>> +	mutex_lock(&dev_priv->dpio_lock);
>> +
>> +	/* program clock channel usage */
>> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
>> +	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
>> +	if (pipe != PIPE_B)
>> +		val &= ~CHV_PCS_USEDCLKCHANNEL;
>> +	else
>> +		val |= CHV_PCS_USEDCLKCHANNEL;
>> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
>> +
>> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
>> +	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
>> +	if (pipe != PIPE_B)
>> +		val &= ~CHV_PCS_USEDCLKCHANNEL;
>> +	else
>> +		val |= CHV_PCS_USEDCLKCHANNEL;
>> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
>> +
>> +	/*
>> +	 * This a a bit weird since generally CL
>> +	 * matches the pipe, but here we need to
>> +	 * pick the CL based on the port.
>> +	 */
>> +	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
>
> Should we add setting bit 15 always in here?

Talked with Ville in rl. This is for fast pll lock and just
happens to be enabled in example modes.

> -Mika
>
>> +	if (pipe != PIPE_B)
>> +		val &= ~CHV_CMN_USEDCLKCHANNEL;
>> +	else
>> +		val |= CHV_CMN_USEDCLKCHANNEL;
>> +	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
>> +
>> +	mutex_unlock(&dev_priv->dpio_lock);
>> +}
>> +
>>  /*
>>   * Native read with retry for link status and receiver capability reads for
>>   * cases where the sink may still be asleep.
>> @@ -4134,6 +4179,7 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
>>  	intel_encoder->get_hw_state = intel_dp_get_hw_state;
>>  	intel_encoder->get_config = intel_dp_get_config;
>>  	if (IS_CHERRYVIEW(dev)) {
>> +		intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
>>  		intel_encoder->pre_enable = chv_pre_enable_dp;
>>  		intel_encoder->enable = vlv_enable_dp;
>>  		intel_encoder->post_disable = chv_post_disable_dp;
>> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
>> index d2b1186..d36f74c 100644
>> --- a/drivers/gpu/drm/i915/intel_hdmi.c
>> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
>> @@ -1186,6 +1186,51 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
>>  	mutex_unlock(&dev_priv->dpio_lock);
>>  }
>>  
>> +static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
>> +{
>> +	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
>> +	struct drm_device *dev = encoder->base.dev;
>> +	struct drm_i915_private *dev_priv = dev->dev_private;
>> +	struct intel_crtc *intel_crtc =
>> +		to_intel_crtc(encoder->base.crtc);
>> +	enum dpio_channel ch = vlv_dport_to_channel(dport);
>> +	enum pipe pipe = intel_crtc->pipe;
>> +	u32 val;
>> +
>> +	mutex_lock(&dev_priv->dpio_lock);
>> +
>> +	/* program clock channel usage */
>> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
>> +	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
>> +	if (pipe != PIPE_B)
>> +		val &= ~CHV_PCS_USEDCLKCHANNEL;
>> +	else
>> +		val |= CHV_PCS_USEDCLKCHANNEL;
>> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
>> +
>> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
>> +	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
>> +	if (pipe != PIPE_B)
>> +		val &= ~CHV_PCS_USEDCLKCHANNEL;
>> +	else
>> +		val |= CHV_PCS_USEDCLKCHANNEL;
>> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
>> +
>> +	/*
>> +	 * This a a bit weird since generally CL
>> +	 * matches the pipe, but here we need to
>> +	 * pick the CL based on the port.
>> +	 */
>> +	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
>> +	if (pipe != PIPE_B)
>> +		val &= ~CHV_CMN_USEDCLKCHANNEL;
>> +	else
>> +		val |= CHV_CMN_USEDCLKCHANNEL;
>> +	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
>> +
>> +	mutex_unlock(&dev_priv->dpio_lock);
>> +}
>> +
>>  static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
>>  {
>>  	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
>> @@ -1486,6 +1531,7 @@ void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
>>  	intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
>>  	intel_encoder->get_config = intel_hdmi_get_config;
>>  	if (IS_CHERRYVIEW(dev)) {
>> +		intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
>>  		intel_encoder->pre_enable = chv_hdmi_pre_enable;
>>  		intel_encoder->enable = vlv_enable_hdmi;
>>  		intel_encoder->post_disable = chv_hdmi_post_disable;
>> -- 
>> 1.8.3.2
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[PATCH v2 68/71] drm/i915/chv: Force clock buffer enables

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Try to force the PHY clock buffer enables to make the clock routing
work.

v2: Fix the pipe B case to actually enable CH0 clock buffers

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   | 18 ++++++++++++++++++
 drivers/gpu/drm/i915/intel_dp.c   | 19 +++++++++++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c | 19 +++++++++++++++++++
 3 files changed, 56 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c8aa70f..d97f68e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -798,6 +798,16 @@ enum punit_power_well {
 #define   DPIO_CHV_PROP_COEFF_SHIFT	0
 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
 
+#define _CHV_CMN_DW5_CH0               0x8114
+#define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
+#define   CHV_BUFRIGHTENA1_NORMAL	(1 << 20)
+#define   CHV_BUFRIGHTENA1_FORCE	(3 << 20)
+#define   CHV_BUFRIGHTENA1_MASK		(3 << 20)
+#define   CHV_BUFLEFTENA1_DISABLE	(0 << 22)
+#define   CHV_BUFLEFTENA1_NORMAL	(1 << 22)
+#define   CHV_BUFLEFTENA1_FORCE		(3 << 22)
+#define   CHV_BUFLEFTENA1_MASK		(3 << 22)
+
 #define _CHV_CMN_DW13_CH0		0x8134
 #define _CHV_CMN_DW0_CH1		0x8080
 #define   DPIO_CHV_S1_DIV_SHIFT		21
@@ -812,6 +822,14 @@ enum punit_power_well {
 #define _CHV_CMN_DW1_CH1		0x8084
 #define   DPIO_AFC_RECAL		(1 << 14)
 #define   DPIO_DCLKP_EN			(1 << 13)
+#define   CHV_BUFLEFTENA2_DISABLE	(0 << 17) /* CL2 DW1 only */
+#define   CHV_BUFLEFTENA2_NORMAL	(1 << 17) /* CL2 DW1 only */
+#define   CHV_BUFLEFTENA2_FORCE		(3 << 17) /* CL2 DW1 only */
+#define   CHV_BUFLEFTENA2_MASK		(3 << 17) /* CL2 DW1 only */
+#define   CHV_BUFRIGHTENA2_DISABLE	(0 << 19) /* CL2 DW1 only */
+#define   CHV_BUFRIGHTENA2_NORMAL	(1 << 19) /* CL2 DW1 only */
+#define   CHV_BUFRIGHTENA2_FORCE	(3 << 19) /* CL2 DW1 only */
+#define   CHV_BUFRIGHTENA2_MASK		(3 << 19) /* CL2 DW1 only */
 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
 
 #define _CHV_CMN_DW19_CH0		0x814c
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 78fa387..dc823e1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2059,6 +2059,25 @@ static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
 
 	mutex_lock(&dev_priv->dpio_lock);
 
+	/* program left/right clock distribution */
+	if (pipe != PIPE_B) {
+		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
+		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
+		if (ch == DPIO_CH0)
+			val |= CHV_BUFLEFTENA1_FORCE;
+		if (ch == DPIO_CH1)
+			val |= CHV_BUFRIGHTENA1_FORCE;
+		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
+	} else {
+		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
+		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
+		if (ch == DPIO_CH0)
+			val |= CHV_BUFLEFTENA2_FORCE;
+		if (ch == DPIO_CH1)
+			val |= CHV_BUFRIGHTENA2_FORCE;
+		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
+	}
+
 	/* program clock channel usage */
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
 	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 0173250..debb2ee 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1224,6 +1224,25 @@ static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
 
 	mutex_lock(&dev_priv->dpio_lock);
 
+	/* program left/right clock distribution */
+	if (pipe != PIPE_B) {
+		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
+		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
+		if (ch == DPIO_CH0)
+			val |= CHV_BUFLEFTENA1_FORCE;
+		if (ch == DPIO_CH1)
+			val |= CHV_BUFRIGHTENA1_FORCE;
+		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
+	} else {
+		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
+		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
+		if (ch == DPIO_CH0)
+			val |= CHV_BUFLEFTENA2_FORCE;
+		if (ch == DPIO_CH1)
+			val |= CHV_BUFRIGHTENA2_FORCE;
+		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
+	}
+
 	/* program clock channel usage */
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
 	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
-- 
1.8.5.5

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[PATCH v2 69/71] drm/i915/chv: Force PHY clock buffers off after PLL disable

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Now that we forced the clock buffers on in .pre_pll_enable() we
should probably undo the damage after we've turned the PLL off.

We do the clock buffer force enable in the .pre_pll_enable() hook
as we need to know which port is going to be used, but in the disable
case we don't need the port since we just disable the clock buffers
to both channels. So we can do this in chv_disable_pll() instead
of having to add any kind of .post_pll_disable() hook.

v2: Improve the commit message

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3215169..376f6c3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1699,6 +1699,17 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 	val &= ~DPIO_DCLKP_EN;
 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
 
+	/* disable left/right clock distribution */
+	if (pipe != PIPE_B) {
+		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
+		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
+		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
+	} else {
+		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
+		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
+		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
+	}
+
 	mutex_unlock(&dev_priv->dpio_lock);
 }
 
-- 
1.8.5.5

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Re: [PATCH 67/71] drm/i915/chv: Try to program the PHY used clock channel overrides

[Mika Kuoppala]

ville.syrjala@linux.intel.com writes:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> These should make it possible to feed port C from pipe A or port B from
> pipe B. Didn't quite seem to work though.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h   |  7 ++++++
>  drivers/gpu/drm/i915/intel_dp.c   | 46 +++++++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_hdmi.c | 46 +++++++++++++++++++++++++++++++++++++++
>  3 files changed, 99 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7056994..4bb733b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -679,6 +679,8 @@ enum punit_power_well {
>  
>  #define _VLV_PCS_DW8_CH0		0x8220
>  #define _VLV_PCS_DW8_CH1		0x8420
> +#define   CHV_PCS_USEDCLKCHANNEL_OVRRIDE	(1 << 20)
> +#define   CHV_PCS_USEDCLKCHANNEL		(1 << 21)
>  #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
>  
>  #define _VLV_PCS01_DW8_CH0		0x0220
> @@ -803,6 +805,11 @@ enum punit_power_well {
>  #define   DPIO_DCLKP_EN			(1 << 13)
>  #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
>  
> +#define _CHV_CMN_DW19_CH0		0x814c
> +#define _CHV_CMN_DW6_CH1		0x8098
> +#define   CHV_CMN_USEDCLKCHANNEL	(1 << 13)
> +#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
> +
>  #define CHV_CMN_DW30			0x8178
>  #define   DPIO_LRC_BYPASS		(1 << 3)
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 9cbd702..9d6982e 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2037,6 +2037,51 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
>  	vlv_wait_port_ready(dev_priv, dport);
>  }
>  
> +static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
> +{
> +	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> +	struct drm_device *dev = encoder->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc =
> +		to_intel_crtc(encoder->base.crtc);
> +	enum dpio_channel ch = vlv_dport_to_channel(dport);
> +	enum pipe pipe = intel_crtc->pipe;
> +	u32 val;
> +
> +	mutex_lock(&dev_priv->dpio_lock);
> +
> +	/* program clock channel usage */
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
> +	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
> +	if (pipe != PIPE_B)
> +		val &= ~CHV_PCS_USEDCLKCHANNEL;
> +	else
> +		val |= CHV_PCS_USEDCLKCHANNEL;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
> +	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
> +	if (pipe != PIPE_B)
> +		val &= ~CHV_PCS_USEDCLKCHANNEL;
> +	else
> +		val |= CHV_PCS_USEDCLKCHANNEL;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
> +
> +	/*
> +	 * This a a bit weird since generally CL
> +	 * matches the pipe, but here we need to
> +	 * pick the CL based on the port.
> +	 */
> +	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
> +	if (pipe != PIPE_B)
> +		val &= ~CHV_CMN_USEDCLKCHANNEL;
> +	else
> +		val |= CHV_CMN_USEDCLKCHANNEL;
> +	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
> +
> +	mutex_unlock(&dev_priv->dpio_lock);
> +}
> +
>  /*
>   * Native read with retry for link status and receiver capability reads for
>   * cases where the sink may still be asleep.
> @@ -4134,6 +4179,7 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
>  	intel_encoder->get_hw_state = intel_dp_get_hw_state;
>  	intel_encoder->get_config = intel_dp_get_config;
>  	if (IS_CHERRYVIEW(dev)) {
> +		intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
>  		intel_encoder->pre_enable = chv_pre_enable_dp;
>  		intel_encoder->enable = vlv_enable_dp;
>  		intel_encoder->post_disable = chv_post_disable_dp;
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index d2b1186..d36f74c 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1186,6 +1186,51 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
>  	mutex_unlock(&dev_priv->dpio_lock);
>  }
>  
> +static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
> +{
> +	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> +	struct drm_device *dev = encoder->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc =
> +		to_intel_crtc(encoder->base.crtc);
> +	enum dpio_channel ch = vlv_dport_to_channel(dport);
> +	enum pipe pipe = intel_crtc->pipe;
> +	u32 val;
> +
> +	mutex_lock(&dev_priv->dpio_lock);
> +
> +	/* program clock channel usage */
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
> +	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
> +	if (pipe != PIPE_B)
> +		val &= ~CHV_PCS_USEDCLKCHANNEL;
> +	else
> +		val |= CHV_PCS_USEDCLKCHANNEL;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
> +	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
> +	if (pipe != PIPE_B)
> +		val &= ~CHV_PCS_USEDCLKCHANNEL;
> +	else
> +		val |= CHV_PCS_USEDCLKCHANNEL;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
> +
> +	/*
> +	 * This a a bit weird since generally CL
> +	 * matches the pipe, but here we need to
> +	 * pick the CL based on the port.
> +	 */
> +	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
> +	if (pipe != PIPE_B)
> +		val &= ~CHV_CMN_USEDCLKCHANNEL;
> +	else
> +		val |= CHV_CMN_USEDCLKCHANNEL;
> +	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
> +
> +	mutex_unlock(&dev_priv->dpio_lock);
> +}
> +
>  static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
>  {
>  	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> @@ -1486,6 +1531,7 @@ void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
>  	intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
>  	intel_encoder->get_config = intel_hdmi_get_config;
>  	if (IS_CHERRYVIEW(dev)) {
> +		intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
>  		intel_encoder->pre_enable = chv_hdmi_pre_enable;
>  		intel_encoder->enable = vlv_enable_hdmi;
>  		intel_encoder->post_disable = chv_hdmi_post_disable;
> -- 
> 1.8.3.2
>
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Re: [PATCH v2 68/71] drm/i915/chv: Force clock buffer enables

[Mika Kuoppala]

ville.syrjala@linux.intel.com writes:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Try to force the PHY clock buffer enables to make the clock routing
> work.
>
> v2: Fix the pipe B case to actually enable CH0 clock buffers
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h   | 18 ++++++++++++++++++
>  drivers/gpu/drm/i915/intel_dp.c   | 19 +++++++++++++++++++
>  drivers/gpu/drm/i915/intel_hdmi.c | 19 +++++++++++++++++++
>  3 files changed, 56 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c8aa70f..d97f68e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -798,6 +798,16 @@ enum punit_power_well {
>  #define   DPIO_CHV_PROP_COEFF_SHIFT	0
>  #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
>  
> +#define _CHV_CMN_DW5_CH0               0x8114
> +#define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
> +#define   CHV_BUFRIGHTENA1_NORMAL	(1 << 20)
> +#define   CHV_BUFRIGHTENA1_FORCE	(3 << 20)
> +#define   CHV_BUFRIGHTENA1_MASK		(3 << 20)
> +#define   CHV_BUFLEFTENA1_DISABLE	(0 << 22)
> +#define   CHV_BUFLEFTENA1_NORMAL	(1 << 22)
> +#define   CHV_BUFLEFTENA1_FORCE		(3 << 22)
> +#define   CHV_BUFLEFTENA1_MASK		(3 << 22)
> +
>  #define _CHV_CMN_DW13_CH0		0x8134
>  #define _CHV_CMN_DW0_CH1		0x8080
>  #define   DPIO_CHV_S1_DIV_SHIFT		21
> @@ -812,6 +822,14 @@ enum punit_power_well {
>  #define _CHV_CMN_DW1_CH1		0x8084
>  #define   DPIO_AFC_RECAL		(1 << 14)
>  #define   DPIO_DCLKP_EN			(1 << 13)
> +#define   CHV_BUFLEFTENA2_DISABLE	(0 << 17) /* CL2 DW1 only */
> +#define   CHV_BUFLEFTENA2_NORMAL	(1 << 17) /* CL2 DW1 only */
> +#define   CHV_BUFLEFTENA2_FORCE		(3 << 17) /* CL2 DW1 only */
> +#define   CHV_BUFLEFTENA2_MASK		(3 << 17) /* CL2 DW1 only */
> +#define   CHV_BUFRIGHTENA2_DISABLE	(0 << 19) /* CL2 DW1 only */
> +#define   CHV_BUFRIGHTENA2_NORMAL	(1 << 19) /* CL2 DW1 only */
> +#define   CHV_BUFRIGHTENA2_FORCE	(3 << 19) /* CL2 DW1 only */
> +#define   CHV_BUFRIGHTENA2_MASK		(3 << 19) /* CL2 DW1 only */
>  #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
>  
>  #define _CHV_CMN_DW19_CH0		0x814c
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 78fa387..dc823e1 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2059,6 +2059,25 @@ static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
>  
>  	mutex_lock(&dev_priv->dpio_lock);
>  
> +	/* program left/right clock distribution */
> +	if (pipe != PIPE_B) {
> +		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
> +		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
> +		if (ch == DPIO_CH0)
> +			val |= CHV_BUFLEFTENA1_FORCE;
> +		if (ch == DPIO_CH1)
> +			val |= CHV_BUFRIGHTENA1_FORCE;
> +		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
> +	} else {
> +		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
> +		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
> +		if (ch == DPIO_CH0)
> +			val |= CHV_BUFLEFTENA2_FORCE;
> +		if (ch == DPIO_CH1)
> +			val |= CHV_BUFRIGHTENA2_FORCE;
> +		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
> +	}
> +
>  	/* program clock channel usage */
>  	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
>  	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 0173250..debb2ee 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1224,6 +1224,25 @@ static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
>  
>  	mutex_lock(&dev_priv->dpio_lock);
>  
> +	/* program left/right clock distribution */
> +	if (pipe != PIPE_B) {
> +		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
> +		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
> +		if (ch == DPIO_CH0)
> +			val |= CHV_BUFLEFTENA1_FORCE;
> +		if (ch == DPIO_CH1)
> +			val |= CHV_BUFRIGHTENA1_FORCE;
> +		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
> +	} else {
> +		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
> +		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
> +		if (ch == DPIO_CH0)
> +			val |= CHV_BUFLEFTENA2_FORCE;
> +		if (ch == DPIO_CH1)
> +			val |= CHV_BUFRIGHTENA2_FORCE;
> +		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
> +	}
> +
>  	/* program clock channel usage */
>  	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
>  	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
> -- 
> 1.8.5.5
>
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Re: [PATCH v2 69/71] drm/i915/chv: Force PHY clock buffers off after PLL disable

[Mika Kuoppala]

ville.syrjala@linux.intel.com writes:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Now that we forced the clock buffers on in .pre_pll_enable() we
> should probably undo the damage after we've turned the PLL off.
>
> We do the clock buffer force enable in the .pre_pll_enable() hook
> as we need to know which port is going to be used, but in the disable
> case we don't need the port since we just disable the clock buffers
> to both channels. So we can do this in chv_disable_pll() instead
> of having to add any kind of .post_pll_disable() hook.
>
> v2: Improve the commit message
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3215169..376f6c3 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1699,6 +1699,17 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
>  	val &= ~DPIO_DCLKP_EN;
>  	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
>  
> +	/* disable left/right clock distribution */
> +	if (pipe != PIPE_B) {
> +		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
> +		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
> +		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
> +	} else {
> +		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
> +		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
> +		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
> +	}
> +
>  	mutex_unlock(&dev_priv->dpio_lock);
>  }
>  
> -- 
> 1.8.5.5
>
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Re: [PATCH 70/71] drm/i915: Don't use pipe_offset stuff for DPLL registers

[Daniel Vetter]

On Wed, Apr 09, 2014 at 08:18:03PM +0100, Damien Lespiau wrote:
> On Wed, Apr 09, 2014 at 01:29:08PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > These are just single registers so wasting space for the pipe offsets
> > seems a bit pointless. So just use the _PIPE3() macro instead.
> > 
> > Also rewrite the _PIPE3() macro to be more obvious, and protect the
> > arguments properly.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

This one here required a bit of conflict resolution. But now all patches
from this series should be applied, yay! And it took less than 8 weeks.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch