[PATCH 0/9] drm/i915: Update derived plane state at crtc enable/disable

[PATCH 0/9] drm/i915: Update derived plane state at crtc enable/disable

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Here's a quick series that tries to make our .crtc_{enable,disable}()
update the derived plane state correctly. The upside of doing this is
that we can actually trust the 'visible' and the clipped src/dst
coordinates for all planes.

I also took the opportunity to make the plane enable/disable happen
atomically when the crtc is enabled/disabled.

And now that the derived plane state is correct I added a few patchs to
use that information in the wm code, and also to prepare for primary plane
windowing.

Ville Syrjälä (9):
  drm/i915: Remove debug prints from primary plane update funcs
  drm/i915: Reduce clutter by using the local plane pointer
  drm/i915: Use plane->state->fb instead of plane->fb in
    intel_plane_restore()
  drm/i915: Make derived plane state correct after crtc_enable
  drm/i915: Pass primary plane size to .update_primary_plane()
  drm/i915: Pass the primary plane position to .update_primary_plane()
  drm/i915: Update watermarks after the derived plane state is uptodate
  drm/i915: Use state->visible in wm calculation
  drm/i915: Don't re-enable an explicitly disabled primary plane due to
    sprite coverage changes

 drivers/gpu/drm/i915/i915_drv.h      |   7 +-
 drivers/gpu/drm/i915/intel_display.c | 310 +++++++++++++++--------------------
 drivers/gpu/drm/i915/intel_pm.c      |  24 ++-
 drivers/gpu/drm/i915/intel_sprite.c  |   8 +-
 4 files changed, 163 insertions(+), 186 deletions(-)

-- 
2.0.5

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[PATCH 1/9] drm/i915: Remove debug prints from primary plane update funcs

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

These are now called from the plane commit hooks, so they really need to
be fast or else we risk atomic update failures. So kill the debug prints
which are slowing things down massively.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 11 -----------
 1 file changed, 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c3a5888..1d5107e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2658,9 +2658,6 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 
 	I915_WRITE(reg, dspcntr);
 
-	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
-		      i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
-		      fb->pitches[0]);
 	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
 	if (INTEL_INFO(dev)->gen >= 4) {
 		I915_WRITE(DSPSURF(plane),
@@ -2762,9 +2759,6 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 
 	I915_WRITE(reg, dspcntr);
 
-	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
-		      i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
-		      fb->pitches[0]);
 	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
 	I915_WRITE(DSPSURF(plane),
 		   i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
@@ -2890,11 +2884,6 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
 
 	I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
 
-	DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
-		      i915_gem_obj_ggtt_offset(obj),
-		      x, y, fb->width, fb->height,
-		      fb->pitches[0]);
-
 	I915_WRITE(PLANE_POS(pipe, 0), 0);
 	I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
 	I915_WRITE(PLANE_SIZE(pipe, 0),
-- 
2.0.5

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Re: [PATCH 1/9] drm/i915: Remove debug prints from primary plane update funcs

[Jesse Barnes]

On 03/10/2015 04:15 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> These are now called from the plane commit hooks, so they really need to
> be fast or else we risk atomic update failures. So kill the debug prints
> which are slowing things down massively.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 11 -----------
>  1 file changed, 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c3a5888..1d5107e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2658,9 +2658,6 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>  
>  	I915_WRITE(reg, dspcntr);
>  
> -	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
> -		      i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
> -		      fb->pitches[0]);
>  	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
>  	if (INTEL_INFO(dev)->gen >= 4) {
>  		I915_WRITE(DSPSURF(plane),
> @@ -2762,9 +2759,6 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>  
>  	I915_WRITE(reg, dspcntr);
>  
> -	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
> -		      i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
> -		      fb->pitches[0]);
>  	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
>  	I915_WRITE(DSPSURF(plane),
>  		   i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
> @@ -2890,11 +2884,6 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
>  
>  	I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
>  
> -	DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
> -		      i915_gem_obj_ggtt_offset(obj),
> -		      x, y, fb->width, fb->height,
> -		      fb->pitches[0]);
> -
>  	I915_WRITE(PLANE_POS(pipe, 0), 0);
>  	I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
>  	I915_WRITE(PLANE_SIZE(pipe, 0),
> 

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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[PATCH 2/9] drm/i915: Reduce clutter by using the local plane pointer

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

No need to go dig throguh intel_crtc->base.cursor when we already have
the same thing as 'plane' local variable.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1d5107e..0da3abf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12299,7 +12299,7 @@ intel_check_cursor_plane(struct drm_plane *plane,
 
 finish:
 	if (intel_crtc->active) {
-		if (intel_crtc->base.cursor->state->crtc_w != state->base.crtc_w)
+		if (plane->state->crtc_w != state->base.crtc_w)
 			intel_crtc->atomic.update_wm = true;
 
 		intel_crtc->atomic.fb_bits |=
-- 
2.0.5

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Re: [PATCH 2/9] drm/i915: Reduce clutter by using the local plane pointer

[Jesse Barnes]

On 03/10/2015 04:15 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> No need to go dig throguh intel_crtc->base.cursor when we already have
> the same thing as 'plane' local variable.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 1d5107e..0da3abf 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12299,7 +12299,7 @@ intel_check_cursor_plane(struct drm_plane *plane,
>  
>  finish:
>  	if (intel_crtc->active) {
> -		if (intel_crtc->base.cursor->state->crtc_w != state->base.crtc_w)
> +		if (plane->state->crtc_w != state->base.crtc_w)
>  			intel_crtc->atomic.update_wm = true;
>  
>  		intel_crtc->atomic.fb_bits |=
> 

At least it looks like we'll always get the right plane obj here. :)

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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[PATCH 3/9] drm/i915: Use plane->state->fb instead of plane->fb in intel_plane_restore()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

plane->fb is not as reliable as plane->state->fb so let's convert
intel_plane_restore() over the the new way of thinking as well.

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_sprite.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 7051da7..a828736 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1361,10 +1361,10 @@ out_unlock:
 
 int intel_plane_restore(struct drm_plane *plane)
 {
-	if (!plane->crtc || !plane->fb)
+	if (!plane->crtc || !plane->state->fb)
 		return 0;
 
-	return plane->funcs->update_plane(plane, plane->crtc, plane->fb,
+	return plane->funcs->update_plane(plane, plane->crtc, plane->state->fb,
 				  plane->state->crtc_x, plane->state->crtc_y,
 				  plane->state->crtc_w, plane->state->crtc_h,
 				  plane->state->src_x, plane->state->src_y,
-- 
2.0.5

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Re: [PATCH 3/9] drm/i915: Use plane->state->fb instead of plane->fb in intel_plane_restore()

[Matt Roper]

On Tue, Mar 10, 2015 at 01:15:23PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> plane->fb is not as reliable as plane->state->fb so let's convert
> intel_plane_restore() over the the new way of thinking as well.
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_sprite.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 7051da7..a828736 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1361,10 +1361,10 @@ out_unlock:
>  
>  int intel_plane_restore(struct drm_plane *plane)
>  {
> -	if (!plane->crtc || !plane->fb)
> +	if (!plane->crtc || !plane->state->fb)
>  		return 0;
>  
> -	return plane->funcs->update_plane(plane, plane->crtc, plane->fb,
> +	return plane->funcs->update_plane(plane, plane->crtc, plane->state->fb,

While we're at it, should we s/plane->crtc/plane->state->crtc/ as well?

Otherwise, 1-3 are

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

>  				  plane->state->crtc_x, plane->state->crtc_y,
>  				  plane->state->crtc_w, plane->state->crtc_h,
>  				  plane->state->src_x, plane->state->src_y,
> -- 
> 2.0.5
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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Re: [PATCH 3/9] drm/i915: Use plane->state->fb instead of plane->fb in intel_plane_restore()

[Ville Syrjälä]

On Tue, Mar 10, 2015 at 10:01:47AM -0700, Matt Roper wrote:
> On Tue, Mar 10, 2015 at 01:15:23PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > plane->fb is not as reliable as plane->state->fb so let's convert
> > intel_plane_restore() over the the new way of thinking as well.
> > 
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_sprite.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > index 7051da7..a828736 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -1361,10 +1361,10 @@ out_unlock:
> >  
> >  int intel_plane_restore(struct drm_plane *plane)
> >  {
> > -	if (!plane->crtc || !plane->fb)
> > +	if (!plane->crtc || !plane->state->fb)
> >  		return 0;
> >  
> > -	return plane->funcs->update_plane(plane, plane->crtc, plane->fb,
> > +	return plane->funcs->update_plane(plane, plane->crtc, plane->state->fb,
> 
> While we're at it, should we s/plane->crtc/plane->state->crtc/ as well?

I tried to make that change everywhere and it blew up. But I think that
was simply because I changed it some .commit hook as well, and currently
we don't have the old state around there, so the 'crtc ? crtc : state->crtc'
just ended up as 'crtc' effectively and that of course didn't work as well
as I'd hoped ;)

But yeah maybe we should make that change. Would just need to pass the
old state to commit instead of the new state, I think.

> 
> Otherwise, 1-3 are
> 
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> 
> >  				  plane->state->crtc_x, plane->state->crtc_y,
> >  				  plane->state->crtc_w, plane->state->crtc_h,
> >  				  plane->state->src_x, plane->state->src_y,
> > -- 
> > 2.0.5
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795

-- 
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Re: [PATCH 3/9] drm/i915: Use plane->state->fb instead of plane->fb in intel_plane_restore()

[Daniel Vetter]

On Tue, Mar 10, 2015 at 07:48:39PM +0200, Ville Syrjälä wrote:
> On Tue, Mar 10, 2015 at 10:01:47AM -0700, Matt Roper wrote:
> > On Tue, Mar 10, 2015 at 01:15:23PM +0200, ville.syrjala@linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > plane->fb is not as reliable as plane->state->fb so let's convert
> > > intel_plane_restore() over the the new way of thinking as well.
> > > 
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_sprite.c | 4 ++--
> > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > > index 7051da7..a828736 100644
> > > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > > @@ -1361,10 +1361,10 @@ out_unlock:
> > >  
> > >  int intel_plane_restore(struct drm_plane *plane)
> > >  {
> > > -	if (!plane->crtc || !plane->fb)
> > > +	if (!plane->crtc || !plane->state->fb)
> > >  		return 0;
> > >  
> > > -	return plane->funcs->update_plane(plane, plane->crtc, plane->fb,
> > > +	return plane->funcs->update_plane(plane, plane->crtc, plane->state->fb,
> > 
> > While we're at it, should we s/plane->crtc/plane->state->crtc/ as well?
> 
> I tried to make that change everywhere and it blew up. But I think that
> was simply because I changed it some .commit hook as well, and currently
> we don't have the old state around there, so the 'crtc ? crtc : state->crtc'
> just ended up as 'crtc' effectively and that of course didn't work as well
> as I'd hoped ;)
> 
> But yeah maybe we should make that change. Would just need to pass the
> old state to commit instead of the new state, I think.

Not sure we should be too agressive with mass-conversion. E.g. for the
plane restore I expect that we'll do some overall atomic helper to
snapshot/restore all the state for suspend/resume and similar cases.
-Daniel
> 
> > 
> > Otherwise, 1-3 are
> > 
> > Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> > 
> > >  				  plane->state->crtc_x, plane->state->crtc_y,
> > >  				  plane->state->crtc_w, plane->state->crtc_h,
> > >  				  plane->state->src_x, plane->state->src_y,
> > > -- 
> > > 2.0.5
> > > 
> > 
> > -- 
> > Matt Roper
> > Graphics Software Engineer
> > IoTG Platform Enabling & Development
> > Intel Corporation
> > (916) 356-2795
> 
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [PATCH 3/9] drm/i915: Use plane->state->fb instead of plane->fb in intel_plane_restore()

[Daniel Vetter]

On Wed, Mar 11, 2015 at 10:41:30AM +0100, Daniel Vetter wrote:
> On Tue, Mar 10, 2015 at 07:48:39PM +0200, Ville Syrjälä wrote:
> > On Tue, Mar 10, 2015 at 10:01:47AM -0700, Matt Roper wrote:
> > > On Tue, Mar 10, 2015 at 01:15:23PM +0200, ville.syrjala@linux.intel.com wrote:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > 
> > > > plane->fb is not as reliable as plane->state->fb so let's convert
> > > > intel_plane_restore() over the the new way of thinking as well.
> > > > 
> > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_sprite.c | 4 ++--
> > > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > > > index 7051da7..a828736 100644
> > > > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > > > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > > > @@ -1361,10 +1361,10 @@ out_unlock:
> > > >  
> > > >  int intel_plane_restore(struct drm_plane *plane)
> > > >  {
> > > > -	if (!plane->crtc || !plane->fb)
> > > > +	if (!plane->crtc || !plane->state->fb)
> > > >  		return 0;
> > > >  
> > > > -	return plane->funcs->update_plane(plane, plane->crtc, plane->fb,
> > > > +	return plane->funcs->update_plane(plane, plane->crtc, plane->state->fb,
> > > 
> > > While we're at it, should we s/plane->crtc/plane->state->crtc/ as well?
> > 
> > I tried to make that change everywhere and it blew up. But I think that
> > was simply because I changed it some .commit hook as well, and currently
> > we don't have the old state around there, so the 'crtc ? crtc : state->crtc'
> > just ended up as 'crtc' effectively and that of course didn't work as well
> > as I'd hoped ;)
> > 
> > But yeah maybe we should make that change. Would just need to pass the
> > old state to commit instead of the new state, I think.
> 
> Not sure we should be too agressive with mass-conversion. E.g. for the
> plane restore I expect that we'll do some overall atomic helper to
> snapshot/restore all the state for suspend/resume and similar cases.
> -Daniel
> > 
> > > 
> > > Otherwise, 1-3 are
> > > 
> > > Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

Oh and: Merged first three, thanks for review&patches.
-Daniel
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[PATCH 4/9] drm/i915: Make derived plane state correct after crtc_enable

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We need to call the plane .atomic_check() hook when enabling the crtc
to make sure all the derived state (eg. visible, clipped src/dst
coordinates) are up to date when we enable the plane. This allows us to
trust this derived state everywhere.

We also take the opportunity to rewrite the plane enable sequence to
perform it as a single atomic update, which is a bit closer to where we
want to end up. Obviously this is a bit of a hack as we can't deal with
errors from .atomic_check(), so we just paper over that by making sure
visible=false so that we don't try to enable the plane with potentially
garbage coordinates and whatnot.

We also abuse the atomic code a bit by not making another copy of the
plane state and just frobbing directly with the plane->state.

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |   3 +
 drivers/gpu/drm/i915/intel_display.c | 222 ++++++++++++++---------------------
 2 files changed, 88 insertions(+), 137 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5462cbf..b16c0a7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -238,6 +238,9 @@ enum hpd_pin {
 #define for_each_intel_crtc(dev, intel_crtc) \
 	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
 
+#define for_each_intel_plane(dev, intel_plane) \
+	list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
+
 #define for_each_intel_encoder(dev, intel_encoder)		\
 	list_for_each_entry(intel_encoder,			\
 			    &(dev)->mode_config.encoder_list,	\
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0da3abf..fdc83f1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2124,66 +2124,6 @@ void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
 	POSTING_READ(reg);
 }
 
-/**
- * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
- * @plane:  plane to be enabled
- * @crtc: crtc for the plane
- *
- * Enable @plane on @crtc, making sure that the pipe is running first.
- */
-static void intel_enable_primary_hw_plane(struct drm_plane *plane,
-					  struct drm_crtc *crtc)
-{
-	struct drm_device *dev = plane->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
-	/* If the pipe isn't enabled, we can't pump pixels and may hang */
-	assert_pipe_enabled(dev_priv, intel_crtc->pipe);
-
-	if (intel_crtc->primary_enabled)
-		return;
-
-	intel_crtc->primary_enabled = true;
-
-	dev_priv->display.update_primary_plane(crtc, plane->fb,
-					       crtc->x, crtc->y);
-
-	/*
-	 * BDW signals flip done immediately if the plane
-	 * is disabled, even if the plane enable is already
-	 * armed to occur at the next vblank :(
-	 */
-	if (IS_BROADWELL(dev))
-		intel_wait_for_vblank(dev, intel_crtc->pipe);
-}
-
-/**
- * intel_disable_primary_hw_plane - disable the primary hardware plane
- * @plane: plane to be disabled
- * @crtc: crtc for the plane
- *
- * Disable @plane on @crtc, making sure that the pipe is running first.
- */
-static void intel_disable_primary_hw_plane(struct drm_plane *plane,
-					   struct drm_crtc *crtc)
-{
-	struct drm_device *dev = plane->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
-	if (WARN_ON(!intel_crtc->active))
-		return;
-
-	if (!intel_crtc->primary_enabled)
-		return;
-
-	intel_crtc->primary_enabled = false;
-
-	dev_priv->display.update_primary_plane(crtc, plane->fb,
-					       crtc->x, crtc->y);
-}
-
 static bool need_vtd_wa(struct drm_device *dev)
 {
 #ifdef CONFIG_INTEL_IOMMU
@@ -2895,7 +2835,10 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
 	POSTING_READ(PLANE_SURF(pipe, 0));
 }
 
-/* Assume fb object is pinned & idle & fenced and just update base pointers */
+/*
+ * Assume fb object is big enough & pinned & idle & fenced,
+ * and just update base pointers
+ */
 static int
 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 			   int x, int y, enum mode_set_atomic state)
@@ -2906,6 +2849,7 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 	if (dev_priv->display.disable_fbc)
 		dev_priv->display.disable_fbc(dev);
 
+	to_intel_crtc(crtc)->primary_enabled = true;
 	dev_priv->display.update_primary_plane(crtc, fb, x, y);
 
 	return 0;
@@ -2933,16 +2877,17 @@ static void intel_update_primary_planes(struct drm_device *dev)
 		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 
 		drm_modeset_lock(&crtc->mutex, NULL);
-		/*
-		 * FIXME: Once we have proper support for primary planes (and
-		 * disabling them without disabling the entire crtc) allow again
-		 * a NULL crtc->primary->fb.
-		 */
-		if (intel_crtc->active && crtc->primary->fb)
+
+		if (intel_crtc->active) {
+			const struct intel_plane_state *state =
+				to_intel_plane_state(crtc->primary->state);
+
 			dev_priv->display.update_primary_plane(crtc,
-							       crtc->primary->fb,
-							       crtc->x,
-							       crtc->y);
+							       state->base.fb,
+							       state->src.x1 >> 16,
+							       state->src.y1 >> 16);
+		}
+
 		drm_modeset_unlock(&crtc->mutex);
 	}
 }
@@ -4183,50 +4128,76 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc)
 	}
 }
 
-static void intel_enable_sprite_planes(struct drm_crtc *crtc)
-{
-	struct drm_device *dev = crtc->dev;
-	enum pipe pipe = to_intel_crtc(crtc)->pipe;
-	struct drm_plane *plane;
-	struct intel_plane *intel_plane;
-
-	drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
-		intel_plane = to_intel_plane(plane);
-		if (intel_plane->pipe == pipe)
-			intel_plane_restore(&intel_plane->base);
-	}
-}
-
 /*
- * Disable a plane internally without actually modifying the plane's state.
- * This will allow us to easily restore the plane later by just reprogramming
- * its state.
+ * Ugly hack to make sure we update the planes correctly
  */
-static void disable_plane_internal(struct drm_plane *plane)
+static void _intel_crtc_enable_planes(struct intel_crtc *crtc)
 {
-	struct intel_plane *intel_plane = to_intel_plane(plane);
-	struct drm_plane_state *state =
-		plane->funcs->atomic_duplicate_state(plane);
-	struct intel_plane_state *intel_state = to_intel_plane_state(state);
+	struct drm_device *dev = crtc->base.dev;
+	enum pipe pipe = crtc->pipe;
+	struct intel_plane *plane;
+	const struct drm_crtc_helper_funcs *crtc_funcs =
+		crtc->base.helper_private;
 
-	intel_state->visible = false;
-	intel_plane->commit_plane(plane, intel_state);
+	for_each_intel_plane(dev, plane) {
+		const struct drm_plane_helper_funcs *funcs =
+			plane->base.helper_private;
+		struct intel_plane_state *state =
+			to_intel_plane_state(plane->base.state);
 
-	intel_plane_destroy_state(plane, state);
+		if (plane->pipe != pipe)
+			continue;
+
+		if (funcs->atomic_check(&plane->base, &state->base))
+			state->visible = false;
+	}
+
+	crtc_funcs->atomic_begin(&crtc->base);
+
+	for_each_intel_plane(dev, plane) {
+		const struct drm_plane_helper_funcs *funcs =
+			plane->base.helper_private;
+
+		if (plane->pipe != pipe)
+			continue;
+
+		funcs->atomic_update(&plane->base, plane->base.state);
+	}
+
+	crtc_funcs->atomic_flush(&crtc->base);
 }
 
-static void intel_disable_sprite_planes(struct drm_crtc *crtc)
+static void _intel_crtc_disable_planes(struct intel_crtc *crtc)
 {
-	struct drm_device *dev = crtc->dev;
-	enum pipe pipe = to_intel_crtc(crtc)->pipe;
-	struct drm_plane *plane;
-	struct intel_plane *intel_plane;
-
-	drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
-		intel_plane = to_intel_plane(plane);
-		if (plane->fb && intel_plane->pipe == pipe)
-			disable_plane_internal(plane);
+	struct drm_device *dev = crtc->base.dev;
+	enum pipe pipe = crtc->pipe;
+	struct intel_plane *plane;
+	const struct drm_crtc_helper_funcs *crtc_funcs =
+		crtc->base.helper_private;
+
+	for_each_intel_plane(dev, plane) {
+		struct intel_plane_state *state =
+			to_intel_plane_state(plane->base.state);
+
+		if (plane->pipe != pipe)
+			continue;
+
+		state->visible = false;
 	}
+
+	crtc_funcs->atomic_begin(&crtc->base);
+
+	for_each_intel_plane(dev, plane) {
+		const struct drm_plane_helper_funcs *funcs =
+			plane->base.helper_private;
+
+		if (plane->pipe != pipe)
+			continue;
+
+		funcs->atomic_update(&plane->base, plane->base.state);
+	}
+
+	crtc_funcs->atomic_flush(&crtc->base);
 }
 
 void hsw_enable_ips(struct intel_crtc *crtc)
@@ -4358,9 +4329,7 @@ static void intel_crtc_enable_planes(struct drm_crtc *crtc)
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 
-	intel_enable_primary_hw_plane(crtc->primary, crtc);
-	intel_enable_sprite_planes(crtc);
-	intel_crtc_update_cursor(crtc, true);
+	_intel_crtc_enable_planes(intel_crtc);
 	intel_crtc_dpms_overlay(intel_crtc, true);
 
 	hsw_enable_ips(intel_crtc);
@@ -4392,9 +4361,7 @@ static void intel_crtc_disable_planes(struct drm_crtc *crtc)
 	hsw_disable_ips(intel_crtc);
 
 	intel_crtc_dpms_overlay(intel_crtc, false);
-	intel_crtc_update_cursor(crtc, false);
-	intel_disable_sprite_planes(crtc);
-	intel_disable_primary_hw_plane(crtc->primary, crtc);
+	_intel_crtc_disable_planes(intel_crtc);
 
 	/*
 	 * FIXME: Once we grow proper nuclear flip support out of this we need
@@ -11708,7 +11675,6 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
 					   modeset_pipes, prepare_pipes,
 					   disable_pipes);
 	} else if (config->fb_changed) {
-		struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
 		struct drm_plane *primary = set->crtc->primary;
 		int vdisplay, hdisplay;
 
@@ -11719,15 +11685,6 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
 						   hdisplay << 16, vdisplay << 16);
 
 		/*
-		 * We need to make sure the primary plane is re-enabled if it
-		 * has previously been turned off.
-		 */
-		if (!intel_crtc->primary_enabled && ret == 0) {
-			WARN_ON(!intel_crtc->active);
-			intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
-		}
-
-		/*
 		 * In the fastboot case this may be our only check of the
 		 * state after boot.  It would be better to only do it on
 		 * the first update, but we don't have a nice way of doing that
@@ -12054,24 +12011,15 @@ intel_commit_primary_plane(struct drm_plane *plane,
 	intel_plane->obj = obj;
 
 	if (intel_crtc->active) {
-		if (state->visible) {
-			/* FIXME: kill this fastboot hack */
+		/* FIXME: kill this fastboot hack */
+		if (state->visible)
 			intel_update_pipe_size(intel_crtc);
 
-			intel_crtc->primary_enabled = true;
-
-			dev_priv->display.update_primary_plane(crtc, plane->fb,
-					crtc->x, crtc->y);
-		} else {
-			/*
-			 * If clipping results in a non-visible primary plane,
-			 * we'll disable the primary plane.  Note that this is
-			 * a bit different than what happens if userspace
-			 * explicitly disables the plane by passing fb=0
-			 * because plane->fb still gets set and pinned.
-			 */
-			intel_disable_primary_hw_plane(plane, crtc);
-		}
+		intel_crtc->primary_enabled = state->visible;
+		dev_priv->display.update_primary_plane(crtc,
+						       state->base.fb,
+						       state->src.x1 >> 16,
+						       state->src.y1 >> 16);
 	}
 }
 
-- 
2.0.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 4/9] drm/i915: Make derived plane state correct after crtc_enable

[Matt Roper]

On Tue, Mar 10, 2015 at 01:15:24PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We need to call the plane .atomic_check() hook when enabling the crtc
> to make sure all the derived state (eg. visible, clipped src/dst
> coordinates) are up to date when we enable the plane. This allows us to
> trust this derived state everywhere.
> 
> We also take the opportunity to rewrite the plane enable sequence to
> perform it as a single atomic update, which is a bit closer to where we
> want to end up. Obviously this is a bit of a hack as we can't deal with
> errors from .atomic_check(), so we just paper over that by making sure
> visible=false so that we don't try to enable the plane with potentially
> garbage coordinates and whatnot.
> 
> We also abuse the atomic code a bit by not making another copy of the
> plane state and just frobbing directly with the plane->state.
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Sonika Jindal <sonika.jindal@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h      |   3 +
>  drivers/gpu/drm/i915/intel_display.c | 222 ++++++++++++++---------------------
>  2 files changed, 88 insertions(+), 137 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5462cbf..b16c0a7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -238,6 +238,9 @@ enum hpd_pin {
>  #define for_each_intel_crtc(dev, intel_crtc) \
>  	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
>  
> +#define for_each_intel_plane(dev, intel_plane) \
> +	list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
> +
>  #define for_each_intel_encoder(dev, intel_encoder)		\
>  	list_for_each_entry(intel_encoder,			\
>  			    &(dev)->mode_config.encoder_list,	\
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0da3abf..fdc83f1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2124,66 +2124,6 @@ void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
>  	POSTING_READ(reg);
>  }
>  
> -/**
> - * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
> - * @plane:  plane to be enabled
> - * @crtc: crtc for the plane
> - *
> - * Enable @plane on @crtc, making sure that the pipe is running first.
> - */
> -static void intel_enable_primary_hw_plane(struct drm_plane *plane,
> -					  struct drm_crtc *crtc)
> -{
> -	struct drm_device *dev = plane->dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -
> -	/* If the pipe isn't enabled, we can't pump pixels and may hang */
> -	assert_pipe_enabled(dev_priv, intel_crtc->pipe);
> -
> -	if (intel_crtc->primary_enabled)
> -		return;
> -
> -	intel_crtc->primary_enabled = true;
> -
> -	dev_priv->display.update_primary_plane(crtc, plane->fb,
> -					       crtc->x, crtc->y);
> -
> -	/*
> -	 * BDW signals flip done immediately if the plane
> -	 * is disabled, even if the plane enable is already
> -	 * armed to occur at the next vblank :(
> -	 */
> -	if (IS_BROADWELL(dev))
> -		intel_wait_for_vblank(dev, intel_crtc->pipe);
> -}
> -
> -/**
> - * intel_disable_primary_hw_plane - disable the primary hardware plane
> - * @plane: plane to be disabled
> - * @crtc: crtc for the plane
> - *
> - * Disable @plane on @crtc, making sure that the pipe is running first.
> - */
> -static void intel_disable_primary_hw_plane(struct drm_plane *plane,
> -					   struct drm_crtc *crtc)
> -{
> -	struct drm_device *dev = plane->dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -
> -	if (WARN_ON(!intel_crtc->active))
> -		return;
> -
> -	if (!intel_crtc->primary_enabled)
> -		return;
> -
> -	intel_crtc->primary_enabled = false;
> -
> -	dev_priv->display.update_primary_plane(crtc, plane->fb,
> -					       crtc->x, crtc->y);
> -}
> -
>  static bool need_vtd_wa(struct drm_device *dev)
>  {
>  #ifdef CONFIG_INTEL_IOMMU
> @@ -2895,7 +2835,10 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
>  	POSTING_READ(PLANE_SURF(pipe, 0));
>  }
>  
> -/* Assume fb object is pinned & idle & fenced and just update base pointers */
> +/*
> + * Assume fb object is big enough & pinned & idle & fenced,
> + * and just update base pointers
> + */
>  static int
>  intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
>  			   int x, int y, enum mode_set_atomic state)
> @@ -2906,6 +2849,7 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
>  	if (dev_priv->display.disable_fbc)
>  		dev_priv->display.disable_fbc(dev);
>  
> +	to_intel_crtc(crtc)->primary_enabled = true;
>  	dev_priv->display.update_primary_plane(crtc, fb, x, y);
>  
>  	return 0;
> @@ -2933,16 +2877,17 @@ static void intel_update_primary_planes(struct drm_device *dev)
>  		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  
>  		drm_modeset_lock(&crtc->mutex, NULL);
> -		/*
> -		 * FIXME: Once we have proper support for primary planes (and
> -		 * disabling them without disabling the entire crtc) allow again
> -		 * a NULL crtc->primary->fb.
> -		 */
> -		if (intel_crtc->active && crtc->primary->fb)
> +
> +		if (intel_crtc->active) {
> +			const struct intel_plane_state *state =
> +				to_intel_plane_state(crtc->primary->state);
> +
>  			dev_priv->display.update_primary_plane(crtc,
> -							       crtc->primary->fb,
> -							       crtc->x,
> -							       crtc->y);
> +							       state->base.fb,
> +							       state->src.x1 >> 16,
> +							       state->src.y1 >> 16);
> +		}
> +
>  		drm_modeset_unlock(&crtc->mutex);
>  	}
>  }
> @@ -4183,50 +4128,76 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc)
>  	}
>  }
>  
> -static void intel_enable_sprite_planes(struct drm_crtc *crtc)
> -{
> -	struct drm_device *dev = crtc->dev;
> -	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> -	struct drm_plane *plane;
> -	struct intel_plane *intel_plane;
> -
> -	drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
> -		intel_plane = to_intel_plane(plane);
> -		if (intel_plane->pipe == pipe)
> -			intel_plane_restore(&intel_plane->base);
> -	}
> -}
> -
>  /*
> - * Disable a plane internally without actually modifying the plane's state.
> - * This will allow us to easily restore the plane later by just reprogramming
> - * its state.
> + * Ugly hack to make sure we update the planes correctly
>   */
> -static void disable_plane_internal(struct drm_plane *plane)
> +static void _intel_crtc_enable_planes(struct intel_crtc *crtc)
>  {
> -	struct intel_plane *intel_plane = to_intel_plane(plane);
> -	struct drm_plane_state *state =
> -		plane->funcs->atomic_duplicate_state(plane);
> -	struct intel_plane_state *intel_state = to_intel_plane_state(state);
> +	struct drm_device *dev = crtc->base.dev;
> +	enum pipe pipe = crtc->pipe;
> +	struct intel_plane *plane;
> +	const struct drm_crtc_helper_funcs *crtc_funcs =
> +		crtc->base.helper_private;
>  
> -	intel_state->visible = false;
> -	intel_plane->commit_plane(plane, intel_state);
> +	for_each_intel_plane(dev, plane) {
> +		const struct drm_plane_helper_funcs *funcs =
> +			plane->base.helper_private;
> +		struct intel_plane_state *state =
> +			to_intel_plane_state(plane->base.state);
>  
> -	intel_plane_destroy_state(plane, state);
> +		if (plane->pipe != pipe)
> +			continue;
> +
> +		if (funcs->atomic_check(&plane->base, &state->base))

Maybe add a WARN_ON() here?  I'm assuming that this shouldn't really be
possible since if this fails it means we've already previously done a
commit of invalid state on a previous atomic transaction.  But if it
does somehow happen, the WARN will give us a clue why the plane contents
simply didn't show up.

> +			state->visible = false;
> +	}
> +
> +	crtc_funcs->atomic_begin(&crtc->base);
> +
> +	for_each_intel_plane(dev, plane) {
> +		const struct drm_plane_helper_funcs *funcs =
> +			plane->base.helper_private;
> +
> +		if (plane->pipe != pipe)
> +			continue;
> +
> +		funcs->atomic_update(&plane->base, plane->base.state);
> +	}
> +
> +	crtc_funcs->atomic_flush(&crtc->base);
>  }
>  
> -static void intel_disable_sprite_planes(struct drm_crtc *crtc)
> +static void _intel_crtc_disable_planes(struct intel_crtc *crtc)
>  {
> -	struct drm_device *dev = crtc->dev;
> -	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> -	struct drm_plane *plane;
> -	struct intel_plane *intel_plane;
> -
> -	drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
> -		intel_plane = to_intel_plane(plane);
> -		if (plane->fb && intel_plane->pipe == pipe)
> -			disable_plane_internal(plane);
> +	struct drm_device *dev = crtc->base.dev;
> +	enum pipe pipe = crtc->pipe;
> +	struct intel_plane *plane;
> +	const struct drm_crtc_helper_funcs *crtc_funcs =
> +		crtc->base.helper_private;
> +
> +	for_each_intel_plane(dev, plane) {
> +		struct intel_plane_state *state =
> +			to_intel_plane_state(plane->base.state);
> +
> +		if (plane->pipe != pipe)
> +			continue;
> +
> +		state->visible = false;
>  	}

I'm not super familiar with the current locking situation of our legacy
modeset paths; is it possible for us to race this with another plane
update or are we already holding locks from somewhere higher in the
callstack?  If it's possible for another thread to swap in a new
plane->state right here then we're not really committing what we thought
we were (and plane->state->visible may be true).


Matt

> +
> +	crtc_funcs->atomic_begin(&crtc->base);
> +
> +	for_each_intel_plane(dev, plane) {
> +		const struct drm_plane_helper_funcs *funcs =
> +			plane->base.helper_private;
> +
> +		if (plane->pipe != pipe)
> +			continue;
> +
> +		funcs->atomic_update(&plane->base, plane->base.state);
> +	}
> +
> +	crtc_funcs->atomic_flush(&crtc->base);
>  }
>  
>  void hsw_enable_ips(struct intel_crtc *crtc)
> @@ -4358,9 +4329,7 @@ static void intel_crtc_enable_planes(struct drm_crtc *crtc)
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	int pipe = intel_crtc->pipe;
>  
> -	intel_enable_primary_hw_plane(crtc->primary, crtc);
> -	intel_enable_sprite_planes(crtc);
> -	intel_crtc_update_cursor(crtc, true);
> +	_intel_crtc_enable_planes(intel_crtc);
>  	intel_crtc_dpms_overlay(intel_crtc, true);
>  
>  	hsw_enable_ips(intel_crtc);
> @@ -4392,9 +4361,7 @@ static void intel_crtc_disable_planes(struct drm_crtc *crtc)
>  	hsw_disable_ips(intel_crtc);
>  
>  	intel_crtc_dpms_overlay(intel_crtc, false);
> -	intel_crtc_update_cursor(crtc, false);
> -	intel_disable_sprite_planes(crtc);
> -	intel_disable_primary_hw_plane(crtc->primary, crtc);
> +	_intel_crtc_disable_planes(intel_crtc);
>  
>  	/*
>  	 * FIXME: Once we grow proper nuclear flip support out of this we need
> @@ -11708,7 +11675,6 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
>  					   modeset_pipes, prepare_pipes,
>  					   disable_pipes);
>  	} else if (config->fb_changed) {
> -		struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
>  		struct drm_plane *primary = set->crtc->primary;
>  		int vdisplay, hdisplay;
>  
> @@ -11719,15 +11685,6 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
>  						   hdisplay << 16, vdisplay << 16);
>  
>  		/*
> -		 * We need to make sure the primary plane is re-enabled if it
> -		 * has previously been turned off.
> -		 */
> -		if (!intel_crtc->primary_enabled && ret == 0) {
> -			WARN_ON(!intel_crtc->active);
> -			intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
> -		}
> -
> -		/*
>  		 * In the fastboot case this may be our only check of the
>  		 * state after boot.  It would be better to only do it on
>  		 * the first update, but we don't have a nice way of doing that
> @@ -12054,24 +12011,15 @@ intel_commit_primary_plane(struct drm_plane *plane,
>  	intel_plane->obj = obj;
>  
>  	if (intel_crtc->active) {
> -		if (state->visible) {
> -			/* FIXME: kill this fastboot hack */
> +		/* FIXME: kill this fastboot hack */
> +		if (state->visible)
>  			intel_update_pipe_size(intel_crtc);
>  
> -			intel_crtc->primary_enabled = true;
> -
> -			dev_priv->display.update_primary_plane(crtc, plane->fb,
> -					crtc->x, crtc->y);
> -		} else {
> -			/*
> -			 * If clipping results in a non-visible primary plane,
> -			 * we'll disable the primary plane.  Note that this is
> -			 * a bit different than what happens if userspace
> -			 * explicitly disables the plane by passing fb=0
> -			 * because plane->fb still gets set and pinned.
> -			 */
> -			intel_disable_primary_hw_plane(plane, crtc);
> -		}
> +		intel_crtc->primary_enabled = state->visible;
> +		dev_priv->display.update_primary_plane(crtc,
> +						       state->base.fb,
> +						       state->src.x1 >> 16,
> +						       state->src.y1 >> 16);
>  	}
>  }
>  
> -- 
> 2.0.5
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 4/9] drm/i915: Make derived plane state correct after crtc_enable

[Ville Syrjälä]

On Tue, Mar 10, 2015 at 10:01:51AM -0700, Matt Roper wrote:
> On Tue, Mar 10, 2015 at 01:15:24PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > We need to call the plane .atomic_check() hook when enabling the crtc
> > to make sure all the derived state (eg. visible, clipped src/dst
> > coordinates) are up to date when we enable the plane. This allows us to
> > trust this derived state everywhere.
> > 
> > We also take the opportunity to rewrite the plane enable sequence to
> > perform it as a single atomic update, which is a bit closer to where we
> > want to end up. Obviously this is a bit of a hack as we can't deal with
> > errors from .atomic_check(), so we just paper over that by making sure
> > visible=false so that we don't try to enable the plane with potentially
> > garbage coordinates and whatnot.
> > 
> > We also abuse the atomic code a bit by not making another copy of the
> > plane state and just frobbing directly with the plane->state.
> > 
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Sonika Jindal <sonika.jindal@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h      |   3 +
> >  drivers/gpu/drm/i915/intel_display.c | 222 ++++++++++++++---------------------
> >  2 files changed, 88 insertions(+), 137 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 5462cbf..b16c0a7 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -238,6 +238,9 @@ enum hpd_pin {
> >  #define for_each_intel_crtc(dev, intel_crtc) \
> >  	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
> >  
> > +#define for_each_intel_plane(dev, intel_plane) \
> > +	list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
> > +
> >  #define for_each_intel_encoder(dev, intel_encoder)		\
> >  	list_for_each_entry(intel_encoder,			\
> >  			    &(dev)->mode_config.encoder_list,	\
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 0da3abf..fdc83f1 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -2124,66 +2124,6 @@ void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
> >  	POSTING_READ(reg);
> >  }
> >  
> > -/**
> > - * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
> > - * @plane:  plane to be enabled
> > - * @crtc: crtc for the plane
> > - *
> > - * Enable @plane on @crtc, making sure that the pipe is running first.
> > - */
> > -static void intel_enable_primary_hw_plane(struct drm_plane *plane,
> > -					  struct drm_crtc *crtc)
> > -{
> > -	struct drm_device *dev = plane->dev;
> > -	struct drm_i915_private *dev_priv = dev->dev_private;
> > -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > -
> > -	/* If the pipe isn't enabled, we can't pump pixels and may hang */
> > -	assert_pipe_enabled(dev_priv, intel_crtc->pipe);
> > -
> > -	if (intel_crtc->primary_enabled)
> > -		return;
> > -
> > -	intel_crtc->primary_enabled = true;
> > -
> > -	dev_priv->display.update_primary_plane(crtc, plane->fb,
> > -					       crtc->x, crtc->y);
> > -
> > -	/*
> > -	 * BDW signals flip done immediately if the plane
> > -	 * is disabled, even if the plane enable is already
> > -	 * armed to occur at the next vblank :(
> > -	 */
> > -	if (IS_BROADWELL(dev))
> > -		intel_wait_for_vblank(dev, intel_crtc->pipe);
> > -}
> > -
> > -/**
> > - * intel_disable_primary_hw_plane - disable the primary hardware plane
> > - * @plane: plane to be disabled
> > - * @crtc: crtc for the plane
> > - *
> > - * Disable @plane on @crtc, making sure that the pipe is running first.
> > - */
> > -static void intel_disable_primary_hw_plane(struct drm_plane *plane,
> > -					   struct drm_crtc *crtc)
> > -{
> > -	struct drm_device *dev = plane->dev;
> > -	struct drm_i915_private *dev_priv = dev->dev_private;
> > -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > -
> > -	if (WARN_ON(!intel_crtc->active))
> > -		return;
> > -
> > -	if (!intel_crtc->primary_enabled)
> > -		return;
> > -
> > -	intel_crtc->primary_enabled = false;
> > -
> > -	dev_priv->display.update_primary_plane(crtc, plane->fb,
> > -					       crtc->x, crtc->y);
> > -}
> > -
> >  static bool need_vtd_wa(struct drm_device *dev)
> >  {
> >  #ifdef CONFIG_INTEL_IOMMU
> > @@ -2895,7 +2835,10 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
> >  	POSTING_READ(PLANE_SURF(pipe, 0));
> >  }
> >  
> > -/* Assume fb object is pinned & idle & fenced and just update base pointers */
> > +/*
> > + * Assume fb object is big enough & pinned & idle & fenced,
> > + * and just update base pointers
> > + */
> >  static int
> >  intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
> >  			   int x, int y, enum mode_set_atomic state)
> > @@ -2906,6 +2849,7 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
> >  	if (dev_priv->display.disable_fbc)
> >  		dev_priv->display.disable_fbc(dev);
> >  
> > +	to_intel_crtc(crtc)->primary_enabled = true;
> >  	dev_priv->display.update_primary_plane(crtc, fb, x, y);
> >  
> >  	return 0;
> > @@ -2933,16 +2877,17 @@ static void intel_update_primary_planes(struct drm_device *dev)
> >  		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> >  
> >  		drm_modeset_lock(&crtc->mutex, NULL);
> > -		/*
> > -		 * FIXME: Once we have proper support for primary planes (and
> > -		 * disabling them without disabling the entire crtc) allow again
> > -		 * a NULL crtc->primary->fb.
> > -		 */
> > -		if (intel_crtc->active && crtc->primary->fb)
> > +
> > +		if (intel_crtc->active) {
> > +			const struct intel_plane_state *state =
> > +				to_intel_plane_state(crtc->primary->state);
> > +
> >  			dev_priv->display.update_primary_plane(crtc,
> > -							       crtc->primary->fb,
> > -							       crtc->x,
> > -							       crtc->y);
> > +							       state->base.fb,
> > +							       state->src.x1 >> 16,
> > +							       state->src.y1 >> 16);
> > +		}
> > +
> >  		drm_modeset_unlock(&crtc->mutex);
> >  	}
> >  }
> > @@ -4183,50 +4128,76 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc)
> >  	}
> >  }
> >  
> > -static void intel_enable_sprite_planes(struct drm_crtc *crtc)
> > -{
> > -	struct drm_device *dev = crtc->dev;
> > -	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> > -	struct drm_plane *plane;
> > -	struct intel_plane *intel_plane;
> > -
> > -	drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
> > -		intel_plane = to_intel_plane(plane);
> > -		if (intel_plane->pipe == pipe)
> > -			intel_plane_restore(&intel_plane->base);
> > -	}
> > -}
> > -
> >  /*
> > - * Disable a plane internally without actually modifying the plane's state.
> > - * This will allow us to easily restore the plane later by just reprogramming
> > - * its state.
> > + * Ugly hack to make sure we update the planes correctly
> >   */
> > -static void disable_plane_internal(struct drm_plane *plane)
> > +static void _intel_crtc_enable_planes(struct intel_crtc *crtc)
> >  {
> > -	struct intel_plane *intel_plane = to_intel_plane(plane);
> > -	struct drm_plane_state *state =
> > -		plane->funcs->atomic_duplicate_state(plane);
> > -	struct intel_plane_state *intel_state = to_intel_plane_state(state);
> > +	struct drm_device *dev = crtc->base.dev;
> > +	enum pipe pipe = crtc->pipe;
> > +	struct intel_plane *plane;
> > +	const struct drm_crtc_helper_funcs *crtc_funcs =
> > +		crtc->base.helper_private;
> >  
> > -	intel_state->visible = false;
> > -	intel_plane->commit_plane(plane, intel_state);
> > +	for_each_intel_plane(dev, plane) {
> > +		const struct drm_plane_helper_funcs *funcs =
> > +			plane->base.helper_private;
> > +		struct intel_plane_state *state =
> > +			to_intel_plane_state(plane->base.state);
> >  
> > -	intel_plane_destroy_state(plane, state);
> > +		if (plane->pipe != pipe)
> > +			continue;
> > +
> > +		if (funcs->atomic_check(&plane->base, &state->base))
> 
> Maybe add a WARN_ON() here?  I'm assuming that this shouldn't really be
> possible since if this fails it means we've already previously done a
> commit of invalid state on a previous atomic transaction.  But if it
> does somehow happen, the WARN will give us a clue why the plane contents
> simply didn't show up.

I can think of one way to make it fail. That is, first set a smaller
mode with the primary plane (and fb) configured to cover that fully, and
then switch to a larger mode without reconfiguring the primary plane. If
the hardware requires the primary plane to be fullscreen it'll fail. But
that should actaully not be possible using the legacy modeset API as it
always reconfigures the primary, so we'd only have to worry about that
with full atomic modeset, and for that we anyway need to change the code
to do the check stuff up front.

So yeah, with the way things are this should not be able to fail. I'll
respin with the WARN.

> > +			state->visible = false;
> > +	}
> > +
> > +	crtc_funcs->atomic_begin(&crtc->base);
> > +
> > +	for_each_intel_plane(dev, plane) {
> > +		const struct drm_plane_helper_funcs *funcs =
> > +			plane->base.helper_private;
> > +
> > +		if (plane->pipe != pipe)
> > +			continue;
> > +
> > +		funcs->atomic_update(&plane->base, plane->base.state);
> > +	}
> > +
> > +	crtc_funcs->atomic_flush(&crtc->base);
> >  }
> >  
> > -static void intel_disable_sprite_planes(struct drm_crtc *crtc)
> > +static void _intel_crtc_disable_planes(struct intel_crtc *crtc)
> >  {
> > -	struct drm_device *dev = crtc->dev;
> > -	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> > -	struct drm_plane *plane;
> > -	struct intel_plane *intel_plane;
> > -
> > -	drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
> > -		intel_plane = to_intel_plane(plane);
> > -		if (plane->fb && intel_plane->pipe == pipe)
> > -			disable_plane_internal(plane);
> > +	struct drm_device *dev = crtc->base.dev;
> > +	enum pipe pipe = crtc->pipe;
> > +	struct intel_plane *plane;
> > +	const struct drm_crtc_helper_funcs *crtc_funcs =
> > +		crtc->base.helper_private;
> > +
> > +	for_each_intel_plane(dev, plane) {
> > +		struct intel_plane_state *state =
> > +			to_intel_plane_state(plane->base.state);
> > +
> > +		if (plane->pipe != pipe)
> > +			continue;
> > +
> > +		state->visible = false;
> >  	}
> 
> I'm not super familiar with the current locking situation of our legacy
> modeset paths; is it possible for us to race this with another plane
> update or are we already holding locks from somewhere higher in the
> callstack?  If it's possible for another thread to swap in a new
> plane->state right here then we're not really committing what we thought
> we were (and plane->state->visible may be true).

We should already be holding all the modeset locks if we're this deep
into the modeset code.

> 
> 
> Matt
> 
> > +
> > +	crtc_funcs->atomic_begin(&crtc->base);
> > +
> > +	for_each_intel_plane(dev, plane) {
> > +		const struct drm_plane_helper_funcs *funcs =
> > +			plane->base.helper_private;
> > +
> > +		if (plane->pipe != pipe)
> > +			continue;
> > +
> > +		funcs->atomic_update(&plane->base, plane->base.state);
> > +	}
> > +
> > +	crtc_funcs->atomic_flush(&crtc->base);
> >  }
> >  
> >  void hsw_enable_ips(struct intel_crtc *crtc)
> > @@ -4358,9 +4329,7 @@ static void intel_crtc_enable_planes(struct drm_crtc *crtc)
> >  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> >  	int pipe = intel_crtc->pipe;
> >  
> > -	intel_enable_primary_hw_plane(crtc->primary, crtc);
> > -	intel_enable_sprite_planes(crtc);
> > -	intel_crtc_update_cursor(crtc, true);
> > +	_intel_crtc_enable_planes(intel_crtc);
> >  	intel_crtc_dpms_overlay(intel_crtc, true);
> >  
> >  	hsw_enable_ips(intel_crtc);
> > @@ -4392,9 +4361,7 @@ static void intel_crtc_disable_planes(struct drm_crtc *crtc)
> >  	hsw_disable_ips(intel_crtc);
> >  
> >  	intel_crtc_dpms_overlay(intel_crtc, false);
> > -	intel_crtc_update_cursor(crtc, false);
> > -	intel_disable_sprite_planes(crtc);
> > -	intel_disable_primary_hw_plane(crtc->primary, crtc);
> > +	_intel_crtc_disable_planes(intel_crtc);
> >  
> >  	/*
> >  	 * FIXME: Once we grow proper nuclear flip support out of this we need
> > @@ -11708,7 +11675,6 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
> >  					   modeset_pipes, prepare_pipes,
> >  					   disable_pipes);
> >  	} else if (config->fb_changed) {
> > -		struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
> >  		struct drm_plane *primary = set->crtc->primary;
> >  		int vdisplay, hdisplay;
> >  
> > @@ -11719,15 +11685,6 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
> >  						   hdisplay << 16, vdisplay << 16);
> >  
> >  		/*
> > -		 * We need to make sure the primary plane is re-enabled if it
> > -		 * has previously been turned off.
> > -		 */
> > -		if (!intel_crtc->primary_enabled && ret == 0) {
> > -			WARN_ON(!intel_crtc->active);
> > -			intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
> > -		}
> > -
> > -		/*
> >  		 * In the fastboot case this may be our only check of the
> >  		 * state after boot.  It would be better to only do it on
> >  		 * the first update, but we don't have a nice way of doing that
> > @@ -12054,24 +12011,15 @@ intel_commit_primary_plane(struct drm_plane *plane,
> >  	intel_plane->obj = obj;
> >  
> >  	if (intel_crtc->active) {
> > -		if (state->visible) {
> > -			/* FIXME: kill this fastboot hack */
> > +		/* FIXME: kill this fastboot hack */
> > +		if (state->visible)
> >  			intel_update_pipe_size(intel_crtc);
> >  
> > -			intel_crtc->primary_enabled = true;
> > -
> > -			dev_priv->display.update_primary_plane(crtc, plane->fb,
> > -					crtc->x, crtc->y);
> > -		} else {
> > -			/*
> > -			 * If clipping results in a non-visible primary plane,
> > -			 * we'll disable the primary plane.  Note that this is
> > -			 * a bit different than what happens if userspace
> > -			 * explicitly disables the plane by passing fb=0
> > -			 * because plane->fb still gets set and pinned.
> > -			 */
> > -			intel_disable_primary_hw_plane(plane, crtc);
> > -		}
> > +		intel_crtc->primary_enabled = state->visible;
> > +		dev_priv->display.update_primary_plane(crtc,
> > +						       state->base.fb,
> > +						       state->src.x1 >> 16,
> > +						       state->src.y1 >> 16);
> >  	}
> >  }
> >  
> > -- 
> > 2.0.5
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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Re: [PATCH 4/9] drm/i915: Make derived plane state correct after crtc_enable

[Daniel Vetter]

On Tue, Mar 10, 2015 at 07:57:13PM +0200, Ville Syrjälä wrote:
> On Tue, Mar 10, 2015 at 10:01:51AM -0700, Matt Roper wrote:
> > On Tue, Mar 10, 2015 at 01:15:24PM +0200, ville.syrjala@linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > -static void disable_plane_internal(struct drm_plane *plane)
> > > +static void _intel_crtc_enable_planes(struct intel_crtc *crtc)
> > >  {
> > > -	struct intel_plane *intel_plane = to_intel_plane(plane);
> > > -	struct drm_plane_state *state =
> > > -		plane->funcs->atomic_duplicate_state(plane);
> > > -	struct intel_plane_state *intel_state = to_intel_plane_state(state);
> > > +	struct drm_device *dev = crtc->base.dev;
> > > +	enum pipe pipe = crtc->pipe;
> > > +	struct intel_plane *plane;
> > > +	const struct drm_crtc_helper_funcs *crtc_funcs =
> > > +		crtc->base.helper_private;
> > >  
> > > -	intel_state->visible = false;
> > > -	intel_plane->commit_plane(plane, intel_state);
> > > +	for_each_intel_plane(dev, plane) {
> > > +		const struct drm_plane_helper_funcs *funcs =
> > > +			plane->base.helper_private;
> > > +		struct intel_plane_state *state =
> > > +			to_intel_plane_state(plane->base.state);
> > >  
> > > -	intel_plane_destroy_state(plane, state);
> > > +		if (plane->pipe != pipe)
> > > +			continue;
> > > +
> > > +		if (funcs->atomic_check(&plane->base, &state->base))
> > 
> > Maybe add a WARN_ON() here?  I'm assuming that this shouldn't really be
> > possible since if this fails it means we've already previously done a
> > commit of invalid state on a previous atomic transaction.  But if it
> > does somehow happen, the WARN will give us a clue why the plane contents
> > simply didn't show up.
> 
> I can think of one way to make it fail. That is, first set a smaller
> mode with the primary plane (and fb) configured to cover that fully, and
> then switch to a larger mode without reconfiguring the primary plane. If
> the hardware requires the primary plane to be fullscreen it'll fail. But
> that should actaully not be possible using the legacy modeset API as it
> always reconfigures the primary, so we'd only have to worry about that
> with full atomic modeset, and for that we anyway need to change the code
> to do the check stuff up front.
> 
> So yeah, with the way things are this should not be able to fail. I'll
> respin with the WARN.

I haven't fully dug into the details here, but a few randome comments:
- While transitioning we're calling the transitional plane helpers, which
  should call the atomic_check stuff for us on the primary plane. If we
  need to call atomic_check on other planes too (why?) then I think that
  should be done as close as possible to where we do that for the primary
  one. Since eventually we need to unbury that call again.

- I don't like frobbing state objects which are committed (i.e. updating
  visible like here), they're supposed to be invariant. With proper atomic
  the way to deal with that is to grab all the required plane states and
  put them into the drm_atomic_state update structure.

- My idea for resolving our current nesting issues with
  enable/disable_planes functions was two parts: a) open-code a hardcoded
  disable-all-planes function by just calling plane disable code
  unconditionally. Iirc there's been patches once somewhere to do that
  split in i915 (maybe I'm dreaming), but this use-case is also why I
  added the atomic_plane_disable hook. b) on restore we just do a normal
  plane commit with the unchanged plane states, they should all still
  work.

btw if we wire up the atomic_disable_plane hook then we can rip out
intel_plane_atomic_update. The "don't disable twice" check is already done
by the helpers in that case.

I'll grab some coffee and see what's all wrong with my ideas here now, but
please bring in critique too ;-)

Cheers, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH 4/9] drm/i915: Make derived plane state correct after crtc_enable

[Daniel Vetter]

On Wed, Mar 11, 2015 at 10:52:29AM +0100, Daniel Vetter wrote:
> On Tue, Mar 10, 2015 at 07:57:13PM +0200, Ville Syrjälä wrote:
> > On Tue, Mar 10, 2015 at 10:01:51AM -0700, Matt Roper wrote:
> > > On Tue, Mar 10, 2015 at 01:15:24PM +0200, ville.syrjala@linux.intel.com wrote:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > -static void disable_plane_internal(struct drm_plane *plane)
> > > > +static void _intel_crtc_enable_planes(struct intel_crtc *crtc)
> > > >  {
> > > > -	struct intel_plane *intel_plane = to_intel_plane(plane);
> > > > -	struct drm_plane_state *state =
> > > > -		plane->funcs->atomic_duplicate_state(plane);
> > > > -	struct intel_plane_state *intel_state = to_intel_plane_state(state);
> > > > +	struct drm_device *dev = crtc->base.dev;
> > > > +	enum pipe pipe = crtc->pipe;
> > > > +	struct intel_plane *plane;
> > > > +	const struct drm_crtc_helper_funcs *crtc_funcs =
> > > > +		crtc->base.helper_private;
> > > >  
> > > > -	intel_state->visible = false;
> > > > -	intel_plane->commit_plane(plane, intel_state);
> > > > +	for_each_intel_plane(dev, plane) {
> > > > +		const struct drm_plane_helper_funcs *funcs =
> > > > +			plane->base.helper_private;
> > > > +		struct intel_plane_state *state =
> > > > +			to_intel_plane_state(plane->base.state);
> > > >  
> > > > -	intel_plane_destroy_state(plane, state);
> > > > +		if (plane->pipe != pipe)
> > > > +			continue;
> > > > +
> > > > +		if (funcs->atomic_check(&plane->base, &state->base))
> > > 
> > > Maybe add a WARN_ON() here?  I'm assuming that this shouldn't really be
> > > possible since if this fails it means we've already previously done a
> > > commit of invalid state on a previous atomic transaction.  But if it
> > > does somehow happen, the WARN will give us a clue why the plane contents
> > > simply didn't show up.
> > 
> > I can think of one way to make it fail. That is, first set a smaller
> > mode with the primary plane (and fb) configured to cover that fully, and
> > then switch to a larger mode without reconfiguring the primary plane. If
> > the hardware requires the primary plane to be fullscreen it'll fail. But
> > that should actaully not be possible using the legacy modeset API as it
> > always reconfigures the primary, so we'd only have to worry about that
> > with full atomic modeset, and for that we anyway need to change the code
> > to do the check stuff up front.
> > 
> > So yeah, with the way things are this should not be able to fail. I'll
> > respin with the WARN.
> 
> I haven't fully dug into the details here, but a few randome comments:
> - While transitioning we're calling the transitional plane helpers, which
>   should call the atomic_check stuff for us on the primary plane. If we
>   need to call atomic_check on other planes too (why?) then I think that
>   should be done as close as possible to where we do that for the primary
>   one. Since eventually we need to unbury that call again.
> 
> - I don't like frobbing state objects which are committed (i.e. updating
>   visible like here), they're supposed to be invariant. With proper atomic
>   the way to deal with that is to grab all the required plane states and
>   put them into the drm_atomic_state update structure.
> 
> - My idea for resolving our current nesting issues with
>   enable/disable_planes functions was two parts: a) open-code a hardcoded
>   disable-all-planes function by just calling plane disable code
>   unconditionally. Iirc there's been patches once somewhere to do that
>   split in i915 (maybe I'm dreaming), but this use-case is also why I
>   added the atomic_plane_disable hook. b) on restore we just do a normal
>   plane commit with the unchanged plane states, they should all still
>   work.
> 
> btw if we wire up the atomic_disable_plane hook then we can rip out
> intel_plane_atomic_update. The "don't disable twice" check is already done
> by the helpers in that case.
> 
> I'll grab some coffee and see what's all wrong with my ideas here now, but
> please bring in critique too ;-)

One immediate problem is that we key off from intel_state->visible to
decide whether to enable or not, and the core helpers key off from
state->fb. So I think we'd need to roll our own, but with the same idea
of splitting out an explicit plane_disable hook.

Or maybe we should add a drm_plane_state->visible derived state which
helpers fill out to match drm_plane_state->fb by default. That might be
even neater, and matches somewhat how we allow drivers to overwrite
crtc_state->needs_modeset to control which hooks the helpers will call.

Clearly, more coffee is neede here ;-)
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH 4/9] drm/i915: Make derived plane state correct after crtc_enable

[Ville Syrjälä]

On Wed, Mar 11, 2015 at 10:52:29AM +0100, Daniel Vetter wrote:
> On Tue, Mar 10, 2015 at 07:57:13PM +0200, Ville Syrjälä wrote:
> > On Tue, Mar 10, 2015 at 10:01:51AM -0700, Matt Roper wrote:
> > > On Tue, Mar 10, 2015 at 01:15:24PM +0200, ville.syrjala@linux.intel.com wrote:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > -static void disable_plane_internal(struct drm_plane *plane)
> > > > +static void _intel_crtc_enable_planes(struct intel_crtc *crtc)
> > > >  {
> > > > -	struct intel_plane *intel_plane = to_intel_plane(plane);
> > > > -	struct drm_plane_state *state =
> > > > -		plane->funcs->atomic_duplicate_state(plane);
> > > > -	struct intel_plane_state *intel_state = to_intel_plane_state(state);
> > > > +	struct drm_device *dev = crtc->base.dev;
> > > > +	enum pipe pipe = crtc->pipe;
> > > > +	struct intel_plane *plane;
> > > > +	const struct drm_crtc_helper_funcs *crtc_funcs =
> > > > +		crtc->base.helper_private;
> > > >  
> > > > -	intel_state->visible = false;
> > > > -	intel_plane->commit_plane(plane, intel_state);
> > > > +	for_each_intel_plane(dev, plane) {
> > > > +		const struct drm_plane_helper_funcs *funcs =
> > > > +			plane->base.helper_private;
> > > > +		struct intel_plane_state *state =
> > > > +			to_intel_plane_state(plane->base.state);
> > > >  
> > > > -	intel_plane_destroy_state(plane, state);
> > > > +		if (plane->pipe != pipe)
> > > > +			continue;
> > > > +
> > > > +		if (funcs->atomic_check(&plane->base, &state->base))
> > > 
> > > Maybe add a WARN_ON() here?  I'm assuming that this shouldn't really be
> > > possible since if this fails it means we've already previously done a
> > > commit of invalid state on a previous atomic transaction.  But if it
> > > does somehow happen, the WARN will give us a clue why the plane contents
> > > simply didn't show up.
> > 
> > I can think of one way to make it fail. That is, first set a smaller
> > mode with the primary plane (and fb) configured to cover that fully, and
> > then switch to a larger mode without reconfiguring the primary plane. If
> > the hardware requires the primary plane to be fullscreen it'll fail. But
> > that should actaully not be possible using the legacy modeset API as it
> > always reconfigures the primary, so we'd only have to worry about that
> > with full atomic modeset, and for that we anyway need to change the code
> > to do the check stuff up front.
> > 
> > So yeah, with the way things are this should not be able to fail. I'll
> > respin with the WARN.
> 
> I haven't fully dug into the details here, but a few randome comments:
> - While transitioning we're calling the transitional plane helpers, which
>   should call the atomic_check stuff for us on the primary plane. If we
>   need to call atomic_check on other planes too (why?)

Because we want the derived state to be updated to match the (potentially
changed) crtc config. We do call the .update_plane() hook from the
modeset path, but that happens at a time when the pipe is off, so our
clipping calculations end up saying the plane is invisible. I think fixing
that the right way pretty much involves the atomic conversion of the
modeset path.

>   then I think that
>   should be done as close as possible to where we do that for the primary
>   one. Since eventually we need to unbury that call again.

With my patch _all_ planes get their .atomic_check() called in the same
place (during plane enable phase of .crtc_enable()).

> 
> - I don't like frobbing state objects which are committed (i.e. updating
>   visible like here), they're supposed to be invariant. With proper atomic
>   the way to deal with that is to grab all the required plane states and
>   put them into the drm_atomic_state update structure.

We really want to frob it so that the derived state will reflect
reality. Most importantly state->visible should be false whenever the
pipe is off, otherwise we can't trust state->visible and would also need
go look at the crtc state whenever we're trying to decide if the plane
is actually on or not.

As for the direct state frobbing, we could make a copy I guess and frob
that instead, and then commit it. But that seems a lot of work for no gain.

> 
> - My idea for resolving our current nesting issues with
>   enable/disable_planes functions was two parts: a) open-code a hardcoded
>   disable-all-planes function by just calling plane disable code
>   unconditionally. Iirc there's been patches once somewhere to do that
>   split in i915 (maybe I'm dreaming), but this use-case is also why I
>   added the atomic_plane_disable hook. b) on restore we just do a normal
>   plane commit with the unchanged plane states, they should all still
>   work.
> 
> btw if we wire up the atomic_disable_plane hook then we can rip out
> intel_plane_atomic_update. The "don't disable twice" check is already done
> by the helpers in that case.
> 
> I'll grab some coffee and see what's all wrong with my ideas here now, but
> please bring in critique too ;-)
> 
> Cheers, Daniel
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 4/9] drm/i915: Make derived plane state correct after crtc_enable

[Daniel Vetter]

On Wed, Mar 11, 2015 at 12:05:39PM +0200, Ville Syrjälä wrote:
> On Wed, Mar 11, 2015 at 10:52:29AM +0100, Daniel Vetter wrote:
> > On Tue, Mar 10, 2015 at 07:57:13PM +0200, Ville Syrjälä wrote:
> > > On Tue, Mar 10, 2015 at 10:01:51AM -0700, Matt Roper wrote:
> > > > On Tue, Mar 10, 2015 at 01:15:24PM +0200, ville.syrjala@linux.intel.com wrote:
> > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > -static void disable_plane_internal(struct drm_plane *plane)
> > > > > +static void _intel_crtc_enable_planes(struct intel_crtc *crtc)
> > > > >  {
> > > > > -	struct intel_plane *intel_plane = to_intel_plane(plane);
> > > > > -	struct drm_plane_state *state =
> > > > > -		plane->funcs->atomic_duplicate_state(plane);
> > > > > -	struct intel_plane_state *intel_state = to_intel_plane_state(state);
> > > > > +	struct drm_device *dev = crtc->base.dev;
> > > > > +	enum pipe pipe = crtc->pipe;
> > > > > +	struct intel_plane *plane;
> > > > > +	const struct drm_crtc_helper_funcs *crtc_funcs =
> > > > > +		crtc->base.helper_private;
> > > > >  
> > > > > -	intel_state->visible = false;
> > > > > -	intel_plane->commit_plane(plane, intel_state);
> > > > > +	for_each_intel_plane(dev, plane) {
> > > > > +		const struct drm_plane_helper_funcs *funcs =
> > > > > +			plane->base.helper_private;
> > > > > +		struct intel_plane_state *state =
> > > > > +			to_intel_plane_state(plane->base.state);
> > > > >  
> > > > > -	intel_plane_destroy_state(plane, state);
> > > > > +		if (plane->pipe != pipe)
> > > > > +			continue;
> > > > > +
> > > > > +		if (funcs->atomic_check(&plane->base, &state->base))
> > > > 
> > > > Maybe add a WARN_ON() here?  I'm assuming that this shouldn't really be
> > > > possible since if this fails it means we've already previously done a
> > > > commit of invalid state on a previous atomic transaction.  But if it
> > > > does somehow happen, the WARN will give us a clue why the plane contents
> > > > simply didn't show up.
> > > 
> > > I can think of one way to make it fail. That is, first set a smaller
> > > mode with the primary plane (and fb) configured to cover that fully, and
> > > then switch to a larger mode without reconfiguring the primary plane. If
> > > the hardware requires the primary plane to be fullscreen it'll fail. But
> > > that should actaully not be possible using the legacy modeset API as it
> > > always reconfigures the primary, so we'd only have to worry about that
> > > with full atomic modeset, and for that we anyway need to change the code
> > > to do the check stuff up front.
> > > 
> > > So yeah, with the way things are this should not be able to fail. I'll
> > > respin with the WARN.
> > 
> > I haven't fully dug into the details here, but a few randome comments:
> > - While transitioning we're calling the transitional plane helpers, which
> >   should call the atomic_check stuff for us on the primary plane. If we
> >   need to call atomic_check on other planes too (why?)
> 
> Because we want the derived state to be updated to match the (potentially
> changed) crtc config. We do call the .update_plane() hook from the
> modeset path, but that happens at a time when the pipe is off, so our
> clipping calculations end up saying the plane is invisible. I think fixing
> that the right way pretty much involves the atomic conversion of the
> modeset path.

Why do we conclude it's invisible? If we can fix the state to not depend
upon the dpms state then things should work ...

> >   then I think that
> >   should be done as close as possible to where we do that for the primary
> >   one. Since eventually we need to unbury that call again.
> 
> With my patch _all_ planes get their .atomic_check() called in the same
> place (during plane enable phase of .crtc_enable()).
> 
> > 
> > - I don't like frobbing state objects which are committed (i.e. updating
> >   visible like here), they're supposed to be invariant. With proper atomic
> >   the way to deal with that is to grab all the required plane states and
> >   put them into the drm_atomic_state update structure.
> 
> We really want to frob it so that the derived state will reflect
> reality. Most importantly state->visible should be false whenever the
> pipe is off, otherwise we can't trust state->visible and would also need
> go look at the crtc state whenever we're trying to decide if the plane
> is actually on or not.

Imo that's the correct thing to do. Calling plane hooks when the pipe is
off just doesn't seem like a good idea to me. Together with runtime pm at
least, crtc/atomic helpers have some "interesting" heritage.

But even there you can fix it by just reordering the commit_planes call to
the bottom, where everything should be on. Iirc that's how Laurent fixed
up rcar runtime pm issues to avoid touching planes when the hw is off.

The other reason why ->visible must take into account dpms state is that
we'll screw up the watermark computation otherwise. Which could result
into a failure on a subsequent dpms on, which is a big no-no.

> As for the direct state frobbing, we could make a copy I guess and frob
> that instead, and then commit it. But that seems a lot of work for no gain.

That's how atomic is supposed to work really. But we can't make a copy in
the crtc_enable really since that should never fail, and we can't push it
out since we might not hold all the locks. That's all ofcourse for the
atomic end-state, but I think even as an interim detour this approach here
doesn't feel like a good approach to me.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH 4/9] drm/i915: Make derived plane state correct after crtc_enable

[Ville Syrjälä]

On Wed, Mar 11, 2015 at 11:24:34AM +0100, Daniel Vetter wrote:
> On Wed, Mar 11, 2015 at 12:05:39PM +0200, Ville Syrjälä wrote:
> > On Wed, Mar 11, 2015 at 10:52:29AM +0100, Daniel Vetter wrote:
> > > On Tue, Mar 10, 2015 at 07:57:13PM +0200, Ville Syrjälä wrote:
> > > > On Tue, Mar 10, 2015 at 10:01:51AM -0700, Matt Roper wrote:
> > > > > On Tue, Mar 10, 2015 at 01:15:24PM +0200, ville.syrjala@linux.intel.com wrote:
> > > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > > -static void disable_plane_internal(struct drm_plane *plane)
> > > > > > +static void _intel_crtc_enable_planes(struct intel_crtc *crtc)
> > > > > >  {
> > > > > > -	struct intel_plane *intel_plane = to_intel_plane(plane);
> > > > > > -	struct drm_plane_state *state =
> > > > > > -		plane->funcs->atomic_duplicate_state(plane);
> > > > > > -	struct intel_plane_state *intel_state = to_intel_plane_state(state);
> > > > > > +	struct drm_device *dev = crtc->base.dev;
> > > > > > +	enum pipe pipe = crtc->pipe;
> > > > > > +	struct intel_plane *plane;
> > > > > > +	const struct drm_crtc_helper_funcs *crtc_funcs =
> > > > > > +		crtc->base.helper_private;
> > > > > >  
> > > > > > -	intel_state->visible = false;
> > > > > > -	intel_plane->commit_plane(plane, intel_state);
> > > > > > +	for_each_intel_plane(dev, plane) {
> > > > > > +		const struct drm_plane_helper_funcs *funcs =
> > > > > > +			plane->base.helper_private;
> > > > > > +		struct intel_plane_state *state =
> > > > > > +			to_intel_plane_state(plane->base.state);
> > > > > >  
> > > > > > -	intel_plane_destroy_state(plane, state);
> > > > > > +		if (plane->pipe != pipe)
> > > > > > +			continue;
> > > > > > +
> > > > > > +		if (funcs->atomic_check(&plane->base, &state->base))
> > > > > 
> > > > > Maybe add a WARN_ON() here?  I'm assuming that this shouldn't really be
> > > > > possible since if this fails it means we've already previously done a
> > > > > commit of invalid state on a previous atomic transaction.  But if it
> > > > > does somehow happen, the WARN will give us a clue why the plane contents
> > > > > simply didn't show up.
> > > > 
> > > > I can think of one way to make it fail. That is, first set a smaller
> > > > mode with the primary plane (and fb) configured to cover that fully, and
> > > > then switch to a larger mode without reconfiguring the primary plane. If
> > > > the hardware requires the primary plane to be fullscreen it'll fail. But
> > > > that should actaully not be possible using the legacy modeset API as it
> > > > always reconfigures the primary, so we'd only have to worry about that
> > > > with full atomic modeset, and for that we anyway need to change the code
> > > > to do the check stuff up front.
> > > > 
> > > > So yeah, with the way things are this should not be able to fail. I'll
> > > > respin with the WARN.
> > > 
> > > I haven't fully dug into the details here, but a few randome comments:
> > > - While transitioning we're calling the transitional plane helpers, which
> > >   should call the atomic_check stuff for us on the primary plane. If we
> > >   need to call atomic_check on other planes too (why?)
> > 
> > Because we want the derived state to be updated to match the (potentially
> > changed) crtc config. We do call the .update_plane() hook from the
> > modeset path, but that happens at a time when the pipe is off, so our
> > clipping calculations end up saying the plane is invisible. I think fixing
> > that the right way pretty much involves the atomic conversion of the
> > modeset path.
> 
> Why do we conclude it's invisible?

Because crtc->active. So for this we'll be wanting crtc_state->active
or somesuch which tells us upfront whether the pipe is going to be
active or not.

But that's also beside the point a bit since we still want to make call
the .atomic_check() for all planes. Right now we'd call it for primary
(at the wrong point wrt. crtc->active) and we call it for sprites later
when crtc->active is showing the right state, but we don't call it at
all for cursors. That's why we still have that ad-hoc extra cursor
clipping code in intel_update_cursor(). If we could make the derived
plane state correct, we could throw that stuff out as well and trust the
regular plane clipping calculations to tell us when the cursor has gone
offscreen.

It'll also make the plane state behave in a consitent manner wrt.
crtc->active. As it stands you simply can't trust the plane state for
primary/cursor planes.

So to fix all of that, I just went ahead and called it for all planes at
the point where we currently call it for sprites. I could have just gone
ahead and called the higher level .update_plane() func for all of them
(as we did for sprites already) but going one level lower allowed me to
get the planes to pop in/out atomically.

I think it's the best way to move forward with getting the plane and wm
code into some kind of sane state.

> If we can fix the state to not depend
> upon the dpms state then things should work ...

That's a more drastic change and needs way more thought.

> 
> > >   then I think that
> > >   should be done as close as possible to where we do that for the primary
> > >   one. Since eventually we need to unbury that call again.
> > 
> > With my patch _all_ planes get their .atomic_check() called in the same
> > place (during plane enable phase of .crtc_enable()).
> > 
> > > 
> > > - I don't like frobbing state objects which are committed (i.e. updating
> > >   visible like here), they're supposed to be invariant. With proper atomic
> > >   the way to deal with that is to grab all the required plane states and
> > >   put them into the drm_atomic_state update structure.
> > 
> > We really want to frob it so that the derived state will reflect
> > reality. Most importantly state->visible should be false whenever the
> > pipe is off, otherwise we can't trust state->visible and would also need
> > go look at the crtc state whenever we're trying to decide if the plane
> > is actually on or not.
> 
> Imo that's the correct thing to do. Calling plane hooks when the pipe is
> off just doesn't seem like a good idea to me. Together with runtime pm at
> least, crtc/atomic helpers have some "interesting" heritage.
> 
> But even there you can fix it by just reordering the commit_planes call to
> the bottom, where everything should be on. Iirc that's how Laurent fixed
> up rcar runtime pm issues to avoid touching planes when the hw is off.
> 
> The other reason why ->visible must take into account dpms state is that
> we'll screw up the watermark computation otherwise. Which could result
> into a failure on a subsequent dpms on, which is a big no-no.

Hmm, right. So for most calculations we'll just want to ignore the
DPMS state and calculate things as if the pipe was active (so only
looking at crtc_state->enabled I suppose). But when it's actually
time to write the values into the hardware we need too consider
the actual state of the pipe as well (so taking DPMS into account).

So yeah, if we decouple plane_state->visible from crtc->active and just
make it check crtc_state->enabled then plane_state->visible can be used
to do all the clipping, and upfront per-pipe wm calculations. But when
it comes time to apply the plane state or watermarks to the hardware we
need to check the actual pipe state.

So good plan, but needs quite a bit of work to get us there.

> 
> > As for the direct state frobbing, we could make a copy I guess and frob
> > that instead, and then commit it. But that seems a lot of work for no gain.
> 
> That's how atomic is supposed to work really. But we can't make a copy in
> the crtc_enable really since that should never fail, and we can't push it
> out since we might not hold all the locks. That's all ofcourse for the
> atomic end-state, but I think even as an interim detour this approach here
> doesn't feel like a good approach to me.

We're going to need the "detour". That is, we do need to call the
.atomic_check() for all planes at modeset time. But trying to do it
earlier will mean changing all the plane visibility calculations to
consider the pipe active whenever crtc_state->enabled==true, and
that's going to require careful review of the code to make sure we
don't trust the plane visibility/clipping information too much. And
the same goes for the watermark code.

So I still think this is the right step to move forward. It'll allow us
to use the derived plane state correctly (and since it still depends on
crtc->active we won't risk enabling planes when the pipe is off), which
allows the plane and wm code to evolve in small steps, rather than some
mass conversion. I think there have been more than enough regressions
recently.

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 4/9] drm/i915: Make derived plane state correct after crtc_enable

[Daniel Vetter]

On Wed, Mar 11, 2015 at 02:19:38PM +0200, Ville Syrjälä wrote:
> On Wed, Mar 11, 2015 at 11:24:34AM +0100, Daniel Vetter wrote:
> > On Wed, Mar 11, 2015 at 12:05:39PM +0200, Ville Syrjälä wrote:
> > > On Wed, Mar 11, 2015 at 10:52:29AM +0100, Daniel Vetter wrote:
> > > > On Tue, Mar 10, 2015 at 07:57:13PM +0200, Ville Syrjälä wrote:
> > > > > On Tue, Mar 10, 2015 at 10:01:51AM -0700, Matt Roper wrote:
> > > > > > On Tue, Mar 10, 2015 at 01:15:24PM +0200, ville.syrjala@linux.intel.com wrote:
> > > > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > > > -static void disable_plane_internal(struct drm_plane *plane)
> > > > > > > +static void _intel_crtc_enable_planes(struct intel_crtc *crtc)
> > > > > > >  {
> > > > > > > -	struct intel_plane *intel_plane = to_intel_plane(plane);
> > > > > > > -	struct drm_plane_state *state =
> > > > > > > -		plane->funcs->atomic_duplicate_state(plane);
> > > > > > > -	struct intel_plane_state *intel_state = to_intel_plane_state(state);
> > > > > > > +	struct drm_device *dev = crtc->base.dev;
> > > > > > > +	enum pipe pipe = crtc->pipe;
> > > > > > > +	struct intel_plane *plane;
> > > > > > > +	const struct drm_crtc_helper_funcs *crtc_funcs =
> > > > > > > +		crtc->base.helper_private;
> > > > > > >  
> > > > > > > -	intel_state->visible = false;
> > > > > > > -	intel_plane->commit_plane(plane, intel_state);
> > > > > > > +	for_each_intel_plane(dev, plane) {
> > > > > > > +		const struct drm_plane_helper_funcs *funcs =
> > > > > > > +			plane->base.helper_private;
> > > > > > > +		struct intel_plane_state *state =
> > > > > > > +			to_intel_plane_state(plane->base.state);
> > > > > > >  
> > > > > > > -	intel_plane_destroy_state(plane, state);
> > > > > > > +		if (plane->pipe != pipe)
> > > > > > > +			continue;
> > > > > > > +
> > > > > > > +		if (funcs->atomic_check(&plane->base, &state->base))
> > > > > > 
> > > > > > Maybe add a WARN_ON() here?  I'm assuming that this shouldn't really be
> > > > > > possible since if this fails it means we've already previously done a
> > > > > > commit of invalid state on a previous atomic transaction.  But if it
> > > > > > does somehow happen, the WARN will give us a clue why the plane contents
> > > > > > simply didn't show up.
> > > > > 
> > > > > I can think of one way to make it fail. That is, first set a smaller
> > > > > mode with the primary plane (and fb) configured to cover that fully, and
> > > > > then switch to a larger mode without reconfiguring the primary plane. If
> > > > > the hardware requires the primary plane to be fullscreen it'll fail. But
> > > > > that should actaully not be possible using the legacy modeset API as it
> > > > > always reconfigures the primary, so we'd only have to worry about that
> > > > > with full atomic modeset, and for that we anyway need to change the code
> > > > > to do the check stuff up front.
> > > > > 
> > > > > So yeah, with the way things are this should not be able to fail. I'll
> > > > > respin with the WARN.
> > > > 
> > > > I haven't fully dug into the details here, but a few randome comments:
> > > > - While transitioning we're calling the transitional plane helpers, which
> > > >   should call the atomic_check stuff for us on the primary plane. If we
> > > >   need to call atomic_check on other planes too (why?)
> > > 
> > > Because we want the derived state to be updated to match the (potentially
> > > changed) crtc config. We do call the .update_plane() hook from the
> > > modeset path, but that happens at a time when the pipe is off, so our
> > > clipping calculations end up saying the plane is invisible. I think fixing
> > > that the right way pretty much involves the atomic conversion of the
> > > modeset path.
> > 
> > Why do we conclude it's invisible?
> 
> Because crtc->active. So for this we'll be wanting crtc_state->active
> or somesuch which tells us upfront whether the pipe is going to be
> active or not.
> 
> But that's also beside the point a bit since we still want to make call
> the .atomic_check() for all planes. Right now we'd call it for primary
> (at the wrong point wrt. crtc->active) and we call it for sprites later
> when crtc->active is showing the right state, but we don't call it at
> all for cursors. That's why we still have that ad-hoc extra cursor
> clipping code in intel_update_cursor(). If we could make the derived
> plane state correct, we could throw that stuff out as well and trust the
> regular plane clipping calculations to tell us when the cursor has gone
> offscreen.
> 
> It'll also make the plane state behave in a consitent manner wrt.
> crtc->active. As it stands you simply can't trust the plane state for
> primary/cursor planes.
> 
> So to fix all of that, I just went ahead and called it for all planes at
> the point where we currently call it for sprites. I could have just gone
> ahead and called the higher level .update_plane() func for all of them
> (as we did for sprites already) but going one level lower allowed me to
> get the planes to pop in/out atomically.
> 
> I think it's the best way to move forward with getting the plane and wm
> code into some kind of sane state.
> 
> > If we can fix the state to not depend
> > upon the dpms state then things should work ...
> 
> That's a more drastic change and needs way more thought.

Yeah, but that's what we need to aim for eventually. So I want to make
sure we're not running into the wrong direction and then have to backtrack
even more.

> > > >   then I think that
> > > >   should be done as close as possible to where we do that for the primary
> > > >   one. Since eventually we need to unbury that call again.
> > > 
> > > With my patch _all_ planes get their .atomic_check() called in the same
> > > place (during plane enable phase of .crtc_enable()).
> > > 
> > > > 
> > > > - I don't like frobbing state objects which are committed (i.e. updating
> > > >   visible like here), they're supposed to be invariant. With proper atomic
> > > >   the way to deal with that is to grab all the required plane states and
> > > >   put them into the drm_atomic_state update structure.
> > > 
> > > We really want to frob it so that the derived state will reflect
> > > reality. Most importantly state->visible should be false whenever the
> > > pipe is off, otherwise we can't trust state->visible and would also need
> > > go look at the crtc state whenever we're trying to decide if the plane
> > > is actually on or not.
> > 
> > Imo that's the correct thing to do. Calling plane hooks when the pipe is
> > off just doesn't seem like a good idea to me. Together with runtime pm at
> > least, crtc/atomic helpers have some "interesting" heritage.
> > 
> > But even there you can fix it by just reordering the commit_planes call to
> > the bottom, where everything should be on. Iirc that's how Laurent fixed
> > up rcar runtime pm issues to avoid touching planes when the hw is off.
> > 
> > The other reason why ->visible must take into account dpms state is that
> > we'll screw up the watermark computation otherwise. Which could result
> > into a failure on a subsequent dpms on, which is a big no-no.
> 
> Hmm, right. So for most calculations we'll just want to ignore the
> DPMS state and calculate things as if the pipe was active (so only
> looking at crtc_state->enabled I suppose). But when it's actually
> time to write the values into the hardware we need too consider
> the actual state of the pipe as well (so taking DPMS into account).
> 
> So yeah, if we decouple plane_state->visible from crtc->active and just
> make it check crtc_state->enabled then plane_state->visible can be used
> to do all the clipping, and upfront per-pipe wm calculations. But when
> it comes time to apply the plane state or watermarks to the hardware we
> need to check the actual pipe state.
> 
> So good plan, but needs quite a bit of work to get us there.
> 
> > > As for the direct state frobbing, we could make a copy I guess and frob
> > > that instead, and then commit it. But that seems a lot of work for no gain.
> > 
> > That's how atomic is supposed to work really. But we can't make a copy in
> > the crtc_enable really since that should never fail, and we can't push it
> > out since we might not hold all the locks. That's all ofcourse for the
> > atomic end-state, but I think even as an interim detour this approach here
> > doesn't feel like a good approach to me.
> 
> We're going to need the "detour". That is, we do need to call the
> .atomic_check() for all planes at modeset time. But trying to do it
> earlier will mean changing all the plane visibility calculations to
> consider the pipe active whenever crtc_state->enabled==true, and
> that's going to require careful review of the code to make sure we
> don't trust the plane visibility/clipping information too much. And
> the same goes for the watermark code.
> 
> So I still think this is the right step to move forward. It'll allow us
> to use the derived plane state correctly (and since it still depends on
> crtc->active we won't risk enabling planes when the pipe is off), which
> allows the plane and wm code to evolve in small steps, rather than some
> mass conversion. I think there have been more than enough regressions
> recently.

Ok, makes sense. It'll mean that there's more steps overall though, which
might lead to more regressions overall, just spread out a bit. And we
definitely need to make sure we unwrap this detour again. As long as
Ander/Matt/you can roughly agree on a plan forward I'll go along with it.

For atomic in the end I think the important bit really from my pov is that
we must not depend in any way upon neither intel_crtc->active nor
crtc_state->active in the watermark computation code. Of course that means
we need to do some untangling to make sure that we can correctly shut down
everything if crtc_state->active isn't set.

Also do we have igt testcases for the regressions this patch series fixes?
atomic is really complex, I think we should fill out gaps as we go along.
So if we have them we need to add them to the list - Daniel Stone is
singed up to work that one down ;-)

Thanks, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH 4/9] drm/i915: Make derived plane state correct after crtc_enable

[Ville Syrjälä]

On Wed, Mar 11, 2015 at 05:23:27PM +0100, Daniel Vetter wrote:
> On Wed, Mar 11, 2015 at 02:19:38PM +0200, Ville Syrjälä wrote:
> > On Wed, Mar 11, 2015 at 11:24:34AM +0100, Daniel Vetter wrote:
> > > On Wed, Mar 11, 2015 at 12:05:39PM +0200, Ville Syrjälä wrote:
> > > > On Wed, Mar 11, 2015 at 10:52:29AM +0100, Daniel Vetter wrote:
> > > > > On Tue, Mar 10, 2015 at 07:57:13PM +0200, Ville Syrjälä wrote:
> > > > > > On Tue, Mar 10, 2015 at 10:01:51AM -0700, Matt Roper wrote:
> > > > > > > On Tue, Mar 10, 2015 at 01:15:24PM +0200, ville.syrjala@linux.intel.com wrote:
> > > > > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > > > > -static void disable_plane_internal(struct drm_plane *plane)
> > > > > > > > +static void _intel_crtc_enable_planes(struct intel_crtc *crtc)
> > > > > > > >  {
> > > > > > > > -	struct intel_plane *intel_plane = to_intel_plane(plane);
> > > > > > > > -	struct drm_plane_state *state =
> > > > > > > > -		plane->funcs->atomic_duplicate_state(plane);
> > > > > > > > -	struct intel_plane_state *intel_state = to_intel_plane_state(state);
> > > > > > > > +	struct drm_device *dev = crtc->base.dev;
> > > > > > > > +	enum pipe pipe = crtc->pipe;
> > > > > > > > +	struct intel_plane *plane;
> > > > > > > > +	const struct drm_crtc_helper_funcs *crtc_funcs =
> > > > > > > > +		crtc->base.helper_private;
> > > > > > > >  
> > > > > > > > -	intel_state->visible = false;
> > > > > > > > -	intel_plane->commit_plane(plane, intel_state);
> > > > > > > > +	for_each_intel_plane(dev, plane) {
> > > > > > > > +		const struct drm_plane_helper_funcs *funcs =
> > > > > > > > +			plane->base.helper_private;
> > > > > > > > +		struct intel_plane_state *state =
> > > > > > > > +			to_intel_plane_state(plane->base.state);
> > > > > > > >  
> > > > > > > > -	intel_plane_destroy_state(plane, state);
> > > > > > > > +		if (plane->pipe != pipe)
> > > > > > > > +			continue;
> > > > > > > > +
> > > > > > > > +		if (funcs->atomic_check(&plane->base, &state->base))
> > > > > > > 
> > > > > > > Maybe add a WARN_ON() here?  I'm assuming that this shouldn't really be
> > > > > > > possible since if this fails it means we've already previously done a
> > > > > > > commit of invalid state on a previous atomic transaction.  But if it
> > > > > > > does somehow happen, the WARN will give us a clue why the plane contents
> > > > > > > simply didn't show up.
> > > > > > 
> > > > > > I can think of one way to make it fail. That is, first set a smaller
> > > > > > mode with the primary plane (and fb) configured to cover that fully, and
> > > > > > then switch to a larger mode without reconfiguring the primary plane. If
> > > > > > the hardware requires the primary plane to be fullscreen it'll fail. But
> > > > > > that should actaully not be possible using the legacy modeset API as it
> > > > > > always reconfigures the primary, so we'd only have to worry about that
> > > > > > with full atomic modeset, and for that we anyway need to change the code
> > > > > > to do the check stuff up front.
> > > > > > 
> > > > > > So yeah, with the way things are this should not be able to fail. I'll
> > > > > > respin with the WARN.
> > > > > 
> > > > > I haven't fully dug into the details here, but a few randome comments:
> > > > > - While transitioning we're calling the transitional plane helpers, which
> > > > >   should call the atomic_check stuff for us on the primary plane. If we
> > > > >   need to call atomic_check on other planes too (why?)
> > > > 
> > > > Because we want the derived state to be updated to match the (potentially
> > > > changed) crtc config. We do call the .update_plane() hook from the
> > > > modeset path, but that happens at a time when the pipe is off, so our
> > > > clipping calculations end up saying the plane is invisible. I think fixing
> > > > that the right way pretty much involves the atomic conversion of the
> > > > modeset path.
> > > 
> > > Why do we conclude it's invisible?
> > 
> > Because crtc->active. So for this we'll be wanting crtc_state->active
> > or somesuch which tells us upfront whether the pipe is going to be
> > active or not.
> > 
> > But that's also beside the point a bit since we still want to make call
> > the .atomic_check() for all planes. Right now we'd call it for primary
> > (at the wrong point wrt. crtc->active) and we call it for sprites later
> > when crtc->active is showing the right state, but we don't call it at
> > all for cursors. That's why we still have that ad-hoc extra cursor
> > clipping code in intel_update_cursor(). If we could make the derived
> > plane state correct, we could throw that stuff out as well and trust the
> > regular plane clipping calculations to tell us when the cursor has gone
> > offscreen.
> > 
> > It'll also make the plane state behave in a consitent manner wrt.
> > crtc->active. As it stands you simply can't trust the plane state for
> > primary/cursor planes.
> > 
> > So to fix all of that, I just went ahead and called it for all planes at
> > the point where we currently call it for sprites. I could have just gone
> > ahead and called the higher level .update_plane() func for all of them
> > (as we did for sprites already) but going one level lower allowed me to
> > get the planes to pop in/out atomically.
> > 
> > I think it's the best way to move forward with getting the plane and wm
> > code into some kind of sane state.
> > 
> > > If we can fix the state to not depend
> > > upon the dpms state then things should work ...
> > 
> > That's a more drastic change and needs way more thought.
> 
> Yeah, but that's what we need to aim for eventually. So I want to make
> sure we're not running into the wrong direction and then have to backtrack
> even more.
> 
> > > > >   then I think that
> > > > >   should be done as close as possible to where we do that for the primary
> > > > >   one. Since eventually we need to unbury that call again.
> > > > 
> > > > With my patch _all_ planes get their .atomic_check() called in the same
> > > > place (during plane enable phase of .crtc_enable()).
> > > > 
> > > > > 
> > > > > - I don't like frobbing state objects which are committed (i.e. updating
> > > > >   visible like here), they're supposed to be invariant. With proper atomic
> > > > >   the way to deal with that is to grab all the required plane states and
> > > > >   put them into the drm_atomic_state update structure.
> > > > 
> > > > We really want to frob it so that the derived state will reflect
> > > > reality. Most importantly state->visible should be false whenever the
> > > > pipe is off, otherwise we can't trust state->visible and would also need
> > > > go look at the crtc state whenever we're trying to decide if the plane
> > > > is actually on or not.
> > > 
> > > Imo that's the correct thing to do. Calling plane hooks when the pipe is
> > > off just doesn't seem like a good idea to me. Together with runtime pm at
> > > least, crtc/atomic helpers have some "interesting" heritage.
> > > 
> > > But even there you can fix it by just reordering the commit_planes call to
> > > the bottom, where everything should be on. Iirc that's how Laurent fixed
> > > up rcar runtime pm issues to avoid touching planes when the hw is off.
> > > 
> > > The other reason why ->visible must take into account dpms state is that
> > > we'll screw up the watermark computation otherwise. Which could result
> > > into a failure on a subsequent dpms on, which is a big no-no.
> > 
> > Hmm, right. So for most calculations we'll just want to ignore the
> > DPMS state and calculate things as if the pipe was active (so only
> > looking at crtc_state->enabled I suppose). But when it's actually
> > time to write the values into the hardware we need too consider
> > the actual state of the pipe as well (so taking DPMS into account).
> > 
> > So yeah, if we decouple plane_state->visible from crtc->active and just
> > make it check crtc_state->enabled then plane_state->visible can be used
> > to do all the clipping, and upfront per-pipe wm calculations. But when
> > it comes time to apply the plane state or watermarks to the hardware we
> > need to check the actual pipe state.
> > 
> > So good plan, but needs quite a bit of work to get us there.
> > 
> > > > As for the direct state frobbing, we could make a copy I guess and frob
> > > > that instead, and then commit it. But that seems a lot of work for no gain.
> > > 
> > > That's how atomic is supposed to work really. But we can't make a copy in
> > > the crtc_enable really since that should never fail, and we can't push it
> > > out since we might not hold all the locks. That's all ofcourse for the
> > > atomic end-state, but I think even as an interim detour this approach here
> > > doesn't feel like a good approach to me.
> > 
> > We're going to need the "detour". That is, we do need to call the
> > .atomic_check() for all planes at modeset time. But trying to do it
> > earlier will mean changing all the plane visibility calculations to
> > consider the pipe active whenever crtc_state->enabled==true, and
> > that's going to require careful review of the code to make sure we
> > don't trust the plane visibility/clipping information too much. And
> > the same goes for the watermark code.
> > 
> > So I still think this is the right step to move forward. It'll allow us
> > to use the derived plane state correctly (and since it still depends on
> > crtc->active we won't risk enabling planes when the pipe is off), which
> > allows the plane and wm code to evolve in small steps, rather than some
> > mass conversion. I think there have been more than enough regressions
> > recently.
> 
> Ok, makes sense. It'll mean that there's more steps overall though, which
> might lead to more regressions overall, just spread out a bit. And we
> definitely need to make sure we unwrap this detour again. As long as
> Ander/Matt/you can roughly agree on a plan forward I'll go along with it.
> 
> For atomic in the end I think the important bit really from my pov is that
> we must not depend in any way upon neither intel_crtc->active nor
> crtc_state->active in the watermark computation code. Of course that means
> we need to do some untangling to make sure that we can correctly shut down
> everything if crtc_state->active isn't set.
> 
> Also do we have igt testcases for the regressions this patch series fixes?
> atomic is really complex, I think we should fill out gaps as we go along.
> So if we have them we need to add them to the list - Daniel Stone is
> singed up to work that one down ;-)

I'm not sure we've had real regressions here. But that's pretty much
just pure luck due to the fact that we haven't been using the derived
plane state except for sprites (for which we already did the full
.update_plane() thing).

So the cursor case was saved by the extra clipping step in
intel_update_cursor(), and for primary we've just been looking at the
user provided unclipped state, and we've been using the pipe source size
as the plane size. So as long as the user didn't put the primary
partially offscreen to require clipping, things have been working more
or less normally.

But to move forward with the primary plane windowing etc. we need to
start looking at the derived state, and so it must be first made
trustworthy.

-- 
Ville Syrjälä
Intel OTC
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[PATCH 5/9] drm/i915: Pass primary plane size to .update_primary_plane()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

In preparation to movable/resizable primary planes pass the clipped
plane size to .update_primary_plane().

Cc: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  3 +-
 drivers/gpu/drm/i915/intel_display.c | 63 ++++++++++++++++++++----------------
 2 files changed, 38 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b16c0a7..e99eef0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -578,7 +578,8 @@ struct drm_i915_display_funcs {
 			  uint32_t flags);
 	void (*update_primary_plane)(struct drm_crtc *crtc,
 				     struct drm_framebuffer *fb,
-				     int x, int y);
+				     int x, int y,
+				     int crtc_w, int crtc_h);
 	void (*hpd_irq_setup)(struct drm_device *dev);
 	/* clock updates for mode set */
 	/* cursor updates */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fdc83f1..1a789f0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2482,7 +2482,8 @@ intel_find_plane_obj(struct intel_crtc *intel_crtc,
 
 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 				      struct drm_framebuffer *fb,
-				      int x, int y)
+				      int x, int y,
+				      int crtc_w, int crtc_h)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2517,20 +2518,16 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 	if (INTEL_INFO(dev)->gen < 4) {
 		if (intel_crtc->pipe == PIPE_B)
 			dspcntr |= DISPPLANE_SEL_PIPE_B;
-
-		/* pipesrc and dspsize control the size that is scaled from,
-		 * which should always be the user's requested size.
-		 */
-		I915_WRITE(DSPSIZE(plane),
-			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
-			   (intel_crtc->config->pipe_src_w - 1));
+		I915_WRITE(DSPSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
 		I915_WRITE(DSPPOS(plane), 0);
 	} else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
-		I915_WRITE(PRIMSIZE(plane),
-			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
-			   (intel_crtc->config->pipe_src_w - 1));
+		I915_WRITE(PRIMSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
 		I915_WRITE(PRIMPOS(plane), 0);
 		I915_WRITE(PRIMCNSTALPHA(plane), 0);
+	} else {
+		WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
+			  crtc_h != intel_crtc->config->pipe_src_h,
+			  "primary plane size doesn't match pipe size\n");
 	}
 
 	switch (fb->pixel_format) {
@@ -2586,14 +2583,14 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 	if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
 		dspcntr |= DISPPLANE_ROTATE_180;
 
-		x += (intel_crtc->config->pipe_src_w - 1);
-		y += (intel_crtc->config->pipe_src_h - 1);
+		x += (crtc_w - 1);
+		y += (crtc_h - 1);
 
 		/* Finding the last pixel of the last line of the display
 		data and adding to linear_offset*/
 		linear_offset +=
-			(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
-			(intel_crtc->config->pipe_src_w - 1) * pixel_size;
+			(crtc_h - 1) * fb->pitches[0] +
+			(crtc_w - 1) * pixel_size;
 	}
 
 	I915_WRITE(reg, dspcntr);
@@ -2611,7 +2608,8 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 
 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 					  struct drm_framebuffer *fb,
-					  int x, int y)
+					  int x, int y,
+					  int crtc_w, int crtc_h)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2643,6 +2641,10 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
 
+	WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
+		  crtc_h != intel_crtc->config->pipe_src_h,
+		  "primary plane size doesn't match pipe size\n");
+
 	switch (fb->pixel_format) {
 	case DRM_FORMAT_C8:
 		dspcntr |= DISPPLANE_8BPP;
@@ -2686,14 +2688,14 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 		dspcntr |= DISPPLANE_ROTATE_180;
 
 		if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
-			x += (intel_crtc->config->pipe_src_w - 1);
-			y += (intel_crtc->config->pipe_src_h - 1);
+			x += (crtc_w - 1);
+			y += (crtc_h - 1);
 
 			/* Finding the last pixel of the last line of the display
 			data and adding to linear_offset*/
 			linear_offset +=
-				(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
-				(intel_crtc->config->pipe_src_w - 1) * pixel_size;
+				(crtc_h - 1) * fb->pitches[0] +
+				(crtc_w - 1) * pixel_size;
 		}
 	}
 
@@ -2747,7 +2749,8 @@ u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
 
 static void skylake_update_primary_plane(struct drm_crtc *crtc,
 					 struct drm_framebuffer *fb,
-					 int x, int y)
+					 int x, int y,
+					 int crtc_w, int crtc_h)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2826,9 +2829,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
 
 	I915_WRITE(PLANE_POS(pipe, 0), 0);
 	I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
-	I915_WRITE(PLANE_SIZE(pipe, 0),
-		   (intel_crtc->config->pipe_src_h - 1) << 16 |
-		   (intel_crtc->config->pipe_src_w - 1));
+	I915_WRITE(PLANE_SIZE(pipe, 0), ((crtc_h - 1) << 16) | (crtc_w - 1));
 	I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
 	I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
 
@@ -2845,12 +2846,16 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 
 	if (dev_priv->display.disable_fbc)
 		dev_priv->display.disable_fbc(dev);
 
+	/* FIXME: this will go badly if the fb isn't big enough */
 	to_intel_crtc(crtc)->primary_enabled = true;
-	dev_priv->display.update_primary_plane(crtc, fb, x, y);
+	dev_priv->display.update_primary_plane(crtc, fb, x, y,
+					       intel_crtc->config->pipe_src_w,
+					       intel_crtc->config->pipe_src_h);
 
 	return 0;
 }
@@ -2885,7 +2890,9 @@ static void intel_update_primary_planes(struct drm_device *dev)
 			dev_priv->display.update_primary_plane(crtc,
 							       state->base.fb,
 							       state->src.x1 >> 16,
-							       state->src.y1 >> 16);
+							       state->src.y1 >> 16,
+							       drm_rect_width(&state->dst),
+							       drm_rect_height(&state->dst));
 		}
 
 		drm_modeset_unlock(&crtc->mutex);
@@ -12019,7 +12026,9 @@ intel_commit_primary_plane(struct drm_plane *plane,
 		dev_priv->display.update_primary_plane(crtc,
 						       state->base.fb,
 						       state->src.x1 >> 16,
-						       state->src.y1 >> 16);
+						       state->src.y1 >> 16,
+						       drm_rect_width(&state->dst),
+						       drm_rect_height(&state->dst));
 	}
 }
 
-- 
2.0.5

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Re: [PATCH 5/9] drm/i915: Pass primary plane size to .update_primary_plane()

[Matt Roper]

On Tue, Mar 10, 2015 at 01:15:25PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> In preparation to movable/resizable primary planes pass the clipped
> plane size to .update_primary_plane().

Personally I feel like it would make more sense to just completely kill
off .update_primary_plane() now rather than trying to evolve it.  We
already have an intel_plane->update_plane() function pointer which is
never set or called for non-sprites at the moment.  We could unify the
handling of low-level plane programming by just using that function
pointer for primary planes as well.

I wouldn't mind also seeing the name of that low-level entrypoint
renamed to something like 'update_hw_plane' to avoid confusion with the
drm_plane entrypoint...


Matt

> 
> Cc: Sonika Jindal <sonika.jindal@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h      |  3 +-
>  drivers/gpu/drm/i915/intel_display.c | 63 ++++++++++++++++++++----------------
>  2 files changed, 38 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b16c0a7..e99eef0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -578,7 +578,8 @@ struct drm_i915_display_funcs {
>  			  uint32_t flags);
>  	void (*update_primary_plane)(struct drm_crtc *crtc,
>  				     struct drm_framebuffer *fb,
> -				     int x, int y);
> +				     int x, int y,
> +				     int crtc_w, int crtc_h);
>  	void (*hpd_irq_setup)(struct drm_device *dev);
>  	/* clock updates for mode set */
>  	/* cursor updates */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index fdc83f1..1a789f0 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2482,7 +2482,8 @@ intel_find_plane_obj(struct intel_crtc *intel_crtc,
>  
>  static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>  				      struct drm_framebuffer *fb,
> -				      int x, int y)
> +				      int x, int y,
> +				      int crtc_w, int crtc_h)
>  {
>  	struct drm_device *dev = crtc->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -2517,20 +2518,16 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>  	if (INTEL_INFO(dev)->gen < 4) {
>  		if (intel_crtc->pipe == PIPE_B)
>  			dspcntr |= DISPPLANE_SEL_PIPE_B;
> -
> -		/* pipesrc and dspsize control the size that is scaled from,
> -		 * which should always be the user's requested size.
> -		 */
> -		I915_WRITE(DSPSIZE(plane),
> -			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
> -			   (intel_crtc->config->pipe_src_w - 1));
> +		I915_WRITE(DSPSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
>  		I915_WRITE(DSPPOS(plane), 0);
>  	} else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
> -		I915_WRITE(PRIMSIZE(plane),
> -			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
> -			   (intel_crtc->config->pipe_src_w - 1));
> +		I915_WRITE(PRIMSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
>  		I915_WRITE(PRIMPOS(plane), 0);
>  		I915_WRITE(PRIMCNSTALPHA(plane), 0);
> +	} else {
> +		WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
> +			  crtc_h != intel_crtc->config->pipe_src_h,
> +			  "primary plane size doesn't match pipe size\n");
>  	}
>  
>  	switch (fb->pixel_format) {
> @@ -2586,14 +2583,14 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>  	if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
>  		dspcntr |= DISPPLANE_ROTATE_180;
>  
> -		x += (intel_crtc->config->pipe_src_w - 1);
> -		y += (intel_crtc->config->pipe_src_h - 1);
> +		x += (crtc_w - 1);
> +		y += (crtc_h - 1);
>  
>  		/* Finding the last pixel of the last line of the display
>  		data and adding to linear_offset*/
>  		linear_offset +=
> -			(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
> -			(intel_crtc->config->pipe_src_w - 1) * pixel_size;
> +			(crtc_h - 1) * fb->pitches[0] +
> +			(crtc_w - 1) * pixel_size;
>  	}
>  
>  	I915_WRITE(reg, dspcntr);
> @@ -2611,7 +2608,8 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>  
>  static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>  					  struct drm_framebuffer *fb,
> -					  int x, int y)
> +					  int x, int y,
> +					  int crtc_w, int crtc_h)
>  {
>  	struct drm_device *dev = crtc->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -2643,6 +2641,10 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>  	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>  		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
>  
> +	WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
> +		  crtc_h != intel_crtc->config->pipe_src_h,
> +		  "primary plane size doesn't match pipe size\n");
> +
>  	switch (fb->pixel_format) {
>  	case DRM_FORMAT_C8:
>  		dspcntr |= DISPPLANE_8BPP;
> @@ -2686,14 +2688,14 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>  		dspcntr |= DISPPLANE_ROTATE_180;
>  
>  		if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
> -			x += (intel_crtc->config->pipe_src_w - 1);
> -			y += (intel_crtc->config->pipe_src_h - 1);
> +			x += (crtc_w - 1);
> +			y += (crtc_h - 1);
>  
>  			/* Finding the last pixel of the last line of the display
>  			data and adding to linear_offset*/
>  			linear_offset +=
> -				(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
> -				(intel_crtc->config->pipe_src_w - 1) * pixel_size;
> +				(crtc_h - 1) * fb->pitches[0] +
> +				(crtc_w - 1) * pixel_size;
>  		}
>  	}
>  
> @@ -2747,7 +2749,8 @@ u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
>  
>  static void skylake_update_primary_plane(struct drm_crtc *crtc,
>  					 struct drm_framebuffer *fb,
> -					 int x, int y)
> +					 int x, int y,
> +					 int crtc_w, int crtc_h)
>  {
>  	struct drm_device *dev = crtc->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -2826,9 +2829,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
>  
>  	I915_WRITE(PLANE_POS(pipe, 0), 0);
>  	I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
> -	I915_WRITE(PLANE_SIZE(pipe, 0),
> -		   (intel_crtc->config->pipe_src_h - 1) << 16 |
> -		   (intel_crtc->config->pipe_src_w - 1));
> +	I915_WRITE(PLANE_SIZE(pipe, 0), ((crtc_h - 1) << 16) | (crtc_w - 1));
>  	I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
>  	I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
>  
> @@ -2845,12 +2846,16 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
>  {
>  	struct drm_device *dev = crtc->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  
>  	if (dev_priv->display.disable_fbc)
>  		dev_priv->display.disable_fbc(dev);
>  
> +	/* FIXME: this will go badly if the fb isn't big enough */
>  	to_intel_crtc(crtc)->primary_enabled = true;
> -	dev_priv->display.update_primary_plane(crtc, fb, x, y);
> +	dev_priv->display.update_primary_plane(crtc, fb, x, y,
> +					       intel_crtc->config->pipe_src_w,
> +					       intel_crtc->config->pipe_src_h);
>  
>  	return 0;
>  }
> @@ -2885,7 +2890,9 @@ static void intel_update_primary_planes(struct drm_device *dev)
>  			dev_priv->display.update_primary_plane(crtc,
>  							       state->base.fb,
>  							       state->src.x1 >> 16,
> -							       state->src.y1 >> 16);
> +							       state->src.y1 >> 16,
> +							       drm_rect_width(&state->dst),
> +							       drm_rect_height(&state->dst));
>  		}
>  
>  		drm_modeset_unlock(&crtc->mutex);
> @@ -12019,7 +12026,9 @@ intel_commit_primary_plane(struct drm_plane *plane,
>  		dev_priv->display.update_primary_plane(crtc,
>  						       state->base.fb,
>  						       state->src.x1 >> 16,
> -						       state->src.y1 >> 16);
> +						       state->src.y1 >> 16,
> +						       drm_rect_width(&state->dst),
> +						       drm_rect_height(&state->dst));
>  	}
>  }
>  
> -- 
> 2.0.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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Re: [PATCH 5/9] drm/i915: Pass primary plane size to .update_primary_plane()

[Ville Syrjälä]

On Tue, Mar 10, 2015 at 10:10:40AM -0700, Matt Roper wrote:
> On Tue, Mar 10, 2015 at 01:15:25PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > In preparation to movable/resizable primary planes pass the clipped
> > plane size to .update_primary_plane().
> 
> Personally I feel like it would make more sense to just completely kill
> off .update_primary_plane() now rather than trying to evolve it.  We
> already have an intel_plane->update_plane() function pointer which is
> never set or called for non-sprites at the moment.  We could unify the
> handling of low-level plane programming by just using that function
> pointer for primary planes as well.

I want to kill it off as well, but that means either killing off
set_base_atomic() or making it use the plane commit hook. I suppose we
could hand craft a suitable plane state for it and just commit that
without any checks or anything?

> 
> I wouldn't mind also seeing the name of that low-level entrypoint
> renamed to something like 'update_hw_plane' to avoid confusion with the
> drm_plane entrypoint...
> 
> 
> Matt
> 
> > 
> > Cc: Sonika Jindal <sonika.jindal@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h      |  3 +-
> >  drivers/gpu/drm/i915/intel_display.c | 63 ++++++++++++++++++++----------------
> >  2 files changed, 38 insertions(+), 28 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index b16c0a7..e99eef0 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -578,7 +578,8 @@ struct drm_i915_display_funcs {
> >  			  uint32_t flags);
> >  	void (*update_primary_plane)(struct drm_crtc *crtc,
> >  				     struct drm_framebuffer *fb,
> > -				     int x, int y);
> > +				     int x, int y,
> > +				     int crtc_w, int crtc_h);
> >  	void (*hpd_irq_setup)(struct drm_device *dev);
> >  	/* clock updates for mode set */
> >  	/* cursor updates */
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index fdc83f1..1a789f0 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -2482,7 +2482,8 @@ intel_find_plane_obj(struct intel_crtc *intel_crtc,
> >  
> >  static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> >  				      struct drm_framebuffer *fb,
> > -				      int x, int y)
> > +				      int x, int y,
> > +				      int crtc_w, int crtc_h)
> >  {
> >  	struct drm_device *dev = crtc->dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -2517,20 +2518,16 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> >  	if (INTEL_INFO(dev)->gen < 4) {
> >  		if (intel_crtc->pipe == PIPE_B)
> >  			dspcntr |= DISPPLANE_SEL_PIPE_B;
> > -
> > -		/* pipesrc and dspsize control the size that is scaled from,
> > -		 * which should always be the user's requested size.
> > -		 */
> > -		I915_WRITE(DSPSIZE(plane),
> > -			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
> > -			   (intel_crtc->config->pipe_src_w - 1));
> > +		I915_WRITE(DSPSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
> >  		I915_WRITE(DSPPOS(plane), 0);
> >  	} else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
> > -		I915_WRITE(PRIMSIZE(plane),
> > -			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
> > -			   (intel_crtc->config->pipe_src_w - 1));
> > +		I915_WRITE(PRIMSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
> >  		I915_WRITE(PRIMPOS(plane), 0);
> >  		I915_WRITE(PRIMCNSTALPHA(plane), 0);
> > +	} else {
> > +		WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
> > +			  crtc_h != intel_crtc->config->pipe_src_h,
> > +			  "primary plane size doesn't match pipe size\n");
> >  	}
> >  
> >  	switch (fb->pixel_format) {
> > @@ -2586,14 +2583,14 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> >  	if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
> >  		dspcntr |= DISPPLANE_ROTATE_180;
> >  
> > -		x += (intel_crtc->config->pipe_src_w - 1);
> > -		y += (intel_crtc->config->pipe_src_h - 1);
> > +		x += (crtc_w - 1);
> > +		y += (crtc_h - 1);
> >  
> >  		/* Finding the last pixel of the last line of the display
> >  		data and adding to linear_offset*/
> >  		linear_offset +=
> > -			(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
> > -			(intel_crtc->config->pipe_src_w - 1) * pixel_size;
> > +			(crtc_h - 1) * fb->pitches[0] +
> > +			(crtc_w - 1) * pixel_size;
> >  	}
> >  
> >  	I915_WRITE(reg, dspcntr);
> > @@ -2611,7 +2608,8 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> >  
> >  static void ironlake_update_primary_plane(struct drm_crtc *crtc,
> >  					  struct drm_framebuffer *fb,
> > -					  int x, int y)
> > +					  int x, int y,
> > +					  int crtc_w, int crtc_h)
> >  {
> >  	struct drm_device *dev = crtc->dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -2643,6 +2641,10 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
> >  	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> >  		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
> >  
> > +	WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
> > +		  crtc_h != intel_crtc->config->pipe_src_h,
> > +		  "primary plane size doesn't match pipe size\n");
> > +
> >  	switch (fb->pixel_format) {
> >  	case DRM_FORMAT_C8:
> >  		dspcntr |= DISPPLANE_8BPP;
> > @@ -2686,14 +2688,14 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
> >  		dspcntr |= DISPPLANE_ROTATE_180;
> >  
> >  		if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
> > -			x += (intel_crtc->config->pipe_src_w - 1);
> > -			y += (intel_crtc->config->pipe_src_h - 1);
> > +			x += (crtc_w - 1);
> > +			y += (crtc_h - 1);
> >  
> >  			/* Finding the last pixel of the last line of the display
> >  			data and adding to linear_offset*/
> >  			linear_offset +=
> > -				(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
> > -				(intel_crtc->config->pipe_src_w - 1) * pixel_size;
> > +				(crtc_h - 1) * fb->pitches[0] +
> > +				(crtc_w - 1) * pixel_size;
> >  		}
> >  	}
> >  
> > @@ -2747,7 +2749,8 @@ u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
> >  
> >  static void skylake_update_primary_plane(struct drm_crtc *crtc,
> >  					 struct drm_framebuffer *fb,
> > -					 int x, int y)
> > +					 int x, int y,
> > +					 int crtc_w, int crtc_h)
> >  {
> >  	struct drm_device *dev = crtc->dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -2826,9 +2829,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
> >  
> >  	I915_WRITE(PLANE_POS(pipe, 0), 0);
> >  	I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
> > -	I915_WRITE(PLANE_SIZE(pipe, 0),
> > -		   (intel_crtc->config->pipe_src_h - 1) << 16 |
> > -		   (intel_crtc->config->pipe_src_w - 1));
> > +	I915_WRITE(PLANE_SIZE(pipe, 0), ((crtc_h - 1) << 16) | (crtc_w - 1));
> >  	I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
> >  	I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
> >  
> > @@ -2845,12 +2846,16 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
> >  {
> >  	struct drm_device *dev = crtc->dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> >  
> >  	if (dev_priv->display.disable_fbc)
> >  		dev_priv->display.disable_fbc(dev);
> >  
> > +	/* FIXME: this will go badly if the fb isn't big enough */
> >  	to_intel_crtc(crtc)->primary_enabled = true;
> > -	dev_priv->display.update_primary_plane(crtc, fb, x, y);
> > +	dev_priv->display.update_primary_plane(crtc, fb, x, y,
> > +					       intel_crtc->config->pipe_src_w,
> > +					       intel_crtc->config->pipe_src_h);
> >  
> >  	return 0;
> >  }
> > @@ -2885,7 +2890,9 @@ static void intel_update_primary_planes(struct drm_device *dev)
> >  			dev_priv->display.update_primary_plane(crtc,
> >  							       state->base.fb,
> >  							       state->src.x1 >> 16,
> > -							       state->src.y1 >> 16);
> > +							       state->src.y1 >> 16,
> > +							       drm_rect_width(&state->dst),
> > +							       drm_rect_height(&state->dst));
> >  		}
> >  
> >  		drm_modeset_unlock(&crtc->mutex);
> > @@ -12019,7 +12026,9 @@ intel_commit_primary_plane(struct drm_plane *plane,
> >  		dev_priv->display.update_primary_plane(crtc,
> >  						       state->base.fb,
> >  						       state->src.x1 >> 16,
> > -						       state->src.y1 >> 16);
> > +						       state->src.y1 >> 16,
> > +						       drm_rect_width(&state->dst),
> > +						       drm_rect_height(&state->dst));
> >  	}
> >  }
> >  
> > -- 
> > 2.0.5
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 5/9] drm/i915: Pass primary plane size to .update_primary_plane()

[Matt Roper]

On Tue, Mar 10, 2015 at 07:59:15PM +0200, Ville Syrjälä wrote:
> On Tue, Mar 10, 2015 at 10:10:40AM -0700, Matt Roper wrote:
> > On Tue, Mar 10, 2015 at 01:15:25PM +0200, ville.syrjala@linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > In preparation to movable/resizable primary planes pass the clipped
> > > plane size to .update_primary_plane().
> > 
> > Personally I feel like it would make more sense to just completely kill
> > off .update_primary_plane() now rather than trying to evolve it.  We
> > already have an intel_plane->update_plane() function pointer which is
> > never set or called for non-sprites at the moment.  We could unify the
> > handling of low-level plane programming by just using that function
> > pointer for primary planes as well.
> 
> I want to kill it off as well, but that means either killing off
> set_base_atomic() or making it use the plane commit hook. I suppose we
> could hand craft a suitable plane state for it and just commit that
> without any checks or anything?

I'm not sure I follow your concern about set_base_atomic().  After your
patch series, it'll be calling

   dev_priv->display.update_primary_plane(crtc, fb, x, y,                                                                                                                                                   
                                          0, 0,                                                                                                                                                             
                                          intel_crtc->config->pipe_src_w,                                                                                                                                   
                                          intel_crtc->config->pipe_src_h);                                                                                                                                  

which basically directly programs the hardware for the primary plane and
doesn't do anything state-related.

It seems to me that just making that low-level call be:

   intel_plane = to_intel_plane(crtc->primary);
   intel_state = to_intel_plane_state(crtc->primary->state);

   intel_plane->update_plane(crtc->primary, crtc, fb, intel_fb_obj(fb),
                             0, 0,
                             intel_crtc->config->pipe_src_w,
                             intel_crtc->config->pipe_src_h,
                             x, y,
                             drm_rect_width(intel_state->src),
                             drm_rect_height(intel_state->src));

shouldn't make a difference; the implementation of
intel_plane->update_plane() would still be the same low-level register
programming without any state manipulation, the only difference being
that we get an extra pair of parameters containing source rect
width/height.

This would also allow us to point both primary and sprite planes at the
same function on SKL, which has two nearly-identical functions at the
moment for the lowest-level plane hardware programming.


Matt

> 
> > 
> > I wouldn't mind also seeing the name of that low-level entrypoint
> > renamed to something like 'update_hw_plane' to avoid confusion with the
> > drm_plane entrypoint...
> > 
> > 
> > Matt
> > 
> > > 
> > > Cc: Sonika Jindal <sonika.jindal@intel.com>
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_drv.h      |  3 +-
> > >  drivers/gpu/drm/i915/intel_display.c | 63 ++++++++++++++++++++----------------
> > >  2 files changed, 38 insertions(+), 28 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > index b16c0a7..e99eef0 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -578,7 +578,8 @@ struct drm_i915_display_funcs {
> > >  			  uint32_t flags);
> > >  	void (*update_primary_plane)(struct drm_crtc *crtc,
> > >  				     struct drm_framebuffer *fb,
> > > -				     int x, int y);
> > > +				     int x, int y,
> > > +				     int crtc_w, int crtc_h);
> > >  	void (*hpd_irq_setup)(struct drm_device *dev);
> > >  	/* clock updates for mode set */
> > >  	/* cursor updates */
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > index fdc83f1..1a789f0 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -2482,7 +2482,8 @@ intel_find_plane_obj(struct intel_crtc *intel_crtc,
> > >  
> > >  static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> > >  				      struct drm_framebuffer *fb,
> > > -				      int x, int y)
> > > +				      int x, int y,
> > > +				      int crtc_w, int crtc_h)
> > >  {
> > >  	struct drm_device *dev = crtc->dev;
> > >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > > @@ -2517,20 +2518,16 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> > >  	if (INTEL_INFO(dev)->gen < 4) {
> > >  		if (intel_crtc->pipe == PIPE_B)
> > >  			dspcntr |= DISPPLANE_SEL_PIPE_B;
> > > -
> > > -		/* pipesrc and dspsize control the size that is scaled from,
> > > -		 * which should always be the user's requested size.
> > > -		 */
> > > -		I915_WRITE(DSPSIZE(plane),
> > > -			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
> > > -			   (intel_crtc->config->pipe_src_w - 1));
> > > +		I915_WRITE(DSPSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
> > >  		I915_WRITE(DSPPOS(plane), 0);
> > >  	} else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
> > > -		I915_WRITE(PRIMSIZE(plane),
> > > -			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
> > > -			   (intel_crtc->config->pipe_src_w - 1));
> > > +		I915_WRITE(PRIMSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
> > >  		I915_WRITE(PRIMPOS(plane), 0);
> > >  		I915_WRITE(PRIMCNSTALPHA(plane), 0);
> > > +	} else {
> > > +		WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
> > > +			  crtc_h != intel_crtc->config->pipe_src_h,
> > > +			  "primary plane size doesn't match pipe size\n");
> > >  	}
> > >  
> > >  	switch (fb->pixel_format) {
> > > @@ -2586,14 +2583,14 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> > >  	if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
> > >  		dspcntr |= DISPPLANE_ROTATE_180;
> > >  
> > > -		x += (intel_crtc->config->pipe_src_w - 1);
> > > -		y += (intel_crtc->config->pipe_src_h - 1);
> > > +		x += (crtc_w - 1);
> > > +		y += (crtc_h - 1);
> > >  
> > >  		/* Finding the last pixel of the last line of the display
> > >  		data and adding to linear_offset*/
> > >  		linear_offset +=
> > > -			(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
> > > -			(intel_crtc->config->pipe_src_w - 1) * pixel_size;
> > > +			(crtc_h - 1) * fb->pitches[0] +
> > > +			(crtc_w - 1) * pixel_size;
> > >  	}
> > >  
> > >  	I915_WRITE(reg, dspcntr);
> > > @@ -2611,7 +2608,8 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> > >  
> > >  static void ironlake_update_primary_plane(struct drm_crtc *crtc,
> > >  					  struct drm_framebuffer *fb,
> > > -					  int x, int y)
> > > +					  int x, int y,
> > > +					  int crtc_w, int crtc_h)
> > >  {
> > >  	struct drm_device *dev = crtc->dev;
> > >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > > @@ -2643,6 +2641,10 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
> > >  	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> > >  		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
> > >  
> > > +	WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
> > > +		  crtc_h != intel_crtc->config->pipe_src_h,
> > > +		  "primary plane size doesn't match pipe size\n");
> > > +
> > >  	switch (fb->pixel_format) {
> > >  	case DRM_FORMAT_C8:
> > >  		dspcntr |= DISPPLANE_8BPP;
> > > @@ -2686,14 +2688,14 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
> > >  		dspcntr |= DISPPLANE_ROTATE_180;
> > >  
> > >  		if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
> > > -			x += (intel_crtc->config->pipe_src_w - 1);
> > > -			y += (intel_crtc->config->pipe_src_h - 1);
> > > +			x += (crtc_w - 1);
> > > +			y += (crtc_h - 1);
> > >  
> > >  			/* Finding the last pixel of the last line of the display
> > >  			data and adding to linear_offset*/
> > >  			linear_offset +=
> > > -				(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
> > > -				(intel_crtc->config->pipe_src_w - 1) * pixel_size;
> > > +				(crtc_h - 1) * fb->pitches[0] +
> > > +				(crtc_w - 1) * pixel_size;
> > >  		}
> > >  	}
> > >  
> > > @@ -2747,7 +2749,8 @@ u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
> > >  
> > >  static void skylake_update_primary_plane(struct drm_crtc *crtc,
> > >  					 struct drm_framebuffer *fb,
> > > -					 int x, int y)
> > > +					 int x, int y,
> > > +					 int crtc_w, int crtc_h)
> > >  {
> > >  	struct drm_device *dev = crtc->dev;
> > >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > > @@ -2826,9 +2829,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
> > >  
> > >  	I915_WRITE(PLANE_POS(pipe, 0), 0);
> > >  	I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
> > > -	I915_WRITE(PLANE_SIZE(pipe, 0),
> > > -		   (intel_crtc->config->pipe_src_h - 1) << 16 |
> > > -		   (intel_crtc->config->pipe_src_w - 1));
> > > +	I915_WRITE(PLANE_SIZE(pipe, 0), ((crtc_h - 1) << 16) | (crtc_w - 1));
> > >  	I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
> > >  	I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
> > >  
> > > @@ -2845,12 +2846,16 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
> > >  {
> > >  	struct drm_device *dev = crtc->dev;
> > >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > > +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > >  
> > >  	if (dev_priv->display.disable_fbc)
> > >  		dev_priv->display.disable_fbc(dev);
> > >  
> > > +	/* FIXME: this will go badly if the fb isn't big enough */
> > >  	to_intel_crtc(crtc)->primary_enabled = true;
> > > -	dev_priv->display.update_primary_plane(crtc, fb, x, y);
> > > +	dev_priv->display.update_primary_plane(crtc, fb, x, y,
> > > +					       intel_crtc->config->pipe_src_w,
> > > +					       intel_crtc->config->pipe_src_h);
> > >  
> > >  	return 0;
> > >  }
> > > @@ -2885,7 +2890,9 @@ static void intel_update_primary_planes(struct drm_device *dev)
> > >  			dev_priv->display.update_primary_plane(crtc,
> > >  							       state->base.fb,
> > >  							       state->src.x1 >> 16,
> > > -							       state->src.y1 >> 16);
> > > +							       state->src.y1 >> 16,
> > > +							       drm_rect_width(&state->dst),
> > > +							       drm_rect_height(&state->dst));
> > >  		}
> > >  
> > >  		drm_modeset_unlock(&crtc->mutex);
> > > @@ -12019,7 +12026,9 @@ intel_commit_primary_plane(struct drm_plane *plane,
> > >  		dev_priv->display.update_primary_plane(crtc,
> > >  						       state->base.fb,
> > >  						       state->src.x1 >> 16,
> > > -						       state->src.y1 >> 16);
> > > +						       state->src.y1 >> 16,
> > > +						       drm_rect_width(&state->dst),
> > > +						       drm_rect_height(&state->dst));
> > >  	}
> > >  }
> > >  
> > > -- 
> > > 2.0.5
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Matt Roper
> > Graphics Software Engineer
> > IoTG Platform Enabling & Development
> > Intel Corporation
> > (916) 356-2795
> 
> -- 
> Ville Syrjälä
> Intel OTC

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 5/9] drm/i915: Pass primary plane size to .update_primary_plane()

[Ville Syrjälä]

On Tue, Mar 10, 2015 at 01:57:09PM -0700, Matt Roper wrote:
> On Tue, Mar 10, 2015 at 07:59:15PM +0200, Ville Syrjälä wrote:
> > On Tue, Mar 10, 2015 at 10:10:40AM -0700, Matt Roper wrote:
> > > On Tue, Mar 10, 2015 at 01:15:25PM +0200, ville.syrjala@linux.intel.com wrote:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > 
> > > > In preparation to movable/resizable primary planes pass the clipped
> > > > plane size to .update_primary_plane().
> > > 
> > > Personally I feel like it would make more sense to just completely kill
> > > off .update_primary_plane() now rather than trying to evolve it.  We
> > > already have an intel_plane->update_plane() function pointer which is
> > > never set or called for non-sprites at the moment.  We could unify the
> > > handling of low-level plane programming by just using that function
> > > pointer for primary planes as well.
> > 
> > I want to kill it off as well, but that means either killing off
> > set_base_atomic() or making it use the plane commit hook. I suppose we
> > could hand craft a suitable plane state for it and just commit that
> > without any checks or anything?
> 
> I'm not sure I follow your concern about set_base_atomic().  After your
> patch series, it'll be calling
> 
>    dev_priv->display.update_primary_plane(crtc, fb, x, y,                                                                                                                                                   
>                                           0, 0,                                                                                                                                                             
>                                           intel_crtc->config->pipe_src_w,                                                                                                                                   
>                                           intel_crtc->config->pipe_src_h);                                                                                                                                  
> 
> which basically directly programs the hardware for the primary plane and
> doesn't do anything state-related.
> 
> It seems to me that just making that low-level call be:
> 
>    intel_plane = to_intel_plane(crtc->primary);
>    intel_state = to_intel_plane_state(crtc->primary->state);
> 
>    intel_plane->update_plane(crtc->primary, crtc, fb, intel_fb_obj(fb),
>                              0, 0,
>                              intel_crtc->config->pipe_src_w,
>                              intel_crtc->config->pipe_src_h,
>                              x, y,
>                              drm_rect_width(intel_state->src),
>                              drm_rect_height(intel_state->src));

We can't really use the current plane state here. It might not match what
we want. Although as I indicated with one FIXME in these patches,
set_base_atomic() will do something bad anyway if the fbdev framebuffer
is too small for the current pipe source size. I suppose we could try
to enable the panel fitter to avoid that, but then we run into problems
with managing the panel fitter which is a scarce resource (and there
is only one on gmch platforms and potentially with extra restrictions
on which pipes can use it).

Maybe we should just sanity check that the fbdev framebuffer is suitably
large for the current mode/pfit settings, and do nothing if it's not?
Or we could try to use a plane that can be resized (or potentially even
scaled) to preset the fbdev framebuffer. The other option would be to
throw out set_base_atomic() entirely. I have no idea if it works at all
currently.

And, as you've mentioned .update_plane(), I'm actually thinking we'll be
wanting to pass just a plane state there, and throw out most of the
function arguments as all that data should be in the plane state
already. And then we'd probably want to hand craft the plane state we
pass into .update_plane() for set_base_atomic() (assuming we'll keep it
at all) so that we don't leak fb references and whatnot. But all of
that is material for another set of patches.

> 
> shouldn't make a difference; the implementation of
> intel_plane->update_plane() would still be the same low-level register
> programming without any state manipulation, the only difference being
> that we get an extra pair of parameters containing source rect
> width/height.
> 
> This would also allow us to point both primary and sprite planes at the
> same function on SKL, which has two nearly-identical functions at the
> moment for the lowest-level plane hardware programming.

As I've noted in my reply to Sonika, the primary_enabled flag is the
main complication here. We really need to sort that out before can
fully unify this stuff.

> 
> 
> Matt
> 
> > 
> > > 
> > > I wouldn't mind also seeing the name of that low-level entrypoint
> > > renamed to something like 'update_hw_plane' to avoid confusion with the
> > > drm_plane entrypoint...
> > > 
> > > 
> > > Matt
> > > 
> > > > 
> > > > Cc: Sonika Jindal <sonika.jindal@intel.com>
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/i915_drv.h      |  3 +-
> > > >  drivers/gpu/drm/i915/intel_display.c | 63 ++++++++++++++++++++----------------
> > > >  2 files changed, 38 insertions(+), 28 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > > index b16c0a7..e99eef0 100644
> > > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > > @@ -578,7 +578,8 @@ struct drm_i915_display_funcs {
> > > >  			  uint32_t flags);
> > > >  	void (*update_primary_plane)(struct drm_crtc *crtc,
> > > >  				     struct drm_framebuffer *fb,
> > > > -				     int x, int y);
> > > > +				     int x, int y,
> > > > +				     int crtc_w, int crtc_h);
> > > >  	void (*hpd_irq_setup)(struct drm_device *dev);
> > > >  	/* clock updates for mode set */
> > > >  	/* cursor updates */
> > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > > index fdc83f1..1a789f0 100644
> > > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > > @@ -2482,7 +2482,8 @@ intel_find_plane_obj(struct intel_crtc *intel_crtc,
> > > >  
> > > >  static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> > > >  				      struct drm_framebuffer *fb,
> > > > -				      int x, int y)
> > > > +				      int x, int y,
> > > > +				      int crtc_w, int crtc_h)
> > > >  {
> > > >  	struct drm_device *dev = crtc->dev;
> > > >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > > > @@ -2517,20 +2518,16 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> > > >  	if (INTEL_INFO(dev)->gen < 4) {
> > > >  		if (intel_crtc->pipe == PIPE_B)
> > > >  			dspcntr |= DISPPLANE_SEL_PIPE_B;
> > > > -
> > > > -		/* pipesrc and dspsize control the size that is scaled from,
> > > > -		 * which should always be the user's requested size.
> > > > -		 */
> > > > -		I915_WRITE(DSPSIZE(plane),
> > > > -			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
> > > > -			   (intel_crtc->config->pipe_src_w - 1));
> > > > +		I915_WRITE(DSPSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
> > > >  		I915_WRITE(DSPPOS(plane), 0);
> > > >  	} else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
> > > > -		I915_WRITE(PRIMSIZE(plane),
> > > > -			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
> > > > -			   (intel_crtc->config->pipe_src_w - 1));
> > > > +		I915_WRITE(PRIMSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
> > > >  		I915_WRITE(PRIMPOS(plane), 0);
> > > >  		I915_WRITE(PRIMCNSTALPHA(plane), 0);
> > > > +	} else {
> > > > +		WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
> > > > +			  crtc_h != intel_crtc->config->pipe_src_h,
> > > > +			  "primary plane size doesn't match pipe size\n");
> > > >  	}
> > > >  
> > > >  	switch (fb->pixel_format) {
> > > > @@ -2586,14 +2583,14 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> > > >  	if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
> > > >  		dspcntr |= DISPPLANE_ROTATE_180;
> > > >  
> > > > -		x += (intel_crtc->config->pipe_src_w - 1);
> > > > -		y += (intel_crtc->config->pipe_src_h - 1);
> > > > +		x += (crtc_w - 1);
> > > > +		y += (crtc_h - 1);
> > > >  
> > > >  		/* Finding the last pixel of the last line of the display
> > > >  		data and adding to linear_offset*/
> > > >  		linear_offset +=
> > > > -			(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
> > > > -			(intel_crtc->config->pipe_src_w - 1) * pixel_size;
> > > > +			(crtc_h - 1) * fb->pitches[0] +
> > > > +			(crtc_w - 1) * pixel_size;
> > > >  	}
> > > >  
> > > >  	I915_WRITE(reg, dspcntr);
> > > > @@ -2611,7 +2608,8 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> > > >  
> > > >  static void ironlake_update_primary_plane(struct drm_crtc *crtc,
> > > >  					  struct drm_framebuffer *fb,
> > > > -					  int x, int y)
> > > > +					  int x, int y,
> > > > +					  int crtc_w, int crtc_h)
> > > >  {
> > > >  	struct drm_device *dev = crtc->dev;
> > > >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > > > @@ -2643,6 +2641,10 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
> > > >  	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> > > >  		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
> > > >  
> > > > +	WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
> > > > +		  crtc_h != intel_crtc->config->pipe_src_h,
> > > > +		  "primary plane size doesn't match pipe size\n");
> > > > +
> > > >  	switch (fb->pixel_format) {
> > > >  	case DRM_FORMAT_C8:
> > > >  		dspcntr |= DISPPLANE_8BPP;
> > > > @@ -2686,14 +2688,14 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
> > > >  		dspcntr |= DISPPLANE_ROTATE_180;
> > > >  
> > > >  		if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
> > > > -			x += (intel_crtc->config->pipe_src_w - 1);
> > > > -			y += (intel_crtc->config->pipe_src_h - 1);
> > > > +			x += (crtc_w - 1);
> > > > +			y += (crtc_h - 1);
> > > >  
> > > >  			/* Finding the last pixel of the last line of the display
> > > >  			data and adding to linear_offset*/
> > > >  			linear_offset +=
> > > > -				(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
> > > > -				(intel_crtc->config->pipe_src_w - 1) * pixel_size;
> > > > +				(crtc_h - 1) * fb->pitches[0] +
> > > > +				(crtc_w - 1) * pixel_size;
> > > >  		}
> > > >  	}
> > > >  
> > > > @@ -2747,7 +2749,8 @@ u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
> > > >  
> > > >  static void skylake_update_primary_plane(struct drm_crtc *crtc,
> > > >  					 struct drm_framebuffer *fb,
> > > > -					 int x, int y)
> > > > +					 int x, int y,
> > > > +					 int crtc_w, int crtc_h)
> > > >  {
> > > >  	struct drm_device *dev = crtc->dev;
> > > >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > > > @@ -2826,9 +2829,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
> > > >  
> > > >  	I915_WRITE(PLANE_POS(pipe, 0), 0);
> > > >  	I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
> > > > -	I915_WRITE(PLANE_SIZE(pipe, 0),
> > > > -		   (intel_crtc->config->pipe_src_h - 1) << 16 |
> > > > -		   (intel_crtc->config->pipe_src_w - 1));
> > > > +	I915_WRITE(PLANE_SIZE(pipe, 0), ((crtc_h - 1) << 16) | (crtc_w - 1));
> > > >  	I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
> > > >  	I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
> > > >  
> > > > @@ -2845,12 +2846,16 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
> > > >  {
> > > >  	struct drm_device *dev = crtc->dev;
> > > >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > > > +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > > >  
> > > >  	if (dev_priv->display.disable_fbc)
> > > >  		dev_priv->display.disable_fbc(dev);
> > > >  
> > > > +	/* FIXME: this will go badly if the fb isn't big enough */
> > > >  	to_intel_crtc(crtc)->primary_enabled = true;
> > > > -	dev_priv->display.update_primary_plane(crtc, fb, x, y);
> > > > +	dev_priv->display.update_primary_plane(crtc, fb, x, y,
> > > > +					       intel_crtc->config->pipe_src_w,
> > > > +					       intel_crtc->config->pipe_src_h);
> > > >  
> > > >  	return 0;
> > > >  }
> > > > @@ -2885,7 +2890,9 @@ static void intel_update_primary_planes(struct drm_device *dev)
> > > >  			dev_priv->display.update_primary_plane(crtc,
> > > >  							       state->base.fb,
> > > >  							       state->src.x1 >> 16,
> > > > -							       state->src.y1 >> 16);
> > > > +							       state->src.y1 >> 16,
> > > > +							       drm_rect_width(&state->dst),
> > > > +							       drm_rect_height(&state->dst));
> > > >  		}
> > > >  
> > > >  		drm_modeset_unlock(&crtc->mutex);
> > > > @@ -12019,7 +12026,9 @@ intel_commit_primary_plane(struct drm_plane *plane,
> > > >  		dev_priv->display.update_primary_plane(crtc,
> > > >  						       state->base.fb,
> > > >  						       state->src.x1 >> 16,
> > > > -						       state->src.y1 >> 16);
> > > > +						       state->src.y1 >> 16,
> > > > +						       drm_rect_width(&state->dst),
> > > > +						       drm_rect_height(&state->dst));
> > > >  	}
> > > >  }
> > > >  
> > > > -- 
> > > > 2.0.5
> > > > 
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > 
> > > -- 
> > > Matt Roper
> > > Graphics Software Engineer
> > > IoTG Platform Enabling & Development
> > > Intel Corporation
> > > (916) 356-2795
> > 
> > -- 
> > Ville Syrjälä
> > Intel OTC
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 5/9] drm/i915: Pass primary plane size to .update_primary_plane()

[Daniel Vetter]

On Tue, Mar 10, 2015 at 07:59:15PM +0200, Ville Syrjälä wrote:
> On Tue, Mar 10, 2015 at 10:10:40AM -0700, Matt Roper wrote:
> > On Tue, Mar 10, 2015 at 01:15:25PM +0200, ville.syrjala@linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > In preparation to movable/resizable primary planes pass the clipped
> > > plane size to .update_primary_plane().
> > 
> > Personally I feel like it would make more sense to just completely kill
> > off .update_primary_plane() now rather than trying to evolve it.  We
> > already have an intel_plane->update_plane() function pointer which is
> > never set or called for non-sprites at the moment.  We could unify the
> > handling of low-level plane programming by just using that function
> > pointer for primary planes as well.
> 
> I want to kill it off as well, but that means either killing off
> set_base_atomic() or making it use the plane commit hook. I suppose we
> could hand craft a suitable plane state for it and just commit that
> without any checks or anything?

set_base_atomic is bonghits imo, I think we should just replace it with
the set_base helper for the transitional helpers. set_base_atomic can't
grab locks and assumes that the buffer is pinned already. Hm, so maybe a
special version of the plane helper which forgoes the prepare/celanup_fb?
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH 5/9] drm/i915: Pass primary plane size to .update_primary_plane()

[sonika]

On Tuesday 10 March 2015 04:45 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> In preparation to movable/resizable primary planes pass the clipped
> plane size to .update_primary_plane().
>
> Cc: Sonika Jindal <sonika.jindal@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_drv.h      |  3 +-
>   drivers/gpu/drm/i915/intel_display.c | 63 ++++++++++++++++++++----------------
>   2 files changed, 38 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b16c0a7..e99eef0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -578,7 +578,8 @@ struct drm_i915_display_funcs {
>   			  uint32_t flags);
>   	void (*update_primary_plane)(struct drm_crtc *crtc,
>   				     struct drm_framebuffer *fb,
> -				     int x, int y);
> +				     int x, int y,
> +				     int crtc_w, int crtc_h);
>   	void (*hpd_irq_setup)(struct drm_device *dev);
>   	/* clock updates for mode set */
>   	/* cursor updates */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index fdc83f1..1a789f0 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2482,7 +2482,8 @@ intel_find_plane_obj(struct intel_crtc *intel_crtc,
>   
>   static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>   				      struct drm_framebuffer *fb,
> -				      int x, int y)
> +				      int x, int y,
> +				      int crtc_w, int crtc_h)
>   {
>   	struct drm_device *dev = crtc->dev;
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -2517,20 +2518,16 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>   	if (INTEL_INFO(dev)->gen < 4) {
>   		if (intel_crtc->pipe == PIPE_B)
>   			dspcntr |= DISPPLANE_SEL_PIPE_B;
> -
> -		/* pipesrc and dspsize control the size that is scaled from,
> -		 * which should always be the user's requested size.
> -		 */
> -		I915_WRITE(DSPSIZE(plane),
> -			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
> -			   (intel_crtc->config->pipe_src_w - 1));
> +		I915_WRITE(DSPSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
>   		I915_WRITE(DSPPOS(plane), 0);
>   	} else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
> -		I915_WRITE(PRIMSIZE(plane),
> -			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
> -			   (intel_crtc->config->pipe_src_w - 1));
> +		I915_WRITE(PRIMSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
>   		I915_WRITE(PRIMPOS(plane), 0);
>   		I915_WRITE(PRIMCNSTALPHA(plane), 0);
> +	} else {
> +		WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
> +			  crtc_h != intel_crtc->config->pipe_src_h,
> +			  "primary plane size doesn't match pipe size\n");
>   	}
>   
>   	switch (fb->pixel_format) {
> @@ -2586,14 +2583,14 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>   	if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
>   		dspcntr |= DISPPLANE_ROTATE_180;
>   
> -		x += (intel_crtc->config->pipe_src_w - 1);
> -		y += (intel_crtc->config->pipe_src_h - 1);
> +		x += (crtc_w - 1);
> +		y += (crtc_h - 1);
>   
>   		/* Finding the last pixel of the last line of the display
>   		data and adding to linear_offset*/
>   		linear_offset +=
> -			(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
> -			(intel_crtc->config->pipe_src_w - 1) * pixel_size;
> +			(crtc_h - 1) * fb->pitches[0] +
> +			(crtc_w - 1) * pixel_size;
>   	}
>   
>   	I915_WRITE(reg, dspcntr);
> @@ -2611,7 +2608,8 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>   
>   static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>   					  struct drm_framebuffer *fb,
> -					  int x, int y)
> +					  int x, int y,
> +					  int crtc_w, int crtc_h)
>   {
>   	struct drm_device *dev = crtc->dev;
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -2643,6 +2641,10 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>   	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>   		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
>   
> +	WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
> +		  crtc_h != intel_crtc->config->pipe_src_h,
> +		  "primary plane size doesn't match pipe size\n");
> +
>   	switch (fb->pixel_format) {
>   	case DRM_FORMAT_C8:
>   		dspcntr |= DISPPLANE_8BPP;
> @@ -2686,14 +2688,14 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>   		dspcntr |= DISPPLANE_ROTATE_180;
>   
>   		if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
> -			x += (intel_crtc->config->pipe_src_w - 1);
> -			y += (intel_crtc->config->pipe_src_h - 1);
> +			x += (crtc_w - 1);
> +			y += (crtc_h - 1);
>   
>   			/* Finding the last pixel of the last line of the display
>   			data and adding to linear_offset*/
>   			linear_offset +=
> -				(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
> -				(intel_crtc->config->pipe_src_w - 1) * pixel_size;
> +				(crtc_h - 1) * fb->pitches[0] +
> +				(crtc_w - 1) * pixel_size;
>   		}
>   	}
>   
> @@ -2747,7 +2749,8 @@ u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
>   
>   static void skylake_update_primary_plane(struct drm_crtc *crtc,
>   					 struct drm_framebuffer *fb,
> -					 int x, int y)
> +					 int x, int y,
> +					 int crtc_w, int crtc_h)
>   {
>   	struct drm_device *dev = crtc->dev;
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -2826,9 +2829,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
>   
>   	I915_WRITE(PLANE_POS(pipe, 0), 0);
>   	I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
> -	I915_WRITE(PLANE_SIZE(pipe, 0),
> -		   (intel_crtc->config->pipe_src_h - 1) << 16 |
> -		   (intel_crtc->config->pipe_src_w - 1));
Shouldn't this be x, y instead of crtc_h and crtc_w?
Because as you explained earlier (on one of my patches) plane_size 
represents the size of scanned out area from the fb.
> +	I915_WRITE(PLANE_SIZE(pipe, 0), ((crtc_h - 1) << 16) | (crtc_w - 1));
>   	I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
>   	I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
>   
> @@ -2845,12 +2846,16 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
>   {
>   	struct drm_device *dev = crtc->dev;
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>   
>   	if (dev_priv->display.disable_fbc)
>   		dev_priv->display.disable_fbc(dev);
>   
> +	/* FIXME: this will go badly if the fb isn't big enough */
>   	to_intel_crtc(crtc)->primary_enabled = true;
> -	dev_priv->display.update_primary_plane(crtc, fb, x, y);
> +	dev_priv->display.update_primary_plane(crtc, fb, x, y,
> +					       intel_crtc->config->pipe_src_w,
> +					       intel_crtc->config->pipe_src_h);
>   
>   	return 0;
>   }
> @@ -2885,7 +2890,9 @@ static void intel_update_primary_planes(struct drm_device *dev)
>   			dev_priv->display.update_primary_plane(crtc,
>   							       state->base.fb,
>   							       state->src.x1 >> 16,
> -							       state->src.y1 >> 16);
> +							       state->src.y1 >> 16,
> +							       drm_rect_width(&state->dst),
> +							       drm_rect_height(&state->dst));
>   		}
>   
>   		drm_modeset_unlock(&crtc->mutex);
> @@ -12019,7 +12026,9 @@ intel_commit_primary_plane(struct drm_plane *plane,
>   		dev_priv->display.update_primary_plane(crtc,
>   						       state->base.fb,
>   						       state->src.x1 >> 16,
> -						       state->src.y1 >> 16);
> +						       state->src.y1 >> 16,
> +						       drm_rect_width(&state->dst),
> +						       drm_rect_height(&state->dst));
>   	}
>   }
>   

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Re: [PATCH 5/9] drm/i915: Pass primary plane size to .update_primary_plane()

[Ville Syrjälä]

On Wed, Mar 11, 2015 at 10:39:31AM +0530, sonika wrote:
> 
> On Tuesday 10 March 2015 04:45 PM, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > In preparation to movable/resizable primary planes pass the clipped
> > plane size to .update_primary_plane().
> >
> > Cc: Sonika Jindal <sonika.jindal@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >   drivers/gpu/drm/i915/i915_drv.h      |  3 +-
> >   drivers/gpu/drm/i915/intel_display.c | 63 ++++++++++++++++++++----------------
> >   2 files changed, 38 insertions(+), 28 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index b16c0a7..e99eef0 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -578,7 +578,8 @@ struct drm_i915_display_funcs {
> >   			  uint32_t flags);
> >   	void (*update_primary_plane)(struct drm_crtc *crtc,
> >   				     struct drm_framebuffer *fb,
> > -				     int x, int y);
> > +				     int x, int y,
> > +				     int crtc_w, int crtc_h);
> >   	void (*hpd_irq_setup)(struct drm_device *dev);
> >   	/* clock updates for mode set */
> >   	/* cursor updates */
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index fdc83f1..1a789f0 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -2482,7 +2482,8 @@ intel_find_plane_obj(struct intel_crtc *intel_crtc,
> >   
> >   static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> >   				      struct drm_framebuffer *fb,
> > -				      int x, int y)
> > +				      int x, int y,
> > +				      int crtc_w, int crtc_h)
> >   {
> >   	struct drm_device *dev = crtc->dev;
> >   	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -2517,20 +2518,16 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> >   	if (INTEL_INFO(dev)->gen < 4) {
> >   		if (intel_crtc->pipe == PIPE_B)
> >   			dspcntr |= DISPPLANE_SEL_PIPE_B;
> > -
> > -		/* pipesrc and dspsize control the size that is scaled from,
> > -		 * which should always be the user's requested size.
> > -		 */
> > -		I915_WRITE(DSPSIZE(plane),
> > -			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
> > -			   (intel_crtc->config->pipe_src_w - 1));
> > +		I915_WRITE(DSPSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
> >   		I915_WRITE(DSPPOS(plane), 0);
> >   	} else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
> > -		I915_WRITE(PRIMSIZE(plane),
> > -			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
> > -			   (intel_crtc->config->pipe_src_w - 1));
> > +		I915_WRITE(PRIMSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
> >   		I915_WRITE(PRIMPOS(plane), 0);
> >   		I915_WRITE(PRIMCNSTALPHA(plane), 0);
> > +	} else {
> > +		WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
> > +			  crtc_h != intel_crtc->config->pipe_src_h,
> > +			  "primary plane size doesn't match pipe size\n");
> >   	}
> >   
> >   	switch (fb->pixel_format) {
> > @@ -2586,14 +2583,14 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> >   	if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
> >   		dspcntr |= DISPPLANE_ROTATE_180;
> >   
> > -		x += (intel_crtc->config->pipe_src_w - 1);
> > -		y += (intel_crtc->config->pipe_src_h - 1);
> > +		x += (crtc_w - 1);
> > +		y += (crtc_h - 1);
> >   
> >   		/* Finding the last pixel of the last line of the display
> >   		data and adding to linear_offset*/
> >   		linear_offset +=
> > -			(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
> > -			(intel_crtc->config->pipe_src_w - 1) * pixel_size;
> > +			(crtc_h - 1) * fb->pitches[0] +
> > +			(crtc_w - 1) * pixel_size;
> >   	}
> >   
> >   	I915_WRITE(reg, dspcntr);
> > @@ -2611,7 +2608,8 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> >   
> >   static void ironlake_update_primary_plane(struct drm_crtc *crtc,
> >   					  struct drm_framebuffer *fb,
> > -					  int x, int y)
> > +					  int x, int y,
> > +					  int crtc_w, int crtc_h)
> >   {
> >   	struct drm_device *dev = crtc->dev;
> >   	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -2643,6 +2641,10 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
> >   	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> >   		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
> >   
> > +	WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
> > +		  crtc_h != intel_crtc->config->pipe_src_h,
> > +		  "primary plane size doesn't match pipe size\n");
> > +
> >   	switch (fb->pixel_format) {
> >   	case DRM_FORMAT_C8:
> >   		dspcntr |= DISPPLANE_8BPP;
> > @@ -2686,14 +2688,14 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
> >   		dspcntr |= DISPPLANE_ROTATE_180;
> >   
> >   		if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
> > -			x += (intel_crtc->config->pipe_src_w - 1);
> > -			y += (intel_crtc->config->pipe_src_h - 1);
> > +			x += (crtc_w - 1);
> > +			y += (crtc_h - 1);
> >   
> >   			/* Finding the last pixel of the last line of the display
> >   			data and adding to linear_offset*/
> >   			linear_offset +=
> > -				(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
> > -				(intel_crtc->config->pipe_src_w - 1) * pixel_size;
> > +				(crtc_h - 1) * fb->pitches[0] +
> > +				(crtc_w - 1) * pixel_size;
> >   		}
> >   	}
> >   
> > @@ -2747,7 +2749,8 @@ u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
> >   
> >   static void skylake_update_primary_plane(struct drm_crtc *crtc,
> >   					 struct drm_framebuffer *fb,
> > -					 int x, int y)
> > +					 int x, int y,
> > +					 int crtc_w, int crtc_h)
> >   {
> >   	struct drm_device *dev = crtc->dev;
> >   	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -2826,9 +2829,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
> >   
> >   	I915_WRITE(PLANE_POS(pipe, 0), 0);
> >   	I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
> > -	I915_WRITE(PLANE_SIZE(pipe, 0),
> > -		   (intel_crtc->config->pipe_src_h - 1) << 16 |
> > -		   (intel_crtc->config->pipe_src_w - 1));
> Shouldn't this be x, y instead of crtc_h and crtc_w?
> Because as you explained earlier (on one of my patches) plane_size 
> represents the size of scanned out area from the fb.

Let me dig up the spec again... You're right, PLANE_SIZE is the input
size. But in this case it doesn't actually matter as there's no scaling
so input and output size are the same.

But yeah, it would be more correct to pass also the src size here and
use that where appropriate. That will make the parameter list look
almost like the sprite .update_plane() function, which is actually a
good thing. We should try to remvoe the primary plane specific functions
and just have one plane update function for each plane "variant". Right
now on SKL we're duplicating basically the same code between
skl_update_primary_plane() and skl_update_plane().

One extra complication is the primary_enabled flag. That needs to be
sorted out somehow before we can unify the primary/sprite code in this
way.

In any case, I'll respin this and pass the src size in there as well.

> > +	I915_WRITE(PLANE_SIZE(pipe, 0), ((crtc_h - 1) << 16) | (crtc_w - 1));
> >   	I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
> >   	I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
> >   
> > @@ -2845,12 +2846,16 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
> >   {
> >   	struct drm_device *dev = crtc->dev;
> >   	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> >   
> >   	if (dev_priv->display.disable_fbc)
> >   		dev_priv->display.disable_fbc(dev);
> >   
> > +	/* FIXME: this will go badly if the fb isn't big enough */
> >   	to_intel_crtc(crtc)->primary_enabled = true;
> > -	dev_priv->display.update_primary_plane(crtc, fb, x, y);
> > +	dev_priv->display.update_primary_plane(crtc, fb, x, y,
> > +					       intel_crtc->config->pipe_src_w,
> > +					       intel_crtc->config->pipe_src_h);
> >   
> >   	return 0;
> >   }
> > @@ -2885,7 +2890,9 @@ static void intel_update_primary_planes(struct drm_device *dev)
> >   			dev_priv->display.update_primary_plane(crtc,
> >   							       state->base.fb,
> >   							       state->src.x1 >> 16,
> > -							       state->src.y1 >> 16);
> > +							       state->src.y1 >> 16,
> > +							       drm_rect_width(&state->dst),
> > +							       drm_rect_height(&state->dst));
> >   		}
> >   
> >   		drm_modeset_unlock(&crtc->mutex);
> > @@ -12019,7 +12026,9 @@ intel_commit_primary_plane(struct drm_plane *plane,
> >   		dev_priv->display.update_primary_plane(crtc,
> >   						       state->base.fb,
> >   						       state->src.x1 >> 16,
> > -						       state->src.y1 >> 16);
> > +						       state->src.y1 >> 16,
> > +						       drm_rect_width(&state->dst),
> > +						       drm_rect_height(&state->dst));
> >   	}
> >   }
> >   

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 5/9] drm/i915: Pass primary plane size to .update_primary_plane()

[sonika]

On Wednesday 11 March 2015 02:57 PM, Ville Syrjälä wrote:
> On Wed, Mar 11, 2015 at 10:39:31AM +0530, sonika wrote:
>> On Tuesday 10 March 2015 04:45 PM, ville.syrjala@linux.intel.com wrote:
>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>
>>> In preparation to movable/resizable primary planes pass the clipped
>>> plane size to .update_primary_plane().
>>>
>>> Cc: Sonika Jindal <sonika.jindal@intel.com>
>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/i915_drv.h      |  3 +-
>>>    drivers/gpu/drm/i915/intel_display.c | 63 ++++++++++++++++++++----------------
>>>    2 files changed, 38 insertions(+), 28 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>> index b16c0a7..e99eef0 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -578,7 +578,8 @@ struct drm_i915_display_funcs {
>>>    			  uint32_t flags);
>>>    	void (*update_primary_plane)(struct drm_crtc *crtc,
>>>    				     struct drm_framebuffer *fb,
>>> -				     int x, int y);
>>> +				     int x, int y,
>>> +				     int crtc_w, int crtc_h);
>>>    	void (*hpd_irq_setup)(struct drm_device *dev);
>>>    	/* clock updates for mode set */
>>>    	/* cursor updates */
>>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>>> index fdc83f1..1a789f0 100644
>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>> @@ -2482,7 +2482,8 @@ intel_find_plane_obj(struct intel_crtc *intel_crtc,
>>>    
>>>    static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>>>    				      struct drm_framebuffer *fb,
>>> -				      int x, int y)
>>> +				      int x, int y,
>>> +				      int crtc_w, int crtc_h)
>>>    {
>>>    	struct drm_device *dev = crtc->dev;
>>>    	struct drm_i915_private *dev_priv = dev->dev_private;
>>> @@ -2517,20 +2518,16 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>>>    	if (INTEL_INFO(dev)->gen < 4) {
>>>    		if (intel_crtc->pipe == PIPE_B)
>>>    			dspcntr |= DISPPLANE_SEL_PIPE_B;
>>> -
>>> -		/* pipesrc and dspsize control the size that is scaled from,
>>> -		 * which should always be the user's requested size.
>>> -		 */
>>> -		I915_WRITE(DSPSIZE(plane),
>>> -			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
>>> -			   (intel_crtc->config->pipe_src_w - 1));
>>> +		I915_WRITE(DSPSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
>>>    		I915_WRITE(DSPPOS(plane), 0);
>>>    	} else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
>>> -		I915_WRITE(PRIMSIZE(plane),
>>> -			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
>>> -			   (intel_crtc->config->pipe_src_w - 1));
>>> +		I915_WRITE(PRIMSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
>>>    		I915_WRITE(PRIMPOS(plane), 0);
>>>    		I915_WRITE(PRIMCNSTALPHA(plane), 0);
>>> +	} else {
>>> +		WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
>>> +			  crtc_h != intel_crtc->config->pipe_src_h,
>>> +			  "primary plane size doesn't match pipe size\n");
>>>    	}
>>>    
>>>    	switch (fb->pixel_format) {
>>> @@ -2586,14 +2583,14 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>>>    	if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
>>>    		dspcntr |= DISPPLANE_ROTATE_180;
>>>    
>>> -		x += (intel_crtc->config->pipe_src_w - 1);
>>> -		y += (intel_crtc->config->pipe_src_h - 1);
>>> +		x += (crtc_w - 1);
>>> +		y += (crtc_h - 1);
>>>    
>>>    		/* Finding the last pixel of the last line of the display
>>>    		data and adding to linear_offset*/
>>>    		linear_offset +=
>>> -			(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
>>> -			(intel_crtc->config->pipe_src_w - 1) * pixel_size;
>>> +			(crtc_h - 1) * fb->pitches[0] +
>>> +			(crtc_w - 1) * pixel_size;
>>>    	}
>>>    
>>>    	I915_WRITE(reg, dspcntr);
>>> @@ -2611,7 +2608,8 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>>>    
>>>    static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>>>    					  struct drm_framebuffer *fb,
>>> -					  int x, int y)
>>> +					  int x, int y,
>>> +					  int crtc_w, int crtc_h)
>>>    {
>>>    	struct drm_device *dev = crtc->dev;
>>>    	struct drm_i915_private *dev_priv = dev->dev_private;
>>> @@ -2643,6 +2641,10 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>>>    	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>>>    		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
>>>    
>>> +	WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
>>> +		  crtc_h != intel_crtc->config->pipe_src_h,
>>> +		  "primary plane size doesn't match pipe size\n");
>>> +
>>>    	switch (fb->pixel_format) {
>>>    	case DRM_FORMAT_C8:
>>>    		dspcntr |= DISPPLANE_8BPP;
>>> @@ -2686,14 +2688,14 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>>>    		dspcntr |= DISPPLANE_ROTATE_180;
>>>    
>>>    		if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
>>> -			x += (intel_crtc->config->pipe_src_w - 1);
>>> -			y += (intel_crtc->config->pipe_src_h - 1);
>>> +			x += (crtc_w - 1);
>>> +			y += (crtc_h - 1);
>>>    
>>>    			/* Finding the last pixel of the last line of the display
>>>    			data and adding to linear_offset*/
>>>    			linear_offset +=
>>> -				(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
>>> -				(intel_crtc->config->pipe_src_w - 1) * pixel_size;
>>> +				(crtc_h - 1) * fb->pitches[0] +
>>> +				(crtc_w - 1) * pixel_size;
>>>    		}
>>>    	}
>>>    
>>> @@ -2747,7 +2749,8 @@ u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
>>>    
>>>    static void skylake_update_primary_plane(struct drm_crtc *crtc,
>>>    					 struct drm_framebuffer *fb,
>>> -					 int x, int y)
>>> +					 int x, int y,
>>> +					 int crtc_w, int crtc_h)
>>>    {
>>>    	struct drm_device *dev = crtc->dev;
>>>    	struct drm_i915_private *dev_priv = dev->dev_private;
>>> @@ -2826,9 +2829,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
>>>    
>>>    	I915_WRITE(PLANE_POS(pipe, 0), 0);
>>>    	I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
>>> -	I915_WRITE(PLANE_SIZE(pipe, 0),
>>> -		   (intel_crtc->config->pipe_src_h - 1) << 16 |
>>> -		   (intel_crtc->config->pipe_src_w - 1));
>> Shouldn't this be x, y instead of crtc_h and crtc_w?
>> Because as you explained earlier (on one of my patches) plane_size
>> represents the size of scanned out area from the fb.
> Let me dig up the spec again... You're right, PLANE_SIZE is the input
> size. But in this case it doesn't actually matter as there's no scaling
> so input and output size are the same.
>
> But yeah, it would be more correct to pass also the src size here and
> use that where appropriate. That will make the parameter list look
> almost like the sprite .update_plane() function, which is actually a
> good thing. We should try to remvoe the primary plane specific functions
> and just have one plane update function for each plane "variant". Right
> now on SKL we're duplicating basically the same code between
> skl_update_primary_plane() and skl_update_plane().
>
> One extra complication is the primary_enabled flag. That needs to be
> sorted out somehow before we can unify the primary/sprite code in this
> way.
>
> In any case, I'll respin this and pass the src size in there as well.
>
But we can use that from state right?
>>> +	I915_WRITE(PLANE_SIZE(pipe, 0), ((crtc_h - 1) << 16) | (crtc_w - 1));
>>>    	I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
>>>    	I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
>>>    
>>> @@ -2845,12 +2846,16 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
>>>    {
>>>    	struct drm_device *dev = crtc->dev;
>>>    	struct drm_i915_private *dev_priv = dev->dev_private;
>>> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>>>    
>>>    	if (dev_priv->display.disable_fbc)
>>>    		dev_priv->display.disable_fbc(dev);
>>>    
>>> +	/* FIXME: this will go badly if the fb isn't big enough */
>>>    	to_intel_crtc(crtc)->primary_enabled = true;
>>> -	dev_priv->display.update_primary_plane(crtc, fb, x, y);
>>> +	dev_priv->display.update_primary_plane(crtc, fb, x, y,
>>> +					       intel_crtc->config->pipe_src_w,
>>> +					       intel_crtc->config->pipe_src_h);
>>>    
>>>    	return 0;
>>>    }
>>> @@ -2885,7 +2890,9 @@ static void intel_update_primary_planes(struct drm_device *dev)
>>>    			dev_priv->display.update_primary_plane(crtc,
>>>    							       state->base.fb,
>>>    							       state->src.x1 >> 16,
>>> -							       state->src.y1 >> 16);
>>> +							       state->src.y1 >> 16,
>>> +							       drm_rect_width(&state->dst),
>>> +							       drm_rect_height(&state->dst));
>>>    		}
>>>    
>>>    		drm_modeset_unlock(&crtc->mutex);
>>> @@ -12019,7 +12026,9 @@ intel_commit_primary_plane(struct drm_plane *plane,
>>>    		dev_priv->display.update_primary_plane(crtc,
>>>    						       state->base.fb,
>>>    						       state->src.x1 >> 16,
>>> -						       state->src.y1 >> 16);
>>> +						       state->src.y1 >> 16,
>>> +						       drm_rect_width(&state->dst),
>>> +						       drm_rect_height(&state->dst));
>>>    	}
>>>    }
>>>    

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[PATCH v2 5/9] drm/i915: Pass primary plane size to .update_primary_plane()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

In preparation to movable/resizeable primary planes pass the clipped
plane size to .update_primary_plane().

v2: Pass src size too and use it appropriately (Sonika)

Cc: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  4 +-
 drivers/gpu/drm/i915/intel_display.c | 81 ++++++++++++++++++++++++------------
 2 files changed, 57 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ec23290..054be42 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -581,7 +581,9 @@ struct drm_i915_display_funcs {
 			  uint32_t flags);
 	void (*update_primary_plane)(struct drm_crtc *crtc,
 				     struct drm_framebuffer *fb,
-				     int x, int y);
+				     int x, int y,
+				     int src_w, int src_h,
+				     int crtc_w, int crtc_h);
 	void (*hpd_irq_setup)(struct drm_device *dev);
 	/* clock updates for mode set */
 	/* cursor updates */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5499c8e..2e9fdaa 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2482,7 +2482,9 @@ intel_find_plane_obj(struct intel_crtc *intel_crtc,
 
 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 				      struct drm_framebuffer *fb,
-				      int x, int y)
+				      int x, int y,
+				      int src_w, int src_h,
+				      int crtc_w, int crtc_h)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2514,23 +2516,22 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 
 	dspcntr |= DISPLAY_PLANE_ENABLE;
 
+	WARN_ONCE(src_w != crtc_w || src_h != crtc_h,
+		  "primary plane doesn't support scaling\n");
+
 	if (INTEL_INFO(dev)->gen < 4) {
 		if (intel_crtc->pipe == PIPE_B)
 			dspcntr |= DISPPLANE_SEL_PIPE_B;
-
-		/* pipesrc and dspsize control the size that is scaled from,
-		 * which should always be the user's requested size.
-		 */
-		I915_WRITE(DSPSIZE(plane),
-			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
-			   (intel_crtc->config->pipe_src_w - 1));
+		I915_WRITE(DSPSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
 		I915_WRITE(DSPPOS(plane), 0);
 	} else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
-		I915_WRITE(PRIMSIZE(plane),
-			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
-			   (intel_crtc->config->pipe_src_w - 1));
+		I915_WRITE(PRIMSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
 		I915_WRITE(PRIMPOS(plane), 0);
 		I915_WRITE(PRIMCNSTALPHA(plane), 0);
+	} else {
+		WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
+			  crtc_h != intel_crtc->config->pipe_src_h,
+			  "primary plane size doesn't match pipe size\n");
 	}
 
 	switch (fb->pixel_format) {
@@ -2586,14 +2587,14 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 	if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
 		dspcntr |= DISPPLANE_ROTATE_180;
 
-		x += (intel_crtc->config->pipe_src_w - 1);
-		y += (intel_crtc->config->pipe_src_h - 1);
+		x += (src_w - 1);
+		y += (src_h - 1);
 
 		/* Finding the last pixel of the last line of the display
 		data and adding to linear_offset*/
 		linear_offset +=
-			(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
-			(intel_crtc->config->pipe_src_w - 1) * pixel_size;
+			(src_h - 1) * fb->pitches[0] +
+			(src_w - 1) * pixel_size;
 	}
 
 	I915_WRITE(reg, dspcntr);
@@ -2611,7 +2612,9 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 
 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 					  struct drm_framebuffer *fb,
-					  int x, int y)
+					  int x, int y,
+					  int src_w, int src_h,
+					  int crtc_w, int crtc_h)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2643,6 +2646,13 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
 
+	WARN_ONCE(src_w != crtc_w || src_h != crtc_h,
+		  "primary plane doesn't support scaling\n");
+
+	WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
+		  crtc_h != intel_crtc->config->pipe_src_h,
+		  "primary plane size doesn't match pipe size\n");
+
 	switch (fb->pixel_format) {
 	case DRM_FORMAT_C8:
 		dspcntr |= DISPPLANE_8BPP;
@@ -2686,14 +2696,14 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 		dspcntr |= DISPPLANE_ROTATE_180;
 
 		if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
-			x += (intel_crtc->config->pipe_src_w - 1);
-			y += (intel_crtc->config->pipe_src_h - 1);
+			x += (src_w - 1);
+			y += (src_h - 1);
 
 			/* Finding the last pixel of the last line of the display
 			data and adding to linear_offset*/
 			linear_offset +=
-				(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
-				(intel_crtc->config->pipe_src_w - 1) * pixel_size;
+				(src_h - 1) * fb->pitches[0] +
+				(src_w - 1) * pixel_size;
 		}
 	}
 
@@ -2747,7 +2757,9 @@ u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
 
 static void skylake_update_primary_plane(struct drm_crtc *crtc,
 					 struct drm_framebuffer *fb,
-					 int x, int y)
+					 int x, int y,
+					 int src_w, int src_h,
+					 int crtc_w, int crtc_h)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2767,6 +2779,9 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
 		    PLANE_CTL_PIPE_GAMMA_ENABLE |
 		    PLANE_CTL_PIPE_CSC_ENABLE;
 
+	WARN_ONCE(src_w != crtc_w || src_h != crtc_h,
+		  "primary plane doesn't support scaling\n");
+
 	switch (fb->pixel_format) {
 	case DRM_FORMAT_RGB565:
 		plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
@@ -2826,9 +2841,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
 
 	I915_WRITE(PLANE_POS(pipe, 0), 0);
 	I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
-	I915_WRITE(PLANE_SIZE(pipe, 0),
-		   (intel_crtc->config->pipe_src_h - 1) << 16 |
-		   (intel_crtc->config->pipe_src_w - 1));
+	I915_WRITE(PLANE_SIZE(pipe, 0), ((src_h - 1) << 16) | (src_w - 1));
 	I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
 	I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
 
@@ -2845,12 +2858,18 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 
 	if (dev_priv->display.disable_fbc)
 		dev_priv->display.disable_fbc(dev);
 
+	/* FIXME: this will go badly if the fb isn't big enough */
 	to_intel_crtc(crtc)->primary_enabled = true;
-	dev_priv->display.update_primary_plane(crtc, fb, x, y);
+	dev_priv->display.update_primary_plane(crtc, fb, x, y,
+					       intel_crtc->config->pipe_src_w,
+					       intel_crtc->config->pipe_src_h,
+					       intel_crtc->config->pipe_src_w,
+					       intel_crtc->config->pipe_src_h);
 
 	return 0;
 }
@@ -2885,7 +2904,11 @@ static void intel_update_primary_planes(struct drm_device *dev)
 			dev_priv->display.update_primary_plane(crtc,
 							       state->base.fb,
 							       state->src.x1 >> 16,
-							       state->src.y1 >> 16);
+							       state->src.y1 >> 16,
+							       drm_rect_width(&state->src) >> 16,
+							       drm_rect_height(&state->src) >> 16,
+							       drm_rect_width(&state->dst),
+							       drm_rect_height(&state->dst));
 		}
 
 		drm_modeset_unlock(&crtc->mutex);
@@ -12070,7 +12093,11 @@ intel_commit_primary_plane(struct drm_plane *plane,
 		dev_priv->display.update_primary_plane(crtc,
 						       state->base.fb,
 						       state->src.x1 >> 16,
-						       state->src.y1 >> 16);
+						       state->src.y1 >> 16,
+						       drm_rect_width(&state->src) >> 16,
+						       drm_rect_height(&state->src) >> 16,
+						       drm_rect_width(&state->dst),
+						       drm_rect_height(&state->dst));
 	}
 }
 
-- 
2.0.5

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Re: [PATCH v2 5/9] drm/i915: Pass primary plane size to .update_primary_plane()

[Jindal, Sonika]

On 3/19/2015 7:58 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> In preparation to movable/resizeable primary planes pass the clipped
> plane size to .update_primary_plane().
>
> v2: Pass src size too and use it appropriately (Sonika)
>
> Cc: Sonika Jindal <sonika.jindal@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_drv.h      |  4 +-
>   drivers/gpu/drm/i915/intel_display.c | 81 ++++++++++++++++++++++++------------
>   2 files changed, 57 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index ec23290..054be42 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -581,7 +581,9 @@ struct drm_i915_display_funcs {
>   			  uint32_t flags);
>   	void (*update_primary_plane)(struct drm_crtc *crtc,
>   				     struct drm_framebuffer *fb,
> -				     int x, int y);
> +				     int x, int y,
> +				     int src_w, int src_h,
> +				     int crtc_w, int crtc_h);
>   	void (*hpd_irq_setup)(struct drm_device *dev);
>   	/* clock updates for mode set */
>   	/* cursor updates */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 5499c8e..2e9fdaa 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2482,7 +2482,9 @@ intel_find_plane_obj(struct intel_crtc *intel_crtc,
>
>   static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>   				      struct drm_framebuffer *fb,
> -				      int x, int y)
> +				      int x, int y,
> +				      int src_w, int src_h,
> +				      int crtc_w, int crtc_h)
>   {
>   	struct drm_device *dev = crtc->dev;
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -2514,23 +2516,22 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>
>   	dspcntr |= DISPLAY_PLANE_ENABLE;
>
> +	WARN_ONCE(src_w != crtc_w || src_h != crtc_h,
> +		  "primary plane doesn't support scaling\n");
> +
>   	if (INTEL_INFO(dev)->gen < 4) {
>   		if (intel_crtc->pipe == PIPE_B)
>   			dspcntr |= DISPPLANE_SEL_PIPE_B;
> -
> -		/* pipesrc and dspsize control the size that is scaled from,
> -		 * which should always be the user's requested size.
> -		 */
> -		I915_WRITE(DSPSIZE(plane),
> -			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
> -			   (intel_crtc->config->pipe_src_w - 1));
> +		I915_WRITE(DSPSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
Shouldn't this be src_* here, like you are doing for skl? Again it 
doesn't matter because no scaling. But still it will look better if we 
use same params across.
>   		I915_WRITE(DSPPOS(plane), 0);
>   	} else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
> -		I915_WRITE(PRIMSIZE(plane),
> -			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
> -			   (intel_crtc->config->pipe_src_w - 1));
> +		I915_WRITE(PRIMSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
Same as above.
>   		I915_WRITE(PRIMPOS(plane), 0);
>   		I915_WRITE(PRIMCNSTALPHA(plane), 0);
> +	} else {
> +		WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
> +			  crtc_h != intel_crtc->config->pipe_src_h,
> +			  "primary plane size doesn't match pipe size\n");
>   	}
>
>   	switch (fb->pixel_format) {
> @@ -2586,14 +2587,14 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>   	if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
>   		dspcntr |= DISPPLANE_ROTATE_180;
>
> -		x += (intel_crtc->config->pipe_src_w - 1);
> -		y += (intel_crtc->config->pipe_src_h - 1);
> +		x += (src_w - 1);
> +		y += (src_h - 1);
>
>   		/* Finding the last pixel of the last line of the display
>   		data and adding to linear_offset*/
>   		linear_offset +=
> -			(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
> -			(intel_crtc->config->pipe_src_w - 1) * pixel_size;
> +			(src_h - 1) * fb->pitches[0] +
> +			(src_w - 1) * pixel_size;
>   	}
>
>   	I915_WRITE(reg, dspcntr);
> @@ -2611,7 +2612,9 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>
>   static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>   					  struct drm_framebuffer *fb,
> -					  int x, int y)
> +					  int x, int y,
> +					  int src_w, int src_h,
> +					  int crtc_w, int crtc_h)
>   {
>   	struct drm_device *dev = crtc->dev;
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -2643,6 +2646,13 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>   	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>   		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
>
> +	WARN_ONCE(src_w != crtc_w || src_h != crtc_h,
> +		  "primary plane doesn't support scaling\n");
> +
> +	WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
> +		  crtc_h != intel_crtc->config->pipe_src_h,
> +		  "primary plane size doesn't match pipe size\n");
> +
I feel this should be part of the check_plane functions where we already 
perform many size related checks.
>   	switch (fb->pixel_format) {
>   	case DRM_FORMAT_C8:
>   		dspcntr |= DISPPLANE_8BPP;
> @@ -2686,14 +2696,14 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>   		dspcntr |= DISPPLANE_ROTATE_180;
>
>   		if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
> -			x += (intel_crtc->config->pipe_src_w - 1);
> -			y += (intel_crtc->config->pipe_src_h - 1);
> +			x += (src_w - 1);
> +			y += (src_h - 1);
>
>   			/* Finding the last pixel of the last line of the display
>   			data and adding to linear_offset*/
>   			linear_offset +=
> -				(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
> -				(intel_crtc->config->pipe_src_w - 1) * pixel_size;
> +				(src_h - 1) * fb->pitches[0] +
> +				(src_w - 1) * pixel_size;
>   		}
>   	}
>
> @@ -2747,7 +2757,9 @@ u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
>
>   static void skylake_update_primary_plane(struct drm_crtc *crtc,
>   					 struct drm_framebuffer *fb,
> -					 int x, int y)
> +					 int x, int y,
> +					 int src_w, int src_h,
> +					 int crtc_w, int crtc_h)
>   {
>   	struct drm_device *dev = crtc->dev;
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -2767,6 +2779,9 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
>   		    PLANE_CTL_PIPE_GAMMA_ENABLE |
>   		    PLANE_CTL_PIPE_CSC_ENABLE;
>
> +	WARN_ONCE(src_w != crtc_w || src_h != crtc_h,
> +		  "primary plane doesn't support scaling\n");
> +
>   	switch (fb->pixel_format) {
>   	case DRM_FORMAT_RGB565:
>   		plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
> @@ -2826,9 +2841,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
>
>   	I915_WRITE(PLANE_POS(pipe, 0), 0);
>   	I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
> -	I915_WRITE(PLANE_SIZE(pipe, 0),
> -		   (intel_crtc->config->pipe_src_h - 1) << 16 |
> -		   (intel_crtc->config->pipe_src_w - 1));
> +	I915_WRITE(PLANE_SIZE(pipe, 0), ((src_h - 1) << 16) | (src_w - 1));
>   	I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
>   	I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
>
> @@ -2845,12 +2858,18 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
>   {
>   	struct drm_device *dev = crtc->dev;
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>
>   	if (dev_priv->display.disable_fbc)
>   		dev_priv->display.disable_fbc(dev);
>
> +	/* FIXME: this will go badly if the fb isn't big enough */
>   	to_intel_crtc(crtc)->primary_enabled = true;
> -	dev_priv->display.update_primary_plane(crtc, fb, x, y);
> +	dev_priv->display.update_primary_plane(crtc, fb, x, y,
> +					       intel_crtc->config->pipe_src_w,
> +					       intel_crtc->config->pipe_src_h,
> +					       intel_crtc->config->pipe_src_w,
> +					       intel_crtc->config->pipe_src_h);
>
>   	return 0;
>   }
> @@ -2885,7 +2904,11 @@ static void intel_update_primary_planes(struct drm_device *dev)
>   			dev_priv->display.update_primary_plane(crtc,
>   							       state->base.fb,
>   							       state->src.x1 >> 16,
> -							       state->src.y1 >> 16);
> +							       state->src.y1 >> 16,
> +							       drm_rect_width(&state->src) >> 16,
> +							       drm_rect_height(&state->src) >> 16,
> +							       drm_rect_width(&state->dst),
> +							       drm_rect_height(&state->dst));
The order in intel_sprite.c is dst x, y, dest w, h, then src x, y, src 
w, h. But we can sort it later when we are actually merging both the 
update functions for primary and sprites.

Also, I think it will be better to pass crtc_x, crtc_y also to be used 
to set plane position.

-Sonika
>   		}
>
>   		drm_modeset_unlock(&crtc->mutex);
> @@ -12070,7 +12093,11 @@ intel_commit_primary_plane(struct drm_plane *plane,
>   		dev_priv->display.update_primary_plane(crtc,
>   						       state->base.fb,
>   						       state->src.x1 >> 16,
> -						       state->src.y1 >> 16);
> +						       state->src.y1 >> 16,
> +						       drm_rect_width(&state->src) >> 16,
> +						       drm_rect_height(&state->src) >> 16,
> +						       drm_rect_width(&state->dst),
> +						       drm_rect_height(&state->dst));
>   	}
>   }
>
>
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Re: [PATCH v2 5/9] drm/i915: Pass primary plane size to .update_primary_plane()

[Ville Syrjälä]

On Fri, Mar 20, 2015 at 03:19:53PM +0530, Jindal, Sonika wrote:
> 
> 
> On 3/19/2015 7:58 PM, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > In preparation to movable/resizeable primary planes pass the clipped
> > plane size to .update_primary_plane().
> >
> > v2: Pass src size too and use it appropriately (Sonika)
> >
> > Cc: Sonika Jindal <sonika.jindal@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >   drivers/gpu/drm/i915/i915_drv.h      |  4 +-
> >   drivers/gpu/drm/i915/intel_display.c | 81 ++++++++++++++++++++++++------------
> >   2 files changed, 57 insertions(+), 28 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index ec23290..054be42 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -581,7 +581,9 @@ struct drm_i915_display_funcs {
> >   			  uint32_t flags);
> >   	void (*update_primary_plane)(struct drm_crtc *crtc,
> >   				     struct drm_framebuffer *fb,
> > -				     int x, int y);
> > +				     int x, int y,
> > +				     int src_w, int src_h,
> > +				     int crtc_w, int crtc_h);
> >   	void (*hpd_irq_setup)(struct drm_device *dev);
> >   	/* clock updates for mode set */
> >   	/* cursor updates */
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 5499c8e..2e9fdaa 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -2482,7 +2482,9 @@ intel_find_plane_obj(struct intel_crtc *intel_crtc,
> >
> >   static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> >   				      struct drm_framebuffer *fb,
> > -				      int x, int y)
> > +				      int x, int y,
> > +				      int src_w, int src_h,
> > +				      int crtc_w, int crtc_h)
> >   {
> >   	struct drm_device *dev = crtc->dev;
> >   	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -2514,23 +2516,22 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> >
> >   	dspcntr |= DISPLAY_PLANE_ENABLE;
> >
> > +	WARN_ONCE(src_w != crtc_w || src_h != crtc_h,
> > +		  "primary plane doesn't support scaling\n");
> > +
> >   	if (INTEL_INFO(dev)->gen < 4) {
> >   		if (intel_crtc->pipe == PIPE_B)
> >   			dspcntr |= DISPPLANE_SEL_PIPE_B;
> > -
> > -		/* pipesrc and dspsize control the size that is scaled from,
> > -		 * which should always be the user's requested size.
> > -		 */
> > -		I915_WRITE(DSPSIZE(plane),
> > -			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
> > -			   (intel_crtc->config->pipe_src_w - 1));
> > +		I915_WRITE(DSPSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
> Shouldn't this be src_* here, like you are doing for skl? Again it 
> doesn't matter because no scaling. But still it will look better if we 
> use same params across.
> >   		I915_WRITE(DSPPOS(plane), 0);
> >   	} else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
> > -		I915_WRITE(PRIMSIZE(plane),
> > -			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
> > -			   (intel_crtc->config->pipe_src_w - 1));
> > +		I915_WRITE(PRIMSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
> Same as above.

Nope. On CHV there is a scaler on one of the planes and there we'll need
to write the dst size into PRIMSIZE, and the src size to another register.
So just using the dst size for PRIMSIZE seems like the right choice.

Also with ILK-IVB sprites the dst size is also in the plane size register,
and the source size is in the plane scale register (eg. DVSSIZE and
DVSSSCALE), so this way seems more consistent with most of the platforms.

Although if we want to expose the pixel/line doubling as fixed 2x
scaling we might need to rethink this again. But I'm going to pretend
that there's no such thing for now.

> >   		I915_WRITE(PRIMPOS(plane), 0);
> >   		I915_WRITE(PRIMCNSTALPHA(plane), 0);
> > +	} else {
> > +		WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
> > +			  crtc_h != intel_crtc->config->pipe_src_h,
> > +			  "primary plane size doesn't match pipe size\n");
> >   	}
> >
> >   	switch (fb->pixel_format) {
> > @@ -2586,14 +2587,14 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> >   	if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
> >   		dspcntr |= DISPPLANE_ROTATE_180;
> >
> > -		x += (intel_crtc->config->pipe_src_w - 1);
> > -		y += (intel_crtc->config->pipe_src_h - 1);
> > +		x += (src_w - 1);
> > +		y += (src_h - 1);
> >
> >   		/* Finding the last pixel of the last line of the display
> >   		data and adding to linear_offset*/
> >   		linear_offset +=
> > -			(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
> > -			(intel_crtc->config->pipe_src_w - 1) * pixel_size;
> > +			(src_h - 1) * fb->pitches[0] +
> > +			(src_w - 1) * pixel_size;
> >   	}
> >
> >   	I915_WRITE(reg, dspcntr);
> > @@ -2611,7 +2612,9 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> >
> >   static void ironlake_update_primary_plane(struct drm_crtc *crtc,
> >   					  struct drm_framebuffer *fb,
> > -					  int x, int y)
> > +					  int x, int y,
> > +					  int src_w, int src_h,
> > +					  int crtc_w, int crtc_h)
> >   {
> >   	struct drm_device *dev = crtc->dev;
> >   	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -2643,6 +2646,13 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
> >   	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> >   		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
> >
> > +	WARN_ONCE(src_w != crtc_w || src_h != crtc_h,
> > +		  "primary plane doesn't support scaling\n");
> > +
> > +	WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
> > +		  crtc_h != intel_crtc->config->pipe_src_h,
> > +		  "primary plane size doesn't match pipe size\n");
> > +
> I feel this should be part of the check_plane functions where we already 
> perform many size related checks.

This is just an assertion to catch anyone passing bogus values here,
and a reminder to people that if they want to extend the primary plane
capabilities there's more work to be done.

> >   	switch (fb->pixel_format) {
> >   	case DRM_FORMAT_C8:
> >   		dspcntr |= DISPPLANE_8BPP;
> > @@ -2686,14 +2696,14 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
> >   		dspcntr |= DISPPLANE_ROTATE_180;
> >
> >   		if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
> > -			x += (intel_crtc->config->pipe_src_w - 1);
> > -			y += (intel_crtc->config->pipe_src_h - 1);
> > +			x += (src_w - 1);
> > +			y += (src_h - 1);
> >
> >   			/* Finding the last pixel of the last line of the display
> >   			data and adding to linear_offset*/
> >   			linear_offset +=
> > -				(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
> > -				(intel_crtc->config->pipe_src_w - 1) * pixel_size;
> > +				(src_h - 1) * fb->pitches[0] +
> > +				(src_w - 1) * pixel_size;
> >   		}
> >   	}
> >
> > @@ -2747,7 +2757,9 @@ u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
> >
> >   static void skylake_update_primary_plane(struct drm_crtc *crtc,
> >   					 struct drm_framebuffer *fb,
> > -					 int x, int y)
> > +					 int x, int y,
> > +					 int src_w, int src_h,
> > +					 int crtc_w, int crtc_h)
> >   {
> >   	struct drm_device *dev = crtc->dev;
> >   	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -2767,6 +2779,9 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
> >   		    PLANE_CTL_PIPE_GAMMA_ENABLE |
> >   		    PLANE_CTL_PIPE_CSC_ENABLE;
> >
> > +	WARN_ONCE(src_w != crtc_w || src_h != crtc_h,
> > +		  "primary plane doesn't support scaling\n");
> > +
> >   	switch (fb->pixel_format) {
> >   	case DRM_FORMAT_RGB565:
> >   		plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
> > @@ -2826,9 +2841,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
> >
> >   	I915_WRITE(PLANE_POS(pipe, 0), 0);
> >   	I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
> > -	I915_WRITE(PLANE_SIZE(pipe, 0),
> > -		   (intel_crtc->config->pipe_src_h - 1) << 16 |
> > -		   (intel_crtc->config->pipe_src_w - 1));
> > +	I915_WRITE(PLANE_SIZE(pipe, 0), ((src_h - 1) << 16) | (src_w - 1));
> >   	I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
> >   	I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
> >
> > @@ -2845,12 +2858,18 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
> >   {
> >   	struct drm_device *dev = crtc->dev;
> >   	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> >
> >   	if (dev_priv->display.disable_fbc)
> >   		dev_priv->display.disable_fbc(dev);
> >
> > +	/* FIXME: this will go badly if the fb isn't big enough */
> >   	to_intel_crtc(crtc)->primary_enabled = true;
> > -	dev_priv->display.update_primary_plane(crtc, fb, x, y);
> > +	dev_priv->display.update_primary_plane(crtc, fb, x, y,
> > +					       intel_crtc->config->pipe_src_w,
> > +					       intel_crtc->config->pipe_src_h,
> > +					       intel_crtc->config->pipe_src_w,
> > +					       intel_crtc->config->pipe_src_h);
> >
> >   	return 0;
> >   }
> > @@ -2885,7 +2904,11 @@ static void intel_update_primary_planes(struct drm_device *dev)
> >   			dev_priv->display.update_primary_plane(crtc,
> >   							       state->base.fb,
> >   							       state->src.x1 >> 16,
> > -							       state->src.y1 >> 16);
> > +							       state->src.y1 >> 16,
> > +							       drm_rect_width(&state->src) >> 16,
> > +							       drm_rect_height(&state->src) >> 16,
> > +							       drm_rect_width(&state->dst),
> > +							       drm_rect_height(&state->dst));
> The order in intel_sprite.c is dst x, y, dest w, h, then src x, y, src 
> w, h. But we can sort it later when we are actually merging both the 
> update functions for primary and sprites.

Oh. Failed to notice that. But yeah easy enough to fix when we unify.

> 
> Also, I think it will be better to pass crtc_x, crtc_y also to be used 
> to set plane position.

That's in the next patch.

> 
> -Sonika
> >   		}
> >
> >   		drm_modeset_unlock(&crtc->mutex);
> > @@ -12070,7 +12093,11 @@ intel_commit_primary_plane(struct drm_plane *plane,
> >   		dev_priv->display.update_primary_plane(crtc,
> >   						       state->base.fb,
> >   						       state->src.x1 >> 16,
> > -						       state->src.y1 >> 16);
> > +						       state->src.y1 >> 16,
> > +						       drm_rect_width(&state->src) >> 16,
> > +						       drm_rect_height(&state->src) >> 16,
> > +						       drm_rect_width(&state->dst),
> > +						       drm_rect_height(&state->dst));
> >   	}
> >   }
> >
> >

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH v2 5/9] drm/i915: Pass primary plane size to .update_primary_plane()

[Jindal, Sonika]

On 3/20/2015 3:34 PM, Ville Syrjälä wrote:
> On Fri, Mar 20, 2015 at 03:19:53PM +0530, Jindal, Sonika wrote:
>>
>>
>> On 3/19/2015 7:58 PM, ville.syrjala@linux.intel.com wrote:
>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>
>>> In preparation to movable/resizeable primary planes pass the clipped
>>> plane size to .update_primary_plane().
>>>
>>> v2: Pass src size too and use it appropriately (Sonika)
>>>
>>> Cc: Sonika Jindal <sonika.jindal@intel.com>
>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/i915_drv.h      |  4 +-
>>>    drivers/gpu/drm/i915/intel_display.c | 81 ++++++++++++++++++++++++------------
>>>    2 files changed, 57 insertions(+), 28 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>> index ec23290..054be42 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -581,7 +581,9 @@ struct drm_i915_display_funcs {
>>>    			  uint32_t flags);
>>>    	void (*update_primary_plane)(struct drm_crtc *crtc,
>>>    				     struct drm_framebuffer *fb,
>>> -				     int x, int y);
>>> +				     int x, int y,
>>> +				     int src_w, int src_h,
>>> +				     int crtc_w, int crtc_h);
>>>    	void (*hpd_irq_setup)(struct drm_device *dev);
>>>    	/* clock updates for mode set */
>>>    	/* cursor updates */
>>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>>> index 5499c8e..2e9fdaa 100644
>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>> @@ -2482,7 +2482,9 @@ intel_find_plane_obj(struct intel_crtc *intel_crtc,
>>>
>>>    static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>>>    				      struct drm_framebuffer *fb,
>>> -				      int x, int y)
>>> +				      int x, int y,
>>> +				      int src_w, int src_h,
>>> +				      int crtc_w, int crtc_h)
>>>    {
>>>    	struct drm_device *dev = crtc->dev;
>>>    	struct drm_i915_private *dev_priv = dev->dev_private;
>>> @@ -2514,23 +2516,22 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>>>
>>>    	dspcntr |= DISPLAY_PLANE_ENABLE;
>>>
>>> +	WARN_ONCE(src_w != crtc_w || src_h != crtc_h,
>>> +		  "primary plane doesn't support scaling\n");
>>> +
>>>    	if (INTEL_INFO(dev)->gen < 4) {
>>>    		if (intel_crtc->pipe == PIPE_B)
>>>    			dspcntr |= DISPPLANE_SEL_PIPE_B;
>>> -
>>> -		/* pipesrc and dspsize control the size that is scaled from,
>>> -		 * which should always be the user's requested size.
>>> -		 */
>>> -		I915_WRITE(DSPSIZE(plane),
>>> -			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
>>> -			   (intel_crtc->config->pipe_src_w - 1));
>>> +		I915_WRITE(DSPSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
>> Shouldn't this be src_* here, like you are doing for skl? Again it
>> doesn't matter because no scaling. But still it will look better if we
>> use same params across.
>>>    		I915_WRITE(DSPPOS(plane), 0);
>>>    	} else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
>>> -		I915_WRITE(PRIMSIZE(plane),
>>> -			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
>>> -			   (intel_crtc->config->pipe_src_w - 1));
>>> +		I915_WRITE(PRIMSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
>> Same as above.
>
> Nope. On CHV there is a scaler on one of the planes and there we'll need
> to write the dst size into PRIMSIZE, and the src size to another register.
> So just using the dst size for PRIMSIZE seems like the right choice.
>
> Also with ILK-IVB sprites the dst size is also in the plane size register,
> and the source size is in the plane scale register (eg. DVSSIZE and
> DVSSSCALE), so this way seems more consistent with most of the platforms.
>
Then it would be good to have some comment here?
> Although if we want to expose the pixel/line doubling as fixed 2x
> scaling we might need to rethink this again. But I'm going to pretend
> that there's no such thing for now.
>
>>>    		I915_WRITE(PRIMPOS(plane), 0);
>>>    		I915_WRITE(PRIMCNSTALPHA(plane), 0);
>>> +	} else {
>>> +		WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
>>> +			  crtc_h != intel_crtc->config->pipe_src_h,
>>> +			  "primary plane size doesn't match pipe size\n");
>>>    	}
>>>
>>>    	switch (fb->pixel_format) {
>>> @@ -2586,14 +2587,14 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>>>    	if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
>>>    		dspcntr |= DISPPLANE_ROTATE_180;
>>>
>>> -		x += (intel_crtc->config->pipe_src_w - 1);
>>> -		y += (intel_crtc->config->pipe_src_h - 1);
>>> +		x += (src_w - 1);
>>> +		y += (src_h - 1);
>>>
>>>    		/* Finding the last pixel of the last line of the display
>>>    		data and adding to linear_offset*/
>>>    		linear_offset +=
>>> -			(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
>>> -			(intel_crtc->config->pipe_src_w - 1) * pixel_size;
>>> +			(src_h - 1) * fb->pitches[0] +
>>> +			(src_w - 1) * pixel_size;
>>>    	}
>>>
>>>    	I915_WRITE(reg, dspcntr);
>>> @@ -2611,7 +2612,9 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>>>
>>>    static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>>>    					  struct drm_framebuffer *fb,
>>> -					  int x, int y)
>>> +					  int x, int y,
>>> +					  int src_w, int src_h,
>>> +					  int crtc_w, int crtc_h)
>>>    {
>>>    	struct drm_device *dev = crtc->dev;
>>>    	struct drm_i915_private *dev_priv = dev->dev_private;
>>> @@ -2643,6 +2646,13 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>>>    	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>>>    		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
>>>
>>> +	WARN_ONCE(src_w != crtc_w || src_h != crtc_h,
>>> +		  "primary plane doesn't support scaling\n");
>>> +
>>> +	WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
>>> +		  crtc_h != intel_crtc->config->pipe_src_h,
>>> +		  "primary plane size doesn't match pipe size\n");
>>> +
>> I feel this should be part of the check_plane functions where we already
>> perform many size related checks.
>
> This is just an assertion to catch anyone passing bogus values here,
> and a reminder to people that if they want to extend the primary plane
> capabilities there's more work to be done.
>
Hmm, but still this can be part of the check_plane. No problem, you call.
>>>    	switch (fb->pixel_format) {
>>>    	case DRM_FORMAT_C8:
>>>    		dspcntr |= DISPPLANE_8BPP;
>>> @@ -2686,14 +2696,14 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>>>    		dspcntr |= DISPPLANE_ROTATE_180;
>>>
>>>    		if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
>>> -			x += (intel_crtc->config->pipe_src_w - 1);
>>> -			y += (intel_crtc->config->pipe_src_h - 1);
>>> +			x += (src_w - 1);
>>> +			y += (src_h - 1);
>>>
>>>    			/* Finding the last pixel of the last line of the display
>>>    			data and adding to linear_offset*/
>>>    			linear_offset +=
>>> -				(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
>>> -				(intel_crtc->config->pipe_src_w - 1) * pixel_size;
>>> +				(src_h - 1) * fb->pitches[0] +
>>> +				(src_w - 1) * pixel_size;
>>>    		}
>>>    	}
>>>
>>> @@ -2747,7 +2757,9 @@ u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
>>>
>>>    static void skylake_update_primary_plane(struct drm_crtc *crtc,
>>>    					 struct drm_framebuffer *fb,
>>> -					 int x, int y)
>>> +					 int x, int y,
>>> +					 int src_w, int src_h,
>>> +					 int crtc_w, int crtc_h)
>>>    {
>>>    	struct drm_device *dev = crtc->dev;
>>>    	struct drm_i915_private *dev_priv = dev->dev_private;
>>> @@ -2767,6 +2779,9 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
>>>    		    PLANE_CTL_PIPE_GAMMA_ENABLE |
>>>    		    PLANE_CTL_PIPE_CSC_ENABLE;
>>>
>>> +	WARN_ONCE(src_w != crtc_w || src_h != crtc_h,
>>> +		  "primary plane doesn't support scaling\n");
>>> +
>>>    	switch (fb->pixel_format) {
>>>    	case DRM_FORMAT_RGB565:
>>>    		plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
>>> @@ -2826,9 +2841,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
>>>
>>>    	I915_WRITE(PLANE_POS(pipe, 0), 0);
>>>    	I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
>>> -	I915_WRITE(PLANE_SIZE(pipe, 0),
>>> -		   (intel_crtc->config->pipe_src_h - 1) << 16 |
>>> -		   (intel_crtc->config->pipe_src_w - 1));
>>> +	I915_WRITE(PLANE_SIZE(pipe, 0), ((src_h - 1) << 16) | (src_w - 1));
>>>    	I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
>>>    	I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
>>>
>>> @@ -2845,12 +2858,18 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
>>>    {
>>>    	struct drm_device *dev = crtc->dev;
>>>    	struct drm_i915_private *dev_priv = dev->dev_private;
>>> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>>>
>>>    	if (dev_priv->display.disable_fbc)
>>>    		dev_priv->display.disable_fbc(dev);
>>>
>>> +	/* FIXME: this will go badly if the fb isn't big enough */
>>>    	to_intel_crtc(crtc)->primary_enabled = true;
>>> -	dev_priv->display.update_primary_plane(crtc, fb, x, y);
>>> +	dev_priv->display.update_primary_plane(crtc, fb, x, y,
>>> +					       intel_crtc->config->pipe_src_w,
>>> +					       intel_crtc->config->pipe_src_h,
>>> +					       intel_crtc->config->pipe_src_w,
>>> +					       intel_crtc->config->pipe_src_h);
>>>
>>>    	return 0;
>>>    }
>>> @@ -2885,7 +2904,11 @@ static void intel_update_primary_planes(struct drm_device *dev)
>>>    			dev_priv->display.update_primary_plane(crtc,
>>>    							       state->base.fb,
>>>    							       state->src.x1 >> 16,
>>> -							       state->src.y1 >> 16);
>>> +							       state->src.y1 >> 16,
>>> +							       drm_rect_width(&state->src) >> 16,
>>> +							       drm_rect_height(&state->src) >> 16,
>>> +							       drm_rect_width(&state->dst),
>>> +							       drm_rect_height(&state->dst));
>> The order in intel_sprite.c is dst x, y, dest w, h, then src x, y, src
>> w, h. But we can sort it later when we are actually merging both the
>> update functions for primary and sprites.
>
> Oh. Failed to notice that. But yeah easy enough to fix when we unify.
>
>>
>> Also, I think it will be better to pass crtc_x, crtc_y also to be used
>> to set plane position.
>
> That's in the next patch.
>
Oops, yes :)
>>
>> -Sonika
>>>    		}
>>>
>>>    		drm_modeset_unlock(&crtc->mutex);
>>> @@ -12070,7 +12093,11 @@ intel_commit_primary_plane(struct drm_plane *plane,
>>>    		dev_priv->display.update_primary_plane(crtc,
>>>    						       state->base.fb,
>>>    						       state->src.x1 >> 16,
>>> -						       state->src.y1 >> 16);
>>> +						       state->src.y1 >> 16,
>>> +						       drm_rect_width(&state->src) >> 16,
>>> +						       drm_rect_height(&state->src) >> 16,
>>> +						       drm_rect_width(&state->dst),
>>> +						       drm_rect_height(&state->dst));
>>>    	}
>>>    }
>>>
>>>
>
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Re: [PATCH v2 5/9] drm/i915: Pass primary plane size to .update_primary_plane()

[Ville Syrjälä]

On Fri, Mar 20, 2015 at 04:23:51PM +0530, Jindal, Sonika wrote:
> 
> 
> On 3/20/2015 3:34 PM, Ville Syrjälä wrote:
> > On Fri, Mar 20, 2015 at 03:19:53PM +0530, Jindal, Sonika wrote:
> >>
> >>
> >> On 3/19/2015 7:58 PM, ville.syrjala@linux.intel.com wrote:
> >>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>>
> >>> In preparation to movable/resizeable primary planes pass the clipped
> >>> plane size to .update_primary_plane().
> >>>
> >>> v2: Pass src size too and use it appropriately (Sonika)
> >>>
> >>> Cc: Sonika Jindal <sonika.jindal@intel.com>
> >>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>> ---
> >>>    drivers/gpu/drm/i915/i915_drv.h      |  4 +-
> >>>    drivers/gpu/drm/i915/intel_display.c | 81 ++++++++++++++++++++++++------------
> >>>    2 files changed, 57 insertions(+), 28 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> >>> index ec23290..054be42 100644
> >>> --- a/drivers/gpu/drm/i915/i915_drv.h
> >>> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >>> @@ -581,7 +581,9 @@ struct drm_i915_display_funcs {
> >>>    			  uint32_t flags);
> >>>    	void (*update_primary_plane)(struct drm_crtc *crtc,
> >>>    				     struct drm_framebuffer *fb,
> >>> -				     int x, int y);
> >>> +				     int x, int y,
> >>> +				     int src_w, int src_h,
> >>> +				     int crtc_w, int crtc_h);
> >>>    	void (*hpd_irq_setup)(struct drm_device *dev);
> >>>    	/* clock updates for mode set */
> >>>    	/* cursor updates */
> >>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> >>> index 5499c8e..2e9fdaa 100644
> >>> --- a/drivers/gpu/drm/i915/intel_display.c
> >>> +++ b/drivers/gpu/drm/i915/intel_display.c
> >>> @@ -2482,7 +2482,9 @@ intel_find_plane_obj(struct intel_crtc *intel_crtc,
> >>>
> >>>    static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> >>>    				      struct drm_framebuffer *fb,
> >>> -				      int x, int y)
> >>> +				      int x, int y,
> >>> +				      int src_w, int src_h,
> >>> +				      int crtc_w, int crtc_h)
> >>>    {
> >>>    	struct drm_device *dev = crtc->dev;
> >>>    	struct drm_i915_private *dev_priv = dev->dev_private;
> >>> @@ -2514,23 +2516,22 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> >>>
> >>>    	dspcntr |= DISPLAY_PLANE_ENABLE;
> >>>
> >>> +	WARN_ONCE(src_w != crtc_w || src_h != crtc_h,
> >>> +		  "primary plane doesn't support scaling\n");
> >>> +
> >>>    	if (INTEL_INFO(dev)->gen < 4) {
> >>>    		if (intel_crtc->pipe == PIPE_B)
> >>>    			dspcntr |= DISPPLANE_SEL_PIPE_B;
> >>> -
> >>> -		/* pipesrc and dspsize control the size that is scaled from,
> >>> -		 * which should always be the user's requested size.
> >>> -		 */
> >>> -		I915_WRITE(DSPSIZE(plane),
> >>> -			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
> >>> -			   (intel_crtc->config->pipe_src_w - 1));
> >>> +		I915_WRITE(DSPSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
> >> Shouldn't this be src_* here, like you are doing for skl? Again it
> >> doesn't matter because no scaling. But still it will look better if we
> >> use same params across.
> >>>    		I915_WRITE(DSPPOS(plane), 0);
> >>>    	} else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
> >>> -		I915_WRITE(PRIMSIZE(plane),
> >>> -			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
> >>> -			   (intel_crtc->config->pipe_src_w - 1));
> >>> +		I915_WRITE(PRIMSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
> >> Same as above.
> >
> > Nope. On CHV there is a scaler on one of the planes and there we'll need
> > to write the dst size into PRIMSIZE, and the src size to another register.
> > So just using the dst size for PRIMSIZE seems like the right choice.
> >
> > Also with ILK-IVB sprites the dst size is also in the plane size register,
> > and the source size is in the plane scale register (eg. DVSSIZE and
> > DVSSSCALE), so this way seems more consistent with most of the platforms.
> >
> Then it would be good to have some comment here?

Dunno. To me it's perfectly clear. SKL is the oddball really, so such
a comment would be better placed there. Although I don't feel a need
to have it there either as the code explains it. And if you don't
believe the code you can always check the spec :)

> > Although if we want to expose the pixel/line doubling as fixed 2x
> > scaling we might need to rethink this again. But I'm going to pretend
> > that there's no such thing for now.
> >
> >>>    		I915_WRITE(PRIMPOS(plane), 0);
> >>>    		I915_WRITE(PRIMCNSTALPHA(plane), 0);
> >>> +	} else {
> >>> +		WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
> >>> +			  crtc_h != intel_crtc->config->pipe_src_h,
> >>> +			  "primary plane size doesn't match pipe size\n");
> >>>    	}
> >>>
> >>>    	switch (fb->pixel_format) {
> >>> @@ -2586,14 +2587,14 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> >>>    	if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
> >>>    		dspcntr |= DISPPLANE_ROTATE_180;
> >>>
> >>> -		x += (intel_crtc->config->pipe_src_w - 1);
> >>> -		y += (intel_crtc->config->pipe_src_h - 1);
> >>> +		x += (src_w - 1);
> >>> +		y += (src_h - 1);
> >>>
> >>>    		/* Finding the last pixel of the last line of the display
> >>>    		data and adding to linear_offset*/
> >>>    		linear_offset +=
> >>> -			(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
> >>> -			(intel_crtc->config->pipe_src_w - 1) * pixel_size;
> >>> +			(src_h - 1) * fb->pitches[0] +
> >>> +			(src_w - 1) * pixel_size;
> >>>    	}
> >>>
> >>>    	I915_WRITE(reg, dspcntr);
> >>> @@ -2611,7 +2612,9 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> >>>
> >>>    static void ironlake_update_primary_plane(struct drm_crtc *crtc,
> >>>    					  struct drm_framebuffer *fb,
> >>> -					  int x, int y)
> >>> +					  int x, int y,
> >>> +					  int src_w, int src_h,
> >>> +					  int crtc_w, int crtc_h)
> >>>    {
> >>>    	struct drm_device *dev = crtc->dev;
> >>>    	struct drm_i915_private *dev_priv = dev->dev_private;
> >>> @@ -2643,6 +2646,13 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
> >>>    	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> >>>    		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
> >>>
> >>> +	WARN_ONCE(src_w != crtc_w || src_h != crtc_h,
> >>> +		  "primary plane doesn't support scaling\n");
> >>> +
> >>> +	WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
> >>> +		  crtc_h != intel_crtc->config->pipe_src_h,
> >>> +		  "primary plane size doesn't match pipe size\n");
> >>> +
> >> I feel this should be part of the check_plane functions where we already
> >> perform many size related checks.
> >
> > This is just an assertion to catch anyone passing bogus values here,
> > and a reminder to people that if they want to extend the primary plane
> > capabilities there's more work to be done.
> >
> Hmm, but still this can be part of the check_plane. No problem, you call.

We still call the .update_primary_plane() directly from some places
without check_plane, so better have it here for now.

> >>>    	switch (fb->pixel_format) {
> >>>    	case DRM_FORMAT_C8:
> >>>    		dspcntr |= DISPPLANE_8BPP;
> >>> @@ -2686,14 +2696,14 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
> >>>    		dspcntr |= DISPPLANE_ROTATE_180;
> >>>
> >>>    		if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
> >>> -			x += (intel_crtc->config->pipe_src_w - 1);
> >>> -			y += (intel_crtc->config->pipe_src_h - 1);
> >>> +			x += (src_w - 1);
> >>> +			y += (src_h - 1);
> >>>
> >>>    			/* Finding the last pixel of the last line of the display
> >>>    			data and adding to linear_offset*/
> >>>    			linear_offset +=
> >>> -				(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
> >>> -				(intel_crtc->config->pipe_src_w - 1) * pixel_size;
> >>> +				(src_h - 1) * fb->pitches[0] +
> >>> +				(src_w - 1) * pixel_size;
> >>>    		}
> >>>    	}
> >>>
> >>> @@ -2747,7 +2757,9 @@ u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
> >>>
> >>>    static void skylake_update_primary_plane(struct drm_crtc *crtc,
> >>>    					 struct drm_framebuffer *fb,
> >>> -					 int x, int y)
> >>> +					 int x, int y,
> >>> +					 int src_w, int src_h,
> >>> +					 int crtc_w, int crtc_h)
> >>>    {
> >>>    	struct drm_device *dev = crtc->dev;
> >>>    	struct drm_i915_private *dev_priv = dev->dev_private;
> >>> @@ -2767,6 +2779,9 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
> >>>    		    PLANE_CTL_PIPE_GAMMA_ENABLE |
> >>>    		    PLANE_CTL_PIPE_CSC_ENABLE;
> >>>
> >>> +	WARN_ONCE(src_w != crtc_w || src_h != crtc_h,
> >>> +		  "primary plane doesn't support scaling\n");
> >>> +
> >>>    	switch (fb->pixel_format) {
> >>>    	case DRM_FORMAT_RGB565:
> >>>    		plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
> >>> @@ -2826,9 +2841,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
> >>>
> >>>    	I915_WRITE(PLANE_POS(pipe, 0), 0);
> >>>    	I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
> >>> -	I915_WRITE(PLANE_SIZE(pipe, 0),
> >>> -		   (intel_crtc->config->pipe_src_h - 1) << 16 |
> >>> -		   (intel_crtc->config->pipe_src_w - 1));
> >>> +	I915_WRITE(PLANE_SIZE(pipe, 0), ((src_h - 1) << 16) | (src_w - 1));
> >>>    	I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
> >>>    	I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
> >>>
> >>> @@ -2845,12 +2858,18 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
> >>>    {
> >>>    	struct drm_device *dev = crtc->dev;
> >>>    	struct drm_i915_private *dev_priv = dev->dev_private;
> >>> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> >>>
> >>>    	if (dev_priv->display.disable_fbc)
> >>>    		dev_priv->display.disable_fbc(dev);
> >>>
> >>> +	/* FIXME: this will go badly if the fb isn't big enough */
> >>>    	to_intel_crtc(crtc)->primary_enabled = true;
> >>> -	dev_priv->display.update_primary_plane(crtc, fb, x, y);
> >>> +	dev_priv->display.update_primary_plane(crtc, fb, x, y,
> >>> +					       intel_crtc->config->pipe_src_w,
> >>> +					       intel_crtc->config->pipe_src_h,
> >>> +					       intel_crtc->config->pipe_src_w,
> >>> +					       intel_crtc->config->pipe_src_h);
> >>>
> >>>    	return 0;
> >>>    }
> >>> @@ -2885,7 +2904,11 @@ static void intel_update_primary_planes(struct drm_device *dev)
> >>>    			dev_priv->display.update_primary_plane(crtc,
> >>>    							       state->base.fb,
> >>>    							       state->src.x1 >> 16,
> >>> -							       state->src.y1 >> 16);
> >>> +							       state->src.y1 >> 16,
> >>> +							       drm_rect_width(&state->src) >> 16,
> >>> +							       drm_rect_height(&state->src) >> 16,
> >>> +							       drm_rect_width(&state->dst),
> >>> +							       drm_rect_height(&state->dst));
> >> The order in intel_sprite.c is dst x, y, dest w, h, then src x, y, src
> >> w, h. But we can sort it later when we are actually merging both the
> >> update functions for primary and sprites.
> >
> > Oh. Failed to notice that. But yeah easy enough to fix when we unify.
> >
> >>
> >> Also, I think it will be better to pass crtc_x, crtc_y also to be used
> >> to set plane position.
> >
> > That's in the next patch.
> >
> Oops, yes :)
> >>
> >> -Sonika
> >>>    		}
> >>>
> >>>    		drm_modeset_unlock(&crtc->mutex);
> >>> @@ -12070,7 +12093,11 @@ intel_commit_primary_plane(struct drm_plane *plane,
> >>>    		dev_priv->display.update_primary_plane(crtc,
> >>>    						       state->base.fb,
> >>>    						       state->src.x1 >> 16,
> >>> -						       state->src.y1 >> 16);
> >>> +						       state->src.y1 >> 16,
> >>> +						       drm_rect_width(&state->src) >> 16,
> >>> +						       drm_rect_height(&state->src) >> 16,
> >>> +						       drm_rect_width(&state->dst),
> >>> +						       drm_rect_height(&state->dst));
> >>>    	}
> >>>    }
> >>>
> >>>
> >

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH v2 5/9] drm/i915: Pass primary plane size to .update_primary_plane()

[sonika]

Looks good to me.

Reviewed-by: Sonika Jindal <sonika.jindal@intel.com>

On Thursday 19 March 2015 07:58 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> In preparation to movable/resizeable primary planes pass the clipped
> plane size to .update_primary_plane().
>
> v2: Pass src size too and use it appropriately (Sonika)
>
> Cc: Sonika Jindal <sonika.jindal@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_drv.h      |  4 +-
>   drivers/gpu/drm/i915/intel_display.c | 81 ++++++++++++++++++++++++------------
>   2 files changed, 57 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index ec23290..054be42 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -581,7 +581,9 @@ struct drm_i915_display_funcs {
>   			  uint32_t flags);
>   	void (*update_primary_plane)(struct drm_crtc *crtc,
>   				     struct drm_framebuffer *fb,
> -				     int x, int y);
> +				     int x, int y,
> +				     int src_w, int src_h,
> +				     int crtc_w, int crtc_h);
>   	void (*hpd_irq_setup)(struct drm_device *dev);
>   	/* clock updates for mode set */
>   	/* cursor updates */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 5499c8e..2e9fdaa 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2482,7 +2482,9 @@ intel_find_plane_obj(struct intel_crtc *intel_crtc,
>   
>   static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>   				      struct drm_framebuffer *fb,
> -				      int x, int y)
> +				      int x, int y,
> +				      int src_w, int src_h,
> +				      int crtc_w, int crtc_h)
>   {
>   	struct drm_device *dev = crtc->dev;
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -2514,23 +2516,22 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>   
>   	dspcntr |= DISPLAY_PLANE_ENABLE;
>   
> +	WARN_ONCE(src_w != crtc_w || src_h != crtc_h,
> +		  "primary plane doesn't support scaling\n");
> +
>   	if (INTEL_INFO(dev)->gen < 4) {
>   		if (intel_crtc->pipe == PIPE_B)
>   			dspcntr |= DISPPLANE_SEL_PIPE_B;
> -
> -		/* pipesrc and dspsize control the size that is scaled from,
> -		 * which should always be the user's requested size.
> -		 */
> -		I915_WRITE(DSPSIZE(plane),
> -			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
> -			   (intel_crtc->config->pipe_src_w - 1));
> +		I915_WRITE(DSPSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
>   		I915_WRITE(DSPPOS(plane), 0);
>   	} else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
> -		I915_WRITE(PRIMSIZE(plane),
> -			   ((intel_crtc->config->pipe_src_h - 1) << 16) |
> -			   (intel_crtc->config->pipe_src_w - 1));
> +		I915_WRITE(PRIMSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
>   		I915_WRITE(PRIMPOS(plane), 0);
>   		I915_WRITE(PRIMCNSTALPHA(plane), 0);
> +	} else {
> +		WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
> +			  crtc_h != intel_crtc->config->pipe_src_h,
> +			  "primary plane size doesn't match pipe size\n");
>   	}
>   
>   	switch (fb->pixel_format) {
> @@ -2586,14 +2587,14 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>   	if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
>   		dspcntr |= DISPPLANE_ROTATE_180;
>   
> -		x += (intel_crtc->config->pipe_src_w - 1);
> -		y += (intel_crtc->config->pipe_src_h - 1);
> +		x += (src_w - 1);
> +		y += (src_h - 1);
>   
>   		/* Finding the last pixel of the last line of the display
>   		data and adding to linear_offset*/
>   		linear_offset +=
> -			(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
> -			(intel_crtc->config->pipe_src_w - 1) * pixel_size;
> +			(src_h - 1) * fb->pitches[0] +
> +			(src_w - 1) * pixel_size;
>   	}
>   
>   	I915_WRITE(reg, dspcntr);
> @@ -2611,7 +2612,9 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>   
>   static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>   					  struct drm_framebuffer *fb,
> -					  int x, int y)
> +					  int x, int y,
> +					  int src_w, int src_h,
> +					  int crtc_w, int crtc_h)
>   {
>   	struct drm_device *dev = crtc->dev;
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -2643,6 +2646,13 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>   	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>   		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
>   
> +	WARN_ONCE(src_w != crtc_w || src_h != crtc_h,
> +		  "primary plane doesn't support scaling\n");
> +
> +	WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
> +		  crtc_h != intel_crtc->config->pipe_src_h,
> +		  "primary plane size doesn't match pipe size\n");
> +
>   	switch (fb->pixel_format) {
>   	case DRM_FORMAT_C8:
>   		dspcntr |= DISPPLANE_8BPP;
> @@ -2686,14 +2696,14 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>   		dspcntr |= DISPPLANE_ROTATE_180;
>   
>   		if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
> -			x += (intel_crtc->config->pipe_src_w - 1);
> -			y += (intel_crtc->config->pipe_src_h - 1);
> +			x += (src_w - 1);
> +			y += (src_h - 1);
>   
>   			/* Finding the last pixel of the last line of the display
>   			data and adding to linear_offset*/
>   			linear_offset +=
> -				(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
> -				(intel_crtc->config->pipe_src_w - 1) * pixel_size;
> +				(src_h - 1) * fb->pitches[0] +
> +				(src_w - 1) * pixel_size;
>   		}
>   	}
>   
> @@ -2747,7 +2757,9 @@ u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
>   
>   static void skylake_update_primary_plane(struct drm_crtc *crtc,
>   					 struct drm_framebuffer *fb,
> -					 int x, int y)
> +					 int x, int y,
> +					 int src_w, int src_h,
> +					 int crtc_w, int crtc_h)
>   {
>   	struct drm_device *dev = crtc->dev;
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -2767,6 +2779,9 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
>   		    PLANE_CTL_PIPE_GAMMA_ENABLE |
>   		    PLANE_CTL_PIPE_CSC_ENABLE;
>   
> +	WARN_ONCE(src_w != crtc_w || src_h != crtc_h,
> +		  "primary plane doesn't support scaling\n");
> +
>   	switch (fb->pixel_format) {
>   	case DRM_FORMAT_RGB565:
>   		plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
> @@ -2826,9 +2841,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
>   
>   	I915_WRITE(PLANE_POS(pipe, 0), 0);
>   	I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
> -	I915_WRITE(PLANE_SIZE(pipe, 0),
> -		   (intel_crtc->config->pipe_src_h - 1) << 16 |
> -		   (intel_crtc->config->pipe_src_w - 1));
> +	I915_WRITE(PLANE_SIZE(pipe, 0), ((src_h - 1) << 16) | (src_w - 1));
>   	I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
>   	I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
>   
> @@ -2845,12 +2858,18 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
>   {
>   	struct drm_device *dev = crtc->dev;
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>   
>   	if (dev_priv->display.disable_fbc)
>   		dev_priv->display.disable_fbc(dev);
>   
> +	/* FIXME: this will go badly if the fb isn't big enough */
>   	to_intel_crtc(crtc)->primary_enabled = true;
> -	dev_priv->display.update_primary_plane(crtc, fb, x, y);
> +	dev_priv->display.update_primary_plane(crtc, fb, x, y,
> +					       intel_crtc->config->pipe_src_w,
> +					       intel_crtc->config->pipe_src_h,
> +					       intel_crtc->config->pipe_src_w,
> +					       intel_crtc->config->pipe_src_h);
>   
>   	return 0;
>   }
> @@ -2885,7 +2904,11 @@ static void intel_update_primary_planes(struct drm_device *dev)
>   			dev_priv->display.update_primary_plane(crtc,
>   							       state->base.fb,
>   							       state->src.x1 >> 16,
> -							       state->src.y1 >> 16);
> +							       state->src.y1 >> 16,
> +							       drm_rect_width(&state->src) >> 16,
> +							       drm_rect_height(&state->src) >> 16,
> +							       drm_rect_width(&state->dst),
> +							       drm_rect_height(&state->dst));
>   		}
>   
>   		drm_modeset_unlock(&crtc->mutex);
> @@ -12070,7 +12093,11 @@ intel_commit_primary_plane(struct drm_plane *plane,
>   		dev_priv->display.update_primary_plane(crtc,
>   						       state->base.fb,
>   						       state->src.x1 >> 16,
> -						       state->src.y1 >> 16);
> +						       state->src.y1 >> 16,
> +						       drm_rect_width(&state->src) >> 16,
> +						       drm_rect_height(&state->src) >> 16,
> +						       drm_rect_width(&state->dst),
> +						       drm_rect_height(&state->dst));
>   	}
>   }
>   

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[PATCH 6/9] drm/i915: Pass the primary plane position to .update_primary_plane()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

In preparation for changing the primary plane position pass the clipped
position to .update_primary_plane().

Cc: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  1 +
 drivers/gpu/drm/i915/intel_display.c | 20 +++++++++++++++-----
 2 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e99eef0..8d8b9a1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -579,6 +579,7 @@ struct drm_i915_display_funcs {
 	void (*update_primary_plane)(struct drm_crtc *crtc,
 				     struct drm_framebuffer *fb,
 				     int x, int y,
+				     int crtc_x, int crtc_y,
 				     int crtc_w, int crtc_h);
 	void (*hpd_irq_setup)(struct drm_device *dev);
 	/* clock updates for mode set */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1a789f0..33680a8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2483,6 +2483,7 @@ intel_find_plane_obj(struct intel_crtc *intel_crtc,
 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 				      struct drm_framebuffer *fb,
 				      int x, int y,
+				      int crtc_x, int crtc_y,
 				      int crtc_w, int crtc_h)
 {
 	struct drm_device *dev = crtc->dev;
@@ -2519,13 +2520,14 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 		if (intel_crtc->pipe == PIPE_B)
 			dspcntr |= DISPPLANE_SEL_PIPE_B;
 		I915_WRITE(DSPSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
-		I915_WRITE(DSPPOS(plane), 0);
+		I915_WRITE(DSPPOS(plane), (crtc_y << 16) | crtc_x);
 	} else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
 		I915_WRITE(PRIMSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
-		I915_WRITE(PRIMPOS(plane), 0);
+		I915_WRITE(PRIMPOS(plane), (crtc_y << 16) | crtc_x);
 		I915_WRITE(PRIMCNSTALPHA(plane), 0);
 	} else {
-		WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
+		WARN_ONCE(crtc_x != 0 || crtc_y != 0 ||
+			  crtc_w != intel_crtc->config->pipe_src_w ||
 			  crtc_h != intel_crtc->config->pipe_src_h,
 			  "primary plane size doesn't match pipe size\n");
 	}
@@ -2609,6 +2611,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 					  struct drm_framebuffer *fb,
 					  int x, int y,
+					  int crtc_x, int crtc_y,
 					  int crtc_w, int crtc_h)
 {
 	struct drm_device *dev = crtc->dev;
@@ -2641,7 +2644,8 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
 
-	WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
+	WARN_ONCE(crtc_x != 0 || crtc_y != 0 ||
+		  crtc_w != intel_crtc->config->pipe_src_w ||
 		  crtc_h != intel_crtc->config->pipe_src_h,
 		  "primary plane size doesn't match pipe size\n");
 
@@ -2750,6 +2754,7 @@ u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
 static void skylake_update_primary_plane(struct drm_crtc *crtc,
 					 struct drm_framebuffer *fb,
 					 int x, int y,
+					 int crtc_x, int crtc_y,
 					 int crtc_w, int crtc_h)
 {
 	struct drm_device *dev = crtc->dev;
@@ -2827,7 +2832,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
 
 	I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
 
-	I915_WRITE(PLANE_POS(pipe, 0), 0);
+	I915_WRITE(PLANE_POS(pipe, 0), (crtc_y << 16) | crtc_x);
 	I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
 	I915_WRITE(PLANE_SIZE(pipe, 0), ((crtc_h - 1) << 16) | (crtc_w - 1));
 	I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
@@ -2854,6 +2859,7 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 	/* FIXME: this will go badly if the fb isn't big enough */
 	to_intel_crtc(crtc)->primary_enabled = true;
 	dev_priv->display.update_primary_plane(crtc, fb, x, y,
+					       0, 0,
 					       intel_crtc->config->pipe_src_w,
 					       intel_crtc->config->pipe_src_h);
 
@@ -2891,6 +2897,8 @@ static void intel_update_primary_planes(struct drm_device *dev)
 							       state->base.fb,
 							       state->src.x1 >> 16,
 							       state->src.y1 >> 16,
+							       state->dst.x1,
+							       state->dst.y1,
 							       drm_rect_width(&state->dst),
 							       drm_rect_height(&state->dst));
 		}
@@ -12027,6 +12035,8 @@ intel_commit_primary_plane(struct drm_plane *plane,
 						       state->base.fb,
 						       state->src.x1 >> 16,
 						       state->src.y1 >> 16,
+						       state->dst.x1,
+						       state->dst.y1,
 						       drm_rect_width(&state->dst),
 						       drm_rect_height(&state->dst));
 	}
-- 
2.0.5

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[PATCH v2 6/9] drm/i915: Pass the primary plane position to .update_primary_plane()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

In preparation for changing the primary plane position pass the clipped
position to .update_primary_plane().

v2: Rebased

Cc: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  1 +
 drivers/gpu/drm/i915/intel_display.c | 20 +++++++++++++++-----
 2 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 054be42..c42e3c5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -583,6 +583,7 @@ struct drm_i915_display_funcs {
 				     struct drm_framebuffer *fb,
 				     int x, int y,
 				     int src_w, int src_h,
+				     int crtc_x, int crtc_y,
 				     int crtc_w, int crtc_h);
 	void (*hpd_irq_setup)(struct drm_device *dev);
 	/* clock updates for mode set */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2e9fdaa..362089f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2484,6 +2484,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 				      struct drm_framebuffer *fb,
 				      int x, int y,
 				      int src_w, int src_h,
+				      int crtc_x, int crtc_y,
 				      int crtc_w, int crtc_h)
 {
 	struct drm_device *dev = crtc->dev;
@@ -2523,13 +2524,14 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 		if (intel_crtc->pipe == PIPE_B)
 			dspcntr |= DISPPLANE_SEL_PIPE_B;
 		I915_WRITE(DSPSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
-		I915_WRITE(DSPPOS(plane), 0);
+		I915_WRITE(DSPPOS(plane), (crtc_y << 16) | crtc_x);
 	} else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
 		I915_WRITE(PRIMSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
-		I915_WRITE(PRIMPOS(plane), 0);
+		I915_WRITE(PRIMPOS(plane), (crtc_y << 16) | crtc_x);
 		I915_WRITE(PRIMCNSTALPHA(plane), 0);
 	} else {
-		WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
+		WARN_ONCE(crtc_x != 0 || crtc_y != 0 ||
+			  crtc_w != intel_crtc->config->pipe_src_w ||
 			  crtc_h != intel_crtc->config->pipe_src_h,
 			  "primary plane size doesn't match pipe size\n");
 	}
@@ -2614,6 +2616,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 					  struct drm_framebuffer *fb,
 					  int x, int y,
 					  int src_w, int src_h,
+					  int crtc_x, int crtc_y,
 					  int crtc_w, int crtc_h)
 {
 	struct drm_device *dev = crtc->dev;
@@ -2649,7 +2652,8 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 	WARN_ONCE(src_w != crtc_w || src_h != crtc_h,
 		  "primary plane doesn't support scaling\n");
 
-	WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
+	WARN_ONCE(crtc_x != 0 || crtc_y != 0 ||
+		  crtc_w != intel_crtc->config->pipe_src_w ||
 		  crtc_h != intel_crtc->config->pipe_src_h,
 		  "primary plane size doesn't match pipe size\n");
 
@@ -2759,6 +2763,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
 					 struct drm_framebuffer *fb,
 					 int x, int y,
 					 int src_w, int src_h,
+					 int crtc_x, int crtc_y,
 					 int crtc_w, int crtc_h)
 {
 	struct drm_device *dev = crtc->dev;
@@ -2839,7 +2844,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
 
 	I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
 
-	I915_WRITE(PLANE_POS(pipe, 0), 0);
+	I915_WRITE(PLANE_POS(pipe, 0), (crtc_y << 16) | crtc_x);
 	I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
 	I915_WRITE(PLANE_SIZE(pipe, 0), ((src_h - 1) << 16) | (src_w - 1));
 	I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
@@ -2866,6 +2871,7 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 	/* FIXME: this will go badly if the fb isn't big enough */
 	to_intel_crtc(crtc)->primary_enabled = true;
 	dev_priv->display.update_primary_plane(crtc, fb, x, y,
+					       0, 0,
 					       intel_crtc->config->pipe_src_w,
 					       intel_crtc->config->pipe_src_h,
 					       intel_crtc->config->pipe_src_w,
@@ -2907,6 +2913,8 @@ static void intel_update_primary_planes(struct drm_device *dev)
 							       state->src.y1 >> 16,
 							       drm_rect_width(&state->src) >> 16,
 							       drm_rect_height(&state->src) >> 16,
+							       state->dst.x1,
+							       state->dst.y1,
 							       drm_rect_width(&state->dst),
 							       drm_rect_height(&state->dst));
 		}
@@ -12096,6 +12104,8 @@ intel_commit_primary_plane(struct drm_plane *plane,
 						       state->src.y1 >> 16,
 						       drm_rect_width(&state->src) >> 16,
 						       drm_rect_height(&state->src) >> 16,
+						       state->dst.x1,
+						       state->dst.y1,
 						       drm_rect_width(&state->dst),
 						       drm_rect_height(&state->dst));
 	}
-- 
2.0.5

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Re: [PATCH v2 6/9] drm/i915: Pass the primary plane position to .update_primary_plane()

[Jindal, Sonika]

On 3/19/2015 7:59 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> In preparation for changing the primary plane position pass the clipped
> position to .update_primary_plane().
>
> v2: Rebased
>
> Cc: Sonika Jindal <sonika.jindal@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_drv.h      |  1 +
>   drivers/gpu/drm/i915/intel_display.c | 20 +++++++++++++++-----
>   2 files changed, 16 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 054be42..c42e3c5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -583,6 +583,7 @@ struct drm_i915_display_funcs {
>   				     struct drm_framebuffer *fb,
>   				     int x, int y,
>   				     int src_w, int src_h,
> +				     int crtc_x, int crtc_y,
>   				     int crtc_w, int crtc_h);
>   	void (*hpd_irq_setup)(struct drm_device *dev);
>   	/* clock updates for mode set */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2e9fdaa..362089f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2484,6 +2484,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>   				      struct drm_framebuffer *fb,
>   				      int x, int y,
>   				      int src_w, int src_h,
> +				      int crtc_x, int crtc_y,
>   				      int crtc_w, int crtc_h)
>   {
>   	struct drm_device *dev = crtc->dev;
> @@ -2523,13 +2524,14 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>   		if (intel_crtc->pipe == PIPE_B)
>   			dspcntr |= DISPPLANE_SEL_PIPE_B;
>   		I915_WRITE(DSPSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
> -		I915_WRITE(DSPPOS(plane), 0);
> +		I915_WRITE(DSPPOS(plane), (crtc_y << 16) | crtc_x);
>   	} else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
>   		I915_WRITE(PRIMSIZE(plane), ((crtc_h - 1) << 16) | (crtc_w - 1));
> -		I915_WRITE(PRIMPOS(plane), 0);
> +		I915_WRITE(PRIMPOS(plane), (crtc_y << 16) | crtc_x);
>   		I915_WRITE(PRIMCNSTALPHA(plane), 0);
>   	} else {
> -		WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
> +		WARN_ONCE(crtc_x != 0 || crtc_y != 0 ||
> +			  crtc_w != intel_crtc->config->pipe_src_w ||
>   			  crtc_h != intel_crtc->config->pipe_src_h,
>   			  "primary plane size doesn't match pipe size\n");
>   	}
> @@ -2614,6 +2616,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>   					  struct drm_framebuffer *fb,
>   					  int x, int y,
>   					  int src_w, int src_h,
> +					  int crtc_x, int crtc_y,
>   					  int crtc_w, int crtc_h)
>   {
>   	struct drm_device *dev = crtc->dev;
> @@ -2649,7 +2652,8 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>   	WARN_ONCE(src_w != crtc_w || src_h != crtc_h,
>   		  "primary plane doesn't support scaling\n");
>
> -	WARN_ONCE(crtc_w != intel_crtc->config->pipe_src_w ||
> +	WARN_ONCE(crtc_x != 0 || crtc_y != 0 ||
> +		  crtc_w != intel_crtc->config->pipe_src_w ||
>   		  crtc_h != intel_crtc->config->pipe_src_h,
>   		  "primary plane size doesn't match pipe size\n");
>
> @@ -2759,6 +2763,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
>   					 struct drm_framebuffer *fb,
>   					 int x, int y,
>   					 int src_w, int src_h,
> +					 int crtc_x, int crtc_y,
>   					 int crtc_w, int crtc_h)
>   {
>   	struct drm_device *dev = crtc->dev;
> @@ -2839,7 +2844,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
>
>   	I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
>
> -	I915_WRITE(PLANE_POS(pipe, 0), 0);
> +	I915_WRITE(PLANE_POS(pipe, 0), (crtc_y << 16) | crtc_x);
>   	I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
>   	I915_WRITE(PLANE_SIZE(pipe, 0), ((src_h - 1) << 16) | (src_w - 1));
>   	I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
> @@ -2866,6 +2871,7 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
>   	/* FIXME: this will go badly if the fb isn't big enough */
>   	to_intel_crtc(crtc)->primary_enabled = true;
>   	dev_priv->display.update_primary_plane(crtc, fb, x, y,
> +					       0, 0,
>   					       intel_crtc->config->pipe_src_w,
>   					       intel_crtc->config->pipe_src_h,
>   					       intel_crtc->config->pipe_src_w,
> @@ -2907,6 +2913,8 @@ static void intel_update_primary_planes(struct drm_device *dev)
>   							       state->src.y1 >> 16,
>   							       drm_rect_width(&state->src) >> 16,
>   							       drm_rect_height(&state->src) >> 16,
> +							       state->dst.x1,
> +							       state->dst.y1,
>   							       drm_rect_width(&state->dst),
>   							       drm_rect_height(&state->dst));
>   		}
> @@ -12096,6 +12104,8 @@ intel_commit_primary_plane(struct drm_plane *plane,
>   						       state->src.y1 >> 16,
>   						       drm_rect_width(&state->src) >> 16,
>   						       drm_rect_height(&state->src) >> 16,
> +						       state->dst.x1,
> +						       state->dst.y1,
>   						       drm_rect_width(&state->dst),
>   						       drm_rect_height(&state->dst));
>   	}
>
Reviewed-by: Sonika Jindal <sonika.jindal@intel.com>
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[PATCH 7/9] drm/i915: Update watermarks after the derived plane state is uptodate

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

When enabling planes during .crtc_enable() we currently want to update
the watermarks before enabling the planes. We already do it once just
before enabling the pipe, but at that point out derived plane state is
still out of whack, so we need to do it again after the .atomic_check()
hooks have been called.

What this means is now we could actually start to trust the derived
plane state (clipped size, 'visible', etc.) in the watermark code.

The pre pipe enable watermark update is supposed to be just make sure
the other pipes are ready to have their FIFOs potentially reduced, so we
need to keep it there as well.

Since we don't yet have proper two-part watermark update leave the
watermakrs alone in the plane disable case. This way they'll get updated
only after the planes and pipe have all been turned off.

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 33680a8..a9201a7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4167,6 +4167,8 @@ static void _intel_crtc_enable_planes(struct intel_crtc *crtc)
 			state->visible = false;
 	}
 
+	intel_update_watermarks(&crtc->base);
+
 	crtc_funcs->atomic_begin(&crtc->base);
 
 	for_each_intel_plane(dev, plane) {
@@ -4213,6 +4215,8 @@ static void _intel_crtc_disable_planes(struct intel_crtc *crtc)
 	}
 
 	crtc_funcs->atomic_flush(&crtc->base);
+
+	/* we'll defer watermark update to after the pipe has been disabled */
 }
 
 void hsw_enable_ips(struct intel_crtc *crtc)
-- 
2.0.5

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Re: [PATCH 7/9] drm/i915: Update watermarks after the derived plane state is uptodate

[Matt Roper]

On Tue, Mar 10, 2015 at 01:15:27PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> When enabling planes during .crtc_enable() we currently want to update
> the watermarks before enabling the planes. We already do it once just
> before enabling the pipe, but at that point out derived plane state is
> still out of whack, so we need to do it again after the .atomic_check()
> hooks have been called.
> 
> What this means is now we could actually start to trust the derived
> plane state (clipped size, 'visible', etc.) in the watermark code.
> 
> The pre pipe enable watermark update is supposed to be just make sure
> the other pipes are ready to have their FIFOs potentially reduced, so we
> need to keep it there as well.
> 
> Since we don't yet have proper two-part watermark update leave the
> watermakrs alone in the plane disable case. This way they'll get updated
> only after the planes and pipe have all been turned off.
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 33680a8..a9201a7 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4167,6 +4167,8 @@ static void _intel_crtc_enable_planes(struct intel_crtc *crtc)
>  			state->visible = false;
>  	}
>  
> +	intel_update_watermarks(&crtc->base);
> +
>  	crtc_funcs->atomic_begin(&crtc->base);
>  
>  	for_each_intel_plane(dev, plane) {
> @@ -4213,6 +4215,8 @@ static void _intel_crtc_disable_planes(struct intel_crtc *crtc)
>  	}
>  
>  	crtc_funcs->atomic_flush(&crtc->base);
> +
> +	/* we'll defer watermark update to after the pipe has been disabled */
>  }
>  
>  void hsw_enable_ips(struct intel_crtc *crtc)
> -- 
> 2.0.5
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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Re: [PATCH 7/9] drm/i915: Update watermarks after the derived plane state is uptodate

[Daniel Vetter]

On Tue, Mar 10, 2015 at 10:13:52AM -0700, Matt Roper wrote:
> On Tue, Mar 10, 2015 at 01:15:27PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > When enabling planes during .crtc_enable() we currently want to update
> > the watermarks before enabling the planes. We already do it once just
> > before enabling the pipe, but at that point out derived plane state is
> > still out of whack, so we need to do it again after the .atomic_check()
> > hooks have been called.
> > 
> > What this means is now we could actually start to trust the derived
> > plane state (clipped size, 'visible', etc.) in the watermark code.
> > 
> > The pre pipe enable watermark update is supposed to be just make sure
> > the other pipes are ready to have their FIFOs potentially reduced, so we
> > need to keep it there as well.
> > 
> > Since we don't yet have proper two-part watermark update leave the
> > watermakrs alone in the plane disable case. This way they'll get updated
> > only after the planes and pipe have all been turned off.
> > 
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

Since I'm not sold on the atomic_check changes in your series I'll hold
off on this one for now.
-Daniel
-- 
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+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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[PATCH 8/9] drm/i915: Use state->visible in wm calculation

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 24 +++++++++++++++++-------
 1 file changed, 17 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a06a2c7..499e054 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1955,6 +1955,7 @@ static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	enum pipe pipe = intel_crtc->pipe;
 	struct drm_plane *plane;
+	const struct intel_plane_state *state;
 
 	if (!intel_crtc->active)
 		return;
@@ -1962,13 +1963,22 @@ static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
 	p->active = true;
 	p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
 	p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
-	p->pri.bytes_per_pixel = crtc->primary->state->fb->bits_per_pixel / 8;
-	p->cur.bytes_per_pixel = 4;
-	p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
-	p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
-	/* TODO: for now, assume primary and cursor planes are always enabled. */
-	p->pri.enabled = true;
-	p->cur.enabled = true;
+
+	state = to_intel_plane_state(crtc->primary->state);
+	if (state->visible) {
+		p->pri.enabled = true;
+		p->pri.bytes_per_pixel =
+			drm_format_plane_cpp(state->base.fb->pixel_format, 0);
+		p->pri.horiz_pixels = drm_rect_width(&state->dst);
+	}
+
+	state = to_intel_plane_state(crtc->cursor->state);
+	if (state->visible) {
+		p->cur.enabled = true;
+		p->cur.bytes_per_pixel =
+			drm_format_plane_cpp(state->base.fb->pixel_format, 0);
+		p->cur.horiz_pixels = state->base.crtc_w;
+	}
 
 	drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
 		struct intel_plane *intel_plane = to_intel_plane(plane);
-- 
2.0.5

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Re: [PATCH 8/9] drm/i915: Use state->visible in wm calculation

[Matt Roper]

On Tue, Mar 10, 2015 at 01:15:28PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

The actual diff here needs to be regenerated since my patch got merged
and changed this area of the code, but your final solution looks right
to me.  The main difference between your patch here and what got merged
yesterday is that your patch starts using state->visible rather than
state->fb, which is the right move to make.

So assuming you rebase your changes onto the latest code,
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 24 +++++++++++++++++-------
>  1 file changed, 17 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a06a2c7..499e054 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1955,6 +1955,7 @@ static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	enum pipe pipe = intel_crtc->pipe;
>  	struct drm_plane *plane;
> +	const struct intel_plane_state *state;
>  
>  	if (!intel_crtc->active)
>  		return;
> @@ -1962,13 +1963,22 @@ static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
>  	p->active = true;
>  	p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
>  	p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
> -	p->pri.bytes_per_pixel = crtc->primary->state->fb->bits_per_pixel / 8;
> -	p->cur.bytes_per_pixel = 4;
> -	p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
> -	p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
> -	/* TODO: for now, assume primary and cursor planes are always enabled. */
> -	p->pri.enabled = true;
> -	p->cur.enabled = true;
> +
> +	state = to_intel_plane_state(crtc->primary->state);
> +	if (state->visible) {
> +		p->pri.enabled = true;
> +		p->pri.bytes_per_pixel =
> +			drm_format_plane_cpp(state->base.fb->pixel_format, 0);
> +		p->pri.horiz_pixels = drm_rect_width(&state->dst);
> +	}
> +
> +	state = to_intel_plane_state(crtc->cursor->state);
> +	if (state->visible) {
> +		p->cur.enabled = true;
> +		p->cur.bytes_per_pixel =
> +			drm_format_plane_cpp(state->base.fb->pixel_format, 0);
> +		p->cur.horiz_pixels = state->base.crtc_w;
> +	}
>  
>  	drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
>  		struct intel_plane *intel_plane = to_intel_plane(plane);
> -- 
> 2.0.5
> 
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IoTG Platform Enabling & Development
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Re: [PATCH 8/9] drm/i915: Use state->visible in wm calculation

[Ville Syrjälä]

On Tue, Mar 10, 2015 at 10:19:56AM -0700, Matt Roper wrote:
> On Tue, Mar 10, 2015 at 01:15:28PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The actual diff here needs to be regenerated since my patch got merged
> and changed this area of the code, but your final solution looks right
> to me.  The main difference between your patch here and what got merged
> yesterday is that your patch starts using state->visible rather than
> state->fb, which is the right move to make.
> 
> So assuming you rebase your changes onto the latest code,
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

Yep, I was expecting a slight conflict here since you were working in the
same vicinity. So I'll respin this one on top of the latest stuff.

And I should change the vlv/chv code while I'm at it...

> 
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 24 +++++++++++++++++-------
> >  1 file changed, 17 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index a06a2c7..499e054 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -1955,6 +1955,7 @@ static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
> >  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> >  	enum pipe pipe = intel_crtc->pipe;
> >  	struct drm_plane *plane;
> > +	const struct intel_plane_state *state;
> >  
> >  	if (!intel_crtc->active)
> >  		return;
> > @@ -1962,13 +1963,22 @@ static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
> >  	p->active = true;
> >  	p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
> >  	p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
> > -	p->pri.bytes_per_pixel = crtc->primary->state->fb->bits_per_pixel / 8;
> > -	p->cur.bytes_per_pixel = 4;
> > -	p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
> > -	p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
> > -	/* TODO: for now, assume primary and cursor planes are always enabled. */
> > -	p->pri.enabled = true;
> > -	p->cur.enabled = true;
> > +
> > +	state = to_intel_plane_state(crtc->primary->state);
> > +	if (state->visible) {
> > +		p->pri.enabled = true;
> > +		p->pri.bytes_per_pixel =
> > +			drm_format_plane_cpp(state->base.fb->pixel_format, 0);
> > +		p->pri.horiz_pixels = drm_rect_width(&state->dst);
> > +	}
> > +
> > +	state = to_intel_plane_state(crtc->cursor->state);
> > +	if (state->visible) {
> > +		p->cur.enabled = true;
> > +		p->cur.bytes_per_pixel =
> > +			drm_format_plane_cpp(state->base.fb->pixel_format, 0);
> > +		p->cur.horiz_pixels = state->base.crtc_w;
> > +	}
> >  
> >  	drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
> >  		struct intel_plane *intel_plane = to_intel_plane(plane);
> > -- 
> > 2.0.5
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795

-- 
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Intel OTC
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[PATCH v2 8/9] drm/i915: Use state->visible in wm calculation

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

v2: Rebase and update the vlv/chv code as well

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 42 ++++++++++++++++++-----------------------
 1 file changed, 18 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e18f0fd..a8c6578 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -915,18 +915,16 @@ static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
 	int entries, prec_mult, drain_latency, pixel_size;
 	int clock = intel_crtc->config->base.adjusted_mode.crtc_clock;
 	const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
+	const struct intel_plane_state *state =
+		to_intel_plane_state(plane->state);
 
-	/*
-	 * FIXME the plane might have an fb
-	 * but be invisible (eg. due to clipping)
-	 */
-	if (!intel_crtc->active || !plane->state->fb)
+	if (!state->visible)
 		return 0;
 
 	if (WARN(clock == 0, "Pixel clock is zero!\n"))
 		return 0;
 
-	pixel_size = drm_format_plane_cpp(plane->state->fb->pixel_format, 0);
+	pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 
 	if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
 		return 0;
@@ -953,15 +951,13 @@ static int vlv_compute_wm(struct intel_crtc *crtc,
 			  int fifo_size)
 {
 	int clock, entries, pixel_size;
+	const struct intel_plane_state *state =
+		to_intel_plane_state(plane->base.state);
 
-	/*
-	 * FIXME the plane might have an fb
-	 * but be invisible (eg. due to clipping)
-	 */
-	if (!crtc->active || !plane->base.state->fb)
+	if (!state->visible)
 		return 0;
 
-	pixel_size = drm_format_plane_cpp(plane->base.state->fb->pixel_format, 0);
+	pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 	clock = crtc->config->base.adjusted_mode.crtc_clock;
 
 	entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
@@ -2037,6 +2033,7 @@ static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	enum pipe pipe = intel_crtc->pipe;
 	struct drm_plane *plane;
+	const struct intel_plane_state *state;
 
 	if (!intel_crtc->active)
 		return;
@@ -2045,24 +2042,21 @@ static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
 	p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
 	p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
 
-	if (crtc->primary->state->fb) {
+	state = to_intel_plane_state(crtc->primary->state);
+	if (state->visible) {
 		p->pri.enabled = true;
 		p->pri.bytes_per_pixel =
-			crtc->primary->state->fb->bits_per_pixel / 8;
-	} else {
-		p->pri.enabled = false;
-		p->pri.bytes_per_pixel = 0;
+			drm_format_plane_cpp(state->base.fb->pixel_format, 0);
+		p->pri.horiz_pixels = drm_rect_width(&state->dst);
 	}
 
-	if (crtc->cursor->state->fb) {
+	state = to_intel_plane_state(crtc->cursor->state);
+	if (state->visible) {
 		p->cur.enabled = true;
-		p->cur.bytes_per_pixel = 4;
-	} else {
-		p->cur.enabled = false;
-		p->cur.bytes_per_pixel = 0;
+		p->cur.bytes_per_pixel =
+			drm_format_plane_cpp(state->base.fb->pixel_format, 0);
+		p->cur.horiz_pixels = state->base.crtc_w;
 	}
-	p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
-	p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
 
 	drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
 		struct intel_plane *intel_plane = to_intel_plane(plane);
-- 
2.0.5

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[PATCH 9/9] drm/i915: Don't re-enable an explicitly disabled primary plane due to sprite coverage changes

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

When the sprite is covering the entire pipe (and color keying is not
enabled) we currently try to automagically disable the primary plane
which is fully covered by the sprite.

Now that .crtc_disable() will simply disable planes by setting the
state->visible to false, the sprite code will actually end up
re-enabling the primary after it got disabled, and then we proceed to
turn off the pipe and are greeted with some warnings from
assert_plane_disabled().

The code doing the automagic disable of covered planes needs to
rewritten to do things correctly as part of the atomic update (or simply
removed), but in the meantime add a a bit of duct tape and simply have
the sprite code check the primary plane's state->visible before
re-enabling it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_sprite.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index a828736..7286497 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1287,7 +1287,9 @@ intel_commit_sprite_plane(struct drm_plane *plane,
 	intel_plane->obj = obj;
 
 	if (intel_crtc->active) {
-		intel_crtc->primary_enabled = !state->hides_primary;
+		intel_crtc->primary_enabled =
+			to_intel_plane_state(crtc->primary->state)->visible &&
+			!state->hides_primary;
 
 		if (state->visible) {
 			crtc_x = state->dst.x1;
-- 
2.0.5

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Re: [PATCH 9/9] drm/i915: Don't re-enable an explicitly disabled primary plane due to sprite coverage changes

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5924
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  282/282              282/282
ILK                                  308/308              308/308
SNB                                  307/307              307/307
IVB                                  375/375              375/375
BYT                                  294/294              294/294
HSW                                  385/385              385/385
BDW                                  315/315              315/315
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
Note: You need to pay more attention to line start with '*'
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Re: [PATCH 9/9] drm/i915: Don't re-enable an explicitly disabled primary plane due to sprite coverage changes

[Daniel Vetter]

On Tue, Mar 10, 2015 at 01:15:29PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> When the sprite is covering the entire pipe (and color keying is not
> enabled) we currently try to automagically disable the primary plane
> which is fully covered by the sprite.
> 
> Now that .crtc_disable() will simply disable planes by setting the
> state->visible to false, the sprite code will actually end up
> re-enabling the primary after it got disabled, and then we proceed to
> turn off the pipe and are greeted with some warnings from
> assert_plane_disabled().
> 
> The code doing the automagic disable of covered planes needs to
> rewritten to do things correctly as part of the atomic update (or simply
> removed), but in the meantime add a a bit of duct tape and simply have
> the sprite code check the primary plane's state->visible before
> re-enabling it.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_sprite.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index a828736..7286497 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1287,7 +1287,9 @@ intel_commit_sprite_plane(struct drm_plane *plane,
>  	intel_plane->obj = obj;
>  
>  	if (intel_crtc->active) {
> -		intel_crtc->primary_enabled = !state->hides_primary;
> +		intel_crtc->primary_enabled =
> +			to_intel_plane_state(crtc->primary->state)->visible &&
> +			!state->hides_primary;

Can't we just nuke intel_crtc->primary_enabled with all your work to tread
state through functions correctly?
-Daniel

>  
>  		if (state->visible) {
>  			crtc_x = state->dst.x1;
> -- 
> 2.0.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH 9/9] drm/i915: Don't re-enable an explicitly disabled primary plane due to sprite coverage changes

[Ville Syrjälä]

On Wed, Mar 11, 2015 at 11:00:32AM +0100, Daniel Vetter wrote:
> On Tue, Mar 10, 2015 at 01:15:29PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > When the sprite is covering the entire pipe (and color keying is not
> > enabled) we currently try to automagically disable the primary plane
> > which is fully covered by the sprite.
> > 
> > Now that .crtc_disable() will simply disable planes by setting the
> > state->visible to false, the sprite code will actually end up
> > re-enabling the primary after it got disabled, and then we proceed to
> > turn off the pipe and are greeted with some warnings from
> > assert_plane_disabled().
> > 
> > The code doing the automagic disable of covered planes needs to
> > rewritten to do things correctly as part of the atomic update (or simply
> > removed), but in the meantime add a a bit of duct tape and simply have
> > the sprite code check the primary plane's state->visible before
> > re-enabling it.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_sprite.c | 4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > index a828736..7286497 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -1287,7 +1287,9 @@ intel_commit_sprite_plane(struct drm_plane *plane,
> >  	intel_plane->obj = obj;
> >  
> >  	if (intel_crtc->active) {
> > -		intel_crtc->primary_enabled = !state->hides_primary;
> > +		intel_crtc->primary_enabled =
> > +			to_intel_plane_state(crtc->primary->state)->visible &&
> > +			!state->hides_primary;
> 
> Can't we just nuke intel_crtc->primary_enabled with all your work to tread
> state through functions correctly?

Not if we want to keep this magic "disable primary when sprite covers
it" code.

I think ideally we'd do the .atomic_check() for all planes, and then
once all planes are clipped and whatnot, we could check which planes
are fully covered by something opaque and make them invisible. Though
that would perhaps mean that we always have to .atomic_check() all the
planes even if only one of them changed.

> -Daniel
> 
> >  
> >  		if (state->visible) {
> >  			crtc_x = state->dst.x1;
> > -- 
> > 2.0.5
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 9/9] drm/i915: Don't re-enable an explicitly disabled primary plane due to sprite coverage changes

[Daniel Vetter]

On Wed, Mar 11, 2015 at 12:09:24PM +0200, Ville Syrjälä wrote:
> On Wed, Mar 11, 2015 at 11:00:32AM +0100, Daniel Vetter wrote:
> > On Tue, Mar 10, 2015 at 01:15:29PM +0200, ville.syrjala@linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > When the sprite is covering the entire pipe (and color keying is not
> > > enabled) we currently try to automagically disable the primary plane
> > > which is fully covered by the sprite.
> > > 
> > > Now that .crtc_disable() will simply disable planes by setting the
> > > state->visible to false, the sprite code will actually end up
> > > re-enabling the primary after it got disabled, and then we proceed to
> > > turn off the pipe and are greeted with some warnings from
> > > assert_plane_disabled().
> > > 
> > > The code doing the automagic disable of covered planes needs to
> > > rewritten to do things correctly as part of the atomic update (or simply
> > > removed), but in the meantime add a a bit of duct tape and simply have
> > > the sprite code check the primary plane's state->visible before
> > > re-enabling it.
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_sprite.c | 4 +++-
> > >  1 file changed, 3 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > > index a828736..7286497 100644
> > > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > > @@ -1287,7 +1287,9 @@ intel_commit_sprite_plane(struct drm_plane *plane,
> > >  	intel_plane->obj = obj;
> > >  
> > >  	if (intel_crtc->active) {
> > > -		intel_crtc->primary_enabled = !state->hides_primary;
> > > +		intel_crtc->primary_enabled =
> > > +			to_intel_plane_state(crtc->primary->state)->visible &&
> > > +			!state->hides_primary;
> > 
> > Can't we just nuke intel_crtc->primary_enabled with all your work to tread
> > state through functions correctly?
> 
> Not if we want to keep this magic "disable primary when sprite covers
> it" code.
> 
> I think ideally we'd do the .atomic_check() for all planes, and then
> once all planes are clipped and whatnot, we could check which planes
> are fully covered by something opaque and make them invisible. Though
> that would perhaps mean that we always have to .atomic_check() all the
> planes even if only one of them changed.

Yeah that's what I've meant with removing primary_enabled - this should
flow into the compuation of ->visible for the primary plane. Keeping
random state out of state objects will be serious trouble.

Also if we do this the wm code will grow clue about the situation and stop
allocating fifo space for the primary plane in that case too.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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