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* [PATCH] drm/i915/guc: Enable GuC submission, where supported
@ 2016-01-05 19:10 yu.dai
  2016-01-06 10:20 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: yu.dai @ 2016-01-05 19:10 UTC (permalink / raw)
  To: intel-gfx

From: Alex Dai <yu.dai@intel.com>

This is to enable command submission via GuC.

Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
---
 drivers/gpu/drm/i915/i915_params.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 8d90c25..2ca4690 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -55,7 +55,7 @@ struct i915_params i915 __read_mostly = {
 	.verbose_state_checks = 1,
 	.nuclear_pageflip = 0,
 	.edp_vswing = 0,
-	.enable_guc_submission = false,
+	.enable_guc_submission = true,
 	.guc_log_level = -1,
 };
 
@@ -198,7 +198,7 @@ MODULE_PARM_DESC(edp_vswing,
 		 "2=default swing(400mV))");
 
 module_param_named_unsafe(enable_guc_submission, i915.enable_guc_submission, bool, 0400);
-MODULE_PARM_DESC(enable_guc_submission, "Enable GuC submission (default:false)");
+MODULE_PARM_DESC(enable_guc_submission, "Enable GuC submission (default:true)");
 
 module_param_named(guc_log_level, i915.guc_log_level, int, 0400);
 MODULE_PARM_DESC(guc_log_level,
-- 
2.5.0

_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH v5 1/1] drm/i915/bxt: Check BIOS RC6 setup before enabling RC6
@ 2016-01-14 15:56 Sagar Arun Kamble
  2016-01-14 16:30 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Sagar Arun Kamble @ 2016-01-14 15:56 UTC (permalink / raw)
  To: intel-gfx; +Cc: shashidhar.hiremath

RC6 setup is shared between BIOS and Driver. BIOS sets up subset of RC6
setup registers. If those are not setup Driver should not enable RC6.
For implementing this, driver can check RC_CTRL0 and RC_CTRL1 values
to know if BIOS has enabled HW/SW RC6.
This will also enable user to control RC6 using BIOS settings alone.
RC6 related instability can be avoided by disabling via BIOS settings
till driver fixes it.

v2: Had placed logic in gen8 function by mistake. Fixed it.
Ensuring RPM is not enabled in case BIOS disabled RC6.

v3: Need to disable RPM if RC6 is disabled due to BIOS settings. (Daniel)
Runtime PM enabling happens before gen9_enable_rc6.
Moved the updation of enable_rc6 parameter in intel_uncore_sanitize.

v4: Added elaborate check for BIOS RC6 setup. Prepared check_pctx for bxt. (Imre)

v5: Caching reserved stolen base and size in the driver private data.
Reorganized RC6 setup check. Moved from gen9_enable_rc6 to intel_uncore_sanitize. (Imre)

Cc: Imre Deak <imre.deak@intel.com>
Change-Id: If89518708e133be6b3c7c6f90869fb66224b7b87
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h        |  1 +
 drivers/gpu/drm/i915/i915_gem_gtt.h    |  2 ++
 drivers/gpu/drm/i915/i915_gem_stolen.c | 39 ++++++++++++++++++----
 drivers/gpu/drm/i915/i915_reg.h        | 11 +++++++
 drivers/gpu/drm/i915/intel_drv.h       |  1 +
 drivers/gpu/drm/i915/intel_pm.c        | 59 ++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_uncore.c    |  4 +++
 7 files changed, 109 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cf7e0fc..0c8e61c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3223,6 +3223,7 @@ int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
 					 u64 end);
 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
 				 struct drm_mm_node *node);
+int i915_gem_init_stolen_reserved(struct drm_device *dev);
 int i915_gem_init_stolen(struct drm_device *dev);
 void i915_gem_cleanup_stolen(struct drm_device *dev);
 struct drm_i915_gem_object *
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index b448ad8..20ff6ca 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -343,6 +343,8 @@ struct i915_gtt {
 
 	size_t stolen_size;		/* Total size of stolen memory */
 	size_t stolen_usable_size;	/* Total size minus BIOS reserved */
+	size_t stolen_reserved_base;
+	size_t stolen_reserved_size;
 	u64 mappable_end;		/* End offset that we can CPU map */
 	struct io_mapping *mappable;	/* Mapping to our CPU mappable region */
 	phys_addr_t mappable_base;	/* PA of our GMADR */
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 3476877..d5a65d9 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -386,14 +386,12 @@ static void bdw_get_stolen_reserved(struct drm_i915_private *dev_priv,
 		*size = stolen_top - *base;
 }
 
-int i915_gem_init_stolen(struct drm_device *dev)
+int i915_gem_init_stolen_reserved(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	unsigned long reserved_total, reserved_base = 0, reserved_size;
+	unsigned long reserved_base = 0, reserved_size;
 	unsigned long stolen_top;
 
-	mutex_init(&dev_priv->mm.stolen_lock);
-
 #ifdef CONFIG_INTEL_IOMMU
 	if (intel_iommu_gfx_mapped && INTEL_INFO(dev)->gen < 8) {
 		DRM_INFO("DMAR active, disabling use of stolen memory\n");
@@ -458,9 +456,38 @@ int i915_gem_init_stolen(struct drm_device *dev)
 		return 0;
 	}
 
+	dev_priv->gtt.stolen_reserved_base = reserved_base;
+	dev_priv->gtt.stolen_reserved_size = reserved_size;
+
+	return 0;
+}
+
+int i915_gem_init_stolen(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	unsigned long reserved_total;
+	unsigned long stolen_top;
+
+	mutex_init(&dev_priv->mm.stolen_lock);
+
+#ifdef CONFIG_INTEL_IOMMU
+	if (intel_iommu_gfx_mapped && INTEL_INFO(dev)->gen < 8) {
+		DRM_INFO("DMAR active, disabling use of stolen memory\n");
+		return 0;
+	}
+#endif
+
+	if (dev_priv->gtt.stolen_size == 0)
+		return 0;
+
+	if (dev_priv->mm.stolen_base == 0)
+		return 0;
+
+	stolen_top = dev_priv->mm.stolen_base + dev_priv->gtt.stolen_size;
+
 	/* It is possible for the reserved area to end before the end of stolen
-	 * memory, so just consider the start. */
-	reserved_total = stolen_top - reserved_base;
+	* memory, so just consider the start. */
+	reserved_total = stolen_top - dev_priv->gtt.stolen_reserved_base;
 
 	DRM_DEBUG_KMS("Memory reserved for graphics device: %zuK, usable: %luK\n",
 		      dev_priv->gtt.stolen_size >> 10,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 007ae83..19ddf79 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6765,6 +6765,16 @@ enum skl_disp_power_wells {
 
 #define  VLV_PMWGICZ				_MMIO(0x1300a4)
 
+#define  RC6_LOCATION				_MMIO(0xD40)
+#define  RC6_CTX_IN_DRAM			1
+#define  RC6_CTX_BASE				_MMIO(0xD48)
+#define  RC6_CTX_BASE_MASK			0xFFFFFFF0
+#define  PWRCTX_MAXCNT_RCSUNIT			_MMIO(0x2054)
+#define  PWRCTX_MAXCNT_VCSUNIT0			_MMIO(0x12054)
+#define  PWRCTX_MAXCNT_BCSUNIT			_MMIO(0x22054)
+#define  PWRCTX_MAXCNT_VECSUNIT			_MMIO(0x1A054)
+#define  PWRCTX_MAXCNT_VCSUNIT1			_MMIO(0x1C054)
+#define  IDLE_TIME_MASK				0xFFFFF
 #define  FORCEWAKE				_MMIO(0xA18C)
 #define  FORCEWAKE_VLV				_MMIO(0x1300b0)
 #define  FORCEWAKE_ACK_VLV			_MMIO(0x1300b4)
@@ -6903,6 +6913,7 @@ enum skl_disp_power_wells {
 #define GEN6_RPDEUC				_MMIO(0xA084)
 #define GEN6_RPDEUCSW				_MMIO(0xA088)
 #define GEN6_RC_STATE				_MMIO(0xA094)
+#define RC6_STATE				(1<<18)
 #define GEN6_RC1_WAKE_RATE_LIMIT		_MMIO(0xA098)
 #define GEN6_RC6_WAKE_RATE_LIMIT		_MMIO(0xA09C)
 #define GEN6_RC6pp_WAKE_RATE_LIMIT		_MMIO(0xA0A0)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0438b57..f22baef 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1564,6 +1564,7 @@ void skl_wm_get_hw_state(struct drm_device *dev);
 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
 			  struct skl_ddb_allocation *ddb /* out */);
 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
+int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6);
 
 /* intel_sdvo.c */
 bool intel_sdvo_init(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 02fe081..c9a32a4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4518,12 +4518,68 @@ static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
 			      (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
 }
 
-static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
+static bool bxt_check_bios_rc6_setup(const struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	bool enable_rc6 = true;
+	unsigned long rc6_ctx_base;
+	bool bios_hw_rc6_enabled, bios_sw_rc6_enabled;
+
+	bios_hw_rc6_enabled = I915_READ(GEN6_RC_CONTROL) &
+				(GEN6_RC_CTL_RC6_ENABLE |
+					GEN6_RC_CTL_HW_ENABLE);
+	bios_sw_rc6_enabled = !(I915_READ(GEN6_RC_CONTROL) &
+				GEN6_RC_CTL_HW_ENABLE) &&
+				(I915_READ(GEN6_RC_STATE) & RC6_STATE);
+
+	if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
+		DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
+		enable_rc6 = false;
+	}
+
+	rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
+	if (!((rc6_ctx_base >= dev_priv->gtt.stolen_reserved_base) &&
+		(rc6_ctx_base <= (dev_priv->gtt.stolen_reserved_base +
+					dev_priv->gtt.stolen_reserved_size)))) {
+		DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
+		enable_rc6 = false;
+	}
+
+	if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
+	      ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
+	      ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
+	      ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
+		DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
+		enable_rc6 = false;
+	}
+
+	if (HAS_BSD2(dev) &&
+		((I915_READ(PWRCTX_MAXCNT_VCSUNIT1) & IDLE_TIME_MASK) > 1)) {
+		DRM_DEBUG_KMS("VCSUNIT1 Idle wait time not set properly.\n");
+		enable_rc6 = false;
+	}
+
+	if (!bios_hw_rc6_enabled && !bios_sw_rc6_enabled) {
+		DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
+		enable_rc6 = false;
+	}
+
+	return enable_rc6;
+}
+
+int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
 {
 	/* No RC6 before Ironlake and code is gone for ilk. */
 	if (INTEL_INFO(dev)->gen < 6)
 		return 0;
 
+	if (IS_BROXTON(dev)) {
+		if (!bxt_check_bios_rc6_setup(dev)) {
+			DRM_INFO("RC6 disabled by BIOS\n");
+			return 0;
+		}
+	}
+
 	/* Respect the kernel parameter if it is set */
 	if (enable_rc6 >= 0) {
 		int mask;
@@ -6014,7 +6070,6 @@ void intel_init_gt_powersave(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
 	/*
 	 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
 	 * requirement.
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 277e60a..43fc3e8 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -359,6 +359,10 @@ void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake)
 
 void intel_uncore_sanitize(struct drm_device *dev)
 {
+	i915_gem_init_stolen_reserved(dev);
+
+	i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
+
 	/* BIOS often leaves RC6 enabled, but disable it for hw init */
 	intel_disable_gt_powersave(dev);
 }
-- 
1.9.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH] drm/i915/bios: Fix the sequence size calculations for MIPI seq v3
@ 2016-01-14 15:12 Jani Nikula
  2016-01-14 16:20 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Jani Nikula @ 2016-01-14 15:12 UTC (permalink / raw)
  To: intel-gfx

Two errors in a single line. The size was read from the wrong offset,
and the end index didn't take the five bytes for sequence byte and size
of sequence into account. Fix it all, and break up the calculations a
bit to make it clearer.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reported-by: Mika Kahola <mika.kahola@intel.com>
Fixes: 2a33d93486f2 ("drm/i915/bios: add support for MIPI sequence block v3")
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_bios.c | 17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 12e2f8b8bf9c..bf62a19c8f69 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -842,6 +842,7 @@ static int goto_next_sequence_v3(const u8 *data, int index, int total)
 {
 	int seq_end;
 	u16 len;
+	u32 size_of_sequence;
 
 	/*
 	 * Could skip sequence based on Size of Sequence alone, but also do some
@@ -852,14 +853,24 @@ static int goto_next_sequence_v3(const u8 *data, int index, int total)
 		return 0;
 	}
 
-	seq_end = index + *((const u32 *)(data + 1));
+	/* Skip Sequence Byte. */
+	index++;
+
+	/*
+	 * Size of Sequence. Excludes the Sequence Byte and the size itself,
+	 * includes MIPI_SEQ_ELEM_END byte, excludes the final MIPI_SEQ_END
+	 * byte.
+	 */
+	size_of_sequence = *((const uint32_t *)(data + index));
+	index += 4;
+
+	seq_end = index + size_of_sequence;
 	if (seq_end > total) {
 		DRM_ERROR("Invalid sequence size\n");
 		return 0;
 	}
 
-	/* Skip Sequence Byte and Size of Sequence. */
-	for (index = index + 5; index < total; index += len) {
+	for (; index < total; index += len) {
 		u8 operation_byte = *(data + index);
 		index++;
 
-- 
2.1.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH] drm/i915: Decouple execbuf uAPI from internal implementation
@ 2016-01-14 15:02 Tvrtko Ursulin
  2016-01-14 15:49 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Tvrtko Ursulin @ 2016-01-14 15:02 UTC (permalink / raw)
  To: Intel-gfx; +Cc: Daniel Vetter

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

At the moment execbuf ring selection is fully coupled to
internal ring ids which is not a good thing on its own.

This dependency is also spread between two source files and
not spelled out at either side which makes it hidden and
fragile.

This patch decouples this dependency by introducing an explicit
translation table of execbuf uAPI to ring id close to the only
call site (i915_gem_do_execbuffer).

This way we are free to change driver internal implementation
details without breaking userspace. All state relating to the
uAPI is now contained in, or next to, i915_gem_do_execbuffer.

As a side benefit, this patch decreases the compiled size
of i915_gem_do_execbuffer.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_drv.h            |   4 +-
 drivers/gpu/drm/i915/i915_gem.c            |   2 +
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 103 +++++++++++++----------------
 drivers/gpu/drm/i915/intel_ringbuffer.h    |  10 +--
 4 files changed, 56 insertions(+), 63 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index eb7bb97f7316..35d5d6099a44 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -334,7 +334,7 @@ struct drm_i915_file_private {
 		unsigned boosts;
 	} rps;
 
-	struct intel_engine_cs *bsd_ring;
+	unsigned int bsd_ring;
 };
 
 enum intel_dpll_id {
@@ -1300,7 +1300,7 @@ struct i915_gem_mm {
 	bool busy;
 
 	/* the indicator for dispatch video commands on two BSD rings */
-	int bsd_ring_dispatch_index;
+	unsigned int bsd_ring_dispatch_index;
 
 	/** Bit 6 swizzling required for X tiling */
 	uint32_t bit_6_swizzle_x;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ddc21d4b388d..26e6842f2df3 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5112,6 +5112,8 @@ int i915_gem_open(struct drm_device *dev, struct drm_file *file)
 	spin_lock_init(&file_priv->mm.lock);
 	INIT_LIST_HEAD(&file_priv->mm.request_list);
 
+	file_priv->bsd_ring = -1;
+
 	ret = i915_gem_context_open(dev, file);
 	if (ret)
 		kfree(file_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index d469c4779ff5..cd8646a23780 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1328,33 +1328,23 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
 
 /**
  * Find one BSD ring to dispatch the corresponding BSD command.
- * The Ring ID is returned.
+ * The ring index is returned.
  */
-static int gen8_dispatch_bsd_ring(struct drm_device *dev,
-				  struct drm_file *file)
+static unsigned int
+gen8_dispatch_bsd_ring(struct drm_i915_private *dev_priv, struct drm_file *file)
 {
-	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_i915_file_private *file_priv = file->driver_priv;
 
-	/* Check whether the file_priv is using one ring */
-	if (file_priv->bsd_ring)
-		return file_priv->bsd_ring->id;
-	else {
-		/* If no, use the ping-pong mechanism to select one ring */
-		int ring_id;
-
-		mutex_lock(&dev->struct_mutex);
-		if (dev_priv->mm.bsd_ring_dispatch_index == 0) {
-			ring_id = VCS;
-			dev_priv->mm.bsd_ring_dispatch_index = 1;
-		} else {
-			ring_id = VCS2;
-			dev_priv->mm.bsd_ring_dispatch_index = 0;
-		}
-		file_priv->bsd_ring = &dev_priv->ring[ring_id];
-		mutex_unlock(&dev->struct_mutex);
-		return ring_id;
+	/* Check whether the file_priv has already selected one ring. */
+	if ((int)file_priv->bsd_ring < 0) {
+		/* If not, use the ping-pong mechanism to select one. */
+		mutex_lock(&dev_priv->dev->struct_mutex);
+		file_priv->bsd_ring = dev_priv->mm.bsd_ring_dispatch_index;
+		dev_priv->mm.bsd_ring_dispatch_index ^= 1;
+		mutex_unlock(&dev_priv->dev->struct_mutex);
 	}
+
+	return file_priv->bsd_ring;
 }
 
 static struct drm_i915_gem_object *
@@ -1377,6 +1367,16 @@ eb_get_batch(struct eb_vmas *eb)
 	return vma->obj;
 }
 
+#define I915_USER_RINGS (4)
+
+static const enum intel_ring_id user_ring_map[I915_USER_RINGS + 1] = {
+	[I915_EXEC_DEFAULT]	= RCS,
+	[I915_EXEC_RENDER]	= RCS,
+	[I915_EXEC_BLT]		= BCS,
+	[I915_EXEC_BSD]		= VCS,
+	[I915_EXEC_VEBOX]	= VECS
+};
+
 static int
 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
 		       struct drm_file *file,
@@ -1393,6 +1393,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
 	struct i915_execbuffer_params params_master; /* XXX: will be removed later */
 	struct i915_execbuffer_params *params = &params_master;
 	const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
+	unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
 	u32 dispatch_flags;
 	int ret;
 	bool need_relocs;
@@ -1414,49 +1415,39 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
 	if (args->flags & I915_EXEC_IS_PINNED)
 		dispatch_flags |= I915_DISPATCH_PINNED;
 
-	if ((args->flags & I915_EXEC_RING_MASK) > LAST_USER_RING) {
-		DRM_DEBUG("execbuf with unknown ring: %d\n",
-			  (int)(args->flags & I915_EXEC_RING_MASK));
+	if (user_ring_id > I915_USER_RINGS) {
+		DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id);
 		return -EINVAL;
 	}
 
-	if (((args->flags & I915_EXEC_RING_MASK) != I915_EXEC_BSD) &&
+	if ((user_ring_id != I915_EXEC_BSD) &&
 	    ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
 		DRM_DEBUG("execbuf with non bsd ring but with invalid "
 			"bsd dispatch flags: %d\n", (int)(args->flags));
 		return -EINVAL;
-	} 
-
-	if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT)
-		ring = &dev_priv->ring[RCS];
-	else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) {
-		if (HAS_BSD2(dev)) {
-			int ring_id;
-
-			switch (args->flags & I915_EXEC_BSD_MASK) {
-			case I915_EXEC_BSD_DEFAULT:
-				ring_id = gen8_dispatch_bsd_ring(dev, file);
-				ring = &dev_priv->ring[ring_id];
-				break;
-			case I915_EXEC_BSD_RING1:
-				ring = &dev_priv->ring[VCS];
-				break;
-			case I915_EXEC_BSD_RING2:
-				ring = &dev_priv->ring[VCS2];
-				break;
-			default:
-				DRM_DEBUG("execbuf with unknown bsd ring: %d\n",
-					  (int)(args->flags & I915_EXEC_BSD_MASK));
-				return -EINVAL;
-			}
-		} else
-			ring = &dev_priv->ring[VCS];
-	} else
-		ring = &dev_priv->ring[(args->flags & I915_EXEC_RING_MASK) - 1];
+	}
+
+	if (user_ring_id == I915_EXEC_BSD && HAS_BSD2(dev)) {
+		unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
+
+		if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
+			bsd_idx = gen8_dispatch_bsd_ring(dev_priv, file);
+		} else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
+			   bsd_idx <= I915_EXEC_BSD_RING2) {
+			bsd_idx--;
+		} else {
+			DRM_DEBUG("execbuf with unknown bsd ring: %u\n",
+				  bsd_idx);
+			return -EINVAL;
+		}
+
+		ring = &dev_priv->ring[_VCS(bsd_idx)];
+	} else {
+		ring = &dev_priv->ring[user_ring_map[user_ring_id]];
+	}
 
 	if (!intel_ring_initialized(ring)) {
-		DRM_DEBUG("execbuf with invalid ring: %d\n",
-			  (int)(args->flags & I915_EXEC_RING_MASK));
+		DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id);
 		return -EINVAL;
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 7349d9258191..fdc220fc2b18 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -148,14 +148,14 @@ struct  i915_ctx_workarounds {
 struct  intel_engine_cs {
 	const char	*name;
 	enum intel_ring_id {
-		RCS = 0x0,
-		VCS,
+		RCS = 0,
 		BCS,
-		VECS,
-		VCS2
+		VCS,
+		VCS2,	/* Keep instances of the same type engine together. */
+		VECS
 	} id;
 #define I915_NUM_RINGS 5
-#define LAST_USER_RING (VECS + 1)
+#define _VCS(n) (VCS + (n))
 	u32		mmio_base;
 	struct		drm_device *dev;
 	struct intel_ringbuffer *buffer;
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH 0/8] drm/i915: Some more fb offsets[] prep stuff
@ 2016-01-14 13:22 ville.syrjala
  2016-01-14 14:49 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: ville.syrjala @ 2016-01-14 13:22 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Yanked a few more prep patches from my earlier fb offsets[] work [1]. First
few have r-bs, the rest don't.

The last two patches are new. Things just tickled my OCD a bit too much so
had to deal with them.

[1] http://lists.freedesktop.org/archives/intel-gfx/2015-October/078050.html

Ville Syrjälä (8):
  drm/i915: Don't leak framebuffer_references if drm_framebuffer_init()
    fails
  drm/i915: Set i915_ggtt_view_normal type explicitly
  drm/i915: Pass the dma_addr_t array as const to rotate_pages()
  drm/i915: Rename the rotated gtt view member to 'rotated'
  drm/i915: Pass stride to rotate_pages()
  drm/i915: Pass rotation_info to intel_rotate_fb_obj_pages()
  drm/i915: Make display gtt offsets u32
  drm/i915: Standardize on 'cpp' for bytes per pixel

 drivers/gpu/drm/i915/i915_gem_gtt.c  |  22 +++---
 drivers/gpu/drm/i915/i915_gem_gtt.h  |   2 +-
 drivers/gpu/drm/i915/intel_display.c |  49 +++++++-------
 drivers/gpu/drm/i915/intel_drv.h     |  12 ++--
 drivers/gpu/drm/i915/intel_pm.c      | 128 +++++++++++++++++------------------
 drivers/gpu/drm/i915/intel_sprite.c  |  40 +++++------
 6 files changed, 123 insertions(+), 130 deletions(-)

-- 
2.4.10

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^ permalink raw reply	[flat|nested] 76+ messages in thread
* [PATCH 1/2] drm/i915: Start WM computation from scratch on ILK-BDW
@ 2016-01-14 12:53 ville.syrjala
  2016-01-14 14:20 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: ville.syrjala @ 2016-01-14 12:53 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

ilk_compute_pipe_wm() assumes as zeroed pipe_wm structure when it
starts. We used to pass such a zeroed struct in, but this got broken
when the pipe_wm structure got embedded in the crtc state.

To fix it without too much fuzz, we need to resort to a memset().

Fixes: 4e0963c7663b ("drm/i915: Calculate pipe watermarks into CRTC state (v3)")
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9df9e9a22f3c..e9f4e6e7b736 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2317,6 +2317,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
 		return PTR_ERR(cstate);
 
 	pipe_wm = &cstate->wm.optimal.ilk;
+	memset(pipe_wm, 0, sizeof(*pipe_wm));
 
 	for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
 		ps = drm_atomic_get_plane_state(state,
-- 
2.4.10

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^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH] drm/i915: Clear pending reset requests during suspend
@ 2016-01-14 10:49 Arun Siluvery
  2016-01-14 12:20 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Arun Siluvery @ 2016-01-14 10:49 UTC (permalink / raw)
  To: intel-gfx; +Cc: Mika Kuoppala

Pending reset requests are cleared before suspending, they should be picked up
after resume when new work is submitted.

This is originally added as part of TDR patches for Gen8 from Tomas Elf which
are under review, as suggested by Chris this is extracted as a separate patch
as it can be useful now.

Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f17a2b0..09ed83e 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -594,6 +594,13 @@ static int i915_drm_suspend(struct drm_device *dev)
 		goto out;
 	}
 
+	/*
+	 * Clear any pending reset requests. They should be picked up
+	 * after resume when new work is submitted
+	 */
+	atomic_clear_mask(I915_RESET_IN_PROGRESS_FLAG,
+			  &dev_priv->gpu_error.reset_counter);
+
 	intel_guc_suspend(dev);
 
 	intel_suspend_gt_powersave(dev);
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH v14 0/11] Support for creating/using Stolen memory backed objects
@ 2016-01-14  6:16 ankitprasad.r.sharma
  2016-01-14 11:20 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: ankitprasad.r.sharma @ 2016-01-14  6:16 UTC (permalink / raw)
  To: intel-gfx; +Cc: akash.goel, shashidhar.hiremath, Ankitprasad Sharma

From: Ankitprasad Sharma <ankitprasad.r.sharma@intel.com>

This patch series adds support for creating/using Stolen memory backed
objects.

Despite being a unified memory architecture (UMA) some bits of memory
are more equal than others. In particular we have the thorny issue of
stolen memory, memory stolen from the system by the BIOS and reserved
for igfx use. Stolen memory is required for some functions of the GPU
and display engine, but in general it goes wasted. Whilst we cannot
return it back to the system, we need to find some other method for
utilising it. As we do not support direct access to the physical address
in the stolen region, it behaves like a different class of memory,
closer in kin to local GPU memory. This strongly suggests that we need a
placement model like TTM if we are to fully utilize these discrete
chunks of differing memory.

To add support for creating Stolen memory backed objects, we extend the
drm_i915_gem_create structure, by adding a new flag through which user
can specify the preference to allocate the object from stolen memory,
which if set, an attempt will be made to allocate the object from stolen
memory subject to the availability of free space in the stolen region.

This patch series adds support for clearing buffer objects via CPU/GTT.
This is particularly useful for clearing out the memory from stolen
region, but can also be used for other shmem allocated objects. Currently
being used for buffers allocated in the stolen region. Also adding support
for stealing purgable stolen pages, if we run out of stolen memory when
trying to allocate an object.

v2: Added support for read/write from/to objects not backed by
shmem using the pread/pwrite interface.
Also extended the current get_aperture ioctl to retrieve the
total and available size of the stolen region.

v3: Removed the extended get_aperture ioctl patch 5 (to be submitted as
part of other patch series), addressed comments by Chris about pread/pwrite
for non shmem backed objects.

v4: Rebased to the latest drm-intel-nightly.

v5: Addressed comments, replaced patch 1/4 "Clearing buffers via blitter
engine" by "Clearing buffers via CPU/GTT".

v6: Rebased to the latest drm-intel-nightly, Addressed comments, updated
stolen memory purging logic by maintaining a list for purgable stolen
memory objects, enabled pread/pwrite for all non-shmem backed objects
without tiling restrictions.

v7: Addressed comments, compiler optimization, new patch added for correct
error code propagation to the userspace.

v8: Added a new patch to the series to Migrate stolen objects before
hibernation, as stolen memory is not preserved across hibernation. Added
correct error propagation for shmem as well non-shmem backed object allocation.

v9: Addressed comments, use of insert_page helper function to map object page
by page which can be helpful in low aperture space availability.

v10: Addressed comments, use insert_page for clearing out the stolen memory

v11: Addressed comments, 3 new patches added to support allocation from Stolen
memory
1. Allow use of i915_gem_object_get_dma_address for stolen backed objects
2. Use insert_page for pwrite_fast
3. Fail the execbuff using stolen objects as batchbuffers

v12: Addressed comments, Removed patch "Fail the execbuff using stolen objects
as batchbuffers"

v13: Addressed comments, Added 2 patches to detect Intel RST and disable stolen
for persistent data if RST device found
1. acpi: Export acpi_bus_type
2. drm/i915: Disable use of stolen area by User when Intel RST is present

v14: Addressed comments, Added 2 base patches to the series
1. drm/i915: Add support for mapping an object page by page
2. drm/i915: Introduce i915_gem_object_get_dma_address()

This can be verified using IGT tests: igt/gem_stolen, igt/gem_create

Ankitprasad Sharma (7):
  drm/i915: Use insert_page for pwrite_fast
  drm/i915: Clearing buffer objects via CPU/GTT
  drm/i915: Support for creating Stolen memory backed objects
  drm/i915: Propagating correct error codes to the userspace
  drm/i915: Support for pread/pwrite from/to non shmem backed objects
  acpi: Export acpi_bus_type
  drm/i915: Disable use of stolen area by User when Intel RST is present

Chris Wilson (4):
  drm/i915: Add support for mapping an object page by page
  drm/i915: Introduce i915_gem_object_get_dma_address()
  drm/i915: Add support for stealing purgable stolen pages
  drm/i915: Migrate stolen objects before hibernation

 drivers/acpi/bus.c                           |   1 +
 drivers/char/agp/intel-gtt.c                 |   9 +
 drivers/gpu/drm/i915/i915_debugfs.c          |   6 +-
 drivers/gpu/drm/i915/i915_dma.c              |   3 +
 drivers/gpu/drm/i915/i915_drv.c              |  17 +-
 drivers/gpu/drm/i915/i915_drv.h              |  58 ++-
 drivers/gpu/drm/i915/i915_gem.c              | 576 +++++++++++++++++++++++----
 drivers/gpu/drm/i915/i915_gem_batch_pool.c   |   4 +-
 drivers/gpu/drm/i915/i915_gem_context.c      |   4 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c          |  49 +++
 drivers/gpu/drm/i915/i915_gem_gtt.h          |   5 +
 drivers/gpu/drm/i915/i915_gem_render_state.c |   7 +-
 drivers/gpu/drm/i915/i915_gem_stolen.c       | 281 +++++++++++--
 drivers/gpu/drm/i915/i915_guc_submission.c   |  52 ++-
 drivers/gpu/drm/i915/intel_acpi.c            |  20 +
 drivers/gpu/drm/i915/intel_display.c         |   5 +-
 drivers/gpu/drm/i915/intel_fbdev.c           |  12 +-
 drivers/gpu/drm/i915/intel_lrc.c             |  10 +-
 drivers/gpu/drm/i915/intel_overlay.c         |   4 +-
 drivers/gpu/drm/i915/intel_pm.c              |  13 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c      |  27 +-
 include/drm/intel-gtt.h                      |   3 +
 include/uapi/drm/i915_drm.h                  |  19 +
 23 files changed, 1022 insertions(+), 163 deletions(-)

-- 
1.9.1

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^ permalink raw reply	[flat|nested] 76+ messages in thread
* [PATCH 00/20] TDR/watchdog support for gen8
@ 2016-01-13 17:28 Arun Siluvery
  2016-01-14  8:30 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Arun Siluvery @ 2016-01-13 17:28 UTC (permalink / raw)
  To: intel-gfx

These patches were sent previously a while ago[1] so rebased on latest nightly
and resending again for feedback.

This patch series adds support for Per engine resets, watchdog timeout
reset. Please see [1] for detailed description.

[1] http://lists.freedesktop.org/archives/intel-gfx/2015-October/078696.html

Tim Gore (1):
  drm/i915: drm/i915 changes to simulated hangs

Tomas Elf (19):
  drm/i915: Make i915_gem_reset_ring_status() public
  drm/i915: Generalise common GPU engine reset request/unrequest code
  drm/i915: TDR / per-engine hang recovery support for gen8.
  drm/i915: TDR / per-engine hang detection
  drm/i915: Extending i915_gem_check_wedge to check engine reset in
    progress
  drm/i915: Reinstate hang recovery work queue.
  drm/i915: Watchdog timeout: Hang detection integration into error
    handler
  drm/i915: Watchdog timeout: IRQ handler for gen8
  drm/i915: Watchdog timeout: Ringbuffer command emission for gen8
  drm/i915: Watchdog timeout: DRM kernel interface enablement
  drm/i915: Fake lost context event interrupts through forced CSB
    checking.
  drm/i915: Debugfs interface for per-engine hang recovery.
  drm/i915: Test infrastructure for context state inconsistency
    simulation
  drm/i915: TDR/watchdog trace points.
  drm/i915: Port of Added scheduler support to __wait_request() calls
  drm/i915: Fix __i915_wait_request() behaviour during hang detection.
  drm/i915: Extended error state with TDR count, watchdog count and
    engine reset count
  drm/i915: TDR / per-engine hang recovery kernel docs
  drm/i915: Enable TDR / per-engine hang recovery

 Documentation/DocBook/gpu.tmpl          | 476 ++++++++++++++++++
 drivers/gpu/drm/i915/i915_debugfs.c     | 163 +++++-
 drivers/gpu/drm/i915/i915_dma.c         |  80 +++
 drivers/gpu/drm/i915/i915_drv.c         | 328 ++++++++++++
 drivers/gpu/drm/i915/i915_drv.h         |  90 +++-
 drivers/gpu/drm/i915/i915_gem.c         | 152 +++++-
 drivers/gpu/drm/i915/i915_gpu_error.c   |   8 +-
 drivers/gpu/drm/i915/i915_irq.c         | 263 ++++++++--
 drivers/gpu/drm/i915/i915_params.c      |  19 +
 drivers/gpu/drm/i915/i915_params.h      |   2 +
 drivers/gpu/drm/i915/i915_reg.h         |   9 +
 drivers/gpu/drm/i915/i915_trace.h       | 354 ++++++++++++-
 drivers/gpu/drm/i915/intel_display.c    |   5 +-
 drivers/gpu/drm/i915/intel_lrc.c        | 865 +++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_lrc.h        |  16 +-
 drivers/gpu/drm/i915/intel_lrc_tdr.h    |  39 ++
 drivers/gpu/drm/i915/intel_ringbuffer.c |  90 +++-
 drivers/gpu/drm/i915/intel_ringbuffer.h |  95 ++++
 drivers/gpu/drm/i915/intel_uncore.c     | 197 +++++++-
 include/uapi/drm/i915_drm.h             |   5 +-
 20 files changed, 3134 insertions(+), 122 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_lrc_tdr.h

-- 
1.9.1

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^ permalink raw reply	[flat|nested] 76+ messages in thread
* [PATCH v10] drm/i915: Extend LRC pinning to cover GPU context writeback
@ 2016-01-13 16:19 Nick Hoath
  2016-01-14  7:20 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Nick Hoath @ 2016-01-13 16:19 UTC (permalink / raw)
  To: intel-gfx; +Cc: Daniel Vetter

Use the first retired request on a new context to unpin
the old context. This ensures that the hw context remains
bound until it has been written back to by the GPU.
Now that the context is pinned until later in the request/context
lifecycle, it no longer needs to be pinned from context_queue to
retire_requests.
This fixes an issue with GuC submission where the GPU might not
have finished writing back the context before it is unpinned. This
results in a GPU hang.

v2: Moved the new pin to cover GuC submission (Alex Dai)
    Moved the new unpin to request_retire to fix coverage leak
v3: Added switch to default context if freeing a still pinned
    context just in case the hw was actually still using it
v4: Unwrapped context unpin to allow calling without a request
v5: Only create a switch to idle context if the ring doesn't
    already have a request pending on it (Alex Dai)
    Rename unsaved to dirty to avoid double negatives (Dave Gordon)
    Changed _no_req postfix to __ prefix for consistency (Dave Gordon)
    Split out per engine cleanup from context_free as it
    was getting unwieldy
    Corrected locking (Dave Gordon)
v6: Removed some bikeshedding (Mika Kuoppala)
    Added explanation of the GuC hang that this fixes (Daniel Vetter)
v7: Removed extra per request pinning from ring reset code (Alex Dai)
    Added forced ring unpin/clean in error case in context free (Alex Dai)
v8: Renamed lrc specific last_context to lrc_last_context as there
    were some reset cases where the codepaths leaked (Mika Kuoppala)
    NULL'd last_context in reset case - there was a pointer leak
    if someone did reset->close context.
v9: Rebase over "Fix context/engine cleanup order"
v10: Rebase over nightly, remove WARN_ON which caused the
    dependency on dev.

Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
Issue: VIZ-4277
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: David Gordon <david.s.gordon@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Alex Dai <yu.dai@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         |   1 +
 drivers/gpu/drm/i915/i915_gem.c         |   3 +
 drivers/gpu/drm/i915/intel_lrc.c        | 138 ++++++++++++++++++++++++++------
 drivers/gpu/drm/i915/intel_lrc.h        |   1 +
 drivers/gpu/drm/i915/intel_ringbuffer.h |   1 +
 5 files changed, 121 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 104bd18..d28e10a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -882,6 +882,7 @@ struct intel_context {
 	struct {
 		struct drm_i915_gem_object *state;
 		struct intel_ringbuffer *ringbuf;
+		bool dirty;
 		int pin_count;
 	} engine[I915_NUM_RINGS];
 
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ddc21d4..7b79405 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1413,6 +1413,9 @@ static void i915_gem_request_retire(struct drm_i915_gem_request *request)
 {
 	trace_i915_gem_request_retire(request);
 
+	if (i915.enable_execlists)
+		intel_lr_context_complete_check(request);
+
 	/* We know the GPU must have read the request to have
 	 * sent us the seqno + interrupt, so use the position
 	 * of tail of the request to update the last known position
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 5027699..b661058 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -585,9 +585,6 @@ static int execlists_context_queue(struct drm_i915_gem_request *request)
 	struct drm_i915_gem_request *cursor;
 	int num_elements = 0;
 
-	if (request->ctx != ring->default_context)
-		intel_lr_context_pin(request);
-
 	i915_gem_request_reference(request);
 
 	spin_lock_irq(&ring->execlist_lock);
@@ -763,6 +760,13 @@ intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
 	if (intel_ring_stopped(ring))
 		return;
 
+	if (request->ctx != ring->default_context) {
+		if (!request->ctx->engine[ring->id].dirty) {
+			intel_lr_context_pin(request);
+			request->ctx->engine[ring->id].dirty = true;
+		}
+	}
+
 	if (dev_priv->guc.execbuf_client)
 		i915_guc_submit(dev_priv->guc.execbuf_client, request);
 	else
@@ -989,12 +993,6 @@ void intel_execlists_retire_requests(struct intel_engine_cs *ring)
 	spin_unlock_irq(&ring->execlist_lock);
 
 	list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
-		struct intel_context *ctx = req->ctx;
-		struct drm_i915_gem_object *ctx_obj =
-				ctx->engine[ring->id].state;
-
-		if (ctx_obj && (ctx != ring->default_context))
-			intel_lr_context_unpin(req);
 		list_del(&req->execlist_link);
 		i915_gem_request_unreference(req);
 	}
@@ -1089,21 +1087,39 @@ reset_pin_count:
 	return ret;
 }
 
-void intel_lr_context_unpin(struct drm_i915_gem_request *rq)
+static void __intel_lr_context_unpin(struct intel_engine_cs *ring,
+		struct intel_context *ctx)
 {
-	struct intel_engine_cs *ring = rq->ring;
-	struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
-	struct intel_ringbuffer *ringbuf = rq->ringbuf;
-
+	struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
+	struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
 	if (ctx_obj) {
 		WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
-		if (--rq->ctx->engine[ring->id].pin_count == 0) {
+		if (--ctx->engine[ring->id].pin_count == 0) {
 			intel_unpin_ringbuffer_obj(ringbuf);
 			i915_gem_object_ggtt_unpin(ctx_obj);
 		}
 	}
 }
 
+void intel_lr_context_unpin(struct drm_i915_gem_request *rq)
+{
+	__intel_lr_context_unpin(rq->ring, rq->ctx);
+}
+
+void intel_lr_context_complete_check(struct drm_i915_gem_request *req)
+{
+	struct intel_engine_cs *ring = req->ring;
+
+	if (ring->lrc_last_context && ring->lrc_last_context != req->ctx &&
+			ring->lrc_last_context->engine[ring->id].dirty) {
+		__intel_lr_context_unpin(
+				ring,
+				ring->lrc_last_context);
+		ring->lrc_last_context->engine[ring->id].dirty = false;
+	}
+	ring->lrc_last_context = req->ctx;
+}
+
 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
 {
 	int ret, i;
@@ -2347,6 +2363,74 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o
 }
 
 /**
+ * intel_lr_context_clean_ring() - clean the ring specific parts of an LRC
+ * @ctx: the LR context being freed.
+ * @ring: the engine being cleaned
+ * @ctx_obj: the hw context being unreferenced
+ * @ringbuf: the ringbuf being freed
+ *
+ * Take care of cleaning up the per-engine backing
+ * objects and the logical ringbuffer.
+ */
+static void
+intel_lr_context_clean_ring(struct intel_context *ctx,
+			    struct intel_engine_cs *ring,
+			    struct drm_i915_gem_object *ctx_obj,
+			    struct intel_ringbuffer *ringbuf)
+{
+	int ret;
+
+	if (ctx == ring->default_context) {
+		intel_unpin_ringbuffer_obj(ringbuf);
+		i915_gem_object_ggtt_unpin(ctx_obj);
+	}
+
+	if (ctx->engine[ring->id].dirty) {
+		struct drm_i915_gem_request *req = NULL;
+
+		/**
+		 * If there is already a request pending on
+		 * this ring, wait for that to complete,
+		 * otherwise create a switch to idle request
+		 */
+		if (list_empty(&ring->request_list)) {
+			int ret;
+
+			ret = i915_gem_request_alloc(
+					ring,
+					ring->default_context,
+					&req);
+			if (!ret)
+				i915_add_request(req);
+			else
+				DRM_DEBUG("Failed to ensure context saved");
+		} else {
+			req = list_first_entry(
+					&ring->request_list,
+					typeof(*req), list);
+		}
+		if (req) {
+			ret = i915_wait_request(req);
+			if (ret != 0) {
+				/**
+				 * If we get here, there's probably been a ring
+				 * reset, so we just clean up the dirty flag.&
+				 * pin count.
+				 */
+				ctx->engine[ring->id].dirty = false;
+				__intel_lr_context_unpin(
+					ring,
+					ctx);
+			}
+		}
+	}
+
+	WARN_ON(ctx->engine[ring->id].pin_count);
+	intel_ringbuffer_free(ringbuf);
+	drm_gem_object_unreference(&ctx_obj->base);
+}
+
+/**
  * intel_lr_context_free() - free the LRC specific bits of a context
  * @ctx: the LR context to free.
  *
@@ -2358,7 +2444,7 @@ void intel_lr_context_free(struct intel_context *ctx)
 {
 	int i;
 
-	for (i = 0; i < I915_NUM_RINGS; i++) {
+	for (i = 0; i < I915_NUM_RINGS; ++i) {
 		struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
 
 		if (ctx_obj) {
@@ -2366,13 +2452,10 @@ void intel_lr_context_free(struct intel_context *ctx)
 					ctx->engine[i].ringbuf;
 			struct intel_engine_cs *ring = ringbuf->ring;
 
-			if (ctx == ring->default_context) {
-				intel_unpin_ringbuffer_obj(ringbuf);
-				i915_gem_object_ggtt_unpin(ctx_obj);
-			}
-			WARN_ON(ctx->engine[ring->id].pin_count);
-			intel_ringbuffer_free(ringbuf);
-			drm_gem_object_unreference(&ctx_obj->base);
+			intel_lr_context_clean_ring(ctx,
+						    ring,
+						    ctx_obj,
+						    ringbuf);
 		}
 	}
 }
@@ -2548,5 +2631,14 @@ void intel_lr_context_reset(struct drm_device *dev,
 
 		ringbuf->head = 0;
 		ringbuf->tail = 0;
+
+		if (ctx->engine[ring->id].dirty) {
+			__intel_lr_context_unpin(
+					ring,
+					ctx);
+			ctx->engine[ring->id].dirty = false;
+			if (ring->lrc_last_context == ctx)
+				ring->lrc_last_context = NULL;
+		}
 	}
 }
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index de41ad6..48690f79 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -106,6 +106,7 @@ void intel_lr_context_reset(struct drm_device *dev,
 			struct intel_context *ctx);
 uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
 				     struct intel_engine_cs *ring);
+void intel_lr_context_complete_check(struct drm_i915_gem_request *req);
 
 /* Execlists */
 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 7349d92..fb1df83 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -276,6 +276,7 @@ struct  intel_engine_cs {
 				      u32 flush_domains);
 	int		(*emit_bb_start)(struct drm_i915_gem_request *req,
 					 u64 offset, unsigned dispatch_flags);
+	struct intel_context *lrc_last_context;
 
 	/**
 	 * List of objects currently involved in rendering from the
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH] drm/i915/dp: fall back to 18 bpp when sink capability is unknown
@ 2016-01-13 14:35 Jani Nikula
  2016-01-13 15:13 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Jani Nikula @ 2016-01-13 14:35 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

Per DP spec, the source device should fall back to 18 bpp, VESA range
RGB when the sink capability is unknown. Fix the color depth
clamping. 18 bpp color depth should ensure full color range in automatic
mode.

The clamping has been HDMI specific since its introduction in

commit 996a2239f93b03c5972923f04b097f65565c5bed
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Fri Apr 19 11:24:34 2013 +0200

    drm/i915: Disable high-bpc on pre-1.4 EDID screens

Cc: stable@vger.kernel.org
Reported-by: Dihan Wickremasuriya <nayomal@gmail.com>
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=105331
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 20 +++++++++++++++-----
 1 file changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 07ca19b0ec17..6eaecd9385ab 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12171,11 +12171,21 @@ connected_sink_compute_bpp(struct intel_connector *connector,
 		pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
 	}
 
-	/* Clamp bpp to 8 on screens without EDID 1.4 */
-	if (connector->base.display_info.bpc == 0 && bpp > 24) {
-		DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
-			      bpp);
-		pipe_config->pipe_bpp = 24;
+	/* Clamp bpp to default limit on screens without EDID 1.4 */
+	if (connector->base.display_info.bpc == 0) {
+		int type = connector->base.connector_type;
+		int clamp_bpp = 24;
+
+		/* Fall back to 18 bpp when DP sink capability is unknown. */
+		if (type == DRM_MODE_CONNECTOR_DisplayPort ||
+		    type == DRM_MODE_CONNECTOR_eDP)
+			clamp_bpp = 18;
+
+		if (bpp > clamp_bpp) {
+			DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
+				      bpp, clamp_bpp);
+			pipe_config->pipe_bpp = clamp_bpp;
+		}
 	}
 }
 
-- 
2.1.4

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^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH] drm/i915: Fix for reserved space WARN_ON when ring begin fails
@ 2016-01-13 12:52 John.C.Harrison
  2016-01-13 13:49 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: John.C.Harrison @ 2016-01-13 12:52 UTC (permalink / raw)
  To: Intel-GFX

From: John Harrison <John.C.Harrison@Intel.com>

The reserved space code was not cleaning up properly in the case where
the intel_ring_begin() call failed. This led to WARN_ONs firing about
a double reserve call when running the gem_reset_stats IGT test.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c        | 8 +++++++-
 drivers/gpu/drm/i915/intel_ringbuffer.c | 8 +++++++-
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 06180dc..7dcc299 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -835,6 +835,8 @@ int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
 
 int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request)
 {
+	int ret;
+
 	/*
 	 * The first call merely notes the reserve request and is common for
 	 * all back ends. The subsequent localised _begin() call actually
@@ -845,7 +847,11 @@ int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request)
 	 */
 	intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
 
-	return intel_logical_ring_begin(request, 0);
+	ret = intel_logical_ring_begin(request, 0);
+	if (ret)
+		intel_ring_reserved_space_cancel(request->ringbuf);
+
+	return ret;
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c9b081f..f1d3a4a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2296,6 +2296,8 @@ int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
 
 int intel_ring_reserve_space(struct drm_i915_gem_request *request)
 {
+	int ret;
+
 	/*
 	 * The first call merely notes the reserve request and is common for
 	 * all back ends. The subsequent localised _begin() call actually
@@ -2306,7 +2308,11 @@ int intel_ring_reserve_space(struct drm_i915_gem_request *request)
 	 */
 	intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
 
-	return intel_ring_begin(request, 0);
+	ret = intel_ring_begin(request, 0);
+	if (ret)
+		intel_ring_reserved_space_cancel(request->ringbuf);
+
+	return ret;
 }
 
 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH 1/1] drm/i915: Reorder shadow registers on gen8 for faster lookup
@ 2016-01-12 15:28 Mika Kuoppala
  2016-01-12 16:20 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Mika Kuoppala @ 2016-01-12 15:28 UTC (permalink / raw)
  To: intel-gfx; +Cc: miku

The most common thing on normal operation is ring tail
pointer update. Put it first in the shadow register list for
gen8, like we do with gen9.

Also order the checks inside reg write paths so that
if register is shadowed, no additional checks need to be made.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index c3c13dc929cb..7a464a1b9d1e 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -932,13 +932,13 @@ hsw_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool t
 }
 
 static const i915_reg_t gen8_shadowed_regs[] = {
-	FORCEWAKE_MT,
-	GEN6_RPNSWREQ,
-	GEN6_RC_VIDEO_FREQ,
 	RING_TAIL(RENDER_RING_BASE),
 	RING_TAIL(GEN6_BSD_RING_BASE),
 	RING_TAIL(VEBOX_RING_BASE),
 	RING_TAIL(BLT_RING_BASE),
+	FORCEWAKE_MT,
+	GEN6_RPNSWREQ,
+	GEN6_RC_VIDEO_FREQ,
 	/* TODO: Other registers are not yet used */
 };
 
@@ -957,7 +957,7 @@ static bool is_gen8_shadowed(struct drm_i915_private *dev_priv,
 static void \
 gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 	GEN6_WRITE_HEADER; \
-	if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(dev_priv, reg)) \
+	if (!is_gen8_shadowed(dev_priv, reg) && NEEDS_FORCE_WAKE(offset)) \
 		__force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 	__raw_i915_write##x(dev_priv, reg, val); \
 	GEN6_WRITE_FOOTER; \
@@ -968,8 +968,8 @@ static void \
 chv_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 	enum forcewake_domains fw_engine = 0; \
 	GEN6_WRITE_HEADER; \
-	if (!NEEDS_FORCE_WAKE(offset) || \
-	    is_gen8_shadowed(dev_priv, reg)) \
+	if (is_gen8_shadowed(dev_priv, reg) || \
+	    !NEEDS_FORCE_WAKE(offset)) \
 		fw_engine = 0; \
 	else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
 		fw_engine = FORCEWAKE_RENDER; \
@@ -1013,8 +1013,8 @@ gen9_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, \
 		bool trace) { \
 	enum forcewake_domains fw_engine; \
 	GEN6_WRITE_HEADER; \
-	if (!SKL_NEEDS_FORCE_WAKE(offset) || \
-	    is_gen9_shadowed(dev_priv, reg)) \
+	if (is_gen9_shadowed(dev_priv, reg) || \
+	    !SKL_NEEDS_FORCE_WAKE(offset)) \
 		fw_engine = 0; \
 	else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
 		fw_engine = FORCEWAKE_RENDER; \
-- 
2.5.0

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^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH 00/22] drm_event cleanup, round 2
@ 2016-01-11 21:40 Daniel Vetter
  2016-01-12  8:30 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Daniel Vetter @ 2016-01-11 21:40 UTC (permalink / raw)
  To: DRI Development; +Cc: Daniel Vetter, Intel Graphics Development

Hi all,

Mostly just small changes from review feedback (plus a few misplaced hunks,
silly me). Plus an attempt at better kerneldoc to explain how this works. Since
that caused questions both from Thomas and Laurent let me explain things also
here:

Currently anyone using drm_events (vblank code, atomic/legacy flips, drivers
like exynos) need to handle event setup, sending to the drm file and handling
when the drm file disappears themselves. This patch series provides functions to
encapsulate all these steps. Furthermore the file closing is handled
differently: Events are no longer completely destroyed in preclose hooks like
all current users do, but instead they're just unlinked from the file. The new
drm_send_event can still be called, but instead of transmitting the event to the
file it'll destroy it right away.

This means that when the drm file disappears it's entirely transparent to
drivers, and we can remove all the special tracking and cleanup code around
preclose functions.

The other consequence is that it's opt-in - drivers are still free to remove
events explicitly when the file disappears, it's just needless code. Which means
the patch series can be split up really nicely into core parts + driver patches.
The only patch I didn't split up in this fashion is the one that creates
drm_send_event - it's imo easier to review this way, and the driver changes are
really simple.

Cheers, Daniel

Daniel Vetter (22):
  drm: kerneldoc for drm_fops.c
  drm: Add functions to setup/tear down drm_events.
  drm/exynos: Use the new event init/free functions
  drm/vmwgfx: Use the new event init/free functions
  drm: Create drm_send_event helpers
  drm/fsl: Remove preclose hook
  drm/armada: Remove NULL open/pre/postclose hooks
  drm/gma500: Remove empty preclose hook
  drm: Clean up pending events in the core
  drm: Nuke vblank event file cleanup code
  drm/i915: Nuke intel_modeset_preclose
  drm/atmel: Nuke preclose
  drm/exynos: Remove event cancelling from postclose
  drm/imx: Unconfuse preclose logic
  drm/msm: Nuke preclose hooks
  drm/omap: Nuke close hooks
  drm/rcar: Nuke preclose hook
  drm/shmob: Nuke preclose hook
  drm/tegra: Stop cancelling page flip events
  drm/tilcdc: Nuke preclose hook
  drm/vc4: Nuke preclose hook
  drm/vmwgfx: Nuke preclose hook

 Documentation/DocBook/gpu.tmpl                 |  48 +----
 drivers/gpu/drm/armada/armada_drv.c            |   3 -
 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c |  18 --
 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c   |  10 -
 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h   |   3 -
 drivers/gpu/drm/drm_atomic.c                   |  44 +---
 drivers/gpu/drm/drm_crtc.c                     |  36 +---
 drivers/gpu/drm/drm_fops.c                     | 271 ++++++++++++++++++++++---
 drivers/gpu/drm/drm_irq.c                      |   7 +-
 drivers/gpu/drm/exynos/exynos_drm_drv.c        |  14 --
 drivers/gpu/drm/exynos/exynos_drm_g2d.c        |  36 +---
 drivers/gpu/drm/exynos/exynos_drm_ipp.c        |  28 +--
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c      |   5 -
 drivers/gpu/drm/gma500/psb_drv.c               |   9 -
 drivers/gpu/drm/i915/i915_dma.c                |   2 -
 drivers/gpu/drm/i915/intel_display.c           |  21 --
 drivers/gpu/drm/i915/intel_drv.h               |   1 -
 drivers/gpu/drm/imx/imx-drm-core.c             |  13 --
 drivers/gpu/drm/imx/ipuv3-crtc.c               |   4 -
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c       |   7 -
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c        |  11 -
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h        |   1 -
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c       |   6 -
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c        |  11 -
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h        |   1 -
 drivers/gpu/drm/omapdrm/omap_crtc.c            |  13 +-
 drivers/gpu/drm/omapdrm/omap_drv.c             |  41 ----
 drivers/gpu/drm/omapdrm/omap_drv.h             |   1 -
 drivers/gpu/drm/rcar-du/rcar_du_crtc.c         |  20 --
 drivers/gpu/drm/rcar-du/rcar_du_crtc.h         |   2 -
 drivers/gpu/drm/rcar-du/rcar_du_drv.c          |  10 -
 drivers/gpu/drm/shmobile/shmob_drm_crtc.c      |  20 --
 drivers/gpu/drm/shmobile/shmob_drm_crtc.h      |   2 -
 drivers/gpu/drm/shmobile/shmob_drm_drv.c       |   8 -
 drivers/gpu/drm/tegra/dc.c                     |  17 --
 drivers/gpu/drm/tegra/drm.c                    |   3 -
 drivers/gpu/drm/tegra/drm.h                    |   1 -
 drivers/gpu/drm/tilcdc/tilcdc_crtc.c           |  20 --
 drivers/gpu/drm/tilcdc/tilcdc_drv.c            |   8 -
 drivers/gpu/drm/tilcdc/tilcdc_drv.h            |   1 -
 drivers/gpu/drm/vc4/vc4_crtc.c                 |  20 --
 drivers/gpu/drm/vc4/vc4_drv.c                  |  10 -
 drivers/gpu/drm/vc4/vc4_drv.h                  |   1 -
 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c            |  11 -
 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h            |   1 -
 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c          |  87 +-------
 drivers/gpu/drm/vmwgfx/vmwgfx_fence.h          |   2 -
 include/drm/drmP.h                             |  26 ++-
 48 files changed, 312 insertions(+), 623 deletions(-)

-- 
2.6.4

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [PATCH v2 0/9] Kill off intel_crtc->atomic!
@ 2016-01-11 12:27 Maarten Lankhorst
  2016-01-11 12:49 ` ✗ failure: Fi.CI.BAT Patchwork
  2016-01-11 14:30 ` Patchwork
  0 siblings, 2 replies; 76+ messages in thread
From: Maarten Lankhorst @ 2016-01-11 12:27 UTC (permalink / raw)
  To: intel-gfx

I've fixed some patches with feedback from review.
It's about time that intel_crtc->atomic dies. It was useful
with the transitional helpers, but can be removed safely now.

Maarten Lankhorst (9):
  drm/i915: Unify power domain handling.
  drm/i915: Kill off intel_crtc->atomic.wait_vblank, v3.
  drm/i915: Remove intel_crtc->atomic.disable_ips.
  drm/i915: Remove atomic.pre_disable_primary.
  drm/i915: Remove update_sprite_watermarks.
  drm/i915: Remove some post-commit members from intel_crtc->atomic, v2.
  drm/i915: Nuke fbc members from intel_crtc->atomic, v2.
  drm/i915: Do not compute watermarks on a noop.
  drm/i915: Remove vblank wait from hsw_enable_ips.

 drivers/gpu/drm/i915/intel_atomic.c  |   2 +
 drivers/gpu/drm/i915/intel_display.c | 291 +++++++++++++++++------------------
 drivers/gpu/drm/i915/intel_drv.h     |  39 ++---
 drivers/gpu/drm/i915/intel_fbc.c     |  20 ++-
 drivers/gpu/drm/i915/intel_pm.c      |  59 ++++---
 5 files changed, 214 insertions(+), 197 deletions(-)

-- 
2.1.0

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^ permalink raw reply	[flat|nested] 76+ messages in thread
* [PATCH] drm/i915: Reject invalid-pad for context-destroy ioctl
@ 2016-01-08 21:40 Chris Wilson
  2016-01-11 11:07 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Chris Wilson @ 2016-01-08 21:40 UTC (permalink / raw)
  To: intel-gfx; +Cc: Daniel Vetter

Unknown parameters, especially structure padding, are expected to invoke
rejection with -EINVAL.

Testcase: igt/gem_ctx_bad_destroy/invalid-pad
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89602
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_gem_context.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 060e902afd1c..baabbd6488d8 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -1001,6 +1001,9 @@ int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
 	struct intel_context *ctx;
 	int ret;
 
+	if (args->pad != 0)
+		return -EINVAL;
+
 	if (args->ctx_id == DEFAULT_CONTEXT_HANDLE)
 		return -ENOENT;
 
-- 
2.7.0.rc3

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^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH 00/21] drm_event cleanup
@ 2016-01-08 20:36 Daniel Vetter
  2016-01-11 11:20 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Daniel Vetter @ 2016-01-08 20:36 UTC (permalink / raw)
  To: DRI Development; +Cc: Daniel Vetter, Intel Graphics Development

Hi all,

This patch series is inspired by a WIP patch from Rob Clark to consolidate the
drm_event handling a bit. I've went a bit further and also moved the pending
event handling and unlinking into the core, which allows us to nuke a bunch of
code from drivers who all copypasted this themselves. Plus fix up all the others
who failed to handle this correctly.

Net -500 lines of code, plus kerneldoc for drm_fops.c and all the new functions
as bonus.

Comments and review highly welcome as usual.

Cheers, Daniel

Daniel Vetter (21):
  drm: kerneldoc for drm_fops.c
  drm: Add functions to setup/tear down drm_events.
  drm/exynos: Use the new event init/free functions
  drm/vmwgfx: Use the new event init/free functions
  drm: Create drm_send_event helpers
  drm/fsl: Remove preclose hook
  drm/armada: Remove NULL open/pre/postclose hooks
  drm/gma500: Remove empty preclose hook
  drm: Clean up pending events in the core
  drm/i915: Nuke intel_modeset_preclose
  drm/atmel: Nuke preclose
  drm/exynos: Remove event cancelling from postclose
  drm/imx: Unconfuse preclose logic
  drm/msm: Nuke preclose hooks
  drm/omap: Nuke close hooks
  drm/rcar: Nuke preclose hook
  drm/shmob: Nuke preclose hook
  drm/tegra: Stop cancelling page flip events
  drm/tilcdc: Nuke preclose hook
  drm/vc4: Nuke preclose hook
  drm/vmwgfx: Nuke preclose hook

 Documentation/DocBook/gpu.tmpl                 |  48 +----
 drivers/gpu/drm/armada/armada_drv.c            |   3 -
 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c |  18 --
 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c   |  10 -
 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h   |   3 -
 drivers/gpu/drm/drm_atomic.c                   |  44 ++---
 drivers/gpu/drm/drm_crtc.c                     |  36 +---
 drivers/gpu/drm/drm_fops.c                     | 259 ++++++++++++++++++++++---
 drivers/gpu/drm/drm_irq.c                      |   7 +-
 drivers/gpu/drm/exynos/exynos_drm_drv.c        |  14 --
 drivers/gpu/drm/exynos/exynos_drm_g2d.c        |  36 +---
 drivers/gpu/drm/exynos/exynos_drm_ipp.c        |  28 +--
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c      |   5 -
 drivers/gpu/drm/gma500/psb_drv.c               |   9 -
 drivers/gpu/drm/i915/i915_dma.c                |   2 -
 drivers/gpu/drm/i915/intel_display.c           |  21 --
 drivers/gpu/drm/i915/intel_drv.h               |   1 -
 drivers/gpu/drm/imx/imx-drm-core.c             |  13 --
 drivers/gpu/drm/imx/ipuv3-crtc.c               |   4 -
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c       |   7 -
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c        |  11 --
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h        |   1 -
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c       |   6 -
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c        |  11 --
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h        |   1 -
 drivers/gpu/drm/omapdrm/omap_drv.c             |  29 ---
 drivers/gpu/drm/rcar-du/rcar_du_crtc.c         |  20 --
 drivers/gpu/drm/rcar-du/rcar_du_crtc.h         |   2 -
 drivers/gpu/drm/rcar-du/rcar_du_drv.c          |  10 -
 drivers/gpu/drm/shmobile/shmob_drm_crtc.c      |  20 --
 drivers/gpu/drm/shmobile/shmob_drm_crtc.h      |   2 -
 drivers/gpu/drm/shmobile/shmob_drm_drv.c       |   8 -
 drivers/gpu/drm/tegra/dc.c                     |  17 --
 drivers/gpu/drm/tegra/drm.c                    |   3 -
 drivers/gpu/drm/tegra/drm.h                    |   1 -
 drivers/gpu/drm/tilcdc/tilcdc_crtc.c           |  20 --
 drivers/gpu/drm/tilcdc/tilcdc_drv.c            |   8 -
 drivers/gpu/drm/tilcdc/tilcdc_drv.h            |   1 -
 drivers/gpu/drm/vc4/vc4_crtc.c                 |  20 --
 drivers/gpu/drm/vc4/vc4_drv.c                  |  10 -
 drivers/gpu/drm/vc4/vc4_drv.h                  |   1 -
 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c            |  10 -
 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c          |  73 +------
 drivers/gpu/drm/vmwgfx/vmwgfx_fence.h          |   2 -
 include/drm/drmP.h                             |  26 ++-
 45 files changed, 299 insertions(+), 582 deletions(-)

-- 
2.6.4

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^ permalink raw reply	[flat|nested] 76+ messages in thread
* [PATCH 1/2] drm/i915: Store edram capabilities instead of fixed size
@ 2016-01-08 16:58 Mika Kuoppala
  2016-01-11 10:27 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Mika Kuoppala @ 2016-01-08 16:58 UTC (permalink / raw)
  To: intel-gfx

Store the edram capabilities instead of only the size of
edram. This is preparatory patch to allow edram size calculation
based on edram capability bits for gen9+.

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c |  2 +-
 drivers/gpu/drm/i915/i915_drv.h     |  7 +++++--
 drivers/gpu/drm/i915/i915_gem.c     |  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c |  2 +-
 drivers/gpu/drm/i915/i915_reg.h     |  2 +-
 drivers/gpu/drm/i915/intel_uncore.c | 39 +++++++++++++++++++++++++------------
 6 files changed, 36 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index e3377abc0d4d..039ace6e4524 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2401,7 +2401,7 @@ static int i915_llc(struct seq_file *m, void *data)
 
 	/* Size calculation for LLC is a bit of a pain. Ignore for now. */
 	seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
-	seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
+	seq_printf(m, "eLLC: %zuMB\n", intel_uncore_edram_size_mb(dev_priv));
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6ef03eea3518..c81f537b2da7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1846,7 +1846,7 @@ struct drm_i915_private {
 	struct intel_l3_parity l3_parity;
 
 	/* Cannot be determined by PCIID. You must always read a register. */
-	size_t ellc_size;
+	u32 edram_cap;
 
 	/* gen6+ rps state */
 	struct intel_gen6_power_mgmt rps;
@@ -2567,8 +2567,9 @@ struct drm_i915_cmd_table {
 #define HAS_BLT(dev)		(INTEL_INFO(dev)->ring_mask & BLT_RING)
 #define HAS_VEBOX(dev)		(INTEL_INFO(dev)->ring_mask & VEBOX_RING)
 #define HAS_LLC(dev)		(INTEL_INFO(dev)->has_llc)
+#define HAS_EDRAM(dev)		(__I915__(dev)->edram_cap & EDRAM_ENABLED)
 #define HAS_WT(dev)		((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
-				 __I915__(dev)->ellc_size)
+				 HAS_EDRAM(dev))
 #define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)
 
 #define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 6)
@@ -2735,6 +2736,8 @@ void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
 					enum forcewake_domains domains);
 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
 					enum forcewake_domains domains);
+unsigned intel_uncore_edram_size_mb(struct drm_i915_private *dev_priv);
+
 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
 static inline bool intel_vgpu_active(struct drm_device *dev)
 {
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d8efc9dfbc48..0a5e5524def3 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4799,7 +4799,7 @@ i915_gem_init_hw(struct drm_device *dev)
 	/* Double layer security blanket, see i915_gem_init() */
 	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
-	if (dev_priv->ellc_size)
+	if (HAS_EDRAM(dev_priv))
 		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
 
 	if (IS_HASWELL(dev))
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 56f4f2e58d53..1d1933130b7a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3157,7 +3157,7 @@ int i915_gem_gtt_init(struct drm_device *dev)
 	} else if (INTEL_INFO(dev)->gen < 8) {
 		gtt->gtt_probe = gen6_gmch_probe;
 		gtt->base.cleanup = gen6_gmch_remove;
-		if (IS_HASWELL(dev) && dev_priv->ellc_size)
+		if (HAS_EDRAM(dev))
 			gtt->base.pte_encode = iris_pte_encode;
 		else if (IS_HASWELL(dev))
 			gtt->base.pte_encode = hsw_pte_encode;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 556a458d669e..f88b75ec5047 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6818,7 +6818,7 @@ enum skl_disp_power_wells {
 
 #define  HSW_IDICR				_MMIO(0x9008)
 #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
-#define  HSW_EDRAM_PRESENT			_MMIO(0x120010)
+#define  HSW_EDRAM_CAP				_MMIO(0x120010)
 #define    EDRAM_ENABLED			0x1
 
 #define GEN6_UCGCTL1				_MMIO(0x9400)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index d0973e08e7eb..0c9059cb3d13 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -310,21 +310,36 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 }
 
-static void intel_uncore_ellc_detect(struct drm_device *dev)
+unsigned intel_uncore_edram_size_mb(struct drm_i915_private *dev_priv)
 {
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	if (!HAS_EDRAM(dev_priv))
+		return 0;
+
+	/* The docs do not explain exactly how the calculation can be
+	 * made. It is somewhat guessable, but for now, it's always
+	 * 128MB.
+	 */
+
+	return 128;
+}
 
-	if ((IS_HASWELL(dev) || IS_BROADWELL(dev) ||
-	     INTEL_INFO(dev)->gen >= 9) &&
-	    (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) {
-		/* The docs do not explain exactly how the calculation can be
-		 * made. It is somewhat guessable, but for now, it's always
-		 * 128MB.
-		 * NB: We can't write IDICR yet because we do not have gt funcs
+static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
+{
+	if (IS_HASWELL(dev_priv) ||
+	    IS_BROADWELL(dev_priv) ||
+	    INTEL_INFO(dev_priv)->gen >= 9) {
+		dev_priv->edram_cap = __raw_i915_read32(dev_priv,
+							HSW_EDRAM_CAP);
+
+		/* NB: We can't write IDICR yet because we do not have gt funcs
 		 * set up */
-		dev_priv->ellc_size = 128;
-		DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
+	} else {
+		dev_priv->edram_cap = 0;
 	}
+
+	if (HAS_EDRAM(dev_priv))
+		DRM_INFO("Found %zuMB of eLLC\n",
+			 intel_uncore_edram_size_mb(dev_priv));
 }
 
 static bool
@@ -1239,7 +1254,7 @@ void intel_uncore_init(struct drm_device *dev)
 
 	i915_check_vgpu(dev);
 
-	intel_uncore_ellc_detect(dev);
+	intel_uncore_edram_detect(dev_priv);
 	intel_uncore_fw_domains_init(dev);
 	__intel_uncore_early_sanitize(dev, false);
 
-- 
2.5.0

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^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH 1/2] drm/i915: Enable mmio_debug for vlv/chv
@ 2016-01-08 13:51 Mika Kuoppala
  2016-01-11  9:59 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Mika Kuoppala @ 2016-01-08 13:51 UTC (permalink / raw)
  To: intel-gfx

With commit 8ac3e1bb76cc ("drm/i915: Add non claimed mmio checking
for vlv/chv") we now have chv/vlv support in place for detecting
unclaimed access. Also the perf hit of extra mmio read
is now only suffered if mmio_debug is set.

This allows us to stuff the macro for unclaimed reg
detection inside a generic gen6 register access, as now all
gens using these macros uses also unclaimed debugs, the one
exception being snb. We gain more clean and generic macros
and only downside is that snb will suffer one branch perf hit
without upside.

Note that the hsw write path debug register check now
happens before fifo check, but this should not make
any real difference.

As vlv/chv use the generic gen6 access macros, the consequence
is that they gain the mmio_debug feature.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 41 ++++++++++++++++++++-----------------
 1 file changed, 22 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index d0973e08e7eb..0b47bc891dc7 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -626,14 +626,11 @@ ilk_dummy_write(struct drm_i915_private *dev_priv)
 }
 
 static void
-hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv,
-			const i915_reg_t reg,
-			const bool read,
-			const bool before)
+__unclaimed_reg_debug(struct drm_i915_private *dev_priv,
+		      const i915_reg_t reg,
+		      const bool read,
+		      const bool before)
 {
-	if (likely(!i915.mmio_debug))
-		return;
-
 	if (WARN(check_for_unclaimed_mmio(dev_priv),
 		 "Unclaimed register detected %s %s register 0x%x\n",
 		 before ? "before" : "after",
@@ -642,6 +639,18 @@ hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv,
 		i915.mmio_debug--; /* Only report the first N failures */
 }
 
+static inline void
+unclaimed_reg_debug(struct drm_i915_private *dev_priv,
+		    const i915_reg_t reg,
+		    const bool read,
+		    const bool before)
+{
+	if (likely(!i915.mmio_debug))
+		return;
+
+	__unclaimed_reg_debug(dev_priv, reg, read, before);
+}
+
 #define GEN2_READ_HEADER(x) \
 	u##x val = 0; \
 	assert_rpm_wakelock_held(dev_priv);
@@ -687,9 +696,11 @@ __gen2_read(64)
 	unsigned long irqflags; \
 	u##x val = 0; \
 	assert_rpm_wakelock_held(dev_priv); \
-	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
+	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
+	unclaimed_reg_debug(dev_priv, reg, true, true)
 
 #define GEN6_READ_FOOTER \
+	unclaimed_reg_debug(dev_priv, reg, true, false); \
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 	trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 	return val
@@ -722,11 +733,9 @@ static inline void __force_wake_get(struct drm_i915_private *dev_priv,
 static u##x \
 gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 	GEN6_READ_HEADER(x); \
-	hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
 	if (NEEDS_FORCE_WAKE(offset)) \
 		__force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 	val = __raw_i915_read##x(dev_priv, reg); \
-	hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
 	GEN6_READ_FOOTER; \
 }
 
@@ -774,7 +783,6 @@ static u##x \
 gen9_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 	enum forcewake_domains fw_engine; \
 	GEN6_READ_HEADER(x); \
-	hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
 	if (!SKL_NEEDS_FORCE_WAKE(offset)) \
 		fw_engine = 0; \
 	else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
@@ -788,7 +796,6 @@ gen9_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 	if (fw_engine) \
 		__force_wake_get(dev_priv, fw_engine); \
 	val = __raw_i915_read##x(dev_priv, reg); \
-	hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
 	GEN6_READ_FOOTER; \
 }
 
@@ -887,9 +894,11 @@ __gen2_write(64)
 	unsigned long irqflags; \
 	trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 	assert_rpm_wakelock_held(dev_priv); \
-	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
+	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
+	unclaimed_reg_debug(dev_priv, reg, false, true)
 
 #define GEN6_WRITE_FOOTER \
+	unclaimed_reg_debug(dev_priv, reg, false, false); \
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
 
 #define __gen6_write(x) \
@@ -915,12 +924,10 @@ hsw_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool t
 	if (NEEDS_FORCE_WAKE(offset)) { \
 		__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 	} \
-	hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 	__raw_i915_write##x(dev_priv, reg, val); \
 	if (unlikely(__fifo_ret)) { \
 		gen6_gt_check_fifodbg(dev_priv); \
 	} \
-	hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 	GEN6_WRITE_FOOTER; \
 }
 
@@ -950,11 +957,9 @@ static bool is_gen8_shadowed(struct drm_i915_private *dev_priv,
 static void \
 gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 	GEN6_WRITE_HEADER; \
-	hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 	if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(dev_priv, reg)) \
 		__force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 	__raw_i915_write##x(dev_priv, reg, val); \
-	hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 	GEN6_WRITE_FOOTER; \
 }
 
@@ -1008,7 +1013,6 @@ gen9_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, \
 		bool trace) { \
 	enum forcewake_domains fw_engine; \
 	GEN6_WRITE_HEADER; \
-	hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 	if (!SKL_NEEDS_FORCE_WAKE(offset) || \
 	    is_gen9_shadowed(dev_priv, reg)) \
 		fw_engine = 0; \
@@ -1023,7 +1027,6 @@ gen9_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, \
 	if (fw_engine) \
 		__force_wake_get(dev_priv, fw_engine); \
 	__raw_i915_write##x(dev_priv, reg, val); \
-	hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 	GEN6_WRITE_FOOTER; \
 }
 
-- 
2.5.0

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^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH v2 00/13] Misc cleanups and locking fixes
@ 2016-01-08 11:29 Tvrtko Ursulin
  2016-01-11  9:44 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Tvrtko Ursulin @ 2016-01-08 11:29 UTC (permalink / raw)
  To: Intel-gfx

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Random cleanups from yesterday mutated into a bit of locking verification and
fixing as suggested by Daniel Vetter.

Replacig list_for_each_entry with a dedicated i915_gem_obj_for_each_vma which
asserts the struct_mutex uncovered a few holes, not all of which (atomic display
are being fixed in this series).

I've also added the same assert to i915_gem_object_get_page since it sounds
correct to me to require it although I have not analysed all callsites. Some
might assume they know what they are doing so the approach might be too
drastic, but one like execlist is fixed in this series.

Tvrtko Ursulin (13):
  drm/i915/bdw+: Replace list_del+list_add_tail with list_move_tail
  drm/i915: Don't need a timer to wake us up
  drm/i915: Avoid invariant conditionals in lrc interrupt handler
  drm/i915: Fail engine initialization if LRCA is incorrectly aligned
  drm/i915: Cache LRCA in the context
  drm/i915: Only grab timestamps when needed
  drm/i915: Introduce dedicated object VMA iterator
  drm/i915: GEM operations need to be done under the big lock
  drm/i915: Remove two impossible asserts
  drm/i915: Introduce dedicated safe object VMA iterator
  drm/i915: Cache ringbuffer GTT address
  drm/i915: Add BKL asserts to get page helpers
  drm/i915: Cache LRC state page in the context

 drivers/gpu/drm/i915/i915_debugfs.c      |  23 +++---
 drivers/gpu/drm/i915/i915_drv.h          |  17 +++++
 drivers/gpu/drm/i915/i915_gem.c          |  72 ++++++++----------
 drivers/gpu/drm/i915/i915_gem_gtt.c      |   2 +-
 drivers/gpu/drm/i915/i915_gem_shrinker.c |   5 +-
 drivers/gpu/drm/i915/i915_gem_stolen.c   |   5 ++
 drivers/gpu/drm/i915/i915_gem_userptr.c  |   2 +-
 drivers/gpu/drm/i915/i915_gpu_error.c    |   4 +-
 drivers/gpu/drm/i915/intel_lrc.c         | 122 ++++++++++++++++---------------
 drivers/gpu/drm/i915/intel_lrc.h         |   3 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c  |   3 +
 drivers/gpu/drm/i915/intel_ringbuffer.h  |   3 +
 12 files changed, 140 insertions(+), 121 deletions(-)

-- 
1.9.1

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^ permalink raw reply	[flat|nested] 76+ messages in thread
* [PATCH 0/7] Explicitly pass crtc_state and plane_state to plane update functions.
@ 2016-01-07 10:54 Maarten Lankhorst
  2016-01-11  8:53 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Maarten Lankhorst @ 2016-01-07 10:54 UTC (permalink / raw)
  To: intel-gfx

Right now there are 3 possible functions, update_plane that's only used by sprites,
disable_plane which may be called during plane disable, and commit_plane which
may call either.

This is a bit messy and unclear. Make update_plane only be called when
the plane is visible, and disable_plane whenever it's not. commit_plane
will be removed to reduce confusion.

This makes it easier to put the vma in plane_state.

Maarten Lankhorst (7):
  drm/i915: Use passed plane state for sprite planes, v4.
  drm/i915: Do not use commit_plane for sprite planes.
  drm/i915: Remove some visibility checks from intel_crtc_update_cursor.
  drm/i915: Make disable_cursor_plane similar to commit_cursor_plane.
  drm/i915: Use the plane state for cursor updates.
  drm/i915: Use plane state for primary plane updates.
  drm/i915: Remove commit_plane function pointer.

 drivers/gpu/drm/i915/i915_drv.h           |   3 -
 drivers/gpu/drm/i915/intel_atomic_plane.c |  10 +-
 drivers/gpu/drm/i915/intel_display.c      | 355 +++++++++++++-----------------
 drivers/gpu/drm/i915/intel_drv.h          |  12 +-
 drivers/gpu/drm/i915/intel_sprite.c       | 129 +++++------
 5 files changed, 224 insertions(+), 285 deletions(-)

-- 
2.1.0

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^ permalink raw reply	[flat|nested] 76+ messages in thread
* [PATCH] drm/i915: Init power domains early in driver load
@ 2016-01-07  9:10 Daniel Vetter
  2016-01-11  9:12 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Daniel Vetter @ 2016-01-07  9:10 UTC (permalink / raw)
  To: DRI Development
  Cc: Intel Graphics Development, Daniel Vetter,
	Ville Syrjälä,
	Patrik Jakobsson, Imre Deak, Jani Nikula, Meelis Roos, stable,
	Daniel Vetter

Since

commit ac9b8236551d1177fd07b56aef9b565d1864420d
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date:   Fri Nov 27 18:55:26 2015 +0200

    drm/i915: Introduce a gmbus power domain

gmbus also needs the power domain infrastructure right from the start,
since as soon as we register the i2c controllers someone can use them.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Meelis Roos <mroos@linux.ee>
Fixes: ac9b8236551d ("drm/i915: Introduce a gmbus power domain")
Cc: stable@vger.kernel.org
References: http://www.spinics.net/lists/intel-gfx/msg83075.html
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index b4741d121a74..405aba2ca736 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -396,8 +396,6 @@ static int i915_load_modeset_init(struct drm_device *dev)
 	if (ret)
 		goto cleanup_vga_switcheroo;
 
-	intel_power_domains_init_hw(dev_priv);
-
 	ret = intel_irq_install(dev_priv);
 	if (ret)
 		goto cleanup_gem_stolen;
@@ -1025,6 +1023,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 
 	intel_irq_init(dev_priv);
 	intel_uncore_sanitize(dev);
+	intel_power_domains_init(dev_priv);
+	intel_power_domains_init_hw(dev_priv);
 
 	/* Try to make sure MCHBAR is enabled before poking at it */
 	intel_setup_mchbar(dev);
@@ -1057,8 +1057,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 			goto out_gem_unload;
 	}
 
-	intel_power_domains_init(dev_priv);
-
 	ret = i915_load_modeset_init(dev);
 	if (ret < 0) {
 		DRM_ERROR("failed to init modeset\n");
-- 
2.6.4


^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH] drm/i915/guc: Fix a memory leak where guc->execbuf_client is not freed
@ 2016-01-06 20:53 yu.dai
  2016-01-13  8:49 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: yu.dai @ 2016-01-06 20:53 UTC (permalink / raw)
  To: intel-gfx

From: Alex Dai <yu.dai@intel.com>

During driver unloading, the guc_client created for command submission
needs to be released to avoid memory leak.

Signed-off-by: Alex Dai <yu.dai@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 9c24424..8ce4f32 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -995,6 +995,9 @@ void i915_guc_submission_fini(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_guc *guc = &dev_priv->guc;
 
+	if (i915.enable_guc_submission)
+		i915_guc_submission_disable(dev);
+
 	gem_release_guc_obj(dev_priv->guc.ads_obj);
 	guc->ads_obj = NULL;
 
-- 
2.5.0

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH 1/3] drm: Defer disabling the vblank IRQ until the next interrupt (for instant-off)
@ 2016-01-06 11:09 Chris Wilson
  2016-01-06 13:20 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Chris Wilson @ 2016-01-06 11:09 UTC (permalink / raw)
  To: dri-devel; +Cc: Michel Dänzer, Laurent Pinchart, Dave Airlie, intel-gfx

On vblank instant-off systems, we can get into a situation where the cost
of enabling and disabling the vblank IRQ around a drmWaitVblank query
dominates. And with the advent of even deeper hardware sleep state,
touching registers becomes ever more expensive.  However, we know that if
the user wants the current vblank counter, they are also very likely to
immediately queue a vblank wait and so we can keep the interrupt around
and only turn it off if we have no further vblank requests queued within
the interrupt interval.

After vblank event delivery, this patch adds a shadow of one vblank where
the interrupt is kept alive for the user to query and queue another vblank
event. Similarly, if the user is using blocking drmWaitVblanks, the
interrupt will be disabled on the IRQ following the wait completion.
However, if the user is simply querying the current vblank counter and
timestamp, the interrupt will be disabled after every IRQ and the user
will enabled it again on the first query following the IRQ.

v2: Mario Kleiner -
After testing this, one more thing that would make sense is to move
the disable block at the end of drm_handle_vblank() instead of at the
top.

Turns out that if high precision timestaming is disabled or doesn't
work for some reason (as can be simulated by echo 0 >
/sys/module/drm/parameters/timestamp_precision_usec), then with your
delayed disable code at its current place, the vblank counter won't
increment anymore at all for instant queries, ie. with your other
"instant query" patches. Clients which repeatedly query the counter
and wait for it to progress will simply hang, spinning in an endless
query loop. There's that comment in vblank_disable_and_save:

"* Skip this step if there isn't any high precision timestamp
 * available. In that case we can't account for this and just
 * hope for the best.
 */

With the disable happening after leading edge of vblank (== hw counter
increment already happened) but before the vblank counter/timestamp
handling in drm_handle_vblank, that step is needed to keep the counter
progressing, so skipping it is bad.

Now without high precision timestamping support, a kms driver must not
set dev->vblank_disable_immediate = true, as this would cause problems
for clients, so this shouldn't matter, but it would be good to still
make this robust against a future kms driver which might have
unreliable high precision timestamping, e.g., high precision
timestamping that intermittently doesn't work.

v3: Patch before coffee needs extra coffee.

Testcase: igt/kms_vblank
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Michel Dänzer <michel@daenzer.net>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Dave Airlie <airlied@redhat.com>,
Cc: Mario Kleiner <mario.kleiner.de@gmail.com>
---
 drivers/gpu/drm/drm_irq.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index 607f493ae801..ca5ef87c57c1 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -1213,9 +1213,9 @@ void drm_vblank_put(struct drm_device *dev, unsigned int pipe)
 	if (atomic_dec_and_test(&vblank->refcount)) {
 		if (drm_vblank_offdelay == 0)
 			return;
-		else if (dev->vblank_disable_immediate || drm_vblank_offdelay < 0)
+		else if (drm_vblank_offdelay < 0)
 			vblank_disable_fn((unsigned long)vblank);
-		else
+		else if (!dev->vblank_disable_immediate)
 			mod_timer(&vblank->disable_timer,
 				  jiffies + ((drm_vblank_offdelay * HZ)/1000));
 	}
@@ -1835,6 +1835,16 @@ bool drm_handle_vblank(struct drm_device *dev, unsigned int pipe)
 	wake_up(&vblank->queue);
 	drm_handle_vblank_events(dev, pipe);
 
+	/* With instant-off, we defer disabling the interrupt until after
+	 * we finish processing the following vblank. The disable has to
+	 * be last (after drm_handle_vblank_events) so that the timestamp
+	 * is always accurate.
+	 */
+	if (dev->vblank_disable_immediate &&
+	    drm_vblank_offdelay > 0 &&
+	    !atomic_read(&vblank->refcount))
+		vblank_disable_fn((unsigned long)vblank);
+
 	spin_unlock_irqrestore(&dev->event_lock, irqflags);
 
 	return true;
-- 
2.7.0.rc3

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^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH 1/2] drm/i915: fix get digital port issue in intel_audio
@ 2016-01-06  2:26 libin.yang
  2016-01-06 12:49 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: libin.yang @ 2016-01-06  2:26 UTC (permalink / raw)
  To: intel-gfx, conselvan2, jani.nikula, ville.syrjala, daniel.vetter, tiwai
  Cc: Libin Yang

From: Libin Yang <libin.yang@linux.intel.com>

For DP MST, use enc_to_mst(encoder)->primary to get intel_digital_port,
instead of using enc_to_dig_port(encoder).

Signed-off-by: Libin Yang <libin.yang@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_audio.c | 21 +++++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 31f6d21..431487a0 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -187,6 +187,16 @@ static bool intel_eld_uptodate(struct drm_connector *connector,
 	return true;
 }
 
+static struct intel_digital_port *
+intel_encoder_to_dig_port(struct intel_encoder *intel_encoder)
+{
+	struct drm_encoder *encoder = &intel_encoder->base;
+
+	if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
+		return enc_to_mst(encoder)->primary;
+	return enc_to_dig_port(encoder);
+}
+
 static void g4x_audio_codec_disable(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
@@ -286,7 +296,7 @@ static void hsw_audio_codec_enable(struct drm_connector *connector,
 	struct i915_audio_component *acomp = dev_priv->audio_component;
 	const uint8_t *eld = connector->eld;
 	struct intel_digital_port *intel_dig_port =
-		enc_to_dig_port(&encoder->base);
+		intel_encoder_to_dig_port(encoder);
 	enum port port = intel_dig_port->port;
 	uint32_t tmp;
 	int len, i;
@@ -500,7 +510,8 @@ void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct i915_audio_component *acomp = dev_priv->audio_component;
-	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+	struct intel_digital_port *intel_dig_port =
+		intel_encoder_to_dig_port(intel_encoder);
 	enum port port = intel_dig_port->port;
 
 	connector = drm_select_eld(encoder);
@@ -546,7 +557,8 @@ void intel_audio_codec_disable(struct intel_encoder *intel_encoder)
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct i915_audio_component *acomp = dev_priv->audio_component;
-	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+	struct intel_digital_port *intel_dig_port =
+		intel_encoder_to_dig_port(intel_encoder);
 	enum port port = intel_dig_port->port;
 
 	if (dev_priv->display.audio_codec_disable)
@@ -724,7 +736,8 @@ static int i915_audio_component_get_eld(struct device *dev, int port,
 	/* intel_encoder might be NULL for DP MST */
 	if (intel_encoder) {
 		ret = 0;
-		intel_dig_port = enc_to_dig_port(&intel_encoder->base);
+		intel_dig_port =
+			intel_encoder_to_dig_port(intel_encoder);
 		*enabled = intel_dig_port->audio_connector != NULL;
 		if (*enabled) {
 			eld = intel_dig_port->audio_connector->eld;
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH] drm/i915: Cleaning up DDI translation tables
@ 2016-01-05 19:18 Rodrigo Vivi
  2016-01-06 11:30 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Rodrigo Vivi @ 2016-01-05 19:18 UTC (permalink / raw)
  To: intel-gfx; +Cc: Rodrigo Vivi

No functional changes.

That state the obvious and just duplicate the place we
need to change whenever the table is updated. So let's clean it.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index bc8a497..d3611f5 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -133,12 +133,12 @@ static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 	{ 0x00002016, 0x000000A0, 0x0 },
 	{ 0x00005012, 0x0000009B, 0x0 },
 	{ 0x00007011, 0x00000088, 0x0 },
-	{ 0x80009010, 0x000000C0, 0x1 },	/* Uses I_boost level 0x1 */
+	{ 0x80009010, 0x000000C0, 0x1 },
 	{ 0x00002016, 0x0000009B, 0x0 },
 	{ 0x00005012, 0x00000088, 0x0 },
-	{ 0x80007011, 0x000000C0, 0x1 },	/* Uses I_boost level 0x1 */
+	{ 0x80007011, 0x000000C0, 0x1 },
 	{ 0x00002016, 0x000000DF, 0x0 },
-	{ 0x80005012, 0x000000C0, 0x1 },	/* Uses I_boost level 0x1 */
+	{ 0x80005012, 0x000000C0, 0x1 },
 };
 
 /* Skylake U */
@@ -146,12 +146,12 @@ static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 	{ 0x0000201B, 0x000000A2, 0x0 },
 	{ 0x00005012, 0x00000088, 0x0 },
 	{ 0x80007011, 0x000000CD, 0x0 },
-	{ 0x80009010, 0x000000C0, 0x1 },	/* Uses I_boost level 0x1 */
+	{ 0x80009010, 0x000000C0, 0x1 },
 	{ 0x0000201B, 0x0000009D, 0x0 },
-	{ 0x80005012, 0x000000C0, 0x1 },	/* Uses I_boost level 0x1 */
-	{ 0x80007011, 0x000000C0, 0x1 },	/* Uses I_boost level 0x1 */
+	{ 0x80005012, 0x000000C0, 0x1 },
+	{ 0x80007011, 0x000000C0, 0x1 },
 	{ 0x00002016, 0x00000088, 0x0 },
-	{ 0x80005012, 0x000000C0, 0x1 },	/* Uses I_boost level 0x1 */
+	{ 0x80005012, 0x000000C0, 0x1 },
 };
 
 /* Skylake Y */
@@ -159,12 +159,12 @@ static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 	{ 0x00000018, 0x000000A2, 0x0 },
 	{ 0x00005012, 0x00000088, 0x0 },
 	{ 0x80007011, 0x000000CD, 0x0 },
-	{ 0x80009010, 0x000000C0, 0x3 },	/* Uses I_boost level 0x3 */
+	{ 0x80009010, 0x000000C0, 0x3 },
 	{ 0x00000018, 0x0000009D, 0x0 },
-	{ 0x80005012, 0x000000C0, 0x3 },	/* Uses I_boost level 0x3 */
-	{ 0x80007011, 0x000000C0, 0x3 },	/* Uses I_boost level 0x3 */
+	{ 0x80005012, 0x000000C0, 0x3 },
+	{ 0x80007011, 0x000000C0, 0x3 },
 	{ 0x00000018, 0x00000088, 0x0 },
-	{ 0x80005012, 0x000000C0, 0x3 },	/* Uses I_boost level 0x3 */
+	{ 0x80005012, 0x000000C0, 0x3 },
 };
 
 /*
-- 
2.4.3

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^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH] drm/i915: Tune down rpm wakelock debug checks
@ 2016-01-05 16:54 Daniel Vetter
  2016-01-06  7:49 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Daniel Vetter @ 2016-01-05 16:54 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter, Daniel Vetter, drm-intel-fixes

They're causing massive amounts of dmesg noise and hence CI noise all
over the place. Enabling them for a bit was good enough to refresh our
task list of what's still needed to enable rpm by default.

To make sure we're not forgetting to make this noisy again add a FIXME
comment.

Fixes: da5827c36607 ("drm/i915: add assert_rpm_wakelock_held helper")
Cc: Imre Deak <imre.deak@intel.com>
Cc: drm-intel-fixes@lists.freedesktop.org
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 187f632aa0ee..d6a8a4730b91 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1453,8 +1453,10 @@ static inline void
 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
 {
 	assert_rpm_device_not_suspended(dev_priv);
-	WARN_ONCE(!atomic_read(&dev_priv->pm.wakeref_count),
-		  "RPM wakelock ref not held during HW access");
+	/* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
+	 * too much noise. */
+	if (!atomic_read(&dev_priv->pm.wakeref_count))
+		DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
 }
 
 static inline int
-- 
2.6.4

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^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH] drm/i915: Force clean compilation with -Werror
@ 2016-01-04 10:13 Chris Wilson
  2016-01-04 11:01 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Chris Wilson @ 2016-01-04 10:13 UTC (permalink / raw)
  To: intel-gfx; +Cc: Jani Nikula

Our driver compiles clean (nowadays thanks to 0day) but for me, at least,
it would be beneficial if the compiler threw an error rather than a
warning when it found a piece of suspect code. (I use this to
compile-check patch series and want to break on the first compiler error
in order to fix the patch.)

v2: Kick off a new "Debugging" submenu for i915.ko

At this point, we applied it to the kernel and promptly kicked it out
again as it broke buildbots (due to a compiler warning on 32bits):

commit 908d759b210effb33d927a8cb6603a16448474e4
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Tue May 26 07:46:21 2015 +0200

    Revert "drm/i915: Force clean compilation with -Werror"

v3: Avoid enabling -Werror for allyesconfig/allmodconfig builds, using
COMPILE_TEST as a suitable proxy suggested by Andrew Morton. (Damien)
Only make the option available for EXPERT to reinforce that the option
should not be casually enabled.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

This is a test! I'm seeing whether I can route git send-email through gmail.
Thanks for your patience.
-Chris

---
 drivers/gpu/drm/i915/Kconfig       |  6 ++++++
 drivers/gpu/drm/i915/Kconfig.debug | 12 ++++++++++++
 drivers/gpu/drm/i915/Makefile      |  2 ++
 3 files changed, 20 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/Kconfig.debug

diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index b979295aab82..33e8563c2f99 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -59,3 +59,9 @@ config DRM_I915_USERPTR
 	  selected to enabled full userptr support.
 
 	  If in doubt, say "Y".
+
+menu "drm/i915 Debugging"
+depends on DRM_I915
+depends on EXPERT
+source drivers/gpu/drm/i915/Kconfig.debug
+endmenu
diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug
new file mode 100644
index 000000000000..1f10ee228eda
--- /dev/null
+++ b/drivers/gpu/drm/i915/Kconfig.debug
@@ -0,0 +1,12 @@
+config DRM_I915_WERROR
+	bool "Force GCC to throw an error instead of a warning when compiling"
+	default n
+	# As this may inadvertently break the build, only allow the user
+	# to shoot oneself in the foot iff they aim really hard
+	depends on EXPERT
+	# We use the dependency on !COMPILE_TEST to not be enabled in
+	# allmodconfig or allyesconfig configurations
+	depends on !COMPILE_TEST
+	---help---
+	  Add -Werror to the build flags for (and only for) i915.ko.
+	  Do not enable this unless you are writing code for the i915.ko module.
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0851de07bd13..1e9895b9a546 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -2,6 +2,8 @@
 # Makefile for the drm device driver.  This driver provides support for the
 # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
 
+subdir-ccflags-$(CONFIG_DRM_I915_WERROR) := -Werror
+
 # Please keep these build lists sorted!
 
 # core driver code
-- 
2.6.4

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^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH 1/3] drm: Balance error path for GEM handle allocation
@ 2016-01-04 10:10 Chris Wilson
  2016-01-04 10:49 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Chris Wilson @ 2016-01-04 10:10 UTC (permalink / raw)
  To: dri-devel; +Cc: intel-gfx

The current error path for failure when establishing a handle for a GEM
object is unbalance, e.g. we call object_close() without calling first
object_open(). Use the typical onion structure to only undo what has
been set up prior to the error.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/drm_gem.c | 29 +++++++++++++++++------------
 1 file changed, 17 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index 2e10bba4468b..a08176debc0e 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -343,27 +343,32 @@ drm_gem_handle_create_tail(struct drm_file *file_priv,
 	spin_unlock(&file_priv->table_lock);
 	idr_preload_end();
 	mutex_unlock(&dev->object_name_lock);
-	if (ret < 0) {
-		drm_gem_object_handle_unreference_unlocked(obj);
-		return ret;
-	}
+	if (ret < 0)
+		goto err_unref;
+
 	*handlep = ret;
 
 	ret = drm_vma_node_allow(&obj->vma_node, file_priv->filp);
-	if (ret) {
-		drm_gem_handle_delete(file_priv, *handlep);
-		return ret;
-	}
+	if (ret)
+		goto err_remove;
 
 	if (dev->driver->gem_open_object) {
 		ret = dev->driver->gem_open_object(obj, file_priv);
-		if (ret) {
-			drm_gem_handle_delete(file_priv, *handlep);
-			return ret;
-		}
+		if (ret)
+			goto err_revoke;
 	}
 
 	return 0;
+
+err_revoke:
+	drm_vma_node_revoke(&obj->vma_node, file_priv->filp);
+err_remove:
+	spin_lock(&file_priv->table_lock);
+	idr_remove(&file_priv->object_idr, *handlep);
+	spin_unlock(&file_priv->table_lock);
+err_unref:
+	drm_gem_object_handle_unreference_unlocked(obj);
+	return ret;
 }
 
 /**
-- 
2.6.4

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^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH] drm/i915: Add RPM references in the *_get_hw_state functions
@ 2015-12-31 12:45 Gabriel Feceoru
  2015-12-31 13:20 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Gabriel Feceoru @ 2015-12-31 12:45 UTC (permalink / raw)
  To: intel-gfx

This gets rid of errors like:

[  906.286213] ------------[ cut here ]------------
[  906.286233] WARNING: CPU: 0 PID: 12252 at drivers/gpu/drm/i915/intel_drv.h:1457 gen6_read32+0x1ca/0x1e0 [i915]()
[  906.286234] RPM wakelock ref not held during HW access
[  906.286235] Modules linked in:
[  906.286236]  snd_hda_intel i915 drm_kms_helper drm msr snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic snd_hda_codec snd_hwdep x86_pkg_temp_thermal snd_hda_core i2c_algo_bit ehci_pci syscopyarea sysfillrect sysimgblt fb_sys_fops ehci_hcd r8169 xhci_pci mii xhci_hcd video [last unloaded: drm]
[  906.286246] CPU: 0 PID: 12252 Comm: kms_pipe_crc_ba Tainted: G     U  W       4.4.0-rc6+ #45
[  906.286247] Hardware name: Dell Inc. Inspiron 3847/088DT1       , BIOS A06 01/15/2015
[  906.286248]  ffffffffc022c098 ffff880210dbbae0 ffffffff813e0e4f ffff880210dbbb28
[  906.286250]  ffff880210dbbb18 ffffffff8105f5f2 ffff8801fff40000 0000000000046040
[  906.286251]  ffff8801fff49170 ffff8801fff49170 ffff8801fff40000 ffff880210dbbb78
[  906.286253] Call Trace:
[  906.286256]  [<ffffffff813e0e4f>] dump_stack+0x44/0x55
[  906.286259]  [<ffffffff8105f5f2>] warn_slowpath_common+0x82/0xc0
[  906.286261]  [<ffffffff8105f67c>] warn_slowpath_fmt+0x4c/0x50
[  906.286270]  [<ffffffffc007e29c>] ? drm_property_free_blob+0x8c/0xb0 [drm]
[  906.286280]  [<ffffffffc01a32ea>] gen6_read32+0x1ca/0x1e0 [i915]
[  906.286283]  [<ffffffff8172cd12>] ? mutex_lock+0x12/0x30
[  906.286294]  [<ffffffffc01e0ef0>] hsw_ddi_wrpll_get_hw_state+0x40/0x50 [i915]
[  906.286304]  [<ffffffffc01c3fa1>] intel_atomic_commit+0xd41/0x1740 [i915]
[  906.286312]  [<ffffffffc008c597>] drm_atomic_commit+0x37/0x60 [drm]
[  906.286316]  [<ffffffffc01373e6>] drm_atomic_helper_set_config+0x76/0xb0 [drm_kms_helper]
[  906.286323]  [<ffffffffc008ac0a>] ? drm_modeset_lock_all_ctx+0x9a/0xb0 [drm]
[  906.286329]  [<ffffffffc007b852>] drm_mode_set_config_internal+0x62/0x100 [drm]
[  906.286335]  [<ffffffffc007fcfd>] drm_mode_setcrtc+0x3cd/0x4e0 [drm]
[  906.286339]  [<ffffffffc0071762>] drm_ioctl+0x152/0x540 [drm]
[  906.286341]  [<ffffffff8109d914>] ? __wake_up+0x44/0x50
[  906.286346]  [<ffffffffc007f930>] ? drm_mode_setplane+0x1b0/0x1b0 [drm]
[  906.286348]  [<ffffffff811dc844>] ? mntput+0x24/0x40
[  906.286350]  [<ffffffff811bfe22>] ? __fput+0x172/0x1e0
[  906.286352]  [<ffffffff811d0758>] do_vfs_ioctl+0x288/0x460
[  906.286353]  [<ffffffff811bfece>] ? ____fput+0xe/0x10

Signed-off-by: Gabriel Feceoru <gabriel.feceoru@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 48 ++++++++++++++++++++++++++++++----------
 1 file changed, 36 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index e6408e5..4ba9f2c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2014,15 +2014,18 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 	enum intel_display_power_domain power_domain;
 	u32 tmp;
 	int i;
+	bool ret = false;
 
 	power_domain = intel_display_port_power_domain(encoder);
 	if (!intel_display_power_is_enabled(dev_priv, power_domain))
-		return false;
+		return ret;
+
+	intel_runtime_pm_get(dev_priv);
 
 	tmp = I915_READ(DDI_BUF_CTL(port));
 
 	if (!(tmp & DDI_BUF_CTL_ENABLE))
-		return false;
+		goto out;
 
 	if (port == PORT_A) {
 		tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
@@ -2040,7 +2043,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 			break;
 		}
 
-		return true;
+		ret = true;
+		goto out;
 	} else {
 		for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
 			tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
@@ -2048,17 +2052,19 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 			if ((tmp & TRANS_DDI_PORT_MASK)
 			    == TRANS_DDI_SELECT_PORT(port)) {
 				if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
-					return false;
+					goto out;
 
 				*pipe = i;
-				return true;
+				ret = true;
+				goto out;
 			}
 		}
 	}
 
 	DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
-
-	return false;
+out:
+	intel_runtime_pm_put(dev_priv);
+	return ret;
 }
 
 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
@@ -2510,7 +2516,10 @@ static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
 	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
 		return false;
 
+	intel_runtime_pm_get(dev_priv);
 	val = I915_READ(WRPLL_CTL(pll->id));
+	intel_runtime_pm_put(dev_priv);
+
 	hw_state->wrpll = val;
 
 	return val & WRPLL_PLL_ENABLE;
@@ -2525,7 +2534,10 @@ static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
 	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
 		return false;
 
+	intel_runtime_pm_get(dev_priv);
 	val = I915_READ(SPLL_CTL);
+	intel_runtime_pm_put(dev_priv);
+
 	hw_state->spll = val;
 
 	return val & SPLL_PLL_ENABLE;
@@ -2644,16 +2656,19 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 	uint32_t val;
 	unsigned int dpll;
 	const struct skl_dpll_regs *regs = skl_dpll_regs;
+	bool ret = false;
 
 	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
-		return false;
+		return ret;
 
 	/* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
 	dpll = pll->id + 1;
 
+	intel_runtime_pm_get(dev_priv);
+
 	val = I915_READ(regs[pll->id].ctl);
 	if (!(val & LCPLL_PLL_ENABLE))
-		return false;
+		goto out;
 
 	val = I915_READ(DPLL_CTRL1);
 	hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
@@ -2664,6 +2679,9 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 		hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
 	}
 
+	ret = true;
+out:
+	intel_runtime_pm_put(dev_priv);
 	return true;
 }
 
@@ -2931,13 +2949,16 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 {
 	enum port port = (enum port)pll->id;	/* 1:1 port->PLL mapping */
 	uint32_t val;
+	bool ret = false;
 
 	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
-		return false;
+		return ret;
+
+	intel_runtime_pm_get(dev_priv);
 
 	val = I915_READ(BXT_PORT_PLL_ENABLE(port));
 	if (!(val & PORT_PLL_ENABLE))
-		return false;
+		goto out;
 
 	hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
 	hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
@@ -2984,7 +3005,10 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 				 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
 	hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
 
-	return true;
+	ret = true;
+out:
+	intel_runtime_pm_put(dev_priv);
+	return ret;
 }
 
 static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
-- 
2.5.0

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^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH] drm/i915/bxt: Fix eDP panel power save/restore
@ 2015-12-30 22:56 Matt Roper
  2015-12-31  7:43 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Matt Roper @ 2015-12-30 22:56 UTC (permalink / raw)
  To: intel-gfx; +Cc: drm-intel-fixes

Broxton-specific panel power sequencing was added in commit

        commit b0a08bec96318be54db97c3f0b9e37b52561f9ea
        Author: Vandana Kannan <vandana.kannan@intel.com>
        Date:   Thu Jun 18 11:00:55 2015 +0530

            drm/i915/bxt: eDP Panel Power sequencing

As noted in that commit, Broxton has two sets of registers (and we're
supposed to read which to use from the VBT, although we're punting on
that part at the moment) and also doesn't have a divisor register.
Although we take the BXT-specific details into account at initial system
init, we fail to save/restore the appropriate registers around system
suspend/resume, which leads to unclaimed register warnings at the
moment, and may also fail to save the proper registers once we start
actually paying attention to the VBT.

Cc: Vandana Kannan <vandana.kannan@intel.com>
Cc: drm-intel-fixes@lists.freedesktop.org
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_suspend.c | 24 ++++++++++++++++++++++--
 1 file changed, 22 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index bf582fe..61bec8e 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -44,7 +44,18 @@ static void i915_save_display(struct drm_device *dev)
 		dev_priv->regfile.saveLVDS = I915_READ(LVDS);
 
 	/* Panel power sequencer */
-	if (HAS_PCH_SPLIT(dev)) {
+	if (IS_BROXTON(dev)) {
+		/*
+		 * TODO: BXT has 2 sets of PPS registers.
+		 * Correct Register for Broxton need to be identified
+		 * using VBT. hardcoding for now.
+		 *
+		 * There's also no divisor register on Broxton.
+		 */
+		dev_priv->regfile.savePP_CONTROL = I915_READ(BXT_PP_CONTROL(0));
+		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(BXT_PP_ON_DELAYS(0));
+		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(BXT_PP_OFF_DELAYS(0));
+	} else if (HAS_PCH_SPLIT(dev)) {
 		dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
 		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
 		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
@@ -83,7 +94,16 @@ static void i915_restore_display(struct drm_device *dev)
 		I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask);
 
 	/* Panel power sequencer */
-	if (HAS_PCH_SPLIT(dev)) {
+	if (IS_BROXTON(dev)) {
+		/*
+		 * TODO: BXT has 2 sets of PPS registers.
+		 * Correct Register for Broxton need to be identified
+		 * using VBT. hardcoding for now
+		 */
+		I915_WRITE(BXT_PP_ON_DELAYS(0), dev_priv->regfile.savePP_ON_DELAYS);
+		I915_WRITE(BXT_PP_OFF_DELAYS(0), dev_priv->regfile.savePP_OFF_DELAYS);
+		I915_WRITE(BXT_PP_CONTROL(0), dev_priv->regfile.savePP_CONTROL);
+	} else if (HAS_PCH_SPLIT(dev)) {
 		I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
 		I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
 		I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
-- 
2.1.4

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH] drm/i915: increase the tries for HDMI hotplug live status checking
@ 2015-12-23  8:11 Gary Wang
  2015-12-23  8:49 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Gary Wang @ 2015-12-23  8:11 UTC (permalink / raw)
  To: intel-gfx; +Cc: Shobhit Kumar

The total delay of HDMI hotplug detecting with 30ms is sometimes not
enoughtfor HDMI live status up with specific HDMI monitors in BSW platform.

After doing experiments for following monitors, it needs 80ms at least
for those worst cases.

Lenovo L246 1xwA (4 failed, necessary hot-plug delay: 58/40/60/40ms)
Philips HH2AP (9 failed, necessary hot-plug delay: 80/50/50/60/46/40/58/58/39ms)
BENQ ET-0035-N (6 failed, necessary hot-plug delay: 60/50/50/80/80/40ms)
DELL U2713HM (2 failed, necessary hot-plug delay: 58/59ms)
HP HP-LP2475w (5 failed, necessary hot-plug delay: 70/50/40/60/40ms)

It looks like 70-80 ms is BSW platform needs in some bad cases of the
monitors at this end (8 times delay at most). Keep less than 100ms for
HDCP pulse HPD low (with at least 100ms) to respond a plug out.

Reviewed-by: Cooper Chiou <cooper.chiou@intel.com>
Tested-by: Gary Wang <gary.c.wang@intel.com>
Cc: Gavin Hindman <gavin.hindman@intel.com>
Cc: Sonika Jindal <sonika.jindal@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Gary Wang <gary.c.wang@intel.com>
---
 drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
 mode change 100644 => 100755 drivers/gpu/drm/i915/intel_hdmi.c

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
old mode 100644
new mode 100755
index 6214175..4a77639
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1392,7 +1392,7 @@ intel_hdmi_detect(struct drm_connector *connector, bool force)
 
 	intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
 
-	for (try = 0; !live_status && try < 4; try++) {
+	for (try = 0; !live_status && try < 9; try++) {
 		if (try)
 			msleep(10);
 		live_status = intel_digital_port_connected(dev_priv,
-- 
1.9.1

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH] drm, i915: Fix pointer size cast
@ 2015-12-21 18:53 Borislav Petkov
  2015-12-22  7:30 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Borislav Petkov @ 2015-12-21 18:53 UTC (permalink / raw)
  To: LKML; +Cc: Daniel Vetter, Jani Nikula, David Airlie, intel-gfx, dri-devel

From: Borislav Petkov <bp@suse.de>

gcc complains on 32-bit like this:

  drivers/gpu/drm/i915/intel_display.c: In function ‘intel_plane_obj_offset’:
  drivers/gpu/drm/i915/intel_display.c:2954:11: warning: cast to pointer from \
	  integer of different size [-Wint-to-pointer-cast]
    offset = (unsigned char *)vma->node.start;
             ^

because vma->node.start is u64 but a pointer on 32-bit is 4 bytes.

Do the calculations with an unsigned long directly and save us the
casts.

Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: David Airlie <airlied@linux.ie>
Cc: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Borislav Petkov <bp@suse.de>
---
 drivers/gpu/drm/i915/intel_display.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 62211abe4922..640cb7c9b7f3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2941,7 +2941,7 @@ unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
 {
 	const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
 	struct i915_vma *vma;
-	unsigned char *offset;
+	unsigned long offset;
 
 	if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
 		view = &i915_ggtt_view_rotated;
@@ -2951,14 +2951,14 @@ unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
 		view->type))
 		return -1;
 
-	offset = (unsigned char *)vma->node.start;
+	offset = vma->node.start;
 
 	if (plane == 1) {
 		offset += vma->ggtt_view.rotation_info.uv_start_page *
 			  PAGE_SIZE;
 	}
 
-	return (unsigned long)offset;
+	return offset;
 }
 
 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
-- 
2.3.5


^ permalink raw reply related	[flat|nested] 76+ messages in thread
* improve handling of the driver's internal default context
@ 2015-12-21 16:04 Dave Gordon
  2015-12-22  7:20 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Dave Gordon @ 2015-12-21 16:04 UTC (permalink / raw)
  To: intel-gfx

A collection of patches to simplify the creation, use, and destruction
of the driver's global default context.

    The first two simplify the many places where the code treats the
    global default context differently from any other context:

	[1/6] drm/i915: mark the global default (intel_)context as such
	[2/6] drm/i915: simplify testing for the global default context

    Then we hide the use of the global-default-context from callers who
    don't need to know how non-batch-related requests are implemented
    internally:

	[3/6] drm/i915: simplify allocation of driver-internal requests

    And get rid of the multiple references to the default context, one
    from each engine (but all pointing to the same structure). This
    allows the refcount and the number of references to match!

	[4/6] drm/i915: abolish separate per-engine default_context

    Finally, fix some incorrect failure paths and tidy up the
    corresponding teardown code:

	[5/6] drm/i915: tidy up initialisation failure paths (legacy)
	[6/6] drm/i915: tidy up initialisation failure paths (GEM &

These should make subsequent reorganisation of other startup/teardown
code easier and safer.

_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [RFC v2] drm/i915/bdw+: Do not emit user interrupts when not needed
@ 2015-12-21 15:33 Tvrtko Ursulin
  2015-12-21 17:30 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Tvrtko Ursulin @ 2015-12-21 15:33 UTC (permalink / raw)
  To: Intel-gfx

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Currently a single request submission in execlist mode results
in two emitted interrupts. First the user interrupt arrives and
is then followed by the context complete interrupt. (This time
delay is caused by the time taken by the GPU to write out the
context and update the CSB.)

This also means every individual batch submission, and also the
end of the coalesced request submission, will result in two
interrupts instead of potentially one.

If we make sure that the last or solitary request does not emit
the MI_USER_INTERRUPT, but instead rely on context complete to
wake up the waiters, we can reduce the CPU time spent in
interrupt handlers.

In some interrupt heavy benchmarks this can be even 50% fewer
interrupts and 1-2% reduced CPU usage (it halved the time spent
in interrupt handlers on an i7 BDW). But on the other hand this
also has the theoretical potential of increasing the wake-up
latency (see earlier reference for the delay between emitting
the user interrupt and context complete).

v2: Clear MI_USER_INTERRUPT instructions when applicable
    rather than emitting them for potentially more robustness
    and not breaking GuC submission.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
I failed to find a benchmark, or a test, which would reliably
show a win (or lose) with this patch.

Therefore I do not think it is worth the complexity and am
filing it for reference only.
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/i915_irq.c  | 24 ++++++++++++------------
 drivers/gpu/drm/i915/intel_lrc.c | 37 +++++++++++++++++++++++++++++++++++++
 3 files changed, 50 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9b82c4532893..94d1084a090b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2825,6 +2825,7 @@ ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
 	ibx_display_interrupt_update(dev_priv, bits, 0);
 }
 
+void intel_notify_ring(struct intel_engine_cs *ring);
 
 /* i915_gem.c */
 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3f8c753997ba..a2087bad0d64 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -994,7 +994,7 @@ static void ironlake_rps_change_irq_handler(struct drm_device *dev)
 	return;
 }
 
-static void notify_ring(struct intel_engine_cs *ring)
+void intel_notify_ring(struct intel_engine_cs *ring)
 {
 	if (!intel_ring_initialized(ring))
 		return;
@@ -1291,9 +1291,9 @@ static void ilk_gt_irq_handler(struct drm_device *dev,
 {
 	if (gt_iir &
 	    (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
-		notify_ring(&dev_priv->ring[RCS]);
+		intel_notify_ring(&dev_priv->ring[RCS]);
 	if (gt_iir & ILK_BSD_USER_INTERRUPT)
-		notify_ring(&dev_priv->ring[VCS]);
+		intel_notify_ring(&dev_priv->ring[VCS]);
 }
 
 static void snb_gt_irq_handler(struct drm_device *dev,
@@ -1303,11 +1303,11 @@ static void snb_gt_irq_handler(struct drm_device *dev,
 
 	if (gt_iir &
 	    (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
-		notify_ring(&dev_priv->ring[RCS]);
+		intel_notify_ring(&dev_priv->ring[RCS]);
 	if (gt_iir & GT_BSD_USER_INTERRUPT)
-		notify_ring(&dev_priv->ring[VCS]);
+		intel_notify_ring(&dev_priv->ring[VCS]);
 	if (gt_iir & GT_BLT_USER_INTERRUPT)
-		notify_ring(&dev_priv->ring[BCS]);
+		intel_notify_ring(&dev_priv->ring[BCS]);
 
 	if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
 		      GT_BSD_CS_ERROR_INTERRUPT |
@@ -1322,7 +1322,7 @@ static __always_inline void
 gen8_cs_irq_handler(struct intel_engine_cs *ring, u32 iir, int test_shift)
 {
 	if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
-		notify_ring(ring);
+		intel_notify_ring(ring);
 	if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
 		intel_lrc_irq_handler(ring);
 }
@@ -1629,7 +1629,7 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
 
 	if (HAS_VEBOX(dev_priv->dev)) {
 		if (pm_iir & PM_VEBOX_USER_INTERRUPT)
-			notify_ring(&dev_priv->ring[VECS]);
+			intel_notify_ring(&dev_priv->ring[VECS]);
 
 		if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
 			DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
@@ -3961,7 +3961,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
 		new_iir = I915_READ16(IIR); /* Flush posted writes */
 
 		if (iir & I915_USER_INTERRUPT)
-			notify_ring(&dev_priv->ring[RCS]);
+			intel_notify_ring(&dev_priv->ring[RCS]);
 
 		for_each_pipe(dev_priv, pipe) {
 			int plane = pipe;
@@ -4157,7 +4157,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
 		new_iir = I915_READ(IIR); /* Flush posted writes */
 
 		if (iir & I915_USER_INTERRUPT)
-			notify_ring(&dev_priv->ring[RCS]);
+			intel_notify_ring(&dev_priv->ring[RCS]);
 
 		for_each_pipe(dev_priv, pipe) {
 			int plane = pipe;
@@ -4387,9 +4387,9 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
 		new_iir = I915_READ(IIR); /* Flush posted writes */
 
 		if (iir & I915_USER_INTERRUPT)
-			notify_ring(&dev_priv->ring[RCS]);
+			intel_notify_ring(&dev_priv->ring[RCS]);
 		if (iir & I915_BSD_USER_INTERRUPT)
-			notify_ring(&dev_priv->ring[VCS]);
+			intel_notify_ring(&dev_priv->ring[VCS]);
 
 		for_each_pipe(dev_priv, pipe) {
 			if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 27f06198a51e..173b3faf5a2a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -359,6 +359,20 @@ static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
 	spin_unlock(&dev_priv->uncore.lock);
 }
 
+static void execlists_clear_user_interrupt(struct drm_i915_gem_request *req)
+{
+	struct intel_ringbuffer *ringbuf = req->ringbuf;
+
+	iowrite32(MI_NOOP, ringbuf->virtual_start + req->tail - 8);
+}
+
+static void execlists_emit_user_interrupt(struct drm_i915_gem_request *req)
+{
+	struct intel_ringbuffer *ringbuf = req->ringbuf;
+
+	iowrite32(MI_USER_INTERRUPT, ringbuf->virtual_start + req->tail - 8);
+}
+
 static int execlists_update_context(struct drm_i915_gem_request *rq)
 {
 	struct intel_engine_cs *ring = rq->ring;
@@ -433,6 +447,14 @@ static void execlists_context_unqueue(struct intel_engine_cs *ring)
 			cursor->elsp_submitted = req0->elsp_submitted;
 			list_move_tail(&req0->execlist_link,
 				       &ring->execlist_retired_req_list);
+			/*
+			 * When coalescing previosly submitted request,
+			 * it might have been the last one in the previous
+			 * submission so had its user interrupt cleared.
+			 * Put it back in.
+			 */
+			if (req0->elsp_submitted)
+				execlists_emit_user_interrupt(req0);
 			req0 = cursor;
 		} else {
 			req1 = cursor;
@@ -440,6 +462,15 @@ static void execlists_context_unqueue(struct intel_engine_cs *ring)
 		}
 	}
 
+	/*
+	 * Last requests submitted on each port do not need to generate
+	 * user interrupts since we will get context complete.
+	 */
+	if (req0->elsp_submitted == 0)
+		execlists_clear_user_interrupt(req0);
+	if (req1 && req1->elsp_submitted == 0)
+		execlists_clear_user_interrupt(req1);
+
 	if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) {
 		/*
 		 * WaIdleLiteRestore: make sure we never cause a lite
@@ -472,6 +503,12 @@ static bool execlists_check_remove_request(struct intel_engine_cs *ring,
 
 	assert_spin_locked(&ring->execlist_lock);
 
+	/*
+	 * This is effectively a context complete interrupt so wake
+	 * up potential waiters on this ring.
+	 */
+	intel_notify_ring(ring);
+
 	head_req = list_first_entry_or_null(&ring->execlist_queue,
 					    struct drm_i915_gem_request,
 					    execlist_link);
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH 00/15] drm/i915/bios: mipi sequence block v3, etc.
@ 2015-12-21 13:10 Jani Nikula
  2016-01-05 16:01 ` ✗ failure: Fi.CI.BAT Patchwork
                   ` (2 more replies)
  0 siblings, 3 replies; 76+ messages in thread
From: Jani Nikula @ 2015-12-21 13:10 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula, Deepak M

Hi all, this is follow-up to my earlier opregion/vbt series [1]. This
covers patches 1 and 7 of Deepak's series [2], but does quite a bunch of
rework to make everything as neat as it can be given the spec. There's
also some generic VBT documentation.

Unfortunately I haven't been able to test this on a machine that
actually has MIPI sequence block v3. However most of the series does not
touch that yet.

BR,
Jani.


[1] http://mid.gmane.org/cover.1450089383.git.jani.nikula@intel.com
[2] http://mid.gmane.org/1448923632-16760-1-git-send-email-m.deepak@intel.com

Jani Nikula (14):
  drm/i915/bios: add proper documentation for the Video BIOS Table (VBT)
  drm/i915/bios: fix header define name for intel_bios.h
  drm/i915/bios: split the MIPI DSI VBT block parsing to two
  drm/i915/bios: have get_blocksize() support MIPI sequence block v3+
  drm/i915/bios: abstract finding the panel sequence block
  drm/i915/bios: rewrite sequence block parsing
  drm/i915/dsi: be defensive about out of bounds sequence id
  drm/i915/dsi: be defensive about out of bounds operation byte
  drm/i915/bios: interpret the i2c element
  drm/i915/bios: add sequences for MIPI sequence block v2
  drm/i915/bios: add defines for v3 sequence block
  drm/i915/bios: add support for MIPI sequence block v3
  drm/i915/dsi: skip unknown elements for sequence block v3+
  drm/i915/dsi: reduce tedious repetition

vkorjani (1):
  drm/i915: Adding the parsing logic for the i2c element

 Documentation/DocBook/gpu.tmpl             |   6 +
 drivers/gpu/drm/i915/i915_drv.h            |   2 +-
 drivers/gpu/drm/i915/intel_bios.c          | 376 +++++++++++++++++------------
 drivers/gpu/drm/i915/intel_bios.h          |  60 +++--
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 198 +++++++++------
 5 files changed, 397 insertions(+), 245 deletions(-)

-- 
2.1.4

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [PATCH v2 0/5] Add GuC ADS (Addition Data Structure)
@ 2015-12-18 20:00 yu.dai
  2016-01-05 12:30 ` ✗ failure: Fi.CI.BAT Patchwork
  2016-01-06  9:01 ` Patchwork
  0 siblings, 2 replies; 76+ messages in thread
From: yu.dai @ 2015-12-18 20:00 UTC (permalink / raw)
  To: intel-gfx

From: Alex Dai <yu.dai@intel.com>

The GuC firmware uses this for various purposes. The ADS itself is a chunk of
memory created by driver to share with GuC. This series creates the GuC ADS
object and setup some basic settings for it.

This version addresses some comments from Chris W. Tidy up some code; replace
kmap_atomic by kmap etc.

Alex Dai (4):
  drm/i915/guc: Add GuC ADS (Addition Data Structure) - allocation
  drm/i915/guc: Add GuC ADS - scheduler policies
  drm/i915/guc: Add GuC ADS - MMIO reg state
  drm/i915/guc: Add GuC ADS - enabling ADS

Dave Gordon (1):
  drm/i915/guc: Expose (intel)_lr_context_size()

 drivers/gpu/drm/i915/i915_guc_reg.h        |   1 +
 drivers/gpu/drm/i915/i915_guc_submission.c |  95 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_guc.h           |   2 +
 drivers/gpu/drm/i915/intel_guc_fwif.h      | 113 ++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_guc_loader.c    |   7 ++
 drivers/gpu/drm/i915/intel_lrc.c           |   4 +-
 drivers/gpu/drm/i915/intel_lrc.h           |   1 +
 7 files changed, 220 insertions(+), 3 deletions(-)

-- 
2.5.0

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [PATCH] drm/i915: edp resume/On time optimization.
@ 2015-12-18 19:55 abhay.kumar
  2015-12-19  7:30 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: abhay.kumar @ 2015-12-18 19:55 UTC (permalink / raw)
  To: Intel-gfx

From: Abhay Kumar <abhay.kumar@intel.com>

Make resume/on codepath not to wait for panel_power_cycle_delay(t11_t12)
if this time is already spent in suspend/poweron time.

Change-Id: Ied0f10f82776af8e6e8ff561bb4e5c0ce1dad4b3
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c |  3 +++
 drivers/gpu/drm/i915/intel_dp.c  | 22 ++++++++++++++--------
 drivers/gpu/drm/i915/intel_drv.h |  2 +-
 3 files changed, 18 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index cbabcb4..fe99d72 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2347,6 +2347,9 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
 		intel_edp_panel_vdd_on(intel_dp);
 		intel_edp_panel_off(intel_dp);
+
+		/* storing panel power off time */
+		intel_dp->panel_power_off_time = ktime_get_with_offset(TK_OFFS_BOOT);
 	}
 
 	if (IS_SKYLAKE(dev))
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index acda70e..845944d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -38,7 +38,6 @@
 #include "intel_drv.h"
 #include <drm/i915_drm.h>
 #include "i915_drv.h"
-
 #define DP_LINK_CHECK_TIMEOUT	(10 * 1000)
 
 /* Compliance test status bits  */
@@ -1654,13 +1653,22 @@ static void wait_panel_off(struct intel_dp *intel_dp)
 
 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
 {
+	ktime_t panel_power_on_time;
+	u32 panel_power_off_duration;
+
 	DRM_DEBUG_KMS("Wait for panel power cycle\n");
 
-	/* When we disable the VDD override bit last we have to do the manual
-	 * wait. */
-	wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
-				       intel_dp->panel_power_cycle_delay);
+        /* take the diffrence of currrent time and panel power off time
+           and then make panel wait for t11_t12 if needed */
+	panel_power_on_time = ktime_get_with_offset(TK_OFFS_BOOT);
+	panel_power_off_duration = (panel_power_on_time.tv64 - intel_dp->panel_power_off_time.tv64);
+	panel_power_off_duration = panel_power_off_duration / 1000000;
 
+	/* When we disable the VDD override bit last we have to do the manual
+	 * wait */
+	if (panel_power_off_duration < intel_dp->panel_power_cycle_delay)
+		wait_remaining_ms_from_jiffies(jiffies,
+				       (intel_dp->panel_power_cycle_delay - panel_power_off_duration));
 	wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 }
 
@@ -1811,7 +1819,7 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
 	I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
 
 	if ((pp & POWER_TARGET_ON) == 0)
-		intel_dp->last_power_cycle = jiffies;
+		intel_dp->panel_power_off_time = ktime_get_with_offset(TK_OFFS_BOOT);
 
 	power_domain = intel_display_port_power_domain(intel_encoder);
 	intel_display_power_put(dev_priv, power_domain);
@@ -1960,7 +1968,6 @@ static void edp_panel_off(struct intel_dp *intel_dp)
 	I915_WRITE(pp_ctrl_reg, pp);
 	POSTING_READ(pp_ctrl_reg);
 
-	intel_dp->last_power_cycle = jiffies;
 	wait_panel_off(intel_dp);
 
 	/* We got a reference when we enabled the VDD. */
@@ -5196,7 +5203,6 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
 
 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
 {
-	intel_dp->last_power_cycle = jiffies;
 	intel_dp->last_power_on = jiffies;
 	intel_dp->last_backlight_off = jiffies;
 }
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d44f2f5..ef82e8f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -722,9 +722,9 @@ struct intel_dp {
 	int backlight_off_delay;
 	struct delayed_work panel_vdd_work;
 	bool want_panel_vdd;
-	unsigned long last_power_cycle;
 	unsigned long last_power_on;
 	unsigned long last_backlight_off;
+	ktime_t panel_power_off_time;
 
 	struct notifier_block edp_notifier;
 
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH] drm/i915: Workaround CHV pipe C cursor fail
@ 2015-12-18 17:24 ville.syrjala
  2015-12-18 17:49 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: ville.syrjala @ 2015-12-18 17:24 UTC (permalink / raw)
  To: intel-gfx; +Cc: stable, Jason Plum

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Turns out CHV pipe C was glued on somewhat poorly, and there's something
wrong with the cursor. If the cursor straddles the left screen edge,
and is then moved away from the edge or disabled, the pipe will often
underrun. If enough underruns are triggered quickly enough the pipe
will fall over and die (it just scans out a solid color and reports
a constant underrun). We need to turn the disp2d power well off and
on again to recover the pipe.

None of that is very nice for the user, so let's just refuse to place
the cursor in the compromised position. The ddx appears to fall back
to swcursor when the ioctl returns an error, so theoretically there's
no loss of functionality for the user (discounting swcursor bugs).
I suppose most cursors images actually have the hotspot not exactly
at 0,0 so under typical conditions the fallback will in fact kick in
as soon as the cursor touches the left edge of the screen.

Any atomic compositor should anyway be prepared to fall back to
GPU composition when things don't work out, so there should be no
problem with those.

Other things that I tried to solve this include flipping all
display related clock gating knobs I could find, increasing the
minimum gtt alignment all the way up to 512k. I also tried to see
if there are more specific screen coordinates that hit the bug, but
the findings were somewhat inconclusive. Sometimes the failures
happen almost across the whole left edge, sometimes more at the very
top and around the bottom half. I wasn't able to find any real pattern
to these variations, so it seems our only choice is to just refuse
to straddle the left screen edge at all.

Cc: stable@vger.kernel.org
Cc: Jason Plum <max@warheads.net>
Testcase: igt/kms_chv_cursor_fail
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92826
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index abd2d2944022..8acc66b95139 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14059,6 +14059,7 @@ intel_check_cursor_plane(struct drm_plane *plane,
 	struct drm_crtc *crtc = crtc_state->base.crtc;
 	struct drm_framebuffer *fb = state->base.fb;
 	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
+	enum pipe pipe = to_intel_plane(plane)->pipe;
 	unsigned stride;
 	int ret;
 
@@ -14092,6 +14093,22 @@ intel_check_cursor_plane(struct drm_plane *plane,
 		return -EINVAL;
 	}
 
+	/*
+	 * There's something wrong with the cursor on CHV pipe C.
+	 * If it straddles the left edge of the screen then
+	 * moving it away from the edge or disabling it often
+	 * results in a pipe underrun, and often that can lead to
+	 * dead pipe (constant underrun reported, and it scans
+	 * out just a solid color). To recover from that, the
+	 * display power well must be turned off and on again.
+	 * Refuse the put the cursor into that compromised position.
+	 */
+	if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
+	    state->visible && state->base.crtc_x < 0) {
+		DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
+		return -EINVAL;
+	}
+
 	return 0;
 }
 
-- 
2.4.10


^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH] Allow userspace to set NULL blob on properties
@ 2015-12-18 15:17 Lionel Landwerlin
  2015-12-18 15:30 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Lionel Landwerlin @ 2015-12-18 15:17 UTC (permalink / raw)
  To: intel-gfx; +Cc: daniel.vetter

Hi,

A couple of people told me I should be able to set a blob property to
NULL from user space using a blob id 0. I couldn't get that to work
(probably nobody's doing this at the moment). Here is a patch to make
that work.

Cheers,

-
Lionel

Lionel Landwerlin (1):
  drm/atomic: allow setting a blob to NULL using id = 0

 drivers/gpu/drm/drm_atomic.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

--
2.6.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [PATCH v9] drm/i915: Extend LRC pinning to cover GPU context writeback
@ 2015-12-18 14:41 Nick Hoath
  2015-12-18 15:01 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Nick Hoath @ 2015-12-18 14:41 UTC (permalink / raw)
  To: intel-gfx; +Cc: Daniel Vetter

Use the first retired request on a new context to unpin
the old context. This ensures that the hw context remains
bound until it has been written back to by the GPU.
Now that the context is pinned until later in the request/context
lifecycle, it no longer needs to be pinned from context_queue to
retire_requests.
This fixes an issue with GuC submission where the GPU might not
have finished writing back the context before it is unpinned. This
results in a GPU hang.

v2: Moved the new pin to cover GuC submission (Alex Dai)
    Moved the new unpin to request_retire to fix coverage leak
v3: Added switch to default context if freeing a still pinned
    context just in case the hw was actually still using it
v4: Unwrapped context unpin to allow calling without a request
v5: Only create a switch to idle context if the ring doesn't
    already have a request pending on it (Alex Dai)
    Rename unsaved to dirty to avoid double negatives (Dave Gordon)
    Changed _no_req postfix to __ prefix for consistency (Dave Gordon)
    Split out per engine cleanup from context_free as it
    was getting unwieldy
    Corrected locking (Dave Gordon)
v6: Removed some bikeshedding (Mika Kuoppala)
    Added explanation of the GuC hang that this fixes (Daniel Vetter)
v7: Removed extra per request pinning from ring reset code (Alex Dai)
    Added forced ring unpin/clean in error case in context free (Alex Dai)
v8: Renamed lrc specific last_context to lrc_last_context as there
    were some reset cases where the codepaths leaked (Mika Kuoppala)
    NULL'd last_context in reset case - there was a pointer leak
    if someone did reset->close context.
v9: Rebase over "Fix context/engine cleanup order"

Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
Issue: VIZ-4277
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: David Gordon <david.s.gordon@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Alex Dai <yu.dai@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         |   1 +
 drivers/gpu/drm/i915/i915_gem.c         |   7 +-
 drivers/gpu/drm/i915/intel_lrc.c        | 146 ++++++++++++++++++++++++++------
 drivers/gpu/drm/i915/intel_lrc.h        |   1 +
 drivers/gpu/drm/i915/intel_ringbuffer.h |   1 +
 5 files changed, 124 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 27bb401..2f6f411 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -887,6 +887,7 @@ struct intel_context {
 	struct {
 		struct drm_i915_gem_object *state;
 		struct intel_ringbuffer *ringbuf;
+		bool dirty;
 		int pin_count;
 	} engine[I915_NUM_RINGS];
 
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 517676a..69e904f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1362,6 +1362,9 @@ static void i915_gem_request_retire(struct drm_i915_gem_request *request)
 {
 	trace_i915_gem_request_retire(request);
 
+	if (i915.enable_execlists)
+		intel_lr_context_complete_check(request);
+
 	/* We know the GPU must have read the request to have
 	 * sent us the seqno + interrupt, so use the position
 	 * of tail of the request to update the last known position
@@ -2772,10 +2775,6 @@ static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
 					struct drm_i915_gem_request,
 					execlist_link);
 			list_del(&submit_req->execlist_link);
-
-			if (submit_req->ctx != ring->default_context)
-				intel_lr_context_unpin(submit_req);
-
 			i915_gem_request_unreference(submit_req);
 		}
 		spin_unlock_irq(&ring->execlist_lock);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index d542a8d..01063f7 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -570,9 +570,6 @@ static int execlists_context_queue(struct drm_i915_gem_request *request)
 	struct drm_i915_gem_request *cursor;
 	int num_elements = 0;
 
-	if (request->ctx != ring->default_context)
-		intel_lr_context_pin(request);
-
 	i915_gem_request_reference(request);
 
 	spin_lock_irq(&ring->execlist_lock);
@@ -736,6 +733,13 @@ intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
 	if (intel_ring_stopped(ring))
 		return;
 
+	if (request->ctx != ring->default_context) {
+		if (!request->ctx->engine[ring->id].dirty) {
+			intel_lr_context_pin(request);
+			request->ctx->engine[ring->id].dirty = true;
+		}
+	}
+
 	if (dev_priv->guc.execbuf_client)
 		i915_guc_submit(dev_priv->guc.execbuf_client, request);
 	else
@@ -962,12 +966,6 @@ void intel_execlists_retire_requests(struct intel_engine_cs *ring)
 	spin_unlock_irq(&ring->execlist_lock);
 
 	list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
-		struct intel_context *ctx = req->ctx;
-		struct drm_i915_gem_object *ctx_obj =
-				ctx->engine[ring->id].state;
-
-		if (ctx_obj && (ctx != ring->default_context))
-			intel_lr_context_unpin(req);
 		list_del(&req->execlist_link);
 		i915_gem_request_unreference(req);
 	}
@@ -1062,21 +1060,39 @@ reset_pin_count:
 	return ret;
 }
 
-void intel_lr_context_unpin(struct drm_i915_gem_request *rq)
+static void __intel_lr_context_unpin(struct intel_engine_cs *ring,
+		struct intel_context *ctx)
 {
-	struct intel_engine_cs *ring = rq->ring;
-	struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
-	struct intel_ringbuffer *ringbuf = rq->ringbuf;
-
+	struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
+	struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
 	if (ctx_obj) {
 		WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
-		if (--rq->ctx->engine[ring->id].pin_count == 0) {
+		if (--ctx->engine[ring->id].pin_count == 0) {
 			intel_unpin_ringbuffer_obj(ringbuf);
 			i915_gem_object_ggtt_unpin(ctx_obj);
 		}
 	}
 }
 
+void intel_lr_context_unpin(struct drm_i915_gem_request *rq)
+{
+	__intel_lr_context_unpin(rq->ring, rq->ctx);
+}
+
+void intel_lr_context_complete_check(struct drm_i915_gem_request *req)
+{
+	struct intel_engine_cs *ring = req->ring;
+
+	if (ring->lrc_last_context && ring->lrc_last_context != req->ctx &&
+			ring->lrc_last_context->engine[ring->id].dirty) {
+		__intel_lr_context_unpin(
+				ring,
+				ring->lrc_last_context);
+		ring->lrc_last_context->engine[ring->id].dirty = false;
+	}
+	ring->lrc_last_context = req->ctx;
+}
+
 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
 {
 	int ret, i;
@@ -2350,6 +2366,81 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o
 }
 
 /**
+ * intel_lr_context_clean_ring() - clean the ring specific parts of an LRC
+ * @ctx: the LR context being freed.
+ * @ring: the engine being cleaned
+ * @ctx_obj: the hw context being unreferenced
+ * @ringbuf: the ringbuf being freed
+ *
+ * Take care of cleaning up the per-engine backing
+ * objects and the logical ringbuffer.
+ */
+static void
+intel_lr_context_clean_ring(struct intel_context *ctx,
+			    struct drm_i915_gem_object *ctx_obj,
+			    struct intel_ringbuffer *ringbuf)
+{
+	int ret;
+	struct intel_engine_cs *ring = ringbuf->ring;
+
+	WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
+
+	if (ctx->is_global_default) {
+		/*
+		 * The HWSP is part of the default context
+		 * object in LRC mode.
+		 */
+		lrc_teardown_hardware_status_page(ring);
+		intel_unpin_ringbuffer_obj(ringbuf);
+		i915_gem_object_ggtt_unpin(ctx_obj);
+	}
+
+	if (ctx->engine[ring->id].dirty) {
+		struct drm_i915_gem_request *req = NULL;
+
+		/**
+		 * If there is already a request pending on
+		 * this ring, wait for that to complete,
+		 * otherwise create a switch to idle request
+		 */
+		if (list_empty(&ring->request_list)) {
+			int ret;
+
+			ret = i915_gem_request_alloc(
+					ring,
+					ring->default_context,
+					&req);
+			if (!ret)
+				i915_add_request(req);
+			else
+				DRM_DEBUG("Failed to ensure context saved");
+		} else {
+			req = list_first_entry(
+					&ring->request_list,
+					typeof(*req), list);
+		}
+		if (req) {
+			ret = i915_wait_request(req);
+			if (ret != 0) {
+				/**
+				 * If we get here, there's probably been a ring
+				 * reset, so we just clean up the dirty flag.&
+				 * pin count.
+				 */
+				ctx->engine[ring->id].dirty = false;
+				__intel_lr_context_unpin(
+					ring,
+					ctx);
+			}
+		}
+	}
+
+	WARN_ON(ctx->engine[ring->id].pin_count);
+	intel_ringbuffer_free(ringbuf);
+	drm_gem_object_unreference(&ctx_obj->base);
+}
+
+/**
  * intel_lr_context_free() - free the LRC specific bits of a context
  * @ctx: the LR context to free.
  *
@@ -2368,19 +2459,9 @@ void intel_lr_context_free(struct intel_context *ctx)
 		if (!ctx_obj)
 			continue;
 
-		if (ctx->is_global_default) {
-			/*
-			 * The HWSP is part of the default context
-			 * object in LRC mode.
-			 */
-			lrc_teardown_hardware_status_page(ringbuf->ring);
-			intel_unpin_ringbuffer_obj(ringbuf);
-			i915_gem_object_ggtt_unpin(ctx_obj);
-		}
-
-		WARN_ON(ctx->engine[i].pin_count);
-		intel_ringbuffer_free(ringbuf);
-		drm_gem_object_unreference(&ctx_obj->base);
+		intel_lr_context_clean_ring(ctx,
+					    ctx_obj,
+					    ringbuf);
 	}
 }
 
@@ -2562,5 +2643,14 @@ void intel_lr_context_reset(struct drm_device *dev,
 
 		ringbuf->head = 0;
 		ringbuf->tail = 0;
+
+		if (ctx->engine[ring->id].dirty) {
+			__intel_lr_context_unpin(
+					ring,
+					ctx);
+			ctx->engine[ring->id].dirty = false;
+			if (ring->lrc_last_context == ctx)
+				ring->lrc_last_context = NULL;
+		}
 	}
 }
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 0b821b9..fd1b6b4 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -91,6 +91,7 @@ void intel_lr_context_reset(struct drm_device *dev,
 			struct intel_context *ctx);
 uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
 				     struct intel_engine_cs *ring);
+void intel_lr_context_complete_check(struct drm_i915_gem_request *req);
 
 /* Execlists */
 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 49574ff..9bd98db 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -275,6 +275,7 @@ struct  intel_engine_cs {
 				      u32 flush_domains);
 	int		(*emit_bb_start)(struct drm_i915_gem_request *req,
 					 u64 offset, unsigned dispatch_flags);
+	struct intel_context *lrc_last_context;
 
 	/**
 	 * List of objects currently involved in rendering from the
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [RFC] drm/i915/bdw+: Do not emit user interrupts when not needed
@ 2015-12-18 11:59 Tvrtko Ursulin
  2015-12-18 12:30 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Tvrtko Ursulin @ 2015-12-18 11:59 UTC (permalink / raw)
  To: Intel-gfx

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

We can rely on context complete interrupt to wake up the waiters
apart in the case where requests are merged into a single ELSP
submission. In this case we inject MI_USER_INTERRUPTS in the
ring buffer to ensure prompt wake-ups.

This optimization has the effect on for example GLBenchmark
Egypt off-screen test of decreasing the number of generated
interrupts per second by a factor of two, and context switched
by factor of five to six.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/i915_irq.c  | 24 ++++++++++++------------
 drivers/gpu/drm/i915/intel_lrc.c | 26 +++++++++++++++++++++++++-
 3 files changed, 38 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1d28d90ed901..f6fd2023aaf0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2811,6 +2811,7 @@ ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
 	ibx_display_interrupt_update(dev_priv, bits, 0);
 }
 
+void intel_notify_ring(struct intel_engine_cs *ring);
 
 /* i915_gem.c */
 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3f8c753997ba..a2087bad0d64 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -994,7 +994,7 @@ static void ironlake_rps_change_irq_handler(struct drm_device *dev)
 	return;
 }
 
-static void notify_ring(struct intel_engine_cs *ring)
+void intel_notify_ring(struct intel_engine_cs *ring)
 {
 	if (!intel_ring_initialized(ring))
 		return;
@@ -1291,9 +1291,9 @@ static void ilk_gt_irq_handler(struct drm_device *dev,
 {
 	if (gt_iir &
 	    (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
-		notify_ring(&dev_priv->ring[RCS]);
+		intel_notify_ring(&dev_priv->ring[RCS]);
 	if (gt_iir & ILK_BSD_USER_INTERRUPT)
-		notify_ring(&dev_priv->ring[VCS]);
+		intel_notify_ring(&dev_priv->ring[VCS]);
 }
 
 static void snb_gt_irq_handler(struct drm_device *dev,
@@ -1303,11 +1303,11 @@ static void snb_gt_irq_handler(struct drm_device *dev,
 
 	if (gt_iir &
 	    (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
-		notify_ring(&dev_priv->ring[RCS]);
+		intel_notify_ring(&dev_priv->ring[RCS]);
 	if (gt_iir & GT_BSD_USER_INTERRUPT)
-		notify_ring(&dev_priv->ring[VCS]);
+		intel_notify_ring(&dev_priv->ring[VCS]);
 	if (gt_iir & GT_BLT_USER_INTERRUPT)
-		notify_ring(&dev_priv->ring[BCS]);
+		intel_notify_ring(&dev_priv->ring[BCS]);
 
 	if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
 		      GT_BSD_CS_ERROR_INTERRUPT |
@@ -1322,7 +1322,7 @@ static __always_inline void
 gen8_cs_irq_handler(struct intel_engine_cs *ring, u32 iir, int test_shift)
 {
 	if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
-		notify_ring(ring);
+		intel_notify_ring(ring);
 	if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
 		intel_lrc_irq_handler(ring);
 }
@@ -1629,7 +1629,7 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
 
 	if (HAS_VEBOX(dev_priv->dev)) {
 		if (pm_iir & PM_VEBOX_USER_INTERRUPT)
-			notify_ring(&dev_priv->ring[VECS]);
+			intel_notify_ring(&dev_priv->ring[VECS]);
 
 		if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
 			DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
@@ -3961,7 +3961,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
 		new_iir = I915_READ16(IIR); /* Flush posted writes */
 
 		if (iir & I915_USER_INTERRUPT)
-			notify_ring(&dev_priv->ring[RCS]);
+			intel_notify_ring(&dev_priv->ring[RCS]);
 
 		for_each_pipe(dev_priv, pipe) {
 			int plane = pipe;
@@ -4157,7 +4157,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
 		new_iir = I915_READ(IIR); /* Flush posted writes */
 
 		if (iir & I915_USER_INTERRUPT)
-			notify_ring(&dev_priv->ring[RCS]);
+			intel_notify_ring(&dev_priv->ring[RCS]);
 
 		for_each_pipe(dev_priv, pipe) {
 			int plane = pipe;
@@ -4387,9 +4387,9 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
 		new_iir = I915_READ(IIR); /* Flush posted writes */
 
 		if (iir & I915_USER_INTERRUPT)
-			notify_ring(&dev_priv->ring[RCS]);
+			intel_notify_ring(&dev_priv->ring[RCS]);
 		if (iir & I915_BSD_USER_INTERRUPT)
-			notify_ring(&dev_priv->ring[VCS]);
+			intel_notify_ring(&dev_priv->ring[VCS]);
 
 		for_each_pipe(dev_priv, pipe) {
 			if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 27f06198a51e..d9be878dbde7 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -359,6 +359,13 @@ static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
 	spin_unlock(&dev_priv->uncore.lock);
 }
 
+static void execlists_emit_user_interrupt(struct drm_i915_gem_request *req)
+{
+	struct intel_ringbuffer *ringbuf = req->ringbuf;
+
+	iowrite32(MI_USER_INTERRUPT, ringbuf->virtual_start + req->tail - 8);
+}
+
 static int execlists_update_context(struct drm_i915_gem_request *rq)
 {
 	struct intel_engine_cs *ring = rq->ring;
@@ -433,6 +440,12 @@ static void execlists_context_unqueue(struct intel_engine_cs *ring)
 			cursor->elsp_submitted = req0->elsp_submitted;
 			list_move_tail(&req0->execlist_link,
 				       &ring->execlist_retired_req_list);
+			/*
+			 * When merging requests make sure there is still
+			 * something after each batch buffer to wake up waiters.
+			 */
+			if (cursor != req0)
+				execlists_emit_user_interrupt(req0);
 			req0 = cursor;
 		} else {
 			req1 = cursor;
@@ -472,6 +485,12 @@ static bool execlists_check_remove_request(struct intel_engine_cs *ring,
 
 	assert_spin_locked(&ring->execlist_lock);
 
+	/*
+	 * This is effectively a context complete interrupt so wake
+	 * up potential waiters on this ring.
+	 */
+	intel_notify_ring(ring);
+
 	head_req = list_first_entry_or_null(&ring->execlist_queue,
 					    struct drm_i915_gem_request,
 					    execlist_link);
@@ -1812,7 +1831,12 @@ static int gen8_emit_request(struct drm_i915_gem_request *request)
 				(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
 	intel_logical_ring_emit(ringbuf, 0);
 	intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
-	intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
+	/*
+	 * Following noop is a placeholder for an optional MI_USER_INTERRUPT
+	 * which will be patched in at ELSP submission time if this request
+	 * will not be ending with a context complete interrupt.
+	 */
+	intel_logical_ring_emit(ringbuf, MI_NOOP);
 	intel_logical_ring_emit(ringbuf, MI_NOOP);
 	intel_logical_ring_advance_and_submit(request);
 
-- 
1.9.1

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH] drm/i915/bdw+: Replace list_del+list_add_tail with list_move_tail
@ 2015-12-18 10:53 Tvrtko Ursulin
  2015-12-18 11:49 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Tvrtko Ursulin @ 2015-12-18 10:53 UTC (permalink / raw)
  To: Intel-gfx

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Same effect for slightly less source code and resulting binary.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 15 ++++++---------
 1 file changed, 6 insertions(+), 9 deletions(-)

Compile tested only!

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 3aa614731d7e..27f06198a51e 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -431,9 +431,8 @@ static void execlists_context_unqueue(struct intel_engine_cs *ring)
 			/* Same ctx: ignore first request, as second request
 			 * will update tail past first request's workload */
 			cursor->elsp_submitted = req0->elsp_submitted;
-			list_del(&req0->execlist_link);
-			list_add_tail(&req0->execlist_link,
-				&ring->execlist_retired_req_list);
+			list_move_tail(&req0->execlist_link,
+				       &ring->execlist_retired_req_list);
 			req0 = cursor;
 		} else {
 			req1 = cursor;
@@ -485,9 +484,8 @@ static bool execlists_check_remove_request(struct intel_engine_cs *ring,
 			     "Never submitted head request\n");
 
 			if (--head_req->elsp_submitted <= 0) {
-				list_del(&head_req->execlist_link);
-				list_add_tail(&head_req->execlist_link,
-					&ring->execlist_retired_req_list);
+				list_move_tail(&head_req->execlist_link,
+					       &ring->execlist_retired_req_list);
 				return true;
 			}
 		}
@@ -592,9 +590,8 @@ static int execlists_context_queue(struct drm_i915_gem_request *request)
 		if (request->ctx == tail_req->ctx) {
 			WARN(tail_req->elsp_submitted != 0,
 				"More than 2 already-submitted reqs queued\n");
-			list_del(&tail_req->execlist_link);
-			list_add_tail(&tail_req->execlist_link,
-				&ring->execlist_retired_req_list);
+			list_move_tail(&tail_req->execlist_link,
+				       &ring->execlist_retired_req_list);
 		}
 	}
 
-- 
1.9.1

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH] drm/i915/vlv: Modifying RC6 Promotion timer for Media workloads.
@ 2015-12-18 10:14 Namrta Salonie
  2015-12-18 10:30 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Namrta Salonie @ 2015-12-18 10:14 UTC (permalink / raw)
  To: intel-gfx; +Cc: akash.goel, Satyanantha, Rama Gopal M

In normal cases, RC6 promotion timer is 1700us. This will result in more
time spent in C1 state. For more residency in C6 in case of media workloads,
this is changed to 250us. Not doing this for 3D workloads as too many C6-C0
transition delays can result in performance impact. Tracking the media
workloads based on command submission to MFX engine.

Signed-off-by: Namrta Salonie <namrta.salonie@intel.com>
Signed-off-by: Satyanantha, Rama Gopal M <rama.gopal.m.satyanantha@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h            |    3 +++
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |   14 +++++++++++++
 drivers/gpu/drm/i915/i915_reg.h            |    2 ++
 drivers/gpu/drm/i915/intel_drv.h           |    2 ++
 drivers/gpu/drm/i915/intel_pm.c            |   30 +++++++++++++++++++++++++++-
 5 files changed, 50 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bc865e23..74c9f86 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1147,6 +1147,9 @@ struct intel_gen6_power_mgmt {
 	 * talking to hw - so only take it when talking to hw!
 	 */
 	struct mutex hw_lock;
+
+	/* Delayed work to adjust RC6 promotion timer */
+	struct delayed_work vlv_media_timeout_work;
 };
 
 /* defined intel_pm.c */
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index a4c243c..af7fbf8 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1254,6 +1254,20 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
 			return ret;
 	}
 
+	/* For VLV, modify RC6 promotion timer upon hitting Media workload only
+	   This will help in better power savings with media scenarios.
+	 */
+	if (((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) &&
+			!IS_CHERRYVIEW(dev) && IS_VALLEYVIEW(dev) &&
+			dev_priv->rps.enabled) {
+		vlv_modify_rc6_promotion_timer(dev_priv, true);
+
+		/*Start a timer for 1 sec to reset this value to original*/
+		mod_delayed_work(dev_priv->wq,
+				&dev_priv->rps.vlv_media_timeout_work,
+				msecs_to_jiffies(1000));
+	}
+
 	exec_len   = args->batch_len;
 	exec_start = params->batch_obj_vm_offset +
 		     params->args_batch_start_offset;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4872245..3f66f5d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6905,6 +6905,8 @@ enum skl_disp_power_wells {
 #define GEN6_RCUBMABDTMR			_MMIO(0xA0B0)
 #define GEN6_RC1e_THRESHOLD			_MMIO(0xA0B4)
 #define GEN6_RC6_THRESHOLD			_MMIO(0xA0B8)
+#define GEN6_RC6_RENDER_PROMOTION_TIMER_TO      0x0557
+#define GEN6_RC6_MEDIA_PROMOTION_TIMER_TO       0x00C3
 #define GEN6_RC6p_THRESHOLD			_MMIO(0xA0BC)
 #define VLV_RCEDATA				_MMIO(0xA0BC)
 #define GEN6_RC6pp_THRESHOLD			_MMIO(0xA0C0)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8fae824..e563d65 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1283,6 +1283,8 @@ void intel_dsi_init(struct drm_device *dev);
 /* intel_dvo.c */
 void intel_dvo_init(struct drm_device *dev);
 
+extern void vlv_modify_rc6_promotion_timer(struct drm_i915_private *dev_priv,
+					   bool media_active);
 
 /* legacy fbdev emulation in intel_fbdev.c */
 #ifdef CONFIG_DRM_FBDEV_EMULATION
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1c1ea63..149b944 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4492,6 +4492,26 @@ static void valleyview_disable_rps(struct drm_device *dev)
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 }
 
+void vlv_modify_rc6_promotion_timer(struct drm_i915_private *dev_priv,
+		bool media_active)
+{
+	/* Update RC6 promotion timers */
+	if (media_active)
+		I915_WRITE(GEN6_RC6_THRESHOLD,
+				GEN6_RC6_MEDIA_PROMOTION_TIMER_TO);
+	else
+		I915_WRITE(GEN6_RC6_THRESHOLD,
+				GEN6_RC6_RENDER_PROMOTION_TIMER_TO);
+}
+
+static void vlv_media_timeout_work_func(struct work_struct *work)
+{
+	struct drm_i915_private *dev_priv = container_of(work, struct drm_i915_private,
+			rps.vlv_media_timeout_work.work);
+
+	vlv_modify_rc6_promotion_timer(dev_priv, false);
+}
+
 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
 {
 	if (IS_VALLEYVIEW(dev)) {
@@ -6050,7 +6070,9 @@ static void gen6_suspend_rps(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);
-
+	/*Cancel any pending work-item*/
+	cancel_delayed_work_sync(&dev_priv->rps.vlv_media_timeout_work);
+	
 	gen6_disable_rps_interrupts(dev);
 }
 
@@ -7258,6 +7280,12 @@ void intel_pm_setup(struct drm_device *dev)
 
 	INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
 			  intel_gen6_powersave_work);
+	/* Initialize a work item to modify RC6 promotion timer
+	 * based on MFX engine activity
+	 */
+	INIT_DELAYED_WORK(&dev_priv->rps.vlv_media_timeout_work,
+			vlv_media_timeout_work_func);
+
 	INIT_LIST_HEAD(&dev_priv->rps.clients);
 	INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
 	INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
-- 
1.7.9.5

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^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH] drm/i915: edp resume/On time optimization.
@ 2015-12-18  6:27 abhay.kumar
  2015-12-18  9:01 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: abhay.kumar @ 2015-12-18  6:27 UTC (permalink / raw)
  To: Intel-gfx

From: Abhay Kumar <abhay.kumar@intel.com>

Make resume codepath not to wait for panel_power_cycle_delay(t11_t12)
if this time is already spent in suspend/poweron time.

Change-Id: Ied0f10f82776af8e6e8ff561bb4e5c0ce1dad4b3
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c |  3 +++
 drivers/gpu/drm/i915/intel_dp.c  | 21 +++++++++++++--------
 drivers/gpu/drm/i915/intel_drv.h |  2 +-
 3 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index cbabcb4..fe99d72 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2347,6 +2347,9 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
 		intel_edp_panel_vdd_on(intel_dp);
 		intel_edp_panel_off(intel_dp);
+
+		/* storing panel power off time */
+		intel_dp->panel_power_off_time = ktime_get_with_offset(TK_OFFS_BOOT);
 	}
 
 	if (IS_SKYLAKE(dev))
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index acda70e..509da67 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -38,7 +38,6 @@
 #include "intel_drv.h"
 #include <drm/i915_drm.h>
 #include "i915_drv.h"
-
 #define DP_LINK_CHECK_TIMEOUT	(10 * 1000)
 
 /* Compliance test status bits  */
@@ -1654,13 +1653,21 @@ static void wait_panel_off(struct intel_dp *intel_dp)
 
 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
 {
+	ktime_t panel_power_on_time;
+	u32 panel_power_off_duration;
+
 	DRM_DEBUG_KMS("Wait for panel power cycle\n");
 
-	/* When we disable the VDD override bit last we have to do the manual
-	 * wait. */
-	wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
-				       intel_dp->panel_power_cycle_delay);
+        /* take the diffrence of currrent time and panel power off time
+           and then make panel wait for t11_t12 if needed */
+        panel_power_on_time = ktime_get_with_offset(TK_OFFS_BOOT);
+        panel_power_off_duration = (panel_power_on_time.tv64 - intel_dp->panel_power_off_time.tv64) / 1000000;
 
+	/* When we disable the VDD override bit last we have to do the manual
+	 * wait */
+	if (panel_power_off_duration < intel_dp->panel_power_cycle_delay)
+		wait_remaining_ms_from_jiffies(jiffies,
+				       (intel_dp->panel_power_cycle_delay - panel_power_off_duration));
 	wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 }
 
@@ -1811,7 +1818,7 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
 	I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
 
 	if ((pp & POWER_TARGET_ON) == 0)
-		intel_dp->last_power_cycle = jiffies;
+		intel_dp->panel_power_off_time = ktime_get_with_offset(TK_OFFS_BOOT);
 
 	power_domain = intel_display_port_power_domain(intel_encoder);
 	intel_display_power_put(dev_priv, power_domain);
@@ -1960,7 +1967,6 @@ static void edp_panel_off(struct intel_dp *intel_dp)
 	I915_WRITE(pp_ctrl_reg, pp);
 	POSTING_READ(pp_ctrl_reg);
 
-	intel_dp->last_power_cycle = jiffies;
 	wait_panel_off(intel_dp);
 
 	/* We got a reference when we enabled the VDD. */
@@ -5196,7 +5202,6 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
 
 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
 {
-	intel_dp->last_power_cycle = jiffies;
 	intel_dp->last_power_on = jiffies;
 	intel_dp->last_backlight_off = jiffies;
 }
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d44f2f5..ef82e8f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -722,9 +722,9 @@ struct intel_dp {
 	int backlight_off_delay;
 	struct delayed_work panel_vdd_work;
 	bool want_panel_vdd;
-	unsigned long last_power_cycle;
 	unsigned long last_power_on;
 	unsigned long last_backlight_off;
+	ktime_t panel_power_off_time;
 
 	struct notifier_block edp_notifier;
 
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH] drm/i915: HWSTAM is not a thing on SKL+
@ 2015-12-18  1:16 Ben Widawsky
  2015-12-18  8:30 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Ben Widawsky @ 2015-12-18  1:16 UTC (permalink / raw)
  To: Intel GFX; +Cc: Ben Widawsky

Compile tested only.

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 42a7be1..a9bc207 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1466,7 +1466,8 @@ static int gen8_init_common_ring(struct intel_engine_cs *ring)
 	u8 next_context_status_buffer_hw;
 
 	I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
-	I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
+	if (INTEL_INFO(ring->dev)->gen == 8)
+		I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
 
 	if (ring->status_page.obj) {
 		I915_WRITE(RING_HWS_PGA(ring->mmio_base),
-- 
2.6.4

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^ permalink raw reply related	[flat|nested] 76+ messages in thread
* [PATCH 00/10] drm/i915: Fixes from my attempt at running igt on gen2
@ 2015-12-14 16:23 ville.syrjala
  2016-01-12  7:49 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: ville.syrjala @ 2015-12-14 16:23 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

It's been a while since I last ran igt on gen2, so I figured I'd
give it a shot. 855 had some failures, 830 no longer worked at
all. So I went ahead and fixed them, and here's the result.

The first three patches are not even gen2 specific bugs I caught
with this effort. The rest is for gen2.

I have some fixes for igt as well, which I'll post separately.

The good news is that with these patches (and the igt fixes) my
855 completes a full kms_flip run without failures, and the BAT
set has only one failure (gem_render_tiled_blits). 830 is fairly
good too, but it does have a lot of underruns and pipe_assert()
dmesg warnings. Lot of those are due to the pipe enable quirks
since we implement those quite haphazardly.

The series is available here:
git://github.com/vsyrjala/linux.git gen2_igt_fixes

Ville Syrjälä (10):
  drm/i915: Release mmaps on partial ggtt vma unbind
  drm/i915: Cleanup phys status page too
  drm/i915: Write out crc frame counts in hex
  drm/i915: Wait for pipe to start before sampling vblank timestamps on
    gen2
  drm/i915: Use drm_vblank_count() on gen2 for crc frame count
  drm/i915: Enable vblank_disable_immediate on gen2
  drm/i915: Allow 27 bytes child_dev for VBT <109
  drm/i915: Expect child dev size of 22 bytes for VBT < 106
  drm/i915: Reject < 8 byte batches on 830/845
  drm/i915: Use MI_BATCH_BUFFER_START on 830/845

 drivers/gpu/drm/i915/i915_debugfs.c        | 13 ++++++++++++-
 drivers/gpu/drm/i915/i915_gem.c            |  3 +++
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |  3 +++
 drivers/gpu/drm/i915/i915_irq.c            | 14 +++++---------
 drivers/gpu/drm/i915/intel_bios.c          | 21 ++++++++++++--------
 drivers/gpu/drm/i915/intel_display.c       | 11 +++++++++++
 drivers/gpu/drm/i915/intel_ringbuffer.c    | 31 +++++++++++++++++++++++-------
 7 files changed, 71 insertions(+), 25 deletions(-)

-- 
2.4.10

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^ permalink raw reply	[flat|nested] 76+ messages in thread
* [PATCH] drm/i915: Avoid writing relocs with addresses in non-canonical form
@ 2015-12-04 11:33 Michał Winiarski
  2015-12-29 16:20 ` ✗ failure: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 76+ messages in thread
From: Michał Winiarski @ 2015-12-04 11:33 UTC (permalink / raw)
  To: intel-gfx

According to bspec, some parts of HW expect the addresses to be in
a canonical form, where bits [63:48] == [47]. Let's convert addresses to
canonical form prior to relocating and return converted offsets to
userspace.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 9 ++++++---
 drivers/gpu/drm/i915/i915_gem_gtt.h        | 5 +++++
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index a4c243c..9f27be9 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -395,7 +395,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
 	target_i915_obj = target_vma->obj;
 	target_obj = &target_vma->obj->base;
 
-	target_offset = target_vma->node.start;
+	target_offset = gen8_canonical_addr(target_vma->node.start);
 
 	/* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
 	 * pipe_control writes because the gpu doesn't properly redirect them
@@ -583,6 +583,7 @@ i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
 	struct drm_i915_gem_object *obj = vma->obj;
 	struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 	uint64_t flags;
+	uint64_t offset;
 	int ret;
 
 	flags = PIN_USER;
@@ -623,8 +624,10 @@ i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
 			entry->flags |= __EXEC_OBJECT_HAS_FENCE;
 	}
 
-	if (entry->offset != vma->node.start) {
-		entry->offset = vma->node.start;
+	offset = gen8_canonical_addr(vma->node.start);
+
+	if (entry->offset != offset) {
+		entry->offset = offset;
 		*need_reloc = true;
 	}
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 877c32c..65e8f88 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -507,6 +507,11 @@ static inline size_t gen8_pte_count(uint64_t address, uint64_t length)
 	return i915_pte_count(address, length, GEN8_PDE_SHIFT);
 }
 
+static inline uint64_t gen8_canonical_addr(uint64_t address)
+{
+	return ((int64_t)address << 16) >> 16;
+}
+
 static inline dma_addr_t
 i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n)
 {
-- 
2.5.0

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^ permalink raw reply related	[flat|nested] 76+ messages in thread
end of thread, other threads:[~2016-01-19 16:43 UTC | newest]

Thread overview: 76+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-01-05 19:10 [PATCH] drm/i915/guc: Enable GuC submission, where supported yu.dai
2016-01-06 10:20 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-07 10:27   ` Dave Gordon
2016-01-07 13:06     ` Jani Nikula
2016-01-07 14:36       ` Daniel Vetter
2016-01-07 14:51         ` Jani Nikula
2016-01-07 15:37         ` Dave Gordon
  -- strict thread matches above, loose matches on Subject: below --
2016-01-14 15:56 [PATCH v5 1/1] drm/i915/bxt: Check BIOS RC6 setup before enabling RC6 Sagar Arun Kamble
2016-01-14 16:30 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-14 15:12 [PATCH] drm/i915/bios: Fix the sequence size calculations for MIPI seq v3 Jani Nikula
2016-01-14 16:20 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-14 15:02 [PATCH] drm/i915: Decouple execbuf uAPI from internal implementation Tvrtko Ursulin
2016-01-14 15:49 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-14 13:22 [PATCH 0/8] drm/i915: Some more fb offsets[] prep stuff ville.syrjala
2016-01-14 14:49 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-14 15:00   ` Ville Syrjälä
2016-01-15 12:03     ` Chris Wilson
2016-01-14 12:53 [PATCH 1/2] drm/i915: Start WM computation from scratch on ILK-BDW ville.syrjala
2016-01-14 14:20 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-14 14:29   ` Ville Syrjälä
2016-01-19 13:58     ` Daniel Vetter
2016-01-19 14:09       ` Ville Syrjälä
2016-01-19 16:43         ` Daniel Vetter
2016-01-14 10:49 [PATCH] drm/i915: Clear pending reset requests during suspend Arun Siluvery
2016-01-14 12:20 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-14  6:16 [PATCH v14 0/11] Support for creating/using Stolen memory backed objects ankitprasad.r.sharma
2016-01-14 11:20 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-13 17:28 [PATCH 00/20] TDR/watchdog support for gen8 Arun Siluvery
2016-01-14  8:30 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-13 16:19 [PATCH v10] drm/i915: Extend LRC pinning to cover GPU context writeback Nick Hoath
2016-01-14  7:20 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-14 11:31   ` Nick Hoath
2016-01-19  9:08     ` Daniel Vetter
2016-01-13 14:35 [PATCH] drm/i915/dp: fall back to 18 bpp when sink capability is unknown Jani Nikula
2016-01-13 15:13 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-13 16:17   ` Daniel Vetter
2016-01-13 18:03     ` Chris Wilson
2016-01-13 12:52 [PATCH] drm/i915: Fix for reserved space WARN_ON when ring begin fails John.C.Harrison
2016-01-13 13:49 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-12 15:28 [PATCH 1/1] drm/i915: Reorder shadow registers on gen8 for faster lookup Mika Kuoppala
2016-01-12 16:20 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-11 21:40 [PATCH 00/22] drm_event cleanup, round 2 Daniel Vetter
2016-01-12  8:30 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-11 12:27 [PATCH v2 0/9] Kill off intel_crtc->atomic! Maarten Lankhorst
2016-01-11 12:49 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-11 14:30 ` Patchwork
2016-01-08 21:40 [PATCH] drm/i915: Reject invalid-pad for context-destroy ioctl Chris Wilson
2016-01-11 11:07 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-08 20:36 [PATCH 00/21] drm_event cleanup Daniel Vetter
2016-01-11 11:20 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-12 16:24   ` Daniel Vetter
2016-01-08 16:58 [PATCH 1/2] drm/i915: Store edram capabilities instead of fixed size Mika Kuoppala
2016-01-11 10:27 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-08 13:51 [PATCH 1/2] drm/i915: Enable mmio_debug for vlv/chv Mika Kuoppala
2016-01-11  9:59 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-11 12:50   ` Mika Kuoppala
2016-01-12 16:22     ` Daniel Vetter
2016-01-13  9:16       ` Mika Kuoppala
2016-01-13  9:20       ` Mika Kuoppala
2016-01-13  9:39         ` Daniel Vetter
2016-01-13  9:39           ` Daniel Vetter
2016-01-08 11:29 [PATCH v2 00/13] Misc cleanups and locking fixes Tvrtko Ursulin
2016-01-11  9:44 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-07 10:54 [PATCH 0/7] Explicitly pass crtc_state and plane_state to plane update functions Maarten Lankhorst
2016-01-11  8:53 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-07  9:10 [PATCH] drm/i915: Init power domains early in driver load Daniel Vetter
2016-01-11  9:12 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-06 20:53 [PATCH] drm/i915/guc: Fix a memory leak where guc->execbuf_client is not freed yu.dai
2016-01-13  8:49 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-06 11:09 [PATCH 1/3] drm: Defer disabling the vblank IRQ until the next interrupt (for instant-off) Chris Wilson
2016-01-06 13:20 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-06  2:26 [PATCH 1/2] drm/i915: fix get digital port issue in intel_audio libin.yang
2016-01-06 12:49 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-05 19:18 [PATCH] drm/i915: Cleaning up DDI translation tables Rodrigo Vivi
2016-01-06 11:30 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-05 16:54 [PATCH] drm/i915: Tune down rpm wakelock debug checks Daniel Vetter
2016-01-06  7:49 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-04 10:13 [PATCH] drm/i915: Force clean compilation with -Werror Chris Wilson
2016-01-04 11:01 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-04 10:10 [PATCH 1/3] drm: Balance error path for GEM handle allocation Chris Wilson
2016-01-04 10:49 ` ✗ failure: Fi.CI.BAT Patchwork
2015-12-31 12:45 [PATCH] drm/i915: Add RPM references in the *_get_hw_state functions Gabriel Feceoru
2015-12-31 13:20 ` ✗ failure: Fi.CI.BAT Patchwork
2015-12-30 22:56 [PATCH] drm/i915/bxt: Fix eDP panel power save/restore Matt Roper
2015-12-31  7:43 ` ✗ failure: Fi.CI.BAT Patchwork
2015-12-23  8:11 [PATCH] drm/i915: increase the tries for HDMI hotplug live status checking Gary Wang
2015-12-23  8:49 ` ✗ failure: Fi.CI.BAT Patchwork
2015-12-21 18:53 [PATCH] drm, i915: Fix pointer size cast Borislav Petkov
2015-12-22  7:30 ` ✗ failure: Fi.CI.BAT Patchwork
2015-12-21 16:04 improve handling of the driver's internal default context Dave Gordon
2015-12-22  7:20 ` ✗ failure: Fi.CI.BAT Patchwork
2015-12-21 15:33 [RFC v2] drm/i915/bdw+: Do not emit user interrupts when not needed Tvrtko Ursulin
2015-12-21 17:30 ` ✗ failure: Fi.CI.BAT Patchwork
2015-12-21 13:10 [PATCH 00/15] drm/i915/bios: mipi sequence block v3, etc Jani Nikula
2016-01-05 16:01 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-11 13:30 ` Patchwork
2016-01-11 14:01 ` Patchwork
2015-12-18 20:00 [PATCH v2 0/5] Add GuC ADS (Addition Data Structure) yu.dai
2016-01-05 12:30 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-06  9:01 ` Patchwork
2015-12-18 19:55 [PATCH] drm/i915: edp resume/On time optimization abhay.kumar
2015-12-19  7:30 ` ✗ failure: Fi.CI.BAT Patchwork
2015-12-18 17:24 [PATCH] drm/i915: Workaround CHV pipe C cursor fail ville.syrjala
2015-12-18 17:49 ` ✗ failure: Fi.CI.BAT Patchwork
2015-12-18 15:17 [PATCH] Allow userspace to set NULL blob on properties Lionel Landwerlin
2015-12-18 15:30 ` ✗ failure: Fi.CI.BAT Patchwork
2015-12-18 14:41 [PATCH v9] drm/i915: Extend LRC pinning to cover GPU context writeback Nick Hoath
2015-12-18 15:01 ` ✗ failure: Fi.CI.BAT Patchwork
2015-12-21 13:44   ` Daniel Vetter
2015-12-18 11:59 [RFC] drm/i915/bdw+: Do not emit user interrupts when not needed Tvrtko Ursulin
2015-12-18 12:30 ` ✗ failure: Fi.CI.BAT Patchwork
2015-12-18 10:53 [PATCH] drm/i915/bdw+: Replace list_del+list_add_tail with list_move_tail Tvrtko Ursulin
2015-12-18 11:49 ` ✗ failure: Fi.CI.BAT Patchwork
2015-12-18 10:14 [PATCH] drm/i915/vlv: Modifying RC6 Promotion timer for Media workloads Namrta Salonie
2015-12-18 10:30 ` ✗ failure: Fi.CI.BAT Patchwork
2015-12-18  6:27 [PATCH] drm/i915: edp resume/On time optimization abhay.kumar
2015-12-18  9:01 ` ✗ failure: Fi.CI.BAT Patchwork
2015-12-18  1:16 [PATCH] drm/i915: HWSTAM is not a thing on SKL+ Ben Widawsky
2015-12-18  8:30 ` ✗ failure: Fi.CI.BAT Patchwork
2015-12-14 16:23 [PATCH 00/10] drm/i915: Fixes from my attempt at running igt on gen2 ville.syrjala
2016-01-12  7:49 ` ✗ failure: Fi.CI.BAT Patchwork
2015-12-04 11:33 [PATCH] drm/i915: Avoid writing relocs with addresses in non-canonical form Michał Winiarski
2015-12-29 16:20 ` ✗ failure: Fi.CI.BAT Patchwork

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