* [PATCH v4 0/9] Add STM32 pinctrl/GPIO driver @ 2016-01-14 12:16 ` Maxime Coquelin 0 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-01-14 12:16 UTC (permalink / raw) To: patrice.chotard, Linus Walleij, Mark Rutland, Rob Herring, linux-gpio, arnd Cc: linux-arm-kernel, linux-kernel, afaerber, devicetree, Daniel Thompson, bruherrera This is the fourth round of STM32 pinctrl series, which takes into account comments made by Patrice on patch 4. The STM32 family has 16 pins per GPIO bank, and the number of bank varies depending on the model. Pins can be multiplexed either in GPIO mode, alternate function (up to 15 functions per pin) or analog (for ADC/DAC). Changes since v3: ----------------- - Rebase on v4.4 - Fix error paths in stm32_pctrl_dt_subnode_to_map() (Patrice) - Remove useless stm32_pctrl_find_function_by_pin function (Patrice) Changes since v2: ----------------- - Rebase on v4.4-rc1 - Declare leds also for Eval board - Set green led as heartbeat - Collect some acks Changes since v1: ----------------- - Add GPIO LEDs support in DT and defconfig - Changes pinmux DT bindings from macros to raw values (Daniel) - Improve DT bindings documentation (Daniel) - Fix some commit fixup and rebase issues. Kind regards, Maxime Maxime Coquelin (9): ARM: Kconfig: Introduce MACH_STM32F429 flag Documentation: dt-bindings: Document STM32 pinctrl driver DT bindings includes: dt-bindings: Add STM32F429 pinctrl DT bindings pinctrl: Add STM32 MCUs support ARM: mach-stm32: Select pinctrl ARM: dts: Add pinctrl node to STM32F429 ARM: dts: Add USART1 pin config to STM32F429 boards ARM: dts: Add leds support to STM32F429 boards ARM: config: Enable GPIO Led driver in stm32_defconfig .../bindings/pinctrl/st,stm32-pinctrl.txt | 126 ++ arch/arm/Kconfig | 6 + arch/arm/boot/dts/stm32429i-eval.dts | 19 + arch/arm/boot/dts/stm32f429-disco.dts | 13 + arch/arm/boot/dts/stm32f429.dtsi | 110 ++ arch/arm/configs/stm32_defconfig | 1 + drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/stm32/Kconfig | 16 + drivers/pinctrl/stm32/Makefile | 5 + drivers/pinctrl/stm32/pinctrl-stm32.c | 834 ++++++++++ drivers/pinctrl/stm32/pinctrl-stm32.h | 43 + drivers/pinctrl/stm32/pinctrl-stm32f429.c | 1598 ++++++++++++++++++++ include/dt-bindings/pinctrl/pinctrl-stm32.h | 12 + include/dt-bindings/pinctrl/stm32f429-pinfunc.h | 1241 +++++++++++++++ 15 files changed, 4026 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt create mode 100644 drivers/pinctrl/stm32/Kconfig create mode 100644 drivers/pinctrl/stm32/Makefile create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32.c create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32.h create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32f429.c create mode 100644 include/dt-bindings/pinctrl/pinctrl-stm32.h create mode 100644 include/dt-bindings/pinctrl/stm32f429-pinfunc.h -- 1.9.1 ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v4 0/9] Add STM32 pinctrl/GPIO driver @ 2016-01-14 12:16 ` Maxime Coquelin 0 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-01-14 12:16 UTC (permalink / raw) To: linux-arm-kernel This is the fourth round of STM32 pinctrl series, which takes into account comments made by Patrice on patch 4. The STM32 family has 16 pins per GPIO bank, and the number of bank varies depending on the model. Pins can be multiplexed either in GPIO mode, alternate function (up to 15 functions per pin) or analog (for ADC/DAC). Changes since v3: ----------------- - Rebase on v4.4 - Fix error paths in stm32_pctrl_dt_subnode_to_map() (Patrice) - Remove useless stm32_pctrl_find_function_by_pin function (Patrice) Changes since v2: ----------------- - Rebase on v4.4-rc1 - Declare leds also for Eval board - Set green led as heartbeat - Collect some acks Changes since v1: ----------------- - Add GPIO LEDs support in DT and defconfig - Changes pinmux DT bindings from macros to raw values (Daniel) - Improve DT bindings documentation (Daniel) - Fix some commit fixup and rebase issues. Kind regards, Maxime Maxime Coquelin (9): ARM: Kconfig: Introduce MACH_STM32F429 flag Documentation: dt-bindings: Document STM32 pinctrl driver DT bindings includes: dt-bindings: Add STM32F429 pinctrl DT bindings pinctrl: Add STM32 MCUs support ARM: mach-stm32: Select pinctrl ARM: dts: Add pinctrl node to STM32F429 ARM: dts: Add USART1 pin config to STM32F429 boards ARM: dts: Add leds support to STM32F429 boards ARM: config: Enable GPIO Led driver in stm32_defconfig .../bindings/pinctrl/st,stm32-pinctrl.txt | 126 ++ arch/arm/Kconfig | 6 + arch/arm/boot/dts/stm32429i-eval.dts | 19 + arch/arm/boot/dts/stm32f429-disco.dts | 13 + arch/arm/boot/dts/stm32f429.dtsi | 110 ++ arch/arm/configs/stm32_defconfig | 1 + drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/stm32/Kconfig | 16 + drivers/pinctrl/stm32/Makefile | 5 + drivers/pinctrl/stm32/pinctrl-stm32.c | 834 ++++++++++ drivers/pinctrl/stm32/pinctrl-stm32.h | 43 + drivers/pinctrl/stm32/pinctrl-stm32f429.c | 1598 ++++++++++++++++++++ include/dt-bindings/pinctrl/pinctrl-stm32.h | 12 + include/dt-bindings/pinctrl/stm32f429-pinfunc.h | 1241 +++++++++++++++ 15 files changed, 4026 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt create mode 100644 drivers/pinctrl/stm32/Kconfig create mode 100644 drivers/pinctrl/stm32/Makefile create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32.c create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32.h create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32f429.c create mode 100644 include/dt-bindings/pinctrl/pinctrl-stm32.h create mode 100644 include/dt-bindings/pinctrl/stm32f429-pinfunc.h -- 1.9.1 ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v4 1/9] ARM: Kconfig: Introduce MACH_STM32F429 flag 2016-01-14 12:16 ` Maxime Coquelin @ 2016-01-14 12:16 ` Maxime Coquelin -1 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-01-14 12:16 UTC (permalink / raw) To: patrice.chotard, Linus Walleij, Mark Rutland, Rob Herring, linux-gpio, arnd Cc: linux-arm-kernel, linux-kernel, afaerber, devicetree, Daniel Thompson, bruherrera This patch introduces the MACH_STM32F429 to make possible to only select STM32F429 pinctrl driver. By default, all the MACH_STM32Fxxx flags will be set with STM32 defconfig. Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> --- arch/arm/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 34e1569..b7aa567 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -969,6 +969,11 @@ config ARCH_STM32 help Support for STMicroelectronics STM32 processors. +config MACH_STM32F429 + bool "STMicrolectronics STM32F429" + depends on ARCH_STM32 + default y + # Definitions to make life easier config ARCH_ACORN bool -- 1.9.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v4 1/9] ARM: Kconfig: Introduce MACH_STM32F429 flag @ 2016-01-14 12:16 ` Maxime Coquelin 0 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-01-14 12:16 UTC (permalink / raw) To: linux-arm-kernel This patch introduces the MACH_STM32F429 to make possible to only select STM32F429 pinctrl driver. By default, all the MACH_STM32Fxxx flags will be set with STM32 defconfig. Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> --- arch/arm/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 34e1569..b7aa567 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -969,6 +969,11 @@ config ARCH_STM32 help Support for STMicroelectronics STM32 processors. +config MACH_STM32F429 + bool "STMicrolectronics STM32F429" + depends on ARCH_STM32 + default y + # Definitions to make life easier config ARCH_ACORN bool -- 1.9.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v4 2/9] Documentation: dt-bindings: Document STM32 pinctrl driver DT bindings 2016-01-14 12:16 ` Maxime Coquelin @ 2016-01-14 12:16 ` Maxime Coquelin -1 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-01-14 12:16 UTC (permalink / raw) To: patrice.chotard, Linus Walleij, Mark Rutland, Rob Herring, linux-gpio, arnd Cc: linux-arm-kernel, linux-kernel, afaerber, devicetree, Daniel Thompson, bruherrera Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> --- .../bindings/pinctrl/st,stm32-pinctrl.txt | 126 +++++++++++++++++++++ 1 file changed, 126 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt new file mode 100644 index 0000000..7b4800c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt @@ -0,0 +1,126 @@ +* STM32 GPIO and Pin Mux/Config controller + +STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware +controller. It controls the input/output settings on the available pins and +also provides ability to multiplex and configure the output of various on-chip +controllers onto these pads. + +Pin controller node: +Required properies: + - compatible: value should be one of the following: + (a) "st,stm32f429-pinctrl" + - #address-cells: The value of this property must be 1 + - #size-cells : The value of this property must be 1 + - ranges : defines mapping between pin controller node (parent) to + gpio-bank node (children). + - pins-are-numbered: Specify the subnodes are using numbered pinmux to + specify pins. + +GPIO controller/bank node: +Required properties: + - gpio-controller : Indicates this device is a GPIO controller + - #gpio-cells : Should be two. + The first cell is the pin number + The second one is the polarity: + - 0 for active high + - 1 for active low + - reg : The gpio address range, relative to the pinctrl range + - clocks : clock that drives this bank + - st,bank-name : Should be a name string for this bank as specified in + the datasheet + +Optional properties: + - reset: : Reference to the reset controller + +Example: +#include <dt-bindings/pinctrl/stm32f429-pinfunc.h> +... + + pin-controller { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32f429-pinctrl"; + ranges = <0 0x40020000 0x3000>; + pins-are-numbered; + + gpioa: gpio@40020000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + resets = <&reset_ahb1 0>; + st,bank-name = "GPIOA"; + }; + ... + pin-functions nodes follow... + }; + +Contents of function subnode node: +---------------------------------- +Subnode format +A pinctrl node should contain at least one subnode representing the +pinctrl group available on the machine. Each subnode will list the +pins it needs, and how they should be configured, with regard to muxer +configuration, pullups, drive, output high/low and output speed. + + node { + pinmux = <PIN_NUMBER_PINMUX>; + GENERIC_PINCONFIG; + }; + +Required properties: +- pinmux: integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are defined in + dt-bindings/pinctrl/<soc>-pinfunc.h directly. + These defines are calculated as: + ((port * 16 + line) << 8) | function + With: + - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11) + - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15) + - function: The function number, can be: + * 0 : GPIO + * 1 : Alternate Function 0 + * 2 : Alternate Function 1 + * 3 : Alternate Function 2 + * ... + * 16 : Alternate Function 15 + * 17 : Analog + +Optional properties: +- GENERIC_PINCONFIG: is the generic pinconfig options to use. + Available options are: + - bias-disable, + - bias-pull-down, + - bias-pull-up, + - drive-push-pull, + - drive-open-drain, + - output-low + - output-high + - slew-rate = <x>, with x being: + < 0 > : Low speed + < 1 > : Medium speed + < 2 > : Fast speed + < 3 > : High speed + +Example: + +pin-controller { +... + usart1_pins_a: usart1@0 { + pins1 { + pinmux = <STM32F429_PA9_FUNC_USART1_TX>; + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32F429_PA10_FUNC_USART1_RX>; + bias-disable; + }; + }; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; -- 1.9.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v4 2/9] Documentation: dt-bindings: Document STM32 pinctrl driver DT bindings @ 2016-01-14 12:16 ` Maxime Coquelin 0 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-01-14 12:16 UTC (permalink / raw) To: linux-arm-kernel Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> --- .../bindings/pinctrl/st,stm32-pinctrl.txt | 126 +++++++++++++++++++++ 1 file changed, 126 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt new file mode 100644 index 0000000..7b4800c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt @@ -0,0 +1,126 @@ +* STM32 GPIO and Pin Mux/Config controller + +STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware +controller. It controls the input/output settings on the available pins and +also provides ability to multiplex and configure the output of various on-chip +controllers onto these pads. + +Pin controller node: +Required properies: + - compatible: value should be one of the following: + (a) "st,stm32f429-pinctrl" + - #address-cells: The value of this property must be 1 + - #size-cells : The value of this property must be 1 + - ranges : defines mapping between pin controller node (parent) to + gpio-bank node (children). + - pins-are-numbered: Specify the subnodes are using numbered pinmux to + specify pins. + +GPIO controller/bank node: +Required properties: + - gpio-controller : Indicates this device is a GPIO controller + - #gpio-cells : Should be two. + The first cell is the pin number + The second one is the polarity: + - 0 for active high + - 1 for active low + - reg : The gpio address range, relative to the pinctrl range + - clocks : clock that drives this bank + - st,bank-name : Should be a name string for this bank as specified in + the datasheet + +Optional properties: + - reset: : Reference to the reset controller + +Example: +#include <dt-bindings/pinctrl/stm32f429-pinfunc.h> +... + + pin-controller { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32f429-pinctrl"; + ranges = <0 0x40020000 0x3000>; + pins-are-numbered; + + gpioa: gpio at 40020000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + resets = <&reset_ahb1 0>; + st,bank-name = "GPIOA"; + }; + ... + pin-functions nodes follow... + }; + +Contents of function subnode node: +---------------------------------- +Subnode format +A pinctrl node should contain at least one subnode representing the +pinctrl group available on the machine. Each subnode will list the +pins it needs, and how they should be configured, with regard to muxer +configuration, pullups, drive, output high/low and output speed. + + node { + pinmux = <PIN_NUMBER_PINMUX>; + GENERIC_PINCONFIG; + }; + +Required properties: +- pinmux: integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are defined in + dt-bindings/pinctrl/<soc>-pinfunc.h directly. + These defines are calculated as: + ((port * 16 + line) << 8) | function + With: + - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11) + - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15) + - function: The function number, can be: + * 0 : GPIO + * 1 : Alternate Function 0 + * 2 : Alternate Function 1 + * 3 : Alternate Function 2 + * ... + * 16 : Alternate Function 15 + * 17 : Analog + +Optional properties: +- GENERIC_PINCONFIG: is the generic pinconfig options to use. + Available options are: + - bias-disable, + - bias-pull-down, + - bias-pull-up, + - drive-push-pull, + - drive-open-drain, + - output-low + - output-high + - slew-rate = <x>, with x being: + < 0 > : Low speed + < 1 > : Medium speed + < 2 > : Fast speed + < 3 > : High speed + +Example: + +pin-controller { +... + usart1_pins_a: usart1 at 0 { + pins1 { + pinmux = <STM32F429_PA9_FUNC_USART1_TX>; + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32F429_PA10_FUNC_USART1_RX>; + bias-disable; + }; + }; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; -- 1.9.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH v4 2/9] Documentation: dt-bindings: Document STM32 pinctrl driver DT bindings 2016-01-14 12:16 ` Maxime Coquelin @ 2016-01-15 2:59 ` Rob Herring -1 siblings, 0 replies; 47+ messages in thread From: Rob Herring @ 2016-01-15 2:59 UTC (permalink / raw) To: Maxime Coquelin Cc: patrice.chotard, Linus Walleij, Mark Rutland, linux-gpio, arnd, linux-arm-kernel, linux-kernel, afaerber, devicetree, Daniel Thompson, bruherrera On Thu, Jan 14, 2016 at 01:16:28PM +0100, Maxime Coquelin wrote: > Acked-by: Patrice Chotard <patrice.chotard@st.com> > Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> > --- > .../bindings/pinctrl/st,stm32-pinctrl.txt | 126 +++++++++++++++++++++ > 1 file changed, 126 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v4 2/9] Documentation: dt-bindings: Document STM32 pinctrl driver DT bindings @ 2016-01-15 2:59 ` Rob Herring 0 siblings, 0 replies; 47+ messages in thread From: Rob Herring @ 2016-01-15 2:59 UTC (permalink / raw) To: linux-arm-kernel On Thu, Jan 14, 2016 at 01:16:28PM +0100, Maxime Coquelin wrote: > Acked-by: Patrice Chotard <patrice.chotard@st.com> > Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> > --- > .../bindings/pinctrl/st,stm32-pinctrl.txt | 126 +++++++++++++++++++++ > 1 file changed, 126 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v4 2/9] Documentation: dt-bindings: Document STM32 pinctrl driver DT bindings 2016-01-14 12:16 ` Maxime Coquelin @ 2016-01-27 13:18 ` Linus Walleij -1 siblings, 0 replies; 47+ messages in thread From: Linus Walleij @ 2016-01-27 13:18 UTC (permalink / raw) To: Maxime Coquelin Cc: Patrice CHOTARD, Mark Rutland, Rob Herring, linux-gpio, Arnd Bergmann, linux-arm-kernel, linux-kernel, Andreas Färber, devicetree, Daniel Thompson, Bruno Herrera On Thu, Jan 14, 2016 at 1:16 PM, Maxime Coquelin <mcoquelin.stm32@gmail.com> wrote: > Acked-by: Patrice Chotard <patrice.chotard@st.com> > Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> This patch applied for linux v4.6 with Rob's ACK. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v4 2/9] Documentation: dt-bindings: Document STM32 pinctrl driver DT bindings @ 2016-01-27 13:18 ` Linus Walleij 0 siblings, 0 replies; 47+ messages in thread From: Linus Walleij @ 2016-01-27 13:18 UTC (permalink / raw) To: linux-arm-kernel On Thu, Jan 14, 2016 at 1:16 PM, Maxime Coquelin <mcoquelin.stm32@gmail.com> wrote: > Acked-by: Patrice Chotard <patrice.chotard@st.com> > Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> This patch applied for linux v4.6 with Rob's ACK. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v4 3/9] includes: dt-bindings: Add STM32F429 pinctrl DT bindings 2016-01-14 12:16 ` Maxime Coquelin @ 2016-01-14 12:16 ` Maxime Coquelin -1 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-01-14 12:16 UTC (permalink / raw) To: patrice.chotard, Linus Walleij, Mark Rutland, Rob Herring, linux-gpio, arnd Cc: linux-arm-kernel, linux-kernel, afaerber, devicetree, Daniel Thompson, bruherrera Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> --- include/dt-bindings/pinctrl/pinctrl-stm32.h | 12 + include/dt-bindings/pinctrl/stm32f429-pinfunc.h | 1241 +++++++++++++++++++++++ 2 files changed, 1253 insertions(+) create mode 100644 include/dt-bindings/pinctrl/pinctrl-stm32.h create mode 100644 include/dt-bindings/pinctrl/stm32f429-pinfunc.h diff --git a/include/dt-bindings/pinctrl/pinctrl-stm32.h b/include/dt-bindings/pinctrl/pinctrl-stm32.h new file mode 100644 index 0000000..a2e7222 --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-stm32.h @@ -0,0 +1,12 @@ +#ifndef _DT_BINDINGS_PINCTRL_STM32_H +#define _DT_BINDINGS_PINCTRL_STM32_H + +#define STM32_PIN_NO(x) ((x) << 8) +#define STM32_GET_PIN_NO(x) ((x) >> 8) +#define STM32_GET_PIN_FUNC(x) ((x) & 0xff) + +#define STM32_PIN_GPIO 0 +#define STM32_PIN_AF(x) ((x) + 1) +#define STM32_PIN_ANALOG (STM32_PIN_AF(15) + 1) + +#endif /* _DT_BINDINGS_PINCTRL_STM32_H */ diff --git a/include/dt-bindings/pinctrl/stm32f429-pinfunc.h b/include/dt-bindings/pinctrl/stm32f429-pinfunc.h new file mode 100644 index 0000000..9dd5fd0 --- /dev/null +++ b/include/dt-bindings/pinctrl/stm32f429-pinfunc.h @@ -0,0 +1,1241 @@ +#ifndef _DT_BINDINGS_STM32F429_PINFUNC_H +#define _DT_BINDINGS_STM32F429_PINFUNC_H + +#include <dt-bindings/pinctrl/pinctrl-stm32.h> + +#define STM32F429_PA0_FUNC_GPIO 0x0 +#define STM32F429_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2 +#define STM32F429_PA0_FUNC_TIM5_CH1 0x3 +#define STM32F429_PA0_FUNC_TIM8_ETR 0x4 +#define STM32F429_PA0_FUNC_USART2_CTS 0x8 +#define STM32F429_PA0_FUNC_UART4_TX 0x9 +#define STM32F429_PA0_FUNC_ETH_MII_CRS 0xc +#define STM32F429_PA0_FUNC_EVENTOUT 0x10 +#define STM32F429_PA0_FUNC_ANALOG 0x11 + +#define STM32F429_PA1_FUNC_GPIO 0x100 +#define STM32F429_PA1_FUNC_TIM2_CH2 0x102 +#define STM32F429_PA1_FUNC_TIM5_CH2 0x103 +#define STM32F429_PA1_FUNC_USART2_RTS 0x108 +#define STM32F429_PA1_FUNC_UART4_RX 0x109 +#define STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK 0x10c +#define STM32F429_PA1_FUNC_EVENTOUT 0x110 +#define STM32F429_PA1_FUNC_ANALOG 0x111 + +#define STM32F429_PA2_FUNC_GPIO 0x200 +#define STM32F429_PA2_FUNC_TIM2_CH3 0x202 +#define STM32F429_PA2_FUNC_TIM5_CH3 0x203 +#define STM32F429_PA2_FUNC_TIM9_CH1 0x204 +#define STM32F429_PA2_FUNC_USART2_TX 0x208 +#define STM32F429_PA2_FUNC_ETH_MDIO 0x20c +#define STM32F429_PA2_FUNC_EVENTOUT 0x210 +#define STM32F429_PA2_FUNC_ANALOG 0x211 + +#define STM32F429_PA3_FUNC_GPIO 0x300 +#define STM32F429_PA3_FUNC_TIM2_CH4 0x302 +#define STM32F429_PA3_FUNC_TIM5_CH4 0x303 +#define STM32F429_PA3_FUNC_TIM9_CH2 0x304 +#define STM32F429_PA3_FUNC_USART2_RX 0x308 +#define STM32F429_PA3_FUNC_OTG_HS_ULPI_D0 0x30b +#define STM32F429_PA3_FUNC_ETH_MII_COL 0x30c +#define STM32F429_PA3_FUNC_LCD_B5 0x30f +#define STM32F429_PA3_FUNC_EVENTOUT 0x310 +#define STM32F429_PA3_FUNC_ANALOG 0x311 + +#define STM32F429_PA4_FUNC_GPIO 0x400 +#define STM32F429_PA4_FUNC_SPI1_NSS 0x406 +#define STM32F429_PA4_FUNC_SPI3_NSS_I2S3_WS 0x407 +#define STM32F429_PA4_FUNC_USART2_CK 0x408 +#define STM32F429_PA4_FUNC_OTG_HS_SOF 0x40d +#define STM32F429_PA4_FUNC_DCMI_HSYNC 0x40e +#define STM32F429_PA4_FUNC_LCD_VSYNC 0x40f +#define STM32F429_PA4_FUNC_EVENTOUT 0x410 +#define STM32F429_PA4_FUNC_ANALOG 0x411 + +#define STM32F429_PA5_FUNC_GPIO 0x500 +#define STM32F429_PA5_FUNC_TIM2_CH1_TIM2_ETR 0x502 +#define STM32F429_PA5_FUNC_TIM8_CH1N 0x504 +#define STM32F429_PA5_FUNC_SPI1_SCK 0x506 +#define STM32F429_PA5_FUNC_OTG_HS_ULPI_CK 0x50b +#define STM32F429_PA5_FUNC_EVENTOUT 0x510 +#define STM32F429_PA5_FUNC_ANALOG 0x511 + +#define STM32F429_PA6_FUNC_GPIO 0x600 +#define STM32F429_PA6_FUNC_TIM1_BKIN 0x602 +#define STM32F429_PA6_FUNC_TIM3_CH1 0x603 +#define STM32F429_PA6_FUNC_TIM8_BKIN 0x604 +#define STM32F429_PA6_FUNC_SPI1_MISO 0x606 +#define STM32F429_PA6_FUNC_TIM13_CH1 0x60a +#define STM32F429_PA6_FUNC_DCMI_PIXCLK 0x60e +#define STM32F429_PA6_FUNC_LCD_G2 0x60f +#define STM32F429_PA6_FUNC_EVENTOUT 0x610 +#define STM32F429_PA6_FUNC_ANALOG 0x611 + +#define STM32F429_PA7_FUNC_GPIO 0x700 +#define STM32F429_PA7_FUNC_TIM1_CH1N 0x702 +#define STM32F429_PA7_FUNC_TIM3_CH2 0x703 +#define STM32F429_PA7_FUNC_TIM8_CH1N 0x704 +#define STM32F429_PA7_FUNC_SPI1_MOSI 0x706 +#define STM32F429_PA7_FUNC_TIM14_CH1 0x70a +#define STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV 0x70c +#define STM32F429_PA7_FUNC_EVENTOUT 0x710 +#define STM32F429_PA7_FUNC_ANALOG 0x711 + +#define STM32F429_PA8_FUNC_GPIO 0x800 +#define STM32F429_PA8_FUNC_MCO1 0x801 +#define STM32F429_PA8_FUNC_TIM1_CH1 0x802 +#define STM32F429_PA8_FUNC_I2C3_SCL 0x805 +#define STM32F429_PA8_FUNC_USART1_CK 0x808 +#define STM32F429_PA8_FUNC_OTG_FS_SOF 0x80b +#define STM32F429_PA8_FUNC_LCD_R6 0x80f +#define STM32F429_PA8_FUNC_EVENTOUT 0x810 +#define STM32F429_PA8_FUNC_ANALOG 0x811 + +#define STM32F429_PA9_FUNC_GPIO 0x900 +#define STM32F429_PA9_FUNC_TIM1_CH2 0x902 +#define STM32F429_PA9_FUNC_I2C3_SMBA 0x905 +#define STM32F429_PA9_FUNC_USART1_TX 0x908 +#define STM32F429_PA9_FUNC_DCMI_D0 0x90e +#define STM32F429_PA9_FUNC_EVENTOUT 0x910 +#define STM32F429_PA9_FUNC_ANALOG 0x911 + +#define STM32F429_PA10_FUNC_GPIO 0xa00 +#define STM32F429_PA10_FUNC_TIM1_CH3 0xa02 +#define STM32F429_PA10_FUNC_USART1_RX 0xa08 +#define STM32F429_PA10_FUNC_OTG_FS_ID 0xa0b +#define STM32F429_PA10_FUNC_DCMI_D1 0xa0e +#define STM32F429_PA10_FUNC_EVENTOUT 0xa10 +#define STM32F429_PA10_FUNC_ANALOG 0xa11 + +#define STM32F429_PA11_FUNC_GPIO 0xb00 +#define STM32F429_PA11_FUNC_TIM1_CH4 0xb02 +#define STM32F429_PA11_FUNC_USART1_CTS 0xb08 +#define STM32F429_PA11_FUNC_CAN1_RX 0xb0a +#define STM32F429_PA11_FUNC_OTG_FS_DM 0xb0b +#define STM32F429_PA11_FUNC_LCD_R4 0xb0f +#define STM32F429_PA11_FUNC_EVENTOUT 0xb10 +#define STM32F429_PA11_FUNC_ANALOG 0xb11 + +#define STM32F429_PA12_FUNC_GPIO 0xc00 +#define STM32F429_PA12_FUNC_TIM1_ETR 0xc02 +#define STM32F429_PA12_FUNC_USART1_RTS 0xc08 +#define STM32F429_PA12_FUNC_CAN1_TX 0xc0a +#define STM32F429_PA12_FUNC_OTG_FS_DP 0xc0b +#define STM32F429_PA12_FUNC_LCD_R5 0xc0f +#define STM32F429_PA12_FUNC_EVENTOUT 0xc10 +#define STM32F429_PA12_FUNC_ANALOG 0xc11 + +#define STM32F429_PA13_FUNC_GPIO 0xd00 +#define STM32F429_PA13_FUNC_JTMS_SWDIO 0xd01 +#define STM32F429_PA13_FUNC_EVENTOUT 0xd10 +#define STM32F429_PA13_FUNC_ANALOG 0xd11 + +#define STM32F429_PA14_FUNC_GPIO 0xe00 +#define STM32F429_PA14_FUNC_JTCK_SWCLK 0xe01 +#define STM32F429_PA14_FUNC_EVENTOUT 0xe10 +#define STM32F429_PA14_FUNC_ANALOG 0xe11 + +#define STM32F429_PA15_FUNC_GPIO 0xf00 +#define STM32F429_PA15_FUNC_JTDI 0xf01 +#define STM32F429_PA15_FUNC_TIM2_CH1_TIM2_ETR 0xf02 +#define STM32F429_PA15_FUNC_SPI1_NSS 0xf06 +#define STM32F429_PA15_FUNC_SPI3_NSS_I2S3_WS 0xf07 +#define STM32F429_PA15_FUNC_EVENTOUT 0xf10 +#define STM32F429_PA15_FUNC_ANALOG 0xf11 + + + +#define STM32F429_PB0_FUNC_GPIO 0x1000 +#define STM32F429_PB0_FUNC_TIM1_CH2N 0x1002 +#define STM32F429_PB0_FUNC_TIM3_CH3 0x1003 +#define STM32F429_PB0_FUNC_TIM8_CH2N 0x1004 +#define STM32F429_PB0_FUNC_LCD_R3 0x100a +#define STM32F429_PB0_FUNC_OTG_HS_ULPI_D1 0x100b +#define STM32F429_PB0_FUNC_ETH_MII_RXD2 0x100c +#define STM32F429_PB0_FUNC_EVENTOUT 0x1010 +#define STM32F429_PB0_FUNC_ANALOG 0x1011 + +#define STM32F429_PB1_FUNC_GPIO 0x1100 +#define STM32F429_PB1_FUNC_TIM1_CH3N 0x1102 +#define STM32F429_PB1_FUNC_TIM3_CH4 0x1103 +#define STM32F429_PB1_FUNC_TIM8_CH3N 0x1104 +#define STM32F429_PB1_FUNC_LCD_R6 0x110a +#define STM32F429_PB1_FUNC_OTG_HS_ULPI_D2 0x110b +#define STM32F429_PB1_FUNC_ETH_MII_RXD3 0x110c +#define STM32F429_PB1_FUNC_EVENTOUT 0x1110 +#define STM32F429_PB1_FUNC_ANALOG 0x1111 + +#define STM32F429_PB2_FUNC_GPIO 0x1200 +#define STM32F429_PB2_FUNC_EVENTOUT 0x1210 +#define STM32F429_PB2_FUNC_ANALOG 0x1211 + +#define STM32F429_PB3_FUNC_GPIO 0x1300 +#define STM32F429_PB3_FUNC_JTDO_TRACESWO 0x1301 +#define STM32F429_PB3_FUNC_TIM2_CH2 0x1302 +#define STM32F429_PB3_FUNC_SPI1_SCK 0x1306 +#define STM32F429_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307 +#define STM32F429_PB3_FUNC_EVENTOUT 0x1310 +#define STM32F429_PB3_FUNC_ANALOG 0x1311 + +#define STM32F429_PB4_FUNC_GPIO 0x1400 +#define STM32F429_PB4_FUNC_NJTRST 0x1401 +#define STM32F429_PB4_FUNC_TIM3_CH1 0x1403 +#define STM32F429_PB4_FUNC_SPI1_MISO 0x1406 +#define STM32F429_PB4_FUNC_SPI3_MISO 0x1407 +#define STM32F429_PB4_FUNC_I2S3EXT_SD 0x1408 +#define STM32F429_PB4_FUNC_EVENTOUT 0x1410 +#define STM32F429_PB4_FUNC_ANALOG 0x1411 + +#define STM32F429_PB5_FUNC_GPIO 0x1500 +#define STM32F429_PB5_FUNC_TIM3_CH2 0x1503 +#define STM32F429_PB5_FUNC_I2C1_SMBA 0x1505 +#define STM32F429_PB5_FUNC_SPI1_MOSI 0x1506 +#define STM32F429_PB5_FUNC_SPI3_MOSI_I2S3_SD 0x1507 +#define STM32F429_PB5_FUNC_CAN2_RX 0x150a +#define STM32F429_PB5_FUNC_OTG_HS_ULPI_D7 0x150b +#define STM32F429_PB5_FUNC_ETH_PPS_OUT 0x150c +#define STM32F429_PB5_FUNC_FMC_SDCKE1 0x150d +#define STM32F429_PB5_FUNC_DCMI_D10 0x150e +#define STM32F429_PB5_FUNC_EVENTOUT 0x1510 +#define STM32F429_PB5_FUNC_ANALOG 0x1511 + +#define STM32F429_PB6_FUNC_GPIO 0x1600 +#define STM32F429_PB6_FUNC_TIM4_CH1 0x1603 +#define STM32F429_PB6_FUNC_I2C1_SCL 0x1605 +#define STM32F429_PB6_FUNC_USART1_TX 0x1608 +#define STM32F429_PB6_FUNC_CAN2_TX 0x160a +#define STM32F429_PB6_FUNC_FMC_SDNE1 0x160d +#define STM32F429_PB6_FUNC_DCMI_D5 0x160e +#define STM32F429_PB6_FUNC_EVENTOUT 0x1610 +#define STM32F429_PB6_FUNC_ANALOG 0x1611 + +#define STM32F429_PB7_FUNC_GPIO 0x1700 +#define STM32F429_PB7_FUNC_TIM4_CH2 0x1703 +#define STM32F429_PB7_FUNC_I2C1_SDA 0x1705 +#define STM32F429_PB7_FUNC_USART1_RX 0x1708 +#define STM32F429_PB7_FUNC_FMC_NL 0x170d +#define STM32F429_PB7_FUNC_DCMI_VSYNC 0x170e +#define STM32F429_PB7_FUNC_EVENTOUT 0x1710 +#define STM32F429_PB7_FUNC_ANALOG 0x1711 + +#define STM32F429_PB8_FUNC_GPIO 0x1800 +#define STM32F429_PB8_FUNC_TIM4_CH3 0x1803 +#define STM32F429_PB8_FUNC_TIM10_CH1 0x1804 +#define STM32F429_PB8_FUNC_I2C1_SCL 0x1805 +#define STM32F429_PB8_FUNC_CAN1_RX 0x180a +#define STM32F429_PB8_FUNC_ETH_MII_TXD3 0x180c +#define STM32F429_PB8_FUNC_SDIO_D4 0x180d +#define STM32F429_PB8_FUNC_DCMI_D6 0x180e +#define STM32F429_PB8_FUNC_LCD_B6 0x180f +#define STM32F429_PB8_FUNC_EVENTOUT 0x1810 +#define STM32F429_PB8_FUNC_ANALOG 0x1811 + +#define STM32F429_PB9_FUNC_GPIO 0x1900 +#define STM32F429_PB9_FUNC_TIM4_CH4 0x1903 +#define STM32F429_PB9_FUNC_TIM11_CH1 0x1904 +#define STM32F429_PB9_FUNC_I2C1_SDA 0x1905 +#define STM32F429_PB9_FUNC_SPI2_NSS_I2S2_WS 0x1906 +#define STM32F429_PB9_FUNC_CAN1_TX 0x190a +#define STM32F429_PB9_FUNC_SDIO_D5 0x190d +#define STM32F429_PB9_FUNC_DCMI_D7 0x190e +#define STM32F429_PB9_FUNC_LCD_B7 0x190f +#define STM32F429_PB9_FUNC_EVENTOUT 0x1910 +#define STM32F429_PB9_FUNC_ANALOG 0x1911 + +#define STM32F429_PB10_FUNC_GPIO 0x1a00 +#define STM32F429_PB10_FUNC_TIM2_CH3 0x1a02 +#define STM32F429_PB10_FUNC_I2C2_SCL 0x1a05 +#define STM32F429_PB10_FUNC_SPI2_SCK_I2S2_CK 0x1a06 +#define STM32F429_PB10_FUNC_USART3_TX 0x1a08 +#define STM32F429_PB10_FUNC_OTG_HS_ULPI_D3 0x1a0b +#define STM32F429_PB10_FUNC_ETH_MII_RX_ER 0x1a0c +#define STM32F429_PB10_FUNC_LCD_G4 0x1a0f +#define STM32F429_PB10_FUNC_EVENTOUT 0x1a10 +#define STM32F429_PB10_FUNC_ANALOG 0x1a11 + +#define STM32F429_PB11_FUNC_GPIO 0x1b00 +#define STM32F429_PB11_FUNC_TIM2_CH4 0x1b02 +#define STM32F429_PB11_FUNC_I2C2_SDA 0x1b05 +#define STM32F429_PB11_FUNC_USART3_RX 0x1b08 +#define STM32F429_PB11_FUNC_OTG_HS_ULPI_D4 0x1b0b +#define STM32F429_PB11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x1b0c +#define STM32F429_PB11_FUNC_LCD_G5 0x1b0f +#define STM32F429_PB11_FUNC_EVENTOUT 0x1b10 +#define STM32F429_PB11_FUNC_ANALOG 0x1b11 + +#define STM32F429_PB12_FUNC_GPIO 0x1c00 +#define STM32F429_PB12_FUNC_TIM1_BKIN 0x1c02 +#define STM32F429_PB12_FUNC_I2C2_SMBA 0x1c05 +#define STM32F429_PB12_FUNC_SPI2_NSS_I2S2_WS 0x1c06 +#define STM32F429_PB12_FUNC_USART3_CK 0x1c08 +#define STM32F429_PB12_FUNC_CAN2_RX 0x1c0a +#define STM32F429_PB12_FUNC_OTG_HS_ULPI_D5 0x1c0b +#define STM32F429_PB12_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x1c0c +#define STM32F429_PB12_FUNC_OTG_HS_ID 0x1c0d +#define STM32F429_PB12_FUNC_EVENTOUT 0x1c10 +#define STM32F429_PB12_FUNC_ANALOG 0x1c11 + +#define STM32F429_PB13_FUNC_GPIO 0x1d00 +#define STM32F429_PB13_FUNC_TIM1_CH1N 0x1d02 +#define STM32F429_PB13_FUNC_SPI2_SCK_I2S2_CK 0x1d06 +#define STM32F429_PB13_FUNC_USART3_CTS 0x1d08 +#define STM32F429_PB13_FUNC_CAN2_TX 0x1d0a +#define STM32F429_PB13_FUNC_OTG_HS_ULPI_D6 0x1d0b +#define STM32F429_PB13_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x1d0c +#define STM32F429_PB13_FUNC_EVENTOUT 0x1d10 +#define STM32F429_PB13_FUNC_ANALOG 0x1d11 + +#define STM32F429_PB14_FUNC_GPIO 0x1e00 +#define STM32F429_PB14_FUNC_TIM1_CH2N 0x1e02 +#define STM32F429_PB14_FUNC_TIM8_CH2N 0x1e04 +#define STM32F429_PB14_FUNC_SPI2_MISO 0x1e06 +#define STM32F429_PB14_FUNC_I2S2EXT_SD 0x1e07 +#define STM32F429_PB14_FUNC_USART3_RTS 0x1e08 +#define STM32F429_PB14_FUNC_TIM12_CH1 0x1e0a +#define STM32F429_PB14_FUNC_OTG_HS_DM 0x1e0d +#define STM32F429_PB14_FUNC_EVENTOUT 0x1e10 +#define STM32F429_PB14_FUNC_ANALOG 0x1e11 + +#define STM32F429_PB15_FUNC_GPIO 0x1f00 +#define STM32F429_PB15_FUNC_RTC_REFIN 0x1f01 +#define STM32F429_PB15_FUNC_TIM1_CH3N 0x1f02 +#define STM32F429_PB15_FUNC_TIM8_CH3N 0x1f04 +#define STM32F429_PB15_FUNC_SPI2_MOSI_I2S2_SD 0x1f06 +#define STM32F429_PB15_FUNC_TIM12_CH2 0x1f0a +#define STM32F429_PB15_FUNC_OTG_HS_DP 0x1f0d +#define STM32F429_PB15_FUNC_EVENTOUT 0x1f10 +#define STM32F429_PB15_FUNC_ANALOG 0x1f11 + + + +#define STM32F429_PC0_FUNC_GPIO 0x2000 +#define STM32F429_PC0_FUNC_OTG_HS_ULPI_STP 0x200b +#define STM32F429_PC0_FUNC_FMC_SDNWE 0x200d +#define STM32F429_PC0_FUNC_EVENTOUT 0x2010 +#define STM32F429_PC0_FUNC_ANALOG 0x2011 + +#define STM32F429_PC1_FUNC_GPIO 0x2100 +#define STM32F429_PC1_FUNC_ETH_MDC 0x210c +#define STM32F429_PC1_FUNC_EVENTOUT 0x2110 +#define STM32F429_PC1_FUNC_ANALOG 0x2111 + +#define STM32F429_PC2_FUNC_GPIO 0x2200 +#define STM32F429_PC2_FUNC_SPI2_MISO 0x2206 +#define STM32F429_PC2_FUNC_I2S2EXT_SD 0x2207 +#define STM32F429_PC2_FUNC_OTG_HS_ULPI_DIR 0x220b +#define STM32F429_PC2_FUNC_ETH_MII_TXD2 0x220c +#define STM32F429_PC2_FUNC_FMC_SDNE0 0x220d +#define STM32F429_PC2_FUNC_EVENTOUT 0x2210 +#define STM32F429_PC2_FUNC_ANALOG 0x2211 + +#define STM32F429_PC3_FUNC_GPIO 0x2300 +#define STM32F429_PC3_FUNC_SPI2_MOSI_I2S2_SD 0x2306 +#define STM32F429_PC3_FUNC_OTG_HS_ULPI_NXT 0x230b +#define STM32F429_PC3_FUNC_ETH_MII_TX_CLK 0x230c +#define STM32F429_PC3_FUNC_FMC_SDCKE0 0x230d +#define STM32F429_PC3_FUNC_EVENTOUT 0x2310 +#define STM32F429_PC3_FUNC_ANALOG 0x2311 + +#define STM32F429_PC4_FUNC_GPIO 0x2400 +#define STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0 0x240c +#define STM32F429_PC4_FUNC_EVENTOUT 0x2410 +#define STM32F429_PC4_FUNC_ANALOG 0x2411 + +#define STM32F429_PC5_FUNC_GPIO 0x2500 +#define STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1 0x250c +#define STM32F429_PC5_FUNC_EVENTOUT 0x2510 +#define STM32F429_PC5_FUNC_ANALOG 0x2511 + +#define STM32F429_PC6_FUNC_GPIO 0x2600 +#define STM32F429_PC6_FUNC_TIM3_CH1 0x2603 +#define STM32F429_PC6_FUNC_TIM8_CH1 0x2604 +#define STM32F429_PC6_FUNC_I2S2_MCK 0x2606 +#define STM32F429_PC6_FUNC_USART6_TX 0x2609 +#define STM32F429_PC6_FUNC_SDIO_D6 0x260d +#define STM32F429_PC6_FUNC_DCMI_D0 0x260e +#define STM32F429_PC6_FUNC_LCD_HSYNC 0x260f +#define STM32F429_PC6_FUNC_EVENTOUT 0x2610 +#define STM32F429_PC6_FUNC_ANALOG 0x2611 + +#define STM32F429_PC7_FUNC_GPIO 0x2700 +#define STM32F429_PC7_FUNC_TIM3_CH2 0x2703 +#define STM32F429_PC7_FUNC_TIM8_CH2 0x2704 +#define STM32F429_PC7_FUNC_I2S3_MCK 0x2707 +#define STM32F429_PC7_FUNC_USART6_RX 0x2709 +#define STM32F429_PC7_FUNC_SDIO_D7 0x270d +#define STM32F429_PC7_FUNC_DCMI_D1 0x270e +#define STM32F429_PC7_FUNC_LCD_G6 0x270f +#define STM32F429_PC7_FUNC_EVENTOUT 0x2710 +#define STM32F429_PC7_FUNC_ANALOG 0x2711 + +#define STM32F429_PC8_FUNC_GPIO 0x2800 +#define STM32F429_PC8_FUNC_TIM3_CH3 0x2803 +#define STM32F429_PC8_FUNC_TIM8_CH3 0x2804 +#define STM32F429_PC8_FUNC_USART6_CK 0x2809 +#define STM32F429_PC8_FUNC_SDIO_D0 0x280d +#define STM32F429_PC8_FUNC_DCMI_D2 0x280e +#define STM32F429_PC8_FUNC_EVENTOUT 0x2810 +#define STM32F429_PC8_FUNC_ANALOG 0x2811 + +#define STM32F429_PC9_FUNC_GPIO 0x2900 +#define STM32F429_PC9_FUNC_MCO2 0x2901 +#define STM32F429_PC9_FUNC_TIM3_CH4 0x2903 +#define STM32F429_PC9_FUNC_TIM8_CH4 0x2904 +#define STM32F429_PC9_FUNC_I2C3_SDA 0x2905 +#define STM32F429_PC9_FUNC_I2S_CKIN 0x2906 +#define STM32F429_PC9_FUNC_SDIO_D1 0x290d +#define STM32F429_PC9_FUNC_DCMI_D3 0x290e +#define STM32F429_PC9_FUNC_EVENTOUT 0x2910 +#define STM32F429_PC9_FUNC_ANALOG 0x2911 + +#define STM32F429_PC10_FUNC_GPIO 0x2a00 +#define STM32F429_PC10_FUNC_SPI3_SCK_I2S3_CK 0x2a07 +#define STM32F429_PC10_FUNC_USART3_TX 0x2a08 +#define STM32F429_PC10_FUNC_UART4_TX 0x2a09 +#define STM32F429_PC10_FUNC_SDIO_D2 0x2a0d +#define STM32F429_PC10_FUNC_DCMI_D8 0x2a0e +#define STM32F429_PC10_FUNC_LCD_R2 0x2a0f +#define STM32F429_PC10_FUNC_EVENTOUT 0x2a10 +#define STM32F429_PC10_FUNC_ANALOG 0x2a11 + +#define STM32F429_PC11_FUNC_GPIO 0x2b00 +#define STM32F429_PC11_FUNC_I2S3EXT_SD 0x2b06 +#define STM32F429_PC11_FUNC_SPI3_MISO 0x2b07 +#define STM32F429_PC11_FUNC_USART3_RX 0x2b08 +#define STM32F429_PC11_FUNC_UART4_RX 0x2b09 +#define STM32F429_PC11_FUNC_SDIO_D3 0x2b0d +#define STM32F429_PC11_FUNC_DCMI_D4 0x2b0e +#define STM32F429_PC11_FUNC_EVENTOUT 0x2b10 +#define STM32F429_PC11_FUNC_ANALOG 0x2b11 + +#define STM32F429_PC12_FUNC_GPIO 0x2c00 +#define STM32F429_PC12_FUNC_SPI3_MOSI_I2S3_SD 0x2c07 +#define STM32F429_PC12_FUNC_USART3_CK 0x2c08 +#define STM32F429_PC12_FUNC_UART5_TX 0x2c09 +#define STM32F429_PC12_FUNC_SDIO_CK 0x2c0d +#define STM32F429_PC12_FUNC_DCMI_D9 0x2c0e +#define STM32F429_PC12_FUNC_EVENTOUT 0x2c10 +#define STM32F429_PC12_FUNC_ANALOG 0x2c11 + +#define STM32F429_PC13_FUNC_GPIO 0x2d00 +#define STM32F429_PC13_FUNC_EVENTOUT 0x2d10 +#define STM32F429_PC13_FUNC_ANALOG 0x2d11 + +#define STM32F429_PC14_FUNC_GPIO 0x2e00 +#define STM32F429_PC14_FUNC_EVENTOUT 0x2e10 +#define STM32F429_PC14_FUNC_ANALOG 0x2e11 + +#define STM32F429_PC15_FUNC_GPIO 0x2f00 +#define STM32F429_PC15_FUNC_EVENTOUT 0x2f10 +#define STM32F429_PC15_FUNC_ANALOG 0x2f11 + + + +#define STM32F429_PD0_FUNC_GPIO 0x3000 +#define STM32F429_PD0_FUNC_CAN1_RX 0x300a +#define STM32F429_PD0_FUNC_FMC_D2 0x300d +#define STM32F429_PD0_FUNC_EVENTOUT 0x3010 +#define STM32F429_PD0_FUNC_ANALOG 0x3011 + +#define STM32F429_PD1_FUNC_GPIO 0x3100 +#define STM32F429_PD1_FUNC_CAN1_TX 0x310a +#define STM32F429_PD1_FUNC_FMC_D3 0x310d +#define STM32F429_PD1_FUNC_EVENTOUT 0x3110 +#define STM32F429_PD1_FUNC_ANALOG 0x3111 + +#define STM32F429_PD2_FUNC_GPIO 0x3200 +#define STM32F429_PD2_FUNC_TIM3_ETR 0x3203 +#define STM32F429_PD2_FUNC_UART5_RX 0x3209 +#define STM32F429_PD2_FUNC_SDIO_CMD 0x320d +#define STM32F429_PD2_FUNC_DCMI_D11 0x320e +#define STM32F429_PD2_FUNC_EVENTOUT 0x3210 +#define STM32F429_PD2_FUNC_ANALOG 0x3211 + +#define STM32F429_PD3_FUNC_GPIO 0x3300 +#define STM32F429_PD3_FUNC_SPI2_SCK_I2S2_CK 0x3306 +#define STM32F429_PD3_FUNC_USART2_CTS 0x3308 +#define STM32F429_PD3_FUNC_FMC_CLK 0x330d +#define STM32F429_PD3_FUNC_DCMI_D5 0x330e +#define STM32F429_PD3_FUNC_LCD_G7 0x330f +#define STM32F429_PD3_FUNC_EVENTOUT 0x3310 +#define STM32F429_PD3_FUNC_ANALOG 0x3311 + +#define STM32F429_PD4_FUNC_GPIO 0x3400 +#define STM32F429_PD4_FUNC_USART2_RTS 0x3408 +#define STM32F429_PD4_FUNC_FMC_NOE 0x340d +#define STM32F429_PD4_FUNC_EVENTOUT 0x3410 +#define STM32F429_PD4_FUNC_ANALOG 0x3411 + +#define STM32F429_PD5_FUNC_GPIO 0x3500 +#define STM32F429_PD5_FUNC_USART2_TX 0x3508 +#define STM32F429_PD5_FUNC_FMC_NWE 0x350d +#define STM32F429_PD5_FUNC_EVENTOUT 0x3510 +#define STM32F429_PD5_FUNC_ANALOG 0x3511 + +#define STM32F429_PD6_FUNC_GPIO 0x3600 +#define STM32F429_PD6_FUNC_SPI3_MOSI_I2S3_SD 0x3606 +#define STM32F429_PD6_FUNC_SAI1_SD_A 0x3607 +#define STM32F429_PD6_FUNC_USART2_RX 0x3608 +#define STM32F429_PD6_FUNC_FMC_NWAIT 0x360d +#define STM32F429_PD6_FUNC_DCMI_D10 0x360e +#define STM32F429_PD6_FUNC_LCD_B2 0x360f +#define STM32F429_PD6_FUNC_EVENTOUT 0x3610 +#define STM32F429_PD6_FUNC_ANALOG 0x3611 + +#define STM32F429_PD7_FUNC_GPIO 0x3700 +#define STM32F429_PD7_FUNC_USART2_CK 0x3708 +#define STM32F429_PD7_FUNC_FMC_NE1_FMC_NCE2 0x370d +#define STM32F429_PD7_FUNC_EVENTOUT 0x3710 +#define STM32F429_PD7_FUNC_ANALOG 0x3711 + +#define STM32F429_PD8_FUNC_GPIO 0x3800 +#define STM32F429_PD8_FUNC_USART3_TX 0x3808 +#define STM32F429_PD8_FUNC_FMC_D13 0x380d +#define STM32F429_PD8_FUNC_EVENTOUT 0x3810 +#define STM32F429_PD8_FUNC_ANALOG 0x3811 + +#define STM32F429_PD9_FUNC_GPIO 0x3900 +#define STM32F429_PD9_FUNC_USART3_RX 0x3908 +#define STM32F429_PD9_FUNC_FMC_D14 0x390d +#define STM32F429_PD9_FUNC_EVENTOUT 0x3910 +#define STM32F429_PD9_FUNC_ANALOG 0x3911 + +#define STM32F429_PD10_FUNC_GPIO 0x3a00 +#define STM32F429_PD10_FUNC_USART3_CK 0x3a08 +#define STM32F429_PD10_FUNC_FMC_D15 0x3a0d +#define STM32F429_PD10_FUNC_LCD_B3 0x3a0f +#define STM32F429_PD10_FUNC_EVENTOUT 0x3a10 +#define STM32F429_PD10_FUNC_ANALOG 0x3a11 + +#define STM32F429_PD11_FUNC_GPIO 0x3b00 +#define STM32F429_PD11_FUNC_USART3_CTS 0x3b08 +#define STM32F429_PD11_FUNC_FMC_A16 0x3b0d +#define STM32F429_PD11_FUNC_EVENTOUT 0x3b10 +#define STM32F429_PD11_FUNC_ANALOG 0x3b11 + +#define STM32F429_PD12_FUNC_GPIO 0x3c00 +#define STM32F429_PD12_FUNC_TIM4_CH1 0x3c03 +#define STM32F429_PD12_FUNC_USART3_RTS 0x3c08 +#define STM32F429_PD12_FUNC_FMC_A17 0x3c0d +#define STM32F429_PD12_FUNC_EVENTOUT 0x3c10 +#define STM32F429_PD12_FUNC_ANALOG 0x3c11 + +#define STM32F429_PD13_FUNC_GPIO 0x3d00 +#define STM32F429_PD13_FUNC_TIM4_CH2 0x3d03 +#define STM32F429_PD13_FUNC_FMC_A18 0x3d0d +#define STM32F429_PD13_FUNC_EVENTOUT 0x3d10 +#define STM32F429_PD13_FUNC_ANALOG 0x3d11 + +#define STM32F429_PD14_FUNC_GPIO 0x3e00 +#define STM32F429_PD14_FUNC_TIM4_CH3 0x3e03 +#define STM32F429_PD14_FUNC_FMC_D0 0x3e0d +#define STM32F429_PD14_FUNC_EVENTOUT 0x3e10 +#define STM32F429_PD14_FUNC_ANALOG 0x3e11 + +#define STM32F429_PD15_FUNC_GPIO 0x3f00 +#define STM32F429_PD15_FUNC_TIM4_CH4 0x3f03 +#define STM32F429_PD15_FUNC_FMC_D1 0x3f0d +#define STM32F429_PD15_FUNC_EVENTOUT 0x3f10 +#define STM32F429_PD15_FUNC_ANALOG 0x3f11 + + + +#define STM32F429_PE0_FUNC_GPIO 0x4000 +#define STM32F429_PE0_FUNC_TIM4_ETR 0x4003 +#define STM32F429_PE0_FUNC_UART8_RX 0x4009 +#define STM32F429_PE0_FUNC_FMC_NBL0 0x400d +#define STM32F429_PE0_FUNC_DCMI_D2 0x400e +#define STM32F429_PE0_FUNC_EVENTOUT 0x4010 +#define STM32F429_PE0_FUNC_ANALOG 0x4011 + +#define STM32F429_PE1_FUNC_GPIO 0x4100 +#define STM32F429_PE1_FUNC_UART8_TX 0x4109 +#define STM32F429_PE1_FUNC_FMC_NBL1 0x410d +#define STM32F429_PE1_FUNC_DCMI_D3 0x410e +#define STM32F429_PE1_FUNC_EVENTOUT 0x4110 +#define STM32F429_PE1_FUNC_ANALOG 0x4111 + +#define STM32F429_PE2_FUNC_GPIO 0x4200 +#define STM32F429_PE2_FUNC_TRACECLK 0x4201 +#define STM32F429_PE2_FUNC_SPI4_SCK 0x4206 +#define STM32F429_PE2_FUNC_SAI1_MCLK_A 0x4207 +#define STM32F429_PE2_FUNC_ETH_MII_TXD3 0x420c +#define STM32F429_PE2_FUNC_FMC_A23 0x420d +#define STM32F429_PE2_FUNC_EVENTOUT 0x4210 +#define STM32F429_PE2_FUNC_ANALOG 0x4211 + +#define STM32F429_PE3_FUNC_GPIO 0x4300 +#define STM32F429_PE3_FUNC_TRACED0 0x4301 +#define STM32F429_PE3_FUNC_SAI1_SD_B 0x4307 +#define STM32F429_PE3_FUNC_FMC_A19 0x430d +#define STM32F429_PE3_FUNC_EVENTOUT 0x4310 +#define STM32F429_PE3_FUNC_ANALOG 0x4311 + +#define STM32F429_PE4_FUNC_GPIO 0x4400 +#define STM32F429_PE4_FUNC_TRACED1 0x4401 +#define STM32F429_PE4_FUNC_SPI4_NSS 0x4406 +#define STM32F429_PE4_FUNC_SAI1_FS_A 0x4407 +#define STM32F429_PE4_FUNC_FMC_A20 0x440d +#define STM32F429_PE4_FUNC_DCMI_D4 0x440e +#define STM32F429_PE4_FUNC_LCD_B0 0x440f +#define STM32F429_PE4_FUNC_EVENTOUT 0x4410 +#define STM32F429_PE4_FUNC_ANALOG 0x4411 + +#define STM32F429_PE5_FUNC_GPIO 0x4500 +#define STM32F429_PE5_FUNC_TRACED2 0x4501 +#define STM32F429_PE5_FUNC_TIM9_CH1 0x4504 +#define STM32F429_PE5_FUNC_SPI4_MISO 0x4506 +#define STM32F429_PE5_FUNC_SAI1_SCK_A 0x4507 +#define STM32F429_PE5_FUNC_FMC_A21 0x450d +#define STM32F429_PE5_FUNC_DCMI_D6 0x450e +#define STM32F429_PE5_FUNC_LCD_G0 0x450f +#define STM32F429_PE5_FUNC_EVENTOUT 0x4510 +#define STM32F429_PE5_FUNC_ANALOG 0x4511 + +#define STM32F429_PE6_FUNC_GPIO 0x4600 +#define STM32F429_PE6_FUNC_TRACED3 0x4601 +#define STM32F429_PE6_FUNC_TIM9_CH2 0x4604 +#define STM32F429_PE6_FUNC_SPI4_MOSI 0x4606 +#define STM32F429_PE6_FUNC_SAI1_SD_A 0x4607 +#define STM32F429_PE6_FUNC_FMC_A22 0x460d +#define STM32F429_PE6_FUNC_DCMI_D7 0x460e +#define STM32F429_PE6_FUNC_LCD_G1 0x460f +#define STM32F429_PE6_FUNC_EVENTOUT 0x4610 +#define STM32F429_PE6_FUNC_ANALOG 0x4611 + +#define STM32F429_PE7_FUNC_GPIO 0x4700 +#define STM32F429_PE7_FUNC_TIM1_ETR 0x4702 +#define STM32F429_PE7_FUNC_UART7_RX 0x4709 +#define STM32F429_PE7_FUNC_FMC_D4 0x470d +#define STM32F429_PE7_FUNC_EVENTOUT 0x4710 +#define STM32F429_PE7_FUNC_ANALOG 0x4711 + +#define STM32F429_PE8_FUNC_GPIO 0x4800 +#define STM32F429_PE8_FUNC_TIM1_CH1N 0x4802 +#define STM32F429_PE8_FUNC_UART7_TX 0x4809 +#define STM32F429_PE8_FUNC_FMC_D5 0x480d +#define STM32F429_PE8_FUNC_EVENTOUT 0x4810 +#define STM32F429_PE8_FUNC_ANALOG 0x4811 + +#define STM32F429_PE9_FUNC_GPIO 0x4900 +#define STM32F429_PE9_FUNC_TIM1_CH1 0x4902 +#define STM32F429_PE9_FUNC_FMC_D6 0x490d +#define STM32F429_PE9_FUNC_EVENTOUT 0x4910 +#define STM32F429_PE9_FUNC_ANALOG 0x4911 + +#define STM32F429_PE10_FUNC_GPIO 0x4a00 +#define STM32F429_PE10_FUNC_TIM1_CH2N 0x4a02 +#define STM32F429_PE10_FUNC_FMC_D7 0x4a0d +#define STM32F429_PE10_FUNC_EVENTOUT 0x4a10 +#define STM32F429_PE10_FUNC_ANALOG 0x4a11 + +#define STM32F429_PE11_FUNC_GPIO 0x4b00 +#define STM32F429_PE11_FUNC_TIM1_CH2 0x4b02 +#define STM32F429_PE11_FUNC_SPI4_NSS 0x4b06 +#define STM32F429_PE11_FUNC_FMC_D8 0x4b0d +#define STM32F429_PE11_FUNC_LCD_G3 0x4b0f +#define STM32F429_PE11_FUNC_EVENTOUT 0x4b10 +#define STM32F429_PE11_FUNC_ANALOG 0x4b11 + +#define STM32F429_PE12_FUNC_GPIO 0x4c00 +#define STM32F429_PE12_FUNC_TIM1_CH3N 0x4c02 +#define STM32F429_PE12_FUNC_SPI4_SCK 0x4c06 +#define STM32F429_PE12_FUNC_FMC_D9 0x4c0d +#define STM32F429_PE12_FUNC_LCD_B4 0x4c0f +#define STM32F429_PE12_FUNC_EVENTOUT 0x4c10 +#define STM32F429_PE12_FUNC_ANALOG 0x4c11 + +#define STM32F429_PE13_FUNC_GPIO 0x4d00 +#define STM32F429_PE13_FUNC_TIM1_CH3 0x4d02 +#define STM32F429_PE13_FUNC_SPI4_MISO 0x4d06 +#define STM32F429_PE13_FUNC_FMC_D10 0x4d0d +#define STM32F429_PE13_FUNC_LCD_DE 0x4d0f +#define STM32F429_PE13_FUNC_EVENTOUT 0x4d10 +#define STM32F429_PE13_FUNC_ANALOG 0x4d11 + +#define STM32F429_PE14_FUNC_GPIO 0x4e00 +#define STM32F429_PE14_FUNC_TIM1_CH4 0x4e02 +#define STM32F429_PE14_FUNC_SPI4_MOSI 0x4e06 +#define STM32F429_PE14_FUNC_FMC_D11 0x4e0d +#define STM32F429_PE14_FUNC_LCD_CLK 0x4e0f +#define STM32F429_PE14_FUNC_EVENTOUT 0x4e10 +#define STM32F429_PE14_FUNC_ANALOG 0x4e11 + +#define STM32F429_PE15_FUNC_GPIO 0x4f00 +#define STM32F429_PE15_FUNC_TIM1_BKIN 0x4f02 +#define STM32F429_PE15_FUNC_FMC_D12 0x4f0d +#define STM32F429_PE15_FUNC_LCD_R7 0x4f0f +#define STM32F429_PE15_FUNC_EVENTOUT 0x4f10 +#define STM32F429_PE15_FUNC_ANALOG 0x4f11 + + + +#define STM32F429_PF0_FUNC_GPIO 0x5000 +#define STM32F429_PF0_FUNC_I2C2_SDA 0x5005 +#define STM32F429_PF0_FUNC_FMC_A0 0x500d +#define STM32F429_PF0_FUNC_EVENTOUT 0x5010 +#define STM32F429_PF0_FUNC_ANALOG 0x5011 + +#define STM32F429_PF1_FUNC_GPIO 0x5100 +#define STM32F429_PF1_FUNC_I2C2_SCL 0x5105 +#define STM32F429_PF1_FUNC_FMC_A1 0x510d +#define STM32F429_PF1_FUNC_EVENTOUT 0x5110 +#define STM32F429_PF1_FUNC_ANALOG 0x5111 + +#define STM32F429_PF2_FUNC_GPIO 0x5200 +#define STM32F429_PF2_FUNC_I2C2_SMBA 0x5205 +#define STM32F429_PF2_FUNC_FMC_A2 0x520d +#define STM32F429_PF2_FUNC_EVENTOUT 0x5210 +#define STM32F429_PF2_FUNC_ANALOG 0x5211 + +#define STM32F429_PF3_FUNC_GPIO 0x5300 +#define STM32F429_PF3_FUNC_FMC_A3 0x530d +#define STM32F429_PF3_FUNC_EVENTOUT 0x5310 +#define STM32F429_PF3_FUNC_ANALOG 0x5311 + +#define STM32F429_PF4_FUNC_GPIO 0x5400 +#define STM32F429_PF4_FUNC_FMC_A4 0x540d +#define STM32F429_PF4_FUNC_EVENTOUT 0x5410 +#define STM32F429_PF4_FUNC_ANALOG 0x5411 + +#define STM32F429_PF5_FUNC_GPIO 0x5500 +#define STM32F429_PF5_FUNC_FMC_A5 0x550d +#define STM32F429_PF5_FUNC_EVENTOUT 0x5510 +#define STM32F429_PF5_FUNC_ANALOG 0x5511 + +#define STM32F429_PF6_FUNC_GPIO 0x5600 +#define STM32F429_PF6_FUNC_TIM10_CH1 0x5604 +#define STM32F429_PF6_FUNC_SPI5_NSS 0x5606 +#define STM32F429_PF6_FUNC_SAI1_SD_B 0x5607 +#define STM32F429_PF6_FUNC_UART7_RX 0x5609 +#define STM32F429_PF6_FUNC_FMC_NIORD 0x560d +#define STM32F429_PF6_FUNC_EVENTOUT 0x5610 +#define STM32F429_PF6_FUNC_ANALOG 0x5611 + +#define STM32F429_PF7_FUNC_GPIO 0x5700 +#define STM32F429_PF7_FUNC_TIM11_CH1 0x5704 +#define STM32F429_PF7_FUNC_SPI5_SCK 0x5706 +#define STM32F429_PF7_FUNC_SAI1_MCLK_B 0x5707 +#define STM32F429_PF7_FUNC_UART7_TX 0x5709 +#define STM32F429_PF7_FUNC_FMC_NREG 0x570d +#define STM32F429_PF7_FUNC_EVENTOUT 0x5710 +#define STM32F429_PF7_FUNC_ANALOG 0x5711 + +#define STM32F429_PF8_FUNC_GPIO 0x5800 +#define STM32F429_PF8_FUNC_SPI5_MISO 0x5806 +#define STM32F429_PF8_FUNC_SAI1_SCK_B 0x5807 +#define STM32F429_PF8_FUNC_TIM13_CH1 0x580a +#define STM32F429_PF8_FUNC_FMC_NIOWR 0x580d +#define STM32F429_PF8_FUNC_EVENTOUT 0x5810 +#define STM32F429_PF8_FUNC_ANALOG 0x5811 + +#define STM32F429_PF9_FUNC_GPIO 0x5900 +#define STM32F429_PF9_FUNC_SPI5_MOSI 0x5906 +#define STM32F429_PF9_FUNC_SAI1_FS_B 0x5907 +#define STM32F429_PF9_FUNC_TIM14_CH1 0x590a +#define STM32F429_PF9_FUNC_FMC_CD 0x590d +#define STM32F429_PF9_FUNC_EVENTOUT 0x5910 +#define STM32F429_PF9_FUNC_ANALOG 0x5911 + +#define STM32F429_PF10_FUNC_GPIO 0x5a00 +#define STM32F429_PF10_FUNC_FMC_INTR 0x5a0d +#define STM32F429_PF10_FUNC_DCMI_D11 0x5a0e +#define STM32F429_PF10_FUNC_LCD_DE 0x5a0f +#define STM32F429_PF10_FUNC_EVENTOUT 0x5a10 +#define STM32F429_PF10_FUNC_ANALOG 0x5a11 + +#define STM32F429_PF11_FUNC_GPIO 0x5b00 +#define STM32F429_PF11_FUNC_SPI5_MOSI 0x5b06 +#define STM32F429_PF11_FUNC_FMC_SDNRAS 0x5b0d +#define STM32F429_PF11_FUNC_DCMI_D12 0x5b0e +#define STM32F429_PF11_FUNC_EVENTOUT 0x5b10 +#define STM32F429_PF11_FUNC_ANALOG 0x5b11 + +#define STM32F429_PF12_FUNC_GPIO 0x5c00 +#define STM32F429_PF12_FUNC_FMC_A6 0x5c0d +#define STM32F429_PF12_FUNC_EVENTOUT 0x5c10 +#define STM32F429_PF12_FUNC_ANALOG 0x5c11 + +#define STM32F429_PF13_FUNC_GPIO 0x5d00 +#define STM32F429_PF13_FUNC_FMC_A7 0x5d0d +#define STM32F429_PF13_FUNC_EVENTOUT 0x5d10 +#define STM32F429_PF13_FUNC_ANALOG 0x5d11 + +#define STM32F429_PF14_FUNC_GPIO 0x5e00 +#define STM32F429_PF14_FUNC_FMC_A8 0x5e0d +#define STM32F429_PF14_FUNC_EVENTOUT 0x5e10 +#define STM32F429_PF14_FUNC_ANALOG 0x5e11 + +#define STM32F429_PF15_FUNC_GPIO 0x5f00 +#define STM32F429_PF15_FUNC_FMC_A9 0x5f0d +#define STM32F429_PF15_FUNC_EVENTOUT 0x5f10 +#define STM32F429_PF15_FUNC_ANALOG 0x5f11 + + + +#define STM32F429_PG0_FUNC_GPIO 0x6000 +#define STM32F429_PG0_FUNC_FMC_A10 0x600d +#define STM32F429_PG0_FUNC_EVENTOUT 0x6010 +#define STM32F429_PG0_FUNC_ANALOG 0x6011 + +#define STM32F429_PG1_FUNC_GPIO 0x6100 +#define STM32F429_PG1_FUNC_FMC_A11 0x610d +#define STM32F429_PG1_FUNC_EVENTOUT 0x6110 +#define STM32F429_PG1_FUNC_ANALOG 0x6111 + +#define STM32F429_PG2_FUNC_GPIO 0x6200 +#define STM32F429_PG2_FUNC_FMC_A12 0x620d +#define STM32F429_PG2_FUNC_EVENTOUT 0x6210 +#define STM32F429_PG2_FUNC_ANALOG 0x6211 + +#define STM32F429_PG3_FUNC_GPIO 0x6300 +#define STM32F429_PG3_FUNC_FMC_A13 0x630d +#define STM32F429_PG3_FUNC_EVENTOUT 0x6310 +#define STM32F429_PG3_FUNC_ANALOG 0x6311 + +#define STM32F429_PG4_FUNC_GPIO 0x6400 +#define STM32F429_PG4_FUNC_FMC_A14_FMC_BA0 0x640d +#define STM32F429_PG4_FUNC_EVENTOUT 0x6410 +#define STM32F429_PG4_FUNC_ANALOG 0x6411 + +#define STM32F429_PG5_FUNC_GPIO 0x6500 +#define STM32F429_PG5_FUNC_FMC_A15_FMC_BA1 0x650d +#define STM32F429_PG5_FUNC_EVENTOUT 0x6510 +#define STM32F429_PG5_FUNC_ANALOG 0x6511 + +#define STM32F429_PG6_FUNC_GPIO 0x6600 +#define STM32F429_PG6_FUNC_FMC_INT2 0x660d +#define STM32F429_PG6_FUNC_DCMI_D12 0x660e +#define STM32F429_PG6_FUNC_LCD_R7 0x660f +#define STM32F429_PG6_FUNC_EVENTOUT 0x6610 +#define STM32F429_PG6_FUNC_ANALOG 0x6611 + +#define STM32F429_PG7_FUNC_GPIO 0x6700 +#define STM32F429_PG7_FUNC_USART6_CK 0x6709 +#define STM32F429_PG7_FUNC_FMC_INT3 0x670d +#define STM32F429_PG7_FUNC_DCMI_D13 0x670e +#define STM32F429_PG7_FUNC_LCD_CLK 0x670f +#define STM32F429_PG7_FUNC_EVENTOUT 0x6710 +#define STM32F429_PG7_FUNC_ANALOG 0x6711 + +#define STM32F429_PG8_FUNC_GPIO 0x6800 +#define STM32F429_PG8_FUNC_SPI6_NSS 0x6806 +#define STM32F429_PG8_FUNC_USART6_RTS 0x6809 +#define STM32F429_PG8_FUNC_ETH_PPS_OUT 0x680c +#define STM32F429_PG8_FUNC_FMC_SDCLK 0x680d +#define STM32F429_PG8_FUNC_EVENTOUT 0x6810 +#define STM32F429_PG8_FUNC_ANALOG 0x6811 + +#define STM32F429_PG9_FUNC_GPIO 0x6900 +#define STM32F429_PG9_FUNC_USART6_RX 0x6909 +#define STM32F429_PG9_FUNC_FMC_NE2_FMC_NCE3 0x690d +#define STM32F429_PG9_FUNC_DCMI_VSYNC 0x690e +#define STM32F429_PG9_FUNC_EVENTOUT 0x6910 +#define STM32F429_PG9_FUNC_ANALOG 0x6911 + +#define STM32F429_PG10_FUNC_GPIO 0x6a00 +#define STM32F429_PG10_FUNC_LCD_G3 0x6a0a +#define STM32F429_PG10_FUNC_FMC_NCE4_1_FMC_NE3 0x6a0d +#define STM32F429_PG10_FUNC_DCMI_D2 0x6a0e +#define STM32F429_PG10_FUNC_LCD_B2 0x6a0f +#define STM32F429_PG10_FUNC_EVENTOUT 0x6a10 +#define STM32F429_PG10_FUNC_ANALOG 0x6a11 + +#define STM32F429_PG11_FUNC_GPIO 0x6b00 +#define STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x6b0c +#define STM32F429_PG11_FUNC_FMC_NCE4_2 0x6b0d +#define STM32F429_PG11_FUNC_DCMI_D3 0x6b0e +#define STM32F429_PG11_FUNC_LCD_B3 0x6b0f +#define STM32F429_PG11_FUNC_EVENTOUT 0x6b10 +#define STM32F429_PG11_FUNC_ANALOG 0x6b11 + +#define STM32F429_PG12_FUNC_GPIO 0x6c00 +#define STM32F429_PG12_FUNC_SPI6_MISO 0x6c06 +#define STM32F429_PG12_FUNC_USART6_RTS 0x6c09 +#define STM32F429_PG12_FUNC_LCD_B4 0x6c0a +#define STM32F429_PG12_FUNC_FMC_NE4 0x6c0d +#define STM32F429_PG12_FUNC_LCD_B1 0x6c0f +#define STM32F429_PG12_FUNC_EVENTOUT 0x6c10 +#define STM32F429_PG12_FUNC_ANALOG 0x6c11 + +#define STM32F429_PG13_FUNC_GPIO 0x6d00 +#define STM32F429_PG13_FUNC_SPI6_SCK 0x6d06 +#define STM32F429_PG13_FUNC_USART6_CTS 0x6d09 +#define STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x6d0c +#define STM32F429_PG13_FUNC_FMC_A24 0x6d0d +#define STM32F429_PG13_FUNC_EVENTOUT 0x6d10 +#define STM32F429_PG13_FUNC_ANALOG 0x6d11 + +#define STM32F429_PG14_FUNC_GPIO 0x6e00 +#define STM32F429_PG14_FUNC_SPI6_MOSI 0x6e06 +#define STM32F429_PG14_FUNC_USART6_TX 0x6e09 +#define STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x6e0c +#define STM32F429_PG14_FUNC_FMC_A25 0x6e0d +#define STM32F429_PG14_FUNC_EVENTOUT 0x6e10 +#define STM32F429_PG14_FUNC_ANALOG 0x6e11 + +#define STM32F429_PG15_FUNC_GPIO 0x6f00 +#define STM32F429_PG15_FUNC_USART6_CTS 0x6f09 +#define STM32F429_PG15_FUNC_FMC_SDNCAS 0x6f0d +#define STM32F429_PG15_FUNC_DCMI_D13 0x6f0e +#define STM32F429_PG15_FUNC_EVENTOUT 0x6f10 +#define STM32F429_PG15_FUNC_ANALOG 0x6f11 + + + +#define STM32F429_PH0_FUNC_GPIO 0x7000 +#define STM32F429_PH0_FUNC_EVENTOUT 0x7010 +#define STM32F429_PH0_FUNC_ANALOG 0x7011 + +#define STM32F429_PH1_FUNC_GPIO 0x7100 +#define STM32F429_PH1_FUNC_EVENTOUT 0x7110 +#define STM32F429_PH1_FUNC_ANALOG 0x7111 + +#define STM32F429_PH2_FUNC_GPIO 0x7200 +#define STM32F429_PH2_FUNC_ETH_MII_CRS 0x720c +#define STM32F429_PH2_FUNC_FMC_SDCKE0 0x720d +#define STM32F429_PH2_FUNC_LCD_R0 0x720f +#define STM32F429_PH2_FUNC_EVENTOUT 0x7210 +#define STM32F429_PH2_FUNC_ANALOG 0x7211 + +#define STM32F429_PH3_FUNC_GPIO 0x7300 +#define STM32F429_PH3_FUNC_ETH_MII_COL 0x730c +#define STM32F429_PH3_FUNC_FMC_SDNE0 0x730d +#define STM32F429_PH3_FUNC_LCD_R1 0x730f +#define STM32F429_PH3_FUNC_EVENTOUT 0x7310 +#define STM32F429_PH3_FUNC_ANALOG 0x7311 + +#define STM32F429_PH4_FUNC_GPIO 0x7400 +#define STM32F429_PH4_FUNC_I2C2_SCL 0x7405 +#define STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT 0x740b +#define STM32F429_PH4_FUNC_EVENTOUT 0x7410 +#define STM32F429_PH4_FUNC_ANALOG 0x7411 + +#define STM32F429_PH5_FUNC_GPIO 0x7500 +#define STM32F429_PH5_FUNC_I2C2_SDA 0x7505 +#define STM32F429_PH5_FUNC_SPI5_NSS 0x7506 +#define STM32F429_PH5_FUNC_FMC_SDNWE 0x750d +#define STM32F429_PH5_FUNC_EVENTOUT 0x7510 +#define STM32F429_PH5_FUNC_ANALOG 0x7511 + +#define STM32F429_PH6_FUNC_GPIO 0x7600 +#define STM32F429_PH6_FUNC_I2C2_SMBA 0x7605 +#define STM32F429_PH6_FUNC_SPI5_SCK 0x7606 +#define STM32F429_PH6_FUNC_TIM12_CH1 0x760a +#define STM32F429_PH6_FUNC_ETH_MII_RXD2 0x760c +#define STM32F429_PH6_FUNC_FMC_SDNE1 0x760d +#define STM32F429_PH6_FUNC_DCMI_D8 0x760e +#define STM32F429_PH6_FUNC_EVENTOUT 0x7610 +#define STM32F429_PH6_FUNC_ANALOG 0x7611 + +#define STM32F429_PH7_FUNC_GPIO 0x7700 +#define STM32F429_PH7_FUNC_I2C3_SCL 0x7705 +#define STM32F429_PH7_FUNC_SPI5_MISO 0x7706 +#define STM32F429_PH7_FUNC_ETH_MII_RXD3 0x770c +#define STM32F429_PH7_FUNC_FMC_SDCKE1 0x770d +#define STM32F429_PH7_FUNC_DCMI_D9 0x770e +#define STM32F429_PH7_FUNC_EVENTOUT 0x7710 +#define STM32F429_PH7_FUNC_ANALOG 0x7711 + +#define STM32F429_PH8_FUNC_GPIO 0x7800 +#define STM32F429_PH8_FUNC_I2C3_SDA 0x7805 +#define STM32F429_PH8_FUNC_FMC_D16 0x780d +#define STM32F429_PH8_FUNC_DCMI_HSYNC 0x780e +#define STM32F429_PH8_FUNC_LCD_R2 0x780f +#define STM32F429_PH8_FUNC_EVENTOUT 0x7810 +#define STM32F429_PH8_FUNC_ANALOG 0x7811 + +#define STM32F429_PH9_FUNC_GPIO 0x7900 +#define STM32F429_PH9_FUNC_I2C3_SMBA 0x7905 +#define STM32F429_PH9_FUNC_TIM12_CH2 0x790a +#define STM32F429_PH9_FUNC_FMC_D17 0x790d +#define STM32F429_PH9_FUNC_DCMI_D0 0x790e +#define STM32F429_PH9_FUNC_LCD_R3 0x790f +#define STM32F429_PH9_FUNC_EVENTOUT 0x7910 +#define STM32F429_PH9_FUNC_ANALOG 0x7911 + +#define STM32F429_PH10_FUNC_GPIO 0x7a00 +#define STM32F429_PH10_FUNC_TIM5_CH1 0x7a03 +#define STM32F429_PH10_FUNC_FMC_D18 0x7a0d +#define STM32F429_PH10_FUNC_DCMI_D1 0x7a0e +#define STM32F429_PH10_FUNC_LCD_R4 0x7a0f +#define STM32F429_PH10_FUNC_EVENTOUT 0x7a10 +#define STM32F429_PH10_FUNC_ANALOG 0x7a11 + +#define STM32F429_PH11_FUNC_GPIO 0x7b00 +#define STM32F429_PH11_FUNC_TIM5_CH2 0x7b03 +#define STM32F429_PH11_FUNC_FMC_D19 0x7b0d +#define STM32F429_PH11_FUNC_DCMI_D2 0x7b0e +#define STM32F429_PH11_FUNC_LCD_R5 0x7b0f +#define STM32F429_PH11_FUNC_EVENTOUT 0x7b10 +#define STM32F429_PH11_FUNC_ANALOG 0x7b11 + +#define STM32F429_PH12_FUNC_GPIO 0x7c00 +#define STM32F429_PH12_FUNC_TIM5_CH3 0x7c03 +#define STM32F429_PH12_FUNC_FMC_D20 0x7c0d +#define STM32F429_PH12_FUNC_DCMI_D3 0x7c0e +#define STM32F429_PH12_FUNC_LCD_R6 0x7c0f +#define STM32F429_PH12_FUNC_EVENTOUT 0x7c10 +#define STM32F429_PH12_FUNC_ANALOG 0x7c11 + +#define STM32F429_PH13_FUNC_GPIO 0x7d00 +#define STM32F429_PH13_FUNC_TIM8_CH1N 0x7d04 +#define STM32F429_PH13_FUNC_CAN1_TX 0x7d0a +#define STM32F429_PH13_FUNC_FMC_D21 0x7d0d +#define STM32F429_PH13_FUNC_LCD_G2 0x7d0f +#define STM32F429_PH13_FUNC_EVENTOUT 0x7d10 +#define STM32F429_PH13_FUNC_ANALOG 0x7d11 + +#define STM32F429_PH14_FUNC_GPIO 0x7e00 +#define STM32F429_PH14_FUNC_TIM8_CH2N 0x7e04 +#define STM32F429_PH14_FUNC_FMC_D22 0x7e0d +#define STM32F429_PH14_FUNC_DCMI_D4 0x7e0e +#define STM32F429_PH14_FUNC_LCD_G3 0x7e0f +#define STM32F429_PH14_FUNC_EVENTOUT 0x7e10 +#define STM32F429_PH14_FUNC_ANALOG 0x7e11 + +#define STM32F429_PH15_FUNC_GPIO 0x7f00 +#define STM32F429_PH15_FUNC_TIM8_CH3N 0x7f04 +#define STM32F429_PH15_FUNC_FMC_D23 0x7f0d +#define STM32F429_PH15_FUNC_DCMI_D11 0x7f0e +#define STM32F429_PH15_FUNC_LCD_G4 0x7f0f +#define STM32F429_PH15_FUNC_EVENTOUT 0x7f10 +#define STM32F429_PH15_FUNC_ANALOG 0x7f11 + + + +#define STM32F429_PI0_FUNC_GPIO 0x8000 +#define STM32F429_PI0_FUNC_TIM5_CH4 0x8003 +#define STM32F429_PI0_FUNC_SPI2_NSS_I2S2_WS 0x8006 +#define STM32F429_PI0_FUNC_FMC_D24 0x800d +#define STM32F429_PI0_FUNC_DCMI_D13 0x800e +#define STM32F429_PI0_FUNC_LCD_G5 0x800f +#define STM32F429_PI0_FUNC_EVENTOUT 0x8010 +#define STM32F429_PI0_FUNC_ANALOG 0x8011 + +#define STM32F429_PI1_FUNC_GPIO 0x8100 +#define STM32F429_PI1_FUNC_SPI2_SCK_I2S2_CK 0x8106 +#define STM32F429_PI1_FUNC_FMC_D25 0x810d +#define STM32F429_PI1_FUNC_DCMI_D8 0x810e +#define STM32F429_PI1_FUNC_LCD_G6 0x810f +#define STM32F429_PI1_FUNC_EVENTOUT 0x8110 +#define STM32F429_PI1_FUNC_ANALOG 0x8111 + +#define STM32F429_PI2_FUNC_GPIO 0x8200 +#define STM32F429_PI2_FUNC_TIM8_CH4 0x8204 +#define STM32F429_PI2_FUNC_SPI2_MISO 0x8206 +#define STM32F429_PI2_FUNC_I2S2EXT_SD 0x8207 +#define STM32F429_PI2_FUNC_FMC_D26 0x820d +#define STM32F429_PI2_FUNC_DCMI_D9 0x820e +#define STM32F429_PI2_FUNC_LCD_G7 0x820f +#define STM32F429_PI2_FUNC_EVENTOUT 0x8210 +#define STM32F429_PI2_FUNC_ANALOG 0x8211 + +#define STM32F429_PI3_FUNC_GPIO 0x8300 +#define STM32F429_PI3_FUNC_TIM8_ETR 0x8304 +#define STM32F429_PI3_FUNC_SPI2_MOSI_I2S2_SD 0x8306 +#define STM32F429_PI3_FUNC_FMC_D27 0x830d +#define STM32F429_PI3_FUNC_DCMI_D10 0x830e +#define STM32F429_PI3_FUNC_EVENTOUT 0x8310 +#define STM32F429_PI3_FUNC_ANALOG 0x8311 + +#define STM32F429_PI4_FUNC_GPIO 0x8400 +#define STM32F429_PI4_FUNC_TIM8_BKIN 0x8404 +#define STM32F429_PI4_FUNC_FMC_NBL2 0x840d +#define STM32F429_PI4_FUNC_DCMI_D5 0x840e +#define STM32F429_PI4_FUNC_LCD_B4 0x840f +#define STM32F429_PI4_FUNC_EVENTOUT 0x8410 +#define STM32F429_PI4_FUNC_ANALOG 0x8411 + +#define STM32F429_PI5_FUNC_GPIO 0x8500 +#define STM32F429_PI5_FUNC_TIM8_CH1 0x8504 +#define STM32F429_PI5_FUNC_FMC_NBL3 0x850d +#define STM32F429_PI5_FUNC_DCMI_VSYNC 0x850e +#define STM32F429_PI5_FUNC_LCD_B5 0x850f +#define STM32F429_PI5_FUNC_EVENTOUT 0x8510 +#define STM32F429_PI5_FUNC_ANALOG 0x8511 + +#define STM32F429_PI6_FUNC_GPIO 0x8600 +#define STM32F429_PI6_FUNC_TIM8_CH2 0x8604 +#define STM32F429_PI6_FUNC_FMC_D28 0x860d +#define STM32F429_PI6_FUNC_DCMI_D6 0x860e +#define STM32F429_PI6_FUNC_LCD_B6 0x860f +#define STM32F429_PI6_FUNC_EVENTOUT 0x8610 +#define STM32F429_PI6_FUNC_ANALOG 0x8611 + +#define STM32F429_PI7_FUNC_GPIO 0x8700 +#define STM32F429_PI7_FUNC_TIM8_CH3 0x8704 +#define STM32F429_PI7_FUNC_FMC_D29 0x870d +#define STM32F429_PI7_FUNC_DCMI_D7 0x870e +#define STM32F429_PI7_FUNC_LCD_B7 0x870f +#define STM32F429_PI7_FUNC_EVENTOUT 0x8710 +#define STM32F429_PI7_FUNC_ANALOG 0x8711 + +#define STM32F429_PI8_FUNC_GPIO 0x8800 +#define STM32F429_PI8_FUNC_EVENTOUT 0x8810 +#define STM32F429_PI8_FUNC_ANALOG 0x8811 + +#define STM32F429_PI9_FUNC_GPIO 0x8900 +#define STM32F429_PI9_FUNC_CAN1_RX 0x890a +#define STM32F429_PI9_FUNC_FMC_D30 0x890d +#define STM32F429_PI9_FUNC_LCD_VSYNC 0x890f +#define STM32F429_PI9_FUNC_EVENTOUT 0x8910 +#define STM32F429_PI9_FUNC_ANALOG 0x8911 + +#define STM32F429_PI10_FUNC_GPIO 0x8a00 +#define STM32F429_PI10_FUNC_ETH_MII_RX_ER 0x8a0c +#define STM32F429_PI10_FUNC_FMC_D31 0x8a0d +#define STM32F429_PI10_FUNC_LCD_HSYNC 0x8a0f +#define STM32F429_PI10_FUNC_EVENTOUT 0x8a10 +#define STM32F429_PI10_FUNC_ANALOG 0x8a11 + +#define STM32F429_PI11_FUNC_GPIO 0x8b00 +#define STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR 0x8b0b +#define STM32F429_PI11_FUNC_EVENTOUT 0x8b10 +#define STM32F429_PI11_FUNC_ANALOG 0x8b11 + +#define STM32F429_PI12_FUNC_GPIO 0x8c00 +#define STM32F429_PI12_FUNC_LCD_HSYNC 0x8c0f +#define STM32F429_PI12_FUNC_EVENTOUT 0x8c10 +#define STM32F429_PI12_FUNC_ANALOG 0x8c11 + +#define STM32F429_PI13_FUNC_GPIO 0x8d00 +#define STM32F429_PI13_FUNC_LCD_VSYNC 0x8d0f +#define STM32F429_PI13_FUNC_EVENTOUT 0x8d10 +#define STM32F429_PI13_FUNC_ANALOG 0x8d11 + +#define STM32F429_PI14_FUNC_GPIO 0x8e00 +#define STM32F429_PI14_FUNC_LCD_CLK 0x8e0f +#define STM32F429_PI14_FUNC_EVENTOUT 0x8e10 +#define STM32F429_PI14_FUNC_ANALOG 0x8e11 + +#define STM32F429_PI15_FUNC_GPIO 0x8f00 +#define STM32F429_PI15_FUNC_LCD_R0 0x8f0f +#define STM32F429_PI15_FUNC_EVENTOUT 0x8f10 +#define STM32F429_PI15_FUNC_ANALOG 0x8f11 + + + +#define STM32F429_PJ0_FUNC_GPIO 0x9000 +#define STM32F429_PJ0_FUNC_LCD_R1 0x900f +#define STM32F429_PJ0_FUNC_EVENTOUT 0x9010 +#define STM32F429_PJ0_FUNC_ANALOG 0x9011 + +#define STM32F429_PJ1_FUNC_GPIO 0x9100 +#define STM32F429_PJ1_FUNC_LCD_R2 0x910f +#define STM32F429_PJ1_FUNC_EVENTOUT 0x9110 +#define STM32F429_PJ1_FUNC_ANALOG 0x9111 + +#define STM32F429_PJ2_FUNC_GPIO 0x9200 +#define STM32F429_PJ2_FUNC_LCD_R3 0x920f +#define STM32F429_PJ2_FUNC_EVENTOUT 0x9210 +#define STM32F429_PJ2_FUNC_ANALOG 0x9211 + +#define STM32F429_PJ3_FUNC_GPIO 0x9300 +#define STM32F429_PJ3_FUNC_LCD_R4 0x930f +#define STM32F429_PJ3_FUNC_EVENTOUT 0x9310 +#define STM32F429_PJ3_FUNC_ANALOG 0x9311 + +#define STM32F429_PJ4_FUNC_GPIO 0x9400 +#define STM32F429_PJ4_FUNC_LCD_R5 0x940f +#define STM32F429_PJ4_FUNC_EVENTOUT 0x9410 +#define STM32F429_PJ4_FUNC_ANALOG 0x9411 + +#define STM32F429_PJ5_FUNC_GPIO 0x9500 +#define STM32F429_PJ5_FUNC_LCD_R6 0x950f +#define STM32F429_PJ5_FUNC_EVENTOUT 0x9510 +#define STM32F429_PJ5_FUNC_ANALOG 0x9511 + +#define STM32F429_PJ6_FUNC_GPIO 0x9600 +#define STM32F429_PJ6_FUNC_LCD_R7 0x960f +#define STM32F429_PJ6_FUNC_EVENTOUT 0x9610 +#define STM32F429_PJ6_FUNC_ANALOG 0x9611 + +#define STM32F429_PJ7_FUNC_GPIO 0x9700 +#define STM32F429_PJ7_FUNC_LCD_G0 0x970f +#define STM32F429_PJ7_FUNC_EVENTOUT 0x9710 +#define STM32F429_PJ7_FUNC_ANALOG 0x9711 + +#define STM32F429_PJ8_FUNC_GPIO 0x9800 +#define STM32F429_PJ8_FUNC_LCD_G1 0x980f +#define STM32F429_PJ8_FUNC_EVENTOUT 0x9810 +#define STM32F429_PJ8_FUNC_ANALOG 0x9811 + +#define STM32F429_PJ9_FUNC_GPIO 0x9900 +#define STM32F429_PJ9_FUNC_LCD_G2 0x990f +#define STM32F429_PJ9_FUNC_EVENTOUT 0x9910 +#define STM32F429_PJ9_FUNC_ANALOG 0x9911 + +#define STM32F429_PJ10_FUNC_GPIO 0x9a00 +#define STM32F429_PJ10_FUNC_LCD_G3 0x9a0f +#define STM32F429_PJ10_FUNC_EVENTOUT 0x9a10 +#define STM32F429_PJ10_FUNC_ANALOG 0x9a11 + +#define STM32F429_PJ11_FUNC_GPIO 0x9b00 +#define STM32F429_PJ11_FUNC_LCD_G4 0x9b0f +#define STM32F429_PJ11_FUNC_EVENTOUT 0x9b10 +#define STM32F429_PJ11_FUNC_ANALOG 0x9b11 + +#define STM32F429_PJ12_FUNC_GPIO 0x9c00 +#define STM32F429_PJ12_FUNC_LCD_B0 0x9c0f +#define STM32F429_PJ12_FUNC_EVENTOUT 0x9c10 +#define STM32F429_PJ12_FUNC_ANALOG 0x9c11 + +#define STM32F429_PJ13_FUNC_GPIO 0x9d00 +#define STM32F429_PJ13_FUNC_LCD_B1 0x9d0f +#define STM32F429_PJ13_FUNC_EVENTOUT 0x9d10 +#define STM32F429_PJ13_FUNC_ANALOG 0x9d11 + +#define STM32F429_PJ14_FUNC_GPIO 0x9e00 +#define STM32F429_PJ14_FUNC_LCD_B2 0x9e0f +#define STM32F429_PJ14_FUNC_EVENTOUT 0x9e10 +#define STM32F429_PJ14_FUNC_ANALOG 0x9e11 + +#define STM32F429_PJ15_FUNC_GPIO 0x9f00 +#define STM32F429_PJ15_FUNC_LCD_B3 0x9f0f +#define STM32F429_PJ15_FUNC_EVENTOUT 0x9f10 +#define STM32F429_PJ15_FUNC_ANALOG 0x9f11 + + + +#define STM32F429_PK0_FUNC_GPIO 0xa000 +#define STM32F429_PK0_FUNC_LCD_G5 0xa00f +#define STM32F429_PK0_FUNC_EVENTOUT 0xa010 +#define STM32F429_PK0_FUNC_ANALOG 0xa011 + +#define STM32F429_PK1_FUNC_GPIO 0xa100 +#define STM32F429_PK1_FUNC_LCD_G6 0xa10f +#define STM32F429_PK1_FUNC_EVENTOUT 0xa110 +#define STM32F429_PK1_FUNC_ANALOG 0xa111 + +#define STM32F429_PK2_FUNC_GPIO 0xa200 +#define STM32F429_PK2_FUNC_LCD_G7 0xa20f +#define STM32F429_PK2_FUNC_EVENTOUT 0xa210 +#define STM32F429_PK2_FUNC_ANALOG 0xa211 + +#define STM32F429_PK3_FUNC_GPIO 0xa300 +#define STM32F429_PK3_FUNC_LCD_B4 0xa30f +#define STM32F429_PK3_FUNC_EVENTOUT 0xa310 +#define STM32F429_PK3_FUNC_ANALOG 0xa311 + +#define STM32F429_PK4_FUNC_GPIO 0xa400 +#define STM32F429_PK4_FUNC_LCD_B5 0xa40f +#define STM32F429_PK4_FUNC_EVENTOUT 0xa410 +#define STM32F429_PK4_FUNC_ANALOG 0xa411 + +#define STM32F429_PK5_FUNC_GPIO 0xa500 +#define STM32F429_PK5_FUNC_LCD_B6 0xa50f +#define STM32F429_PK5_FUNC_EVENTOUT 0xa510 +#define STM32F429_PK5_FUNC_ANALOG 0xa511 + +#define STM32F429_PK6_FUNC_GPIO 0xa600 +#define STM32F429_PK6_FUNC_LCD_B7 0xa60f +#define STM32F429_PK6_FUNC_EVENTOUT 0xa610 +#define STM32F429_PK6_FUNC_ANALOG 0xa611 + +#define STM32F429_PK7_FUNC_GPIO 0xa700 +#define STM32F429_PK7_FUNC_LCD_DE 0xa70f +#define STM32F429_PK7_FUNC_EVENTOUT 0xa710 +#define STM32F429_PK7_FUNC_ANALOG 0xa711 + +#endif /* _DT_BINDINGS_STM32F429_PINFUNC_H */ -- 1.9.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v4 3/9] includes: dt-bindings: Add STM32F429 pinctrl DT bindings @ 2016-01-14 12:16 ` Maxime Coquelin 0 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-01-14 12:16 UTC (permalink / raw) To: linux-arm-kernel Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> --- include/dt-bindings/pinctrl/pinctrl-stm32.h | 12 + include/dt-bindings/pinctrl/stm32f429-pinfunc.h | 1241 +++++++++++++++++++++++ 2 files changed, 1253 insertions(+) create mode 100644 include/dt-bindings/pinctrl/pinctrl-stm32.h create mode 100644 include/dt-bindings/pinctrl/stm32f429-pinfunc.h diff --git a/include/dt-bindings/pinctrl/pinctrl-stm32.h b/include/dt-bindings/pinctrl/pinctrl-stm32.h new file mode 100644 index 0000000..a2e7222 --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-stm32.h @@ -0,0 +1,12 @@ +#ifndef _DT_BINDINGS_PINCTRL_STM32_H +#define _DT_BINDINGS_PINCTRL_STM32_H + +#define STM32_PIN_NO(x) ((x) << 8) +#define STM32_GET_PIN_NO(x) ((x) >> 8) +#define STM32_GET_PIN_FUNC(x) ((x) & 0xff) + +#define STM32_PIN_GPIO 0 +#define STM32_PIN_AF(x) ((x) + 1) +#define STM32_PIN_ANALOG (STM32_PIN_AF(15) + 1) + +#endif /* _DT_BINDINGS_PINCTRL_STM32_H */ diff --git a/include/dt-bindings/pinctrl/stm32f429-pinfunc.h b/include/dt-bindings/pinctrl/stm32f429-pinfunc.h new file mode 100644 index 0000000..9dd5fd0 --- /dev/null +++ b/include/dt-bindings/pinctrl/stm32f429-pinfunc.h @@ -0,0 +1,1241 @@ +#ifndef _DT_BINDINGS_STM32F429_PINFUNC_H +#define _DT_BINDINGS_STM32F429_PINFUNC_H + +#include <dt-bindings/pinctrl/pinctrl-stm32.h> + +#define STM32F429_PA0_FUNC_GPIO 0x0 +#define STM32F429_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2 +#define STM32F429_PA0_FUNC_TIM5_CH1 0x3 +#define STM32F429_PA0_FUNC_TIM8_ETR 0x4 +#define STM32F429_PA0_FUNC_USART2_CTS 0x8 +#define STM32F429_PA0_FUNC_UART4_TX 0x9 +#define STM32F429_PA0_FUNC_ETH_MII_CRS 0xc +#define STM32F429_PA0_FUNC_EVENTOUT 0x10 +#define STM32F429_PA0_FUNC_ANALOG 0x11 + +#define STM32F429_PA1_FUNC_GPIO 0x100 +#define STM32F429_PA1_FUNC_TIM2_CH2 0x102 +#define STM32F429_PA1_FUNC_TIM5_CH2 0x103 +#define STM32F429_PA1_FUNC_USART2_RTS 0x108 +#define STM32F429_PA1_FUNC_UART4_RX 0x109 +#define STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK 0x10c +#define STM32F429_PA1_FUNC_EVENTOUT 0x110 +#define STM32F429_PA1_FUNC_ANALOG 0x111 + +#define STM32F429_PA2_FUNC_GPIO 0x200 +#define STM32F429_PA2_FUNC_TIM2_CH3 0x202 +#define STM32F429_PA2_FUNC_TIM5_CH3 0x203 +#define STM32F429_PA2_FUNC_TIM9_CH1 0x204 +#define STM32F429_PA2_FUNC_USART2_TX 0x208 +#define STM32F429_PA2_FUNC_ETH_MDIO 0x20c +#define STM32F429_PA2_FUNC_EVENTOUT 0x210 +#define STM32F429_PA2_FUNC_ANALOG 0x211 + +#define STM32F429_PA3_FUNC_GPIO 0x300 +#define STM32F429_PA3_FUNC_TIM2_CH4 0x302 +#define STM32F429_PA3_FUNC_TIM5_CH4 0x303 +#define STM32F429_PA3_FUNC_TIM9_CH2 0x304 +#define STM32F429_PA3_FUNC_USART2_RX 0x308 +#define STM32F429_PA3_FUNC_OTG_HS_ULPI_D0 0x30b +#define STM32F429_PA3_FUNC_ETH_MII_COL 0x30c +#define STM32F429_PA3_FUNC_LCD_B5 0x30f +#define STM32F429_PA3_FUNC_EVENTOUT 0x310 +#define STM32F429_PA3_FUNC_ANALOG 0x311 + +#define STM32F429_PA4_FUNC_GPIO 0x400 +#define STM32F429_PA4_FUNC_SPI1_NSS 0x406 +#define STM32F429_PA4_FUNC_SPI3_NSS_I2S3_WS 0x407 +#define STM32F429_PA4_FUNC_USART2_CK 0x408 +#define STM32F429_PA4_FUNC_OTG_HS_SOF 0x40d +#define STM32F429_PA4_FUNC_DCMI_HSYNC 0x40e +#define STM32F429_PA4_FUNC_LCD_VSYNC 0x40f +#define STM32F429_PA4_FUNC_EVENTOUT 0x410 +#define STM32F429_PA4_FUNC_ANALOG 0x411 + +#define STM32F429_PA5_FUNC_GPIO 0x500 +#define STM32F429_PA5_FUNC_TIM2_CH1_TIM2_ETR 0x502 +#define STM32F429_PA5_FUNC_TIM8_CH1N 0x504 +#define STM32F429_PA5_FUNC_SPI1_SCK 0x506 +#define STM32F429_PA5_FUNC_OTG_HS_ULPI_CK 0x50b +#define STM32F429_PA5_FUNC_EVENTOUT 0x510 +#define STM32F429_PA5_FUNC_ANALOG 0x511 + +#define STM32F429_PA6_FUNC_GPIO 0x600 +#define STM32F429_PA6_FUNC_TIM1_BKIN 0x602 +#define STM32F429_PA6_FUNC_TIM3_CH1 0x603 +#define STM32F429_PA6_FUNC_TIM8_BKIN 0x604 +#define STM32F429_PA6_FUNC_SPI1_MISO 0x606 +#define STM32F429_PA6_FUNC_TIM13_CH1 0x60a +#define STM32F429_PA6_FUNC_DCMI_PIXCLK 0x60e +#define STM32F429_PA6_FUNC_LCD_G2 0x60f +#define STM32F429_PA6_FUNC_EVENTOUT 0x610 +#define STM32F429_PA6_FUNC_ANALOG 0x611 + +#define STM32F429_PA7_FUNC_GPIO 0x700 +#define STM32F429_PA7_FUNC_TIM1_CH1N 0x702 +#define STM32F429_PA7_FUNC_TIM3_CH2 0x703 +#define STM32F429_PA7_FUNC_TIM8_CH1N 0x704 +#define STM32F429_PA7_FUNC_SPI1_MOSI 0x706 +#define STM32F429_PA7_FUNC_TIM14_CH1 0x70a +#define STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV 0x70c +#define STM32F429_PA7_FUNC_EVENTOUT 0x710 +#define STM32F429_PA7_FUNC_ANALOG 0x711 + +#define STM32F429_PA8_FUNC_GPIO 0x800 +#define STM32F429_PA8_FUNC_MCO1 0x801 +#define STM32F429_PA8_FUNC_TIM1_CH1 0x802 +#define STM32F429_PA8_FUNC_I2C3_SCL 0x805 +#define STM32F429_PA8_FUNC_USART1_CK 0x808 +#define STM32F429_PA8_FUNC_OTG_FS_SOF 0x80b +#define STM32F429_PA8_FUNC_LCD_R6 0x80f +#define STM32F429_PA8_FUNC_EVENTOUT 0x810 +#define STM32F429_PA8_FUNC_ANALOG 0x811 + +#define STM32F429_PA9_FUNC_GPIO 0x900 +#define STM32F429_PA9_FUNC_TIM1_CH2 0x902 +#define STM32F429_PA9_FUNC_I2C3_SMBA 0x905 +#define STM32F429_PA9_FUNC_USART1_TX 0x908 +#define STM32F429_PA9_FUNC_DCMI_D0 0x90e +#define STM32F429_PA9_FUNC_EVENTOUT 0x910 +#define STM32F429_PA9_FUNC_ANALOG 0x911 + +#define STM32F429_PA10_FUNC_GPIO 0xa00 +#define STM32F429_PA10_FUNC_TIM1_CH3 0xa02 +#define STM32F429_PA10_FUNC_USART1_RX 0xa08 +#define STM32F429_PA10_FUNC_OTG_FS_ID 0xa0b +#define STM32F429_PA10_FUNC_DCMI_D1 0xa0e +#define STM32F429_PA10_FUNC_EVENTOUT 0xa10 +#define STM32F429_PA10_FUNC_ANALOG 0xa11 + +#define STM32F429_PA11_FUNC_GPIO 0xb00 +#define STM32F429_PA11_FUNC_TIM1_CH4 0xb02 +#define STM32F429_PA11_FUNC_USART1_CTS 0xb08 +#define STM32F429_PA11_FUNC_CAN1_RX 0xb0a +#define STM32F429_PA11_FUNC_OTG_FS_DM 0xb0b +#define STM32F429_PA11_FUNC_LCD_R4 0xb0f +#define STM32F429_PA11_FUNC_EVENTOUT 0xb10 +#define STM32F429_PA11_FUNC_ANALOG 0xb11 + +#define STM32F429_PA12_FUNC_GPIO 0xc00 +#define STM32F429_PA12_FUNC_TIM1_ETR 0xc02 +#define STM32F429_PA12_FUNC_USART1_RTS 0xc08 +#define STM32F429_PA12_FUNC_CAN1_TX 0xc0a +#define STM32F429_PA12_FUNC_OTG_FS_DP 0xc0b +#define STM32F429_PA12_FUNC_LCD_R5 0xc0f +#define STM32F429_PA12_FUNC_EVENTOUT 0xc10 +#define STM32F429_PA12_FUNC_ANALOG 0xc11 + +#define STM32F429_PA13_FUNC_GPIO 0xd00 +#define STM32F429_PA13_FUNC_JTMS_SWDIO 0xd01 +#define STM32F429_PA13_FUNC_EVENTOUT 0xd10 +#define STM32F429_PA13_FUNC_ANALOG 0xd11 + +#define STM32F429_PA14_FUNC_GPIO 0xe00 +#define STM32F429_PA14_FUNC_JTCK_SWCLK 0xe01 +#define STM32F429_PA14_FUNC_EVENTOUT 0xe10 +#define STM32F429_PA14_FUNC_ANALOG 0xe11 + +#define STM32F429_PA15_FUNC_GPIO 0xf00 +#define STM32F429_PA15_FUNC_JTDI 0xf01 +#define STM32F429_PA15_FUNC_TIM2_CH1_TIM2_ETR 0xf02 +#define STM32F429_PA15_FUNC_SPI1_NSS 0xf06 +#define STM32F429_PA15_FUNC_SPI3_NSS_I2S3_WS 0xf07 +#define STM32F429_PA15_FUNC_EVENTOUT 0xf10 +#define STM32F429_PA15_FUNC_ANALOG 0xf11 + + + +#define STM32F429_PB0_FUNC_GPIO 0x1000 +#define STM32F429_PB0_FUNC_TIM1_CH2N 0x1002 +#define STM32F429_PB0_FUNC_TIM3_CH3 0x1003 +#define STM32F429_PB0_FUNC_TIM8_CH2N 0x1004 +#define STM32F429_PB0_FUNC_LCD_R3 0x100a +#define STM32F429_PB0_FUNC_OTG_HS_ULPI_D1 0x100b +#define STM32F429_PB0_FUNC_ETH_MII_RXD2 0x100c +#define STM32F429_PB0_FUNC_EVENTOUT 0x1010 +#define STM32F429_PB0_FUNC_ANALOG 0x1011 + +#define STM32F429_PB1_FUNC_GPIO 0x1100 +#define STM32F429_PB1_FUNC_TIM1_CH3N 0x1102 +#define STM32F429_PB1_FUNC_TIM3_CH4 0x1103 +#define STM32F429_PB1_FUNC_TIM8_CH3N 0x1104 +#define STM32F429_PB1_FUNC_LCD_R6 0x110a +#define STM32F429_PB1_FUNC_OTG_HS_ULPI_D2 0x110b +#define STM32F429_PB1_FUNC_ETH_MII_RXD3 0x110c +#define STM32F429_PB1_FUNC_EVENTOUT 0x1110 +#define STM32F429_PB1_FUNC_ANALOG 0x1111 + +#define STM32F429_PB2_FUNC_GPIO 0x1200 +#define STM32F429_PB2_FUNC_EVENTOUT 0x1210 +#define STM32F429_PB2_FUNC_ANALOG 0x1211 + +#define STM32F429_PB3_FUNC_GPIO 0x1300 +#define STM32F429_PB3_FUNC_JTDO_TRACESWO 0x1301 +#define STM32F429_PB3_FUNC_TIM2_CH2 0x1302 +#define STM32F429_PB3_FUNC_SPI1_SCK 0x1306 +#define STM32F429_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307 +#define STM32F429_PB3_FUNC_EVENTOUT 0x1310 +#define STM32F429_PB3_FUNC_ANALOG 0x1311 + +#define STM32F429_PB4_FUNC_GPIO 0x1400 +#define STM32F429_PB4_FUNC_NJTRST 0x1401 +#define STM32F429_PB4_FUNC_TIM3_CH1 0x1403 +#define STM32F429_PB4_FUNC_SPI1_MISO 0x1406 +#define STM32F429_PB4_FUNC_SPI3_MISO 0x1407 +#define STM32F429_PB4_FUNC_I2S3EXT_SD 0x1408 +#define STM32F429_PB4_FUNC_EVENTOUT 0x1410 +#define STM32F429_PB4_FUNC_ANALOG 0x1411 + +#define STM32F429_PB5_FUNC_GPIO 0x1500 +#define STM32F429_PB5_FUNC_TIM3_CH2 0x1503 +#define STM32F429_PB5_FUNC_I2C1_SMBA 0x1505 +#define STM32F429_PB5_FUNC_SPI1_MOSI 0x1506 +#define STM32F429_PB5_FUNC_SPI3_MOSI_I2S3_SD 0x1507 +#define STM32F429_PB5_FUNC_CAN2_RX 0x150a +#define STM32F429_PB5_FUNC_OTG_HS_ULPI_D7 0x150b +#define STM32F429_PB5_FUNC_ETH_PPS_OUT 0x150c +#define STM32F429_PB5_FUNC_FMC_SDCKE1 0x150d +#define STM32F429_PB5_FUNC_DCMI_D10 0x150e +#define STM32F429_PB5_FUNC_EVENTOUT 0x1510 +#define STM32F429_PB5_FUNC_ANALOG 0x1511 + +#define STM32F429_PB6_FUNC_GPIO 0x1600 +#define STM32F429_PB6_FUNC_TIM4_CH1 0x1603 +#define STM32F429_PB6_FUNC_I2C1_SCL 0x1605 +#define STM32F429_PB6_FUNC_USART1_TX 0x1608 +#define STM32F429_PB6_FUNC_CAN2_TX 0x160a +#define STM32F429_PB6_FUNC_FMC_SDNE1 0x160d +#define STM32F429_PB6_FUNC_DCMI_D5 0x160e +#define STM32F429_PB6_FUNC_EVENTOUT 0x1610 +#define STM32F429_PB6_FUNC_ANALOG 0x1611 + +#define STM32F429_PB7_FUNC_GPIO 0x1700 +#define STM32F429_PB7_FUNC_TIM4_CH2 0x1703 +#define STM32F429_PB7_FUNC_I2C1_SDA 0x1705 +#define STM32F429_PB7_FUNC_USART1_RX 0x1708 +#define STM32F429_PB7_FUNC_FMC_NL 0x170d +#define STM32F429_PB7_FUNC_DCMI_VSYNC 0x170e +#define STM32F429_PB7_FUNC_EVENTOUT 0x1710 +#define STM32F429_PB7_FUNC_ANALOG 0x1711 + +#define STM32F429_PB8_FUNC_GPIO 0x1800 +#define STM32F429_PB8_FUNC_TIM4_CH3 0x1803 +#define STM32F429_PB8_FUNC_TIM10_CH1 0x1804 +#define STM32F429_PB8_FUNC_I2C1_SCL 0x1805 +#define STM32F429_PB8_FUNC_CAN1_RX 0x180a +#define STM32F429_PB8_FUNC_ETH_MII_TXD3 0x180c +#define STM32F429_PB8_FUNC_SDIO_D4 0x180d +#define STM32F429_PB8_FUNC_DCMI_D6 0x180e +#define STM32F429_PB8_FUNC_LCD_B6 0x180f +#define STM32F429_PB8_FUNC_EVENTOUT 0x1810 +#define STM32F429_PB8_FUNC_ANALOG 0x1811 + +#define STM32F429_PB9_FUNC_GPIO 0x1900 +#define STM32F429_PB9_FUNC_TIM4_CH4 0x1903 +#define STM32F429_PB9_FUNC_TIM11_CH1 0x1904 +#define STM32F429_PB9_FUNC_I2C1_SDA 0x1905 +#define STM32F429_PB9_FUNC_SPI2_NSS_I2S2_WS 0x1906 +#define STM32F429_PB9_FUNC_CAN1_TX 0x190a +#define STM32F429_PB9_FUNC_SDIO_D5 0x190d +#define STM32F429_PB9_FUNC_DCMI_D7 0x190e +#define STM32F429_PB9_FUNC_LCD_B7 0x190f +#define STM32F429_PB9_FUNC_EVENTOUT 0x1910 +#define STM32F429_PB9_FUNC_ANALOG 0x1911 + +#define STM32F429_PB10_FUNC_GPIO 0x1a00 +#define STM32F429_PB10_FUNC_TIM2_CH3 0x1a02 +#define STM32F429_PB10_FUNC_I2C2_SCL 0x1a05 +#define STM32F429_PB10_FUNC_SPI2_SCK_I2S2_CK 0x1a06 +#define STM32F429_PB10_FUNC_USART3_TX 0x1a08 +#define STM32F429_PB10_FUNC_OTG_HS_ULPI_D3 0x1a0b +#define STM32F429_PB10_FUNC_ETH_MII_RX_ER 0x1a0c +#define STM32F429_PB10_FUNC_LCD_G4 0x1a0f +#define STM32F429_PB10_FUNC_EVENTOUT 0x1a10 +#define STM32F429_PB10_FUNC_ANALOG 0x1a11 + +#define STM32F429_PB11_FUNC_GPIO 0x1b00 +#define STM32F429_PB11_FUNC_TIM2_CH4 0x1b02 +#define STM32F429_PB11_FUNC_I2C2_SDA 0x1b05 +#define STM32F429_PB11_FUNC_USART3_RX 0x1b08 +#define STM32F429_PB11_FUNC_OTG_HS_ULPI_D4 0x1b0b +#define STM32F429_PB11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x1b0c +#define STM32F429_PB11_FUNC_LCD_G5 0x1b0f +#define STM32F429_PB11_FUNC_EVENTOUT 0x1b10 +#define STM32F429_PB11_FUNC_ANALOG 0x1b11 + +#define STM32F429_PB12_FUNC_GPIO 0x1c00 +#define STM32F429_PB12_FUNC_TIM1_BKIN 0x1c02 +#define STM32F429_PB12_FUNC_I2C2_SMBA 0x1c05 +#define STM32F429_PB12_FUNC_SPI2_NSS_I2S2_WS 0x1c06 +#define STM32F429_PB12_FUNC_USART3_CK 0x1c08 +#define STM32F429_PB12_FUNC_CAN2_RX 0x1c0a +#define STM32F429_PB12_FUNC_OTG_HS_ULPI_D5 0x1c0b +#define STM32F429_PB12_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x1c0c +#define STM32F429_PB12_FUNC_OTG_HS_ID 0x1c0d +#define STM32F429_PB12_FUNC_EVENTOUT 0x1c10 +#define STM32F429_PB12_FUNC_ANALOG 0x1c11 + +#define STM32F429_PB13_FUNC_GPIO 0x1d00 +#define STM32F429_PB13_FUNC_TIM1_CH1N 0x1d02 +#define STM32F429_PB13_FUNC_SPI2_SCK_I2S2_CK 0x1d06 +#define STM32F429_PB13_FUNC_USART3_CTS 0x1d08 +#define STM32F429_PB13_FUNC_CAN2_TX 0x1d0a +#define STM32F429_PB13_FUNC_OTG_HS_ULPI_D6 0x1d0b +#define STM32F429_PB13_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x1d0c +#define STM32F429_PB13_FUNC_EVENTOUT 0x1d10 +#define STM32F429_PB13_FUNC_ANALOG 0x1d11 + +#define STM32F429_PB14_FUNC_GPIO 0x1e00 +#define STM32F429_PB14_FUNC_TIM1_CH2N 0x1e02 +#define STM32F429_PB14_FUNC_TIM8_CH2N 0x1e04 +#define STM32F429_PB14_FUNC_SPI2_MISO 0x1e06 +#define STM32F429_PB14_FUNC_I2S2EXT_SD 0x1e07 +#define STM32F429_PB14_FUNC_USART3_RTS 0x1e08 +#define STM32F429_PB14_FUNC_TIM12_CH1 0x1e0a +#define STM32F429_PB14_FUNC_OTG_HS_DM 0x1e0d +#define STM32F429_PB14_FUNC_EVENTOUT 0x1e10 +#define STM32F429_PB14_FUNC_ANALOG 0x1e11 + +#define STM32F429_PB15_FUNC_GPIO 0x1f00 +#define STM32F429_PB15_FUNC_RTC_REFIN 0x1f01 +#define STM32F429_PB15_FUNC_TIM1_CH3N 0x1f02 +#define STM32F429_PB15_FUNC_TIM8_CH3N 0x1f04 +#define STM32F429_PB15_FUNC_SPI2_MOSI_I2S2_SD 0x1f06 +#define STM32F429_PB15_FUNC_TIM12_CH2 0x1f0a +#define STM32F429_PB15_FUNC_OTG_HS_DP 0x1f0d +#define STM32F429_PB15_FUNC_EVENTOUT 0x1f10 +#define STM32F429_PB15_FUNC_ANALOG 0x1f11 + + + +#define STM32F429_PC0_FUNC_GPIO 0x2000 +#define STM32F429_PC0_FUNC_OTG_HS_ULPI_STP 0x200b +#define STM32F429_PC0_FUNC_FMC_SDNWE 0x200d +#define STM32F429_PC0_FUNC_EVENTOUT 0x2010 +#define STM32F429_PC0_FUNC_ANALOG 0x2011 + +#define STM32F429_PC1_FUNC_GPIO 0x2100 +#define STM32F429_PC1_FUNC_ETH_MDC 0x210c +#define STM32F429_PC1_FUNC_EVENTOUT 0x2110 +#define STM32F429_PC1_FUNC_ANALOG 0x2111 + +#define STM32F429_PC2_FUNC_GPIO 0x2200 +#define STM32F429_PC2_FUNC_SPI2_MISO 0x2206 +#define STM32F429_PC2_FUNC_I2S2EXT_SD 0x2207 +#define STM32F429_PC2_FUNC_OTG_HS_ULPI_DIR 0x220b +#define STM32F429_PC2_FUNC_ETH_MII_TXD2 0x220c +#define STM32F429_PC2_FUNC_FMC_SDNE0 0x220d +#define STM32F429_PC2_FUNC_EVENTOUT 0x2210 +#define STM32F429_PC2_FUNC_ANALOG 0x2211 + +#define STM32F429_PC3_FUNC_GPIO 0x2300 +#define STM32F429_PC3_FUNC_SPI2_MOSI_I2S2_SD 0x2306 +#define STM32F429_PC3_FUNC_OTG_HS_ULPI_NXT 0x230b +#define STM32F429_PC3_FUNC_ETH_MII_TX_CLK 0x230c +#define STM32F429_PC3_FUNC_FMC_SDCKE0 0x230d +#define STM32F429_PC3_FUNC_EVENTOUT 0x2310 +#define STM32F429_PC3_FUNC_ANALOG 0x2311 + +#define STM32F429_PC4_FUNC_GPIO 0x2400 +#define STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0 0x240c +#define STM32F429_PC4_FUNC_EVENTOUT 0x2410 +#define STM32F429_PC4_FUNC_ANALOG 0x2411 + +#define STM32F429_PC5_FUNC_GPIO 0x2500 +#define STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1 0x250c +#define STM32F429_PC5_FUNC_EVENTOUT 0x2510 +#define STM32F429_PC5_FUNC_ANALOG 0x2511 + +#define STM32F429_PC6_FUNC_GPIO 0x2600 +#define STM32F429_PC6_FUNC_TIM3_CH1 0x2603 +#define STM32F429_PC6_FUNC_TIM8_CH1 0x2604 +#define STM32F429_PC6_FUNC_I2S2_MCK 0x2606 +#define STM32F429_PC6_FUNC_USART6_TX 0x2609 +#define STM32F429_PC6_FUNC_SDIO_D6 0x260d +#define STM32F429_PC6_FUNC_DCMI_D0 0x260e +#define STM32F429_PC6_FUNC_LCD_HSYNC 0x260f +#define STM32F429_PC6_FUNC_EVENTOUT 0x2610 +#define STM32F429_PC6_FUNC_ANALOG 0x2611 + +#define STM32F429_PC7_FUNC_GPIO 0x2700 +#define STM32F429_PC7_FUNC_TIM3_CH2 0x2703 +#define STM32F429_PC7_FUNC_TIM8_CH2 0x2704 +#define STM32F429_PC7_FUNC_I2S3_MCK 0x2707 +#define STM32F429_PC7_FUNC_USART6_RX 0x2709 +#define STM32F429_PC7_FUNC_SDIO_D7 0x270d +#define STM32F429_PC7_FUNC_DCMI_D1 0x270e +#define STM32F429_PC7_FUNC_LCD_G6 0x270f +#define STM32F429_PC7_FUNC_EVENTOUT 0x2710 +#define STM32F429_PC7_FUNC_ANALOG 0x2711 + +#define STM32F429_PC8_FUNC_GPIO 0x2800 +#define STM32F429_PC8_FUNC_TIM3_CH3 0x2803 +#define STM32F429_PC8_FUNC_TIM8_CH3 0x2804 +#define STM32F429_PC8_FUNC_USART6_CK 0x2809 +#define STM32F429_PC8_FUNC_SDIO_D0 0x280d +#define STM32F429_PC8_FUNC_DCMI_D2 0x280e +#define STM32F429_PC8_FUNC_EVENTOUT 0x2810 +#define STM32F429_PC8_FUNC_ANALOG 0x2811 + +#define STM32F429_PC9_FUNC_GPIO 0x2900 +#define STM32F429_PC9_FUNC_MCO2 0x2901 +#define STM32F429_PC9_FUNC_TIM3_CH4 0x2903 +#define STM32F429_PC9_FUNC_TIM8_CH4 0x2904 +#define STM32F429_PC9_FUNC_I2C3_SDA 0x2905 +#define STM32F429_PC9_FUNC_I2S_CKIN 0x2906 +#define STM32F429_PC9_FUNC_SDIO_D1 0x290d +#define STM32F429_PC9_FUNC_DCMI_D3 0x290e +#define STM32F429_PC9_FUNC_EVENTOUT 0x2910 +#define STM32F429_PC9_FUNC_ANALOG 0x2911 + +#define STM32F429_PC10_FUNC_GPIO 0x2a00 +#define STM32F429_PC10_FUNC_SPI3_SCK_I2S3_CK 0x2a07 +#define STM32F429_PC10_FUNC_USART3_TX 0x2a08 +#define STM32F429_PC10_FUNC_UART4_TX 0x2a09 +#define STM32F429_PC10_FUNC_SDIO_D2 0x2a0d +#define STM32F429_PC10_FUNC_DCMI_D8 0x2a0e +#define STM32F429_PC10_FUNC_LCD_R2 0x2a0f +#define STM32F429_PC10_FUNC_EVENTOUT 0x2a10 +#define STM32F429_PC10_FUNC_ANALOG 0x2a11 + +#define STM32F429_PC11_FUNC_GPIO 0x2b00 +#define STM32F429_PC11_FUNC_I2S3EXT_SD 0x2b06 +#define STM32F429_PC11_FUNC_SPI3_MISO 0x2b07 +#define STM32F429_PC11_FUNC_USART3_RX 0x2b08 +#define STM32F429_PC11_FUNC_UART4_RX 0x2b09 +#define STM32F429_PC11_FUNC_SDIO_D3 0x2b0d +#define STM32F429_PC11_FUNC_DCMI_D4 0x2b0e +#define STM32F429_PC11_FUNC_EVENTOUT 0x2b10 +#define STM32F429_PC11_FUNC_ANALOG 0x2b11 + +#define STM32F429_PC12_FUNC_GPIO 0x2c00 +#define STM32F429_PC12_FUNC_SPI3_MOSI_I2S3_SD 0x2c07 +#define STM32F429_PC12_FUNC_USART3_CK 0x2c08 +#define STM32F429_PC12_FUNC_UART5_TX 0x2c09 +#define STM32F429_PC12_FUNC_SDIO_CK 0x2c0d +#define STM32F429_PC12_FUNC_DCMI_D9 0x2c0e +#define STM32F429_PC12_FUNC_EVENTOUT 0x2c10 +#define STM32F429_PC12_FUNC_ANALOG 0x2c11 + +#define STM32F429_PC13_FUNC_GPIO 0x2d00 +#define STM32F429_PC13_FUNC_EVENTOUT 0x2d10 +#define STM32F429_PC13_FUNC_ANALOG 0x2d11 + +#define STM32F429_PC14_FUNC_GPIO 0x2e00 +#define STM32F429_PC14_FUNC_EVENTOUT 0x2e10 +#define STM32F429_PC14_FUNC_ANALOG 0x2e11 + +#define STM32F429_PC15_FUNC_GPIO 0x2f00 +#define STM32F429_PC15_FUNC_EVENTOUT 0x2f10 +#define STM32F429_PC15_FUNC_ANALOG 0x2f11 + + + +#define STM32F429_PD0_FUNC_GPIO 0x3000 +#define STM32F429_PD0_FUNC_CAN1_RX 0x300a +#define STM32F429_PD0_FUNC_FMC_D2 0x300d +#define STM32F429_PD0_FUNC_EVENTOUT 0x3010 +#define STM32F429_PD0_FUNC_ANALOG 0x3011 + +#define STM32F429_PD1_FUNC_GPIO 0x3100 +#define STM32F429_PD1_FUNC_CAN1_TX 0x310a +#define STM32F429_PD1_FUNC_FMC_D3 0x310d +#define STM32F429_PD1_FUNC_EVENTOUT 0x3110 +#define STM32F429_PD1_FUNC_ANALOG 0x3111 + +#define STM32F429_PD2_FUNC_GPIO 0x3200 +#define STM32F429_PD2_FUNC_TIM3_ETR 0x3203 +#define STM32F429_PD2_FUNC_UART5_RX 0x3209 +#define STM32F429_PD2_FUNC_SDIO_CMD 0x320d +#define STM32F429_PD2_FUNC_DCMI_D11 0x320e +#define STM32F429_PD2_FUNC_EVENTOUT 0x3210 +#define STM32F429_PD2_FUNC_ANALOG 0x3211 + +#define STM32F429_PD3_FUNC_GPIO 0x3300 +#define STM32F429_PD3_FUNC_SPI2_SCK_I2S2_CK 0x3306 +#define STM32F429_PD3_FUNC_USART2_CTS 0x3308 +#define STM32F429_PD3_FUNC_FMC_CLK 0x330d +#define STM32F429_PD3_FUNC_DCMI_D5 0x330e +#define STM32F429_PD3_FUNC_LCD_G7 0x330f +#define STM32F429_PD3_FUNC_EVENTOUT 0x3310 +#define STM32F429_PD3_FUNC_ANALOG 0x3311 + +#define STM32F429_PD4_FUNC_GPIO 0x3400 +#define STM32F429_PD4_FUNC_USART2_RTS 0x3408 +#define STM32F429_PD4_FUNC_FMC_NOE 0x340d +#define STM32F429_PD4_FUNC_EVENTOUT 0x3410 +#define STM32F429_PD4_FUNC_ANALOG 0x3411 + +#define STM32F429_PD5_FUNC_GPIO 0x3500 +#define STM32F429_PD5_FUNC_USART2_TX 0x3508 +#define STM32F429_PD5_FUNC_FMC_NWE 0x350d +#define STM32F429_PD5_FUNC_EVENTOUT 0x3510 +#define STM32F429_PD5_FUNC_ANALOG 0x3511 + +#define STM32F429_PD6_FUNC_GPIO 0x3600 +#define STM32F429_PD6_FUNC_SPI3_MOSI_I2S3_SD 0x3606 +#define STM32F429_PD6_FUNC_SAI1_SD_A 0x3607 +#define STM32F429_PD6_FUNC_USART2_RX 0x3608 +#define STM32F429_PD6_FUNC_FMC_NWAIT 0x360d +#define STM32F429_PD6_FUNC_DCMI_D10 0x360e +#define STM32F429_PD6_FUNC_LCD_B2 0x360f +#define STM32F429_PD6_FUNC_EVENTOUT 0x3610 +#define STM32F429_PD6_FUNC_ANALOG 0x3611 + +#define STM32F429_PD7_FUNC_GPIO 0x3700 +#define STM32F429_PD7_FUNC_USART2_CK 0x3708 +#define STM32F429_PD7_FUNC_FMC_NE1_FMC_NCE2 0x370d +#define STM32F429_PD7_FUNC_EVENTOUT 0x3710 +#define STM32F429_PD7_FUNC_ANALOG 0x3711 + +#define STM32F429_PD8_FUNC_GPIO 0x3800 +#define STM32F429_PD8_FUNC_USART3_TX 0x3808 +#define STM32F429_PD8_FUNC_FMC_D13 0x380d +#define STM32F429_PD8_FUNC_EVENTOUT 0x3810 +#define STM32F429_PD8_FUNC_ANALOG 0x3811 + +#define STM32F429_PD9_FUNC_GPIO 0x3900 +#define STM32F429_PD9_FUNC_USART3_RX 0x3908 +#define STM32F429_PD9_FUNC_FMC_D14 0x390d +#define STM32F429_PD9_FUNC_EVENTOUT 0x3910 +#define STM32F429_PD9_FUNC_ANALOG 0x3911 + +#define STM32F429_PD10_FUNC_GPIO 0x3a00 +#define STM32F429_PD10_FUNC_USART3_CK 0x3a08 +#define STM32F429_PD10_FUNC_FMC_D15 0x3a0d +#define STM32F429_PD10_FUNC_LCD_B3 0x3a0f +#define STM32F429_PD10_FUNC_EVENTOUT 0x3a10 +#define STM32F429_PD10_FUNC_ANALOG 0x3a11 + +#define STM32F429_PD11_FUNC_GPIO 0x3b00 +#define STM32F429_PD11_FUNC_USART3_CTS 0x3b08 +#define STM32F429_PD11_FUNC_FMC_A16 0x3b0d +#define STM32F429_PD11_FUNC_EVENTOUT 0x3b10 +#define STM32F429_PD11_FUNC_ANALOG 0x3b11 + +#define STM32F429_PD12_FUNC_GPIO 0x3c00 +#define STM32F429_PD12_FUNC_TIM4_CH1 0x3c03 +#define STM32F429_PD12_FUNC_USART3_RTS 0x3c08 +#define STM32F429_PD12_FUNC_FMC_A17 0x3c0d +#define STM32F429_PD12_FUNC_EVENTOUT 0x3c10 +#define STM32F429_PD12_FUNC_ANALOG 0x3c11 + +#define STM32F429_PD13_FUNC_GPIO 0x3d00 +#define STM32F429_PD13_FUNC_TIM4_CH2 0x3d03 +#define STM32F429_PD13_FUNC_FMC_A18 0x3d0d +#define STM32F429_PD13_FUNC_EVENTOUT 0x3d10 +#define STM32F429_PD13_FUNC_ANALOG 0x3d11 + +#define STM32F429_PD14_FUNC_GPIO 0x3e00 +#define STM32F429_PD14_FUNC_TIM4_CH3 0x3e03 +#define STM32F429_PD14_FUNC_FMC_D0 0x3e0d +#define STM32F429_PD14_FUNC_EVENTOUT 0x3e10 +#define STM32F429_PD14_FUNC_ANALOG 0x3e11 + +#define STM32F429_PD15_FUNC_GPIO 0x3f00 +#define STM32F429_PD15_FUNC_TIM4_CH4 0x3f03 +#define STM32F429_PD15_FUNC_FMC_D1 0x3f0d +#define STM32F429_PD15_FUNC_EVENTOUT 0x3f10 +#define STM32F429_PD15_FUNC_ANALOG 0x3f11 + + + +#define STM32F429_PE0_FUNC_GPIO 0x4000 +#define STM32F429_PE0_FUNC_TIM4_ETR 0x4003 +#define STM32F429_PE0_FUNC_UART8_RX 0x4009 +#define STM32F429_PE0_FUNC_FMC_NBL0 0x400d +#define STM32F429_PE0_FUNC_DCMI_D2 0x400e +#define STM32F429_PE0_FUNC_EVENTOUT 0x4010 +#define STM32F429_PE0_FUNC_ANALOG 0x4011 + +#define STM32F429_PE1_FUNC_GPIO 0x4100 +#define STM32F429_PE1_FUNC_UART8_TX 0x4109 +#define STM32F429_PE1_FUNC_FMC_NBL1 0x410d +#define STM32F429_PE1_FUNC_DCMI_D3 0x410e +#define STM32F429_PE1_FUNC_EVENTOUT 0x4110 +#define STM32F429_PE1_FUNC_ANALOG 0x4111 + +#define STM32F429_PE2_FUNC_GPIO 0x4200 +#define STM32F429_PE2_FUNC_TRACECLK 0x4201 +#define STM32F429_PE2_FUNC_SPI4_SCK 0x4206 +#define STM32F429_PE2_FUNC_SAI1_MCLK_A 0x4207 +#define STM32F429_PE2_FUNC_ETH_MII_TXD3 0x420c +#define STM32F429_PE2_FUNC_FMC_A23 0x420d +#define STM32F429_PE2_FUNC_EVENTOUT 0x4210 +#define STM32F429_PE2_FUNC_ANALOG 0x4211 + +#define STM32F429_PE3_FUNC_GPIO 0x4300 +#define STM32F429_PE3_FUNC_TRACED0 0x4301 +#define STM32F429_PE3_FUNC_SAI1_SD_B 0x4307 +#define STM32F429_PE3_FUNC_FMC_A19 0x430d +#define STM32F429_PE3_FUNC_EVENTOUT 0x4310 +#define STM32F429_PE3_FUNC_ANALOG 0x4311 + +#define STM32F429_PE4_FUNC_GPIO 0x4400 +#define STM32F429_PE4_FUNC_TRACED1 0x4401 +#define STM32F429_PE4_FUNC_SPI4_NSS 0x4406 +#define STM32F429_PE4_FUNC_SAI1_FS_A 0x4407 +#define STM32F429_PE4_FUNC_FMC_A20 0x440d +#define STM32F429_PE4_FUNC_DCMI_D4 0x440e +#define STM32F429_PE4_FUNC_LCD_B0 0x440f +#define STM32F429_PE4_FUNC_EVENTOUT 0x4410 +#define STM32F429_PE4_FUNC_ANALOG 0x4411 + +#define STM32F429_PE5_FUNC_GPIO 0x4500 +#define STM32F429_PE5_FUNC_TRACED2 0x4501 +#define STM32F429_PE5_FUNC_TIM9_CH1 0x4504 +#define STM32F429_PE5_FUNC_SPI4_MISO 0x4506 +#define STM32F429_PE5_FUNC_SAI1_SCK_A 0x4507 +#define STM32F429_PE5_FUNC_FMC_A21 0x450d +#define STM32F429_PE5_FUNC_DCMI_D6 0x450e +#define STM32F429_PE5_FUNC_LCD_G0 0x450f +#define STM32F429_PE5_FUNC_EVENTOUT 0x4510 +#define STM32F429_PE5_FUNC_ANALOG 0x4511 + +#define STM32F429_PE6_FUNC_GPIO 0x4600 +#define STM32F429_PE6_FUNC_TRACED3 0x4601 +#define STM32F429_PE6_FUNC_TIM9_CH2 0x4604 +#define STM32F429_PE6_FUNC_SPI4_MOSI 0x4606 +#define STM32F429_PE6_FUNC_SAI1_SD_A 0x4607 +#define STM32F429_PE6_FUNC_FMC_A22 0x460d +#define STM32F429_PE6_FUNC_DCMI_D7 0x460e +#define STM32F429_PE6_FUNC_LCD_G1 0x460f +#define STM32F429_PE6_FUNC_EVENTOUT 0x4610 +#define STM32F429_PE6_FUNC_ANALOG 0x4611 + +#define STM32F429_PE7_FUNC_GPIO 0x4700 +#define STM32F429_PE7_FUNC_TIM1_ETR 0x4702 +#define STM32F429_PE7_FUNC_UART7_RX 0x4709 +#define STM32F429_PE7_FUNC_FMC_D4 0x470d +#define STM32F429_PE7_FUNC_EVENTOUT 0x4710 +#define STM32F429_PE7_FUNC_ANALOG 0x4711 + +#define STM32F429_PE8_FUNC_GPIO 0x4800 +#define STM32F429_PE8_FUNC_TIM1_CH1N 0x4802 +#define STM32F429_PE8_FUNC_UART7_TX 0x4809 +#define STM32F429_PE8_FUNC_FMC_D5 0x480d +#define STM32F429_PE8_FUNC_EVENTOUT 0x4810 +#define STM32F429_PE8_FUNC_ANALOG 0x4811 + +#define STM32F429_PE9_FUNC_GPIO 0x4900 +#define STM32F429_PE9_FUNC_TIM1_CH1 0x4902 +#define STM32F429_PE9_FUNC_FMC_D6 0x490d +#define STM32F429_PE9_FUNC_EVENTOUT 0x4910 +#define STM32F429_PE9_FUNC_ANALOG 0x4911 + +#define STM32F429_PE10_FUNC_GPIO 0x4a00 +#define STM32F429_PE10_FUNC_TIM1_CH2N 0x4a02 +#define STM32F429_PE10_FUNC_FMC_D7 0x4a0d +#define STM32F429_PE10_FUNC_EVENTOUT 0x4a10 +#define STM32F429_PE10_FUNC_ANALOG 0x4a11 + +#define STM32F429_PE11_FUNC_GPIO 0x4b00 +#define STM32F429_PE11_FUNC_TIM1_CH2 0x4b02 +#define STM32F429_PE11_FUNC_SPI4_NSS 0x4b06 +#define STM32F429_PE11_FUNC_FMC_D8 0x4b0d +#define STM32F429_PE11_FUNC_LCD_G3 0x4b0f +#define STM32F429_PE11_FUNC_EVENTOUT 0x4b10 +#define STM32F429_PE11_FUNC_ANALOG 0x4b11 + +#define STM32F429_PE12_FUNC_GPIO 0x4c00 +#define STM32F429_PE12_FUNC_TIM1_CH3N 0x4c02 +#define STM32F429_PE12_FUNC_SPI4_SCK 0x4c06 +#define STM32F429_PE12_FUNC_FMC_D9 0x4c0d +#define STM32F429_PE12_FUNC_LCD_B4 0x4c0f +#define STM32F429_PE12_FUNC_EVENTOUT 0x4c10 +#define STM32F429_PE12_FUNC_ANALOG 0x4c11 + +#define STM32F429_PE13_FUNC_GPIO 0x4d00 +#define STM32F429_PE13_FUNC_TIM1_CH3 0x4d02 +#define STM32F429_PE13_FUNC_SPI4_MISO 0x4d06 +#define STM32F429_PE13_FUNC_FMC_D10 0x4d0d +#define STM32F429_PE13_FUNC_LCD_DE 0x4d0f +#define STM32F429_PE13_FUNC_EVENTOUT 0x4d10 +#define STM32F429_PE13_FUNC_ANALOG 0x4d11 + +#define STM32F429_PE14_FUNC_GPIO 0x4e00 +#define STM32F429_PE14_FUNC_TIM1_CH4 0x4e02 +#define STM32F429_PE14_FUNC_SPI4_MOSI 0x4e06 +#define STM32F429_PE14_FUNC_FMC_D11 0x4e0d +#define STM32F429_PE14_FUNC_LCD_CLK 0x4e0f +#define STM32F429_PE14_FUNC_EVENTOUT 0x4e10 +#define STM32F429_PE14_FUNC_ANALOG 0x4e11 + +#define STM32F429_PE15_FUNC_GPIO 0x4f00 +#define STM32F429_PE15_FUNC_TIM1_BKIN 0x4f02 +#define STM32F429_PE15_FUNC_FMC_D12 0x4f0d +#define STM32F429_PE15_FUNC_LCD_R7 0x4f0f +#define STM32F429_PE15_FUNC_EVENTOUT 0x4f10 +#define STM32F429_PE15_FUNC_ANALOG 0x4f11 + + + +#define STM32F429_PF0_FUNC_GPIO 0x5000 +#define STM32F429_PF0_FUNC_I2C2_SDA 0x5005 +#define STM32F429_PF0_FUNC_FMC_A0 0x500d +#define STM32F429_PF0_FUNC_EVENTOUT 0x5010 +#define STM32F429_PF0_FUNC_ANALOG 0x5011 + +#define STM32F429_PF1_FUNC_GPIO 0x5100 +#define STM32F429_PF1_FUNC_I2C2_SCL 0x5105 +#define STM32F429_PF1_FUNC_FMC_A1 0x510d +#define STM32F429_PF1_FUNC_EVENTOUT 0x5110 +#define STM32F429_PF1_FUNC_ANALOG 0x5111 + +#define STM32F429_PF2_FUNC_GPIO 0x5200 +#define STM32F429_PF2_FUNC_I2C2_SMBA 0x5205 +#define STM32F429_PF2_FUNC_FMC_A2 0x520d +#define STM32F429_PF2_FUNC_EVENTOUT 0x5210 +#define STM32F429_PF2_FUNC_ANALOG 0x5211 + +#define STM32F429_PF3_FUNC_GPIO 0x5300 +#define STM32F429_PF3_FUNC_FMC_A3 0x530d +#define STM32F429_PF3_FUNC_EVENTOUT 0x5310 +#define STM32F429_PF3_FUNC_ANALOG 0x5311 + +#define STM32F429_PF4_FUNC_GPIO 0x5400 +#define STM32F429_PF4_FUNC_FMC_A4 0x540d +#define STM32F429_PF4_FUNC_EVENTOUT 0x5410 +#define STM32F429_PF4_FUNC_ANALOG 0x5411 + +#define STM32F429_PF5_FUNC_GPIO 0x5500 +#define STM32F429_PF5_FUNC_FMC_A5 0x550d +#define STM32F429_PF5_FUNC_EVENTOUT 0x5510 +#define STM32F429_PF5_FUNC_ANALOG 0x5511 + +#define STM32F429_PF6_FUNC_GPIO 0x5600 +#define STM32F429_PF6_FUNC_TIM10_CH1 0x5604 +#define STM32F429_PF6_FUNC_SPI5_NSS 0x5606 +#define STM32F429_PF6_FUNC_SAI1_SD_B 0x5607 +#define STM32F429_PF6_FUNC_UART7_RX 0x5609 +#define STM32F429_PF6_FUNC_FMC_NIORD 0x560d +#define STM32F429_PF6_FUNC_EVENTOUT 0x5610 +#define STM32F429_PF6_FUNC_ANALOG 0x5611 + +#define STM32F429_PF7_FUNC_GPIO 0x5700 +#define STM32F429_PF7_FUNC_TIM11_CH1 0x5704 +#define STM32F429_PF7_FUNC_SPI5_SCK 0x5706 +#define STM32F429_PF7_FUNC_SAI1_MCLK_B 0x5707 +#define STM32F429_PF7_FUNC_UART7_TX 0x5709 +#define STM32F429_PF7_FUNC_FMC_NREG 0x570d +#define STM32F429_PF7_FUNC_EVENTOUT 0x5710 +#define STM32F429_PF7_FUNC_ANALOG 0x5711 + +#define STM32F429_PF8_FUNC_GPIO 0x5800 +#define STM32F429_PF8_FUNC_SPI5_MISO 0x5806 +#define STM32F429_PF8_FUNC_SAI1_SCK_B 0x5807 +#define STM32F429_PF8_FUNC_TIM13_CH1 0x580a +#define STM32F429_PF8_FUNC_FMC_NIOWR 0x580d +#define STM32F429_PF8_FUNC_EVENTOUT 0x5810 +#define STM32F429_PF8_FUNC_ANALOG 0x5811 + +#define STM32F429_PF9_FUNC_GPIO 0x5900 +#define STM32F429_PF9_FUNC_SPI5_MOSI 0x5906 +#define STM32F429_PF9_FUNC_SAI1_FS_B 0x5907 +#define STM32F429_PF9_FUNC_TIM14_CH1 0x590a +#define STM32F429_PF9_FUNC_FMC_CD 0x590d +#define STM32F429_PF9_FUNC_EVENTOUT 0x5910 +#define STM32F429_PF9_FUNC_ANALOG 0x5911 + +#define STM32F429_PF10_FUNC_GPIO 0x5a00 +#define STM32F429_PF10_FUNC_FMC_INTR 0x5a0d +#define STM32F429_PF10_FUNC_DCMI_D11 0x5a0e +#define STM32F429_PF10_FUNC_LCD_DE 0x5a0f +#define STM32F429_PF10_FUNC_EVENTOUT 0x5a10 +#define STM32F429_PF10_FUNC_ANALOG 0x5a11 + +#define STM32F429_PF11_FUNC_GPIO 0x5b00 +#define STM32F429_PF11_FUNC_SPI5_MOSI 0x5b06 +#define STM32F429_PF11_FUNC_FMC_SDNRAS 0x5b0d +#define STM32F429_PF11_FUNC_DCMI_D12 0x5b0e +#define STM32F429_PF11_FUNC_EVENTOUT 0x5b10 +#define STM32F429_PF11_FUNC_ANALOG 0x5b11 + +#define STM32F429_PF12_FUNC_GPIO 0x5c00 +#define STM32F429_PF12_FUNC_FMC_A6 0x5c0d +#define STM32F429_PF12_FUNC_EVENTOUT 0x5c10 +#define STM32F429_PF12_FUNC_ANALOG 0x5c11 + +#define STM32F429_PF13_FUNC_GPIO 0x5d00 +#define STM32F429_PF13_FUNC_FMC_A7 0x5d0d +#define STM32F429_PF13_FUNC_EVENTOUT 0x5d10 +#define STM32F429_PF13_FUNC_ANALOG 0x5d11 + +#define STM32F429_PF14_FUNC_GPIO 0x5e00 +#define STM32F429_PF14_FUNC_FMC_A8 0x5e0d +#define STM32F429_PF14_FUNC_EVENTOUT 0x5e10 +#define STM32F429_PF14_FUNC_ANALOG 0x5e11 + +#define STM32F429_PF15_FUNC_GPIO 0x5f00 +#define STM32F429_PF15_FUNC_FMC_A9 0x5f0d +#define STM32F429_PF15_FUNC_EVENTOUT 0x5f10 +#define STM32F429_PF15_FUNC_ANALOG 0x5f11 + + + +#define STM32F429_PG0_FUNC_GPIO 0x6000 +#define STM32F429_PG0_FUNC_FMC_A10 0x600d +#define STM32F429_PG0_FUNC_EVENTOUT 0x6010 +#define STM32F429_PG0_FUNC_ANALOG 0x6011 + +#define STM32F429_PG1_FUNC_GPIO 0x6100 +#define STM32F429_PG1_FUNC_FMC_A11 0x610d +#define STM32F429_PG1_FUNC_EVENTOUT 0x6110 +#define STM32F429_PG1_FUNC_ANALOG 0x6111 + +#define STM32F429_PG2_FUNC_GPIO 0x6200 +#define STM32F429_PG2_FUNC_FMC_A12 0x620d +#define STM32F429_PG2_FUNC_EVENTOUT 0x6210 +#define STM32F429_PG2_FUNC_ANALOG 0x6211 + +#define STM32F429_PG3_FUNC_GPIO 0x6300 +#define STM32F429_PG3_FUNC_FMC_A13 0x630d +#define STM32F429_PG3_FUNC_EVENTOUT 0x6310 +#define STM32F429_PG3_FUNC_ANALOG 0x6311 + +#define STM32F429_PG4_FUNC_GPIO 0x6400 +#define STM32F429_PG4_FUNC_FMC_A14_FMC_BA0 0x640d +#define STM32F429_PG4_FUNC_EVENTOUT 0x6410 +#define STM32F429_PG4_FUNC_ANALOG 0x6411 + +#define STM32F429_PG5_FUNC_GPIO 0x6500 +#define STM32F429_PG5_FUNC_FMC_A15_FMC_BA1 0x650d +#define STM32F429_PG5_FUNC_EVENTOUT 0x6510 +#define STM32F429_PG5_FUNC_ANALOG 0x6511 + +#define STM32F429_PG6_FUNC_GPIO 0x6600 +#define STM32F429_PG6_FUNC_FMC_INT2 0x660d +#define STM32F429_PG6_FUNC_DCMI_D12 0x660e +#define STM32F429_PG6_FUNC_LCD_R7 0x660f +#define STM32F429_PG6_FUNC_EVENTOUT 0x6610 +#define STM32F429_PG6_FUNC_ANALOG 0x6611 + +#define STM32F429_PG7_FUNC_GPIO 0x6700 +#define STM32F429_PG7_FUNC_USART6_CK 0x6709 +#define STM32F429_PG7_FUNC_FMC_INT3 0x670d +#define STM32F429_PG7_FUNC_DCMI_D13 0x670e +#define STM32F429_PG7_FUNC_LCD_CLK 0x670f +#define STM32F429_PG7_FUNC_EVENTOUT 0x6710 +#define STM32F429_PG7_FUNC_ANALOG 0x6711 + +#define STM32F429_PG8_FUNC_GPIO 0x6800 +#define STM32F429_PG8_FUNC_SPI6_NSS 0x6806 +#define STM32F429_PG8_FUNC_USART6_RTS 0x6809 +#define STM32F429_PG8_FUNC_ETH_PPS_OUT 0x680c +#define STM32F429_PG8_FUNC_FMC_SDCLK 0x680d +#define STM32F429_PG8_FUNC_EVENTOUT 0x6810 +#define STM32F429_PG8_FUNC_ANALOG 0x6811 + +#define STM32F429_PG9_FUNC_GPIO 0x6900 +#define STM32F429_PG9_FUNC_USART6_RX 0x6909 +#define STM32F429_PG9_FUNC_FMC_NE2_FMC_NCE3 0x690d +#define STM32F429_PG9_FUNC_DCMI_VSYNC 0x690e +#define STM32F429_PG9_FUNC_EVENTOUT 0x6910 +#define STM32F429_PG9_FUNC_ANALOG 0x6911 + +#define STM32F429_PG10_FUNC_GPIO 0x6a00 +#define STM32F429_PG10_FUNC_LCD_G3 0x6a0a +#define STM32F429_PG10_FUNC_FMC_NCE4_1_FMC_NE3 0x6a0d +#define STM32F429_PG10_FUNC_DCMI_D2 0x6a0e +#define STM32F429_PG10_FUNC_LCD_B2 0x6a0f +#define STM32F429_PG10_FUNC_EVENTOUT 0x6a10 +#define STM32F429_PG10_FUNC_ANALOG 0x6a11 + +#define STM32F429_PG11_FUNC_GPIO 0x6b00 +#define STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x6b0c +#define STM32F429_PG11_FUNC_FMC_NCE4_2 0x6b0d +#define STM32F429_PG11_FUNC_DCMI_D3 0x6b0e +#define STM32F429_PG11_FUNC_LCD_B3 0x6b0f +#define STM32F429_PG11_FUNC_EVENTOUT 0x6b10 +#define STM32F429_PG11_FUNC_ANALOG 0x6b11 + +#define STM32F429_PG12_FUNC_GPIO 0x6c00 +#define STM32F429_PG12_FUNC_SPI6_MISO 0x6c06 +#define STM32F429_PG12_FUNC_USART6_RTS 0x6c09 +#define STM32F429_PG12_FUNC_LCD_B4 0x6c0a +#define STM32F429_PG12_FUNC_FMC_NE4 0x6c0d +#define STM32F429_PG12_FUNC_LCD_B1 0x6c0f +#define STM32F429_PG12_FUNC_EVENTOUT 0x6c10 +#define STM32F429_PG12_FUNC_ANALOG 0x6c11 + +#define STM32F429_PG13_FUNC_GPIO 0x6d00 +#define STM32F429_PG13_FUNC_SPI6_SCK 0x6d06 +#define STM32F429_PG13_FUNC_USART6_CTS 0x6d09 +#define STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x6d0c +#define STM32F429_PG13_FUNC_FMC_A24 0x6d0d +#define STM32F429_PG13_FUNC_EVENTOUT 0x6d10 +#define STM32F429_PG13_FUNC_ANALOG 0x6d11 + +#define STM32F429_PG14_FUNC_GPIO 0x6e00 +#define STM32F429_PG14_FUNC_SPI6_MOSI 0x6e06 +#define STM32F429_PG14_FUNC_USART6_TX 0x6e09 +#define STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x6e0c +#define STM32F429_PG14_FUNC_FMC_A25 0x6e0d +#define STM32F429_PG14_FUNC_EVENTOUT 0x6e10 +#define STM32F429_PG14_FUNC_ANALOG 0x6e11 + +#define STM32F429_PG15_FUNC_GPIO 0x6f00 +#define STM32F429_PG15_FUNC_USART6_CTS 0x6f09 +#define STM32F429_PG15_FUNC_FMC_SDNCAS 0x6f0d +#define STM32F429_PG15_FUNC_DCMI_D13 0x6f0e +#define STM32F429_PG15_FUNC_EVENTOUT 0x6f10 +#define STM32F429_PG15_FUNC_ANALOG 0x6f11 + + + +#define STM32F429_PH0_FUNC_GPIO 0x7000 +#define STM32F429_PH0_FUNC_EVENTOUT 0x7010 +#define STM32F429_PH0_FUNC_ANALOG 0x7011 + +#define STM32F429_PH1_FUNC_GPIO 0x7100 +#define STM32F429_PH1_FUNC_EVENTOUT 0x7110 +#define STM32F429_PH1_FUNC_ANALOG 0x7111 + +#define STM32F429_PH2_FUNC_GPIO 0x7200 +#define STM32F429_PH2_FUNC_ETH_MII_CRS 0x720c +#define STM32F429_PH2_FUNC_FMC_SDCKE0 0x720d +#define STM32F429_PH2_FUNC_LCD_R0 0x720f +#define STM32F429_PH2_FUNC_EVENTOUT 0x7210 +#define STM32F429_PH2_FUNC_ANALOG 0x7211 + +#define STM32F429_PH3_FUNC_GPIO 0x7300 +#define STM32F429_PH3_FUNC_ETH_MII_COL 0x730c +#define STM32F429_PH3_FUNC_FMC_SDNE0 0x730d +#define STM32F429_PH3_FUNC_LCD_R1 0x730f +#define STM32F429_PH3_FUNC_EVENTOUT 0x7310 +#define STM32F429_PH3_FUNC_ANALOG 0x7311 + +#define STM32F429_PH4_FUNC_GPIO 0x7400 +#define STM32F429_PH4_FUNC_I2C2_SCL 0x7405 +#define STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT 0x740b +#define STM32F429_PH4_FUNC_EVENTOUT 0x7410 +#define STM32F429_PH4_FUNC_ANALOG 0x7411 + +#define STM32F429_PH5_FUNC_GPIO 0x7500 +#define STM32F429_PH5_FUNC_I2C2_SDA 0x7505 +#define STM32F429_PH5_FUNC_SPI5_NSS 0x7506 +#define STM32F429_PH5_FUNC_FMC_SDNWE 0x750d +#define STM32F429_PH5_FUNC_EVENTOUT 0x7510 +#define STM32F429_PH5_FUNC_ANALOG 0x7511 + +#define STM32F429_PH6_FUNC_GPIO 0x7600 +#define STM32F429_PH6_FUNC_I2C2_SMBA 0x7605 +#define STM32F429_PH6_FUNC_SPI5_SCK 0x7606 +#define STM32F429_PH6_FUNC_TIM12_CH1 0x760a +#define STM32F429_PH6_FUNC_ETH_MII_RXD2 0x760c +#define STM32F429_PH6_FUNC_FMC_SDNE1 0x760d +#define STM32F429_PH6_FUNC_DCMI_D8 0x760e +#define STM32F429_PH6_FUNC_EVENTOUT 0x7610 +#define STM32F429_PH6_FUNC_ANALOG 0x7611 + +#define STM32F429_PH7_FUNC_GPIO 0x7700 +#define STM32F429_PH7_FUNC_I2C3_SCL 0x7705 +#define STM32F429_PH7_FUNC_SPI5_MISO 0x7706 +#define STM32F429_PH7_FUNC_ETH_MII_RXD3 0x770c +#define STM32F429_PH7_FUNC_FMC_SDCKE1 0x770d +#define STM32F429_PH7_FUNC_DCMI_D9 0x770e +#define STM32F429_PH7_FUNC_EVENTOUT 0x7710 +#define STM32F429_PH7_FUNC_ANALOG 0x7711 + +#define STM32F429_PH8_FUNC_GPIO 0x7800 +#define STM32F429_PH8_FUNC_I2C3_SDA 0x7805 +#define STM32F429_PH8_FUNC_FMC_D16 0x780d +#define STM32F429_PH8_FUNC_DCMI_HSYNC 0x780e +#define STM32F429_PH8_FUNC_LCD_R2 0x780f +#define STM32F429_PH8_FUNC_EVENTOUT 0x7810 +#define STM32F429_PH8_FUNC_ANALOG 0x7811 + +#define STM32F429_PH9_FUNC_GPIO 0x7900 +#define STM32F429_PH9_FUNC_I2C3_SMBA 0x7905 +#define STM32F429_PH9_FUNC_TIM12_CH2 0x790a +#define STM32F429_PH9_FUNC_FMC_D17 0x790d +#define STM32F429_PH9_FUNC_DCMI_D0 0x790e +#define STM32F429_PH9_FUNC_LCD_R3 0x790f +#define STM32F429_PH9_FUNC_EVENTOUT 0x7910 +#define STM32F429_PH9_FUNC_ANALOG 0x7911 + +#define STM32F429_PH10_FUNC_GPIO 0x7a00 +#define STM32F429_PH10_FUNC_TIM5_CH1 0x7a03 +#define STM32F429_PH10_FUNC_FMC_D18 0x7a0d +#define STM32F429_PH10_FUNC_DCMI_D1 0x7a0e +#define STM32F429_PH10_FUNC_LCD_R4 0x7a0f +#define STM32F429_PH10_FUNC_EVENTOUT 0x7a10 +#define STM32F429_PH10_FUNC_ANALOG 0x7a11 + +#define STM32F429_PH11_FUNC_GPIO 0x7b00 +#define STM32F429_PH11_FUNC_TIM5_CH2 0x7b03 +#define STM32F429_PH11_FUNC_FMC_D19 0x7b0d +#define STM32F429_PH11_FUNC_DCMI_D2 0x7b0e +#define STM32F429_PH11_FUNC_LCD_R5 0x7b0f +#define STM32F429_PH11_FUNC_EVENTOUT 0x7b10 +#define STM32F429_PH11_FUNC_ANALOG 0x7b11 + +#define STM32F429_PH12_FUNC_GPIO 0x7c00 +#define STM32F429_PH12_FUNC_TIM5_CH3 0x7c03 +#define STM32F429_PH12_FUNC_FMC_D20 0x7c0d +#define STM32F429_PH12_FUNC_DCMI_D3 0x7c0e +#define STM32F429_PH12_FUNC_LCD_R6 0x7c0f +#define STM32F429_PH12_FUNC_EVENTOUT 0x7c10 +#define STM32F429_PH12_FUNC_ANALOG 0x7c11 + +#define STM32F429_PH13_FUNC_GPIO 0x7d00 +#define STM32F429_PH13_FUNC_TIM8_CH1N 0x7d04 +#define STM32F429_PH13_FUNC_CAN1_TX 0x7d0a +#define STM32F429_PH13_FUNC_FMC_D21 0x7d0d +#define STM32F429_PH13_FUNC_LCD_G2 0x7d0f +#define STM32F429_PH13_FUNC_EVENTOUT 0x7d10 +#define STM32F429_PH13_FUNC_ANALOG 0x7d11 + +#define STM32F429_PH14_FUNC_GPIO 0x7e00 +#define STM32F429_PH14_FUNC_TIM8_CH2N 0x7e04 +#define STM32F429_PH14_FUNC_FMC_D22 0x7e0d +#define STM32F429_PH14_FUNC_DCMI_D4 0x7e0e +#define STM32F429_PH14_FUNC_LCD_G3 0x7e0f +#define STM32F429_PH14_FUNC_EVENTOUT 0x7e10 +#define STM32F429_PH14_FUNC_ANALOG 0x7e11 + +#define STM32F429_PH15_FUNC_GPIO 0x7f00 +#define STM32F429_PH15_FUNC_TIM8_CH3N 0x7f04 +#define STM32F429_PH15_FUNC_FMC_D23 0x7f0d +#define STM32F429_PH15_FUNC_DCMI_D11 0x7f0e +#define STM32F429_PH15_FUNC_LCD_G4 0x7f0f +#define STM32F429_PH15_FUNC_EVENTOUT 0x7f10 +#define STM32F429_PH15_FUNC_ANALOG 0x7f11 + + + +#define STM32F429_PI0_FUNC_GPIO 0x8000 +#define STM32F429_PI0_FUNC_TIM5_CH4 0x8003 +#define STM32F429_PI0_FUNC_SPI2_NSS_I2S2_WS 0x8006 +#define STM32F429_PI0_FUNC_FMC_D24 0x800d +#define STM32F429_PI0_FUNC_DCMI_D13 0x800e +#define STM32F429_PI0_FUNC_LCD_G5 0x800f +#define STM32F429_PI0_FUNC_EVENTOUT 0x8010 +#define STM32F429_PI0_FUNC_ANALOG 0x8011 + +#define STM32F429_PI1_FUNC_GPIO 0x8100 +#define STM32F429_PI1_FUNC_SPI2_SCK_I2S2_CK 0x8106 +#define STM32F429_PI1_FUNC_FMC_D25 0x810d +#define STM32F429_PI1_FUNC_DCMI_D8 0x810e +#define STM32F429_PI1_FUNC_LCD_G6 0x810f +#define STM32F429_PI1_FUNC_EVENTOUT 0x8110 +#define STM32F429_PI1_FUNC_ANALOG 0x8111 + +#define STM32F429_PI2_FUNC_GPIO 0x8200 +#define STM32F429_PI2_FUNC_TIM8_CH4 0x8204 +#define STM32F429_PI2_FUNC_SPI2_MISO 0x8206 +#define STM32F429_PI2_FUNC_I2S2EXT_SD 0x8207 +#define STM32F429_PI2_FUNC_FMC_D26 0x820d +#define STM32F429_PI2_FUNC_DCMI_D9 0x820e +#define STM32F429_PI2_FUNC_LCD_G7 0x820f +#define STM32F429_PI2_FUNC_EVENTOUT 0x8210 +#define STM32F429_PI2_FUNC_ANALOG 0x8211 + +#define STM32F429_PI3_FUNC_GPIO 0x8300 +#define STM32F429_PI3_FUNC_TIM8_ETR 0x8304 +#define STM32F429_PI3_FUNC_SPI2_MOSI_I2S2_SD 0x8306 +#define STM32F429_PI3_FUNC_FMC_D27 0x830d +#define STM32F429_PI3_FUNC_DCMI_D10 0x830e +#define STM32F429_PI3_FUNC_EVENTOUT 0x8310 +#define STM32F429_PI3_FUNC_ANALOG 0x8311 + +#define STM32F429_PI4_FUNC_GPIO 0x8400 +#define STM32F429_PI4_FUNC_TIM8_BKIN 0x8404 +#define STM32F429_PI4_FUNC_FMC_NBL2 0x840d +#define STM32F429_PI4_FUNC_DCMI_D5 0x840e +#define STM32F429_PI4_FUNC_LCD_B4 0x840f +#define STM32F429_PI4_FUNC_EVENTOUT 0x8410 +#define STM32F429_PI4_FUNC_ANALOG 0x8411 + +#define STM32F429_PI5_FUNC_GPIO 0x8500 +#define STM32F429_PI5_FUNC_TIM8_CH1 0x8504 +#define STM32F429_PI5_FUNC_FMC_NBL3 0x850d +#define STM32F429_PI5_FUNC_DCMI_VSYNC 0x850e +#define STM32F429_PI5_FUNC_LCD_B5 0x850f +#define STM32F429_PI5_FUNC_EVENTOUT 0x8510 +#define STM32F429_PI5_FUNC_ANALOG 0x8511 + +#define STM32F429_PI6_FUNC_GPIO 0x8600 +#define STM32F429_PI6_FUNC_TIM8_CH2 0x8604 +#define STM32F429_PI6_FUNC_FMC_D28 0x860d +#define STM32F429_PI6_FUNC_DCMI_D6 0x860e +#define STM32F429_PI6_FUNC_LCD_B6 0x860f +#define STM32F429_PI6_FUNC_EVENTOUT 0x8610 +#define STM32F429_PI6_FUNC_ANALOG 0x8611 + +#define STM32F429_PI7_FUNC_GPIO 0x8700 +#define STM32F429_PI7_FUNC_TIM8_CH3 0x8704 +#define STM32F429_PI7_FUNC_FMC_D29 0x870d +#define STM32F429_PI7_FUNC_DCMI_D7 0x870e +#define STM32F429_PI7_FUNC_LCD_B7 0x870f +#define STM32F429_PI7_FUNC_EVENTOUT 0x8710 +#define STM32F429_PI7_FUNC_ANALOG 0x8711 + +#define STM32F429_PI8_FUNC_GPIO 0x8800 +#define STM32F429_PI8_FUNC_EVENTOUT 0x8810 +#define STM32F429_PI8_FUNC_ANALOG 0x8811 + +#define STM32F429_PI9_FUNC_GPIO 0x8900 +#define STM32F429_PI9_FUNC_CAN1_RX 0x890a +#define STM32F429_PI9_FUNC_FMC_D30 0x890d +#define STM32F429_PI9_FUNC_LCD_VSYNC 0x890f +#define STM32F429_PI9_FUNC_EVENTOUT 0x8910 +#define STM32F429_PI9_FUNC_ANALOG 0x8911 + +#define STM32F429_PI10_FUNC_GPIO 0x8a00 +#define STM32F429_PI10_FUNC_ETH_MII_RX_ER 0x8a0c +#define STM32F429_PI10_FUNC_FMC_D31 0x8a0d +#define STM32F429_PI10_FUNC_LCD_HSYNC 0x8a0f +#define STM32F429_PI10_FUNC_EVENTOUT 0x8a10 +#define STM32F429_PI10_FUNC_ANALOG 0x8a11 + +#define STM32F429_PI11_FUNC_GPIO 0x8b00 +#define STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR 0x8b0b +#define STM32F429_PI11_FUNC_EVENTOUT 0x8b10 +#define STM32F429_PI11_FUNC_ANALOG 0x8b11 + +#define STM32F429_PI12_FUNC_GPIO 0x8c00 +#define STM32F429_PI12_FUNC_LCD_HSYNC 0x8c0f +#define STM32F429_PI12_FUNC_EVENTOUT 0x8c10 +#define STM32F429_PI12_FUNC_ANALOG 0x8c11 + +#define STM32F429_PI13_FUNC_GPIO 0x8d00 +#define STM32F429_PI13_FUNC_LCD_VSYNC 0x8d0f +#define STM32F429_PI13_FUNC_EVENTOUT 0x8d10 +#define STM32F429_PI13_FUNC_ANALOG 0x8d11 + +#define STM32F429_PI14_FUNC_GPIO 0x8e00 +#define STM32F429_PI14_FUNC_LCD_CLK 0x8e0f +#define STM32F429_PI14_FUNC_EVENTOUT 0x8e10 +#define STM32F429_PI14_FUNC_ANALOG 0x8e11 + +#define STM32F429_PI15_FUNC_GPIO 0x8f00 +#define STM32F429_PI15_FUNC_LCD_R0 0x8f0f +#define STM32F429_PI15_FUNC_EVENTOUT 0x8f10 +#define STM32F429_PI15_FUNC_ANALOG 0x8f11 + + + +#define STM32F429_PJ0_FUNC_GPIO 0x9000 +#define STM32F429_PJ0_FUNC_LCD_R1 0x900f +#define STM32F429_PJ0_FUNC_EVENTOUT 0x9010 +#define STM32F429_PJ0_FUNC_ANALOG 0x9011 + +#define STM32F429_PJ1_FUNC_GPIO 0x9100 +#define STM32F429_PJ1_FUNC_LCD_R2 0x910f +#define STM32F429_PJ1_FUNC_EVENTOUT 0x9110 +#define STM32F429_PJ1_FUNC_ANALOG 0x9111 + +#define STM32F429_PJ2_FUNC_GPIO 0x9200 +#define STM32F429_PJ2_FUNC_LCD_R3 0x920f +#define STM32F429_PJ2_FUNC_EVENTOUT 0x9210 +#define STM32F429_PJ2_FUNC_ANALOG 0x9211 + +#define STM32F429_PJ3_FUNC_GPIO 0x9300 +#define STM32F429_PJ3_FUNC_LCD_R4 0x930f +#define STM32F429_PJ3_FUNC_EVENTOUT 0x9310 +#define STM32F429_PJ3_FUNC_ANALOG 0x9311 + +#define STM32F429_PJ4_FUNC_GPIO 0x9400 +#define STM32F429_PJ4_FUNC_LCD_R5 0x940f +#define STM32F429_PJ4_FUNC_EVENTOUT 0x9410 +#define STM32F429_PJ4_FUNC_ANALOG 0x9411 + +#define STM32F429_PJ5_FUNC_GPIO 0x9500 +#define STM32F429_PJ5_FUNC_LCD_R6 0x950f +#define STM32F429_PJ5_FUNC_EVENTOUT 0x9510 +#define STM32F429_PJ5_FUNC_ANALOG 0x9511 + +#define STM32F429_PJ6_FUNC_GPIO 0x9600 +#define STM32F429_PJ6_FUNC_LCD_R7 0x960f +#define STM32F429_PJ6_FUNC_EVENTOUT 0x9610 +#define STM32F429_PJ6_FUNC_ANALOG 0x9611 + +#define STM32F429_PJ7_FUNC_GPIO 0x9700 +#define STM32F429_PJ7_FUNC_LCD_G0 0x970f +#define STM32F429_PJ7_FUNC_EVENTOUT 0x9710 +#define STM32F429_PJ7_FUNC_ANALOG 0x9711 + +#define STM32F429_PJ8_FUNC_GPIO 0x9800 +#define STM32F429_PJ8_FUNC_LCD_G1 0x980f +#define STM32F429_PJ8_FUNC_EVENTOUT 0x9810 +#define STM32F429_PJ8_FUNC_ANALOG 0x9811 + +#define STM32F429_PJ9_FUNC_GPIO 0x9900 +#define STM32F429_PJ9_FUNC_LCD_G2 0x990f +#define STM32F429_PJ9_FUNC_EVENTOUT 0x9910 +#define STM32F429_PJ9_FUNC_ANALOG 0x9911 + +#define STM32F429_PJ10_FUNC_GPIO 0x9a00 +#define STM32F429_PJ10_FUNC_LCD_G3 0x9a0f +#define STM32F429_PJ10_FUNC_EVENTOUT 0x9a10 +#define STM32F429_PJ10_FUNC_ANALOG 0x9a11 + +#define STM32F429_PJ11_FUNC_GPIO 0x9b00 +#define STM32F429_PJ11_FUNC_LCD_G4 0x9b0f +#define STM32F429_PJ11_FUNC_EVENTOUT 0x9b10 +#define STM32F429_PJ11_FUNC_ANALOG 0x9b11 + +#define STM32F429_PJ12_FUNC_GPIO 0x9c00 +#define STM32F429_PJ12_FUNC_LCD_B0 0x9c0f +#define STM32F429_PJ12_FUNC_EVENTOUT 0x9c10 +#define STM32F429_PJ12_FUNC_ANALOG 0x9c11 + +#define STM32F429_PJ13_FUNC_GPIO 0x9d00 +#define STM32F429_PJ13_FUNC_LCD_B1 0x9d0f +#define STM32F429_PJ13_FUNC_EVENTOUT 0x9d10 +#define STM32F429_PJ13_FUNC_ANALOG 0x9d11 + +#define STM32F429_PJ14_FUNC_GPIO 0x9e00 +#define STM32F429_PJ14_FUNC_LCD_B2 0x9e0f +#define STM32F429_PJ14_FUNC_EVENTOUT 0x9e10 +#define STM32F429_PJ14_FUNC_ANALOG 0x9e11 + +#define STM32F429_PJ15_FUNC_GPIO 0x9f00 +#define STM32F429_PJ15_FUNC_LCD_B3 0x9f0f +#define STM32F429_PJ15_FUNC_EVENTOUT 0x9f10 +#define STM32F429_PJ15_FUNC_ANALOG 0x9f11 + + + +#define STM32F429_PK0_FUNC_GPIO 0xa000 +#define STM32F429_PK0_FUNC_LCD_G5 0xa00f +#define STM32F429_PK0_FUNC_EVENTOUT 0xa010 +#define STM32F429_PK0_FUNC_ANALOG 0xa011 + +#define STM32F429_PK1_FUNC_GPIO 0xa100 +#define STM32F429_PK1_FUNC_LCD_G6 0xa10f +#define STM32F429_PK1_FUNC_EVENTOUT 0xa110 +#define STM32F429_PK1_FUNC_ANALOG 0xa111 + +#define STM32F429_PK2_FUNC_GPIO 0xa200 +#define STM32F429_PK2_FUNC_LCD_G7 0xa20f +#define STM32F429_PK2_FUNC_EVENTOUT 0xa210 +#define STM32F429_PK2_FUNC_ANALOG 0xa211 + +#define STM32F429_PK3_FUNC_GPIO 0xa300 +#define STM32F429_PK3_FUNC_LCD_B4 0xa30f +#define STM32F429_PK3_FUNC_EVENTOUT 0xa310 +#define STM32F429_PK3_FUNC_ANALOG 0xa311 + +#define STM32F429_PK4_FUNC_GPIO 0xa400 +#define STM32F429_PK4_FUNC_LCD_B5 0xa40f +#define STM32F429_PK4_FUNC_EVENTOUT 0xa410 +#define STM32F429_PK4_FUNC_ANALOG 0xa411 + +#define STM32F429_PK5_FUNC_GPIO 0xa500 +#define STM32F429_PK5_FUNC_LCD_B6 0xa50f +#define STM32F429_PK5_FUNC_EVENTOUT 0xa510 +#define STM32F429_PK5_FUNC_ANALOG 0xa511 + +#define STM32F429_PK6_FUNC_GPIO 0xa600 +#define STM32F429_PK6_FUNC_LCD_B7 0xa60f +#define STM32F429_PK6_FUNC_EVENTOUT 0xa610 +#define STM32F429_PK6_FUNC_ANALOG 0xa611 + +#define STM32F429_PK7_FUNC_GPIO 0xa700 +#define STM32F429_PK7_FUNC_LCD_DE 0xa70f +#define STM32F429_PK7_FUNC_EVENTOUT 0xa710 +#define STM32F429_PK7_FUNC_ANALOG 0xa711 + +#endif /* _DT_BINDINGS_STM32F429_PINFUNC_H */ -- 1.9.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v4 4/9] pinctrl: Add STM32 MCUs support 2016-01-14 12:16 ` Maxime Coquelin @ 2016-01-14 12:16 ` Maxime Coquelin -1 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-01-14 12:16 UTC (permalink / raw) To: patrice.chotard, Linus Walleij, Mark Rutland, Rob Herring, linux-gpio, arnd Cc: linux-arm-kernel, linux-kernel, afaerber, devicetree, Daniel Thompson, bruherrera This patch adds pinctrl and GPIO support to STMicroelectronic's STM32 family of MCUs. While it only supports STM32F429 for now, it has been designed to enable support of other MCUs of the family (e.g. STM32F746). Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> --- drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/stm32/Kconfig | 16 + drivers/pinctrl/stm32/Makefile | 5 + drivers/pinctrl/stm32/pinctrl-stm32.c | 834 +++++++++++++++ drivers/pinctrl/stm32/pinctrl-stm32.h | 43 + drivers/pinctrl/stm32/pinctrl-stm32f429.c | 1598 +++++++++++++++++++++++++++++ 7 files changed, 2498 insertions(+) create mode 100644 drivers/pinctrl/stm32/Kconfig create mode 100644 drivers/pinctrl/stm32/Makefile create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32.c create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32.h create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32f429.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 312c78b..c524bf5 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -256,6 +256,7 @@ source "drivers/pinctrl/qcom/Kconfig" source "drivers/pinctrl/samsung/Kconfig" source "drivers/pinctrl/sh-pfc/Kconfig" source "drivers/pinctrl/spear/Kconfig" +source "drivers/pinctrl/stm32/Kconfig" source "drivers/pinctrl/sunxi/Kconfig" source "drivers/pinctrl/uniphier/Kconfig" source "drivers/pinctrl/vt8500/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 738cb49..640079c 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -50,6 +50,7 @@ obj-$(CONFIG_ARCH_QCOM) += qcom/ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/ obj-$(CONFIG_PLAT_SPEAR) += spear/ +obj-$(CONFIG_ARCH_STM32) += stm32/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ obj-$(CONFIG_ARCH_VT8500) += vt8500/ diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig new file mode 100644 index 0000000..0f28841 --- /dev/null +++ b/drivers/pinctrl/stm32/Kconfig @@ -0,0 +1,16 @@ +if ARCH_STM32 || COMPILE_TEST + +config PINCTRL_STM32 + bool + depends on OF + select PINMUX + select GENERIC_PINCONF + select GPIOLIB + +config PINCTRL_STM32F429 + bool "STMicroelectronics STM32F429 pin control" if COMPILE_TEST && !MACH_STM32F429 + depends on OF + default MACH_STM32F429 + select PINCTRL_STM32 + +endif diff --git a/drivers/pinctrl/stm32/Makefile b/drivers/pinctrl/stm32/Makefile new file mode 100644 index 0000000..fc17d42 --- /dev/null +++ b/drivers/pinctrl/stm32/Makefile @@ -0,0 +1,5 @@ +# Core +obj-$(CONFIG_PINCTRL_STM32) += pinctrl-stm32.o + +# SoC Drivers +obj-$(CONFIG_PINCTRL_STM32F429) += pinctrl-stm32f429.o diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c new file mode 100644 index 0000000..d25d4a0 --- /dev/null +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -0,0 +1,834 @@ +/* + * Copyright (C) Maxime Coquelin 2015 + * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> + * License terms: GNU General Public License (GPL), version 2 + * + * Heavily based on Mediatek's pinctrl driver + */ +#include <linux/clk.h> +#include <linux/gpio.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/of_irq.h> +#include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/reset.h> +#include <linux/slab.h> + +#include <dt-bindings/pinctrl/pinctrl-stm32.h> + +#include "../core.h" +#include "../pinconf.h" +#include "../pinctrl-utils.h" +#include "pinctrl-stm32.h" + +#define STM32_GPIO_MODER 0x00 +#define STM32_GPIO_TYPER 0x04 +#define STM32_GPIO_SPEEDR 0x08 +#define STM32_GPIO_PUPDR 0x0c +#define STM32_GPIO_IDR 0x10 +#define STM32_GPIO_ODR 0x14 +#define STM32_GPIO_BSRR 0x18 +#define STM32_GPIO_LCKR 0x1c +#define STM32_GPIO_AFRL 0x20 +#define STM32_GPIO_AFRH 0x24 + +#define STM32_GPIO_PINS_PER_BANK 16 + +#define gpio_range_to_bank(chip) \ + container_of(chip, struct stm32_gpio_bank, range) + +#define gpio_chip_to_bank(chip) \ + container_of(chip, struct stm32_gpio_bank, gpio_chip) + +static const char * const stm32_gpio_functions[] = { + "gpio", "af0", "af1", + "af2", "af3", "af4", + "af5", "af6", "af7", + "af8", "af9", "af10", + "af11", "af12", "af13", + "af14", "af15", "analog", +}; + +struct stm32_pinctrl_group { + const char *name; + unsigned long config; + unsigned pin; +}; + +struct stm32_gpio_bank { + void __iomem *base; + struct clk *clk; + spinlock_t lock; + struct gpio_chip gpio_chip; + struct pinctrl_gpio_range range; +}; + +struct stm32_pinctrl { + struct device *dev; + struct pinctrl_dev *pctl_dev; + struct pinctrl_desc pctl_desc; + struct stm32_pinctrl_group *groups; + unsigned ngroups; + const char **grp_names; + struct stm32_gpio_bank *banks; + unsigned nbanks; + const struct stm32_pinctrl_match_data *match_data; +}; + +static inline int stm32_gpio_pin(int gpio) +{ + return gpio % STM32_GPIO_PINS_PER_BANK; +} + +static inline u32 stm32_gpio_get_mode(u32 function) +{ + switch (function) { + case STM32_PIN_GPIO: + return 0; + case STM32_PIN_AF(0) ... STM32_PIN_AF(15): + return 2; + case STM32_PIN_ANALOG: + return 3; + } + + return 0; +} + +static inline u32 stm32_gpio_get_alt(u32 function) +{ + switch (function) { + case STM32_PIN_GPIO: + return 0; + case STM32_PIN_AF(0) ... STM32_PIN_AF(15): + return function - 1; + case STM32_PIN_ANALOG: + return 0; + } + + return 0; +} + +/* GPIO functions */ + +static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, + unsigned offset, int value) +{ + if (!value) + offset += STM32_GPIO_PINS_PER_BANK; + + clk_enable(bank->clk); + + writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); + + clk_disable(bank->clk); +} + +static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + return pinctrl_request_gpio(chip->base + offset); +} + +static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + pinctrl_free_gpio(chip->base + offset); +} + +static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); + int ret; + + clk_enable(bank->clk); + + ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); + + clk_disable(bank->clk); + + return ret; +} + +static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); + + __stm32_gpio_set(bank, offset, value); +} + +static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + return pinctrl_gpio_direction_input(chip->base + offset); +} + +static int stm32_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); + + __stm32_gpio_set(bank, offset, value); + pinctrl_gpio_direction_output(chip->base + offset); + + return 0; +} + +static struct gpio_chip stm32_gpio_template = { + .request = stm32_gpio_request, + .free = stm32_gpio_free, + .get = stm32_gpio_get, + .set = stm32_gpio_set, + .direction_input = stm32_gpio_direction_input, + .direction_output = stm32_gpio_direction_output, +}; + +/* Pinctrl functions */ + +static struct stm32_pinctrl_group * +stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin) +{ + int i; + + for (i = 0; i < pctl->ngroups; i++) { + struct stm32_pinctrl_group *grp = pctl->groups + i; + + if (grp->pin == pin) + return grp; + } + + return NULL; +} + +static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl, + u32 pin_num, u32 fnum) +{ + int i; + + for (i = 0; i < pctl->match_data->npins; i++) { + const struct stm32_desc_pin *pin = pctl->match_data->pins + i; + const struct stm32_desc_function *func = pin->functions; + + if (pin->pin.number != pin_num) + continue; + + while (func && func->name) { + if (func->num == fnum) + return true; + func++; + } + + break; + } + + return false; +} + +static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl, + u32 pin, u32 fnum, struct stm32_pinctrl_group *grp, + struct pinctrl_map **map, unsigned *reserved_maps, + unsigned *num_maps) +{ + if (*num_maps == *reserved_maps) + return -ENOSPC; + + (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[*num_maps].data.mux.group = grp->name; + + if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) { + dev_err(pctl->dev, "invalid function %d on pin %d .\n", + fnum, pin); + return -EINVAL; + } + + (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum]; + (*num_maps)++; + + return 0; +} + +static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, + struct device_node *node, + struct pinctrl_map **map, + unsigned *reserved_maps, + unsigned *num_maps) +{ + struct stm32_pinctrl *pctl; + struct stm32_pinctrl_group *grp; + struct property *pins; + u32 pinfunc, pin, func; + unsigned long *configs; + unsigned int num_configs; + bool has_config = 0; + unsigned reserve = 0; + int num_pins, num_funcs, maps_per_pin, i, err; + + pctl = pinctrl_dev_get_drvdata(pctldev); + + pins = of_find_property(node, "pinmux", NULL); + if (!pins) { + dev_err(pctl->dev, "missing pins property in node %s .\n", + node->name); + return -EINVAL; + } + + err = pinconf_generic_parse_dt_config(node, pctldev, &configs, + &num_configs); + if (err) + return err; + + if (num_configs) + has_config = 1; + + num_pins = pins->length / sizeof(u32); + num_funcs = num_pins; + maps_per_pin = 0; + if (num_funcs) + maps_per_pin++; + if (has_config && num_pins >= 1) + maps_per_pin++; + + if (!num_pins || !maps_per_pin) + return -EINVAL; + + reserve = num_pins * maps_per_pin; + + err = pinctrl_utils_reserve_map(pctldev, map, + reserved_maps, num_maps, reserve); + if (err) + return err; + + for (i = 0; i < num_pins; i++) { + err = of_property_read_u32_index(node, "pinmux", + i, &pinfunc); + if (err) + return err; + + pin = STM32_GET_PIN_NO(pinfunc); + func = STM32_GET_PIN_FUNC(pinfunc); + + if (pin >= pctl->match_data->npins) { + dev_err(pctl->dev, "invalid pin number.\n"); + return -EINVAL; + } + + if (!stm32_pctrl_is_function_valid(pctl, pin, func)) { + dev_err(pctl->dev, "invalid function.\n"); + return -EINVAL; + } + + grp = stm32_pctrl_find_group_by_pin(pctl, pin); + if (!grp) { + dev_err(pctl->dev, "unable to match pin %d to group\n", + pin); + return -EINVAL; + } + + err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, + reserved_maps, num_maps); + if (err) + return err; + + if (has_config) { + err = pinctrl_utils_add_map_configs(pctldev, map, + reserved_maps, num_maps, grp->name, + configs, num_configs, + PIN_MAP_TYPE_CONFIGS_GROUP); + if (err) + return err; + } + } + + return 0; +} + +static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, unsigned *num_maps) +{ + struct device_node *np; + unsigned reserved_maps; + int ret; + + *map = NULL; + *num_maps = 0; + reserved_maps = 0; + + for_each_child_of_node(np_config, np) { + ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map, + &reserved_maps, num_maps); + if (ret < 0) { + pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); + return ret; + } + } + + return 0; +} + +static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->ngroups; +} + +static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->groups[group].name; +} + +static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *pins = (unsigned *)&pctl->groups[group].pin; + *num_pins = 1; + + return 0; +} + +static const struct pinctrl_ops stm32_pctrl_ops = { + .dt_node_to_map = stm32_pctrl_dt_node_to_map, + .dt_free_map = pinctrl_utils_dt_free_map, + .get_groups_count = stm32_pctrl_get_groups_count, + .get_group_name = stm32_pctrl_get_group_name, + .get_group_pins = stm32_pctrl_get_group_pins, +}; + + +/* Pinmux functions */ + +static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(stm32_gpio_functions); +} + +static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + return stm32_gpio_functions[selector]; +} + +static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char * const **groups, + unsigned * const num_groups) +{ + struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *groups = pctl->grp_names; + *num_groups = pctl->ngroups; + + return 0; +} + +static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank, + int pin, u32 mode, u32 alt) +{ + u32 val; + int alt_shift = (pin % 8) * 4; + int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; + unsigned long flags; + + clk_enable(bank->clk); + spin_lock_irqsave(&bank->lock, flags); + + val = readl_relaxed(bank->base + alt_offset); + val &= ~GENMASK(alt_shift + 3, alt_shift); + val |= (alt << alt_shift); + writel_relaxed(val, bank->base + alt_offset); + + val = readl_relaxed(bank->base + STM32_GPIO_MODER); + val &= ~GENMASK(pin * 2 + 1, pin * 2); + val |= mode << (pin * 2); + writel_relaxed(val, bank->base + STM32_GPIO_MODER); + + spin_unlock_irqrestore(&bank->lock, flags); + clk_disable(bank->clk); +} + +static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) +{ + bool ret; + struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct stm32_pinctrl_group *g = pctl->groups + group; + struct pinctrl_gpio_range *range; + struct stm32_gpio_bank *bank; + u32 mode, alt; + int pin; + + ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); + if (!ret) { + dev_err(pctl->dev, "invalid function %d on group %d .\n", + function, group); + return -EINVAL; + } + + range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); + bank = gpio_range_to_bank(range); + pin = stm32_gpio_pin(g->pin); + + mode = stm32_gpio_get_mode(function); + alt = stm32_gpio_get_alt(function); + + stm32_pmx_set_mode(bank, pin, mode, alt); + + return 0; +} + +static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, unsigned gpio, + bool input) +{ + struct stm32_gpio_bank *bank = gpio_range_to_bank(range); + int pin = stm32_gpio_pin(gpio); + + stm32_pmx_set_mode(bank, pin, !input, 0); + + return 0; +} + +static const struct pinmux_ops stm32_pmx_ops = { + .get_functions_count = stm32_pmx_get_funcs_cnt, + .get_function_name = stm32_pmx_get_func_name, + .get_function_groups = stm32_pmx_get_func_groups, + .set_mux = stm32_pmx_set_mux, + .gpio_set_direction = stm32_pmx_gpio_set_direction, +}; + +/* Pinconf functions */ + +static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank, + unsigned offset, u32 drive) +{ + unsigned long flags; + u32 val; + + clk_enable(bank->clk); + spin_lock_irqsave(&bank->lock, flags); + + val = readl_relaxed(bank->base + STM32_GPIO_TYPER); + val &= ~BIT(offset); + val |= drive << offset; + writel_relaxed(val, bank->base + STM32_GPIO_TYPER); + + spin_unlock_irqrestore(&bank->lock, flags); + clk_disable(bank->clk); +} + +static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank, + unsigned offset, u32 speed) +{ + unsigned long flags; + u32 val; + + clk_enable(bank->clk); + spin_lock_irqsave(&bank->lock, flags); + + val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); + val &= ~GENMASK(offset * 2 + 1, offset * 2); + val |= speed << (offset * 2); + writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); + + spin_unlock_irqrestore(&bank->lock, flags); + clk_disable(bank->clk); +} + +static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank, + unsigned offset, u32 bias) +{ + unsigned long flags; + u32 val; + + clk_enable(bank->clk); + spin_lock_irqsave(&bank->lock, flags); + + val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); + val &= ~GENMASK(offset * 2 + 1, offset * 2); + val |= bias << (offset * 2); + writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); + + spin_unlock_irqrestore(&bank->lock, flags); + clk_disable(bank->clk); +} + +static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, + unsigned int pin, enum pin_config_param param, + enum pin_config_param arg) +{ + struct pinctrl_gpio_range *range; + struct stm32_gpio_bank *bank; + int offset, ret = 0; + + range = pinctrl_find_gpio_range_from_pin(pctldev, pin); + bank = gpio_range_to_bank(range); + offset = stm32_gpio_pin(pin); + + switch (param) { + case PIN_CONFIG_DRIVE_PUSH_PULL: + stm32_pconf_set_driving(bank, offset, 0); + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + stm32_pconf_set_driving(bank, offset, 1); + break; + case PIN_CONFIG_SLEW_RATE: + stm32_pconf_set_speed(bank, offset, arg); + break; + case PIN_CONFIG_BIAS_DISABLE: + stm32_pconf_set_bias(bank, offset, 0); + break; + case PIN_CONFIG_BIAS_PULL_UP: + stm32_pconf_set_bias(bank, offset, 1); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + stm32_pconf_set_bias(bank, offset, 2); + break; + case PIN_CONFIG_OUTPUT: + __stm32_gpio_set(bank, offset, arg); + ret = stm32_pmx_gpio_set_direction(pctldev, NULL, pin, false); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static int stm32_pconf_group_get(struct pinctrl_dev *pctldev, + unsigned group, + unsigned long *config) +{ + struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *config = pctl->groups[group].config; + + return 0; +} + +static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, + unsigned long *configs, unsigned num_configs) +{ + struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct stm32_pinctrl_group *g = &pctl->groups[group]; + int i, ret; + + for (i = 0; i < num_configs; i++) { + ret = stm32_pconf_parse_conf(pctldev, g->pin, + pinconf_to_config_param(configs[i]), + pinconf_to_config_argument(configs[i])); + if (ret < 0) + return ret; + + g->config = configs[i]; + } + + return 0; +} + +static const struct pinconf_ops stm32_pconf_ops = { + .pin_config_group_get = stm32_pconf_group_get, + .pin_config_group_set = stm32_pconf_group_set, +}; + +static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, + struct device_node *np) +{ + int bank_nr = pctl->nbanks; + struct stm32_gpio_bank *bank = &pctl->banks[bank_nr]; + struct pinctrl_gpio_range *range = &bank->range; + struct device *dev = pctl->dev; + struct resource res; + struct reset_control *rstc; + int err, npins; + + rstc = of_reset_control_get(np, NULL); + if (!IS_ERR(rstc)) + reset_control_deassert(rstc); + + if (of_address_to_resource(np, 0, &res)) + return -ENODEV; + + bank->base = devm_ioremap_resource(dev, &res); + if (IS_ERR(bank->base)) + return PTR_ERR(bank->base); + + bank->clk = of_clk_get_by_name(np, NULL); + if (IS_ERR(bank->clk)) { + dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk)); + return PTR_ERR(bank->clk); + } + + err = clk_prepare(bank->clk); + if (err) { + dev_err(dev, "failed to prepare clk (%d)\n", err); + return err; + } + + npins = pctl->match_data->npins; + npins -= bank_nr * STM32_GPIO_PINS_PER_BANK; + if (npins < 0) + return -EINVAL; + else if (npins > STM32_GPIO_PINS_PER_BANK) + npins = STM32_GPIO_PINS_PER_BANK; + + bank->gpio_chip = stm32_gpio_template; + bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; + bank->gpio_chip.ngpio = npins; + bank->gpio_chip.of_node = np; + bank->gpio_chip.dev = dev; + spin_lock_init(&bank->lock); + + of_property_read_string(np, "st,bank-name", &range->name); + bank->gpio_chip.label = range->name; + + range->id = bank_nr; + range->pin_base = range->base = range->id * STM32_GPIO_PINS_PER_BANK; + range->npins = bank->gpio_chip.ngpio; + range->gc = &bank->gpio_chip; + err = gpiochip_add(&bank->gpio_chip); + if (err) { + dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr); + return err; + } + + dev_info(dev, "%s bank added\n", range->name); + return 0; +} + +static int stm32_pctrl_build_state(struct platform_device *pdev) +{ + struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); + int i; + + pctl->ngroups = pctl->match_data->npins; + + /* Allocate groups */ + pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, + sizeof(*pctl->groups), GFP_KERNEL); + if (!pctl->groups) + return -ENOMEM; + + /* We assume that one pin is one group, use pin name as group name. */ + pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, + sizeof(*pctl->grp_names), GFP_KERNEL); + if (!pctl->grp_names) + return -ENOMEM; + + for (i = 0; i < pctl->match_data->npins; i++) { + const struct stm32_desc_pin *pin = pctl->match_data->pins + i; + struct stm32_pinctrl_group *group = pctl->groups + i; + + group->name = pin->pin.name; + group->pin = pin->pin.number; + + pctl->grp_names[i] = pin->pin.name; + } + + return 0; +} + +int stm32_pctl_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct device_node *child; + const struct of_device_id *match; + struct device *dev = &pdev->dev; + struct stm32_pinctrl *pctl; + struct pinctrl_pin_desc *pins; + int i, ret, banks = 0; + + if (!np) + return -EINVAL; + + match = of_match_device(dev->driver->of_match_table, dev); + if (!match || !match->data) + return -EINVAL; + + if (!of_find_property(np, "pins-are-numbered", NULL)) { + dev_err(dev, "only support pins-are-numbered format\n"); + return -EINVAL; + } + + pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); + if (!pctl) + return -ENOMEM; + + platform_set_drvdata(pdev, pctl); + + pctl->dev = dev; + pctl->match_data = match->data; + ret = stm32_pctrl_build_state(pdev); + if (ret) { + dev_err(dev, "build state failed: %d\n", ret); + return -EINVAL; + } + + for_each_child_of_node(np, child) + if (of_property_read_bool(child, "gpio-controller")) + banks++; + + if (!banks) { + dev_err(dev, "at least one GPIO bank is required\n"); + return -EINVAL; + } + + pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), + GFP_KERNEL); + if (!pctl->banks) + return -ENOMEM; + + for_each_child_of_node(np, child) { + if (of_property_read_bool(child, "gpio-controller")) { + ret = stm32_gpiolib_register_bank(pctl, child); + if (ret) + return ret; + + pctl->nbanks++; + } + } + + pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins), + GFP_KERNEL); + if (!pins) + return -ENOMEM; + + for (i = 0; i < pctl->match_data->npins; i++) + pins[i] = pctl->match_data->pins[i].pin; + + pctl->pctl_desc.name = dev_name(&pdev->dev); + pctl->pctl_desc.owner = THIS_MODULE; + pctl->pctl_desc.pins = pins; + pctl->pctl_desc.npins = pctl->match_data->npins; + pctl->pctl_desc.confops = &stm32_pconf_ops; + pctl->pctl_desc.pctlops = &stm32_pctrl_ops; + pctl->pctl_desc.pmxops = &stm32_pmx_ops; + pctl->dev = &pdev->dev; + + pctl->pctl_dev = pinctrl_register(&pctl->pctl_desc, &pdev->dev, pctl); + if (!pctl->pctl_dev) { + dev_err(&pdev->dev, "Failed pinctrl registration\n"); + return -EINVAL; + } + + for (i = 0; i < pctl->nbanks; i++) + pinctrl_add_gpio_range(pctl->pctl_dev, &pctl->banks[i].range); + + dev_info(dev, "Pinctrl STM32 initialized\n"); + + return 0; +} + diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.h b/drivers/pinctrl/stm32/pinctrl-stm32.h new file mode 100644 index 0000000..1b7c369 --- /dev/null +++ b/drivers/pinctrl/stm32/pinctrl-stm32.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) Maxime Coquelin 2015 + * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> + * License terms: GNU General Public License (GPL), version 2 + */ +#ifndef __PINCTRL_STM32_H +#define __PINCTRL_STM32_H + +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinconf-generic.h> + +struct stm32_desc_function { + const char *name; + const unsigned char num; +}; + +struct stm32_desc_pin { + struct pinctrl_pin_desc pin; + const struct stm32_desc_function *functions; +}; + +#define STM32_PIN(_pin, ...) \ + { \ + .pin = _pin, \ + .functions = (struct stm32_desc_function[]){ \ + __VA_ARGS__, { } }, \ + } + +#define STM32_FUNCTION(_num, _name) \ + { \ + .num = _num, \ + .name = _name, \ + } + +struct stm32_pinctrl_match_data { + const struct stm32_desc_pin *pins; + const unsigned int npins; +}; + +int stm32_pctl_probe(struct platform_device *pdev); + +#endif /* __PINCTRL_STM32_H */ + diff --git a/drivers/pinctrl/stm32/pinctrl-stm32f429.c b/drivers/pinctrl/stm32/pinctrl-stm32f429.c new file mode 100644 index 0000000..f34016b --- /dev/null +++ b/drivers/pinctrl/stm32/pinctrl-stm32f429.c @@ -0,0 +1,1598 @@ +/* + * Copyright (C) Maxime Coquelin 2015 + * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> + * License terms: GNU General Public License (GPL), version 2 + */ +#include <linux/init.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-stm32.h" + +static const struct stm32_desc_pin stm32f429_pins[] = { + STM32_PIN( + PINCTRL_PIN(0, "PA0"), + STM32_FUNCTION(0, "GPIOA0"), + STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"), + STM32_FUNCTION(3, "TIM5_CH1"), + STM32_FUNCTION(4, "TIM8_ETR"), + STM32_FUNCTION(8, "USART2_CTS"), + STM32_FUNCTION(9, "UART4_TX"), + STM32_FUNCTION(12, "ETH_MII_CRS"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(1, "PA1"), + STM32_FUNCTION(0, "GPIOA1"), + STM32_FUNCTION(2, "TIM2_CH2"), + STM32_FUNCTION(3, "TIM5_CH2"), + STM32_FUNCTION(8, "USART2_RTS"), + STM32_FUNCTION(9, "UART4_RX"), + STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(2, "PA2"), + STM32_FUNCTION(0, "GPIOA2"), + STM32_FUNCTION(2, "TIM2_CH3"), + STM32_FUNCTION(3, "TIM5_CH3"), + STM32_FUNCTION(4, "TIM9_CH1"), + STM32_FUNCTION(8, "USART2_TX"), + STM32_FUNCTION(12, "ETH_MDIO"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(3, "PA3"), + STM32_FUNCTION(0, "GPIOA3"), + STM32_FUNCTION(2, "TIM2_CH4"), + STM32_FUNCTION(3, "TIM5_CH4"), + STM32_FUNCTION(4, "TIM9_CH2"), + STM32_FUNCTION(8, "USART2_RX"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D0"), + STM32_FUNCTION(12, "ETH_MII_COL"), + STM32_FUNCTION(15, "LCD_B5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(4, "PA4"), + STM32_FUNCTION(0, "GPIOA4"), + STM32_FUNCTION(6, "SPI1_NSS"), + STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"), + STM32_FUNCTION(8, "USART2_CK"), + STM32_FUNCTION(13, "OTG_HS_SOF"), + STM32_FUNCTION(14, "DCMI_HSYNC"), + STM32_FUNCTION(15, "LCD_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(5, "PA5"), + STM32_FUNCTION(0, "GPIOA5"), + STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"), + STM32_FUNCTION(4, "TIM8_CH1N"), + STM32_FUNCTION(6, "SPI1_SCK"), + STM32_FUNCTION(11, "OTG_HS_ULPI_CK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(6, "PA6"), + STM32_FUNCTION(0, "GPIOA6"), + STM32_FUNCTION(2, "TIM1_BKIN"), + STM32_FUNCTION(3, "TIM3_CH1"), + STM32_FUNCTION(4, "TIM8_BKIN"), + STM32_FUNCTION(6, "SPI1_MISO"), + STM32_FUNCTION(10, "TIM13_CH1"), + STM32_FUNCTION(14, "DCMI_PIXCLK"), + STM32_FUNCTION(15, "LCD_G2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(7, "PA7"), + STM32_FUNCTION(0, "GPIOA7"), + STM32_FUNCTION(2, "TIM1_CH1N"), + STM32_FUNCTION(3, "TIM3_CH2"), + STM32_FUNCTION(4, "TIM8_CH1N"), + STM32_FUNCTION(6, "SPI1_MOSI"), + STM32_FUNCTION(10, "TIM14_CH1"), + STM32_FUNCTION(12, "ETH_MII_RX_DV ETH_RMII_CRS_DV"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(8, "PA8"), + STM32_FUNCTION(0, "GPIOA8"), + STM32_FUNCTION(1, "MCO1"), + STM32_FUNCTION(2, "TIM1_CH1"), + STM32_FUNCTION(5, "I2C3_SCL"), + STM32_FUNCTION(8, "USART1_CK"), + STM32_FUNCTION(11, "OTG_FS_SOF"), + STM32_FUNCTION(15, "LCD_R6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(9, "PA9"), + STM32_FUNCTION(0, "GPIOA9"), + STM32_FUNCTION(2, "TIM1_CH2"), + STM32_FUNCTION(5, "I2C3_SMBA"), + STM32_FUNCTION(8, "USART1_TX"), + STM32_FUNCTION(14, "DCMI_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(10, "PA10"), + STM32_FUNCTION(0, "GPIOA10"), + STM32_FUNCTION(2, "TIM1_CH3"), + STM32_FUNCTION(8, "USART1_RX"), + STM32_FUNCTION(11, "OTG_FS_ID"), + STM32_FUNCTION(14, "DCMI_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(11, "PA11"), + STM32_FUNCTION(0, "GPIOA11"), + STM32_FUNCTION(2, "TIM1_CH4"), + STM32_FUNCTION(8, "USART1_CTS"), + STM32_FUNCTION(10, "CAN1_RX"), + STM32_FUNCTION(11, "OTG_FS_DM"), + STM32_FUNCTION(15, "LCD_R4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(12, "PA12"), + STM32_FUNCTION(0, "GPIOA12"), + STM32_FUNCTION(2, "TIM1_ETR"), + STM32_FUNCTION(8, "USART1_RTS"), + STM32_FUNCTION(10, "CAN1_TX"), + STM32_FUNCTION(11, "OTG_FS_DP"), + STM32_FUNCTION(15, "LCD_R5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(13, "PA13"), + STM32_FUNCTION(0, "GPIOA13"), + STM32_FUNCTION(1, "JTMS SWDIO"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(14, "PA14"), + STM32_FUNCTION(0, "GPIOA14"), + STM32_FUNCTION(1, "JTCK SWCLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(15, "PA15"), + STM32_FUNCTION(0, "GPIOA15"), + STM32_FUNCTION(1, "JTDI"), + STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"), + STM32_FUNCTION(6, "SPI1_NSS"), + STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(16, "PB0"), + STM32_FUNCTION(0, "GPIOB0"), + STM32_FUNCTION(2, "TIM1_CH2N"), + STM32_FUNCTION(3, "TIM3_CH3"), + STM32_FUNCTION(4, "TIM8_CH2N"), + STM32_FUNCTION(10, "LCD_R3"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D1"), + STM32_FUNCTION(12, "ETH_MII_RXD2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(17, "PB1"), + STM32_FUNCTION(0, "GPIOB1"), + STM32_FUNCTION(2, "TIM1_CH3N"), + STM32_FUNCTION(3, "TIM3_CH4"), + STM32_FUNCTION(4, "TIM8_CH3N"), + STM32_FUNCTION(10, "LCD_R6"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D2"), + STM32_FUNCTION(12, "ETH_MII_RXD3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(18, "PB2"), + STM32_FUNCTION(0, "GPIOB2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(19, "PB3"), + STM32_FUNCTION(0, "GPIOB3"), + STM32_FUNCTION(1, "JTDO TRACESWO"), + STM32_FUNCTION(2, "TIM2_CH2"), + STM32_FUNCTION(6, "SPI1_SCK"), + STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(20, "PB4"), + STM32_FUNCTION(0, "GPIOB4"), + STM32_FUNCTION(1, "NJTRST"), + STM32_FUNCTION(3, "TIM3_CH1"), + STM32_FUNCTION(6, "SPI1_MISO"), + STM32_FUNCTION(7, "SPI3_MISO"), + STM32_FUNCTION(8, "I2S3EXT_SD"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(21, "PB5"), + STM32_FUNCTION(0, "GPIOB5"), + STM32_FUNCTION(3, "TIM3_CH2"), + STM32_FUNCTION(5, "I2C1_SMBA"), + STM32_FUNCTION(6, "SPI1_MOSI"), + STM32_FUNCTION(7, "SPI3_MOSI I2S3_SD"), + STM32_FUNCTION(10, "CAN2_RX"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D7"), + STM32_FUNCTION(12, "ETH_PPS_OUT"), + STM32_FUNCTION(13, "FMC_SDCKE1"), + STM32_FUNCTION(14, "DCMI_D10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(22, "PB6"), + STM32_FUNCTION(0, "GPIOB6"), + STM32_FUNCTION(3, "TIM4_CH1"), + STM32_FUNCTION(5, "I2C1_SCL"), + STM32_FUNCTION(8, "USART1_TX"), + STM32_FUNCTION(10, "CAN2_TX"), + STM32_FUNCTION(13, "FMC_SDNE1"), + STM32_FUNCTION(14, "DCMI_D5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(23, "PB7"), + STM32_FUNCTION(0, "GPIOB7"), + STM32_FUNCTION(3, "TIM4_CH2"), + STM32_FUNCTION(5, "I2C1_SDA"), + STM32_FUNCTION(8, "USART1_RX"), + STM32_FUNCTION(13, "FMC_NL"), + STM32_FUNCTION(14, "DCMI_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(24, "PB8"), + STM32_FUNCTION(0, "GPIOB8"), + STM32_FUNCTION(3, "TIM4_CH3"), + STM32_FUNCTION(4, "TIM10_CH1"), + STM32_FUNCTION(5, "I2C1_SCL"), + STM32_FUNCTION(10, "CAN1_RX"), + STM32_FUNCTION(12, "ETH_MII_TXD3"), + STM32_FUNCTION(13, "SDIO_D4"), + STM32_FUNCTION(14, "DCMI_D6"), + STM32_FUNCTION(15, "LCD_B6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(25, "PB9"), + STM32_FUNCTION(0, "GPIOB9"), + STM32_FUNCTION(3, "TIM4_CH4"), + STM32_FUNCTION(4, "TIM11_CH1"), + STM32_FUNCTION(5, "I2C1_SDA"), + STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"), + STM32_FUNCTION(10, "CAN1_TX"), + STM32_FUNCTION(13, "SDIO_D5"), + STM32_FUNCTION(14, "DCMI_D7"), + STM32_FUNCTION(15, "LCD_B7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(26, "PB10"), + STM32_FUNCTION(0, "GPIOB10"), + STM32_FUNCTION(2, "TIM2_CH3"), + STM32_FUNCTION(5, "I2C2_SCL"), + STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(8, "USART3_TX"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D3"), + STM32_FUNCTION(12, "ETH_MII_RX_ER"), + STM32_FUNCTION(15, "LCD_G4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(27, "PB11"), + STM32_FUNCTION(0, "GPIOB11"), + STM32_FUNCTION(2, "TIM2_CH4"), + STM32_FUNCTION(5, "I2C2_SDA"), + STM32_FUNCTION(8, "USART3_RX"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D4"), + STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"), + STM32_FUNCTION(15, "LCD_G5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(28, "PB12"), + STM32_FUNCTION(0, "GPIOB12"), + STM32_FUNCTION(2, "TIM1_BKIN"), + STM32_FUNCTION(5, "I2C2_SMBA"), + STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"), + STM32_FUNCTION(8, "USART3_CK"), + STM32_FUNCTION(10, "CAN2_RX"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D5"), + STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"), + STM32_FUNCTION(13, "OTG_HS_ID"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(29, "PB13"), + STM32_FUNCTION(0, "GPIOB13"), + STM32_FUNCTION(2, "TIM1_CH1N"), + STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(8, "USART3_CTS"), + STM32_FUNCTION(10, "CAN2_TX"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D6"), + STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(30, "PB14"), + STM32_FUNCTION(0, "GPIOB14"), + STM32_FUNCTION(2, "TIM1_CH2N"), + STM32_FUNCTION(4, "TIM8_CH2N"), + STM32_FUNCTION(6, "SPI2_MISO"), + STM32_FUNCTION(7, "I2S2EXT_SD"), + STM32_FUNCTION(8, "USART3_RTS"), + STM32_FUNCTION(10, "TIM12_CH1"), + STM32_FUNCTION(13, "OTG_HS_DM"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(31, "PB15"), + STM32_FUNCTION(0, "GPIOB15"), + STM32_FUNCTION(1, "RTC_REFIN"), + STM32_FUNCTION(2, "TIM1_CH3N"), + STM32_FUNCTION(4, "TIM8_CH3N"), + STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"), + STM32_FUNCTION(10, "TIM12_CH2"), + STM32_FUNCTION(13, "OTG_HS_DP"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(32, "PC0"), + STM32_FUNCTION(0, "GPIOC0"), + STM32_FUNCTION(11, "OTG_HS_ULPI_STP"), + STM32_FUNCTION(13, "FMC_SDNWE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(33, "PC1"), + STM32_FUNCTION(0, "GPIOC1"), + STM32_FUNCTION(12, "ETH_MDC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(34, "PC2"), + STM32_FUNCTION(0, "GPIOC2"), + STM32_FUNCTION(6, "SPI2_MISO"), + STM32_FUNCTION(7, "I2S2EXT_SD"), + STM32_FUNCTION(11, "OTG_HS_ULPI_DIR"), + STM32_FUNCTION(12, "ETH_MII_TXD2"), + STM32_FUNCTION(13, "FMC_SDNE0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(35, "PC3"), + STM32_FUNCTION(0, "GPIOC3"), + STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"), + STM32_FUNCTION(11, "OTG_HS_ULPI_NXT"), + STM32_FUNCTION(12, "ETH_MII_TX_CLK"), + STM32_FUNCTION(13, "FMC_SDCKE0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(36, "PC4"), + STM32_FUNCTION(0, "GPIOC4"), + STM32_FUNCTION(12, "ETH_MII_RXD0 ETH_RMII_RXD0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(37, "PC5"), + STM32_FUNCTION(0, "GPIOC5"), + STM32_FUNCTION(12, "ETH_MII_RXD1 ETH_RMII_RXD1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(38, "PC6"), + STM32_FUNCTION(0, "GPIOC6"), + STM32_FUNCTION(3, "TIM3_CH1"), + STM32_FUNCTION(4, "TIM8_CH1"), + STM32_FUNCTION(6, "I2S2_MCK"), + STM32_FUNCTION(9, "USART6_TX"), + STM32_FUNCTION(13, "SDIO_D6"), + STM32_FUNCTION(14, "DCMI_D0"), + STM32_FUNCTION(15, "LCD_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(39, "PC7"), + STM32_FUNCTION(0, "GPIOC7"), + STM32_FUNCTION(3, "TIM3_CH2"), + STM32_FUNCTION(4, "TIM8_CH2"), + STM32_FUNCTION(7, "I2S3_MCK"), + STM32_FUNCTION(9, "USART6_RX"), + STM32_FUNCTION(13, "SDIO_D7"), + STM32_FUNCTION(14, "DCMI_D1"), + STM32_FUNCTION(15, "LCD_G6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(40, "PC8"), + STM32_FUNCTION(0, "GPIOC8"), + STM32_FUNCTION(3, "TIM3_CH3"), + STM32_FUNCTION(4, "TIM8_CH3"), + STM32_FUNCTION(9, "USART6_CK"), + STM32_FUNCTION(13, "SDIO_D0"), + STM32_FUNCTION(14, "DCMI_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(41, "PC9"), + STM32_FUNCTION(0, "GPIOC9"), + STM32_FUNCTION(1, "MCO2"), + STM32_FUNCTION(3, "TIM3_CH4"), + STM32_FUNCTION(4, "TIM8_CH4"), + STM32_FUNCTION(5, "I2C3_SDA"), + STM32_FUNCTION(6, "I2S_CKIN"), + STM32_FUNCTION(13, "SDIO_D1"), + STM32_FUNCTION(14, "DCMI_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(42, "PC10"), + STM32_FUNCTION(0, "GPIOC10"), + STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"), + STM32_FUNCTION(8, "USART3_TX"), + STM32_FUNCTION(9, "UART4_TX"), + STM32_FUNCTION(13, "SDIO_D2"), + STM32_FUNCTION(14, "DCMI_D8"), + STM32_FUNCTION(15, "LCD_R2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(43, "PC11"), + STM32_FUNCTION(0, "GPIOC11"), + STM32_FUNCTION(6, "I2S3EXT_SD"), + STM32_FUNCTION(7, "SPI3_MISO"), + STM32_FUNCTION(8, "USART3_RX"), + STM32_FUNCTION(9, "UART4_RX"), + STM32_FUNCTION(13, "SDIO_D3"), + STM32_FUNCTION(14, "DCMI_D4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(44, "PC12"), + STM32_FUNCTION(0, "GPIOC12"), + STM32_FUNCTION(7, "SPI3_MOSI I2S3_SD"), + STM32_FUNCTION(8, "USART3_CK"), + STM32_FUNCTION(9, "UART5_TX"), + STM32_FUNCTION(13, "SDIO_CK"), + STM32_FUNCTION(14, "DCMI_D9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(45, "PC13"), + STM32_FUNCTION(0, "GPIOC13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(46, "PC14"), + STM32_FUNCTION(0, "GPIOC14"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(47, "PC15"), + STM32_FUNCTION(0, "GPIOC15"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(48, "PD0"), + STM32_FUNCTION(0, "GPIOD0"), + STM32_FUNCTION(10, "CAN1_RX"), + STM32_FUNCTION(13, "FMC_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(49, "PD1"), + STM32_FUNCTION(0, "GPIOD1"), + STM32_FUNCTION(10, "CAN1_TX"), + STM32_FUNCTION(13, "FMC_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(50, "PD2"), + STM32_FUNCTION(0, "GPIOD2"), + STM32_FUNCTION(3, "TIM3_ETR"), + STM32_FUNCTION(9, "UART5_RX"), + STM32_FUNCTION(13, "SDIO_CMD"), + STM32_FUNCTION(14, "DCMI_D11"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(51, "PD3"), + STM32_FUNCTION(0, "GPIOD3"), + STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(8, "USART2_CTS"), + STM32_FUNCTION(13, "FMC_CLK"), + STM32_FUNCTION(14, "DCMI_D5"), + STM32_FUNCTION(15, "LCD_G7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(52, "PD4"), + STM32_FUNCTION(0, "GPIOD4"), + STM32_FUNCTION(8, "USART2_RTS"), + STM32_FUNCTION(13, "FMC_NOE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(53, "PD5"), + STM32_FUNCTION(0, "GPIOD5"), + STM32_FUNCTION(8, "USART2_TX"), + STM32_FUNCTION(13, "FMC_NWE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(54, "PD6"), + STM32_FUNCTION(0, "GPIOD6"), + STM32_FUNCTION(6, "SPI3_MOSI I2S3_SD"), + STM32_FUNCTION(7, "SAI1_SD_A"), + STM32_FUNCTION(8, "USART2_RX"), + STM32_FUNCTION(13, "FMC_NWAIT"), + STM32_FUNCTION(14, "DCMI_D10"), + STM32_FUNCTION(15, "LCD_B2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(55, "PD7"), + STM32_FUNCTION(0, "GPIOD7"), + STM32_FUNCTION(8, "USART2_CK"), + STM32_FUNCTION(13, "FMC_NE1 FMC_NCE2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(56, "PD8"), + STM32_FUNCTION(0, "GPIOD8"), + STM32_FUNCTION(8, "USART3_TX"), + STM32_FUNCTION(13, "FMC_D13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(57, "PD9"), + STM32_FUNCTION(0, "GPIOD9"), + STM32_FUNCTION(8, "USART3_RX"), + STM32_FUNCTION(13, "FMC_D14"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(58, "PD10"), + STM32_FUNCTION(0, "GPIOD10"), + STM32_FUNCTION(8, "USART3_CK"), + STM32_FUNCTION(13, "FMC_D15"), + STM32_FUNCTION(15, "LCD_B3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(59, "PD11"), + STM32_FUNCTION(0, "GPIOD11"), + STM32_FUNCTION(8, "USART3_CTS"), + STM32_FUNCTION(13, "FMC_A16"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(60, "PD12"), + STM32_FUNCTION(0, "GPIOD12"), + STM32_FUNCTION(3, "TIM4_CH1"), + STM32_FUNCTION(8, "USART3_RTS"), + STM32_FUNCTION(13, "FMC_A17"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(61, "PD13"), + STM32_FUNCTION(0, "GPIOD13"), + STM32_FUNCTION(3, "TIM4_CH2"), + STM32_FUNCTION(13, "FMC_A18"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(62, "PD14"), + STM32_FUNCTION(0, "GPIOD14"), + STM32_FUNCTION(3, "TIM4_CH3"), + STM32_FUNCTION(13, "FMC_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(63, "PD15"), + STM32_FUNCTION(0, "GPIOD15"), + STM32_FUNCTION(3, "TIM4_CH4"), + STM32_FUNCTION(13, "FMC_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(64, "PE0"), + STM32_FUNCTION(0, "GPIOE0"), + STM32_FUNCTION(3, "TIM4_ETR"), + STM32_FUNCTION(9, "UART8_RX"), + STM32_FUNCTION(13, "FMC_NBL0"), + STM32_FUNCTION(14, "DCMI_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(65, "PE1"), + STM32_FUNCTION(0, "GPIOE1"), + STM32_FUNCTION(9, "UART8_TX"), + STM32_FUNCTION(13, "FMC_NBL1"), + STM32_FUNCTION(14, "DCMI_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(66, "PE2"), + STM32_FUNCTION(0, "GPIOE2"), + STM32_FUNCTION(1, "TRACECLK"), + STM32_FUNCTION(6, "SPI4_SCK"), + STM32_FUNCTION(7, "SAI1_MCLK_A"), + STM32_FUNCTION(12, "ETH_MII_TXD3"), + STM32_FUNCTION(13, "FMC_A23"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(67, "PE3"), + STM32_FUNCTION(0, "GPIOE3"), + STM32_FUNCTION(1, "TRACED0"), + STM32_FUNCTION(7, "SAI1_SD_B"), + STM32_FUNCTION(13, "FMC_A19"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(68, "PE4"), + STM32_FUNCTION(0, "GPIOE4"), + STM32_FUNCTION(1, "TRACED1"), + STM32_FUNCTION(6, "SPI4_NSS"), + STM32_FUNCTION(7, "SAI1_FS_A"), + STM32_FUNCTION(13, "FMC_A20"), + STM32_FUNCTION(14, "DCMI_D4"), + STM32_FUNCTION(15, "LCD_B0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(69, "PE5"), + STM32_FUNCTION(0, "GPIOE5"), + STM32_FUNCTION(1, "TRACED2"), + STM32_FUNCTION(4, "TIM9_CH1"), + STM32_FUNCTION(6, "SPI4_MISO"), + STM32_FUNCTION(7, "SAI1_SCK_A"), + STM32_FUNCTION(13, "FMC_A21"), + STM32_FUNCTION(14, "DCMI_D6"), + STM32_FUNCTION(15, "LCD_G0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(70, "PE6"), + STM32_FUNCTION(0, "GPIOE6"), + STM32_FUNCTION(1, "TRACED3"), + STM32_FUNCTION(4, "TIM9_CH2"), + STM32_FUNCTION(6, "SPI4_MOSI"), + STM32_FUNCTION(7, "SAI1_SD_A"), + STM32_FUNCTION(13, "FMC_A22"), + STM32_FUNCTION(14, "DCMI_D7"), + STM32_FUNCTION(15, "LCD_G1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(71, "PE7"), + STM32_FUNCTION(0, "GPIOE7"), + STM32_FUNCTION(2, "TIM1_ETR"), + STM32_FUNCTION(9, "UART7_RX"), + STM32_FUNCTION(13, "FMC_D4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(72, "PE8"), + STM32_FUNCTION(0, "GPIOE8"), + STM32_FUNCTION(2, "TIM1_CH1N"), + STM32_FUNCTION(9, "UART7_TX"), + STM32_FUNCTION(13, "FMC_D5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(73, "PE9"), + STM32_FUNCTION(0, "GPIOE9"), + STM32_FUNCTION(2, "TIM1_CH1"), + STM32_FUNCTION(13, "FMC_D6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(74, "PE10"), + STM32_FUNCTION(0, "GPIOE10"), + STM32_FUNCTION(2, "TIM1_CH2N"), + STM32_FUNCTION(13, "FMC_D7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(75, "PE11"), + STM32_FUNCTION(0, "GPIOE11"), + STM32_FUNCTION(2, "TIM1_CH2"), + STM32_FUNCTION(6, "SPI4_NSS"), + STM32_FUNCTION(13, "FMC_D8"), + STM32_FUNCTION(15, "LCD_G3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(76, "PE12"), + STM32_FUNCTION(0, "GPIOE12"), + STM32_FUNCTION(2, "TIM1_CH3N"), + STM32_FUNCTION(6, "SPI4_SCK"), + STM32_FUNCTION(13, "FMC_D9"), + STM32_FUNCTION(15, "LCD_B4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(77, "PE13"), + STM32_FUNCTION(0, "GPIOE13"), + STM32_FUNCTION(2, "TIM1_CH3"), + STM32_FUNCTION(6, "SPI4_MISO"), + STM32_FUNCTION(13, "FMC_D10"), + STM32_FUNCTION(15, "LCD_DE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(78, "PE14"), + STM32_FUNCTION(0, "GPIOE14"), + STM32_FUNCTION(2, "TIM1_CH4"), + STM32_FUNCTION(6, "SPI4_MOSI"), + STM32_FUNCTION(13, "FMC_D11"), + STM32_FUNCTION(15, "LCD_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(79, "PE15"), + STM32_FUNCTION(0, "GPIOE15"), + STM32_FUNCTION(2, "TIM1_BKIN"), + STM32_FUNCTION(13, "FMC_D12"), + STM32_FUNCTION(15, "LCD_R7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(80, "PF0"), + STM32_FUNCTION(0, "GPIOF0"), + STM32_FUNCTION(5, "I2C2_SDA"), + STM32_FUNCTION(13, "FMC_A0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(81, "PF1"), + STM32_FUNCTION(0, "GPIOF1"), + STM32_FUNCTION(5, "I2C2_SCL"), + STM32_FUNCTION(13, "FMC_A1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(82, "PF2"), + STM32_FUNCTION(0, "GPIOF2"), + STM32_FUNCTION(5, "I2C2_SMBA"), + STM32_FUNCTION(13, "FMC_A2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(83, "PF3"), + STM32_FUNCTION(0, "GPIOF3"), + STM32_FUNCTION(13, "FMC_A3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(84, "PF4"), + STM32_FUNCTION(0, "GPIOF4"), + STM32_FUNCTION(13, "FMC_A4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(85, "PF5"), + STM32_FUNCTION(0, "GPIOF5"), + STM32_FUNCTION(13, "FMC_A5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(86, "PF6"), + STM32_FUNCTION(0, "GPIOF6"), + STM32_FUNCTION(4, "TIM10_CH1"), + STM32_FUNCTION(6, "SPI5_NSS"), + STM32_FUNCTION(7, "SAI1_SD_B"), + STM32_FUNCTION(9, "UART7_RX"), + STM32_FUNCTION(13, "FMC_NIORD"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(87, "PF7"), + STM32_FUNCTION(0, "GPIOF7"), + STM32_FUNCTION(4, "TIM11_CH1"), + STM32_FUNCTION(6, "SPI5_SCK"), + STM32_FUNCTION(7, "SAI1_MCLK_B"), + STM32_FUNCTION(9, "UART7_TX"), + STM32_FUNCTION(13, "FMC_NREG"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(88, "PF8"), + STM32_FUNCTION(0, "GPIOF8"), + STM32_FUNCTION(6, "SPI5_MISO"), + STM32_FUNCTION(7, "SAI1_SCK_B"), + STM32_FUNCTION(10, "TIM13_CH1"), + STM32_FUNCTION(13, "FMC_NIOWR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(89, "PF9"), + STM32_FUNCTION(0, "GPIOF9"), + STM32_FUNCTION(6, "SPI5_MOSI"), + STM32_FUNCTION(7, "SAI1_FS_B"), + STM32_FUNCTION(10, "TIM14_CH1"), + STM32_FUNCTION(13, "FMC_CD"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(90, "PF10"), + STM32_FUNCTION(0, "GPIOF10"), + STM32_FUNCTION(13, "FMC_INTR"), + STM32_FUNCTION(14, "DCMI_D11"), + STM32_FUNCTION(15, "LCD_DE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(91, "PF11"), + STM32_FUNCTION(0, "GPIOF11"), + STM32_FUNCTION(6, "SPI5_MOSI"), + STM32_FUNCTION(13, "FMC_SDNRAS"), + STM32_FUNCTION(14, "DCMI_D12"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(92, "PF12"), + STM32_FUNCTION(0, "GPIOF12"), + STM32_FUNCTION(13, "FMC_A6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(93, "PF13"), + STM32_FUNCTION(0, "GPIOF13"), + STM32_FUNCTION(13, "FMC_A7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(94, "PF14"), + STM32_FUNCTION(0, "GPIOF14"), + STM32_FUNCTION(13, "FMC_A8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(95, "PF15"), + STM32_FUNCTION(0, "GPIOF15"), + STM32_FUNCTION(13, "FMC_A9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(96, "PG0"), + STM32_FUNCTION(0, "GPIOG0"), + STM32_FUNCTION(13, "FMC_A10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(97, "PG1"), + STM32_FUNCTION(0, "GPIOG1"), + STM32_FUNCTION(13, "FMC_A11"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(98, "PG2"), + STM32_FUNCTION(0, "GPIOG2"), + STM32_FUNCTION(13, "FMC_A12"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(99, "PG3"), + STM32_FUNCTION(0, "GPIOG3"), + STM32_FUNCTION(13, "FMC_A13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(100, "PG4"), + STM32_FUNCTION(0, "GPIOG4"), + STM32_FUNCTION(13, "FMC_A14 FMC_BA0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(101, "PG5"), + STM32_FUNCTION(0, "GPIOG5"), + STM32_FUNCTION(13, "FMC_A15 FMC_BA1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(102, "PG6"), + STM32_FUNCTION(0, "GPIOG6"), + STM32_FUNCTION(13, "FMC_INT2"), + STM32_FUNCTION(14, "DCMI_D12"), + STM32_FUNCTION(15, "LCD_R7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(103, "PG7"), + STM32_FUNCTION(0, "GPIOG7"), + STM32_FUNCTION(9, "USART6_CK"), + STM32_FUNCTION(13, "FMC_INT3"), + STM32_FUNCTION(14, "DCMI_D13"), + STM32_FUNCTION(15, "LCD_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(104, "PG8"), + STM32_FUNCTION(0, "GPIOG8"), + STM32_FUNCTION(6, "SPI6_NSS"), + STM32_FUNCTION(9, "USART6_RTS"), + STM32_FUNCTION(12, "ETH_PPS_OUT"), + STM32_FUNCTION(13, "FMC_SDCLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(105, "PG9"), + STM32_FUNCTION(0, "GPIOG9"), + STM32_FUNCTION(9, "USART6_RX"), + STM32_FUNCTION(13, "FMC_NE2 FMC_NCE3"), + STM32_FUNCTION(14, "DCMI_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(106, "PG10"), + STM32_FUNCTION(0, "GPIOG10"), + STM32_FUNCTION(10, "LCD_G3"), + STM32_FUNCTION(13, "FMC_NCE4_1 FMC_NE3"), + STM32_FUNCTION(14, "DCMI_D2"), + STM32_FUNCTION(15, "LCD_B2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(107, "PG11"), + STM32_FUNCTION(0, "GPIOG11"), + STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"), + STM32_FUNCTION(13, "FMC_NCE4_2"), + STM32_FUNCTION(14, "DCMI_D3"), + STM32_FUNCTION(15, "LCD_B3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(108, "PG12"), + STM32_FUNCTION(0, "GPIOG12"), + STM32_FUNCTION(6, "SPI6_MISO"), + STM32_FUNCTION(9, "USART6_RTS"), + STM32_FUNCTION(10, "LCD_B4"), + STM32_FUNCTION(13, "FMC_NE4"), + STM32_FUNCTION(15, "LCD_B1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(109, "PG13"), + STM32_FUNCTION(0, "GPIOG13"), + STM32_FUNCTION(6, "SPI6_SCK"), + STM32_FUNCTION(9, "USART6_CTS"), + STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"), + STM32_FUNCTION(13, "FMC_A24"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(110, "PG14"), + STM32_FUNCTION(0, "GPIOG14"), + STM32_FUNCTION(6, "SPI6_MOSI"), + STM32_FUNCTION(9, "USART6_TX"), + STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"), + STM32_FUNCTION(13, "FMC_A25"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(111, "PG15"), + STM32_FUNCTION(0, "GPIOG15"), + STM32_FUNCTION(9, "USART6_CTS"), + STM32_FUNCTION(13, "FMC_SDNCAS"), + STM32_FUNCTION(14, "DCMI_D13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(112, "PH0"), + STM32_FUNCTION(0, "GPIOH0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(113, "PH1"), + STM32_FUNCTION(0, "GPIOH1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(114, "PH2"), + STM32_FUNCTION(0, "GPIOH2"), + STM32_FUNCTION(12, "ETH_MII_CRS"), + STM32_FUNCTION(13, "FMC_SDCKE0"), + STM32_FUNCTION(15, "LCD_R0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(115, "PH3"), + STM32_FUNCTION(0, "GPIOH3"), + STM32_FUNCTION(12, "ETH_MII_COL"), + STM32_FUNCTION(13, "FMC_SDNE0"), + STM32_FUNCTION(15, "LCD_R1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(116, "PH4"), + STM32_FUNCTION(0, "GPIOH4"), + STM32_FUNCTION(5, "I2C2_SCL"), + STM32_FUNCTION(11, "OTG_HS_ULPI_NXT"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(117, "PH5"), + STM32_FUNCTION(0, "GPIOH5"), + STM32_FUNCTION(5, "I2C2_SDA"), + STM32_FUNCTION(6, "SPI5_NSS"), + STM32_FUNCTION(13, "FMC_SDNWE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(118, "PH6"), + STM32_FUNCTION(0, "GPIOH6"), + STM32_FUNCTION(5, "I2C2_SMBA"), + STM32_FUNCTION(6, "SPI5_SCK"), + STM32_FUNCTION(10, "TIM12_CH1"), + STM32_FUNCTION(12, "ETH_MII_RXD2"), + STM32_FUNCTION(13, "FMC_SDNE1"), + STM32_FUNCTION(14, "DCMI_D8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(119, "PH7"), + STM32_FUNCTION(0, "GPIOH7"), + STM32_FUNCTION(5, "I2C3_SCL"), + STM32_FUNCTION(6, "SPI5_MISO"), + STM32_FUNCTION(12, "ETH_MII_RXD3"), + STM32_FUNCTION(13, "FMC_SDCKE1"), + STM32_FUNCTION(14, "DCMI_D9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(120, "PH8"), + STM32_FUNCTION(0, "GPIOH8"), + STM32_FUNCTION(5, "I2C3_SDA"), + STM32_FUNCTION(13, "FMC_D16"), + STM32_FUNCTION(14, "DCMI_HSYNC"), + STM32_FUNCTION(15, "LCD_R2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(121, "PH9"), + STM32_FUNCTION(0, "GPIOH9"), + STM32_FUNCTION(5, "I2C3_SMBA"), + STM32_FUNCTION(10, "TIM12_CH2"), + STM32_FUNCTION(13, "FMC_D17"), + STM32_FUNCTION(14, "DCMI_D0"), + STM32_FUNCTION(15, "LCD_R3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(122, "PH10"), + STM32_FUNCTION(0, "GPIOH10"), + STM32_FUNCTION(3, "TIM5_CH1"), + STM32_FUNCTION(13, "FMC_D18"), + STM32_FUNCTION(14, "DCMI_D1"), + STM32_FUNCTION(15, "LCD_R4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(123, "PH11"), + STM32_FUNCTION(0, "GPIOH11"), + STM32_FUNCTION(3, "TIM5_CH2"), + STM32_FUNCTION(13, "FMC_D19"), + STM32_FUNCTION(14, "DCMI_D2"), + STM32_FUNCTION(15, "LCD_R5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(124, "PH12"), + STM32_FUNCTION(0, "GPIOH12"), + STM32_FUNCTION(3, "TIM5_CH3"), + STM32_FUNCTION(13, "FMC_D20"), + STM32_FUNCTION(14, "DCMI_D3"), + STM32_FUNCTION(15, "LCD_R6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(125, "PH13"), + STM32_FUNCTION(0, "GPIOH13"), + STM32_FUNCTION(4, "TIM8_CH1N"), + STM32_FUNCTION(10, "CAN1_TX"), + STM32_FUNCTION(13, "FMC_D21"), + STM32_FUNCTION(15, "LCD_G2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(126, "PH14"), + STM32_FUNCTION(0, "GPIOH14"), + STM32_FUNCTION(4, "TIM8_CH2N"), + STM32_FUNCTION(13, "FMC_D22"), + STM32_FUNCTION(14, "DCMI_D4"), + STM32_FUNCTION(15, "LCD_G3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(127, "PH15"), + STM32_FUNCTION(0, "GPIOH15"), + STM32_FUNCTION(4, "TIM8_CH3N"), + STM32_FUNCTION(13, "FMC_D23"), + STM32_FUNCTION(14, "DCMI_D11"), + STM32_FUNCTION(15, "LCD_G4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(128, "PI0"), + STM32_FUNCTION(0, "GPIOI0"), + STM32_FUNCTION(3, "TIM5_CH4"), + STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"), + STM32_FUNCTION(13, "FMC_D24"), + STM32_FUNCTION(14, "DCMI_D13"), + STM32_FUNCTION(15, "LCD_G5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(129, "PI1"), + STM32_FUNCTION(0, "GPIOI1"), + STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(13, "FMC_D25"), + STM32_FUNCTION(14, "DCMI_D8"), + STM32_FUNCTION(15, "LCD_G6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(130, "PI2"), + STM32_FUNCTION(0, "GPIOI2"), + STM32_FUNCTION(4, "TIM8_CH4"), + STM32_FUNCTION(6, "SPI2_MISO"), + STM32_FUNCTION(7, "I2S2EXT_SD"), + STM32_FUNCTION(13, "FMC_D26"), + STM32_FUNCTION(14, "DCMI_D9"), + STM32_FUNCTION(15, "LCD_G7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(131, "PI3"), + STM32_FUNCTION(0, "GPIOI3"), + STM32_FUNCTION(4, "TIM8_ETR"), + STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"), + STM32_FUNCTION(13, "FMC_D27"), + STM32_FUNCTION(14, "DCMI_D10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(132, "PI4"), + STM32_FUNCTION(0, "GPIOI4"), + STM32_FUNCTION(4, "TIM8_BKIN"), + STM32_FUNCTION(13, "FMC_NBL2"), + STM32_FUNCTION(14, "DCMI_D5"), + STM32_FUNCTION(15, "LCD_B4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(133, "PI5"), + STM32_FUNCTION(0, "GPIOI5"), + STM32_FUNCTION(4, "TIM8_CH1"), + STM32_FUNCTION(13, "FMC_NBL3"), + STM32_FUNCTION(14, "DCMI_VSYNC"), + STM32_FUNCTION(15, "LCD_B5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(134, "PI6"), + STM32_FUNCTION(0, "GPIOI6"), + STM32_FUNCTION(4, "TIM8_CH2"), + STM32_FUNCTION(13, "FMC_D28"), + STM32_FUNCTION(14, "DCMI_D6"), + STM32_FUNCTION(15, "LCD_B6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(135, "PI7"), + STM32_FUNCTION(0, "GPIOI7"), + STM32_FUNCTION(4, "TIM8_CH3"), + STM32_FUNCTION(13, "FMC_D29"), + STM32_FUNCTION(14, "DCMI_D7"), + STM32_FUNCTION(15, "LCD_B7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(136, "PI8"), + STM32_FUNCTION(0, "GPIOI8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(137, "PI9"), + STM32_FUNCTION(0, "GPIOI9"), + STM32_FUNCTION(10, "CAN1_RX"), + STM32_FUNCTION(13, "FMC_D30"), + STM32_FUNCTION(15, "LCD_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(138, "PI10"), + STM32_FUNCTION(0, "GPIOI10"), + STM32_FUNCTION(12, "ETH_MII_RX_ER"), + STM32_FUNCTION(13, "FMC_D31"), + STM32_FUNCTION(15, "LCD_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(139, "PI11"), + STM32_FUNCTION(0, "GPIOI11"), + STM32_FUNCTION(11, "OTG_HS_ULPI_DIR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(140, "PI12"), + STM32_FUNCTION(0, "GPIOI12"), + STM32_FUNCTION(15, "LCD_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(141, "PI13"), + STM32_FUNCTION(0, "GPIOI13"), + STM32_FUNCTION(15, "LCD_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(142, "PI14"), + STM32_FUNCTION(0, "GPIOI14"), + STM32_FUNCTION(15, "LCD_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(143, "PI15"), + STM32_FUNCTION(0, "GPIOI15"), + STM32_FUNCTION(15, "LCD_R0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(144, "PJ0"), + STM32_FUNCTION(0, "GPIOJ0"), + STM32_FUNCTION(15, "LCD_R1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(145, "PJ1"), + STM32_FUNCTION(0, "GPIOJ1"), + STM32_FUNCTION(15, "LCD_R2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(146, "PJ2"), + STM32_FUNCTION(0, "GPIOJ2"), + STM32_FUNCTION(15, "LCD_R3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(147, "PJ3"), + STM32_FUNCTION(0, "GPIOJ3"), + STM32_FUNCTION(15, "LCD_R4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(148, "PJ4"), + STM32_FUNCTION(0, "GPIOJ4"), + STM32_FUNCTION(15, "LCD_R5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(149, "PJ5"), + STM32_FUNCTION(0, "GPIOJ5"), + STM32_FUNCTION(15, "LCD_R6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(150, "PJ6"), + STM32_FUNCTION(0, "GPIOJ6"), + STM32_FUNCTION(15, "LCD_R7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(151, "PJ7"), + STM32_FUNCTION(0, "GPIOJ7"), + STM32_FUNCTION(15, "LCD_G0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(152, "PJ8"), + STM32_FUNCTION(0, "GPIOJ8"), + STM32_FUNCTION(15, "LCD_G1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(153, "PJ9"), + STM32_FUNCTION(0, "GPIOJ9"), + STM32_FUNCTION(15, "LCD_G2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(154, "PJ10"), + STM32_FUNCTION(0, "GPIOJ10"), + STM32_FUNCTION(15, "LCD_G3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(155, "PJ11"), + STM32_FUNCTION(0, "GPIOJ11"), + STM32_FUNCTION(15, "LCD_G4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(156, "PJ12"), + STM32_FUNCTION(0, "GPIOJ12"), + STM32_FUNCTION(15, "LCD_B0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(157, "PJ13"), + STM32_FUNCTION(0, "GPIOJ13"), + STM32_FUNCTION(15, "LCD_B1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(158, "PJ14"), + STM32_FUNCTION(0, "GPIOJ14"), + STM32_FUNCTION(15, "LCD_B2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(159, "PJ15"), + STM32_FUNCTION(0, "GPIOJ15"), + STM32_FUNCTION(15, "LCD_B3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(160, "PK0"), + STM32_FUNCTION(0, "GPIOK0"), + STM32_FUNCTION(15, "LCD_G5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(161, "PK1"), + STM32_FUNCTION(0, "GPIOK1"), + STM32_FUNCTION(15, "LCD_G6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(162, "PK2"), + STM32_FUNCTION(0, "GPIOK2"), + STM32_FUNCTION(15, "LCD_G7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(163, "PK3"), + STM32_FUNCTION(0, "GPIOK3"), + STM32_FUNCTION(15, "LCD_B4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(164, "PK4"), + STM32_FUNCTION(0, "GPIOK4"), + STM32_FUNCTION(15, "LCD_B5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(165, "PK5"), + STM32_FUNCTION(0, "GPIOK5"), + STM32_FUNCTION(15, "LCD_B6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(166, "PK6"), + STM32_FUNCTION(0, "GPIOK6"), + STM32_FUNCTION(15, "LCD_B7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(167, "PK7"), + STM32_FUNCTION(0, "GPIOK7"), + STM32_FUNCTION(15, "LCD_DE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), +}; + +static struct stm32_pinctrl_match_data stm32f429_match_data = { + .pins = stm32f429_pins, + .npins = ARRAY_SIZE(stm32f429_pins), +}; + +static const struct of_device_id stm32f429_pctrl_match[] = { + { + .compatible = "st,stm32f429-pinctrl", + .data = &stm32f429_match_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, stm32f429_pctrl_match); + +static struct platform_driver stm32f429_pinctrl_driver = { + .probe = stm32_pctl_probe, + .driver = { + .name = "stm32f429-pinctrl", + .of_match_table = stm32f429_pctrl_match, + }, +}; + +static int __init stm32f429_pinctrl_init(void) +{ + return platform_driver_register(&stm32f429_pinctrl_driver); +} + +module_init(stm32f429_pinctrl_init); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("STM32F429 Pinctrl Driver"); +MODULE_AUTHOR("Maxime Coquelin <mcoquelin.stm32@gmail.com>"); -- 1.9.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v4 4/9] pinctrl: Add STM32 MCUs support @ 2016-01-14 12:16 ` Maxime Coquelin 0 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-01-14 12:16 UTC (permalink / raw) To: linux-arm-kernel This patch adds pinctrl and GPIO support to STMicroelectronic's STM32 family of MCUs. While it only supports STM32F429 for now, it has been designed to enable support of other MCUs of the family (e.g. STM32F746). Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> --- drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/stm32/Kconfig | 16 + drivers/pinctrl/stm32/Makefile | 5 + drivers/pinctrl/stm32/pinctrl-stm32.c | 834 +++++++++++++++ drivers/pinctrl/stm32/pinctrl-stm32.h | 43 + drivers/pinctrl/stm32/pinctrl-stm32f429.c | 1598 +++++++++++++++++++++++++++++ 7 files changed, 2498 insertions(+) create mode 100644 drivers/pinctrl/stm32/Kconfig create mode 100644 drivers/pinctrl/stm32/Makefile create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32.c create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32.h create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32f429.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 312c78b..c524bf5 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -256,6 +256,7 @@ source "drivers/pinctrl/qcom/Kconfig" source "drivers/pinctrl/samsung/Kconfig" source "drivers/pinctrl/sh-pfc/Kconfig" source "drivers/pinctrl/spear/Kconfig" +source "drivers/pinctrl/stm32/Kconfig" source "drivers/pinctrl/sunxi/Kconfig" source "drivers/pinctrl/uniphier/Kconfig" source "drivers/pinctrl/vt8500/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 738cb49..640079c 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -50,6 +50,7 @@ obj-$(CONFIG_ARCH_QCOM) += qcom/ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/ obj-$(CONFIG_PLAT_SPEAR) += spear/ +obj-$(CONFIG_ARCH_STM32) += stm32/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ obj-$(CONFIG_ARCH_VT8500) += vt8500/ diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig new file mode 100644 index 0000000..0f28841 --- /dev/null +++ b/drivers/pinctrl/stm32/Kconfig @@ -0,0 +1,16 @@ +if ARCH_STM32 || COMPILE_TEST + +config PINCTRL_STM32 + bool + depends on OF + select PINMUX + select GENERIC_PINCONF + select GPIOLIB + +config PINCTRL_STM32F429 + bool "STMicroelectronics STM32F429 pin control" if COMPILE_TEST && !MACH_STM32F429 + depends on OF + default MACH_STM32F429 + select PINCTRL_STM32 + +endif diff --git a/drivers/pinctrl/stm32/Makefile b/drivers/pinctrl/stm32/Makefile new file mode 100644 index 0000000..fc17d42 --- /dev/null +++ b/drivers/pinctrl/stm32/Makefile @@ -0,0 +1,5 @@ +# Core +obj-$(CONFIG_PINCTRL_STM32) += pinctrl-stm32.o + +# SoC Drivers +obj-$(CONFIG_PINCTRL_STM32F429) += pinctrl-stm32f429.o diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c new file mode 100644 index 0000000..d25d4a0 --- /dev/null +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -0,0 +1,834 @@ +/* + * Copyright (C) Maxime Coquelin 2015 + * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> + * License terms: GNU General Public License (GPL), version 2 + * + * Heavily based on Mediatek's pinctrl driver + */ +#include <linux/clk.h> +#include <linux/gpio.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/of_irq.h> +#include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/reset.h> +#include <linux/slab.h> + +#include <dt-bindings/pinctrl/pinctrl-stm32.h> + +#include "../core.h" +#include "../pinconf.h" +#include "../pinctrl-utils.h" +#include "pinctrl-stm32.h" + +#define STM32_GPIO_MODER 0x00 +#define STM32_GPIO_TYPER 0x04 +#define STM32_GPIO_SPEEDR 0x08 +#define STM32_GPIO_PUPDR 0x0c +#define STM32_GPIO_IDR 0x10 +#define STM32_GPIO_ODR 0x14 +#define STM32_GPIO_BSRR 0x18 +#define STM32_GPIO_LCKR 0x1c +#define STM32_GPIO_AFRL 0x20 +#define STM32_GPIO_AFRH 0x24 + +#define STM32_GPIO_PINS_PER_BANK 16 + +#define gpio_range_to_bank(chip) \ + container_of(chip, struct stm32_gpio_bank, range) + +#define gpio_chip_to_bank(chip) \ + container_of(chip, struct stm32_gpio_bank, gpio_chip) + +static const char * const stm32_gpio_functions[] = { + "gpio", "af0", "af1", + "af2", "af3", "af4", + "af5", "af6", "af7", + "af8", "af9", "af10", + "af11", "af12", "af13", + "af14", "af15", "analog", +}; + +struct stm32_pinctrl_group { + const char *name; + unsigned long config; + unsigned pin; +}; + +struct stm32_gpio_bank { + void __iomem *base; + struct clk *clk; + spinlock_t lock; + struct gpio_chip gpio_chip; + struct pinctrl_gpio_range range; +}; + +struct stm32_pinctrl { + struct device *dev; + struct pinctrl_dev *pctl_dev; + struct pinctrl_desc pctl_desc; + struct stm32_pinctrl_group *groups; + unsigned ngroups; + const char **grp_names; + struct stm32_gpio_bank *banks; + unsigned nbanks; + const struct stm32_pinctrl_match_data *match_data; +}; + +static inline int stm32_gpio_pin(int gpio) +{ + return gpio % STM32_GPIO_PINS_PER_BANK; +} + +static inline u32 stm32_gpio_get_mode(u32 function) +{ + switch (function) { + case STM32_PIN_GPIO: + return 0; + case STM32_PIN_AF(0) ... STM32_PIN_AF(15): + return 2; + case STM32_PIN_ANALOG: + return 3; + } + + return 0; +} + +static inline u32 stm32_gpio_get_alt(u32 function) +{ + switch (function) { + case STM32_PIN_GPIO: + return 0; + case STM32_PIN_AF(0) ... STM32_PIN_AF(15): + return function - 1; + case STM32_PIN_ANALOG: + return 0; + } + + return 0; +} + +/* GPIO functions */ + +static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, + unsigned offset, int value) +{ + if (!value) + offset += STM32_GPIO_PINS_PER_BANK; + + clk_enable(bank->clk); + + writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); + + clk_disable(bank->clk); +} + +static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + return pinctrl_request_gpio(chip->base + offset); +} + +static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + pinctrl_free_gpio(chip->base + offset); +} + +static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); + int ret; + + clk_enable(bank->clk); + + ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); + + clk_disable(bank->clk); + + return ret; +} + +static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); + + __stm32_gpio_set(bank, offset, value); +} + +static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + return pinctrl_gpio_direction_input(chip->base + offset); +} + +static int stm32_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); + + __stm32_gpio_set(bank, offset, value); + pinctrl_gpio_direction_output(chip->base + offset); + + return 0; +} + +static struct gpio_chip stm32_gpio_template = { + .request = stm32_gpio_request, + .free = stm32_gpio_free, + .get = stm32_gpio_get, + .set = stm32_gpio_set, + .direction_input = stm32_gpio_direction_input, + .direction_output = stm32_gpio_direction_output, +}; + +/* Pinctrl functions */ + +static struct stm32_pinctrl_group * +stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin) +{ + int i; + + for (i = 0; i < pctl->ngroups; i++) { + struct stm32_pinctrl_group *grp = pctl->groups + i; + + if (grp->pin == pin) + return grp; + } + + return NULL; +} + +static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl, + u32 pin_num, u32 fnum) +{ + int i; + + for (i = 0; i < pctl->match_data->npins; i++) { + const struct stm32_desc_pin *pin = pctl->match_data->pins + i; + const struct stm32_desc_function *func = pin->functions; + + if (pin->pin.number != pin_num) + continue; + + while (func && func->name) { + if (func->num == fnum) + return true; + func++; + } + + break; + } + + return false; +} + +static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl, + u32 pin, u32 fnum, struct stm32_pinctrl_group *grp, + struct pinctrl_map **map, unsigned *reserved_maps, + unsigned *num_maps) +{ + if (*num_maps == *reserved_maps) + return -ENOSPC; + + (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[*num_maps].data.mux.group = grp->name; + + if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) { + dev_err(pctl->dev, "invalid function %d on pin %d .\n", + fnum, pin); + return -EINVAL; + } + + (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum]; + (*num_maps)++; + + return 0; +} + +static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, + struct device_node *node, + struct pinctrl_map **map, + unsigned *reserved_maps, + unsigned *num_maps) +{ + struct stm32_pinctrl *pctl; + struct stm32_pinctrl_group *grp; + struct property *pins; + u32 pinfunc, pin, func; + unsigned long *configs; + unsigned int num_configs; + bool has_config = 0; + unsigned reserve = 0; + int num_pins, num_funcs, maps_per_pin, i, err; + + pctl = pinctrl_dev_get_drvdata(pctldev); + + pins = of_find_property(node, "pinmux", NULL); + if (!pins) { + dev_err(pctl->dev, "missing pins property in node %s .\n", + node->name); + return -EINVAL; + } + + err = pinconf_generic_parse_dt_config(node, pctldev, &configs, + &num_configs); + if (err) + return err; + + if (num_configs) + has_config = 1; + + num_pins = pins->length / sizeof(u32); + num_funcs = num_pins; + maps_per_pin = 0; + if (num_funcs) + maps_per_pin++; + if (has_config && num_pins >= 1) + maps_per_pin++; + + if (!num_pins || !maps_per_pin) + return -EINVAL; + + reserve = num_pins * maps_per_pin; + + err = pinctrl_utils_reserve_map(pctldev, map, + reserved_maps, num_maps, reserve); + if (err) + return err; + + for (i = 0; i < num_pins; i++) { + err = of_property_read_u32_index(node, "pinmux", + i, &pinfunc); + if (err) + return err; + + pin = STM32_GET_PIN_NO(pinfunc); + func = STM32_GET_PIN_FUNC(pinfunc); + + if (pin >= pctl->match_data->npins) { + dev_err(pctl->dev, "invalid pin number.\n"); + return -EINVAL; + } + + if (!stm32_pctrl_is_function_valid(pctl, pin, func)) { + dev_err(pctl->dev, "invalid function.\n"); + return -EINVAL; + } + + grp = stm32_pctrl_find_group_by_pin(pctl, pin); + if (!grp) { + dev_err(pctl->dev, "unable to match pin %d to group\n", + pin); + return -EINVAL; + } + + err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, + reserved_maps, num_maps); + if (err) + return err; + + if (has_config) { + err = pinctrl_utils_add_map_configs(pctldev, map, + reserved_maps, num_maps, grp->name, + configs, num_configs, + PIN_MAP_TYPE_CONFIGS_GROUP); + if (err) + return err; + } + } + + return 0; +} + +static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, unsigned *num_maps) +{ + struct device_node *np; + unsigned reserved_maps; + int ret; + + *map = NULL; + *num_maps = 0; + reserved_maps = 0; + + for_each_child_of_node(np_config, np) { + ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map, + &reserved_maps, num_maps); + if (ret < 0) { + pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); + return ret; + } + } + + return 0; +} + +static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->ngroups; +} + +static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->groups[group].name; +} + +static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *pins = (unsigned *)&pctl->groups[group].pin; + *num_pins = 1; + + return 0; +} + +static const struct pinctrl_ops stm32_pctrl_ops = { + .dt_node_to_map = stm32_pctrl_dt_node_to_map, + .dt_free_map = pinctrl_utils_dt_free_map, + .get_groups_count = stm32_pctrl_get_groups_count, + .get_group_name = stm32_pctrl_get_group_name, + .get_group_pins = stm32_pctrl_get_group_pins, +}; + + +/* Pinmux functions */ + +static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(stm32_gpio_functions); +} + +static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + return stm32_gpio_functions[selector]; +} + +static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char * const **groups, + unsigned * const num_groups) +{ + struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *groups = pctl->grp_names; + *num_groups = pctl->ngroups; + + return 0; +} + +static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank, + int pin, u32 mode, u32 alt) +{ + u32 val; + int alt_shift = (pin % 8) * 4; + int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; + unsigned long flags; + + clk_enable(bank->clk); + spin_lock_irqsave(&bank->lock, flags); + + val = readl_relaxed(bank->base + alt_offset); + val &= ~GENMASK(alt_shift + 3, alt_shift); + val |= (alt << alt_shift); + writel_relaxed(val, bank->base + alt_offset); + + val = readl_relaxed(bank->base + STM32_GPIO_MODER); + val &= ~GENMASK(pin * 2 + 1, pin * 2); + val |= mode << (pin * 2); + writel_relaxed(val, bank->base + STM32_GPIO_MODER); + + spin_unlock_irqrestore(&bank->lock, flags); + clk_disable(bank->clk); +} + +static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) +{ + bool ret; + struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct stm32_pinctrl_group *g = pctl->groups + group; + struct pinctrl_gpio_range *range; + struct stm32_gpio_bank *bank; + u32 mode, alt; + int pin; + + ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); + if (!ret) { + dev_err(pctl->dev, "invalid function %d on group %d .\n", + function, group); + return -EINVAL; + } + + range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); + bank = gpio_range_to_bank(range); + pin = stm32_gpio_pin(g->pin); + + mode = stm32_gpio_get_mode(function); + alt = stm32_gpio_get_alt(function); + + stm32_pmx_set_mode(bank, pin, mode, alt); + + return 0; +} + +static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, unsigned gpio, + bool input) +{ + struct stm32_gpio_bank *bank = gpio_range_to_bank(range); + int pin = stm32_gpio_pin(gpio); + + stm32_pmx_set_mode(bank, pin, !input, 0); + + return 0; +} + +static const struct pinmux_ops stm32_pmx_ops = { + .get_functions_count = stm32_pmx_get_funcs_cnt, + .get_function_name = stm32_pmx_get_func_name, + .get_function_groups = stm32_pmx_get_func_groups, + .set_mux = stm32_pmx_set_mux, + .gpio_set_direction = stm32_pmx_gpio_set_direction, +}; + +/* Pinconf functions */ + +static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank, + unsigned offset, u32 drive) +{ + unsigned long flags; + u32 val; + + clk_enable(bank->clk); + spin_lock_irqsave(&bank->lock, flags); + + val = readl_relaxed(bank->base + STM32_GPIO_TYPER); + val &= ~BIT(offset); + val |= drive << offset; + writel_relaxed(val, bank->base + STM32_GPIO_TYPER); + + spin_unlock_irqrestore(&bank->lock, flags); + clk_disable(bank->clk); +} + +static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank, + unsigned offset, u32 speed) +{ + unsigned long flags; + u32 val; + + clk_enable(bank->clk); + spin_lock_irqsave(&bank->lock, flags); + + val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); + val &= ~GENMASK(offset * 2 + 1, offset * 2); + val |= speed << (offset * 2); + writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); + + spin_unlock_irqrestore(&bank->lock, flags); + clk_disable(bank->clk); +} + +static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank, + unsigned offset, u32 bias) +{ + unsigned long flags; + u32 val; + + clk_enable(bank->clk); + spin_lock_irqsave(&bank->lock, flags); + + val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); + val &= ~GENMASK(offset * 2 + 1, offset * 2); + val |= bias << (offset * 2); + writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); + + spin_unlock_irqrestore(&bank->lock, flags); + clk_disable(bank->clk); +} + +static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, + unsigned int pin, enum pin_config_param param, + enum pin_config_param arg) +{ + struct pinctrl_gpio_range *range; + struct stm32_gpio_bank *bank; + int offset, ret = 0; + + range = pinctrl_find_gpio_range_from_pin(pctldev, pin); + bank = gpio_range_to_bank(range); + offset = stm32_gpio_pin(pin); + + switch (param) { + case PIN_CONFIG_DRIVE_PUSH_PULL: + stm32_pconf_set_driving(bank, offset, 0); + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + stm32_pconf_set_driving(bank, offset, 1); + break; + case PIN_CONFIG_SLEW_RATE: + stm32_pconf_set_speed(bank, offset, arg); + break; + case PIN_CONFIG_BIAS_DISABLE: + stm32_pconf_set_bias(bank, offset, 0); + break; + case PIN_CONFIG_BIAS_PULL_UP: + stm32_pconf_set_bias(bank, offset, 1); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + stm32_pconf_set_bias(bank, offset, 2); + break; + case PIN_CONFIG_OUTPUT: + __stm32_gpio_set(bank, offset, arg); + ret = stm32_pmx_gpio_set_direction(pctldev, NULL, pin, false); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static int stm32_pconf_group_get(struct pinctrl_dev *pctldev, + unsigned group, + unsigned long *config) +{ + struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *config = pctl->groups[group].config; + + return 0; +} + +static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, + unsigned long *configs, unsigned num_configs) +{ + struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct stm32_pinctrl_group *g = &pctl->groups[group]; + int i, ret; + + for (i = 0; i < num_configs; i++) { + ret = stm32_pconf_parse_conf(pctldev, g->pin, + pinconf_to_config_param(configs[i]), + pinconf_to_config_argument(configs[i])); + if (ret < 0) + return ret; + + g->config = configs[i]; + } + + return 0; +} + +static const struct pinconf_ops stm32_pconf_ops = { + .pin_config_group_get = stm32_pconf_group_get, + .pin_config_group_set = stm32_pconf_group_set, +}; + +static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, + struct device_node *np) +{ + int bank_nr = pctl->nbanks; + struct stm32_gpio_bank *bank = &pctl->banks[bank_nr]; + struct pinctrl_gpio_range *range = &bank->range; + struct device *dev = pctl->dev; + struct resource res; + struct reset_control *rstc; + int err, npins; + + rstc = of_reset_control_get(np, NULL); + if (!IS_ERR(rstc)) + reset_control_deassert(rstc); + + if (of_address_to_resource(np, 0, &res)) + return -ENODEV; + + bank->base = devm_ioremap_resource(dev, &res); + if (IS_ERR(bank->base)) + return PTR_ERR(bank->base); + + bank->clk = of_clk_get_by_name(np, NULL); + if (IS_ERR(bank->clk)) { + dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk)); + return PTR_ERR(bank->clk); + } + + err = clk_prepare(bank->clk); + if (err) { + dev_err(dev, "failed to prepare clk (%d)\n", err); + return err; + } + + npins = pctl->match_data->npins; + npins -= bank_nr * STM32_GPIO_PINS_PER_BANK; + if (npins < 0) + return -EINVAL; + else if (npins > STM32_GPIO_PINS_PER_BANK) + npins = STM32_GPIO_PINS_PER_BANK; + + bank->gpio_chip = stm32_gpio_template; + bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; + bank->gpio_chip.ngpio = npins; + bank->gpio_chip.of_node = np; + bank->gpio_chip.dev = dev; + spin_lock_init(&bank->lock); + + of_property_read_string(np, "st,bank-name", &range->name); + bank->gpio_chip.label = range->name; + + range->id = bank_nr; + range->pin_base = range->base = range->id * STM32_GPIO_PINS_PER_BANK; + range->npins = bank->gpio_chip.ngpio; + range->gc = &bank->gpio_chip; + err = gpiochip_add(&bank->gpio_chip); + if (err) { + dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr); + return err; + } + + dev_info(dev, "%s bank added\n", range->name); + return 0; +} + +static int stm32_pctrl_build_state(struct platform_device *pdev) +{ + struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); + int i; + + pctl->ngroups = pctl->match_data->npins; + + /* Allocate groups */ + pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, + sizeof(*pctl->groups), GFP_KERNEL); + if (!pctl->groups) + return -ENOMEM; + + /* We assume that one pin is one group, use pin name as group name. */ + pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, + sizeof(*pctl->grp_names), GFP_KERNEL); + if (!pctl->grp_names) + return -ENOMEM; + + for (i = 0; i < pctl->match_data->npins; i++) { + const struct stm32_desc_pin *pin = pctl->match_data->pins + i; + struct stm32_pinctrl_group *group = pctl->groups + i; + + group->name = pin->pin.name; + group->pin = pin->pin.number; + + pctl->grp_names[i] = pin->pin.name; + } + + return 0; +} + +int stm32_pctl_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct device_node *child; + const struct of_device_id *match; + struct device *dev = &pdev->dev; + struct stm32_pinctrl *pctl; + struct pinctrl_pin_desc *pins; + int i, ret, banks = 0; + + if (!np) + return -EINVAL; + + match = of_match_device(dev->driver->of_match_table, dev); + if (!match || !match->data) + return -EINVAL; + + if (!of_find_property(np, "pins-are-numbered", NULL)) { + dev_err(dev, "only support pins-are-numbered format\n"); + return -EINVAL; + } + + pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); + if (!pctl) + return -ENOMEM; + + platform_set_drvdata(pdev, pctl); + + pctl->dev = dev; + pctl->match_data = match->data; + ret = stm32_pctrl_build_state(pdev); + if (ret) { + dev_err(dev, "build state failed: %d\n", ret); + return -EINVAL; + } + + for_each_child_of_node(np, child) + if (of_property_read_bool(child, "gpio-controller")) + banks++; + + if (!banks) { + dev_err(dev, "at least one GPIO bank is required\n"); + return -EINVAL; + } + + pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), + GFP_KERNEL); + if (!pctl->banks) + return -ENOMEM; + + for_each_child_of_node(np, child) { + if (of_property_read_bool(child, "gpio-controller")) { + ret = stm32_gpiolib_register_bank(pctl, child); + if (ret) + return ret; + + pctl->nbanks++; + } + } + + pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins), + GFP_KERNEL); + if (!pins) + return -ENOMEM; + + for (i = 0; i < pctl->match_data->npins; i++) + pins[i] = pctl->match_data->pins[i].pin; + + pctl->pctl_desc.name = dev_name(&pdev->dev); + pctl->pctl_desc.owner = THIS_MODULE; + pctl->pctl_desc.pins = pins; + pctl->pctl_desc.npins = pctl->match_data->npins; + pctl->pctl_desc.confops = &stm32_pconf_ops; + pctl->pctl_desc.pctlops = &stm32_pctrl_ops; + pctl->pctl_desc.pmxops = &stm32_pmx_ops; + pctl->dev = &pdev->dev; + + pctl->pctl_dev = pinctrl_register(&pctl->pctl_desc, &pdev->dev, pctl); + if (!pctl->pctl_dev) { + dev_err(&pdev->dev, "Failed pinctrl registration\n"); + return -EINVAL; + } + + for (i = 0; i < pctl->nbanks; i++) + pinctrl_add_gpio_range(pctl->pctl_dev, &pctl->banks[i].range); + + dev_info(dev, "Pinctrl STM32 initialized\n"); + + return 0; +} + diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.h b/drivers/pinctrl/stm32/pinctrl-stm32.h new file mode 100644 index 0000000..1b7c369 --- /dev/null +++ b/drivers/pinctrl/stm32/pinctrl-stm32.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) Maxime Coquelin 2015 + * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> + * License terms: GNU General Public License (GPL), version 2 + */ +#ifndef __PINCTRL_STM32_H +#define __PINCTRL_STM32_H + +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinconf-generic.h> + +struct stm32_desc_function { + const char *name; + const unsigned char num; +}; + +struct stm32_desc_pin { + struct pinctrl_pin_desc pin; + const struct stm32_desc_function *functions; +}; + +#define STM32_PIN(_pin, ...) \ + { \ + .pin = _pin, \ + .functions = (struct stm32_desc_function[]){ \ + __VA_ARGS__, { } }, \ + } + +#define STM32_FUNCTION(_num, _name) \ + { \ + .num = _num, \ + .name = _name, \ + } + +struct stm32_pinctrl_match_data { + const struct stm32_desc_pin *pins; + const unsigned int npins; +}; + +int stm32_pctl_probe(struct platform_device *pdev); + +#endif /* __PINCTRL_STM32_H */ + diff --git a/drivers/pinctrl/stm32/pinctrl-stm32f429.c b/drivers/pinctrl/stm32/pinctrl-stm32f429.c new file mode 100644 index 0000000..f34016b --- /dev/null +++ b/drivers/pinctrl/stm32/pinctrl-stm32f429.c @@ -0,0 +1,1598 @@ +/* + * Copyright (C) Maxime Coquelin 2015 + * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> + * License terms: GNU General Public License (GPL), version 2 + */ +#include <linux/init.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-stm32.h" + +static const struct stm32_desc_pin stm32f429_pins[] = { + STM32_PIN( + PINCTRL_PIN(0, "PA0"), + STM32_FUNCTION(0, "GPIOA0"), + STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"), + STM32_FUNCTION(3, "TIM5_CH1"), + STM32_FUNCTION(4, "TIM8_ETR"), + STM32_FUNCTION(8, "USART2_CTS"), + STM32_FUNCTION(9, "UART4_TX"), + STM32_FUNCTION(12, "ETH_MII_CRS"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(1, "PA1"), + STM32_FUNCTION(0, "GPIOA1"), + STM32_FUNCTION(2, "TIM2_CH2"), + STM32_FUNCTION(3, "TIM5_CH2"), + STM32_FUNCTION(8, "USART2_RTS"), + STM32_FUNCTION(9, "UART4_RX"), + STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(2, "PA2"), + STM32_FUNCTION(0, "GPIOA2"), + STM32_FUNCTION(2, "TIM2_CH3"), + STM32_FUNCTION(3, "TIM5_CH3"), + STM32_FUNCTION(4, "TIM9_CH1"), + STM32_FUNCTION(8, "USART2_TX"), + STM32_FUNCTION(12, "ETH_MDIO"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(3, "PA3"), + STM32_FUNCTION(0, "GPIOA3"), + STM32_FUNCTION(2, "TIM2_CH4"), + STM32_FUNCTION(3, "TIM5_CH4"), + STM32_FUNCTION(4, "TIM9_CH2"), + STM32_FUNCTION(8, "USART2_RX"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D0"), + STM32_FUNCTION(12, "ETH_MII_COL"), + STM32_FUNCTION(15, "LCD_B5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(4, "PA4"), + STM32_FUNCTION(0, "GPIOA4"), + STM32_FUNCTION(6, "SPI1_NSS"), + STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"), + STM32_FUNCTION(8, "USART2_CK"), + STM32_FUNCTION(13, "OTG_HS_SOF"), + STM32_FUNCTION(14, "DCMI_HSYNC"), + STM32_FUNCTION(15, "LCD_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(5, "PA5"), + STM32_FUNCTION(0, "GPIOA5"), + STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"), + STM32_FUNCTION(4, "TIM8_CH1N"), + STM32_FUNCTION(6, "SPI1_SCK"), + STM32_FUNCTION(11, "OTG_HS_ULPI_CK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(6, "PA6"), + STM32_FUNCTION(0, "GPIOA6"), + STM32_FUNCTION(2, "TIM1_BKIN"), + STM32_FUNCTION(3, "TIM3_CH1"), + STM32_FUNCTION(4, "TIM8_BKIN"), + STM32_FUNCTION(6, "SPI1_MISO"), + STM32_FUNCTION(10, "TIM13_CH1"), + STM32_FUNCTION(14, "DCMI_PIXCLK"), + STM32_FUNCTION(15, "LCD_G2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(7, "PA7"), + STM32_FUNCTION(0, "GPIOA7"), + STM32_FUNCTION(2, "TIM1_CH1N"), + STM32_FUNCTION(3, "TIM3_CH2"), + STM32_FUNCTION(4, "TIM8_CH1N"), + STM32_FUNCTION(6, "SPI1_MOSI"), + STM32_FUNCTION(10, "TIM14_CH1"), + STM32_FUNCTION(12, "ETH_MII_RX_DV ETH_RMII_CRS_DV"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(8, "PA8"), + STM32_FUNCTION(0, "GPIOA8"), + STM32_FUNCTION(1, "MCO1"), + STM32_FUNCTION(2, "TIM1_CH1"), + STM32_FUNCTION(5, "I2C3_SCL"), + STM32_FUNCTION(8, "USART1_CK"), + STM32_FUNCTION(11, "OTG_FS_SOF"), + STM32_FUNCTION(15, "LCD_R6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(9, "PA9"), + STM32_FUNCTION(0, "GPIOA9"), + STM32_FUNCTION(2, "TIM1_CH2"), + STM32_FUNCTION(5, "I2C3_SMBA"), + STM32_FUNCTION(8, "USART1_TX"), + STM32_FUNCTION(14, "DCMI_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(10, "PA10"), + STM32_FUNCTION(0, "GPIOA10"), + STM32_FUNCTION(2, "TIM1_CH3"), + STM32_FUNCTION(8, "USART1_RX"), + STM32_FUNCTION(11, "OTG_FS_ID"), + STM32_FUNCTION(14, "DCMI_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(11, "PA11"), + STM32_FUNCTION(0, "GPIOA11"), + STM32_FUNCTION(2, "TIM1_CH4"), + STM32_FUNCTION(8, "USART1_CTS"), + STM32_FUNCTION(10, "CAN1_RX"), + STM32_FUNCTION(11, "OTG_FS_DM"), + STM32_FUNCTION(15, "LCD_R4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(12, "PA12"), + STM32_FUNCTION(0, "GPIOA12"), + STM32_FUNCTION(2, "TIM1_ETR"), + STM32_FUNCTION(8, "USART1_RTS"), + STM32_FUNCTION(10, "CAN1_TX"), + STM32_FUNCTION(11, "OTG_FS_DP"), + STM32_FUNCTION(15, "LCD_R5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(13, "PA13"), + STM32_FUNCTION(0, "GPIOA13"), + STM32_FUNCTION(1, "JTMS SWDIO"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(14, "PA14"), + STM32_FUNCTION(0, "GPIOA14"), + STM32_FUNCTION(1, "JTCK SWCLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(15, "PA15"), + STM32_FUNCTION(0, "GPIOA15"), + STM32_FUNCTION(1, "JTDI"), + STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"), + STM32_FUNCTION(6, "SPI1_NSS"), + STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(16, "PB0"), + STM32_FUNCTION(0, "GPIOB0"), + STM32_FUNCTION(2, "TIM1_CH2N"), + STM32_FUNCTION(3, "TIM3_CH3"), + STM32_FUNCTION(4, "TIM8_CH2N"), + STM32_FUNCTION(10, "LCD_R3"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D1"), + STM32_FUNCTION(12, "ETH_MII_RXD2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(17, "PB1"), + STM32_FUNCTION(0, "GPIOB1"), + STM32_FUNCTION(2, "TIM1_CH3N"), + STM32_FUNCTION(3, "TIM3_CH4"), + STM32_FUNCTION(4, "TIM8_CH3N"), + STM32_FUNCTION(10, "LCD_R6"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D2"), + STM32_FUNCTION(12, "ETH_MII_RXD3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(18, "PB2"), + STM32_FUNCTION(0, "GPIOB2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(19, "PB3"), + STM32_FUNCTION(0, "GPIOB3"), + STM32_FUNCTION(1, "JTDO TRACESWO"), + STM32_FUNCTION(2, "TIM2_CH2"), + STM32_FUNCTION(6, "SPI1_SCK"), + STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(20, "PB4"), + STM32_FUNCTION(0, "GPIOB4"), + STM32_FUNCTION(1, "NJTRST"), + STM32_FUNCTION(3, "TIM3_CH1"), + STM32_FUNCTION(6, "SPI1_MISO"), + STM32_FUNCTION(7, "SPI3_MISO"), + STM32_FUNCTION(8, "I2S3EXT_SD"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(21, "PB5"), + STM32_FUNCTION(0, "GPIOB5"), + STM32_FUNCTION(3, "TIM3_CH2"), + STM32_FUNCTION(5, "I2C1_SMBA"), + STM32_FUNCTION(6, "SPI1_MOSI"), + STM32_FUNCTION(7, "SPI3_MOSI I2S3_SD"), + STM32_FUNCTION(10, "CAN2_RX"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D7"), + STM32_FUNCTION(12, "ETH_PPS_OUT"), + STM32_FUNCTION(13, "FMC_SDCKE1"), + STM32_FUNCTION(14, "DCMI_D10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(22, "PB6"), + STM32_FUNCTION(0, "GPIOB6"), + STM32_FUNCTION(3, "TIM4_CH1"), + STM32_FUNCTION(5, "I2C1_SCL"), + STM32_FUNCTION(8, "USART1_TX"), + STM32_FUNCTION(10, "CAN2_TX"), + STM32_FUNCTION(13, "FMC_SDNE1"), + STM32_FUNCTION(14, "DCMI_D5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(23, "PB7"), + STM32_FUNCTION(0, "GPIOB7"), + STM32_FUNCTION(3, "TIM4_CH2"), + STM32_FUNCTION(5, "I2C1_SDA"), + STM32_FUNCTION(8, "USART1_RX"), + STM32_FUNCTION(13, "FMC_NL"), + STM32_FUNCTION(14, "DCMI_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(24, "PB8"), + STM32_FUNCTION(0, "GPIOB8"), + STM32_FUNCTION(3, "TIM4_CH3"), + STM32_FUNCTION(4, "TIM10_CH1"), + STM32_FUNCTION(5, "I2C1_SCL"), + STM32_FUNCTION(10, "CAN1_RX"), + STM32_FUNCTION(12, "ETH_MII_TXD3"), + STM32_FUNCTION(13, "SDIO_D4"), + STM32_FUNCTION(14, "DCMI_D6"), + STM32_FUNCTION(15, "LCD_B6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(25, "PB9"), + STM32_FUNCTION(0, "GPIOB9"), + STM32_FUNCTION(3, "TIM4_CH4"), + STM32_FUNCTION(4, "TIM11_CH1"), + STM32_FUNCTION(5, "I2C1_SDA"), + STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"), + STM32_FUNCTION(10, "CAN1_TX"), + STM32_FUNCTION(13, "SDIO_D5"), + STM32_FUNCTION(14, "DCMI_D7"), + STM32_FUNCTION(15, "LCD_B7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(26, "PB10"), + STM32_FUNCTION(0, "GPIOB10"), + STM32_FUNCTION(2, "TIM2_CH3"), + STM32_FUNCTION(5, "I2C2_SCL"), + STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(8, "USART3_TX"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D3"), + STM32_FUNCTION(12, "ETH_MII_RX_ER"), + STM32_FUNCTION(15, "LCD_G4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(27, "PB11"), + STM32_FUNCTION(0, "GPIOB11"), + STM32_FUNCTION(2, "TIM2_CH4"), + STM32_FUNCTION(5, "I2C2_SDA"), + STM32_FUNCTION(8, "USART3_RX"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D4"), + STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"), + STM32_FUNCTION(15, "LCD_G5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(28, "PB12"), + STM32_FUNCTION(0, "GPIOB12"), + STM32_FUNCTION(2, "TIM1_BKIN"), + STM32_FUNCTION(5, "I2C2_SMBA"), + STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"), + STM32_FUNCTION(8, "USART3_CK"), + STM32_FUNCTION(10, "CAN2_RX"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D5"), + STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"), + STM32_FUNCTION(13, "OTG_HS_ID"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(29, "PB13"), + STM32_FUNCTION(0, "GPIOB13"), + STM32_FUNCTION(2, "TIM1_CH1N"), + STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(8, "USART3_CTS"), + STM32_FUNCTION(10, "CAN2_TX"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D6"), + STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(30, "PB14"), + STM32_FUNCTION(0, "GPIOB14"), + STM32_FUNCTION(2, "TIM1_CH2N"), + STM32_FUNCTION(4, "TIM8_CH2N"), + STM32_FUNCTION(6, "SPI2_MISO"), + STM32_FUNCTION(7, "I2S2EXT_SD"), + STM32_FUNCTION(8, "USART3_RTS"), + STM32_FUNCTION(10, "TIM12_CH1"), + STM32_FUNCTION(13, "OTG_HS_DM"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(31, "PB15"), + STM32_FUNCTION(0, "GPIOB15"), + STM32_FUNCTION(1, "RTC_REFIN"), + STM32_FUNCTION(2, "TIM1_CH3N"), + STM32_FUNCTION(4, "TIM8_CH3N"), + STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"), + STM32_FUNCTION(10, "TIM12_CH2"), + STM32_FUNCTION(13, "OTG_HS_DP"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(32, "PC0"), + STM32_FUNCTION(0, "GPIOC0"), + STM32_FUNCTION(11, "OTG_HS_ULPI_STP"), + STM32_FUNCTION(13, "FMC_SDNWE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(33, "PC1"), + STM32_FUNCTION(0, "GPIOC1"), + STM32_FUNCTION(12, "ETH_MDC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(34, "PC2"), + STM32_FUNCTION(0, "GPIOC2"), + STM32_FUNCTION(6, "SPI2_MISO"), + STM32_FUNCTION(7, "I2S2EXT_SD"), + STM32_FUNCTION(11, "OTG_HS_ULPI_DIR"), + STM32_FUNCTION(12, "ETH_MII_TXD2"), + STM32_FUNCTION(13, "FMC_SDNE0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(35, "PC3"), + STM32_FUNCTION(0, "GPIOC3"), + STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"), + STM32_FUNCTION(11, "OTG_HS_ULPI_NXT"), + STM32_FUNCTION(12, "ETH_MII_TX_CLK"), + STM32_FUNCTION(13, "FMC_SDCKE0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(36, "PC4"), + STM32_FUNCTION(0, "GPIOC4"), + STM32_FUNCTION(12, "ETH_MII_RXD0 ETH_RMII_RXD0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(37, "PC5"), + STM32_FUNCTION(0, "GPIOC5"), + STM32_FUNCTION(12, "ETH_MII_RXD1 ETH_RMII_RXD1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(38, "PC6"), + STM32_FUNCTION(0, "GPIOC6"), + STM32_FUNCTION(3, "TIM3_CH1"), + STM32_FUNCTION(4, "TIM8_CH1"), + STM32_FUNCTION(6, "I2S2_MCK"), + STM32_FUNCTION(9, "USART6_TX"), + STM32_FUNCTION(13, "SDIO_D6"), + STM32_FUNCTION(14, "DCMI_D0"), + STM32_FUNCTION(15, "LCD_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(39, "PC7"), + STM32_FUNCTION(0, "GPIOC7"), + STM32_FUNCTION(3, "TIM3_CH2"), + STM32_FUNCTION(4, "TIM8_CH2"), + STM32_FUNCTION(7, "I2S3_MCK"), + STM32_FUNCTION(9, "USART6_RX"), + STM32_FUNCTION(13, "SDIO_D7"), + STM32_FUNCTION(14, "DCMI_D1"), + STM32_FUNCTION(15, "LCD_G6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(40, "PC8"), + STM32_FUNCTION(0, "GPIOC8"), + STM32_FUNCTION(3, "TIM3_CH3"), + STM32_FUNCTION(4, "TIM8_CH3"), + STM32_FUNCTION(9, "USART6_CK"), + STM32_FUNCTION(13, "SDIO_D0"), + STM32_FUNCTION(14, "DCMI_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(41, "PC9"), + STM32_FUNCTION(0, "GPIOC9"), + STM32_FUNCTION(1, "MCO2"), + STM32_FUNCTION(3, "TIM3_CH4"), + STM32_FUNCTION(4, "TIM8_CH4"), + STM32_FUNCTION(5, "I2C3_SDA"), + STM32_FUNCTION(6, "I2S_CKIN"), + STM32_FUNCTION(13, "SDIO_D1"), + STM32_FUNCTION(14, "DCMI_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(42, "PC10"), + STM32_FUNCTION(0, "GPIOC10"), + STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"), + STM32_FUNCTION(8, "USART3_TX"), + STM32_FUNCTION(9, "UART4_TX"), + STM32_FUNCTION(13, "SDIO_D2"), + STM32_FUNCTION(14, "DCMI_D8"), + STM32_FUNCTION(15, "LCD_R2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(43, "PC11"), + STM32_FUNCTION(0, "GPIOC11"), + STM32_FUNCTION(6, "I2S3EXT_SD"), + STM32_FUNCTION(7, "SPI3_MISO"), + STM32_FUNCTION(8, "USART3_RX"), + STM32_FUNCTION(9, "UART4_RX"), + STM32_FUNCTION(13, "SDIO_D3"), + STM32_FUNCTION(14, "DCMI_D4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(44, "PC12"), + STM32_FUNCTION(0, "GPIOC12"), + STM32_FUNCTION(7, "SPI3_MOSI I2S3_SD"), + STM32_FUNCTION(8, "USART3_CK"), + STM32_FUNCTION(9, "UART5_TX"), + STM32_FUNCTION(13, "SDIO_CK"), + STM32_FUNCTION(14, "DCMI_D9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(45, "PC13"), + STM32_FUNCTION(0, "GPIOC13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(46, "PC14"), + STM32_FUNCTION(0, "GPIOC14"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(47, "PC15"), + STM32_FUNCTION(0, "GPIOC15"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(48, "PD0"), + STM32_FUNCTION(0, "GPIOD0"), + STM32_FUNCTION(10, "CAN1_RX"), + STM32_FUNCTION(13, "FMC_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(49, "PD1"), + STM32_FUNCTION(0, "GPIOD1"), + STM32_FUNCTION(10, "CAN1_TX"), + STM32_FUNCTION(13, "FMC_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(50, "PD2"), + STM32_FUNCTION(0, "GPIOD2"), + STM32_FUNCTION(3, "TIM3_ETR"), + STM32_FUNCTION(9, "UART5_RX"), + STM32_FUNCTION(13, "SDIO_CMD"), + STM32_FUNCTION(14, "DCMI_D11"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(51, "PD3"), + STM32_FUNCTION(0, "GPIOD3"), + STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(8, "USART2_CTS"), + STM32_FUNCTION(13, "FMC_CLK"), + STM32_FUNCTION(14, "DCMI_D5"), + STM32_FUNCTION(15, "LCD_G7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(52, "PD4"), + STM32_FUNCTION(0, "GPIOD4"), + STM32_FUNCTION(8, "USART2_RTS"), + STM32_FUNCTION(13, "FMC_NOE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(53, "PD5"), + STM32_FUNCTION(0, "GPIOD5"), + STM32_FUNCTION(8, "USART2_TX"), + STM32_FUNCTION(13, "FMC_NWE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(54, "PD6"), + STM32_FUNCTION(0, "GPIOD6"), + STM32_FUNCTION(6, "SPI3_MOSI I2S3_SD"), + STM32_FUNCTION(7, "SAI1_SD_A"), + STM32_FUNCTION(8, "USART2_RX"), + STM32_FUNCTION(13, "FMC_NWAIT"), + STM32_FUNCTION(14, "DCMI_D10"), + STM32_FUNCTION(15, "LCD_B2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(55, "PD7"), + STM32_FUNCTION(0, "GPIOD7"), + STM32_FUNCTION(8, "USART2_CK"), + STM32_FUNCTION(13, "FMC_NE1 FMC_NCE2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(56, "PD8"), + STM32_FUNCTION(0, "GPIOD8"), + STM32_FUNCTION(8, "USART3_TX"), + STM32_FUNCTION(13, "FMC_D13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(57, "PD9"), + STM32_FUNCTION(0, "GPIOD9"), + STM32_FUNCTION(8, "USART3_RX"), + STM32_FUNCTION(13, "FMC_D14"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(58, "PD10"), + STM32_FUNCTION(0, "GPIOD10"), + STM32_FUNCTION(8, "USART3_CK"), + STM32_FUNCTION(13, "FMC_D15"), + STM32_FUNCTION(15, "LCD_B3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(59, "PD11"), + STM32_FUNCTION(0, "GPIOD11"), + STM32_FUNCTION(8, "USART3_CTS"), + STM32_FUNCTION(13, "FMC_A16"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(60, "PD12"), + STM32_FUNCTION(0, "GPIOD12"), + STM32_FUNCTION(3, "TIM4_CH1"), + STM32_FUNCTION(8, "USART3_RTS"), + STM32_FUNCTION(13, "FMC_A17"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(61, "PD13"), + STM32_FUNCTION(0, "GPIOD13"), + STM32_FUNCTION(3, "TIM4_CH2"), + STM32_FUNCTION(13, "FMC_A18"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(62, "PD14"), + STM32_FUNCTION(0, "GPIOD14"), + STM32_FUNCTION(3, "TIM4_CH3"), + STM32_FUNCTION(13, "FMC_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(63, "PD15"), + STM32_FUNCTION(0, "GPIOD15"), + STM32_FUNCTION(3, "TIM4_CH4"), + STM32_FUNCTION(13, "FMC_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(64, "PE0"), + STM32_FUNCTION(0, "GPIOE0"), + STM32_FUNCTION(3, "TIM4_ETR"), + STM32_FUNCTION(9, "UART8_RX"), + STM32_FUNCTION(13, "FMC_NBL0"), + STM32_FUNCTION(14, "DCMI_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(65, "PE1"), + STM32_FUNCTION(0, "GPIOE1"), + STM32_FUNCTION(9, "UART8_TX"), + STM32_FUNCTION(13, "FMC_NBL1"), + STM32_FUNCTION(14, "DCMI_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(66, "PE2"), + STM32_FUNCTION(0, "GPIOE2"), + STM32_FUNCTION(1, "TRACECLK"), + STM32_FUNCTION(6, "SPI4_SCK"), + STM32_FUNCTION(7, "SAI1_MCLK_A"), + STM32_FUNCTION(12, "ETH_MII_TXD3"), + STM32_FUNCTION(13, "FMC_A23"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(67, "PE3"), + STM32_FUNCTION(0, "GPIOE3"), + STM32_FUNCTION(1, "TRACED0"), + STM32_FUNCTION(7, "SAI1_SD_B"), + STM32_FUNCTION(13, "FMC_A19"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(68, "PE4"), + STM32_FUNCTION(0, "GPIOE4"), + STM32_FUNCTION(1, "TRACED1"), + STM32_FUNCTION(6, "SPI4_NSS"), + STM32_FUNCTION(7, "SAI1_FS_A"), + STM32_FUNCTION(13, "FMC_A20"), + STM32_FUNCTION(14, "DCMI_D4"), + STM32_FUNCTION(15, "LCD_B0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(69, "PE5"), + STM32_FUNCTION(0, "GPIOE5"), + STM32_FUNCTION(1, "TRACED2"), + STM32_FUNCTION(4, "TIM9_CH1"), + STM32_FUNCTION(6, "SPI4_MISO"), + STM32_FUNCTION(7, "SAI1_SCK_A"), + STM32_FUNCTION(13, "FMC_A21"), + STM32_FUNCTION(14, "DCMI_D6"), + STM32_FUNCTION(15, "LCD_G0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(70, "PE6"), + STM32_FUNCTION(0, "GPIOE6"), + STM32_FUNCTION(1, "TRACED3"), + STM32_FUNCTION(4, "TIM9_CH2"), + STM32_FUNCTION(6, "SPI4_MOSI"), + STM32_FUNCTION(7, "SAI1_SD_A"), + STM32_FUNCTION(13, "FMC_A22"), + STM32_FUNCTION(14, "DCMI_D7"), + STM32_FUNCTION(15, "LCD_G1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(71, "PE7"), + STM32_FUNCTION(0, "GPIOE7"), + STM32_FUNCTION(2, "TIM1_ETR"), + STM32_FUNCTION(9, "UART7_RX"), + STM32_FUNCTION(13, "FMC_D4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(72, "PE8"), + STM32_FUNCTION(0, "GPIOE8"), + STM32_FUNCTION(2, "TIM1_CH1N"), + STM32_FUNCTION(9, "UART7_TX"), + STM32_FUNCTION(13, "FMC_D5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(73, "PE9"), + STM32_FUNCTION(0, "GPIOE9"), + STM32_FUNCTION(2, "TIM1_CH1"), + STM32_FUNCTION(13, "FMC_D6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(74, "PE10"), + STM32_FUNCTION(0, "GPIOE10"), + STM32_FUNCTION(2, "TIM1_CH2N"), + STM32_FUNCTION(13, "FMC_D7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(75, "PE11"), + STM32_FUNCTION(0, "GPIOE11"), + STM32_FUNCTION(2, "TIM1_CH2"), + STM32_FUNCTION(6, "SPI4_NSS"), + STM32_FUNCTION(13, "FMC_D8"), + STM32_FUNCTION(15, "LCD_G3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(76, "PE12"), + STM32_FUNCTION(0, "GPIOE12"), + STM32_FUNCTION(2, "TIM1_CH3N"), + STM32_FUNCTION(6, "SPI4_SCK"), + STM32_FUNCTION(13, "FMC_D9"), + STM32_FUNCTION(15, "LCD_B4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(77, "PE13"), + STM32_FUNCTION(0, "GPIOE13"), + STM32_FUNCTION(2, "TIM1_CH3"), + STM32_FUNCTION(6, "SPI4_MISO"), + STM32_FUNCTION(13, "FMC_D10"), + STM32_FUNCTION(15, "LCD_DE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(78, "PE14"), + STM32_FUNCTION(0, "GPIOE14"), + STM32_FUNCTION(2, "TIM1_CH4"), + STM32_FUNCTION(6, "SPI4_MOSI"), + STM32_FUNCTION(13, "FMC_D11"), + STM32_FUNCTION(15, "LCD_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(79, "PE15"), + STM32_FUNCTION(0, "GPIOE15"), + STM32_FUNCTION(2, "TIM1_BKIN"), + STM32_FUNCTION(13, "FMC_D12"), + STM32_FUNCTION(15, "LCD_R7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(80, "PF0"), + STM32_FUNCTION(0, "GPIOF0"), + STM32_FUNCTION(5, "I2C2_SDA"), + STM32_FUNCTION(13, "FMC_A0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(81, "PF1"), + STM32_FUNCTION(0, "GPIOF1"), + STM32_FUNCTION(5, "I2C2_SCL"), + STM32_FUNCTION(13, "FMC_A1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(82, "PF2"), + STM32_FUNCTION(0, "GPIOF2"), + STM32_FUNCTION(5, "I2C2_SMBA"), + STM32_FUNCTION(13, "FMC_A2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(83, "PF3"), + STM32_FUNCTION(0, "GPIOF3"), + STM32_FUNCTION(13, "FMC_A3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(84, "PF4"), + STM32_FUNCTION(0, "GPIOF4"), + STM32_FUNCTION(13, "FMC_A4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(85, "PF5"), + STM32_FUNCTION(0, "GPIOF5"), + STM32_FUNCTION(13, "FMC_A5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(86, "PF6"), + STM32_FUNCTION(0, "GPIOF6"), + STM32_FUNCTION(4, "TIM10_CH1"), + STM32_FUNCTION(6, "SPI5_NSS"), + STM32_FUNCTION(7, "SAI1_SD_B"), + STM32_FUNCTION(9, "UART7_RX"), + STM32_FUNCTION(13, "FMC_NIORD"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(87, "PF7"), + STM32_FUNCTION(0, "GPIOF7"), + STM32_FUNCTION(4, "TIM11_CH1"), + STM32_FUNCTION(6, "SPI5_SCK"), + STM32_FUNCTION(7, "SAI1_MCLK_B"), + STM32_FUNCTION(9, "UART7_TX"), + STM32_FUNCTION(13, "FMC_NREG"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(88, "PF8"), + STM32_FUNCTION(0, "GPIOF8"), + STM32_FUNCTION(6, "SPI5_MISO"), + STM32_FUNCTION(7, "SAI1_SCK_B"), + STM32_FUNCTION(10, "TIM13_CH1"), + STM32_FUNCTION(13, "FMC_NIOWR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(89, "PF9"), + STM32_FUNCTION(0, "GPIOF9"), + STM32_FUNCTION(6, "SPI5_MOSI"), + STM32_FUNCTION(7, "SAI1_FS_B"), + STM32_FUNCTION(10, "TIM14_CH1"), + STM32_FUNCTION(13, "FMC_CD"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(90, "PF10"), + STM32_FUNCTION(0, "GPIOF10"), + STM32_FUNCTION(13, "FMC_INTR"), + STM32_FUNCTION(14, "DCMI_D11"), + STM32_FUNCTION(15, "LCD_DE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(91, "PF11"), + STM32_FUNCTION(0, "GPIOF11"), + STM32_FUNCTION(6, "SPI5_MOSI"), + STM32_FUNCTION(13, "FMC_SDNRAS"), + STM32_FUNCTION(14, "DCMI_D12"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(92, "PF12"), + STM32_FUNCTION(0, "GPIOF12"), + STM32_FUNCTION(13, "FMC_A6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(93, "PF13"), + STM32_FUNCTION(0, "GPIOF13"), + STM32_FUNCTION(13, "FMC_A7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(94, "PF14"), + STM32_FUNCTION(0, "GPIOF14"), + STM32_FUNCTION(13, "FMC_A8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(95, "PF15"), + STM32_FUNCTION(0, "GPIOF15"), + STM32_FUNCTION(13, "FMC_A9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(96, "PG0"), + STM32_FUNCTION(0, "GPIOG0"), + STM32_FUNCTION(13, "FMC_A10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(97, "PG1"), + STM32_FUNCTION(0, "GPIOG1"), + STM32_FUNCTION(13, "FMC_A11"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(98, "PG2"), + STM32_FUNCTION(0, "GPIOG2"), + STM32_FUNCTION(13, "FMC_A12"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(99, "PG3"), + STM32_FUNCTION(0, "GPIOG3"), + STM32_FUNCTION(13, "FMC_A13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(100, "PG4"), + STM32_FUNCTION(0, "GPIOG4"), + STM32_FUNCTION(13, "FMC_A14 FMC_BA0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(101, "PG5"), + STM32_FUNCTION(0, "GPIOG5"), + STM32_FUNCTION(13, "FMC_A15 FMC_BA1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(102, "PG6"), + STM32_FUNCTION(0, "GPIOG6"), + STM32_FUNCTION(13, "FMC_INT2"), + STM32_FUNCTION(14, "DCMI_D12"), + STM32_FUNCTION(15, "LCD_R7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(103, "PG7"), + STM32_FUNCTION(0, "GPIOG7"), + STM32_FUNCTION(9, "USART6_CK"), + STM32_FUNCTION(13, "FMC_INT3"), + STM32_FUNCTION(14, "DCMI_D13"), + STM32_FUNCTION(15, "LCD_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(104, "PG8"), + STM32_FUNCTION(0, "GPIOG8"), + STM32_FUNCTION(6, "SPI6_NSS"), + STM32_FUNCTION(9, "USART6_RTS"), + STM32_FUNCTION(12, "ETH_PPS_OUT"), + STM32_FUNCTION(13, "FMC_SDCLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(105, "PG9"), + STM32_FUNCTION(0, "GPIOG9"), + STM32_FUNCTION(9, "USART6_RX"), + STM32_FUNCTION(13, "FMC_NE2 FMC_NCE3"), + STM32_FUNCTION(14, "DCMI_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(106, "PG10"), + STM32_FUNCTION(0, "GPIOG10"), + STM32_FUNCTION(10, "LCD_G3"), + STM32_FUNCTION(13, "FMC_NCE4_1 FMC_NE3"), + STM32_FUNCTION(14, "DCMI_D2"), + STM32_FUNCTION(15, "LCD_B2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(107, "PG11"), + STM32_FUNCTION(0, "GPIOG11"), + STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"), + STM32_FUNCTION(13, "FMC_NCE4_2"), + STM32_FUNCTION(14, "DCMI_D3"), + STM32_FUNCTION(15, "LCD_B3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(108, "PG12"), + STM32_FUNCTION(0, "GPIOG12"), + STM32_FUNCTION(6, "SPI6_MISO"), + STM32_FUNCTION(9, "USART6_RTS"), + STM32_FUNCTION(10, "LCD_B4"), + STM32_FUNCTION(13, "FMC_NE4"), + STM32_FUNCTION(15, "LCD_B1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(109, "PG13"), + STM32_FUNCTION(0, "GPIOG13"), + STM32_FUNCTION(6, "SPI6_SCK"), + STM32_FUNCTION(9, "USART6_CTS"), + STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"), + STM32_FUNCTION(13, "FMC_A24"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(110, "PG14"), + STM32_FUNCTION(0, "GPIOG14"), + STM32_FUNCTION(6, "SPI6_MOSI"), + STM32_FUNCTION(9, "USART6_TX"), + STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"), + STM32_FUNCTION(13, "FMC_A25"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(111, "PG15"), + STM32_FUNCTION(0, "GPIOG15"), + STM32_FUNCTION(9, "USART6_CTS"), + STM32_FUNCTION(13, "FMC_SDNCAS"), + STM32_FUNCTION(14, "DCMI_D13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(112, "PH0"), + STM32_FUNCTION(0, "GPIOH0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(113, "PH1"), + STM32_FUNCTION(0, "GPIOH1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(114, "PH2"), + STM32_FUNCTION(0, "GPIOH2"), + STM32_FUNCTION(12, "ETH_MII_CRS"), + STM32_FUNCTION(13, "FMC_SDCKE0"), + STM32_FUNCTION(15, "LCD_R0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(115, "PH3"), + STM32_FUNCTION(0, "GPIOH3"), + STM32_FUNCTION(12, "ETH_MII_COL"), + STM32_FUNCTION(13, "FMC_SDNE0"), + STM32_FUNCTION(15, "LCD_R1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(116, "PH4"), + STM32_FUNCTION(0, "GPIOH4"), + STM32_FUNCTION(5, "I2C2_SCL"), + STM32_FUNCTION(11, "OTG_HS_ULPI_NXT"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(117, "PH5"), + STM32_FUNCTION(0, "GPIOH5"), + STM32_FUNCTION(5, "I2C2_SDA"), + STM32_FUNCTION(6, "SPI5_NSS"), + STM32_FUNCTION(13, "FMC_SDNWE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(118, "PH6"), + STM32_FUNCTION(0, "GPIOH6"), + STM32_FUNCTION(5, "I2C2_SMBA"), + STM32_FUNCTION(6, "SPI5_SCK"), + STM32_FUNCTION(10, "TIM12_CH1"), + STM32_FUNCTION(12, "ETH_MII_RXD2"), + STM32_FUNCTION(13, "FMC_SDNE1"), + STM32_FUNCTION(14, "DCMI_D8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(119, "PH7"), + STM32_FUNCTION(0, "GPIOH7"), + STM32_FUNCTION(5, "I2C3_SCL"), + STM32_FUNCTION(6, "SPI5_MISO"), + STM32_FUNCTION(12, "ETH_MII_RXD3"), + STM32_FUNCTION(13, "FMC_SDCKE1"), + STM32_FUNCTION(14, "DCMI_D9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(120, "PH8"), + STM32_FUNCTION(0, "GPIOH8"), + STM32_FUNCTION(5, "I2C3_SDA"), + STM32_FUNCTION(13, "FMC_D16"), + STM32_FUNCTION(14, "DCMI_HSYNC"), + STM32_FUNCTION(15, "LCD_R2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(121, "PH9"), + STM32_FUNCTION(0, "GPIOH9"), + STM32_FUNCTION(5, "I2C3_SMBA"), + STM32_FUNCTION(10, "TIM12_CH2"), + STM32_FUNCTION(13, "FMC_D17"), + STM32_FUNCTION(14, "DCMI_D0"), + STM32_FUNCTION(15, "LCD_R3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(122, "PH10"), + STM32_FUNCTION(0, "GPIOH10"), + STM32_FUNCTION(3, "TIM5_CH1"), + STM32_FUNCTION(13, "FMC_D18"), + STM32_FUNCTION(14, "DCMI_D1"), + STM32_FUNCTION(15, "LCD_R4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(123, "PH11"), + STM32_FUNCTION(0, "GPIOH11"), + STM32_FUNCTION(3, "TIM5_CH2"), + STM32_FUNCTION(13, "FMC_D19"), + STM32_FUNCTION(14, "DCMI_D2"), + STM32_FUNCTION(15, "LCD_R5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(124, "PH12"), + STM32_FUNCTION(0, "GPIOH12"), + STM32_FUNCTION(3, "TIM5_CH3"), + STM32_FUNCTION(13, "FMC_D20"), + STM32_FUNCTION(14, "DCMI_D3"), + STM32_FUNCTION(15, "LCD_R6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(125, "PH13"), + STM32_FUNCTION(0, "GPIOH13"), + STM32_FUNCTION(4, "TIM8_CH1N"), + STM32_FUNCTION(10, "CAN1_TX"), + STM32_FUNCTION(13, "FMC_D21"), + STM32_FUNCTION(15, "LCD_G2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(126, "PH14"), + STM32_FUNCTION(0, "GPIOH14"), + STM32_FUNCTION(4, "TIM8_CH2N"), + STM32_FUNCTION(13, "FMC_D22"), + STM32_FUNCTION(14, "DCMI_D4"), + STM32_FUNCTION(15, "LCD_G3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(127, "PH15"), + STM32_FUNCTION(0, "GPIOH15"), + STM32_FUNCTION(4, "TIM8_CH3N"), + STM32_FUNCTION(13, "FMC_D23"), + STM32_FUNCTION(14, "DCMI_D11"), + STM32_FUNCTION(15, "LCD_G4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(128, "PI0"), + STM32_FUNCTION(0, "GPIOI0"), + STM32_FUNCTION(3, "TIM5_CH4"), + STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"), + STM32_FUNCTION(13, "FMC_D24"), + STM32_FUNCTION(14, "DCMI_D13"), + STM32_FUNCTION(15, "LCD_G5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(129, "PI1"), + STM32_FUNCTION(0, "GPIOI1"), + STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(13, "FMC_D25"), + STM32_FUNCTION(14, "DCMI_D8"), + STM32_FUNCTION(15, "LCD_G6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(130, "PI2"), + STM32_FUNCTION(0, "GPIOI2"), + STM32_FUNCTION(4, "TIM8_CH4"), + STM32_FUNCTION(6, "SPI2_MISO"), + STM32_FUNCTION(7, "I2S2EXT_SD"), + STM32_FUNCTION(13, "FMC_D26"), + STM32_FUNCTION(14, "DCMI_D9"), + STM32_FUNCTION(15, "LCD_G7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(131, "PI3"), + STM32_FUNCTION(0, "GPIOI3"), + STM32_FUNCTION(4, "TIM8_ETR"), + STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"), + STM32_FUNCTION(13, "FMC_D27"), + STM32_FUNCTION(14, "DCMI_D10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(132, "PI4"), + STM32_FUNCTION(0, "GPIOI4"), + STM32_FUNCTION(4, "TIM8_BKIN"), + STM32_FUNCTION(13, "FMC_NBL2"), + STM32_FUNCTION(14, "DCMI_D5"), + STM32_FUNCTION(15, "LCD_B4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(133, "PI5"), + STM32_FUNCTION(0, "GPIOI5"), + STM32_FUNCTION(4, "TIM8_CH1"), + STM32_FUNCTION(13, "FMC_NBL3"), + STM32_FUNCTION(14, "DCMI_VSYNC"), + STM32_FUNCTION(15, "LCD_B5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(134, "PI6"), + STM32_FUNCTION(0, "GPIOI6"), + STM32_FUNCTION(4, "TIM8_CH2"), + STM32_FUNCTION(13, "FMC_D28"), + STM32_FUNCTION(14, "DCMI_D6"), + STM32_FUNCTION(15, "LCD_B6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(135, "PI7"), + STM32_FUNCTION(0, "GPIOI7"), + STM32_FUNCTION(4, "TIM8_CH3"), + STM32_FUNCTION(13, "FMC_D29"), + STM32_FUNCTION(14, "DCMI_D7"), + STM32_FUNCTION(15, "LCD_B7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(136, "PI8"), + STM32_FUNCTION(0, "GPIOI8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(137, "PI9"), + STM32_FUNCTION(0, "GPIOI9"), + STM32_FUNCTION(10, "CAN1_RX"), + STM32_FUNCTION(13, "FMC_D30"), + STM32_FUNCTION(15, "LCD_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(138, "PI10"), + STM32_FUNCTION(0, "GPIOI10"), + STM32_FUNCTION(12, "ETH_MII_RX_ER"), + STM32_FUNCTION(13, "FMC_D31"), + STM32_FUNCTION(15, "LCD_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(139, "PI11"), + STM32_FUNCTION(0, "GPIOI11"), + STM32_FUNCTION(11, "OTG_HS_ULPI_DIR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(140, "PI12"), + STM32_FUNCTION(0, "GPIOI12"), + STM32_FUNCTION(15, "LCD_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(141, "PI13"), + STM32_FUNCTION(0, "GPIOI13"), + STM32_FUNCTION(15, "LCD_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(142, "PI14"), + STM32_FUNCTION(0, "GPIOI14"), + STM32_FUNCTION(15, "LCD_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(143, "PI15"), + STM32_FUNCTION(0, "GPIOI15"), + STM32_FUNCTION(15, "LCD_R0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(144, "PJ0"), + STM32_FUNCTION(0, "GPIOJ0"), + STM32_FUNCTION(15, "LCD_R1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(145, "PJ1"), + STM32_FUNCTION(0, "GPIOJ1"), + STM32_FUNCTION(15, "LCD_R2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(146, "PJ2"), + STM32_FUNCTION(0, "GPIOJ2"), + STM32_FUNCTION(15, "LCD_R3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(147, "PJ3"), + STM32_FUNCTION(0, "GPIOJ3"), + STM32_FUNCTION(15, "LCD_R4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(148, "PJ4"), + STM32_FUNCTION(0, "GPIOJ4"), + STM32_FUNCTION(15, "LCD_R5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(149, "PJ5"), + STM32_FUNCTION(0, "GPIOJ5"), + STM32_FUNCTION(15, "LCD_R6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(150, "PJ6"), + STM32_FUNCTION(0, "GPIOJ6"), + STM32_FUNCTION(15, "LCD_R7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(151, "PJ7"), + STM32_FUNCTION(0, "GPIOJ7"), + STM32_FUNCTION(15, "LCD_G0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(152, "PJ8"), + STM32_FUNCTION(0, "GPIOJ8"), + STM32_FUNCTION(15, "LCD_G1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(153, "PJ9"), + STM32_FUNCTION(0, "GPIOJ9"), + STM32_FUNCTION(15, "LCD_G2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(154, "PJ10"), + STM32_FUNCTION(0, "GPIOJ10"), + STM32_FUNCTION(15, "LCD_G3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(155, "PJ11"), + STM32_FUNCTION(0, "GPIOJ11"), + STM32_FUNCTION(15, "LCD_G4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(156, "PJ12"), + STM32_FUNCTION(0, "GPIOJ12"), + STM32_FUNCTION(15, "LCD_B0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(157, "PJ13"), + STM32_FUNCTION(0, "GPIOJ13"), + STM32_FUNCTION(15, "LCD_B1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(158, "PJ14"), + STM32_FUNCTION(0, "GPIOJ14"), + STM32_FUNCTION(15, "LCD_B2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(159, "PJ15"), + STM32_FUNCTION(0, "GPIOJ15"), + STM32_FUNCTION(15, "LCD_B3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(160, "PK0"), + STM32_FUNCTION(0, "GPIOK0"), + STM32_FUNCTION(15, "LCD_G5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(161, "PK1"), + STM32_FUNCTION(0, "GPIOK1"), + STM32_FUNCTION(15, "LCD_G6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(162, "PK2"), + STM32_FUNCTION(0, "GPIOK2"), + STM32_FUNCTION(15, "LCD_G7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(163, "PK3"), + STM32_FUNCTION(0, "GPIOK3"), + STM32_FUNCTION(15, "LCD_B4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(164, "PK4"), + STM32_FUNCTION(0, "GPIOK4"), + STM32_FUNCTION(15, "LCD_B5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(165, "PK5"), + STM32_FUNCTION(0, "GPIOK5"), + STM32_FUNCTION(15, "LCD_B6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(166, "PK6"), + STM32_FUNCTION(0, "GPIOK6"), + STM32_FUNCTION(15, "LCD_B7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(167, "PK7"), + STM32_FUNCTION(0, "GPIOK7"), + STM32_FUNCTION(15, "LCD_DE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), +}; + +static struct stm32_pinctrl_match_data stm32f429_match_data = { + .pins = stm32f429_pins, + .npins = ARRAY_SIZE(stm32f429_pins), +}; + +static const struct of_device_id stm32f429_pctrl_match[] = { + { + .compatible = "st,stm32f429-pinctrl", + .data = &stm32f429_match_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, stm32f429_pctrl_match); + +static struct platform_driver stm32f429_pinctrl_driver = { + .probe = stm32_pctl_probe, + .driver = { + .name = "stm32f429-pinctrl", + .of_match_table = stm32f429_pctrl_match, + }, +}; + +static int __init stm32f429_pinctrl_init(void) +{ + return platform_driver_register(&stm32f429_pinctrl_driver); +} + +module_init(stm32f429_pinctrl_init); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("STM32F429 Pinctrl Driver"); +MODULE_AUTHOR("Maxime Coquelin <mcoquelin.stm32@gmail.com>"); -- 1.9.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
[parent not found: <1452773795-24216-5-git-send-email-mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH v4 4/9] pinctrl: Add STM32 MCUs support 2016-01-14 12:16 ` Maxime Coquelin (?) @ 2016-01-27 13:16 ` Linus Walleij -1 siblings, 0 replies; 47+ messages in thread From: Linus Walleij @ 2016-01-27 13:16 UTC (permalink / raw) To: Maxime Coquelin Cc: Patrice CHOTARD, Mark Rutland, Rob Herring, linux-gpio-u79uwXL29TY76Z2rM5mHXA, Arnd Bergmann, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA, Andreas Färber, devicetree-u79uwXL29TY76Z2rM5mHXA, Daniel Thompson, Bruno Herrera On Thu, Jan 14, 2016 at 1:16 PM, Maxime Coquelin <mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote: > This patch adds pinctrl and GPIO support to STMicroelectronic's STM32 > family of MCUs. > > While it only supports STM32F429 for now, it has been designed to enable > support of other MCUs of the family (e.g. STM32F746). > > Acked-by: Patrice Chotard <patrice.chotard-qxv4g6HH51o@public.gmane.org> > Signed-off-by: Maxime Coquelin <mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> This patch applied for kernel v4.6. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v4 4/9] pinctrl: Add STM32 MCUs support @ 2016-01-27 13:16 ` Linus Walleij 0 siblings, 0 replies; 47+ messages in thread From: Linus Walleij @ 2016-01-27 13:16 UTC (permalink / raw) To: linux-arm-kernel On Thu, Jan 14, 2016 at 1:16 PM, Maxime Coquelin <mcoquelin.stm32@gmail.com> wrote: > This patch adds pinctrl and GPIO support to STMicroelectronic's STM32 > family of MCUs. > > While it only supports STM32F429 for now, it has been designed to enable > support of other MCUs of the family (e.g. STM32F746). > > Acked-by: Patrice Chotard <patrice.chotard@st.com> > Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> This patch applied for kernel v4.6. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v4 4/9] pinctrl: Add STM32 MCUs support @ 2016-01-27 13:16 ` Linus Walleij 0 siblings, 0 replies; 47+ messages in thread From: Linus Walleij @ 2016-01-27 13:16 UTC (permalink / raw) To: Maxime Coquelin Cc: Patrice CHOTARD, Mark Rutland, Rob Herring, linux-gpio, Arnd Bergmann, linux-arm-kernel, linux-kernel, Andreas Färber, devicetree, Daniel Thompson, Bruno Herrera On Thu, Jan 14, 2016 at 1:16 PM, Maxime Coquelin <mcoquelin.stm32@gmail.com> wrote: > This patch adds pinctrl and GPIO support to STMicroelectronic's STM32 > family of MCUs. > > While it only supports STM32F429 for now, it has been designed to enable > support of other MCUs of the family (e.g. STM32F746). > > Acked-by: Patrice Chotard <patrice.chotard@st.com> > Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> This patch applied for kernel v4.6. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v4 4/9] pinctrl: Add STM32 MCUs support 2016-01-27 13:16 ` Linus Walleij @ 2016-02-01 10:21 ` Arnd Bergmann -1 siblings, 0 replies; 47+ messages in thread From: Arnd Bergmann @ 2016-02-01 10:21 UTC (permalink / raw) To: Linus Walleij Cc: Maxime Coquelin, Patrice CHOTARD, Mark Rutland, Rob Herring, linux-gpio, linux-arm-kernel, linux-kernel, Andreas Färber, devicetree, Daniel Thompson, Bruno Herrera On Wednesday 27 January 2016 14:16:32 Linus Walleij wrote: > On Thu, Jan 14, 2016 at 1:16 PM, Maxime Coquelin > <mcoquelin.stm32@gmail.com> wrote: > > > This patch adds pinctrl and GPIO support to STMicroelectronic's STM32 > > family of MCUs. > > > > While it only supports STM32F429 for now, it has been designed to enable > > support of other MCUs of the family (e.g. STM32F746). > > > > Acked-by: Patrice Chotard <patrice.chotard@st.com> > > Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> > > This patch applied for kernel v4.6. > This breaks the kernel build, please revert: drivers/pinctrl/stm32/pinctrl-stm32.c:26:47: fatal error: dt-bindings/pinctrl/pinctrl-stm32.h: No such file or directory Arnd ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v4 4/9] pinctrl: Add STM32 MCUs support @ 2016-02-01 10:21 ` Arnd Bergmann 0 siblings, 0 replies; 47+ messages in thread From: Arnd Bergmann @ 2016-02-01 10:21 UTC (permalink / raw) To: linux-arm-kernel On Wednesday 27 January 2016 14:16:32 Linus Walleij wrote: > On Thu, Jan 14, 2016 at 1:16 PM, Maxime Coquelin > <mcoquelin.stm32@gmail.com> wrote: > > > This patch adds pinctrl and GPIO support to STMicroelectronic's STM32 > > family of MCUs. > > > > While it only supports STM32F429 for now, it has been designed to enable > > support of other MCUs of the family (e.g. STM32F746). > > > > Acked-by: Patrice Chotard <patrice.chotard@st.com> > > Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> > > This patch applied for kernel v4.6. > This breaks the kernel build, please revert: drivers/pinctrl/stm32/pinctrl-stm32.c:26:47: fatal error: dt-bindings/pinctrl/pinctrl-stm32.h: No such file or directory Arnd ^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v4 4/9] pinctrl: Add STM32 MCUs support 2016-02-01 10:21 ` Arnd Bergmann @ 2016-02-01 10:39 ` Maxime Coquelin -1 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-02-01 10:39 UTC (permalink / raw) To: Arnd Bergmann Cc: Linus Walleij, Patrice CHOTARD, Mark Rutland, Rob Herring, linux-gpio, linux-arm-kernel, linux-kernel, Andreas Färber, devicetree, Daniel Thompson, Bruno Herrera 2016-02-01 11:21 GMT+01:00 Arnd Bergmann <arnd@arndb.de>: > On Wednesday 27 January 2016 14:16:32 Linus Walleij wrote: >> On Thu, Jan 14, 2016 at 1:16 PM, Maxime Coquelin >> <mcoquelin.stm32@gmail.com> wrote: >> >> > This patch adds pinctrl and GPIO support to STMicroelectronic's STM32 >> > family of MCUs. >> > >> > While it only supports STM32F429 for now, it has been designed to enable >> > support of other MCUs of the family (e.g. STM32F746). >> > >> > Acked-by: Patrice Chotard <patrice.chotard@st.com> >> > Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> >> >> This patch applied for kernel v4.6. >> > > This breaks the kernel build, please revert: > > drivers/pinctrl/stm32/pinctrl-stm32.c:26:47: fatal error: dt-bindings/pinctrl/pinctrl-stm32.h: No such file or directory Right, I missed to notify this dependency to Linus, sorry about that. This dependency is no more needed, so I could just move the macros to the driver side. Note that I also noticed a breakage at build time due to field renaming in gpio_chip structure (dev -> parent). I propose to rebase the series and move the defines into the driver. Is it ok for you? Regards, Maxime ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v4 4/9] pinctrl: Add STM32 MCUs support @ 2016-02-01 10:39 ` Maxime Coquelin 0 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-02-01 10:39 UTC (permalink / raw) To: linux-arm-kernel 2016-02-01 11:21 GMT+01:00 Arnd Bergmann <arnd@arndb.de>: > On Wednesday 27 January 2016 14:16:32 Linus Walleij wrote: >> On Thu, Jan 14, 2016 at 1:16 PM, Maxime Coquelin >> <mcoquelin.stm32@gmail.com> wrote: >> >> > This patch adds pinctrl and GPIO support to STMicroelectronic's STM32 >> > family of MCUs. >> > >> > While it only supports STM32F429 for now, it has been designed to enable >> > support of other MCUs of the family (e.g. STM32F746). >> > >> > Acked-by: Patrice Chotard <patrice.chotard@st.com> >> > Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> >> >> This patch applied for kernel v4.6. >> > > This breaks the kernel build, please revert: > > drivers/pinctrl/stm32/pinctrl-stm32.c:26:47: fatal error: dt-bindings/pinctrl/pinctrl-stm32.h: No such file or directory Right, I missed to notify this dependency to Linus, sorry about that. This dependency is no more needed, so I could just move the macros to the driver side. Note that I also noticed a breakage at build time due to field renaming in gpio_chip structure (dev -> parent). I propose to rebase the series and move the defines into the driver. Is it ok for you? Regards, Maxime ^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v4 4/9] pinctrl: Add STM32 MCUs support 2016-02-01 10:39 ` Maxime Coquelin @ 2016-02-01 12:09 ` Maxime Coquelin -1 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-02-01 12:09 UTC (permalink / raw) To: Maxime Coquelin, Arnd Bergmann, Linus Walleij Cc: Mark Rutland, devicetree, Daniel Thompson, Bruno Herrera, Patrice CHOTARD, linux-kernel, linux-gpio, Rob Herring, Andreas Färber, linux-arm-kernel On 02/01/2016 11:39 AM, Maxime Coquelin wrote: > 2016-02-01 11:21 GMT+01:00 Arnd Bergmann <arnd@arndb.de>: >> On Wednesday 27 January 2016 14:16:32 Linus Walleij wrote: >>> On Thu, Jan 14, 2016 at 1:16 PM, Maxime Coquelin >>> <mcoquelin.stm32@gmail.com> wrote: >>> >>>> This patch adds pinctrl and GPIO support to STMicroelectronic's STM32 >>>> family of MCUs. >>>> >>>> While it only supports STM32F429 for now, it has been designed to enable >>>> support of other MCUs of the family (e.g. STM32F746). >>>> >>>> Acked-by: Patrice Chotard <patrice.chotard@st.com> >>>> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> >>> This patch applied for kernel v4.6. >>> >> This breaks the kernel build, please revert: >> >> drivers/pinctrl/stm32/pinctrl-stm32.c:26:47: fatal error: dt-bindings/pinctrl/pinctrl-stm32.h: No such file or directory > Right, I missed to notify this dependency to Linus, sorry about that. > This dependency is no more needed, so I could just move the macros to > the driver side. > > Note that I also noticed a breakage at build time due to field > renaming in gpio_chip structure (dev -> parent). > > I propose to rebase the series and move the defines into the driver. > Is it ok for you? > I have rebased the series, taking care to fix the mentioned problems. Linus, do you confirm you will revert STM32 pinctrl patches from your tree? Thanks, Maxime ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v4 4/9] pinctrl: Add STM32 MCUs support @ 2016-02-01 12:09 ` Maxime Coquelin 0 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-02-01 12:09 UTC (permalink / raw) To: linux-arm-kernel On 02/01/2016 11:39 AM, Maxime Coquelin wrote: > 2016-02-01 11:21 GMT+01:00 Arnd Bergmann <arnd@arndb.de>: >> On Wednesday 27 January 2016 14:16:32 Linus Walleij wrote: >>> On Thu, Jan 14, 2016 at 1:16 PM, Maxime Coquelin >>> <mcoquelin.stm32@gmail.com> wrote: >>> >>>> This patch adds pinctrl and GPIO support to STMicroelectronic's STM32 >>>> family of MCUs. >>>> >>>> While it only supports STM32F429 for now, it has been designed to enable >>>> support of other MCUs of the family (e.g. STM32F746). >>>> >>>> Acked-by: Patrice Chotard <patrice.chotard@st.com> >>>> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> >>> This patch applied for kernel v4.6. >>> >> This breaks the kernel build, please revert: >> >> drivers/pinctrl/stm32/pinctrl-stm32.c:26:47: fatal error: dt-bindings/pinctrl/pinctrl-stm32.h: No such file or directory > Right, I missed to notify this dependency to Linus, sorry about that. > This dependency is no more needed, so I could just move the macros to > the driver side. > > Note that I also noticed a breakage at build time due to field > renaming in gpio_chip structure (dev -> parent). > > I propose to rebase the series and move the defines into the driver. > Is it ok for you? > I have rebased the series, taking care to fix the mentioned problems. Linus, do you confirm you will revert STM32 pinctrl patches from your tree? Thanks, Maxime ^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v4 4/9] pinctrl: Add STM32 MCUs support 2016-02-01 12:09 ` Maxime Coquelin @ 2016-02-13 14:48 ` Linus Walleij -1 siblings, 0 replies; 47+ messages in thread From: Linus Walleij @ 2016-02-13 14:48 UTC (permalink / raw) To: Maxime Coquelin Cc: Maxime Coquelin, Arnd Bergmann, Mark Rutland, devicetree, Daniel Thompson, Bruno Herrera, Patrice CHOTARD, linux-kernel, linux-gpio, Rob Herring, Andreas Färber, linux-arm-kernel On Mon, Feb 1, 2016 at 1:09 PM, Maxime Coquelin <maxime.coquelin@st.com> wrote: > On 02/01/2016 11:39 AM, Maxime Coquelin wrote: >> 2016-02-01 11:21 GMT+01:00 Arnd Bergmann <arnd@arndb.de>: >>> drivers/pinctrl/stm32/pinctrl-stm32.c:26:47: fatal error: >>> dt-bindings/pinctrl/pinctrl-stm32.h: No such file or directory >> >> Right, I missed to notify this dependency to Linus, sorry about that. >> This dependency is no more needed, so I could just move the macros to >> the driver side. >> >> Note that I also noticed a breakage at build time due to field >> renaming in gpio_chip structure (dev -> parent). >> >> I propose to rebase the series and move the defines into the driver. >> Is it ok for you? >> > I have rebased the series, taking care to fix the mentioned problems. > > Linus, do you confirm you will revert STM32 pinctrl patches from your tree? I guess the other fixes removes the need to do this. Sorry for not staying on top of this issue, I was swamped with mail and had a hard time prioritizing :( Yours, Linus Walleij ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v4 4/9] pinctrl: Add STM32 MCUs support @ 2016-02-13 14:48 ` Linus Walleij 0 siblings, 0 replies; 47+ messages in thread From: Linus Walleij @ 2016-02-13 14:48 UTC (permalink / raw) To: linux-arm-kernel On Mon, Feb 1, 2016 at 1:09 PM, Maxime Coquelin <maxime.coquelin@st.com> wrote: > On 02/01/2016 11:39 AM, Maxime Coquelin wrote: >> 2016-02-01 11:21 GMT+01:00 Arnd Bergmann <arnd@arndb.de>: >>> drivers/pinctrl/stm32/pinctrl-stm32.c:26:47: fatal error: >>> dt-bindings/pinctrl/pinctrl-stm32.h: No such file or directory >> >> Right, I missed to notify this dependency to Linus, sorry about that. >> This dependency is no more needed, so I could just move the macros to >> the driver side. >> >> Note that I also noticed a breakage at build time due to field >> renaming in gpio_chip structure (dev -> parent). >> >> I propose to rebase the series and move the defines into the driver. >> Is it ok for you? >> > I have rebased the series, taking care to fix the mentioned problems. > > Linus, do you confirm you will revert STM32 pinctrl patches from your tree? I guess the other fixes removes the need to do this. Sorry for not staying on top of this issue, I was swamped with mail and had a hard time prioritizing :( Yours, Linus Walleij ^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v4 4/9] pinctrl: Add STM32 MCUs support 2016-02-13 14:48 ` Linus Walleij @ 2016-02-13 17:14 ` Maxime Coquelin -1 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-02-13 17:14 UTC (permalink / raw) To: Linus Walleij, Maxime Coquelin Cc: Arnd Bergmann, Mark Rutland, devicetree, Daniel Thompson, Bruno Herrera, Patrice CHOTARD, linux-kernel, linux-gpio, Rob Herring, Andreas Färber, linux-arm-kernel On 02/13/2016 03:48 PM, Linus Walleij wrote: > On Mon, Feb 1, 2016 at 1:09 PM, Maxime Coquelin <maxime.coquelin@st.com> wrote: >> On 02/01/2016 11:39 AM, Maxime Coquelin wrote: >>> 2016-02-01 11:21 GMT+01:00 Arnd Bergmann <arnd@arndb.de>: > >>>> drivers/pinctrl/stm32/pinctrl-stm32.c:26:47: fatal error: >>>> dt-bindings/pinctrl/pinctrl-stm32.h: No such file or directory >>> >>> Right, I missed to notify this dependency to Linus, sorry about that. >>> This dependency is no more needed, so I could just move the macros to >>> the driver side. >>> >>> Note that I also noticed a breakage at build time due to field >>> renaming in gpio_chip structure (dev -> parent). >>> >>> I propose to rebase the series and move the defines into the driver. >>> Is it ok for you? >>> >> I have rebased the series, taking care to fix the mentioned problems. >> >> Linus, do you confirm you will revert STM32 pinctrl patches from your tree? > > I guess the other fixes removes the need to do this. Exactly, all should be fine now. > > Sorry for not staying on top of this issue, I was swamped with mail > and had a hard time prioritizing :( No worries! Thanks, Maxime ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v4 4/9] pinctrl: Add STM32 MCUs support @ 2016-02-13 17:14 ` Maxime Coquelin 0 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-02-13 17:14 UTC (permalink / raw) To: linux-arm-kernel On 02/13/2016 03:48 PM, Linus Walleij wrote: > On Mon, Feb 1, 2016 at 1:09 PM, Maxime Coquelin <maxime.coquelin@st.com> wrote: >> On 02/01/2016 11:39 AM, Maxime Coquelin wrote: >>> 2016-02-01 11:21 GMT+01:00 Arnd Bergmann <arnd@arndb.de>: > >>>> drivers/pinctrl/stm32/pinctrl-stm32.c:26:47: fatal error: >>>> dt-bindings/pinctrl/pinctrl-stm32.h: No such file or directory >>> >>> Right, I missed to notify this dependency to Linus, sorry about that. >>> This dependency is no more needed, so I could just move the macros to >>> the driver side. >>> >>> Note that I also noticed a breakage at build time due to field >>> renaming in gpio_chip structure (dev -> parent). >>> >>> I propose to rebase the series and move the defines into the driver. >>> Is it ok for you? >>> >> I have rebased the series, taking care to fix the mentioned problems. >> >> Linus, do you confirm you will revert STM32 pinctrl patches from your tree? > > I guess the other fixes removes the need to do this. Exactly, all should be fine now. > > Sorry for not staying on top of this issue, I was swamped with mail > and had a hard time prioritizing :( No worries! Thanks, Maxime ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v4 5/9] ARM: mach-stm32: Select pinctrl 2016-01-14 12:16 ` Maxime Coquelin @ 2016-01-14 12:16 ` Maxime Coquelin -1 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-01-14 12:16 UTC (permalink / raw) To: patrice.chotard, Linus Walleij, Mark Rutland, Rob Herring, linux-gpio, arnd Cc: linux-arm-kernel, linux-kernel, afaerber, devicetree, Daniel Thompson, bruherrera Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b7aa567..f700a90 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -965,6 +965,7 @@ config ARCH_STM32 select ARCH_HAS_RESET_CONTROLLER select ARMV7M_SYSTICK select CLKSRC_STM32 + select PINCTRL select RESET_CONTROLLER help Support for STMicroelectronics STM32 processors. -- 1.9.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v4 5/9] ARM: mach-stm32: Select pinctrl @ 2016-01-14 12:16 ` Maxime Coquelin 0 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-01-14 12:16 UTC (permalink / raw) To: linux-arm-kernel Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b7aa567..f700a90 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -965,6 +965,7 @@ config ARCH_STM32 select ARCH_HAS_RESET_CONTROLLER select ARMV7M_SYSTICK select CLKSRC_STM32 + select PINCTRL select RESET_CONTROLLER help Support for STMicroelectronics STM32 processors. -- 1.9.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v4 6/9] ARM: dts: Add pinctrl node to STM32F429 2016-01-14 12:16 ` Maxime Coquelin @ 2016-01-14 12:16 ` Maxime Coquelin -1 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-01-14 12:16 UTC (permalink / raw) To: patrice.chotard, Linus Walleij, Mark Rutland, Rob Herring, linux-gpio, arnd Cc: linux-arm-kernel, linux-kernel, afaerber, devicetree, Daniel Thompson, bruherrera The STM32F429 MCU has 11 GPIO banks, with 16 pins per bank. Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> --- arch/arm/boot/dts/stm32f429.dtsi | 97 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 5e1e234..62d2b3d 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -46,6 +46,7 @@ */ #include "armv7-m.dtsi" +#include <dt-bindings/pinctrl/stm32f429-pinfunc.h> / { clocks { @@ -168,6 +169,102 @@ status = "disabled"; }; + pin-controller { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32f429-pinctrl"; + ranges = <0 0x40020000 0x3000>; + pins-are-numbered; + + gpioa: gpio@40020000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + clocks = <&rcc 0 256>; + st,bank-name = "GPIOA"; + }; + + gpiob: gpio@40020400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x400 0x400>; + clocks = <&rcc 0 257>; + st,bank-name = "GPIOB"; + }; + + gpioc: gpio@40020800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x800 0x400>; + clocks = <&rcc 0 258>; + st,bank-name = "GPIOC"; + }; + + gpiod: gpio@40020c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0xc00 0x400>; + clocks = <&rcc 0 259>; + st,bank-name = "GPIOD"; + }; + + gpioe: gpio@40021000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&rcc 0 260>; + st,bank-name = "GPIOE"; + }; + + gpiof: gpio@40021400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1400 0x400>; + clocks = <&rcc 0 261>; + st,bank-name = "GPIOF"; + }; + + gpiog: gpio@40021800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1800 0x400>; + clocks = <&rcc 0 262>; + st,bank-name = "GPIOG"; + }; + + gpioh: gpio@40021c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1c00 0x400>; + clocks = <&rcc 0 263>; + st,bank-name = "GPIOH"; + }; + + gpioi: gpio@40022000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&rcc 0 264>; + st,bank-name = "GPIOI"; + }; + + gpioj: gpio@40022400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2400 0x400>; + clocks = <&rcc 0 265>; + st,bank-name = "GPIOJ"; + }; + + gpiok: gpio@40022800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2800 0x400>; + clocks = <&rcc 0 266>; + st,bank-name = "GPIOK"; + }; + }; + rcc: rcc@40023810 { #clock-cells = <2>; compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; -- 1.9.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v4 6/9] ARM: dts: Add pinctrl node to STM32F429 @ 2016-01-14 12:16 ` Maxime Coquelin 0 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-01-14 12:16 UTC (permalink / raw) To: linux-arm-kernel The STM32F429 MCU has 11 GPIO banks, with 16 pins per bank. Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> --- arch/arm/boot/dts/stm32f429.dtsi | 97 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 5e1e234..62d2b3d 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -46,6 +46,7 @@ */ #include "armv7-m.dtsi" +#include <dt-bindings/pinctrl/stm32f429-pinfunc.h> / { clocks { @@ -168,6 +169,102 @@ status = "disabled"; }; + pin-controller { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32f429-pinctrl"; + ranges = <0 0x40020000 0x3000>; + pins-are-numbered; + + gpioa: gpio at 40020000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + clocks = <&rcc 0 256>; + st,bank-name = "GPIOA"; + }; + + gpiob: gpio at 40020400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x400 0x400>; + clocks = <&rcc 0 257>; + st,bank-name = "GPIOB"; + }; + + gpioc: gpio at 40020800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x800 0x400>; + clocks = <&rcc 0 258>; + st,bank-name = "GPIOC"; + }; + + gpiod: gpio at 40020c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0xc00 0x400>; + clocks = <&rcc 0 259>; + st,bank-name = "GPIOD"; + }; + + gpioe: gpio at 40021000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&rcc 0 260>; + st,bank-name = "GPIOE"; + }; + + gpiof: gpio at 40021400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1400 0x400>; + clocks = <&rcc 0 261>; + st,bank-name = "GPIOF"; + }; + + gpiog: gpio at 40021800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1800 0x400>; + clocks = <&rcc 0 262>; + st,bank-name = "GPIOG"; + }; + + gpioh: gpio at 40021c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1c00 0x400>; + clocks = <&rcc 0 263>; + st,bank-name = "GPIOH"; + }; + + gpioi: gpio at 40022000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&rcc 0 264>; + st,bank-name = "GPIOI"; + }; + + gpioj: gpio at 40022400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2400 0x400>; + clocks = <&rcc 0 265>; + st,bank-name = "GPIOJ"; + }; + + gpiok: gpio at 40022800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2800 0x400>; + clocks = <&rcc 0 266>; + st,bank-name = "GPIOK"; + }; + }; + rcc: rcc at 40023810 { #clock-cells = <2>; compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; -- 1.9.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v4 7/9] ARM: dts: Add USART1 pin config to STM32F429 boards 2016-01-14 12:16 ` Maxime Coquelin @ 2016-01-14 12:16 ` Maxime Coquelin -1 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-01-14 12:16 UTC (permalink / raw) To: patrice.chotard, Linus Walleij, Mark Rutland, Rob Herring, linux-gpio, arnd Cc: linux-arm-kernel, linux-kernel, afaerber, devicetree, Daniel Thompson, bruherrera This patch selects USART1 pin configuration on PA9/PA10 pins for both Eval and Disco boards. Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> --- arch/arm/boot/dts/stm32429i-eval.dts | 2 ++ arch/arm/boot/dts/stm32f429-disco.dts | 2 ++ arch/arm/boot/dts/stm32f429.dtsi | 13 +++++++++++++ 3 files changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index 6964fc9..71fe17a 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -71,5 +71,7 @@ }; &usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index f0b731d..e3ce796 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -71,5 +71,7 @@ }; &usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 62d2b3d..1cf713e 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -263,6 +263,19 @@ clocks = <&rcc 0 266>; st,bank-name = "GPIOK"; }; + + usart1_pins_a: usart1@0 { + pins1 { + pinmux = <STM32F429_PA9_FUNC_USART1_TX>; + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32F429_PA10_FUNC_USART1_RX>; + bias-disable; + }; + }; }; rcc: rcc@40023810 { -- 1.9.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v4 7/9] ARM: dts: Add USART1 pin config to STM32F429 boards @ 2016-01-14 12:16 ` Maxime Coquelin 0 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-01-14 12:16 UTC (permalink / raw) To: linux-arm-kernel This patch selects USART1 pin configuration on PA9/PA10 pins for both Eval and Disco boards. Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> --- arch/arm/boot/dts/stm32429i-eval.dts | 2 ++ arch/arm/boot/dts/stm32f429-disco.dts | 2 ++ arch/arm/boot/dts/stm32f429.dtsi | 13 +++++++++++++ 3 files changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index 6964fc9..71fe17a 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -71,5 +71,7 @@ }; &usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index f0b731d..e3ce796 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -71,5 +71,7 @@ }; &usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 62d2b3d..1cf713e 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -263,6 +263,19 @@ clocks = <&rcc 0 266>; st,bank-name = "GPIOK"; }; + + usart1_pins_a: usart1 at 0 { + pins1 { + pinmux = <STM32F429_PA9_FUNC_USART1_TX>; + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32F429_PA10_FUNC_USART1_RX>; + bias-disable; + }; + }; }; rcc: rcc at 40023810 { -- 1.9.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v4 8/9] ARM: dts: Add leds support to STM32F429 boards 2016-01-14 12:16 ` Maxime Coquelin @ 2016-01-14 12:16 ` Maxime Coquelin -1 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-01-14 12:16 UTC (permalink / raw) To: patrice.chotard, Linus Walleij, Mark Rutland, Rob Herring, linux-gpio, arnd Cc: linux-arm-kernel, linux-kernel, afaerber, devicetree, Daniel Thompson, bruherrera Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> --- arch/arm/boot/dts/stm32429i-eval.dts | 17 +++++++++++++++++ arch/arm/boot/dts/stm32f429-disco.dts | 11 +++++++++++ 2 files changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index 71fe17a..e3921d9 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -64,6 +64,23 @@ aliases { serial0 = &usart1; }; + + leds { + compatible = "gpio-leds"; + green { + gpios = <&gpiog 6 1>; + linux,default-trigger = "heartbeat"; + }; + orange { + gpios = <&gpiog 7 1>; + }; + red { + gpios = <&gpiog 10 1>; + }; + blue { + gpios = <&gpiog 12 1>; + }; + }; }; &clk_hse { diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index e3ce796..0140807 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -64,6 +64,17 @@ aliases { serial0 = &usart1; }; + + leds { + compatible = "gpio-leds"; + red { + gpios = <&gpiog 14 0>; + }; + green { + gpios = <&gpiog 13 0>; + linux,default-trigger = "heartbeat"; + }; + }; }; &clk_hse { -- 1.9.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v4 8/9] ARM: dts: Add leds support to STM32F429 boards @ 2016-01-14 12:16 ` Maxime Coquelin 0 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-01-14 12:16 UTC (permalink / raw) To: linux-arm-kernel Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> --- arch/arm/boot/dts/stm32429i-eval.dts | 17 +++++++++++++++++ arch/arm/boot/dts/stm32f429-disco.dts | 11 +++++++++++ 2 files changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index 71fe17a..e3921d9 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -64,6 +64,23 @@ aliases { serial0 = &usart1; }; + + leds { + compatible = "gpio-leds"; + green { + gpios = <&gpiog 6 1>; + linux,default-trigger = "heartbeat"; + }; + orange { + gpios = <&gpiog 7 1>; + }; + red { + gpios = <&gpiog 10 1>; + }; + blue { + gpios = <&gpiog 12 1>; + }; + }; }; &clk_hse { diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index e3ce796..0140807 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -64,6 +64,17 @@ aliases { serial0 = &usart1; }; + + leds { + compatible = "gpio-leds"; + red { + gpios = <&gpiog 14 0>; + }; + green { + gpios = <&gpiog 13 0>; + linux,default-trigger = "heartbeat"; + }; + }; }; &clk_hse { -- 1.9.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
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* [PATCH v4 9/9] ARM: config: Enable GPIO Led driver in stm32_defconfig 2016-01-14 12:16 ` Maxime Coquelin (?) @ 2016-01-14 12:16 ` Maxime Coquelin -1 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-01-14 12:16 UTC (permalink / raw) To: patrice.chotard-qxv4g6HH51o, Linus Walleij, Mark Rutland, Rob Herring, linux-gpio-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4 Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA, afaerber-l3A5Bk7waGM, devicetree-u79uwXL29TY76Z2rM5mHXA, Daniel Thompson, bruherrera-Re5JQEeQqe8AvxtiuMwx3w Acked-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> Acked-by: Patrice Chotard <patrice.chotard-qxv4g6HH51o@public.gmane.org> Signed-off-by: Maxime Coquelin <mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> --- arch/arm/configs/stm32_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig index 4725fab..92ade2e 100644 --- a/arch/arm/configs/stm32_defconfig +++ b/arch/arm/configs/stm32_defconfig @@ -52,6 +52,7 @@ CONFIG_SERIAL_STM32_CONSOLE=y # CONFIG_USB_SUPPORT is not set CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y # CONFIG_FILE_LOCKING is not set -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v4 9/9] ARM: config: Enable GPIO Led driver in stm32_defconfig @ 2016-01-14 12:16 ` Maxime Coquelin 0 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-01-14 12:16 UTC (permalink / raw) To: linux-arm-kernel Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> --- arch/arm/configs/stm32_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig index 4725fab..92ade2e 100644 --- a/arch/arm/configs/stm32_defconfig +++ b/arch/arm/configs/stm32_defconfig @@ -52,6 +52,7 @@ CONFIG_SERIAL_STM32_CONSOLE=y # CONFIG_USB_SUPPORT is not set CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y # CONFIG_FILE_LOCKING is not set -- 1.9.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v4 9/9] ARM: config: Enable GPIO Led driver in stm32_defconfig @ 2016-01-14 12:16 ` Maxime Coquelin 0 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-01-14 12:16 UTC (permalink / raw) To: patrice.chotard, Linus Walleij, Mark Rutland, Rob Herring, linux-gpio, arnd Cc: linux-arm-kernel, linux-kernel, afaerber, devicetree, Daniel Thompson, bruherrera Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> --- arch/arm/configs/stm32_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig index 4725fab..92ade2e 100644 --- a/arch/arm/configs/stm32_defconfig +++ b/arch/arm/configs/stm32_defconfig @@ -52,6 +52,7 @@ CONFIG_SERIAL_STM32_CONSOLE=y # CONFIG_USB_SUPPORT is not set CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y # CONFIG_FILE_LOCKING is not set -- 1.9.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH v4 0/9] Add STM32 pinctrl/GPIO driver 2016-01-14 12:16 ` Maxime Coquelin @ 2016-01-27 13:20 ` Linus Walleij -1 siblings, 0 replies; 47+ messages in thread From: Linus Walleij @ 2016-01-27 13:20 UTC (permalink / raw) To: Maxime Coquelin Cc: Patrice CHOTARD, Mark Rutland, Rob Herring, linux-gpio, Arnd Bergmann, linux-arm-kernel, linux-kernel, Andreas Färber, devicetree, Daniel Thompson, Bruno Herrera On Thu, Jan 14, 2016 at 1:16 PM, Maxime Coquelin <mcoquelin.stm32@gmail.com> wrote: > This is the fourth round of STM32 pinctrl series, which takes into > account comments made by Patrice on patch 4. I have applied patch 2 and 4 to the pinctrl tree. Please put the rest of the patches in through ARM SoC, you can add my Acked-by: Linus Walleij <linus.walleij@linaro.org> to them. AFAICT there is no compile-time dependency between these two patches and the rest, so it should merge just fine. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v4 0/9] Add STM32 pinctrl/GPIO driver @ 2016-01-27 13:20 ` Linus Walleij 0 siblings, 0 replies; 47+ messages in thread From: Linus Walleij @ 2016-01-27 13:20 UTC (permalink / raw) To: linux-arm-kernel On Thu, Jan 14, 2016 at 1:16 PM, Maxime Coquelin <mcoquelin.stm32@gmail.com> wrote: > This is the fourth round of STM32 pinctrl series, which takes into > account comments made by Patrice on patch 4. I have applied patch 2 and 4 to the pinctrl tree. Please put the rest of the patches in through ARM SoC, you can add my Acked-by: Linus Walleij <linus.walleij@linaro.org> to them. AFAICT there is no compile-time dependency between these two patches and the rest, so it should merge just fine. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 47+ messages in thread
[parent not found: <CACRpkdYGQ1xObWfka2CN9au6YMGhpu4qcTZpu72bzuJjO38tog-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH v4 0/9] Add STM32 pinctrl/GPIO driver 2016-01-27 13:20 ` Linus Walleij (?) @ 2016-01-27 17:00 ` Maxime Coquelin -1 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-01-27 17:00 UTC (permalink / raw) To: Linus Walleij Cc: Patrice CHOTARD, Mark Rutland, Rob Herring, linux-gpio-u79uwXL29TY76Z2rM5mHXA, Arnd Bergmann, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA, Andreas Färber, devicetree-u79uwXL29TY76Z2rM5mHXA, Daniel Thompson, Bruno Herrera Hi Linus, On 01/27/2016 02:20 PM, Linus Walleij wrote: > On Thu, Jan 14, 2016 at 1:16 PM, Maxime Coquelin > <mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote: > >> This is the fourth round of STM32 pinctrl series, which takes into >> account comments made by Patrice on patch 4. > > I have applied patch 2 and 4 to the pinctrl tree. Thanks a lot! > > Please put the rest of the patches in through ARM SoC, you can > add my > Acked-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> > to them. > > AFAICT there is no compile-time dependency between these two > patches and the rest, so it should merge just fine. Indeed, I confirm. Regards, Maxime -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v4 0/9] Add STM32 pinctrl/GPIO driver @ 2016-01-27 17:00 ` Maxime Coquelin 0 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-01-27 17:00 UTC (permalink / raw) To: linux-arm-kernel Hi Linus, On 01/27/2016 02:20 PM, Linus Walleij wrote: > On Thu, Jan 14, 2016 at 1:16 PM, Maxime Coquelin > <mcoquelin.stm32@gmail.com> wrote: > >> This is the fourth round of STM32 pinctrl series, which takes into >> account comments made by Patrice on patch 4. > > I have applied patch 2 and 4 to the pinctrl tree. Thanks a lot! > > Please put the rest of the patches in through ARM SoC, you can > add my > Acked-by: Linus Walleij <linus.walleij@linaro.org> > to them. > > AFAICT there is no compile-time dependency between these two > patches and the rest, so it should merge just fine. Indeed, I confirm. Regards, Maxime ^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v4 0/9] Add STM32 pinctrl/GPIO driver @ 2016-01-27 17:00 ` Maxime Coquelin 0 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-01-27 17:00 UTC (permalink / raw) To: Linus Walleij Cc: Patrice CHOTARD, Mark Rutland, Rob Herring, linux-gpio, Arnd Bergmann, linux-arm-kernel, linux-kernel, Andreas Färber, devicetree, Daniel Thompson, Bruno Herrera Hi Linus, On 01/27/2016 02:20 PM, Linus Walleij wrote: > On Thu, Jan 14, 2016 at 1:16 PM, Maxime Coquelin > <mcoquelin.stm32@gmail.com> wrote: > >> This is the fourth round of STM32 pinctrl series, which takes into >> account comments made by Patrice on patch 4. > > I have applied patch 2 and 4 to the pinctrl tree. Thanks a lot! > > Please put the rest of the patches in through ARM SoC, you can > add my > Acked-by: Linus Walleij <linus.walleij@linaro.org> > to them. > > AFAICT there is no compile-time dependency between these two > patches and the rest, so it should merge just fine. Indeed, I confirm. Regards, Maxime ^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v4 0/9] Add STM32 pinctrl/GPIO driver 2016-01-27 13:20 ` Linus Walleij @ 2016-01-27 20:59 ` Maxime Coquelin -1 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-01-27 20:59 UTC (permalink / raw) To: Linus Walleij Cc: Patrice CHOTARD, Mark Rutland, Rob Herring, linux-gpio, Arnd Bergmann, linux-arm-kernel, linux-kernel, Andreas Färber, devicetree, Daniel Thompson, Bruno Herrera On 01/27/2016 02:20 PM, Linus Walleij wrote: > On Thu, Jan 14, 2016 at 1:16 PM, Maxime Coquelin > <mcoquelin.stm32@gmail.com> wrote: > >> >This is the fourth round of STM32 pinctrl series, which takes into >> >account comments made by Patrice on patch 4. > I have applied patch 2 and 4 to the pinctrl tree. Just tried to compile your devel branch, and it breaks: CC drivers/pinctrl/stm32/pinctrl-stm32f429.o drivers/pinctrl/stm32/pinctrl-stm32.c: In function 'stm32_gpiolib_register_bank': drivers/pinctrl/stm32/pinctrl-stm32.c:692:17: error: 'struct gpio_chip' has no member named 'dev' bank->gpio_chip.dev = dev; ^ make[3]: *** [drivers/pinctrl/stm32/pinctrl-stm32.o] Error 1 This is due to the field renaming you did in gpio_chip struct: 58383c7 gpio: change member .dev to .parent How do you prefer to proceed? Should I send a fix on top of your devel branch, or you will fix it directly? Thanks, Maxime ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v4 0/9] Add STM32 pinctrl/GPIO driver @ 2016-01-27 20:59 ` Maxime Coquelin 0 siblings, 0 replies; 47+ messages in thread From: Maxime Coquelin @ 2016-01-27 20:59 UTC (permalink / raw) To: linux-arm-kernel On 01/27/2016 02:20 PM, Linus Walleij wrote: > On Thu, Jan 14, 2016 at 1:16 PM, Maxime Coquelin > <mcoquelin.stm32@gmail.com> wrote: > >> >This is the fourth round of STM32 pinctrl series, which takes into >> >account comments made by Patrice on patch 4. > I have applied patch 2 and 4 to the pinctrl tree. Just tried to compile your devel branch, and it breaks: CC drivers/pinctrl/stm32/pinctrl-stm32f429.o drivers/pinctrl/stm32/pinctrl-stm32.c: In function 'stm32_gpiolib_register_bank': drivers/pinctrl/stm32/pinctrl-stm32.c:692:17: error: 'struct gpio_chip' has no member named 'dev' bank->gpio_chip.dev = dev; ^ make[3]: *** [drivers/pinctrl/stm32/pinctrl-stm32.o] Error 1 This is due to the field renaming you did in gpio_chip struct: 58383c7 gpio: change member .dev to .parent How do you prefer to proceed? Should I send a fix on top of your devel branch, or you will fix it directly? Thanks, Maxime ^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v4 0/9] Add STM32 pinctrl/GPIO driver 2016-01-27 20:59 ` Maxime Coquelin @ 2016-02-05 22:50 ` Linus Walleij -1 siblings, 0 replies; 47+ messages in thread From: Linus Walleij @ 2016-02-05 22:50 UTC (permalink / raw) To: Maxime Coquelin Cc: Patrice CHOTARD, Mark Rutland, Rob Herring, linux-gpio, Arnd Bergmann, linux-arm-kernel, linux-kernel, Andreas Färber, devicetree, Daniel Thompson, Bruno Herrera On Wed, Jan 27, 2016 at 9:59 PM, Maxime Coquelin <mcoquelin.stm32@gmail.com> wrote: > How do you prefer to proceed? > Should I send a fix on top of your devel branch, or you will fix it > directly? I fixed it now and also got rid of the surplus container_of static inline. Sorry for the delay. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v4 0/9] Add STM32 pinctrl/GPIO driver @ 2016-02-05 22:50 ` Linus Walleij 0 siblings, 0 replies; 47+ messages in thread From: Linus Walleij @ 2016-02-05 22:50 UTC (permalink / raw) To: linux-arm-kernel On Wed, Jan 27, 2016 at 9:59 PM, Maxime Coquelin <mcoquelin.stm32@gmail.com> wrote: > How do you prefer to proceed? > Should I send a fix on top of your devel branch, or you will fix it > directly? I fixed it now and also got rid of the surplus container_of static inline. Sorry for the delay. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 47+ messages in thread
end of thread, other threads:[~2016-02-13 17:14 UTC | newest]
Thread overview: 47+ messages (download: mbox.gz / follow: Atom feed)
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2016-01-14 12:16 [PATCH v4 0/9] Add STM32 pinctrl/GPIO driver Maxime Coquelin
2016-01-14 12:16 ` Maxime Coquelin
2016-01-14 12:16 ` [PATCH v4 1/9] ARM: Kconfig: Introduce MACH_STM32F429 flag Maxime Coquelin
2016-01-14 12:16 ` Maxime Coquelin
2016-01-14 12:16 ` [PATCH v4 2/9] Documentation: dt-bindings: Document STM32 pinctrl driver DT bindings Maxime Coquelin
2016-01-14 12:16 ` Maxime Coquelin
2016-01-15 2:59 ` Rob Herring
2016-01-15 2:59 ` Rob Herring
2016-01-27 13:18 ` Linus Walleij
2016-01-27 13:18 ` Linus Walleij
2016-01-14 12:16 ` [PATCH v4 3/9] includes: dt-bindings: Add STM32F429 pinctrl " Maxime Coquelin
2016-01-14 12:16 ` Maxime Coquelin
2016-01-14 12:16 ` [PATCH v4 4/9] pinctrl: Add STM32 MCUs support Maxime Coquelin
2016-01-14 12:16 ` Maxime Coquelin
[not found] ` <1452773795-24216-5-git-send-email-mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2016-01-27 13:16 ` Linus Walleij
2016-01-27 13:16 ` Linus Walleij
2016-01-27 13:16 ` Linus Walleij
2016-02-01 10:21 ` Arnd Bergmann
2016-02-01 10:21 ` Arnd Bergmann
2016-02-01 10:39 ` Maxime Coquelin
2016-02-01 10:39 ` Maxime Coquelin
2016-02-01 12:09 ` Maxime Coquelin
2016-02-01 12:09 ` Maxime Coquelin
2016-02-13 14:48 ` Linus Walleij
2016-02-13 14:48 ` Linus Walleij
2016-02-13 17:14 ` Maxime Coquelin
2016-02-13 17:14 ` Maxime Coquelin
2016-01-14 12:16 ` [PATCH v4 5/9] ARM: mach-stm32: Select pinctrl Maxime Coquelin
2016-01-14 12:16 ` Maxime Coquelin
2016-01-14 12:16 ` [PATCH v4 6/9] ARM: dts: Add pinctrl node to STM32F429 Maxime Coquelin
2016-01-14 12:16 ` Maxime Coquelin
2016-01-14 12:16 ` [PATCH v4 7/9] ARM: dts: Add USART1 pin config to STM32F429 boards Maxime Coquelin
2016-01-14 12:16 ` Maxime Coquelin
2016-01-14 12:16 ` [PATCH v4 8/9] ARM: dts: Add leds support " Maxime Coquelin
2016-01-14 12:16 ` Maxime Coquelin
[not found] ` <1452773795-24216-1-git-send-email-mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2016-01-14 12:16 ` [PATCH v4 9/9] ARM: config: Enable GPIO Led driver in stm32_defconfig Maxime Coquelin
2016-01-14 12:16 ` Maxime Coquelin
2016-01-14 12:16 ` Maxime Coquelin
2016-01-27 13:20 ` [PATCH v4 0/9] Add STM32 pinctrl/GPIO driver Linus Walleij
2016-01-27 13:20 ` Linus Walleij
[not found] ` <CACRpkdYGQ1xObWfka2CN9au6YMGhpu4qcTZpu72bzuJjO38tog-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-01-27 17:00 ` Maxime Coquelin
2016-01-27 17:00 ` Maxime Coquelin
2016-01-27 17:00 ` Maxime Coquelin
2016-01-27 20:59 ` Maxime Coquelin
2016-01-27 20:59 ` Maxime Coquelin
2016-02-05 22:50 ` Linus Walleij
2016-02-05 22:50 ` Linus Walleij
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