[PATCH v4 00/26] Add support for GuC-based SLPC

[PATCH v4 00/26] Add support for GuC-based SLPC

[Sagar Arun Kamble]

SLPC (Single Loop Power Controller) is a replacement for some host-based
power management features. The SLPC implementation runs in firmware on GuC.

This series has been tested with SKL/BXT GuC firmware version 9.18 which
is yet to be released. Performance and power testing(SKL) with these
patches and 9.18 firmware is at parity and in some cases better than host
RPS today on various Linux benchmarks.

The graphics power management features in SLPC in this version are called
GTPERF, BALANCER, and DCC.

GTPERF is a combination of DFPS (Dynamic FPS) and Turbo. DFPS adjusts
requested graphics frequency to maintain target framerate. Turbo adjusts
requested graphics frequency to maintain target GT busyness; this includes
an adaptive boost turbo method (Disabled currently)

BALANCER adjusts balance between power budgets for IA and GT in power
limited scenarios and based on affinity of workload to IA/GT. BALANCER is
only active when all display pipes are in "game" mode.

DCC (Duty Cycle Control) adjusts requested graphics frequency and stalls
guc-scheduler to maintain actual graphics frequency in efficient range.

The last series can be found in the archive at
"[Intel-gfx] [PATCH v4 00/21] Add support for GuC-based SLPC"
https://lists.freedesktop.org/archives/intel-gfx/2016-April/094445.html

This series incorporates feedback from code reviews on earlier series.
It drops the display mode notification patches as it is not needed for
Turbo part of GTPERF. This series also adds new interface changes for SLPC
support on 9.18 GuC Firmware which is not yet published.
Will like to get review started prior to firmware is published.

SLPC will get enabled on adding support for v9.18 firmware.

v2: Addressed review comments on v1. Removed patch to enable SLPC by
default.

v3: Addressed WARNING in igt@drv_module_reload_basic flagged by trybot BAT.
Added change for sanitizing GT PM during reset. Added separate patch for
sysfs interface to know HW requested frequency. Also, earlier patches did
not go as series hence were not correctly picked up by BAT.

v4: Changes to multiple patches. CI BAT is passing. Performance run on SKL
GT2 done and shows perf at parity with Host Turbo. For BXT, SLPC improves
performance when GuC is enabled compared to Host Turbo and SLPC is at par
with Base except for some minor drops. This series keeps only support of
v9.18 firmware for better readability. If needed, other SLPC interfaces
for different GuC version will be added later. Incorporated change related
slice suggested by Dave. (rebase miss).

VIZ-6773, VIZ-6889, VIZ-6890

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Beuchat, Marc <marc.beuchat@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>


Sagar Arun Kamble (7):
  drm/i915: Remove RPM suspend dependency on rps.enabled and related
    changes
  drm/i915/slpc: Only Enable GTPERF, Disable DCC, Balancer, IBC, FPS
    Stall
  drm/i915/slpc: Update freq min/max softlimits
  drm/i915/slpc: Check GuC load status in SLPC active check
  drm/i915/slpc: Keep RP SW Mode enabled while disabling rps
  drm/i915: Add sysfs interface to know the HW requested frequency
  drm/i915: Mark GuC load status as PENDING in i915_drm_resume_early

Tom O'Rourke (19):
  drm/i915/slpc: Expose guc functions for use with SLPC
  drm/i915/slpc: Add has_slpc capability flag
  drm/i915/slpc: Add SKL SLPC Support
  drm/i915/slpc: Add enable_slpc module parameter
  drm/i915/slpc: Sanitize SLPC version
  drm/i915/slpc: Use intel_slpc_* functions if supported
  drm/i915/slpc: Enable SLPC in guc if supported
  drm/i915/slpc: If using SLPC, do not set frequency
  drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
  drm/i915/slpc: Update sysfs/debugfs interfaces for frequency
    parameters
  drm/i915/slpc: Send reset event
  drm/i915/slpc: Send shutdown event
  drm/i915/slpc: Add slpc_status enum values
  drm/i915/slpc: Add parameter unset/set/get functions
  drm/i915/slpc: Add slpc support for max/min freq
  drm/i915/slpc: Add enable/disable debugfs for slpc
  drm/i915/slpc: Add i915_slpc_info to debugfs
  drm/i915/slpc: Add Broxton SLPC support
  drm/i915/slpc: Enable SLPC, where supported

 drivers/gpu/drm/i915/Makefile              |   3 +-
 drivers/gpu/drm/i915/i915_debugfs.c        | 491 ++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_drv.c            |  21 +-
 drivers/gpu/drm/i915/i915_drv.h            |   4 +-
 drivers/gpu/drm/i915/i915_guc_submission.c |  16 +-
 drivers/gpu/drm/i915/i915_params.c         |   6 +
 drivers/gpu/drm/i915/i915_params.h         |   1 +
 drivers/gpu/drm/i915/i915_pci.c            |   3 +
 drivers/gpu/drm/i915/i915_sysfs.c          |  49 +++
 drivers/gpu/drm/i915/intel_drv.h           |  13 +
 drivers/gpu/drm/i915/intel_guc.h           |  11 +
 drivers/gpu/drm/i915/intel_guc_loader.c    |  30 ++
 drivers/gpu/drm/i915/intel_pm.c            | 133 ++++++--
 drivers/gpu/drm/i915/intel_runtime_pm.c    |   3 +-
 drivers/gpu/drm/i915/intel_slpc.c          | 389 +++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h          | 215 +++++++++++++
 16 files changed, 1334 insertions(+), 54 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.h

-- 
1.9.1

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[PATCH v4 01/26] drm/i915: Remove RPM suspend dependency on rps.enabled and related changes

[Sagar Arun Kamble]

For Gen9, RPM suspend is dependent on rps.enabled. This is needed for
other platforms as RC6 and RPS enabling is indicated by rps.enabled. RPM
Suspend depends only on RC6, so we need to remove the check of rps.enabled.
For Gen9 RC6 and RPS enabling is separated hence do rps.enabled check only
for non-Gen9 platforms. Once RC6 and RPS enabling is separated for other
GENs this check can be completely removed.
Moved setting of rps.enabled to platform level functions as there is case
of disabling of RPS in gen9_enable_rps.

v2: Changing parameter to dev_priv for IS_GEN9 and HAS_RUNTIME_PM and line
    spacing changes. (David)
    and commit message update for checkpatch issues.

v3: Rebase.

v4: Commit message update.

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c         | 14 +++++++++++---
 drivers/gpu/drm/i915/intel_pm.c         | 20 ++++++++++++++++++--
 drivers/gpu/drm/i915/intel_runtime_pm.c |  3 +--
 3 files changed, 30 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 02c34d6..1f677a9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2284,10 +2284,18 @@ static int intel_runtime_suspend(struct device *kdev)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	int ret;
 
-	if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
+	if (WARN_ON_ONCE(!intel_enable_rc6()))
 		return -ENODEV;
 
-	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
+	/*
+	 * Once RC6 and RPS enabling is separated for non-GEN9 platforms
+	 * below check should be removed.
+	*/
+	if (!IS_GEN9(dev_priv))
+		if (WARN_ON_ONCE(!dev_priv->rps.enabled))
+			return -ENODEV;
+
+	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
 		return -ENODEV;
 
 	DRM_DEBUG_KMS("Suspending device\n");
@@ -2391,7 +2399,7 @@ static int intel_runtime_resume(struct device *kdev)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	int ret = 0;
 
-	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
+	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
 		return -ENODEV;
 
 	DRM_DEBUG_KMS("Resuming device\n");
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4f833a0..b9c460c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5061,6 +5061,8 @@ static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
 {
 	I915_WRITE(GEN6_RP_CONTROL, 0);
+
+	dev_priv->rps.enabled = false;
 }
 
 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
@@ -5068,11 +5070,15 @@ static void gen6_disable_rps(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 	I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
 	I915_WRITE(GEN6_RP_CONTROL, 0);
+
+	dev_priv->rps.enabled = false;
 }
 
 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
 {
 	I915_WRITE(GEN6_RC_CONTROL, 0);
+
+	dev_priv->rps.enabled = false;
 }
 
 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
@@ -5084,6 +5090,8 @@ static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = false;
 }
 
 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
@@ -5301,6 +5309,8 @@ static void gen9_enable_rps(struct drm_i915_private *dev_priv)
 	reset_rps(dev_priv, gen6_set_rps);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
@@ -5444,6 +5454,8 @@ static void gen8_enable_rps(struct drm_i915_private *dev_priv)
 	reset_rps(dev_priv, gen6_set_rps);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
@@ -5540,6 +5552,8 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
 	}
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
@@ -6014,6 +6028,8 @@ static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
 	reset_rps(dev_priv, valleyview_set_rps);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
@@ -6094,6 +6110,8 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
 	reset_rps(dev_priv, valleyview_set_rps);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static unsigned long intel_pxfreq(u32 vidfreq)
@@ -6683,7 +6701,6 @@ void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
 		ironlake_disable_drps(dev_priv);
 	}
 
-	dev_priv->rps.enabled = false;
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
@@ -6727,7 +6744,6 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 	WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
 	WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
 
-	dev_priv->rps.enabled = true;
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 6c11168..ed1faf1 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2758,7 +2758,6 @@ void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
 {
 	struct pci_dev *pdev = dev_priv->drm.pdev;
-	struct drm_device *dev = &dev_priv->drm;
 	struct device *kdev = &pdev->dev;
 
 	pm_runtime_set_autosuspend_delay(kdev, 10000); /* 10s */
@@ -2770,7 +2769,7 @@ void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
 	 * so the driver's own RPM reference tracking asserts also work on
 	 * platforms without RPM support.
 	 */
-	if (!HAS_RUNTIME_PM(dev)) {
+	if (!HAS_RUNTIME_PM(dev_priv)) {
 		pm_runtime_dont_use_autosuspend(kdev);
 		pm_runtime_get_sync(kdev);
 	} else {
-- 
1.9.1

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[PATCH v4 02/26] drm/i915/slpc: Expose guc functions for use with SLPC

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Expose host2guc_action for use by SLPC in intel_slpc.c.

Expose functions to allocate and release objects used
by GuC to be used for SLPC shared memory object.

v1: Updated function names as they need to be made extern. (ChrisW)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 16 ++++++++--------
 drivers/gpu/drm/i915/intel_guc.h           |  2 ++
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 77526d7..5f80751 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -47,7 +47,7 @@
  * Firmware writes a success/fail code back to the action register after
  * processes the request. The kernel driver polls waiting for this update and
  * then proceeds.
- * See host2guc_action()
+ * See i915_guc_action()
  *
  * Doorbells:
  * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
@@ -75,7 +75,7 @@ static inline bool host2guc_action_response(struct drm_i915_private *dev_priv,
 	return GUC2HOST_IS_RESPONSE(val);
 }
 
-static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
+int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
 	u32 status;
@@ -139,7 +139,7 @@ static int host2guc_allocate_doorbell(struct intel_guc *guc,
 	data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL;
 	data[1] = client->ctx_index;
 
-	return host2guc_action(guc, data, 2);
+	return i915_guc_action(guc, data, 2);
 }
 
 static int host2guc_release_doorbell(struct intel_guc *guc,
@@ -150,7 +150,7 @@ static int host2guc_release_doorbell(struct intel_guc *guc,
 	data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL;
 	data[1] = client->ctx_index;
 
-	return host2guc_action(guc, data, 2);
+	return i915_guc_action(guc, data, 2);
 }
 
 static int host2guc_sample_forcewake(struct intel_guc *guc,
@@ -167,7 +167,7 @@ static int host2guc_sample_forcewake(struct intel_guc *guc,
 		/* bit 0 and 1 are for Render and Media domain separately */
 		data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
 
-	return host2guc_action(guc, data, ARRAY_SIZE(data));
+	return i915_guc_action(guc, data, ARRAY_SIZE(data));
 }
 
 /*
@@ -620,7 +620,7 @@ static void i915_guc_submit(struct drm_i915_gem_request *rq)
  *
  * Return:	A i915_vma if successful, otherwise an ERR_PTR.
  */
-static struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size)
+struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
 	struct drm_i915_gem_object *obj;
@@ -1064,7 +1064,7 @@ int intel_guc_suspend(struct drm_device *dev)
 	/* first page is shared data with GuC */
 	data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
 
-	return host2guc_action(guc, data, ARRAY_SIZE(data));
+	return i915_guc_action(guc, data, ARRAY_SIZE(data));
 }
 
 
@@ -1089,5 +1089,5 @@ int intel_guc_resume(struct drm_device *dev)
 	/* first page is shared data with GuC */
 	data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
 
-	return host2guc_action(guc, data, ARRAY_SIZE(data));
+	return i915_guc_action(guc, data, ARRAY_SIZE(data));
 }
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index c973262..9e6b948 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -155,9 +155,11 @@ extern int intel_guc_suspend(struct drm_device *dev);
 extern int intel_guc_resume(struct drm_device *dev);
 
 /* i915_guc_submission.c */
+int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len);
 int i915_guc_submission_init(struct drm_i915_private *dev_priv);
 int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
 int i915_guc_wq_check_space(struct drm_i915_gem_request *rq);
+struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size);
 void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
 void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
 
-- 
1.9.1

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[PATCH v4 03/26] drm/i915/slpc: Add has_slpc capability flag

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Add has_slpc capablity flag to indicate GuC firmware
supports single loop power control (SLPC).  SLPC is
a replacement for some host-based power management
features.

v1: fix whitespace (Sagar)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f39bede..069d269 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -677,7 +677,8 @@ struct intel_csr {
 	func(has_snoop) sep \
 	func(has_ddi) sep \
 	func(has_fpga_dbg) sep \
-	func(has_pooled_eu)
+	func(has_pooled_eu) sep \
+	func(has_slpc)
 
 #define DEFINE_FLAG(name) u8 name:1
 #define SEP_SEMICOLON ;
@@ -2811,6 +2812,7 @@ struct drm_i915_cmd_table {
 #define HAS_GUC(dev)		(INTEL_INFO(dev)->has_guc)
 #define HAS_GUC_UCODE(dev)	(HAS_GUC(dev))
 #define HAS_GUC_SCHED(dev)	(HAS_GUC(dev))
+#define HAS_SLPC(dev)		(INTEL_INFO(dev)->has_slpc)
 
 #define HAS_RESOURCE_STREAMER(dev) (INTEL_INFO(dev)->has_resource_streamer)
 
-- 
1.9.1

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[PATCH v4 04/26] drm/i915/slpc: Add SKL SLPC Support

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

This patch adds has_slpc to skylake info.

The SLPC interface has changed and could continue to
change. Only GuC versions known to be compatible are
supported here.

On Skylake, GuC firmware v6 is supported.  Other
platforms and versions can be added here later.

v1: Move slpc_version_check to intel_guc_ucode_init.
    fix whitespace (Sagar)
    Moved version check to different patch as has_slpc
    should not be updated based on it. Instead module parameter
    should be updated based on version check. (Sagar)
    Added support to skylake_gt3 as well. (Sagar)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d771870d..873565c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -328,6 +328,7 @@ static const struct intel_device_info intel_skylake_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.has_slpc = 1,
 };
 
 static const struct intel_device_info intel_skylake_gt3_info = {
@@ -336,6 +337,7 @@ static const struct intel_device_info intel_skylake_gt3_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.has_slpc = 1,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
-- 
1.9.1

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[PATCH v4 05/26] drm/i915/slpc: Add enable_slpc module parameter

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

i915.enable_slpc is used to override the default for slpc usage.
The expected values are -1=auto, 0=disabled [default], 1=enabled.

slpc_enable_sanitize() converts i915.enable_slpc to either 0 or 1.
Interpretation of default value is based on HAS_SLPC(), after
slpc_version_check().  This function also enforces the requirement
that guc_submission is required for slpc.

intel_slpc_enabled() returns 1 if SLPC should be used.

v1: Add early call to sanitize enable_slpc in intel_guc_ucode_init
    Remove sanitize enable_slpc call before firmware version check
    is performed. (ChrisW)
    Version check is added in next patch and that will be done as
    part of slpc_enable_sanitize function in the next patch. (Sagar)
    Updated slpc option sanitize function call for platforms without
    GuC support. This was caught by CI BAT.

v2: Changed parameter to dev_priv for HAS_SLPC macro. (David)
    Code indentation based on checkpatch.

v3: Rebase.

v4: Moved sanitization of SLPC option post GuC load.

Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_params.c      |  6 ++++++
 drivers/gpu/drm/i915/i915_params.h      |  1 +
 drivers/gpu/drm/i915/intel_guc.h        |  7 +++++++
 drivers/gpu/drm/i915/intel_guc_loader.c | 19 +++++++++++++++++++
 drivers/gpu/drm/i915/intel_pm.c         |  2 ++
 5 files changed, 35 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 768ad89..72b3097 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -36,6 +36,7 @@ struct i915_params i915 __read_mostly = {
 	.enable_dc = -1,
 	.enable_fbc = -1,
 	.enable_execlists = -1,
+	.enable_slpc = 0,
 	.enable_hangcheck = true,
 	.enable_ppgtt = -1,
 	.enable_psr = -1,
@@ -131,6 +132,11 @@ MODULE_PARM_DESC(enable_execlists,
 	"Override execlists usage. "
 	"(-1=auto [default], 0=disabled, 1=enabled)");
 
+module_param_named_unsafe(enable_slpc, i915.enable_slpc, int, 0400);
+MODULE_PARM_DESC(enable_slpc,
+	"Override single-loop-power-controller (slpc) usage. "
+	"(-1=auto, 0=disabled [default], 1=enabled)");
+
 module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600);
 MODULE_PARM_DESC(enable_psr, "Enable PSR "
 		 "(0=disabled, 1=enabled - link mode chosen per-platform, 2=force link-standby mode, 3=force link-off mode) "
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 3a0dd78..391c471 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -39,6 +39,7 @@ struct i915_params {
 	int enable_fbc;
 	int enable_ppgtt;
 	int enable_execlists;
+	int enable_slpc;
 	int enable_psr;
 	unsigned int preliminary_hw_support;
 	int disable_power_well;
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 9e6b948..d73e4ed 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -146,6 +146,12 @@ struct intel_guc {
 	uint32_t last_seqno[I915_NUM_ENGINES];
 };
 
+static inline int intel_slpc_enabled(void)
+{
+	WARN_ON(i915.enable_slpc < 0);
+	return i915.enable_slpc;
+}
+
 /* intel_guc_loader.c */
 extern void intel_guc_init(struct drm_device *dev);
 extern int intel_guc_setup(struct drm_device *dev);
@@ -153,6 +159,7 @@ extern void intel_guc_fini(struct drm_device *dev);
 extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
 extern int intel_guc_suspend(struct drm_device *dev);
 extern int intel_guc_resume(struct drm_device *dev);
+extern void sanitize_slpc_option(struct drm_i915_private *dev_priv);
 
 /* i915_guc_submission.c */
 int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 853928f..fb38018 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -144,6 +144,25 @@ static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
 	}
 }
 
+void sanitize_slpc_option(struct drm_i915_private *dev_priv)
+{
+	/* Handle default case */
+	if (i915.enable_slpc < 0)
+		i915.enable_slpc = HAS_SLPC(dev_priv);
+
+	/* slpc requires hardware support and compatible firmware */
+	if (!HAS_SLPC(dev_priv))
+		i915.enable_slpc = 0;
+
+	/* slpc requires guc loaded */
+	if (!i915.enable_guc_loading)
+		i915.enable_slpc = 0;
+
+	/* slpc requires guc submission */
+	if (!i915.enable_guc_submission)
+		i915.enable_slpc = 0;
+}
+
 static u32 get_gttype(struct drm_i915_private *dev_priv)
 {
 	/* XXX: GT type based on PCI device ID? field seems unused by fw */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b9c460c..56bde62 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6598,6 +6598,8 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
 		intel_runtime_pm_get(dev_priv);
 	}
 
+	sanitize_slpc_option(dev_priv);
+
 	mutex_lock(&dev_priv->drm.struct_mutex);
 	mutex_lock(&dev_priv->rps.hw_lock);
 
-- 
1.9.1

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[PATCH v4 06/26] drm/i915/slpc: Sanitize SLPC version

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

The SLPC interface has changed and could continue to
change.  Only GuC versions known to be compatible are
supported here.

On Skylake, GuC firmware v9 is supported.  Other
platforms and versions can be added here later.

v1: Updated with modified sanitize_slpc_option in earlier patch.

v2-v3: Rebase.

v4: Updated support for GuC firmware v9.

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index fb38018..500b0b6 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -146,6 +146,8 @@ static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
 
 void sanitize_slpc_option(struct drm_i915_private *dev_priv)
 {
+	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+
 	/* Handle default case */
 	if (i915.enable_slpc < 0)
 		i915.enable_slpc = HAS_SLPC(dev_priv);
@@ -161,6 +163,9 @@ void sanitize_slpc_option(struct drm_i915_private *dev_priv)
 	/* slpc requires guc submission */
 	if (!i915.enable_guc_submission)
 		i915.enable_slpc = 0;
+
+	if (IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 9))
+		i915.enable_slpc = 0;
 }
 
 static u32 get_gttype(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[PATCH v4 07/26] drm/i915/slpc: Use intel_slpc_* functions if supported

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

On platforms with SLPC support: call intel_slpc_*()
functions from corresponding intel_*_gt_powersave()
functions; and do not use rps functions.

v1: Return void instead of ignored error code (Paulo)
    enable/disable RC6 in SLPC flows (Sagar)
    replace HAS_SLPC() use with intel_slpc_enabled()
	or intel_slpc_active() (Paulo)
    Fix for renaming gen9_disable_rps to gen9_disable_rc6 in
    "drm/i915/bxt: Explicitly clear the Turbo control register"
    Defer RC6 and SLPC enabling to intel_gen6_powersave_work. (Sagar)
    Performance drop with SLPC was happening as ring frequency table
    was not programmed when SLPC was enabled. This patch programs ring
    frequency table with SLPC. Initial reset of SLPC is based on kernel
    parameter as planning to add slpc state in intel_slpc_active. Cleanup
    is also based on kernel parameter as SLPC gets disabled in
    disable/suspend.(Sagar)

v2: Usage of INTEL_GEN instead of INTEL_INFO->gen (David)
    Checkpatch update.

v3: Rebase

v4: Removed reset functions to comply with *_gt_powersave routines.
    (Sagar)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/Makefile     |  3 +-
 drivers/gpu/drm/i915/intel_drv.h  |  4 ++
 drivers/gpu/drm/i915/intel_guc.h  |  1 +
 drivers/gpu/drm/i915/intel_pm.c   | 96 +++++++++++++++++++++++++++------------
 drivers/gpu/drm/i915/intel_slpc.c | 46 +++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h | 34 ++++++++++++++
 6 files changed, 153 insertions(+), 31 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a7da246..229290d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -52,7 +52,8 @@ i915-y += i915_cmd_parser.o \
 
 # general-purpose microcontroller (GuC) support
 i915-y += intel_guc_loader.o \
-	  i915_guc_submission.o
+	  i915_guc_submission.o \
+	  intel_slpc.o
 
 # autogenerated null render state
 i915-y += intel_renderstate_gen6.o \
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7868d5c..cf9aa24 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1705,6 +1705,10 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder,
 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 			  enum dpio_channel ch, bool override);
 
+static inline int intel_slpc_active(struct drm_i915_private *dev_priv)
+{
+	return 0;
+}
 
 /* intel_pm.c */
 void intel_init_clock_gating(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index d73e4ed..83dec66 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -27,6 +27,7 @@
 #include "intel_guc_fwif.h"
 #include "i915_guc_reg.h"
 #include "intel_ringbuffer.h"
+#include "intel_slpc.h"
 
 struct drm_i915_gem_request;
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 56bde62..db5c4ef 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4988,7 +4988,8 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
 	 * our rpm wakeref. And then disable the interrupts to stop any
 	 * futher RPS reclocking whilst we are asleep.
 	 */
-	gen6_disable_rps_interrupts(dev_priv);
+	if (!intel_slpc_active(dev_priv))
+		gen6_disable_rps_interrupts(dev_priv);
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 	if (dev_priv->rps.enabled) {
@@ -6641,6 +6642,9 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
 	/* Finally allow us to boost to max by default */
 	dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
 
+	if (intel_slpc_enabled())
+		intel_slpc_init(dev_priv);
+
 	mutex_unlock(&dev_priv->rps.hw_lock);
 	mutex_unlock(&dev_priv->drm.struct_mutex);
 
@@ -6649,7 +6653,9 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
 
 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (IS_VALLEYVIEW(dev_priv))
+	if (intel_slpc_enabled())
+		intel_slpc_cleanup(dev_priv);
+	else if (IS_VALLEYVIEW(dev_priv))
 		valleyview_cleanup_gt_powersave(dev_priv);
 
 	if (!i915.enable_rc6)
@@ -6673,24 +6679,38 @@ void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
 		intel_runtime_pm_put(dev_priv);
 
 	/* gen6_rps_idle() will be called later to disable interrupts */
+
+	if (intel_slpc_active(dev_priv))
+		intel_slpc_suspend(dev_priv);
 }
 
 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	dev_priv->rps.enabled = true; /* force disabling */
-	intel_disable_gt_powersave(dev_priv);
+	if (intel_slpc_enabled()) {
+		/* TODO: Set SLPC enabled forcefully */
+		intel_disable_gt_powersave(dev_priv);
+	} else {
+		dev_priv->rps.enabled = true; /* force disabling */
+		intel_disable_gt_powersave(dev_priv);
 
-	gen6_reset_rps_interrupts(dev_priv);
+		gen6_reset_rps_interrupts(dev_priv);
+	}
 }
 
 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (!READ_ONCE(dev_priv->rps.enabled))
+	if (intel_slpc_enabled()) {
+		if (!intel_slpc_active(dev_priv))
+			return;
+	} else if (!READ_ONCE(dev_priv->rps.enabled))
 		return;
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (intel_slpc_active(dev_priv)) {
+		gen9_disable_rc6(dev_priv);
+		intel_slpc_disable(dev_priv);
+	} else if (INTEL_GEN(dev_priv) >= 9) {
 		gen9_disable_rc6(dev_priv);
 		gen9_disable_rps(dev_priv);
 	} else if (IS_CHERRYVIEW(dev_priv)) {
@@ -6711,7 +6731,10 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 	/* We shouldn't be disabling as we submit, so this should be less
 	 * racy than it appears!
 	 */
-	if (READ_ONCE(dev_priv->rps.enabled))
+	if (intel_slpc_enabled()) {
+		if (intel_slpc_active(dev_priv))
+			return;
+	} else if (READ_ONCE(dev_priv->rps.enabled))
 		return;
 
 	/* Powersaving is controlled by the host when inside a VM */
@@ -6720,31 +6743,38 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 
-	if (IS_CHERRYVIEW(dev_priv)) {
-		cherryview_enable_rps(dev_priv);
-	} else if (IS_VALLEYVIEW(dev_priv)) {
-		valleyview_enable_rps(dev_priv);
-	} else if (INTEL_GEN(dev_priv) >= 9) {
+	if (intel_slpc_enabled()) {
 		gen9_enable_rc6(dev_priv);
-		gen9_enable_rps(dev_priv);
+		intel_slpc_enable(dev_priv);
 		if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 			gen6_update_ring_freq(dev_priv);
-	} else if (IS_BROADWELL(dev_priv)) {
-		gen8_enable_rps(dev_priv);
-		gen6_update_ring_freq(dev_priv);
-	} else if (INTEL_GEN(dev_priv) >= 6) {
-		gen6_enable_rps(dev_priv);
-		gen6_update_ring_freq(dev_priv);
-	} else if (IS_IRONLAKE_M(dev_priv)) {
-		ironlake_enable_drps(dev_priv);
-		intel_init_emon(dev_priv);
-	}
+	} else {
+		if (IS_CHERRYVIEW(dev_priv)) {
+			cherryview_enable_rps(dev_priv);
+		} else if (IS_VALLEYVIEW(dev_priv)) {
+			valleyview_enable_rps(dev_priv);
+		} else if (INTEL_GEN(dev_priv) >= 9) {
+			gen9_enable_rc6(dev_priv);
+			gen9_enable_rps(dev_priv);
+			if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
+				gen6_update_ring_freq(dev_priv);
+		} else if (IS_BROADWELL(dev_priv)) {
+			gen8_enable_rps(dev_priv);
+			gen6_update_ring_freq(dev_priv);
+		} else if (INTEL_GEN(dev_priv) >= 6) {
+			gen6_enable_rps(dev_priv);
+			gen6_update_ring_freq(dev_priv);
+		} else if (IS_IRONLAKE_M(dev_priv)) {
+			ironlake_enable_drps(dev_priv);
+			intel_init_emon(dev_priv);
+		}
 
-	WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
-	WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
+		WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
+		WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
 
-	WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
-	WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
+		WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
+		WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
+	}
 
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
@@ -6756,7 +6786,10 @@ static void __intel_autoenable_gt_powersave(struct work_struct *work)
 	struct intel_engine_cs *rcs;
 	struct drm_i915_gem_request *req;
 
-	if (READ_ONCE(dev_priv->rps.enabled))
+	if (intel_slpc_enabled()) {
+		if (intel_slpc_active(dev_priv))
+			goto out;
+	} else if (READ_ONCE(dev_priv->rps.enabled))
 		goto out;
 
 	rcs = &dev_priv->engine[RCS];
@@ -6786,7 +6819,10 @@ out:
 
 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (READ_ONCE(dev_priv->rps.enabled))
+	if (intel_slpc_enabled()) {
+		if (intel_slpc_active(dev_priv))
+			return;
+	} else if (READ_ONCE(dev_priv->rps.enabled))
 		return;
 
 	if (IS_IRONLAKE_M(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
new file mode 100644
index 0000000..be9e84c
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#include <linux/firmware.h>
+#include "i915_drv.h"
+#include "intel_guc.h"
+
+void intel_slpc_init(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_suspend(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_disable(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_enable(struct drm_i915_private *dev_priv)
+{
+}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
new file mode 100644
index 0000000..28296f1
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#ifndef _INTEL_SLPC_H_
+#define _INTEL_SLPC_H_
+
+/* intel_slpc.c */
+void intel_slpc_init(struct drm_i915_private *dev_priv);
+void intel_slpc_cleanup(struct drm_i915_private *dev_priv);
+void intel_slpc_suspend(struct drm_i915_private *dev_priv);
+void intel_slpc_disable(struct drm_i915_private *dev_priv);
+void intel_slpc_enable(struct drm_i915_private *dev_priv);
+
+#endif
-- 
1.9.1

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[PATCH v4 08/26] drm/i915/slpc: Enable SLPC in guc if supported

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

If slpc enabled, then add enable SLPC flag to guc
control parameter during guc load.

v1: Use intel_slpc_enabled() (Paulo)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 500b0b6..2dda771 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -213,6 +213,9 @@ static void set_guc_init_params(struct drm_i915_private *dev_priv)
 	params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
 			GUC_CTL_VCS2_ENABLED;
 
+	if (intel_slpc_enabled())
+		params[GUC_CTL_FEATURE] |= GUC_CTL_ENABLE_SLPC;
+
 	if (i915.guc_log_level >= 0) {
 		params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
 		params[GUC_CTL_DEBUG] =
-- 
1.9.1

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[PATCH v4 09/26] drm/i915/slpc: If using SLPC, do not set frequency

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

When frequency requests are made by SLPC, host driver
should not attempt to make frequency requests due to
potential conflicts.

Host-based turbo operations are already avoided when
SLPC is used.  This change covers other frequency
requests such as from sysfs or debugfs interfaces.

A later patch in this series updates sysfs/debugfs
interfaces for setting max/min frequencies with SLPC.

v1: Use intel_slpc_active instead of HAS_SLPC (Paulo)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index db5c4ef..d187066 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5047,6 +5047,9 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv,
 
 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
 {
+	if (intel_slpc_active(dev_priv))
+		return;
+
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		valleyview_set_rps(dev_priv, val);
 	else
-- 
1.9.1

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[PATCH v4 10/26] drm/i915/slpc: Allocate/Release/Initialize SLPC shared data

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

SLPC shared data is used to pass information
to/from SLPC in GuC firmware.

For Skylake, platform sku type and slice count
are identified from device id and fuse values.

Support for other platforms needs to be added.

v1: Update for SLPC interface version 2015.2.4
    intel_slpc_active() returns 1 if slpc initialized (Paulo)
    change default host_os to "Windows"
    Spelling fixes (Sagar Kamble and Nick Hoath)
    Added WARN for checking if upper 32bits of GTT offset
    of shared object are zero. (ChrisW)
    Changed function call from gem_allocate/release_guc_obj to
    i915_guc_allocate/release_gem_obj. (Sagar)
    Updated commit message and moved POWER_PLAN and POWER_SOURCE
    definition from later patch. (Akash)
    Add struct_mutex locking while allocating/releasing slpc shared
    object. This was caught by CI BAT. Adding SLPC state variable
    to determine if it is active as it not just dependent on shared
    data setup.
    Rebase with guc_allocate_vma related changes.

v2: WARN_ON for platform_sku validity and space changes. (David)
    Checkpatch update.

v3: Fixing WARNING in igt@drv_module_reload_basic found in trybot BAT
    with SLPC Enabled.

v4: Updated support for GuC v9. s/slice_total/hweight8(slice_mask)/ (Dave).

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h  |  7 ++-
 drivers/gpu/drm/i915/intel_guc.h  |  2 +
 drivers/gpu/drm/i915/intel_pm.c   |  6 ++-
 drivers/gpu/drm/i915/intel_slpc.c | 88 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h | 99 +++++++++++++++++++++++++++++++++++++++
 5 files changed, 199 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index cf9aa24..796c52f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1707,7 +1707,12 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 
 static inline int intel_slpc_active(struct drm_i915_private *dev_priv)
 {
-	return 0;
+	int ret = 0;
+
+	if (dev_priv->guc.slpc.vma && dev_priv->guc.slpc.enabled)
+		ret = 1;
+
+	return ret;
 }
 
 /* intel_pm.c */
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 83dec66..6e24e60 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -145,6 +145,8 @@ struct intel_guc {
 
 	uint64_t submissions[I915_NUM_ENGINES];
 	uint32_t last_seqno[I915_NUM_ENGINES];
+
+	struct intel_slpc slpc;
 };
 
 static inline int intel_slpc_enabled(void)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d187066..2211f7b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6656,7 +6656,8 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
 
 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (intel_slpc_enabled())
+	if (intel_slpc_enabled() &&
+	    dev_priv->guc.slpc.vma)
 		intel_slpc_cleanup(dev_priv);
 	else if (IS_VALLEYVIEW(dev_priv))
 		valleyview_cleanup_gt_powersave(dev_priv);
@@ -6746,7 +6747,8 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 
-	if (intel_slpc_enabled()) {
+	if (intel_slpc_enabled() &&
+	    dev_priv->guc.slpc.vma) {
 		gen9_enable_rc6(dev_priv);
 		intel_slpc_enable(dev_priv);
 		if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index be9e84c..972db18 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -22,15 +22,103 @@
  *
  */
 #include <linux/firmware.h>
+#include <asm/msr-index.h>
 #include "i915_drv.h"
 #include "intel_guc.h"
 
+static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
+{
+	enum slpc_platform_sku platform_sku;
+
+	if (IS_SKL_ULX(dev_priv))
+		platform_sku = SLPC_PLATFORM_SKU_ULX;
+	else if (IS_SKL_ULT(dev_priv))
+		platform_sku = SLPC_PLATFORM_SKU_ULT;
+	else
+		platform_sku = SLPC_PLATFORM_SKU_DT;
+
+	WARN_ON(platform_sku > 0xFF);
+
+	return platform_sku;
+}
+
+static unsigned int slpc_get_slice_count(struct drm_i915_private *dev_priv)
+{
+	unsigned int slice_count = 1;
+
+	if (IS_SKYLAKE(dev_priv))
+		slice_count = hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask);
+
+	return slice_count;
+}
+
+static void slpc_shared_data_init(struct drm_i915_private *dev_priv)
+{
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	struct slpc_shared_data *data;
+	u64 msr_value;
+
+	if (!dev_priv->guc.slpc.vma)
+		return;
+
+	obj = dev_priv->guc.slpc.vma->obj;
+
+	page = i915_gem_object_get_page(obj, 0);
+	if (page) {
+		data = kmap_atomic(page);
+		memset(data, 0, sizeof(struct slpc_shared_data));
+
+		data->shared_data_size = sizeof(struct slpc_shared_data);
+		data->global_state = (u32)SLPC_GLOBAL_STATE_NOT_RUNNING;
+		data->platform_info.platform_sku =
+					(u8)slpc_get_platform_sku(dev_priv);
+		data->platform_info.slice_count =
+					(u8)slpc_get_slice_count(dev_priv);
+		data->platform_info.power_plan_source =
+			(u8)SLPC_POWER_PLAN_SOURCE(SLPC_POWER_PLAN_BALANCED,
+						    SLPC_POWER_SOURCE_AC);
+		rdmsrl(MSR_TURBO_RATIO_LIMIT, msr_value);
+		data->platform_info.P0_freq = (u8)msr_value;
+		rdmsrl(MSR_PLATFORM_INFO, msr_value);
+		data->platform_info.P1_freq = (u8)(msr_value >> 8);
+		data->platform_info.Pe_freq = (u8)(msr_value >> 40);
+		data->platform_info.Pn_freq = (u8)(msr_value >> 48);
+
+		kunmap_atomic(data);
+	}
+}
+
 void intel_slpc_init(struct drm_i915_private *dev_priv)
 {
+	struct intel_guc *guc = &dev_priv->guc;
+	struct i915_vma *vma;
+
+	/* Allocate shared data structure */
+	vma = dev_priv->guc.slpc.vma;
+	if (!vma) {
+		vma = guc_allocate_vma(guc,
+			       PAGE_ALIGN(sizeof(struct slpc_shared_data)));
+		if (IS_ERR(vma)) {
+			DRM_ERROR("slpc_shared_data allocation failed\n");
+			i915.enable_slpc = 0;
+			return;
+		}
+
+		dev_priv->guc.slpc.vma = vma;
+	}
+
+	slpc_shared_data_init(dev_priv);
 }
 
 void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
 {
+	struct intel_guc *guc = &dev_priv->guc;
+
+	/* Release shared data structure */
+	mutex_lock(&dev_priv->drm.struct_mutex);
+	i915_vma_unpin_and_release(&guc->slpc.vma);
+	mutex_unlock(&dev_priv->drm.struct_mutex);
 }
 
 void intel_slpc_suspend(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 28296f1..6cdbc96 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -24,6 +24,105 @@
 #ifndef _INTEL_SLPC_H_
 #define _INTEL_SLPC_H_
 
+enum slpc_global_state {
+	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
+	SLPC_GLOBAL_STATE_INITIALIZING = 1,
+	SLPC_GLOBAL_STATE_RESETTING = 2,
+	SLPC_GLOBAL_STATE_RUNNING = 3,
+	SLPC_GLOBAL_STATE_SHUTTING_DOWN = 4,
+	SLPC_GLOBAL_STATE_ERROR = 5
+};
+
+enum slpc_platform_sku {
+	SLPC_PLATFORM_SKU_UNDEFINED = 0,
+	SLPC_PLATFORM_SKU_ULX = 1,
+	SLPC_PLATFORM_SKU_ULT = 2,
+	SLPC_PLATFORM_SKU_T = 3,
+	SLPC_PLATFORM_SKU_MOBL = 4,
+	SLPC_PLATFORM_SKU_DT = 5,
+	SLPC_PLATFORM_SKU_UNKNOWN = 6,
+};
+
+enum slpc_power_plan {
+	SLPC_POWER_PLAN_UNDEFINED = 0,
+	SLPC_POWER_PLAN_BATTERY_SAVER = 1,
+	SLPC_POWER_PLAN_BALANCED = 2,
+	SLPC_POWER_PLAN_PERFORMANCE = 3,
+	SLPC_POWER_PLAN_UNKNOWN = 4,
+};
+
+enum slpc_power_source {
+	SLPC_POWER_SOURCE_UNDEFINED = 0,
+	SLPC_POWER_SOURCE_AC = 1,
+	SLPC_POWER_SOURCE_DC = 2,
+	SLPC_POWER_SOURCE_UNKNOWN = 3,
+};
+
+#define SLPC_POWER_PLAN_SOURCE(plan, source) ((plan) | ((source) << 6))
+#define SLPC_POWER_PLAN(plan_source) ((plan_source) & 0x3F)
+#define SLPC_POWER_SOURCE(plan_source) ((plan_source) >> 6)
+
+struct slpc_platform_info {
+	u8 platform_sku;
+	u8 slice_count;
+	u8 reserved;
+	u8 power_plan_source;
+	u8 P0_freq;
+	u8 P1_freq;
+	u8 Pe_freq;
+	u8 Pn_freq;
+	u32 reserved1;
+	u32 reserved2;
+} __packed;
+
+struct slpc_task_state_data {
+	union {
+		u32 bitfield1;
+		struct {
+			u32 gtperf_task_active:1;
+			u32 gtperf_stall_possible:1;
+			u32 gtperf_gaming_mode:1;
+			u32 gtperf_target_fps:8;
+			u32 dcc_task_active:1;
+			u32 in_dcc:1;
+			u32 in_dct:1;
+			u32 freq_switch_active:1;
+			u32 ibc_enabled:1;
+			u32 ibc_active:1;
+			u32 pg1_enabled:1;
+			u32 pg1_active:1;
+			u32 reserved:13;
+		};
+	};
+	union {
+		u32 bitfield2;
+		struct {
+			u32 freq_unslice_max:8;
+			u32 freq_unslice_min:8;
+			u32 freq_slice_max:8;
+			u32 freq_slice_min:8;
+		};
+	};
+};
+
+#define SLPC_MAX_OVERRIDE_PARAMETERS 192
+#define SLPC_OVERRIDE_BITFIELD_SIZE ((SLPC_MAX_OVERRIDE_PARAMETERS + 31) / 32)
+
+struct slpc_shared_data {
+	u32 reserved;
+	u32 shared_data_size;
+	u32 global_state;
+	struct slpc_platform_info platform_info;
+	struct slpc_task_state_data task_state_data;
+	u32 override_parameters_set_bits[SLPC_OVERRIDE_BITFIELD_SIZE];
+	u32 override_parameters_values[SLPC_MAX_OVERRIDE_PARAMETERS];
+} __packed;
+
+struct intel_slpc {
+	struct i915_vma *vma;
+	bool enabled;
+};
+
 /* intel_slpc.c */
 void intel_slpc_init(struct drm_i915_private *dev_priv);
 void intel_slpc_cleanup(struct drm_i915_private *dev_priv);
-- 
1.9.1

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[PATCH v4 11/26] drm/i915/slpc: Update sysfs/debugfs interfaces for frequency parameters

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

When SLPC is controlling requested frequency, the rps.cur_freq
value is not used to make the frequency request.

Requested frequency from register RPNSWREQ has the value
most recently requested by SLPC firmware. Adding new sysfs
interface gt_req_freq_mhz to know this value.
SLPC requested value needs to be made available to i915 without
reading RPNSWREQ.

v1: Replace HAS_SLPC with intel_slpc_active (Paulo)
    Avoid magic numbers (Nick)
    Use a function for repeated code (Jon)

v2: Add "SLPC Active" to i915_frequency_info output and
    don't update cur_freq as it is driver internal request. (Chris)

v3: Removing sysfs interface gt_req_freq_mhz out of this patch
    for proper division of functionality. (Sagar)

v4: idle_freq, boost_freq are also not used with SLPC.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 24 ++++++++++++++++++------
 drivers/gpu/drm/i915/i915_sysfs.c   |  3 +++
 2 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 02b627e..71bce32 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1083,6 +1083,9 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 
 	intel_runtime_pm_get(dev_priv);
 
+	if (intel_slpc_active(dev_priv))
+		seq_puts(m, "SLPC Active\n");
+
 	if (IS_GEN5(dev_priv)) {
 		u16 rgvswctl = I915_READ16(MEMSWCTL);
 		u16 rgvstat = I915_READ16(MEMSTAT_ILK);
@@ -1250,15 +1253,21 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		seq_printf(m, "Max overclocked frequency: %dMHz\n",
 			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
 
-		seq_printf(m, "Current freq: %d MHz\n",
-			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
+		if (!intel_slpc_active(dev_priv)) {
+			seq_printf(m, "Current freq: %d MHz\n",
+				   intel_gpu_freq(dev_priv,
+						  dev_priv->rps.cur_freq));
+			seq_printf(m, "Idle freq: %d MHz\n",
+				   intel_gpu_freq(dev_priv,
+						  dev_priv->rps.idle_freq));
+			seq_printf(m, "Boost freq: %d MHz\n",
+				   intel_gpu_freq(dev_priv,
+						  dev_priv->rps.boost_freq));
+		}
+
 		seq_printf(m, "Actual freq: %d MHz\n", cagf);
-		seq_printf(m, "Idle freq: %d MHz\n",
-			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
 		seq_printf(m, "Min freq: %d MHz\n",
 			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
-		seq_printf(m, "Boost freq: %d MHz\n",
-			   intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
 		seq_printf(m, "Max freq: %d MHz\n",
 			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
 		seq_printf(m,
@@ -2315,6 +2324,9 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
 	struct drm_device *dev = &dev_priv->drm;
 	struct drm_file *file;
 
+	if (intel_slpc_active(dev_priv))
+		return -ENODEV;
+
 	seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
 	seq_printf(m, "GPU busy? %s [%x]\n",
 		   yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 1012eee..020d64e 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -299,6 +299,9 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
 {
 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 
+	if (intel_slpc_active(dev_priv))
+		return -ENODEV;
+
 	return snprintf(buf, PAGE_SIZE, "%d\n",
 			intel_gpu_freq(dev_priv,
 				       dev_priv->rps.cur_freq));
-- 
1.9.1

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[PATCH v4 12/26] drm/i915/slpc: Send reset event

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Add host2guc SLPC reset event and send reset event
during enable.

v1: Extract host2guc_slpc to handle slpc status code
    coding style changes (Paulo)
    Removed WARN_ON for checking msb of gtt address of
    shared gem obj. (ChrisW)
    host2guc_action to i915_guc_action change.(Sagar)
    Updating SLPC enabled status. (Sagar)

v2: Commit message update. (David)

v3: Rebase.

v4: Added DRM_INFO message when SLPC is enabled.

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 29 +++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h | 14 ++++++++++++++
 2 files changed, 43 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 972db18..3b99231 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -26,6 +26,32 @@
 #include "i915_drv.h"
 #include "intel_guc.h"
 
+static void host2guc_slpc(struct drm_i915_private *dev_priv, u32 *data, u32 len)
+{
+	int ret = i915_guc_action(&dev_priv->guc, data, len);
+
+	if (!ret) {
+		ret = I915_READ(SOFT_SCRATCH(1));
+		ret &= SLPC_EVENT_STATUS_MASK;
+	}
+
+	if (ret)
+		DRM_ERROR("event 0x%x status %d\n", (data[1] >> 8), ret);
+}
+
+static void host2guc_slpc_reset(struct drm_i915_private *dev_priv)
+{
+	u32 data[4];
+	u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_RESET, 2);
+	data[2] = shared_data_gtt_offset;
+	data[3] = 0;
+
+	host2guc_slpc(dev_priv, data, 4);
+}
+
 static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
 {
 	enum slpc_platform_sku platform_sku;
@@ -131,4 +157,7 @@ void intel_slpc_disable(struct drm_i915_private *dev_priv)
 
 void intel_slpc_enable(struct drm_i915_private *dev_priv)
 {
+	host2guc_slpc_reset(dev_priv);
+	DRM_INFO("SLPC Enabled\n");
+	dev_priv->guc.slpc.enabled = true;
 }
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 6cdbc96..a96f365 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -24,6 +24,20 @@
 #ifndef _INTEL_SLPC_H_
 #define _INTEL_SLPC_H_
 
+enum slpc_event_id {
+	SLPC_EVENT_RESET = 0,
+	SLPC_EVENT_SHUTDOWN = 1,
+	SLPC_EVENT_PLATFORM_INFO_CHANGE = 2,
+	SLPC_EVENT_DISPLAY_MODE_CHANGE = 3,
+	SLPC_EVENT_FLIP_COMPLETE = 4,
+	SLPC_EVENT_QUERY_TASK_STATE = 5,
+	SLPC_EVENT_PARAMETER_SET = 6,
+	SLPC_EVENT_PARAMETER_UNSET = 7,
+};
+
+#define SLPC_EVENT(id, argc) ((u32) (id) << 8 | (argc))
+#define SLPC_EVENT_STATUS_MASK	0xFF
+
 enum slpc_global_state {
 	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
 	SLPC_GLOBAL_STATE_INITIALIZING = 1,
-- 
1.9.1

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[PATCH v4 13/26] drm/i915/slpc: Send shutdown event

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Send SLPC shutdown event during disable, suspend, and reset
operations. Sending shutdown event while already shutdown
is OK.

v1: Return void instead of ignored error code (Paulo)
    Removed WARN_ON for checking msb of gtt address of
    shared gem obj. (ChrisW)
    Added SLPC state update during disable, suspend and reset.
    Changed semantics of reset. It is supposed to just disable. (Sagar)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c   |  6 ++++--
 drivers/gpu/drm/i915/intel_slpc.c | 17 +++++++++++++++++
 2 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2211f7b..70e08d9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6691,7 +6691,7 @@ void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
 {
 	if (intel_slpc_enabled()) {
-		/* TODO: Set SLPC enabled forcefully */
+		dev_priv->guc.slpc.enabled = true;
 		intel_disable_gt_powersave(dev_priv);
 	} else {
 		dev_priv->rps.enabled = true; /* force disabling */
@@ -6704,8 +6704,10 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
 {
 	if (intel_slpc_enabled()) {
-		if (!intel_slpc_active(dev_priv))
+		if (!intel_slpc_active(dev_priv)) {
+			dev_priv->guc.slpc.enabled = false;
 			return;
+		}
 	} else if (!READ_ONCE(dev_priv->rps.enabled))
 		return;
 
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 3b99231..2aa2ba4 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -52,6 +52,19 @@ static void host2guc_slpc_reset(struct drm_i915_private *dev_priv)
 	host2guc_slpc(dev_priv, data, 4);
 }
 
+static void host2guc_slpc_shutdown(struct drm_i915_private *dev_priv)
+{
+	u32 data[4];
+	u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_SHUTDOWN, 2);
+	data[2] = shared_data_gtt_offset;
+	data[3] = 0;
+
+	host2guc_slpc(dev_priv, data, 4);
+}
+
 static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
 {
 	enum slpc_platform_sku platform_sku;
@@ -149,10 +162,14 @@ void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
 
 void intel_slpc_suspend(struct drm_i915_private *dev_priv)
 {
+	host2guc_slpc_shutdown(dev_priv);
+	dev_priv->guc.slpc.enabled = false;
 }
 
 void intel_slpc_disable(struct drm_i915_private *dev_priv)
 {
+	host2guc_slpc_shutdown(dev_priv);
+	dev_priv->guc.slpc.enabled = false;
 }
 
 void intel_slpc_enable(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[PATCH v4 14/26] drm/i915/slpc: Add slpc_status enum values

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

v1: fix whitespace (Sagar)

v2-v3: Rebase.

v4: Updated with GuC firmware v9.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.h | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index a96f365..4838e1e 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -24,6 +24,32 @@
 #ifndef _INTEL_SLPC_H_
 #define _INTEL_SLPC_H_
 
+enum slpc_status {
+	SLPC_STATUS_OK = 0,
+	SLPC_STATUS_ERROR = 1,
+	SLPC_STATUS_ILLEGAL_COMMAND = 2,
+	SLPC_STATUS_INVALID_ARGS = 3,
+	SLPC_STATUS_INVALID_PARAMS = 4,
+	SLPC_STATUS_INVALID_DATA = 5,
+	SLPC_STATUS_OUT_OF_RANGE = 6,
+	SLPC_STATUS_NOT_SUPPORTED = 7,
+	SLPC_STATUS_NOT_IMPLEMENTED = 8,
+	SLPC_STATUS_NO_DATA = 9,
+	SLPC_STATUS_EVENT_NOT_REGISTERED = 10,
+	SLPC_STATUS_REGISTER_LOCKED = 11,
+	SLPC_STATUS_TEMPORARILY_UNAVAILABLE = 12,
+	SLPC_STATUS_VALUE_ALREADY_SET = 13,
+	SLPC_STATUS_VALUE_ALREADY_UNSET = 14,
+	SLPC_STATUS_VALUE_NOT_CHANGED = 15,
+	SLPC_STATUS_MEMIO_ERROR = 16,
+	SLPC_STATUS_EVENT_QUEUED_REQ_DPC = 17,
+	SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC = 18,
+	SLPC_STATUS_NO_EVENT_QUEUED = 19,
+	SLPC_STATUS_OUT_OF_SPACE = 20,
+	SLPC_STATUS_TIMEOUT = 21,
+	SLPC_STATUS_NO_LOCK = 22,
+};
+
 enum slpc_event_id {
 	SLPC_EVENT_RESET = 0,
 	SLPC_EVENT_SHUTDOWN = 1,
-- 
1.9.1

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[PATCH v4 15/26] drm/i915/slpc: Add parameter unset/set/get functions

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Add slpc_param_id enum values.
Add events for setting/unsetting parameters.

v1: Use host2guc_slpc
    update slcp_param_id enum values for SLPC 2015.2.4
    return void instead of ignored error code (Paulo)

v2: Checkpatch update.

v3: Rebase.

v4: Updated with GuC firmware v9.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 102 ++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h |  32 +++++++++++-
 2 files changed, 133 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 2aa2ba4..84b0423 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -65,6 +65,108 @@ static void host2guc_slpc_shutdown(struct drm_i915_private *dev_priv)
 	host2guc_slpc(dev_priv, data, 4);
 }
 
+static void host2guc_slpc_set_param(struct drm_i915_private *dev_priv,
+				    enum slpc_param_id id, u32 value)
+{
+	u32 data[4];
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2);
+	data[2] = (u32) id;
+	data[3] = value;
+
+	host2guc_slpc(dev_priv, data, 4);
+}
+
+static void host2guc_slpc_unset_param(struct drm_i915_private *dev_priv,
+				      enum slpc_param_id id)
+{
+	u32 data[3];
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1);
+	data[2] = (u32) id;
+
+	host2guc_slpc(dev_priv, data, 3);
+}
+
+void intel_slpc_unset_param(struct drm_i915_private *dev_priv,
+			    enum slpc_param_id id)
+{
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	struct slpc_shared_data *data = NULL;
+
+	obj = dev_priv->guc.slpc.vma->obj;
+	if (obj) {
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			data = kmap_atomic(page);
+	}
+
+	if (data) {
+		data->override_parameters_set_bits[id >> 5]
+							&= (~(1 << (id % 32)));
+		data->override_parameters_values[id] = 0;
+		kunmap_atomic(data);
+
+		host2guc_slpc_unset_param(dev_priv, id);
+	}
+}
+
+void intel_slpc_set_param(struct drm_i915_private *dev_priv,
+			  enum slpc_param_id id,
+			  u32 value)
+{
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	struct slpc_shared_data *data = NULL;
+
+	obj = dev_priv->guc.slpc.vma->obj;
+	if (obj) {
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			data = kmap_atomic(page);
+	}
+
+	if (data) {
+		data->override_parameters_set_bits[id >> 5]
+							|= (1 << (id % 32));
+		data->override_parameters_values[id] = value;
+		kunmap_atomic(data);
+
+		host2guc_slpc_set_param(dev_priv, id, value);
+	}
+}
+
+void intel_slpc_get_param(struct drm_i915_private *dev_priv,
+			  enum slpc_param_id id,
+			  int *overriding, u32 *value)
+{
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	struct slpc_shared_data *data = NULL;
+	u32 bits;
+
+	obj = dev_priv->guc.slpc.vma->obj;
+	if (obj) {
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			data = kmap_atomic(page);
+	}
+
+	if (data) {
+		if (overriding) {
+			bits = data->override_parameters_set_bits[id >> 5];
+			*overriding = (0 != (bits & (1 << (id % 32))));
+		}
+		if (value)
+			*value = data->override_parameters_values[id];
+
+		kunmap_atomic(data);
+	}
+}
+
 static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
 {
 	enum slpc_platform_sku platform_sku;
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 4838e1e..b0a627d 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -64,6 +64,29 @@ enum slpc_event_id {
 #define SLPC_EVENT(id, argc) ((u32) (id) << 8 | (argc))
 #define SLPC_EVENT_STATUS_MASK	0xFF
 
+enum slpc_param_id {
+	SLPC_PARAM_TASK_ENABLE_GTPERF = 0,
+	SLPC_PARAM_TASK_DISABLE_GTPERF = 1,
+	SLPC_PARAM_TASK_ENABLE_BALANCER = 2,
+	SLPC_PARAM_TASK_DISABLE_BALANCER = 3,
+	SLPC_PARAM_TASK_ENABLE_DCC = 4,
+	SLPC_PARAM_TASK_DISABLE_DCC = 5,
+	SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ = 6,
+	SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,
+	SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,
+	SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9,
+	SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS = 10,
+	SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11,
+	SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING = 12,
+	SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13,
+	SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14,
+	SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15,
+	SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING = 16,
+	SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO = 17,
+	SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE = 18,
+	SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE = 19,
+};
+
 enum slpc_global_state {
 	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
 	SLPC_GLOBAL_STATE_INITIALIZING = 1,
@@ -169,5 +192,12 @@ void intel_slpc_cleanup(struct drm_i915_private *dev_priv);
 void intel_slpc_suspend(struct drm_i915_private *dev_priv);
 void intel_slpc_disable(struct drm_i915_private *dev_priv);
 void intel_slpc_enable(struct drm_i915_private *dev_priv);
-
+void intel_slpc_unset_param(struct drm_i915_private *dev_priv,
+			    enum slpc_param_id id);
+void intel_slpc_set_param(struct drm_i915_private *dev_priv,
+			  enum slpc_param_id id,
+			  u32 value);
+void intel_slpc_get_param(struct drm_i915_private *dev_priv,
+			  enum slpc_param_id id,
+			  int *overriding, u32 *value);
 #endif
-- 
1.9.1

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[PATCH v4 16/26] drm/i915/slpc: Add slpc support for max/min freq

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Update sysfs and debugfs functions to set SLPC
parameters when setting max/min frequency.

v1: Update for SLPC 2015.2.4 (params for both slice and unslice)
    Replace HAS_SLPC with intel_slpc_active() (Paulo)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 18 ++++++++++++++++++
 drivers/gpu/drm/i915/i915_sysfs.c   | 18 ++++++++++++++++++
 2 files changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 71bce32..0956d1f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4873,6 +4873,15 @@ i915_max_freq_set(void *data, u64 val)
 
 	dev_priv->rps.max_freq_softlimit = val;
 
+	if (intel_slpc_active(dev_priv)) {
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+	}
+
 	intel_set_rps(dev_priv, val);
 
 	mutex_unlock(&dev_priv->rps.hw_lock);
@@ -4928,6 +4937,15 @@ i915_min_freq_set(void *data, u64 val)
 
 	dev_priv->rps.min_freq_softlimit = val;
 
+	if (intel_slpc_active(dev_priv)) {
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+	}
+
 	intel_set_rps(dev_priv, val);
 
 	mutex_unlock(&dev_priv->rps.hw_lock);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 020d64e..ab161ca 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -391,6 +391,15 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
 
 	dev_priv->rps.max_freq_softlimit = val;
 
+	if (intel_slpc_active(dev_priv)) {
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+	}
+
 	val = clamp_t(int, dev_priv->rps.cur_freq,
 		      dev_priv->rps.min_freq_softlimit,
 		      dev_priv->rps.max_freq_softlimit);
@@ -444,6 +453,15 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
 
 	dev_priv->rps.min_freq_softlimit = val;
 
+	if (intel_slpc_active(dev_priv)) {
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+	}
+
 	val = clamp_t(int, dev_priv->rps.cur_freq,
 		      dev_priv->rps.min_freq_softlimit,
 		      dev_priv->rps.max_freq_softlimit);
-- 
1.9.1

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[PATCH v4 17/26] drm/i915/slpc: Add enable/disable debugfs for slpc

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Adds debugfs hooks for each slpc task.

The enable/disable debugfs files are
i915_slpc_gtperf, i915_slpc_balancer, and i915_slpc_dcc.

Each of these can take the values:
"default", "enabled", or "disabled"

v1: update for SLPC v2015.2.4
    dfps and turbo merged and renamed "gtperf"
    ibc split out and renamed "balancer"
    Avoid magic numbers (Jon Bloomfield)

v2-v3: Rebase.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 252 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h   |   5 +
 2 files changed, 257 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 0956d1f..4fde685 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1075,6 +1075,255 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
 			i915_next_seqno_get, i915_next_seqno_set,
 			"0x%llx\n");
 
+static int slpc_enable_disable_get(struct drm_device *dev, u64 *val,
+				   enum slpc_param_id enable_id,
+				   enum slpc_param_id disable_id)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int override_enable, override_disable;
+	u32 value_enable, value_disable;
+	int ret = 0;
+
+	if (!intel_slpc_active(dev_priv)) {
+		ret = -ENODEV;
+	} else if (val) {
+		intel_slpc_get_param(dev_priv, enable_id, &override_enable,
+				     &value_enable);
+		intel_slpc_get_param(dev_priv, disable_id, &override_disable,
+				     &value_disable);
+
+		/* set the output value:
+		* 0: default
+		* 1: enabled
+		* 2: disabled
+		* 3: unknown (should not happen)
+		*/
+		if (override_disable && (value_disable == 1))
+			*val = SLPC_PARAM_TASK_DISABLED;
+		else if (override_enable && (value_enable == 1))
+			*val = SLPC_PARAM_TASK_ENABLED;
+		else if (!override_enable && !override_disable)
+			*val = SLPC_PARAM_TASK_DEFAULT;
+		else
+			*val = SLPC_PARAM_TASK_UNKNOWN;
+
+	} else {
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static int slpc_enable_disable_set(struct drm_device *dev, u64 val,
+				   enum slpc_param_id enable_id,
+				   enum slpc_param_id disable_id)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int ret = 0;
+
+	if (!intel_slpc_active(dev_priv)) {
+		ret = -ENODEV;
+	} else if (val == SLPC_PARAM_TASK_DEFAULT) {
+		/* set default */
+		intel_slpc_unset_param(dev_priv, enable_id);
+		intel_slpc_unset_param(dev_priv, disable_id);
+	} else if (val == SLPC_PARAM_TASK_ENABLED) {
+		/* set enable */
+		intel_slpc_set_param(dev_priv, enable_id, 1);
+		intel_slpc_unset_param(dev_priv, disable_id);
+	} else if (val == SLPC_PARAM_TASK_DISABLED) {
+		/* set disable */
+		intel_slpc_set_param(dev_priv, disable_id, 1);
+		intel_slpc_unset_param(dev_priv, enable_id);
+	} else {
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static void slpc_param_show(struct seq_file *m, enum slpc_param_id enable_id,
+			    enum slpc_param_id disable_id)
+{
+	struct drm_device *dev = m->private;
+	const char *status;
+	u64 val;
+	int ret;
+
+	ret = slpc_enable_disable_get(dev, &val, enable_id, disable_id);
+
+	if (ret) {
+		seq_printf(m, "error %d\n", ret);
+	} else {
+		switch (val) {
+		case SLPC_PARAM_TASK_DEFAULT:
+			status = "default\n";
+			break;
+
+		case SLPC_PARAM_TASK_ENABLED:
+			status = "enabled\n";
+			break;
+
+		case SLPC_PARAM_TASK_DISABLED:
+			status = "disabled\n";
+			break;
+
+		default:
+			status = "unknown\n";
+			break;
+		}
+
+		seq_puts(m, status);
+	}
+}
+
+static int slpc_param_write(struct seq_file *m, const char __user *ubuf,
+			    size_t len, enum slpc_param_id enable_id,
+			    enum slpc_param_id disable_id)
+{
+	struct drm_device *dev = m->private;
+	u64 val;
+	int ret = 0;
+	char buf[10];
+
+	if (len >= sizeof(buf))
+		ret = -EINVAL;
+	else if (copy_from_user(buf, ubuf, len))
+		ret = -EFAULT;
+	else
+		buf[len] = '\0';
+
+	if (!ret) {
+		if (!strncmp(buf, "default", 7))
+			val = SLPC_PARAM_TASK_DEFAULT;
+		else if (!strncmp(buf, "enabled", 7))
+			val = SLPC_PARAM_TASK_ENABLED;
+		else if (!strncmp(buf, "disabled", 8))
+			val = SLPC_PARAM_TASK_DISABLED;
+		else
+			ret = -EINVAL;
+	}
+
+	if (!ret)
+		ret = slpc_enable_disable_set(dev, val, enable_id, disable_id);
+
+	return ret;
+}
+
+static int slpc_gtperf_show(struct seq_file *m, void *data)
+{
+	slpc_param_show(m, SLPC_PARAM_TASK_ENABLE_GTPERF,
+			SLPC_PARAM_TASK_DISABLE_GTPERF);
+
+	return 0;
+}
+
+static int slpc_gtperf_open(struct inode *inode, struct file *file)
+{
+	struct drm_connector *dev = inode->i_private;
+
+	return single_open(file, slpc_gtperf_show, dev);
+}
+
+static ssize_t slpc_gtperf_write(struct file *file, const char __user *ubuf,
+			      size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret = 0;
+
+	ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_GTPERF,
+			       SLPC_PARAM_TASK_DISABLE_GTPERF);
+	if (ret)
+		return (size_t) ret;
+
+	return len;
+}
+
+static const struct file_operations i915_slpc_gtperf_fops = {
+	.owner	 = THIS_MODULE,
+	.open	 = slpc_gtperf_open,
+	.release = single_release,
+	.read	 = seq_read,
+	.write	 = slpc_gtperf_write,
+	.llseek	 = seq_lseek
+};
+
+static int slpc_balancer_show(struct seq_file *m, void *data)
+{
+	slpc_param_show(m, SLPC_PARAM_TASK_ENABLE_BALANCER,
+			SLPC_PARAM_TASK_DISABLE_BALANCER);
+
+	return 0;
+}
+
+static int slpc_balancer_open(struct inode *inode, struct file *file)
+{
+	struct drm_connector *dev = inode->i_private;
+
+	return single_open(file, slpc_balancer_show, dev);
+}
+
+static ssize_t slpc_balancer_write(struct file *file, const char __user *ubuf,
+			      size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret = 0;
+
+	ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_BALANCER,
+			       SLPC_PARAM_TASK_DISABLE_BALANCER);
+	if (ret)
+		return (size_t) ret;
+
+	return len;
+}
+
+static const struct file_operations i915_slpc_balancer_fops = {
+	.owner	 = THIS_MODULE,
+	.open	 = slpc_balancer_open,
+	.release = single_release,
+	.read	 = seq_read,
+	.write	 = slpc_balancer_write,
+	.llseek	 = seq_lseek
+};
+
+static int slpc_dcc_show(struct seq_file *m, void *data)
+{
+	slpc_param_show(m, SLPC_PARAM_TASK_ENABLE_DCC,
+			SLPC_PARAM_TASK_DISABLE_DCC);
+
+	return 0;
+}
+
+static int slpc_dcc_open(struct inode *inode, struct file *file)
+{
+	struct drm_connector *dev = inode->i_private;
+
+	return single_open(file, slpc_dcc_show, dev);
+}
+
+static ssize_t slpc_dcc_write(struct file *file, const char __user *ubuf,
+			      size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret = 0;
+
+	ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_DCC,
+			       SLPC_PARAM_TASK_DISABLE_DCC);
+	if (ret)
+		return (size_t) ret;
+
+	return len;
+}
+
+static const struct file_operations i915_slpc_dcc_fops = {
+	.owner	 = THIS_MODULE,
+	.open	 = slpc_dcc_open,
+	.release = single_release,
+	.read	 = seq_read,
+	.write	 = slpc_dcc_write,
+	.llseek	 = seq_lseek
+};
+
 static int i915_frequency_info(struct seq_file *m, void *unused)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -5319,6 +5568,9 @@ static const struct i915_debugfs_files {
 	const struct file_operations *fops;
 } i915_debugfs_files[] = {
 	{"i915_wedged", &i915_wedged_fops},
+	{"i915_slpc_gtperf", &i915_slpc_gtperf_fops},
+	{"i915_slpc_balancer", &i915_slpc_balancer_fops},
+	{"i915_slpc_dcc", &i915_slpc_dcc_fops},
 	{"i915_max_freq", &i915_max_freq_fops},
 	{"i915_min_freq", &i915_min_freq_fops},
 	{"i915_cache_sharing", &i915_cache_sharing_fops},
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index b0a627d..3a134e2 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -87,6 +87,11 @@ enum slpc_param_id {
 	SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE = 19,
 };
 
+#define SLPC_PARAM_TASK_DEFAULT 0
+#define SLPC_PARAM_TASK_ENABLED 1
+#define SLPC_PARAM_TASK_DISABLED 2
+#define SLPC_PARAM_TASK_UNKNOWN 3
+
 enum slpc_global_state {
 	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
 	SLPC_GLOBAL_STATE_INITIALIZING = 1,
-- 
1.9.1

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[PATCH v4 18/26] drm/i915/slpc: Add i915_slpc_info to debugfs

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

i915_slpc_info shows the contents of SLPC shared data
parsed into text format.

v1: Reformat slpc info (Radek)
    squashed query task state info
    in slpc info, kunmap before seq_print (Paulo)
    return void instead of ignored return value (Paulo)
    Avoid magic numbers and use local variables (Jon Bloomfield)
    Removed WARN_ON for checking msb of gtt address of
    shared gem obj. (ChrisW)
    Moved definition of power plan and power source to earlier
    patch in the series.
    drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
    (Akash)

v2-v3: Rebase.

v4: Updated with GuC firmware v9.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 197 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.c   |  19 ++++
 drivers/gpu/drm/i915/intel_slpc.h   |   1 +
 3 files changed, 217 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 4fde685..8e1e83b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1324,6 +1324,202 @@ static const struct file_operations i915_slpc_dcc_fops = {
 	.llseek	 = seq_lseek
 };
 
+static int i915_slpc_info(struct seq_file *m, void *unused)
+{
+	struct drm_info_node *node = m->private;
+	struct drm_device *dev = node->minor->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	void *pv = NULL;
+	struct slpc_shared_data data;
+	struct slpc_task_state_data *task_data;
+	int i, value;
+	enum slpc_global_state global_state;
+	enum slpc_platform_sku platform_sku;
+	enum slpc_power_plan power_plan;
+	enum slpc_power_source power_source;
+
+	if (!intel_slpc_active(dev_priv))
+		return -ENODEV;
+
+	obj = dev_priv->guc.slpc.vma->obj;
+	if (obj) {
+		intel_slpc_query_task_state(dev_priv);
+
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			pv = kmap_atomic(page);
+	}
+
+	if (pv) {
+		data = *(struct slpc_shared_data *) pv;
+		kunmap_atomic(pv);
+
+		seq_printf(m, "shared data size: %d\n", data.shared_data_size);
+
+		global_state = (enum slpc_global_state) data.global_state;
+		seq_printf(m, "global state: %d (", global_state);
+		switch (global_state) {
+		case SLPC_GLOBAL_STATE_NOT_RUNNING:
+			seq_puts(m, "not running)\n");
+			break;
+		case SLPC_GLOBAL_STATE_INITIALIZING:
+			seq_puts(m, "initializing)\n");
+			break;
+		case SLPC_GLOBAL_STATE_RESETTING:
+			seq_puts(m, "resetting)\n");
+			break;
+		case SLPC_GLOBAL_STATE_RUNNING:
+			seq_puts(m, "running)\n");
+			break;
+		case SLPC_GLOBAL_STATE_SHUTTING_DOWN:
+			seq_puts(m, "shutting down)\n");
+			break;
+		case SLPC_GLOBAL_STATE_ERROR:
+			seq_puts(m, "error)\n");
+			break;
+		default:
+			seq_puts(m, "unknown)\n");
+			break;
+		}
+
+		platform_sku = (enum slpc_platform_sku)
+				data.platform_info.platform_sku;
+		seq_printf(m, "sku: %d (", platform_sku);
+		switch (platform_sku) {
+		case SLPC_PLATFORM_SKU_UNDEFINED:
+			seq_puts(m, "undefined)\n");
+			break;
+		case SLPC_PLATFORM_SKU_ULX:
+			seq_puts(m, "ULX)\n");
+			break;
+		case SLPC_PLATFORM_SKU_ULT:
+			seq_puts(m, "ULT)\n");
+			break;
+		case SLPC_PLATFORM_SKU_T:
+			seq_puts(m, "T)\n");
+			break;
+		case SLPC_PLATFORM_SKU_MOBL:
+			seq_puts(m, "Mobile)\n");
+			break;
+		case SLPC_PLATFORM_SKU_DT:
+			seq_puts(m, "DT)\n");
+			break;
+		case SLPC_PLATFORM_SKU_UNKNOWN:
+		default:
+			seq_puts(m, "unknown)\n");
+			break;
+		}
+		seq_printf(m, "slice count: %d\n",
+			   data.platform_info.slice_count);
+
+		seq_printf(m, "power plan/source: 0x%x\n\tplan:\t",
+			   data.platform_info.power_plan_source);
+		power_plan = (enum slpc_power_plan) SLPC_POWER_PLAN(
+					data.platform_info.power_plan_source);
+		power_source = (enum slpc_power_source) SLPC_POWER_SOURCE(
+					data.platform_info.power_plan_source);
+		switch (power_plan) {
+		case SLPC_POWER_PLAN_UNDEFINED:
+			seq_puts(m, "undefined");
+			break;
+		case SLPC_POWER_PLAN_BATTERY_SAVER:
+			seq_puts(m, "battery saver");
+			break;
+		case SLPC_POWER_PLAN_BALANCED:
+			seq_puts(m, "balanced");
+			break;
+		case SLPC_POWER_PLAN_PERFORMANCE:
+			seq_puts(m, "performance");
+			break;
+		case SLPC_POWER_PLAN_UNKNOWN:
+		default:
+			seq_puts(m, "unknown");
+			break;
+		}
+		seq_puts(m, "\n\tsource:\t");
+		switch (power_source) {
+		case SLPC_POWER_SOURCE_UNDEFINED:
+			seq_puts(m, "undefined\n");
+			break;
+		case SLPC_POWER_SOURCE_AC:
+			seq_puts(m, "AC\n");
+			break;
+		case SLPC_POWER_SOURCE_DC:
+			seq_puts(m, "DC\n");
+			break;
+		case SLPC_POWER_SOURCE_UNKNOWN:
+		default:
+			seq_puts(m, "unknown\n");
+			break;
+		}
+
+		seq_printf(m, "IA frequency (MHz):\n\tP0: %d\n\tP1: %d\n\tPe: %d\n\tPn: %d\n",
+			   data.platform_info.P0_freq * 50,
+			   data.platform_info.P1_freq * 50,
+			   data.platform_info.Pe_freq * 50,
+			   data.platform_info.Pn_freq * 50);
+
+		task_data = &data.task_state_data;
+		seq_printf(m, "task state data: 0x%08x 0x%08x\n",
+			   task_data->bitfield1, task_data->bitfield2);
+
+		seq_printf(m, "\tgtperf task active: %s\n",
+			   yesno(task_data->gtperf_task_active));
+		seq_printf(m, "\tgtperf stall possible: %s\n",
+			   yesno(task_data->gtperf_stall_possible));
+		seq_printf(m, "\tgtperf gaming mode: %s\n",
+			   yesno(task_data->gtperf_gaming_mode));
+		seq_printf(m, "\tgtperf target fps: %d\n",
+			   task_data->gtperf_target_fps);
+
+		seq_printf(m, "\tdcc task active: %s\n",
+			   yesno(task_data->dcc_task_active));
+		seq_printf(m, "\tin dcc: %s\n",
+			   yesno(task_data->in_dcc));
+		seq_printf(m, "\tin dct: %s\n",
+			   yesno(task_data->in_dct));
+		seq_printf(m, "\tfreq switch active: %d\n",
+			   task_data->freq_switch_active);
+
+		seq_printf(m, "\tibc enabled: %s\n",
+			   yesno(task_data->ibc_enabled));
+		seq_printf(m, "\tibc active: %s\n",
+			   yesno(task_data->ibc_active));
+		seq_printf(m, "\tpg1 enabled: %s\n",
+			   yesno(task_data->pg1_enabled));
+		seq_printf(m, "\tpg1 active: %s\n",
+			   yesno(task_data->pg1_active));
+
+		seq_printf(m, "\tunslice max freq: %d\n",
+			   task_data->freq_unslice_max);
+		seq_printf(m, "\tunslice min freq: %d\n",
+			   task_data->freq_unslice_min);
+		seq_printf(m, "\tslice max freq: %d\n",
+			   task_data->freq_slice_max);
+		seq_printf(m, "\tslice min freq: %d\n",
+			   task_data->freq_slice_min);
+
+		seq_puts(m, "override parameter bitfield\n");
+		for (i = 0; i < SLPC_OVERRIDE_BITFIELD_SIZE; i++)
+			seq_printf(m, "%d: 0x%08x\n", i,
+				   data.override_parameters_set_bits[i]);
+
+		seq_puts(m, "override parameters (only non-zero shown)\n");
+		for (i = 0; i < SLPC_MAX_OVERRIDE_PARAMETERS; i++) {
+			value = data.override_parameters_values[i];
+			if (value)
+				seq_printf(m, "%d: 0x%8x\n", i, value);
+		}
+
+	} else {
+		seq_puts(m, "no SLPC info available\n");
+	}
+
+	return 0;
+}
+
 static int i915_frequency_info(struct seq_file *m, void *unused)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -5526,6 +5722,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
 	{"i915_guc_info", i915_guc_info, 0},
 	{"i915_guc_load_status", i915_guc_load_status_info, 0},
 	{"i915_guc_log_dump", i915_guc_log_dump, 0},
+	{"i915_slpc_info", i915_slpc_info, 0},
 	{"i915_frequency_info", i915_frequency_info, 0},
 	{"i915_hangcheck_info", i915_hangcheck_info, 0},
 	{"i915_drpc_info", i915_drpc_info, 0},
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 84b0423..392a048 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -167,6 +167,25 @@ void intel_slpc_get_param(struct drm_i915_private *dev_priv,
 	}
 }
 
+static void host2guc_slpc_query_task_state(struct drm_i915_private *dev_priv)
+{
+	u32 data[4];
+	u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2);
+	data[2] = shared_data_gtt_offset;
+	data[3] = 0;
+
+	host2guc_slpc(dev_priv, data, 4);
+}
+
+void intel_slpc_query_task_state(struct drm_i915_private *dev_priv)
+{
+	if (intel_slpc_active(dev_priv))
+		host2guc_slpc_query_task_state(dev_priv);
+}
+
 static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
 {
 	enum slpc_platform_sku platform_sku;
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 3a134e2..cc43194 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -205,4 +205,5 @@ void intel_slpc_set_param(struct drm_i915_private *dev_priv,
 void intel_slpc_get_param(struct drm_i915_private *dev_priv,
 			  enum slpc_param_id id,
 			  int *overriding, u32 *value);
+void intel_slpc_query_task_state(struct drm_i915_private *dev_priv);
 #endif
-- 
1.9.1

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[PATCH v4 19/26] drm/i915/slpc: Add Broxton SLPC support

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Adds has_slpc to broxton info and adds broxton firmware version check
to sanitize_slpc_option.

v1: Adjusted slpc version check for major version 8.
    Added message if version mismatch happens for easier debug. (Sagar)

v2-v3: Rebase.

v4: Commit message update.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c         | 1 +
 drivers/gpu/drm/i915/intel_guc_loader.c | 5 ++++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 873565c..7526be0 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -360,6 +360,7 @@ static const struct intel_device_info intel_broxton_info = {
 	.has_hw_contexts = 1,
 	.has_logical_ring_contexts = 1,
 	.has_guc = 1,
+	.has_slpc = 1,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
 	BDW_COLORS,
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 2dda771..f0101a8 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -164,8 +164,11 @@ void sanitize_slpc_option(struct drm_i915_private *dev_priv)
 	if (!i915.enable_guc_submission)
 		i915.enable_slpc = 0;
 
-	if (IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 9))
+	if ((IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 9))
+	     || (IS_BROXTON(dev_priv) && (guc_fw->guc_fw_major_found != 9))) {
+		DRM_INFO("SLPC not supported with current GuC firmware\n");
 		i915.enable_slpc = 0;
+	}
 }
 
 static u32 get_gttype(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[PATCH v4 20/26] drm/i915/slpc: Only Enable GTPERF, Disable DCC, Balancer, IBC, FPS Stall

[Sagar Arun Kamble]

v1: Updated tasks and frequency post reset.
    Added DFPS param update for MAX_FPS and FPS Stall.

v2-v3: Rebase.

v4: Updated with GuC firmware v9.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c |  2 +-
 drivers/gpu/drm/i915/intel_slpc.c   | 41 +++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h   |  5 +++++
 3 files changed, 47 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 8e1e83b..46d8e25 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1114,7 +1114,7 @@ static int slpc_enable_disable_get(struct drm_device *dev, u64 *val,
 	return ret;
 }
 
-static int slpc_enable_disable_set(struct drm_device *dev, u64 val,
+int slpc_enable_disable_set(struct drm_device *dev, u64 val,
 				   enum slpc_param_id enable_id,
 				   enum slpc_param_id disable_id)
 {
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 392a048..da775a8 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -295,7 +295,48 @@ void intel_slpc_disable(struct drm_i915_private *dev_priv)
 
 void intel_slpc_enable(struct drm_i915_private *dev_priv)
 {
+	u64 val;
+
 	host2guc_slpc_reset(dev_priv);
 	DRM_INFO("SLPC Enabled\n");
 	dev_priv->guc.slpc.enabled = true;
+
+	/* Enable only GTPERF task, Disable others */
+	val = SLPC_PARAM_TASK_ENABLED;
+	slpc_enable_disable_set(&dev_priv->drm, val,
+				SLPC_PARAM_TASK_ENABLE_GTPERF,
+				SLPC_PARAM_TASK_DISABLE_GTPERF);
+
+	val = SLPC_PARAM_TASK_DISABLED;
+	slpc_enable_disable_set(&dev_priv->drm, val,
+				SLPC_PARAM_TASK_ENABLE_BALANCER,
+				SLPC_PARAM_TASK_DISABLE_BALANCER);
+
+	slpc_enable_disable_set(&dev_priv->drm, val,
+				SLPC_PARAM_TASK_ENABLE_DCC,
+				SLPC_PARAM_TASK_DISABLE_DCC);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING,
+			     0);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS,
+			     0);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING,
+			     0);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO,
+			     0);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE,
+			     0);
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
+			     0);
 }
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index cc43194..8436965 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -206,4 +206,9 @@ void intel_slpc_get_param(struct drm_i915_private *dev_priv,
 			  enum slpc_param_id id,
 			  int *overriding, u32 *value);
 void intel_slpc_query_task_state(struct drm_i915_private *dev_priv);
+
+/* i915_debugfs.c */
+int slpc_enable_disable_set(struct drm_device *dev, u64 val,
+			    enum slpc_param_id enable_id,
+			    enum slpc_param_id disable_id);
 #endif
-- 
1.9.1

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[PATCH v4 21/26] drm/i915/slpc: Update freq min/max softlimits

[Sagar Arun Kamble]

v2: Removing checks for vma obj and kmap_atomic validity. (Chris)

v3: Rebase.

v4: Updated to make sure SLPC enable keeps min/max freq softlimits
    unchanged after initializing once. (Chris)

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 47 +++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h |  1 +
 2 files changed, 48 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index da775a8..4ffa72f 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -269,6 +269,7 @@ void intel_slpc_init(struct drm_i915_private *dev_priv)
 	}
 
 	slpc_shared_data_init(dev_priv);
+	dev_priv->guc.slpc.first_enable = false;
 }
 
 void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
@@ -279,6 +280,8 @@ void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
 	mutex_lock(&dev_priv->drm.struct_mutex);
 	i915_vma_unpin_and_release(&guc->slpc.vma);
 	mutex_unlock(&dev_priv->drm.struct_mutex);
+
+	dev_priv->guc.slpc.first_enable = false;
 }
 
 void intel_slpc_suspend(struct drm_i915_private *dev_priv)
@@ -339,4 +342,48 @@ void intel_slpc_enable(struct drm_i915_private *dev_priv)
 	intel_slpc_set_param(dev_priv,
 			     SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
 			     0);
+
+	if (!dev_priv->guc.slpc.first_enable) {
+		struct drm_i915_gem_object *obj;
+		void *pv = NULL;
+		struct slpc_shared_data data;
+
+		obj = dev_priv->guc.slpc.vma->obj;
+		intel_slpc_query_task_state(dev_priv);
+
+		pv = kmap_atomic(i915_gem_object_get_page(obj, 0));
+		data = *(struct slpc_shared_data *) pv;
+		kunmap_atomic(pv);
+
+		/*
+		 * TODO: Define separate variables for slice and unslice
+		 *	 frequencies for driver state variable.
+		 */
+		dev_priv->rps.max_freq_softlimit =
+				data.task_state_data.freq_unslice_max;
+		dev_priv->rps.min_freq_softlimit =
+				data.task_state_data.freq_unslice_min;
+
+		dev_priv->rps.max_freq_softlimit *= GEN9_FREQ_SCALER;
+		dev_priv->rps.min_freq_softlimit *= GEN9_FREQ_SCALER;
+		dev_priv->guc.slpc.first_enable = true;
+	} else {
+		/* Ask SLPC to operate within min/max freq softlimits */
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv,
+					dev_priv->rps.max_freq_softlimit));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv,
+					dev_priv->rps.max_freq_softlimit));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv,
+					dev_priv->rps.min_freq_softlimit));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv,
+					dev_priv->rps.min_freq_softlimit));
+	}
 }
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 8436965..9a8602a 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -189,6 +189,7 @@ struct slpc_shared_data {
 struct intel_slpc {
 	struct i915_vma *vma;
 	bool enabled;
+	bool first_enable;
 };
 
 /* intel_slpc.c */
-- 
1.9.1

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[PATCH v4 22/26] drm/i915/slpc: Check GuC load status in SLPC active check

[Sagar Arun Kamble]

SLPC status has to be linked with GuC load status to make sure
SLPC actions get invoked when GuC is loaded.

v2: Space and function return convention issues. (Deepak)

v3: Rebase.

v4: Limiting the check for SLPC actions.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 796c52f..f92678c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1707,8 +1707,12 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 
 static inline int intel_slpc_active(struct drm_i915_private *dev_priv)
 {
+	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 	int ret = 0;
 
+	if (guc_fw->guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+		return ret;
+
 	if (dev_priv->guc.slpc.vma && dev_priv->guc.slpc.enabled)
 		ret = 1;
 
-- 
1.9.1

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[PATCH v4 23/26] drm/i915/slpc: Keep RP SW Mode enabled while disabling rps

[Sagar Arun Kamble]

With SLPC, only RP SW Mode control should be left enabled by i915.
Else, SLPC requests through through RPNSWREQ will not be granted.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 70e08d9..d06c9bb 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5064,7 +5064,13 @@ static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
 
 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
 {
-	I915_WRITE(GEN6_RP_CONTROL, 0);
+	uint32_t rp_ctl = 0;
+
+	/* RP SW Mode Control will be needed for SLPC, Hence not clearing.*/
+	if (i915.enable_slpc)
+		rp_ctl = I915_READ(GEN6_RP_CONTROL) & GEN6_RP_MEDIA_MODE_MASK;
+
+	I915_WRITE(GEN6_RP_CONTROL, rp_ctl);
 
 	dev_priv->rps.enabled = false;
 }
-- 
1.9.1

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[PATCH v4 24/26] drm/i915/slpc: Enable SLPC, where supported

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

This patch makes SLPC enabled by default on
platforms with hardware/firmware support.

v1: Removing warning "enable_slpc < 0" as it is
set to -1 with this patch now. This was caught by CI BAT.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_params.c | 4 ++--
 drivers/gpu/drm/i915/intel_guc.h   | 1 -
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 72b3097..7b3b3fd 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -36,7 +36,7 @@ struct i915_params i915 __read_mostly = {
 	.enable_dc = -1,
 	.enable_fbc = -1,
 	.enable_execlists = -1,
-	.enable_slpc = 0,
+	.enable_slpc = -1,
 	.enable_hangcheck = true,
 	.enable_ppgtt = -1,
 	.enable_psr = -1,
@@ -135,7 +135,7 @@ MODULE_PARM_DESC(enable_execlists,
 module_param_named_unsafe(enable_slpc, i915.enable_slpc, int, 0400);
 MODULE_PARM_DESC(enable_slpc,
 	"Override single-loop-power-controller (slpc) usage. "
-	"(-1=auto, 0=disabled [default], 1=enabled)");
+	"(-1=auto [default], 0=disabled, 1=enabled)");
 
 module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600);
 MODULE_PARM_DESC(enable_psr, "Enable PSR "
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 6e24e60..e9e1163 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -151,7 +151,6 @@ struct intel_guc {
 
 static inline int intel_slpc_enabled(void)
 {
-	WARN_ON(i915.enable_slpc < 0);
 	return i915.enable_slpc;
 }
 
-- 
1.9.1

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[PATCH v4 25/26] drm/i915: Add sysfs interface to know the HW requested frequency

[Sagar Arun Kamble]

With SLPC, user can read this value to know SLPC requested frequency.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_sysfs.c | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index ab161ca..7bff742 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -307,6 +307,32 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
 				       dev_priv->rps.cur_freq));
 }
 
+static ssize_t gt_req_freq_mhz_show(struct device *kdev,
+				    struct device_attribute *attr, char *buf)
+{
+	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
+	u32 reqf;
+
+	if (!intel_runtime_pm_get_if_in_use(dev_priv))
+		return -ENODEV;
+
+	reqf = I915_READ(GEN6_RPNSWREQ);
+	intel_runtime_pm_put(dev_priv);
+
+	if (IS_GEN9(dev_priv))
+		reqf >>= 23;
+	else {
+		reqf &= ~GEN6_TURBO_DISABLE;
+		if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+			reqf >>= 24;
+		else
+			reqf >>= 25;
+	}
+	reqf = intel_gpu_freq(dev_priv, reqf);
+
+	return snprintf(buf, PAGE_SIZE, "%d\n", reqf);
+}
+
 static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
 {
 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
@@ -481,6 +507,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
 
 static DEVICE_ATTR(gt_act_freq_mhz, S_IRUGO, gt_act_freq_mhz_show, NULL);
 static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
+static DEVICE_ATTR(gt_req_freq_mhz, S_IRUGO, gt_req_freq_mhz_show, NULL);
 static DEVICE_ATTR(gt_boost_freq_mhz, S_IRUGO, gt_boost_freq_mhz_show, gt_boost_freq_mhz_store);
 static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
 static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);
@@ -513,6 +540,7 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr
 static const struct attribute *gen6_attrs[] = {
 	&dev_attr_gt_act_freq_mhz.attr,
 	&dev_attr_gt_cur_freq_mhz.attr,
+	&dev_attr_gt_req_freq_mhz.attr,
 	&dev_attr_gt_boost_freq_mhz.attr,
 	&dev_attr_gt_max_freq_mhz.attr,
 	&dev_attr_gt_min_freq_mhz.attr,
-- 
1.9.1

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[PATCH v4 26/26] drm/i915: Mark GuC load status as PENDING in i915_drm_resume_early

[Sagar Arun Kamble]

This will help avoid Host to GuC actions being called till GuC gets
loaded during i915_drm_resume.

v2-v3: Rebase.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1f677a9..aeb97ac 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1627,6 +1627,7 @@ static int i915_drm_resume(struct drm_device *dev)
 static int i915_drm_resume_early(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 	struct pci_dev *pdev = dev_priv->drm.pdev;
 	int ret;
 
@@ -1684,6 +1685,12 @@ static int i915_drm_resume_early(struct drm_device *dev)
 		DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
 			  ret);
 
+	/*
+	 * Mark GuC FW load status as PENDING to avoid any Host to GuC actions
+	 * invoked till GuC gets loaded in i915_drm_resume.
+	*/
+	guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
+
 	intel_uncore_early_sanitize(dev_priv, true);
 
 	if (IS_BROXTON(dev_priv)) {
-- 
1.9.1

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✓ Fi.CI.BAT: success for Add support for GuC-based SLPC (rev5)

[Patchwork]

== Series Details ==

Series: Add support for GuC-based SLPC (rev5)
URL   : https://patchwork.freedesktop.org/series/2691/
State : success

== Summary ==

Series 2691v5 Add support for GuC-based SLPC
http://patchwork.freedesktop.org/api/1.0/series/2691/revisions/5/mbox/

Test drv_module_reload_basic:
                skip       -> PASS       (fi-skl-6260u)
Test kms_cursor_legacy:
        Subgroup basic-cursor-vs-flip-varying-size:
                fail       -> PASS       (fi-ilk-650)

fi-bdw-5557u     total:254  pass:238  dwarn:0   dfail:0   fail:1   skip:15 
fi-bsw-n3050     total:254  pass:207  dwarn:0   dfail:0   fail:1   skip:46 
fi-byt-n2820     total:254  pass:211  dwarn:0   dfail:0   fail:2   skip:41 
fi-hsw-4770k     total:254  pass:231  dwarn:0   dfail:0   fail:1   skip:22 
fi-hsw-4770r     total:254  pass:227  dwarn:0   dfail:0   fail:1   skip:26 
fi-ilk-650       total:254  pass:184  dwarn:0   dfail:0   fail:2   skip:68 
fi-ivb-3520m     total:254  pass:222  dwarn:0   dfail:0   fail:1   skip:31 
fi-ivb-3770      total:254  pass:222  dwarn:0   dfail:0   fail:1   skip:31 
fi-skl-6260u     total:254  pass:239  dwarn:0   dfail:0   fail:1   skip:14 
fi-skl-6700hq    total:254  pass:226  dwarn:0   dfail:0   fail:2   skip:26 
fi-skl-6700k     total:254  pass:224  dwarn:1   dfail:0   fail:1   skip:28 
fi-snb-2520m     total:254  pass:208  dwarn:0   dfail:0   fail:1   skip:45 
fi-snb-2600      total:254  pass:208  dwarn:0   dfail:0   fail:1   skip:45 

Results at /archive/results/CI_IGT_test/Patchwork_2501/

5986f290e25f42d3d5df390411cc43683deb1301 drm-intel-nightly: 2016y-09m-08d-09h-11m-50s UTC integration manifest
e1ac102 drm/i915: Mark GuC load status as PENDING in i915_drm_resume_early
12cb572 drm/i915: Add sysfs interface to know the HW requested frequency
6544734 drm/i915/slpc: Enable SLPC, where supported
46a66b4 drm/i915/slpc: Keep RP SW Mode enabled while disabling rps
f0547df drm/i915/slpc: Check GuC load status in SLPC active check
22558c7 drm/i915/slpc: Update freq min/max softlimits
5466b14 drm/i915/slpc: Only Enable GTPERF, Disable DCC, Balancer, IBC, FPS Stall
0d52f57 drm/i915/slpc: Add Broxton SLPC support
29857c7 drm/i915/slpc: Add i915_slpc_info to debugfs
4650a5e drm/i915/slpc: Add enable/disable debugfs for slpc
244c9f4 drm/i915/slpc: Add slpc support for max/min freq
e6fe3ca drm/i915/slpc: Add parameter unset/set/get functions
36eac20 drm/i915/slpc: Add slpc_status enum values
a8805d8 drm/i915/slpc: Send shutdown event
500605c drm/i915/slpc: Send reset event
ca1f1a7 drm/i915/slpc: Update sysfs/debugfs interfaces for frequency parameters
67f591c drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
12b75a7 drm/i915/slpc: If using SLPC, do not set frequency
f2989fc drm/i915/slpc: Enable SLPC in guc if supported
54e0f88 drm/i915/slpc: Use intel_slpc_* functions if supported
43f52e5 drm/i915/slpc: Sanitize SLPC version
716abb9 drm/i915/slpc: Add enable_slpc module parameter
a0f9659 drm/i915/slpc: Add SKL SLPC Support
4d8dfc8 drm/i915/slpc: Add has_slpc capability flag
c3b03b9 drm/i915/slpc: Expose guc functions for use with SLPC
364cd83 drm/i915: Remove RPM suspend dependency on rps.enabled and related changes

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Re: [PATCH v4 25/26] drm/i915: Add sysfs interface to know the HW requested frequency

[Chris Wilson]

On Fri, Sep 09, 2016 at 06:21:44PM +0530, Sagar Arun Kamble wrote:
> With SLPC, user can read this value to know SLPC requested frequency.

Not SLPC specific, even elsewhere there may be a delay between the cur
value and the req (just means something more on SLPC).

Though I'm never keen on expanding the stable ABI, I can't object to
this given the existence of the others - but I will ask for a use case
other than debug.
-Chris

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Re: [PATCH v4 24/26] drm/i915/slpc: Enable SLPC, where supported

[Chris Wilson]

On Fri, Sep 09, 2016 at 06:21:43PM +0530, Sagar Arun Kamble wrote:
> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
> 
> This patch makes SLPC enabled by default on
> platforms with hardware/firmware support.
> 
> v1: Removing warning "enable_slpc < 0" as it is
> set to -1 with this patch now. This was caught by CI BAT.
> 
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_params.c | 4 ++--
>  drivers/gpu/drm/i915/intel_guc.h   | 1 -
>  2 files changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
> index 72b3097..7b3b3fd 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -36,7 +36,7 @@ struct i915_params i915 __read_mostly = {
>  	.enable_dc = -1,
>  	.enable_fbc = -1,
>  	.enable_execlists = -1,
> -	.enable_slpc = 0,
> +	.enable_slpc = -1,
>  	.enable_hangcheck = true,
>  	.enable_ppgtt = -1,
>  	.enable_psr = -1,
> @@ -135,7 +135,7 @@ MODULE_PARM_DESC(enable_execlists,
>  module_param_named_unsafe(enable_slpc, i915.enable_slpc, int, 0400);
>  MODULE_PARM_DESC(enable_slpc,
>  	"Override single-loop-power-controller (slpc) usage. "
> -	"(-1=auto, 0=disabled [default], 1=enabled)");
> +	"(-1=auto [default], 0=disabled, 1=enabled)");
>  
>  module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600);
>  MODULE_PARM_DESC(enable_psr, "Enable PSR "
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index 6e24e60..e9e1163 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -151,7 +151,6 @@ struct intel_guc {
>  
>  static inline int intel_slpc_enabled(void)
>  {
> -	WARN_ON(i915.enable_slpc < 0);

Remove this from the original path, and make it return a bool, since
i915.enable_slpc is always sanitized.

The this patch simply becomes flipping the switch.
-Chris

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Re: [PATCH v4 16/26] drm/i915/slpc: Add slpc support for max/min freq

[Chris Wilson]

On Fri, Sep 09, 2016 at 06:21:35PM +0530, Sagar Arun Kamble wrote:
> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
> 
> Update sysfs and debugfs functions to set SLPC
> parameters when setting max/min frequency.
> 
> v1: Update for SLPC 2015.2.4 (params for both slice and unslice)
>     Replace HAS_SLPC with intel_slpc_active() (Paulo)
> 
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 18 ++++++++++++++++++
>  drivers/gpu/drm/i915/i915_sysfs.c   | 18 ++++++++++++++++++
>  2 files changed, 36 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 71bce32..0956d1f 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -4873,6 +4873,15 @@ i915_max_freq_set(void *data, u64 val)
>  
>  	dev_priv->rps.max_freq_softlimit = val;
>  
> +	if (intel_slpc_active(dev_priv)) {
> +		intel_slpc_set_param(dev_priv,
> +				     SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
> +				     (u32) intel_gpu_freq(dev_priv, val));

Hmm, there are a lot of these casts. Why?

Changing intel_gpu_freq(), intel_freq_opcode() to take and return
unsigned would help.
-Chris

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Re: [PATCH v4 17/26] drm/i915/slpc: Add enable/disable debugfs for slpc

[Chris Wilson]

On Fri, Sep 09, 2016 at 06:21:36PM +0530, Sagar Arun Kamble wrote:
> +static ssize_t slpc_dcc_write(struct file *file, const char __user *ubuf,
> +			      size_t len, loff_t *offp)
> +{
> +	struct seq_file *m = file->private_data;
> +	int ret = 0;
> +
> +	ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_DCC,
> +			       SLPC_PARAM_TASK_DISABLE_DCC);
> +	if (ret)
> +		return (size_t) ret;

What value is (ssize_t)(size_t)-1 as seen by userspace? Is it negative?
-Chris

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Re: [PATCH v4 23/26] drm/i915/slpc: Keep RP SW Mode enabled while disabling rps

[Chris Wilson]

On Fri, Sep 09, 2016 at 06:21:42PM +0530, Sagar Arun Kamble wrote:
> With SLPC, only RP SW Mode control should be left enabled by i915.
> Else, SLPC requests through through RPNSWREQ will not be granted.
> 
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 70e08d9..d06c9bb 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5064,7 +5064,13 @@ static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
>  
>  static void gen9_disable_rps(struct drm_i915_private *dev_priv)
>  {
> -	I915_WRITE(GEN6_RP_CONTROL, 0);
> +	uint32_t rp_ctl = 0;

u32 rp_ctl = 0;

> +
> +	/* RP SW Mode Control will be needed for SLPC, Hence not clearing.*/

	/* RP SW Mode Control will be needed for SLPC, so keep it enabled. */

> +	if (i915.enable_slpc)

intel_slpc_enabled() ? (consistency!)

> +		rp_ctl = I915_READ(GEN6_RP_CONTROL) & GEN6_RP_MEDIA_MODE_MASK;

Ok, so this is not doing what you describe. This is preserving state,
yes. But if we know that state is meant to be enabled for SLPC why are
we reading it back.

I am left with questions about what is happening behind our backs, and
what the code is trying to hide.
-Chris

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Re: [PATCH v4 26/26] drm/i915: Mark GuC load status as PENDING in i915_drm_resume_early

[Chris Wilson]

On Fri, Sep 09, 2016 at 06:21:45PM +0530, Sagar Arun Kamble wrote:
> This will help avoid Host to GuC actions being called till GuC gets
> loaded during i915_drm_resume.
> 
> v2-v3: Rebase.
> 
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>

This looks independent, so ping the people who know about the guc
firmware loading and get it applied.
-Chris

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Re: [PATCH v4 10/26] drm/i915/slpc: Allocate/Release/Initialize SLPC shared data

[Chris Wilson]

On Fri, Sep 09, 2016 at 06:21:29PM +0530, Sagar Arun Kamble wrote:
> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
> 
> SLPC shared data is used to pass information
> to/from SLPC in GuC firmware.
> 
> For Skylake, platform sku type and slice count
> are identified from device id and fuse values.
> 
> Support for other platforms needs to be added.
> 
> v1: Update for SLPC interface version 2015.2.4
>     intel_slpc_active() returns 1 if slpc initialized (Paulo)
>     change default host_os to "Windows"
>     Spelling fixes (Sagar Kamble and Nick Hoath)
>     Added WARN for checking if upper 32bits of GTT offset
>     of shared object are zero. (ChrisW)
>     Changed function call from gem_allocate/release_guc_obj to
>     i915_guc_allocate/release_gem_obj. (Sagar)
>     Updated commit message and moved POWER_PLAN and POWER_SOURCE
>     definition from later patch. (Akash)
>     Add struct_mutex locking while allocating/releasing slpc shared
>     object. This was caught by CI BAT. Adding SLPC state variable
>     to determine if it is active as it not just dependent on shared
>     data setup.
>     Rebase with guc_allocate_vma related changes.
> 
> v2: WARN_ON for platform_sku validity and space changes. (David)
>     Checkpatch update.
> 
> v3: Fixing WARNING in igt@drv_module_reload_basic found in trybot BAT
>     with SLPC Enabled.
> 
> v4: Updated support for GuC v9. s/slice_total/hweight8(slice_mask)/ (Dave).
> 
> Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_drv.h  |  7 ++-
>  drivers/gpu/drm/i915/intel_guc.h  |  2 +
>  drivers/gpu/drm/i915/intel_pm.c   |  6 ++-
>  drivers/gpu/drm/i915/intel_slpc.c | 88 ++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_slpc.h | 99 +++++++++++++++++++++++++++++++++++++++
>  5 files changed, 199 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index cf9aa24..796c52f 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1707,7 +1707,12 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
>  

I am going to need an idiot's guide here as to the difference between
enabled() and active().

>  static inline int intel_slpc_active(struct drm_i915_private *dev_priv)

bool.

>  {
> -	return 0;
> +	int ret = 0;
> +
> +	if (dev_priv->guc.slpc.vma && dev_priv->guc.slpc.enabled)
> +		ret = 1;
> +
> +	return ret;
>  }
>  
>  /* intel_pm.c */
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index 83dec66..6e24e60 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -145,6 +145,8 @@ struct intel_guc {
>  
>  	uint64_t submissions[I915_NUM_ENGINES];
>  	uint32_t last_seqno[I915_NUM_ENGINES];
> +
> +	struct intel_slpc slpc;
>  };
>  
>  static inline int intel_slpc_enabled(void)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d187066..2211f7b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6656,7 +6656,8 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
>  
>  void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
>  {
> -	if (intel_slpc_enabled())
> +	if (intel_slpc_enabled() &&
> +	    dev_priv->guc.slpc.vma)
>  		intel_slpc_cleanup(dev_priv);
>  	else if (IS_VALLEYVIEW(dev_priv))
>  		valleyview_cleanup_gt_powersave(dev_priv);
> @@ -6746,7 +6747,8 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
>  
>  	mutex_lock(&dev_priv->rps.hw_lock);
>  
> -	if (intel_slpc_enabled()) {
> +	if (intel_slpc_enabled() &&
> +	    dev_priv->guc.slpc.vma) {
>  		gen9_enable_rc6(dev_priv);
>  		intel_slpc_enable(dev_priv);
>  		if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
> index be9e84c..972db18 100644
> --- a/drivers/gpu/drm/i915/intel_slpc.c
> +++ b/drivers/gpu/drm/i915/intel_slpc.c
> @@ -22,15 +22,103 @@
>   *
>   */
>  #include <linux/firmware.h>
> +#include <asm/msr-index.h>
>  #include "i915_drv.h"
>  #include "intel_guc.h"
>  
> +static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
> +{
> +	enum slpc_platform_sku platform_sku;
> +
> +	if (IS_SKL_ULX(dev_priv))
> +		platform_sku = SLPC_PLATFORM_SKU_ULX;
> +	else if (IS_SKL_ULT(dev_priv))
> +		platform_sku = SLPC_PLATFORM_SKU_ULT;
> +	else
> +		platform_sku = SLPC_PLATFORM_SKU_DT;
> +
> +	WARN_ON(platform_sku > 0xFF);
> +
> +	return platform_sku;
> +}
> +
> +static unsigned int slpc_get_slice_count(struct drm_i915_private *dev_priv)
> +{
> +	unsigned int slice_count = 1;
> +
> +	if (IS_SKYLAKE(dev_priv))
> +		slice_count = hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask);
> +
> +	return slice_count;
> +}
> +
> +static void slpc_shared_data_init(struct drm_i915_private *dev_priv)
> +{
> +	struct drm_i915_gem_object *obj;
> +	struct page *page;
> +	struct slpc_shared_data *data;
> +	u64 msr_value;
> +
> +	if (!dev_priv->guc.slpc.vma)
> +		return;
> +
> +	obj = dev_priv->guc.slpc.vma->obj;
> +
> +	page = i915_gem_object_get_page(obj, 0);

page = i915_vma_first_pgae(dev_priv->guc.slpc.vma);

and cannot be NULL (by construction in guc_allocate_vma).

> +	if (page) {
> +		data = kmap_atomic(page);
> +		memset(data, 0, sizeof(struct slpc_shared_data));
> +
> +		data->shared_data_size = sizeof(struct slpc_shared_data);
> +		data->global_state = (u32)SLPC_GLOBAL_STATE_NOT_RUNNING;
> +		data->platform_info.platform_sku =
> +					(u8)slpc_get_platform_sku(dev_priv);
> +		data->platform_info.slice_count =
> +					(u8)slpc_get_slice_count(dev_priv);
> +		data->platform_info.power_plan_source =
> +			(u8)SLPC_POWER_PLAN_SOURCE(SLPC_POWER_PLAN_BALANCED,
> +						    SLPC_POWER_SOURCE_AC);
> +		rdmsrl(MSR_TURBO_RATIO_LIMIT, msr_value);
> +		data->platform_info.P0_freq = (u8)msr_value;
> +		rdmsrl(MSR_PLATFORM_INFO, msr_value);
> +		data->platform_info.P1_freq = (u8)(msr_value >> 8);
> +		data->platform_info.Pe_freq = (u8)(msr_value >> 40);
> +		data->platform_info.Pn_freq = (u8)(msr_value >> 48);

The u8 et al are implied anyway, are they not?

> +
> +		kunmap_atomic(data);
> +	}
> +}
> +
>  void intel_slpc_init(struct drm_i915_private *dev_priv)
>  {
> +	struct intel_guc *guc = &dev_priv->guc;
> +	struct i915_vma *vma;
> +
> +	/* Allocate shared data structure */
> +	vma = dev_priv->guc.slpc.vma;
> +	if (!vma) {

There's always something fishy about init routines called multiple
times.
-Chris

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Re: [PATCH v4 11/26] drm/i915/slpc: Update sysfs/debugfs interfaces for frequency parameters

[Chris Wilson]

On Fri, Sep 09, 2016 at 06:21:30PM +0530, Sagar Arun Kamble wrote:
> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
> 
> When SLPC is controlling requested frequency, the rps.cur_freq
> value is not used to make the frequency request.
> 
> Requested frequency from register RPNSWREQ has the value
> most recently requested by SLPC firmware. Adding new sysfs
> interface gt_req_freq_mhz to know this value.
> SLPC requested value needs to be made available to i915 without
> reading RPNSWREQ.
> 
> v1: Replace HAS_SLPC with intel_slpc_active (Paulo)
>     Avoid magic numbers (Nick)
>     Use a function for repeated code (Jon)
> 
> v2: Add "SLPC Active" to i915_frequency_info output and
>     don't update cur_freq as it is driver internal request. (Chris)
> 
> v3: Removing sysfs interface gt_req_freq_mhz out of this patch
>     for proper division of functionality. (Sagar)
> 
> v4: idle_freq, boost_freq are also not used with SLPC.
> 
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 24 ++++++++++++++++++------
>  drivers/gpu/drm/i915/i915_sysfs.c   |  3 +++
>  2 files changed, 21 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 02b627e..71bce32 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1083,6 +1083,9 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  
>  	intel_runtime_pm_get(dev_priv);
>  
> +	if (intel_slpc_active(dev_priv))
> +		seq_puts(m, "SLPC Active\n");
> +
>  	if (IS_GEN5(dev_priv)) {
>  		u16 rgvswctl = I915_READ16(MEMSWCTL);
>  		u16 rgvstat = I915_READ16(MEMSTAT_ILK);
> @@ -1250,15 +1253,21 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  		seq_printf(m, "Max overclocked frequency: %dMHz\n",
>  			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
>  
> -		seq_printf(m, "Current freq: %d MHz\n",
> -			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
> +		if (!intel_slpc_active(dev_priv)) {

Just keep printing them, we have the banner upfront, and being able to
track and compare internal values vs hw state is still important. (And
the ordering was fairly intentional.)

> +			seq_printf(m, "Current freq: %d MHz\n",
> +				   intel_gpu_freq(dev_priv,
> +						  dev_priv->rps.cur_freq));
> +			seq_printf(m, "Idle freq: %d MHz\n",
> +				   intel_gpu_freq(dev_priv,
> +						  dev_priv->rps.idle_freq));
> +			seq_printf(m, "Boost freq: %d MHz\n",
> +				   intel_gpu_freq(dev_priv,
> +						  dev_priv->rps.boost_freq));
> +		}
> +
>  		seq_printf(m, "Actual freq: %d MHz\n", cagf);
> -		seq_printf(m, "Idle freq: %d MHz\n",
> -			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
>  		seq_printf(m, "Min freq: %d MHz\n",
>  			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
> -		seq_printf(m, "Boost freq: %d MHz\n",
> -			   intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
>  		seq_printf(m, "Max freq: %d MHz\n",
>  			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
>  		seq_printf(m,
> @@ -2315,6 +2324,9 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
>  	struct drm_device *dev = &dev_priv->drm;
>  	struct drm_file *file;
>  
> +	if (intel_slpc_active(dev_priv))
> +		return -ENODEV;
> +
>  	seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
>  	seq_printf(m, "GPU busy? %s [%x]\n",
>  		   yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index 1012eee..020d64e 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -299,6 +299,9 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
>  {
>  	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
>  
> +	if (intel_slpc_active(dev_priv))
> +		return -ENODEV;

Ok, I had a thought that we allowed the user to directly set cur freq,
but we don't.
-Chris

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Re: [PATCH v4 18/26] drm/i915/slpc: Add i915_slpc_info to debugfs

[Chris Wilson]

On Fri, Sep 09, 2016 at 06:21:37PM +0530, Sagar Arun Kamble wrote:
> +	if (!intel_slpc_active(dev_priv))
> +		return -ENODEV;

Can we really say slpc is active without an slpc.vma?
-Chris

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Re: [PATCH v4 07/26] drm/i915/slpc: Use intel_slpc_* functions if supported

[Chris Wilson]

On Fri, Sep 09, 2016 at 06:21:26PM +0530, Sagar Arun Kamble wrote:
> @@ -6720,31 +6743,38 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
> +	if (intel_slpc_enabled()) {
> +	} else {
>  
> -	WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
> -	WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
> +		WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
> +		WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
>  
> -	WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
> -	WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
> +		WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
> +		WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);

You seem to be chickening out of some sanity checks on values we present
to the user.
-Chris

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Re: [PATCH v4 09/26] drm/i915/slpc: If using SLPC, do not set frequency

[Chris Wilson]

On Fri, Sep 09, 2016 at 06:21:28PM +0530, Sagar Arun Kamble wrote:
> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
> 
> When frequency requests are made by SLPC, host driver
> should not attempt to make frequency requests due to
> potential conflicts.
> 
> Host-based turbo operations are already avoided when
> SLPC is used.  This change covers other frequency
> requests such as from sysfs or debugfs interfaces.
> 
> A later patch in this series updates sysfs/debugfs
> interfaces for setting max/min frequencies with SLPC.
> 
> v1: Use intel_slpc_active instead of HAS_SLPC (Paulo)
> 
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index db5c4ef..d187066 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5047,6 +5047,9 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv,
>  
>  void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
>  {
> +	if (intel_slpc_active(dev_priv))
> +		return;

active not enabled?

All of the other checks in rps are enabled, right?
-Chris

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Re: [PATCH v4 07/26] drm/i915/slpc: Use intel_slpc_* functions if supported

[Kamble, Sagar A]

Thanks for the review.


On 9/9/2016 10:50 PM, Chris Wilson wrote:
> On Fri, Sep 09, 2016 at 06:21:26PM +0530, Sagar Arun Kamble wrote:
>> @@ -6720,31 +6743,38 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
>> +	if (intel_slpc_enabled()) {
>> +	} else {
>>   
>> -	WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
>> -	WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
>> +		WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
>> +		WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
>>   
>> -	WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
>> -	WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
>> +		WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
>> +		WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
> You seem to be chickening out of some sanity checks on values we present
> to the user.
> -Chris

Will restore these. idle_freq not applicable to SLPC hence will remove 
check for it with SLPC.

>

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Re: [PATCH v4 09/26] drm/i915/slpc: If using SLPC, do not set frequency

[Kamble, Sagar A]

On 9/9/2016 10:51 PM, Chris Wilson wrote:
> On Fri, Sep 09, 2016 at 06:21:28PM +0530, Sagar Arun Kamble wrote:
>> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
>>
>> When frequency requests are made by SLPC, host driver
>> should not attempt to make frequency requests due to
>> potential conflicts.
>>
>> Host-based turbo operations are already avoided when
>> SLPC is used.  This change covers other frequency
>> requests such as from sysfs or debugfs interfaces.
>>
>> A later patch in this series updates sysfs/debugfs
>> interfaces for setting max/min frequencies with SLPC.
>>
>> v1: Use intel_slpc_active instead of HAS_SLPC (Paulo)
>>
>> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
>> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_pm.c | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index db5c4ef..d187066 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -5047,6 +5047,9 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv,
>>   
>>   void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
>>   {
>> +	if (intel_slpc_active(dev_priv))
>> +		return;
> active not enabled?
>
> All of the other checks in rps are enabled, right?
> -Chris

Will change this to make consistent.

>

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Re: [PATCH v4 10/26] drm/i915/slpc: Allocate/Release/Initialize SLPC shared data

[Kamble, Sagar A]

On 9/9/2016 10:38 PM, Chris Wilson wrote:
> On Fri, Sep 09, 2016 at 06:21:29PM +0530, Sagar Arun Kamble wrote:
>> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
>>
>> SLPC shared data is used to pass information
>> to/from SLPC in GuC firmware.
>>
>> For Skylake, platform sku type and slice count
>> are identified from device id and fuse values.
>>
>> Support for other platforms needs to be added.
>>
>> v1: Update for SLPC interface version 2015.2.4
>>      intel_slpc_active() returns 1 if slpc initialized (Paulo)
>>      change default host_os to "Windows"
>>      Spelling fixes (Sagar Kamble and Nick Hoath)
>>      Added WARN for checking if upper 32bits of GTT offset
>>      of shared object are zero. (ChrisW)
>>      Changed function call from gem_allocate/release_guc_obj to
>>      i915_guc_allocate/release_gem_obj. (Sagar)
>>      Updated commit message and moved POWER_PLAN and POWER_SOURCE
>>      definition from later patch. (Akash)
>>      Add struct_mutex locking while allocating/releasing slpc shared
>>      object. This was caught by CI BAT. Adding SLPC state variable
>>      to determine if it is active as it not just dependent on shared
>>      data setup.
>>      Rebase with guc_allocate_vma related changes.
>>
>> v2: WARN_ON for platform_sku validity and space changes. (David)
>>      Checkpatch update.
>>
>> v3: Fixing WARNING in igt@drv_module_reload_basic found in trybot BAT
>>      with SLPC Enabled.
>>
>> v4: Updated support for GuC v9. s/slice_total/hweight8(slice_mask)/ (Dave).
>>
>> Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
>> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
>> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_drv.h  |  7 ++-
>>   drivers/gpu/drm/i915/intel_guc.h  |  2 +
>>   drivers/gpu/drm/i915/intel_pm.c   |  6 ++-
>>   drivers/gpu/drm/i915/intel_slpc.c | 88 ++++++++++++++++++++++++++++++++++
>>   drivers/gpu/drm/i915/intel_slpc.h | 99 +++++++++++++++++++++++++++++++++++++++
>>   5 files changed, 199 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index cf9aa24..796c52f 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -1707,7 +1707,12 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
>>   
> I am going to need an idiot's guide here as to the difference between
> enabled() and active().
Idea was to set active only when shared data is initialized. enabled was 
used to do initial/final setup.
Will change this and make consistent everywhere by keeping only one state.
>
>>   static inline int intel_slpc_active(struct drm_i915_private *dev_priv)
> bool.
will update
>
>>   {
>> -	return 0;
>> +	int ret = 0;
>> +
>> +	if (dev_priv->guc.slpc.vma && dev_priv->guc.slpc.enabled)
>> +		ret = 1;
>> +
>> +	return ret;
>>   }
>>   
>>   /* intel_pm.c */
>> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
>> index 83dec66..6e24e60 100644
>> --- a/drivers/gpu/drm/i915/intel_guc.h
>> +++ b/drivers/gpu/drm/i915/intel_guc.h
>> @@ -145,6 +145,8 @@ struct intel_guc {
>>   
>>   	uint64_t submissions[I915_NUM_ENGINES];
>>   	uint32_t last_seqno[I915_NUM_ENGINES];
>> +
>> +	struct intel_slpc slpc;
>>   };
>>   
>>   static inline int intel_slpc_enabled(void)
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index d187066..2211f7b 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -6656,7 +6656,8 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
>>   
>>   void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
>>   {
>> -	if (intel_slpc_enabled())
>> +	if (intel_slpc_enabled() &&
>> +	    dev_priv->guc.slpc.vma)
>>   		intel_slpc_cleanup(dev_priv);
>>   	else if (IS_VALLEYVIEW(dev_priv))
>>   		valleyview_cleanup_gt_powersave(dev_priv);
>> @@ -6746,7 +6747,8 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
>>   
>>   	mutex_lock(&dev_priv->rps.hw_lock);
>>   
>> -	if (intel_slpc_enabled()) {
>> +	if (intel_slpc_enabled() &&
>> +	    dev_priv->guc.slpc.vma) {
>>   		gen9_enable_rc6(dev_priv);
>>   		intel_slpc_enable(dev_priv);
>>   		if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
>> diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
>> index be9e84c..972db18 100644
>> --- a/drivers/gpu/drm/i915/intel_slpc.c
>> +++ b/drivers/gpu/drm/i915/intel_slpc.c
>> @@ -22,15 +22,103 @@
>>    *
>>    */
>>   #include <linux/firmware.h>
>> +#include <asm/msr-index.h>
>>   #include "i915_drv.h"
>>   #include "intel_guc.h"
>>   
>> +static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
>> +{
>> +	enum slpc_platform_sku platform_sku;
>> +
>> +	if (IS_SKL_ULX(dev_priv))
>> +		platform_sku = SLPC_PLATFORM_SKU_ULX;
>> +	else if (IS_SKL_ULT(dev_priv))
>> +		platform_sku = SLPC_PLATFORM_SKU_ULT;
>> +	else
>> +		platform_sku = SLPC_PLATFORM_SKU_DT;
>> +
>> +	WARN_ON(platform_sku > 0xFF);
>> +
>> +	return platform_sku;
>> +}
>> +
>> +static unsigned int slpc_get_slice_count(struct drm_i915_private *dev_priv)
>> +{
>> +	unsigned int slice_count = 1;
>> +
>> +	if (IS_SKYLAKE(dev_priv))
>> +		slice_count = hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask);
>> +
>> +	return slice_count;
>> +}
>> +
>> +static void slpc_shared_data_init(struct drm_i915_private *dev_priv)
>> +{
>> +	struct drm_i915_gem_object *obj;
>> +	struct page *page;
>> +	struct slpc_shared_data *data;
>> +	u64 msr_value;
>> +
>> +	if (!dev_priv->guc.slpc.vma)
>> +		return;
>> +
>> +	obj = dev_priv->guc.slpc.vma->obj;
>> +
>> +	page = i915_gem_object_get_page(obj, 0);
> page = i915_vma_first_pgae(dev_priv->guc.slpc.vma);
>
> and cannot be NULL (by construction in guc_allocate_vma).
will update
>> +	if (page) {
>> +		data = kmap_atomic(page);
>> +		memset(data, 0, sizeof(struct slpc_shared_data));
>> +
>> +		data->shared_data_size = sizeof(struct slpc_shared_data);
>> +		data->global_state = (u32)SLPC_GLOBAL_STATE_NOT_RUNNING;
>> +		data->platform_info.platform_sku =
>> +					(u8)slpc_get_platform_sku(dev_priv);
>> +		data->platform_info.slice_count =
>> +					(u8)slpc_get_slice_count(dev_priv);
>> +		data->platform_info.power_plan_source =
>> +			(u8)SLPC_POWER_PLAN_SOURCE(SLPC_POWER_PLAN_BALANCED,
>> +						    SLPC_POWER_SOURCE_AC);
>> +		rdmsrl(MSR_TURBO_RATIO_LIMIT, msr_value);
>> +		data->platform_info.P0_freq = (u8)msr_value;
>> +		rdmsrl(MSR_PLATFORM_INFO, msr_value);
>> +		data->platform_info.P1_freq = (u8)(msr_value >> 8);
>> +		data->platform_info.Pe_freq = (u8)(msr_value >> 40);
>> +		data->platform_info.Pn_freq = (u8)(msr_value >> 48);
> The u8 et al are implied anyway, are they not?
yes. will update
>> +
>> +		kunmap_atomic(data);
>> +	}
>> +}
>> +
>>   void intel_slpc_init(struct drm_i915_private *dev_priv)
>>   {
>> +	struct intel_guc *guc = &dev_priv->guc;
>> +	struct i915_vma *vma;
>> +
>> +	/* Allocate shared data structure */
>> +	vma = dev_priv->guc.slpc.vma;
>> +	if (!vma) {
> There's always something fishy about init routines called multiple
> times.
intel_slpc_init will be called only once during intel_init_gt_powersave
> -Chris
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Re: [PATCH v4 11/26] drm/i915/slpc: Update sysfs/debugfs interfaces for frequency parameters

[Kamble, Sagar A]

On 9/9/2016 10:43 PM, Chris Wilson wrote:
> On Fri, Sep 09, 2016 at 06:21:30PM +0530, Sagar Arun Kamble wrote:
>> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
>>
>> When SLPC is controlling requested frequency, the rps.cur_freq
>> value is not used to make the frequency request.
>>
>> Requested frequency from register RPNSWREQ has the value
>> most recently requested by SLPC firmware. Adding new sysfs
>> interface gt_req_freq_mhz to know this value.
>> SLPC requested value needs to be made available to i915 without
>> reading RPNSWREQ.
>>
>> v1: Replace HAS_SLPC with intel_slpc_active (Paulo)
>>      Avoid magic numbers (Nick)
>>      Use a function for repeated code (Jon)
>>
>> v2: Add "SLPC Active" to i915_frequency_info output and
>>      don't update cur_freq as it is driver internal request. (Chris)
>>
>> v3: Removing sysfs interface gt_req_freq_mhz out of this patch
>>      for proper division of functionality. (Sagar)
>>
>> v4: idle_freq, boost_freq are also not used with SLPC.
>>
>> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
>> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_debugfs.c | 24 ++++++++++++++++++------
>>   drivers/gpu/drm/i915/i915_sysfs.c   |  3 +++
>>   2 files changed, 21 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>> index 02b627e..71bce32 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -1083,6 +1083,9 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>>   
>>   	intel_runtime_pm_get(dev_priv);
>>   
>> +	if (intel_slpc_active(dev_priv))
>> +		seq_puts(m, "SLPC Active\n");
>> +
>>   	if (IS_GEN5(dev_priv)) {
>>   		u16 rgvswctl = I915_READ16(MEMSWCTL);
>>   		u16 rgvstat = I915_READ16(MEMSTAT_ILK);
>> @@ -1250,15 +1253,21 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>>   		seq_printf(m, "Max overclocked frequency: %dMHz\n",
>>   			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
>>   
>> -		seq_printf(m, "Current freq: %d MHz\n",
>> -			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
>> +		if (!intel_slpc_active(dev_priv)) {
> Just keep printing them, we have the banner upfront, and being able to
> track and compare internal values vs hw state is still important. (And
> the ordering was fairly intentional.)
cur_freq, idle_freq, boost_freq will not be applicable with SLPC.
With SLPC we should rely on value from RPNSWREQ for cur_freq.
>
>> +			seq_printf(m, "Current freq: %d MHz\n",
>> +				   intel_gpu_freq(dev_priv,
>> +						  dev_priv->rps.cur_freq));
>> +			seq_printf(m, "Idle freq: %d MHz\n",
>> +				   intel_gpu_freq(dev_priv,
>> +						  dev_priv->rps.idle_freq));
>> +			seq_printf(m, "Boost freq: %d MHz\n",
>> +				   intel_gpu_freq(dev_priv,
>> +						  dev_priv->rps.boost_freq));
>> +		}
>> +
>>   		seq_printf(m, "Actual freq: %d MHz\n", cagf);
>> -		seq_printf(m, "Idle freq: %d MHz\n",
>> -			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
>>   		seq_printf(m, "Min freq: %d MHz\n",
>>   			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
>> -		seq_printf(m, "Boost freq: %d MHz\n",
>> -			   intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
>>   		seq_printf(m, "Max freq: %d MHz\n",
>>   			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
>>   		seq_printf(m,
>> @@ -2315,6 +2324,9 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
>>   	struct drm_device *dev = &dev_priv->drm;
>>   	struct drm_file *file;
>>   
>> +	if (intel_slpc_active(dev_priv))
>> +		return -ENODEV;
>> +
>>   	seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
>>   	seq_printf(m, "GPU busy? %s [%x]\n",
>>   		   yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
>> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
>> index 1012eee..020d64e 100644
>> --- a/drivers/gpu/drm/i915/i915_sysfs.c
>> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
>> @@ -299,6 +299,9 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
>>   {
>>   	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
>>   
>> +	if (intel_slpc_active(dev_priv))
>> +		return -ENODEV;
> Ok, I had a thought that we allowed the user to directly set cur freq,
> but we don't.
> -Chris
>

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Re: [PATCH v4 16/26] drm/i915/slpc: Add slpc support for max/min freq

[Kamble, Sagar A]

On 9/9/2016 10:19 PM, Chris Wilson wrote:
> On Fri, Sep 09, 2016 at 06:21:35PM +0530, Sagar Arun Kamble wrote:
>> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
>>
>> Update sysfs and debugfs functions to set SLPC
>> parameters when setting max/min frequency.
>>
>> v1: Update for SLPC 2015.2.4 (params for both slice and unslice)
>>      Replace HAS_SLPC with intel_slpc_active() (Paulo)
>>
>> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
>> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_debugfs.c | 18 ++++++++++++++++++
>>   drivers/gpu/drm/i915/i915_sysfs.c   | 18 ++++++++++++++++++
>>   2 files changed, 36 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>> index 71bce32..0956d1f 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -4873,6 +4873,15 @@ i915_max_freq_set(void *data, u64 val)
>>   
>>   	dev_priv->rps.max_freq_softlimit = val;
>>   
>> +	if (intel_slpc_active(dev_priv)) {
>> +		intel_slpc_set_param(dev_priv,
>> +				     SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
>> +				     (u32) intel_gpu_freq(dev_priv, val));
> Hmm, there are a lot of these casts. Why?
>
> Changing intel_gpu_freq(), intel_freq_opcode() to take and return
> unsigned would help.
will fix this
> -Chris
>

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Re: [PATCH v4 17/26] drm/i915/slpc: Add enable/disable debugfs for slpc

[Kamble, Sagar A]

On 9/9/2016 10:24 PM, Chris Wilson wrote:
> On Fri, Sep 09, 2016 at 06:21:36PM +0530, Sagar Arun Kamble wrote:
>> +static ssize_t slpc_dcc_write(struct file *file, const char __user *ubuf,
>> +			      size_t len, loff_t *offp)
>> +{
>> +	struct seq_file *m = file->private_data;
>> +	int ret = 0;
>> +
>> +	ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_DCC,
>> +			       SLPC_PARAM_TASK_DISABLE_DCC);
>> +	if (ret)
>> +		return (size_t) ret;
> What value is (ssize_t)(size_t)-1 as seen by userspace? Is it negative?
Will fix this. casting is not needed.
> -Chris
>

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Re: [PATCH v4 18/26] drm/i915/slpc: Add i915_slpc_info to debugfs

[Kamble, Sagar A]

On 9/9/2016 10:44 PM, Chris Wilson wrote:
> On Fri, Sep 09, 2016 at 06:21:37PM +0530, Sagar Arun Kamble wrote:
>> +	if (!intel_slpc_active(dev_priv))
>> +		return -ENODEV;
> Can we really say slpc is active without an slpc.vma?
No. Will remove this check.
> -Chris
>

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Re: [PATCH v4 24/26] drm/i915/slpc: Enable SLPC, where supported

[Kamble, Sagar A]

On 9/9/2016 10:15 PM, Chris Wilson wrote:
> On Fri, Sep 09, 2016 at 06:21:43PM +0530, Sagar Arun Kamble wrote:
>> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
>>
>> This patch makes SLPC enabled by default on
>> platforms with hardware/firmware support.
>>
>> v1: Removing warning "enable_slpc < 0" as it is
>> set to -1 with this patch now. This was caught by CI BAT.
>>
>> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
>> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_params.c | 4 ++--
>>   drivers/gpu/drm/i915/intel_guc.h   | 1 -
>>   2 files changed, 2 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
>> index 72b3097..7b3b3fd 100644
>> --- a/drivers/gpu/drm/i915/i915_params.c
>> +++ b/drivers/gpu/drm/i915/i915_params.c
>> @@ -36,7 +36,7 @@ struct i915_params i915 __read_mostly = {
>>   	.enable_dc = -1,
>>   	.enable_fbc = -1,
>>   	.enable_execlists = -1,
>> -	.enable_slpc = 0,
>> +	.enable_slpc = -1,
>>   	.enable_hangcheck = true,
>>   	.enable_ppgtt = -1,
>>   	.enable_psr = -1,
>> @@ -135,7 +135,7 @@ MODULE_PARM_DESC(enable_execlists,
>>   module_param_named_unsafe(enable_slpc, i915.enable_slpc, int, 0400);
>>   MODULE_PARM_DESC(enable_slpc,
>>   	"Override single-loop-power-controller (slpc) usage. "
>> -	"(-1=auto, 0=disabled [default], 1=enabled)");
>> +	"(-1=auto [default], 0=disabled, 1=enabled)");
>>   
>>   module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600);
>>   MODULE_PARM_DESC(enable_psr, "Enable PSR "
>> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
>> index 6e24e60..e9e1163 100644
>> --- a/drivers/gpu/drm/i915/intel_guc.h
>> +++ b/drivers/gpu/drm/i915/intel_guc.h
>> @@ -151,7 +151,6 @@ struct intel_guc {
>>   
>>   static inline int intel_slpc_enabled(void)
>>   {
>> -	WARN_ON(i915.enable_slpc < 0);
> Remove this from the original path, and make it return a bool, since
> i915.enable_slpc is always sanitized.
>
> The this patch simply becomes flipping the switch.
Will update this.
> -Chris
>

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Re: [PATCH v4 23/26] drm/i915/slpc: Keep RP SW Mode enabled while disabling rps

[Kamble, Sagar A]

On 9/9/2016 10:28 PM, Chris Wilson wrote:
> On Fri, Sep 09, 2016 at 06:21:42PM +0530, Sagar Arun Kamble wrote:
>> With SLPC, only RP SW Mode control should be left enabled by i915.
>> Else, SLPC requests through through RPNSWREQ will not be granted.
>>
>> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_pm.c | 8 +++++++-
>>   1 file changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 70e08d9..d06c9bb 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -5064,7 +5064,13 @@ static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
>>   
>>   static void gen9_disable_rps(struct drm_i915_private *dev_priv)
>>   {
>> -	I915_WRITE(GEN6_RP_CONTROL, 0);
>> +	uint32_t rp_ctl = 0;
> u32 rp_ctl = 0;
>
>> +
>> +	/* RP SW Mode Control will be needed for SLPC, Hence not clearing.*/
> 	/* RP SW Mode Control will be needed for SLPC, so keep it enabled. */
>
>> +	if (i915.enable_slpc)
> intel_slpc_enabled() ? (consistency!)
Will update this.
>
>> +		rp_ctl = I915_READ(GEN6_RP_CONTROL) & GEN6_RP_MEDIA_MODE_MASK;
> Ok, so this is not doing what you describe. This is preserving state,
> yes. But if we know that state is meant to be enabled for SLPC why are
> we reading it back.
>
> I am left with questions about what is happening behind our backs, and
> what the code is trying to hide.
Will fix this. SLPC is going to request frequency hence we need to make 
sure host
does not tamper RP_CONTROL settings.
> -Chris
>

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Re: [PATCH v4 25/26] drm/i915: Add sysfs interface to know the HW requested frequency

[Kamble, Sagar A]

On 9/9/2016 10:13 PM, Chris Wilson wrote:
> On Fri, Sep 09, 2016 at 06:21:44PM +0530, Sagar Arun Kamble wrote:
>> With SLPC, user can read this value to know SLPC requested frequency.
> Not SLPC specific, even elsewhere there may be a delay between the cur
> value and the req (just means something more on SLPC).
cur_freq is updated whenever RPNSWREQ is written so they should be same 
right?
Where will delay come into picture?
>
> Though I'm never keen on expanding the stable ABI, I can't object to
> this given the existence of the others - but I will ask for a use case
> other than debug.
For testing SLPC requests from Host side we have to rely on read of RPNSWREQ
> -Chris
>

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Re: [PATCH v4 11/26] drm/i915/slpc: Update sysfs/debugfs interfaces for frequency parameters

[Chris Wilson]

On Thu, Sep 15, 2016 at 04:11:45PM +0530, Kamble, Sagar A wrote:
> 
> 
> On 9/9/2016 10:43 PM, Chris Wilson wrote:
> >On Fri, Sep 09, 2016 at 06:21:30PM +0530, Sagar Arun Kamble wrote:
> >>From: Tom O'Rourke <Tom.O'Rourke@intel.com>
> >>
> >>When SLPC is controlling requested frequency, the rps.cur_freq
> >>value is not used to make the frequency request.
> >>
> >>Requested frequency from register RPNSWREQ has the value
> >>most recently requested by SLPC firmware. Adding new sysfs
> >>interface gt_req_freq_mhz to know this value.
> >>SLPC requested value needs to be made available to i915 without
> >>reading RPNSWREQ.
> >>
> >>v1: Replace HAS_SLPC with intel_slpc_active (Paulo)
> >>     Avoid magic numbers (Nick)
> >>     Use a function for repeated code (Jon)
> >>
> >>v2: Add "SLPC Active" to i915_frequency_info output and
> >>     don't update cur_freq as it is driver internal request. (Chris)
> >>
> >>v3: Removing sysfs interface gt_req_freq_mhz out of this patch
> >>     for proper division of functionality. (Sagar)
> >>
> >>v4: idle_freq, boost_freq are also not used with SLPC.
> >>
> >>Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> >>Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> >>---
> >>  drivers/gpu/drm/i915/i915_debugfs.c | 24 ++++++++++++++++++------
> >>  drivers/gpu/drm/i915/i915_sysfs.c   |  3 +++
> >>  2 files changed, 21 insertions(+), 6 deletions(-)
> >>
> >>diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> >>index 02b627e..71bce32 100644
> >>--- a/drivers/gpu/drm/i915/i915_debugfs.c
> >>+++ b/drivers/gpu/drm/i915/i915_debugfs.c
> >>@@ -1083,6 +1083,9 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> >>  	intel_runtime_pm_get(dev_priv);
> >>+	if (intel_slpc_active(dev_priv))
> >>+		seq_puts(m, "SLPC Active\n");
> >>+
> >>  	if (IS_GEN5(dev_priv)) {
> >>  		u16 rgvswctl = I915_READ16(MEMSWCTL);
> >>  		u16 rgvstat = I915_READ16(MEMSTAT_ILK);
> >>@@ -1250,15 +1253,21 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> >>  		seq_printf(m, "Max overclocked frequency: %dMHz\n",
> >>  			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
> >>-		seq_printf(m, "Current freq: %d MHz\n",
> >>-			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
> >>+		if (!intel_slpc_active(dev_priv)) {
> >Just keep printing them, we have the banner upfront, and being able to
> >track and compare internal values vs hw state is still important. (And
> >the ordering was fairly intentional.)
> cur_freq, idle_freq, boost_freq will not be applicable with SLPC.
> With SLPC we should rely on value from RPNSWREQ for cur_freq.

Hence the banner. We still want to be able to inspect our internal
values to see if anything is going wrong, whether SLPC is enabled or
not. E.g. if SLPC is and yet the bookkeeping is changing, something is
wrong.
-Chris

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Re: [PATCH v4 25/26] drm/i915: Add sysfs interface to know the HW requested frequency

[Chris Wilson]

On Thu, Sep 15, 2016 at 04:14:22PM +0530, Kamble, Sagar A wrote:
> 
> 
> On 9/9/2016 10:13 PM, Chris Wilson wrote:
> >On Fri, Sep 09, 2016 at 06:21:44PM +0530, Sagar Arun Kamble wrote:
> >>With SLPC, user can read this value to know SLPC requested frequency.
> >Not SLPC specific, even elsewhere there may be a delay between the cur
> >value and the req (just means something more on SLPC).
> cur_freq is updated whenever RPNSWREQ is written so they should be
> same right?
> Where will delay come into picture?

RPNSWEQ is only updated from an irq worker. Plenty of scope for
breakage.
-Chris

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