* [PATCH 0/4] Amlogic Meson SAR ADC support
@ 2017-01-11 17:43 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-11 17:43 UTC (permalink / raw)
To: jic23-DgEjT+Ai2ygdnm+yROfE0A, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
khilman-rdvid1DuHRBWk0Htik3J/w, linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-clk-u79uwXL29TY76Z2rM5mHXA
Cc: carlo-KA+7E9HrN00dnm+yROfE0A, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, mturquette-rdvid1DuHRBWk0Htik3J/w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, narmstrong-rdvid1DuHRBWk0Htik3J/w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Martin Blumenstingl
This series add support for the SAR ADC on Amlogic Meson GXBB, GXL and
GXM SoCs.
The hardware on GXBB provides 10-bit ADC results, while GXL and GXM are
providing 12-bit results. Support for older SoCs (Meson8b and Meson8)
can be added with little effort, most of which is testing I guess (I
don't have any pre-GXBB hardware so I can't say).
A new set of clocks had to be added to the GXBB clock controller (used
by the GXBB/GXL/GXM SoCs) which are required to get the ADC working.
The ADC itself can sample multiple channels at the same time and allows
capturing multiple samples (which can be used for filtering/averaging).
The ADC results are stored inside a FIFO register. More details on what
the driver supports (or doesn't) can be found in the description of
patch #3.
The code is based on the public S805 (Meson8b) and S905 (GXBB)
datasheets, as well as by reading (various versions of) the vendor
driver and by inspecting the registers on the vendor kernels of my
testing-hardware.
Typical use-cases for the ADC on the Meson GX SoCs are:
- adc-keys ("ADC attached resistor ladder buttons")
- SoC temperature measurement (not supported by this driver yet as
the system firmware does this already and provides the values via the
SCPI protocol)
- "version-strapping" (different resistor values are used to indicate
the board-revision)
- and of course typical ADC measurements
Martin Blumenstingl (4):
Documentation: dt-bindings: add the Amlogic Meson SAR ADC
documentation
clk: gxbb: add the SAR ADC clocks and expose them
iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
ARM64: dts: meson: meson-gx: add the SAR ADC
.../bindings/iio/adc/amlogic,meson-saradc.txt | 31 +
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 +
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 +
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 +
drivers/clk/meson/gxbb.c | 48 ++
drivers/clk/meson/gxbb.h | 9 +-
drivers/iio/adc/Kconfig | 12 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/meson_saradc.c | 860 +++++++++++++++++++++
include/dt-bindings/clock/gxbb-clkc.h | 4 +
10 files changed, 990 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
create mode 100644 drivers/iio/adc/meson_saradc.c
--
2.11.0
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH 0/4] Amlogic Meson SAR ADC support
@ 2017-01-11 17:43 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-11 17:43 UTC (permalink / raw)
To: jic23, knaack.h, lars, pmeerw, robh+dt, mark.rutland, khilman,
linux-iio, devicetree, linux-amlogic, linux-clk
Cc: carlo, catalin.marinas, will.deacon, mturquette, sboyd,
narmstrong, linux-arm-kernel, Martin Blumenstingl
This series add support for the SAR ADC on Amlogic Meson GXBB, GXL and
GXM SoCs.
The hardware on GXBB provides 10-bit ADC results, while GXL and GXM are
providing 12-bit results. Support for older SoCs (Meson8b and Meson8)
can be added with little effort, most of which is testing I guess (I
don't have any pre-GXBB hardware so I can't say).
A new set of clocks had to be added to the GXBB clock controller (used
by the GXBB/GXL/GXM SoCs) which are required to get the ADC working.
The ADC itself can sample multiple channels at the same time and allows
capturing multiple samples (which can be used for filtering/averaging).
The ADC results are stored inside a FIFO register. More details on what
the driver supports (or doesn't) can be found in the description of
patch #3.
The code is based on the public S805 (Meson8b) and S905 (GXBB)
datasheets, as well as by reading (various versions of) the vendor
driver and by inspecting the registers on the vendor kernels of my
testing-hardware.
Typical use-cases for the ADC on the Meson GX SoCs are:
- adc-keys ("ADC attached resistor ladder buttons")
- SoC temperature measurement (not supported by this driver yet as
the system firmware does this already and provides the values via the
SCPI protocol)
- "version-strapping" (different resistor values are used to indicate
the board-revision)
- and of course typical ADC measurements
Martin Blumenstingl (4):
Documentation: dt-bindings: add the Amlogic Meson SAR ADC
documentation
clk: gxbb: add the SAR ADC clocks and expose them
iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
ARM64: dts: meson: meson-gx: add the SAR ADC
.../bindings/iio/adc/amlogic,meson-saradc.txt | 31 +
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 +
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 +
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 +
drivers/clk/meson/gxbb.c | 48 ++
drivers/clk/meson/gxbb.h | 9 +-
drivers/iio/adc/Kconfig | 12 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/meson_saradc.c | 860 +++++++++++++++++++++
include/dt-bindings/clock/gxbb-clkc.h | 4 +
10 files changed, 990 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
create mode 100644 drivers/iio/adc/meson_saradc.c
--
2.11.0
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH 0/4] Amlogic Meson SAR ADC support
@ 2017-01-11 17:43 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-11 17:43 UTC (permalink / raw)
To: linux-arm-kernel
This series add support for the SAR ADC on Amlogic Meson GXBB, GXL and
GXM SoCs.
The hardware on GXBB provides 10-bit ADC results, while GXL and GXM are
providing 12-bit results. Support for older SoCs (Meson8b and Meson8)
can be added with little effort, most of which is testing I guess (I
don't have any pre-GXBB hardware so I can't say).
A new set of clocks had to be added to the GXBB clock controller (used
by the GXBB/GXL/GXM SoCs) which are required to get the ADC working.
The ADC itself can sample multiple channels at the same time and allows
capturing multiple samples (which can be used for filtering/averaging).
The ADC results are stored inside a FIFO register. More details on what
the driver supports (or doesn't) can be found in the description of
patch #3.
The code is based on the public S805 (Meson8b) and S905 (GXBB)
datasheets, as well as by reading (various versions of) the vendor
driver and by inspecting the registers on the vendor kernels of my
testing-hardware.
Typical use-cases for the ADC on the Meson GX SoCs are:
- adc-keys ("ADC attached resistor ladder buttons")
- SoC temperature measurement (not supported by this driver yet as
the system firmware does this already and provides the values via the
SCPI protocol)
- "version-strapping" (different resistor values are used to indicate
the board-revision)
- and of course typical ADC measurements
Martin Blumenstingl (4):
Documentation: dt-bindings: add the Amlogic Meson SAR ADC
documentation
clk: gxbb: add the SAR ADC clocks and expose them
iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
ARM64: dts: meson: meson-gx: add the SAR ADC
.../bindings/iio/adc/amlogic,meson-saradc.txt | 31 +
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 +
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 +
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 +
drivers/clk/meson/gxbb.c | 48 ++
drivers/clk/meson/gxbb.h | 9 +-
drivers/iio/adc/Kconfig | 12 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/meson_saradc.c | 860 +++++++++++++++++++++
include/dt-bindings/clock/gxbb-clkc.h | 4 +
10 files changed, 990 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
create mode 100644 drivers/iio/adc/meson_saradc.c
--
2.11.0
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH 0/4] Amlogic Meson SAR ADC support
@ 2017-01-11 17:43 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-11 17:43 UTC (permalink / raw)
To: linus-amlogic
This series add support for the SAR ADC on Amlogic Meson GXBB, GXL and
GXM SoCs.
The hardware on GXBB provides 10-bit ADC results, while GXL and GXM are
providing 12-bit results. Support for older SoCs (Meson8b and Meson8)
can be added with little effort, most of which is testing I guess (I
don't have any pre-GXBB hardware so I can't say).
A new set of clocks had to be added to the GXBB clock controller (used
by the GXBB/GXL/GXM SoCs) which are required to get the ADC working.
The ADC itself can sample multiple channels at the same time and allows
capturing multiple samples (which can be used for filtering/averaging).
The ADC results are stored inside a FIFO register. More details on what
the driver supports (or doesn't) can be found in the description of
patch #3.
The code is based on the public S805 (Meson8b) and S905 (GXBB)
datasheets, as well as by reading (various versions of) the vendor
driver and by inspecting the registers on the vendor kernels of my
testing-hardware.
Typical use-cases for the ADC on the Meson GX SoCs are:
- adc-keys ("ADC attached resistor ladder buttons")
- SoC temperature measurement (not supported by this driver yet as
the system firmware does this already and provides the values via the
SCPI protocol)
- "version-strapping" (different resistor values are used to indicate
the board-revision)
- and of course typical ADC measurements
Martin Blumenstingl (4):
Documentation: dt-bindings: add the Amlogic Meson SAR ADC
documentation
clk: gxbb: add the SAR ADC clocks and expose them
iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
ARM64: dts: meson: meson-gx: add the SAR ADC
.../bindings/iio/adc/amlogic,meson-saradc.txt | 31 +
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 +
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 +
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 +
drivers/clk/meson/gxbb.c | 48 ++
drivers/clk/meson/gxbb.h | 9 +-
drivers/iio/adc/Kconfig | 12 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/meson_saradc.c | 860 +++++++++++++++++++++
include/dt-bindings/clock/gxbb-clkc.h | 4 +
10 files changed, 990 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
create mode 100644 drivers/iio/adc/meson_saradc.c
--
2.11.0
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
2017-01-11 17:43 ` Martin Blumenstingl
(?)
(?)
@ 2017-01-11 17:43 ` Martin Blumenstingl
-1 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-11 17:43 UTC (permalink / raw)
To: jic23-DgEjT+Ai2ygdnm+yROfE0A, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
khilman-rdvid1DuHRBWk0Htik3J/w, linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-clk-u79uwXL29TY76Z2rM5mHXA
Cc: carlo-KA+7E9HrN00dnm+yROfE0A, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, mturquette-rdvid1DuHRBWk0Htik3J/w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, narmstrong-rdvid1DuHRBWk0Htik3J/w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Martin Blumenstingl
This adds the devicetree binding documentation for the SAR ADC found in
Amlogic Meson SoCs.
Currently only the GXBB, GXL and GXM SoCs are supported.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
.../bindings/iio/adc/amlogic,meson-saradc.txt | 31 ++++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
new file mode 100644
index 000000000000..9a0bec7afc63
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
@@ -0,0 +1,31 @@
+* Amlogic Meson SAR (Successive Approximation Register) A/D converter
+
+Required properties:
+- compatible: depending on the SoC this should be one of:
+ - "amlogic,meson-gxbb-saradc" for GXBB
+ - "amlogic,meson-gxl-saradc" for GXL and GXM
+ along with the generic "amlogic,meson-saradc"
+- reg: the physical base address and length of the registers
+- clocks: phandle and clock identifier (see clock-names)
+- clock-names: mandatory clocks:
+ - "clkin" for the reference clock (typically XTAL)
+ - "core" for the SAR ADC core clock
+ optional clocks:
+ - "sana" for the analog clock
+ - "adc_clk" for the ADC (sampling) clock
+ - "adc_sel" for the ADC (sampling) clock mux
+- vref-supply: the regulator supply for the ADC reference voltage
+- #io-channel-cells: must be 1, see ../iio-bindings.txt
+
+Example:
+ saradc: adc@8680 {
+ compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
+ #io-channel-cells = <1>;
+ reg = <0x0 0x8680 0x0 0x34>;
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+ };
--
2.11.0
--
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^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
@ 2017-01-11 17:43 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-11 17:43 UTC (permalink / raw)
To: jic23, knaack.h, lars, pmeerw, robh+dt, mark.rutland, khilman,
linux-iio, devicetree, linux-amlogic, linux-clk
Cc: carlo, catalin.marinas, will.deacon, mturquette, sboyd,
narmstrong, linux-arm-kernel, Martin Blumenstingl
This adds the devicetree binding documentation for the SAR ADC found in
Amlogic Meson SoCs.
Currently only the GXBB, GXL and GXM SoCs are supported.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
.../bindings/iio/adc/amlogic,meson-saradc.txt | 31 ++++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
new file mode 100644
index 000000000000..9a0bec7afc63
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
@@ -0,0 +1,31 @@
+* Amlogic Meson SAR (Successive Approximation Register) A/D converter
+
+Required properties:
+- compatible: depending on the SoC this should be one of:
+ - "amlogic,meson-gxbb-saradc" for GXBB
+ - "amlogic,meson-gxl-saradc" for GXL and GXM
+ along with the generic "amlogic,meson-saradc"
+- reg: the physical base address and length of the registers
+- clocks: phandle and clock identifier (see clock-names)
+- clock-names: mandatory clocks:
+ - "clkin" for the reference clock (typically XTAL)
+ - "core" for the SAR ADC core clock
+ optional clocks:
+ - "sana" for the analog clock
+ - "adc_clk" for the ADC (sampling) clock
+ - "adc_sel" for the ADC (sampling) clock mux
+- vref-supply: the regulator supply for the ADC reference voltage
+- #io-channel-cells: must be 1, see ../iio-bindings.txt
+
+Example:
+ saradc: adc@8680 {
+ compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
+ #io-channel-cells = <1>;
+ reg = <0x0 0x8680 0x0 0x34>;
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+ };
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
@ 2017-01-11 17:43 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-11 17:43 UTC (permalink / raw)
To: linux-arm-kernel
This adds the devicetree binding documentation for the SAR ADC found in
Amlogic Meson SoCs.
Currently only the GXBB, GXL and GXM SoCs are supported.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
.../bindings/iio/adc/amlogic,meson-saradc.txt | 31 ++++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
new file mode 100644
index 000000000000..9a0bec7afc63
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
@@ -0,0 +1,31 @@
+* Amlogic Meson SAR (Successive Approximation Register) A/D converter
+
+Required properties:
+- compatible: depending on the SoC this should be one of:
+ - "amlogic,meson-gxbb-saradc" for GXBB
+ - "amlogic,meson-gxl-saradc" for GXL and GXM
+ along with the generic "amlogic,meson-saradc"
+- reg: the physical base address and length of the registers
+- clocks: phandle and clock identifier (see clock-names)
+- clock-names: mandatory clocks:
+ - "clkin" for the reference clock (typically XTAL)
+ - "core" for the SAR ADC core clock
+ optional clocks:
+ - "sana" for the analog clock
+ - "adc_clk" for the ADC (sampling) clock
+ - "adc_sel" for the ADC (sampling) clock mux
+- vref-supply: the regulator supply for the ADC reference voltage
+- #io-channel-cells: must be 1, see ../iio-bindings.txt
+
+Example:
+ saradc: adc at 8680 {
+ compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
+ #io-channel-cells = <1>;
+ reg = <0x0 0x8680 0x0 0x34>;
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+ };
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
@ 2017-01-11 17:43 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-11 17:43 UTC (permalink / raw)
To: linus-amlogic
This adds the devicetree binding documentation for the SAR ADC found in
Amlogic Meson SoCs.
Currently only the GXBB, GXL and GXM SoCs are supported.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
.../bindings/iio/adc/amlogic,meson-saradc.txt | 31 ++++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
new file mode 100644
index 000000000000..9a0bec7afc63
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
@@ -0,0 +1,31 @@
+* Amlogic Meson SAR (Successive Approximation Register) A/D converter
+
+Required properties:
+- compatible: depending on the SoC this should be one of:
+ - "amlogic,meson-gxbb-saradc" for GXBB
+ - "amlogic,meson-gxl-saradc" for GXL and GXM
+ along with the generic "amlogic,meson-saradc"
+- reg: the physical base address and length of the registers
+- clocks: phandle and clock identifier (see clock-names)
+- clock-names: mandatory clocks:
+ - "clkin" for the reference clock (typically XTAL)
+ - "core" for the SAR ADC core clock
+ optional clocks:
+ - "sana" for the analog clock
+ - "adc_clk" for the ADC (sampling) clock
+ - "adc_sel" for the ADC (sampling) clock mux
+- vref-supply: the regulator supply for the ADC reference voltage
+- #io-channel-cells: must be 1, see ../iio-bindings.txt
+
+Example:
+ saradc: adc at 8680 {
+ compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
+ #io-channel-cells = <1>;
+ reg = <0x0 0x8680 0x0 0x34>;
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+ };
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH 2/4] clk: gxbb: add the SAR ADC clocks and expose them
2017-01-11 17:43 ` Martin Blumenstingl
(?)
(?)
@ 2017-01-11 17:43 ` Martin Blumenstingl
-1 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-11 17:43 UTC (permalink / raw)
To: jic23-DgEjT+Ai2ygdnm+yROfE0A, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
khilman-rdvid1DuHRBWk0Htik3J/w, linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-clk-u79uwXL29TY76Z2rM5mHXA
Cc: carlo-KA+7E9HrN00dnm+yROfE0A, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, mturquette-rdvid1DuHRBWk0Htik3J/w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, narmstrong-rdvid1DuHRBWk0Htik3J/w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Martin Blumenstingl
The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
- a mux clock to choose between different ADC reference clocks (this is
2-bit wide, but the datasheet only lists the parents for the first
bit)
- a divider for the input/reference clock
- a gate which enables the ADC clock
Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
CLKID_SANA (which seems to enable the analog inputs, but unfortunately
there is no documentation for this - we just mimic what the vendor
driver does).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
drivers/clk/meson/gxbb.c | 48 +++++++++++++++++++++++++++++++++++
drivers/clk/meson/gxbb.h | 9 ++++---
include/dt-bindings/clock/gxbb-clkc.h | 4 +++
3 files changed, 58 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 9d9af446bafc..1c1ec137a3cc 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -564,6 +564,46 @@ static struct clk_gate gxbb_clk81 = {
},
};
+static struct clk_mux gxbb_sar_adc_clk_sel = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .mask = 0x3,
+ .shift = 9,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk_sel",
+ .ops = &clk_mux_ops,
+ /* NOTE: The datasheet doesn't list the parents for bit 10 */
+ .parent_names = (const char *[]){ "xtal", "clk81", },
+ .num_parents = 2,
+ },
+};
+
+static struct clk_divider gxbb_sar_adc_clk_div = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .shift = 0,
+ .width = 8,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk_div",
+ .ops = &clk_divider_ops,
+ .parent_names = (const char *[]){ "sar_adc_clk_sel" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_gate gxbb_sar_adc_clk = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .bit_idx = 8,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk",
+ .ops = &clk_gate_ops,
+ .parent_names = (const char *[]){ "sar_adc_clk_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
/* Everything Else (EE) domain gates */
static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -754,6 +794,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
[CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
[CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
[CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
+ [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
+ [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
+ [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
},
.num = NR_CLKS,
};
@@ -856,6 +899,7 @@ static struct clk_gate *gxbb_clk_gates[] = {
&gxbb_emmc_a,
&gxbb_emmc_b,
&gxbb_emmc_c,
+ &gxbb_sar_adc_clk,
};
static int gxbb_clkc_probe(struct platform_device *pdev)
@@ -888,6 +932,10 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
gxbb_mpeg_clk_sel.reg = clk_base + (u64)gxbb_mpeg_clk_sel.reg;
gxbb_mpeg_clk_div.reg = clk_base + (u64)gxbb_mpeg_clk_div.reg;
+ /* Populate the base address for the SAR ADC clks */
+ gxbb_sar_adc_clk_sel.reg = clk_base + (u64)gxbb_sar_adc_clk_sel.reg;
+ gxbb_sar_adc_clk_div.reg = clk_base + (u64)gxbb_sar_adc_clk_div.reg;
+
/* Populate base address for gates */
for (i = 0; i < ARRAY_SIZE(gxbb_clk_gates); i++)
gxbb_clk_gates[i]->reg = clk_base +
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 0252939ba58f..d90052d74abd 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -191,7 +191,7 @@
#define CLKID_PERIPHS 20
#define CLKID_SPICC 21
/* CLKID_I2C */
-#define CLKID_SAR_ADC 23
+/* #define CLKID_SAR_ADC */
#define CLKID_SMART_CARD 24
#define CLKID_RNG0 25
#define CLKID_UART0 26
@@ -237,7 +237,7 @@
#define CLKID_MMC_PCLK 66
#define CLKID_DVIN 67
#define CLKID_UART2 68
-#define CLKID_SANA 69
+/* #define CLKID_SANA */
#define CLKID_VPU_INTR 70
#define CLKID_SEC_AHB_AHB3_BRIDGE 71
#define CLKID_CLK81_A53 72
@@ -265,8 +265,11 @@
/* CLKID_SD_EMMC_A */
/* CLKID_SD_EMMC_B */
/* CLKID_SD_EMMC_C */
+/* CLKID_SAR_ADC_CLK */
+/* CLKID_SAR_ADC_SEL */
+#define CLKID_SAR_ADC_DIV 99
-#define NR_CLKS 97
+#define NR_CLKS 100
/* include the CLKIDs that have been made part of the stable DT binding */
#include <dt-bindings/clock/gxbb-clkc.h>
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index baade6f429d0..c2e93676010d 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -14,15 +14,19 @@
#define CLKID_MPLL2 15
#define CLKID_SPI 34
#define CLKID_I2C 22
+#define CLKID_SAR_ADC 23
#define CLKID_ETH 36
#define CLKID_USB0 50
#define CLKID_USB1 51
#define CLKID_USB 55
#define CLKID_USB1_DDR_BRIDGE 64
#define CLKID_USB0_DDR_BRIDGE 65
+#define CLKID_SANA 69
#define CLKID_AO_I2C 93
#define CLKID_SD_EMMC_A 94
#define CLKID_SD_EMMC_B 95
#define CLKID_SD_EMMC_C 96
+#define CLKID_SAR_ADC_CLK 97
+#define CLKID_SAR_ADC_SEL 98
#endif /* __GXBB_CLKC_H */
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH 2/4] clk: gxbb: add the SAR ADC clocks and expose them
@ 2017-01-11 17:43 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-11 17:43 UTC (permalink / raw)
To: jic23, knaack.h, lars, pmeerw, robh+dt, mark.rutland, khilman,
linux-iio, devicetree, linux-amlogic, linux-clk
Cc: carlo, catalin.marinas, will.deacon, mturquette, sboyd,
narmstrong, linux-arm-kernel, Martin Blumenstingl
The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
- a mux clock to choose between different ADC reference clocks (this is
2-bit wide, but the datasheet only lists the parents for the first
bit)
- a divider for the input/reference clock
- a gate which enables the ADC clock
Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
CLKID_SANA (which seems to enable the analog inputs, but unfortunately
there is no documentation for this - we just mimic what the vendor
driver does).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/clk/meson/gxbb.c | 48 +++++++++++++++++++++++++++++++++++
drivers/clk/meson/gxbb.h | 9 ++++---
include/dt-bindings/clock/gxbb-clkc.h | 4 +++
3 files changed, 58 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 9d9af446bafc..1c1ec137a3cc 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -564,6 +564,46 @@ static struct clk_gate gxbb_clk81 = {
},
};
+static struct clk_mux gxbb_sar_adc_clk_sel = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .mask = 0x3,
+ .shift = 9,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk_sel",
+ .ops = &clk_mux_ops,
+ /* NOTE: The datasheet doesn't list the parents for bit 10 */
+ .parent_names = (const char *[]){ "xtal", "clk81", },
+ .num_parents = 2,
+ },
+};
+
+static struct clk_divider gxbb_sar_adc_clk_div = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .shift = 0,
+ .width = 8,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk_div",
+ .ops = &clk_divider_ops,
+ .parent_names = (const char *[]){ "sar_adc_clk_sel" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_gate gxbb_sar_adc_clk = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .bit_idx = 8,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk",
+ .ops = &clk_gate_ops,
+ .parent_names = (const char *[]){ "sar_adc_clk_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
/* Everything Else (EE) domain gates */
static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -754,6 +794,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
[CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
[CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
[CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
+ [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
+ [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
+ [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
},
.num = NR_CLKS,
};
@@ -856,6 +899,7 @@ static struct clk_gate *gxbb_clk_gates[] = {
&gxbb_emmc_a,
&gxbb_emmc_b,
&gxbb_emmc_c,
+ &gxbb_sar_adc_clk,
};
static int gxbb_clkc_probe(struct platform_device *pdev)
@@ -888,6 +932,10 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
gxbb_mpeg_clk_sel.reg = clk_base + (u64)gxbb_mpeg_clk_sel.reg;
gxbb_mpeg_clk_div.reg = clk_base + (u64)gxbb_mpeg_clk_div.reg;
+ /* Populate the base address for the SAR ADC clks */
+ gxbb_sar_adc_clk_sel.reg = clk_base + (u64)gxbb_sar_adc_clk_sel.reg;
+ gxbb_sar_adc_clk_div.reg = clk_base + (u64)gxbb_sar_adc_clk_div.reg;
+
/* Populate base address for gates */
for (i = 0; i < ARRAY_SIZE(gxbb_clk_gates); i++)
gxbb_clk_gates[i]->reg = clk_base +
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 0252939ba58f..d90052d74abd 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -191,7 +191,7 @@
#define CLKID_PERIPHS 20
#define CLKID_SPICC 21
/* CLKID_I2C */
-#define CLKID_SAR_ADC 23
+/* #define CLKID_SAR_ADC */
#define CLKID_SMART_CARD 24
#define CLKID_RNG0 25
#define CLKID_UART0 26
@@ -237,7 +237,7 @@
#define CLKID_MMC_PCLK 66
#define CLKID_DVIN 67
#define CLKID_UART2 68
-#define CLKID_SANA 69
+/* #define CLKID_SANA */
#define CLKID_VPU_INTR 70
#define CLKID_SEC_AHB_AHB3_BRIDGE 71
#define CLKID_CLK81_A53 72
@@ -265,8 +265,11 @@
/* CLKID_SD_EMMC_A */
/* CLKID_SD_EMMC_B */
/* CLKID_SD_EMMC_C */
+/* CLKID_SAR_ADC_CLK */
+/* CLKID_SAR_ADC_SEL */
+#define CLKID_SAR_ADC_DIV 99
-#define NR_CLKS 97
+#define NR_CLKS 100
/* include the CLKIDs that have been made part of the stable DT binding */
#include <dt-bindings/clock/gxbb-clkc.h>
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index baade6f429d0..c2e93676010d 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -14,15 +14,19 @@
#define CLKID_MPLL2 15
#define CLKID_SPI 34
#define CLKID_I2C 22
+#define CLKID_SAR_ADC 23
#define CLKID_ETH 36
#define CLKID_USB0 50
#define CLKID_USB1 51
#define CLKID_USB 55
#define CLKID_USB1_DDR_BRIDGE 64
#define CLKID_USB0_DDR_BRIDGE 65
+#define CLKID_SANA 69
#define CLKID_AO_I2C 93
#define CLKID_SD_EMMC_A 94
#define CLKID_SD_EMMC_B 95
#define CLKID_SD_EMMC_C 96
+#define CLKID_SAR_ADC_CLK 97
+#define CLKID_SAR_ADC_SEL 98
#endif /* __GXBB_CLKC_H */
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH 2/4] clk: gxbb: add the SAR ADC clocks and expose them
@ 2017-01-11 17:43 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-11 17:43 UTC (permalink / raw)
To: linux-arm-kernel
The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
- a mux clock to choose between different ADC reference clocks (this is
2-bit wide, but the datasheet only lists the parents for the first
bit)
- a divider for the input/reference clock
- a gate which enables the ADC clock
Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
CLKID_SANA (which seems to enable the analog inputs, but unfortunately
there is no documentation for this - we just mimic what the vendor
driver does).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/clk/meson/gxbb.c | 48 +++++++++++++++++++++++++++++++++++
drivers/clk/meson/gxbb.h | 9 ++++---
include/dt-bindings/clock/gxbb-clkc.h | 4 +++
3 files changed, 58 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 9d9af446bafc..1c1ec137a3cc 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -564,6 +564,46 @@ static struct clk_gate gxbb_clk81 = {
},
};
+static struct clk_mux gxbb_sar_adc_clk_sel = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .mask = 0x3,
+ .shift = 9,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk_sel",
+ .ops = &clk_mux_ops,
+ /* NOTE: The datasheet doesn't list the parents for bit 10 */
+ .parent_names = (const char *[]){ "xtal", "clk81", },
+ .num_parents = 2,
+ },
+};
+
+static struct clk_divider gxbb_sar_adc_clk_div = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .shift = 0,
+ .width = 8,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk_div",
+ .ops = &clk_divider_ops,
+ .parent_names = (const char *[]){ "sar_adc_clk_sel" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_gate gxbb_sar_adc_clk = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .bit_idx = 8,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk",
+ .ops = &clk_gate_ops,
+ .parent_names = (const char *[]){ "sar_adc_clk_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
/* Everything Else (EE) domain gates */
static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -754,6 +794,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
[CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
[CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
[CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
+ [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
+ [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
+ [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
},
.num = NR_CLKS,
};
@@ -856,6 +899,7 @@ static struct clk_gate *gxbb_clk_gates[] = {
&gxbb_emmc_a,
&gxbb_emmc_b,
&gxbb_emmc_c,
+ &gxbb_sar_adc_clk,
};
static int gxbb_clkc_probe(struct platform_device *pdev)
@@ -888,6 +932,10 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
gxbb_mpeg_clk_sel.reg = clk_base + (u64)gxbb_mpeg_clk_sel.reg;
gxbb_mpeg_clk_div.reg = clk_base + (u64)gxbb_mpeg_clk_div.reg;
+ /* Populate the base address for the SAR ADC clks */
+ gxbb_sar_adc_clk_sel.reg = clk_base + (u64)gxbb_sar_adc_clk_sel.reg;
+ gxbb_sar_adc_clk_div.reg = clk_base + (u64)gxbb_sar_adc_clk_div.reg;
+
/* Populate base address for gates */
for (i = 0; i < ARRAY_SIZE(gxbb_clk_gates); i++)
gxbb_clk_gates[i]->reg = clk_base +
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 0252939ba58f..d90052d74abd 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -191,7 +191,7 @@
#define CLKID_PERIPHS 20
#define CLKID_SPICC 21
/* CLKID_I2C */
-#define CLKID_SAR_ADC 23
+/* #define CLKID_SAR_ADC */
#define CLKID_SMART_CARD 24
#define CLKID_RNG0 25
#define CLKID_UART0 26
@@ -237,7 +237,7 @@
#define CLKID_MMC_PCLK 66
#define CLKID_DVIN 67
#define CLKID_UART2 68
-#define CLKID_SANA 69
+/* #define CLKID_SANA */
#define CLKID_VPU_INTR 70
#define CLKID_SEC_AHB_AHB3_BRIDGE 71
#define CLKID_CLK81_A53 72
@@ -265,8 +265,11 @@
/* CLKID_SD_EMMC_A */
/* CLKID_SD_EMMC_B */
/* CLKID_SD_EMMC_C */
+/* CLKID_SAR_ADC_CLK */
+/* CLKID_SAR_ADC_SEL */
+#define CLKID_SAR_ADC_DIV 99
-#define NR_CLKS 97
+#define NR_CLKS 100
/* include the CLKIDs that have been made part of the stable DT binding */
#include <dt-bindings/clock/gxbb-clkc.h>
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index baade6f429d0..c2e93676010d 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -14,15 +14,19 @@
#define CLKID_MPLL2 15
#define CLKID_SPI 34
#define CLKID_I2C 22
+#define CLKID_SAR_ADC 23
#define CLKID_ETH 36
#define CLKID_USB0 50
#define CLKID_USB1 51
#define CLKID_USB 55
#define CLKID_USB1_DDR_BRIDGE 64
#define CLKID_USB0_DDR_BRIDGE 65
+#define CLKID_SANA 69
#define CLKID_AO_I2C 93
#define CLKID_SD_EMMC_A 94
#define CLKID_SD_EMMC_B 95
#define CLKID_SD_EMMC_C 96
+#define CLKID_SAR_ADC_CLK 97
+#define CLKID_SAR_ADC_SEL 98
#endif /* __GXBB_CLKC_H */
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH 2/4] clk: gxbb: add the SAR ADC clocks and expose them
@ 2017-01-11 17:43 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-11 17:43 UTC (permalink / raw)
To: linus-amlogic
The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
- a mux clock to choose between different ADC reference clocks (this is
2-bit wide, but the datasheet only lists the parents for the first
bit)
- a divider for the input/reference clock
- a gate which enables the ADC clock
Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
CLKID_SANA (which seems to enable the analog inputs, but unfortunately
there is no documentation for this - we just mimic what the vendor
driver does).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/clk/meson/gxbb.c | 48 +++++++++++++++++++++++++++++++++++
drivers/clk/meson/gxbb.h | 9 ++++---
include/dt-bindings/clock/gxbb-clkc.h | 4 +++
3 files changed, 58 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 9d9af446bafc..1c1ec137a3cc 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -564,6 +564,46 @@ static struct clk_gate gxbb_clk81 = {
},
};
+static struct clk_mux gxbb_sar_adc_clk_sel = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .mask = 0x3,
+ .shift = 9,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk_sel",
+ .ops = &clk_mux_ops,
+ /* NOTE: The datasheet doesn't list the parents for bit 10 */
+ .parent_names = (const char *[]){ "xtal", "clk81", },
+ .num_parents = 2,
+ },
+};
+
+static struct clk_divider gxbb_sar_adc_clk_div = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .shift = 0,
+ .width = 8,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk_div",
+ .ops = &clk_divider_ops,
+ .parent_names = (const char *[]){ "sar_adc_clk_sel" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_gate gxbb_sar_adc_clk = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .bit_idx = 8,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk",
+ .ops = &clk_gate_ops,
+ .parent_names = (const char *[]){ "sar_adc_clk_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
/* Everything Else (EE) domain gates */
static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -754,6 +794,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
[CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
[CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
[CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
+ [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
+ [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
+ [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
},
.num = NR_CLKS,
};
@@ -856,6 +899,7 @@ static struct clk_gate *gxbb_clk_gates[] = {
&gxbb_emmc_a,
&gxbb_emmc_b,
&gxbb_emmc_c,
+ &gxbb_sar_adc_clk,
};
static int gxbb_clkc_probe(struct platform_device *pdev)
@@ -888,6 +932,10 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
gxbb_mpeg_clk_sel.reg = clk_base + (u64)gxbb_mpeg_clk_sel.reg;
gxbb_mpeg_clk_div.reg = clk_base + (u64)gxbb_mpeg_clk_div.reg;
+ /* Populate the base address for the SAR ADC clks */
+ gxbb_sar_adc_clk_sel.reg = clk_base + (u64)gxbb_sar_adc_clk_sel.reg;
+ gxbb_sar_adc_clk_div.reg = clk_base + (u64)gxbb_sar_adc_clk_div.reg;
+
/* Populate base address for gates */
for (i = 0; i < ARRAY_SIZE(gxbb_clk_gates); i++)
gxbb_clk_gates[i]->reg = clk_base +
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 0252939ba58f..d90052d74abd 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -191,7 +191,7 @@
#define CLKID_PERIPHS 20
#define CLKID_SPICC 21
/* CLKID_I2C */
-#define CLKID_SAR_ADC 23
+/* #define CLKID_SAR_ADC */
#define CLKID_SMART_CARD 24
#define CLKID_RNG0 25
#define CLKID_UART0 26
@@ -237,7 +237,7 @@
#define CLKID_MMC_PCLK 66
#define CLKID_DVIN 67
#define CLKID_UART2 68
-#define CLKID_SANA 69
+/* #define CLKID_SANA */
#define CLKID_VPU_INTR 70
#define CLKID_SEC_AHB_AHB3_BRIDGE 71
#define CLKID_CLK81_A53 72
@@ -265,8 +265,11 @@
/* CLKID_SD_EMMC_A */
/* CLKID_SD_EMMC_B */
/* CLKID_SD_EMMC_C */
+/* CLKID_SAR_ADC_CLK */
+/* CLKID_SAR_ADC_SEL */
+#define CLKID_SAR_ADC_DIV 99
-#define NR_CLKS 97
+#define NR_CLKS 100
/* include the CLKIDs that have been made part of the stable DT binding */
#include <dt-bindings/clock/gxbb-clkc.h>
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index baade6f429d0..c2e93676010d 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -14,15 +14,19 @@
#define CLKID_MPLL2 15
#define CLKID_SPI 34
#define CLKID_I2C 22
+#define CLKID_SAR_ADC 23
#define CLKID_ETH 36
#define CLKID_USB0 50
#define CLKID_USB1 51
#define CLKID_USB 55
#define CLKID_USB1_DDR_BRIDGE 64
#define CLKID_USB0_DDR_BRIDGE 65
+#define CLKID_SANA 69
#define CLKID_AO_I2C 93
#define CLKID_SD_EMMC_A 94
#define CLKID_SD_EMMC_B 95
#define CLKID_SD_EMMC_C 96
+#define CLKID_SAR_ADC_CLK 97
+#define CLKID_SAR_ADC_SEL 98
#endif /* __GXBB_CLKC_H */
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
2017-01-11 17:43 ` Martin Blumenstingl
(?)
@ 2017-01-11 17:43 ` Martin Blumenstingl
-1 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-11 17:43 UTC (permalink / raw)
To: jic23, knaack.h, lars, pmeerw, robh+dt, mark.rutland, khilman,
linux-iio, devicetree, linux-amlogic, linux-clk
Cc: carlo, catalin.marinas, will.deacon, mturquette, sboyd,
narmstrong, linux-arm-kernel, Martin Blumenstingl
This adds support for the SAR (Successive Approximation Register) ADC
on the Amlogic Meson SoCs.
The code is based on the public S805 (Meson8b) and S905 (GXBB)
datasheets, as well as by reading (various versions of) the vendor
driver and by inspecting the registers on the vendor kernels of my
testing-hardware.
Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
The code was written to support older SoCs (Meson8 and Meson8b) as well,
but due to lack of actual testing-hardware no of_device_id was added for
these.
Two "features" from the vendor driver are currently missing:
- the vendor driver uses channel #7 for calibration (this improves the
accuracy of the results - in my tests the results were less than 3%
off without calibration compared to the vendor driver). Adding support
for this should be easy, but is not required for most applications.
- channel #6 is connected to the SoCs internal temperature sensor.
Adding support for this is probably not so easy since (based on the
u-boot sources) most SoC versions are using different registers and
algorithms for the conversion from "ADC value" to temperature.
Supported by the hardware but currently not supported by the driver:
- reading multiple channels at the same time (the hardware has a FIFO
buffer which stores multiple results)
- continuous sampling (this would require a way to enable this
individually because otherwise the ADC would be drawing power
constantly)
- interrupt support (similar to the vendor driver this new driver is
polling the results. It is unclear if the IRQ-mode is supported on
older (Meson6 or Meson8) hardware as well or if there are any errata)
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/iio/adc/Kconfig | 12 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/meson_saradc.c | 860 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 873 insertions(+)
create mode 100644 drivers/iio/adc/meson_saradc.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 9c8b558ba19e..86059b9b91bf 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -371,6 +371,18 @@ config MEN_Z188_ADC
This driver can also be built as a module. If so, the module will be
called men_z188_adc.
+config MESON_SARADC
+ tristate "Amlogic Meson SAR ADC driver"
+ default ARCH_MESON
+ depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
+ select REGMAP_MMIO
+ help
+ Say yes here to build support for the SAR ADC found in Amlogic Meson
+ SoCs.
+
+ To compile this driver as a module, choose M here: the
+ module will be called meson_saradc.
+
config MXS_LRADC
tristate "Freescale i.MX23/i.MX28 LRADC"
depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index d36c4be8d1fc..de05b9e75f8f 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
obj-$(CONFIG_MCP3422) += mcp3422.o
obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
+obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
obj-$(CONFIG_NAU7802) += nau7802.o
obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
new file mode 100644
index 000000000000..06e8ac620385
--- /dev/null
+++ b/drivers/iio/adc/meson_saradc.c
@@ -0,0 +1,860 @@
+/*
+ * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
+ *
+ * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iio/iio.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/reset.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+
+#define SAR_ADC_REG0 0x00
+ #define SAR_ADC_REG0_PANEL_DETECT BIT(31)
+ #define SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
+ #define SAR_ADC_REG0_DELTA_BUSY BIT(30)
+ #define SAR_ADC_REG0_AVG_BUSY BIT(29)
+ #define SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
+ #define SAR_ADC_REG0_FIFO_FULL BIT(27)
+ #define SAR_ADC_REG0_FIFO_EMPTY BIT(26)
+ #define SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
+ #define SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
+ #define SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
+ #define SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
+ #define SAR_ADC_REG0_SAMPLING_STOP BIT(14)
+ #define SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
+ #define SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
+ #define SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
+ #define SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
+ #define SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
+ #define SAR_ADC_REG0_SAMPLING_START BIT(2)
+ #define SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
+ #define SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
+
+#define SAR_ADC_CHAN_LIST 0x04
+ #define SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
+ #define SAR_ADC_CHAN_CHAN_ENTRY_MASK(_chan) \
+ (GENMASK(2, 0) << (_chan * 3))
+
+#define SAR_ADC_AVG_CNTL 0x08
+ #define SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
+ (16 + (_chan * 2))
+ #define SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
+ (GENMASK(17, 16) << (_chan * 2))
+ #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
+ (0 + (_chan * 2))
+ #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
+ (GENMASK(1, 0) << (_chan * 2))
+
+#define SAR_ADC_REG3 0x0c
+ #define SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
+ #define SAR_ADC_REG3_CLK_EN BIT(30)
+ #define SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
+ #define SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
+ #define SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
+ #define SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
+ #define SAR_ADC_REG3_DETECT_EN BIT(22)
+ #define SAR_ADC_REG3_ADC_EN BIT(21)
+ #define SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
+ #define SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
+ #define SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
+ #define SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
+ #define SAR_ADC_REG3_ADC_CLK_DIV_MASK GENMASK(15, 10)
+ #define SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
+ #define SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
+
+#define SAR_ADC_DELAY 0x10
+ #define SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
+ #define SAR_ADC_DELAY_BL30_BUSY BIT(15)
+ #define SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
+ #define SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
+ #define SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
+ #define SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
+
+#define SAR_ADC_LAST_RD 0x14
+ #define SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
+ #define SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
+
+#define SAR_ADC_FIFO_RD 0x18
+ #define SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
+ #define SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
+
+#define SAR_ADC_AUX_SW 0x1c
+ #define SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
+ (GENMASK(10, 8) << ((_chan - 2) * 2))
+ #define SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
+ #define SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
+ #define SAR_ADC_AUX_SW_MODE_SEL BIT(4)
+ #define SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
+ #define SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
+ #define SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
+ #define SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
+
+#define SAR_ADC_CHAN_10_SW 0x20
+ #define SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
+
+#define SAR_ADC_DETECT_IDLE_SW 0x24
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK GENMASK(25, 23)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_P_MUX BIT(22)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_N_MUX BIT(21)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YP_DRIVE_SW BIT(19)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XP_DRIVE_SW BIT(18)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YM_DRIVE_SW BIT(17)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XM_DRIVE_SW BIT(16)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK GENMASK(9, 7)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_P_MUX BIT(6)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_N_MUX BIT(5)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YP_DRIVE_SW BIT(3)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XP_DRIVE_SW BIT(2)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YM_DRIVE_SW BIT(1)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XM_DRIVE_SW BIT(0)
+
+#define SAR_ADC_DELTA_10 0x28
+ #define SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
+ #define SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
+ #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_SHIFT 16
+ #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
+ #define SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
+ #define SAR_ADC_DELTA_10_TS_C_SHIFT 11
+ #define SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
+ #define SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
+ #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_SHIFT 0
+ #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
+
+/* NOTE: registers from here are undocumented (the vendor Linux kernel driver
+ * and u-boot source served as reference). These only seem to be relevant on
+ * GXBB and newer.
+ */
+#define SAR_ADC_REG11 0x2c
+ #define SAR_ADC_REG11_BANDGAP_EN BIT(13)
+
+#define SAR_ADC_REG13 0x34
+ #define SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
+
+#define SAR_ADC_MAX_FIFO_SIZE 32
+#define SAR_ADC_NUM_CHANNELS ARRAY_SIZE(meson_saradc_iio_channels)
+#define SAR_ADC_VALUE_MASK(_priv) (BIT(_priv->resolution) - 1)
+
+#define MESON_SAR_ADC_CHAN(_chan, _type) { \
+ .type = _type, \
+ .indexed = true, \
+ .channel = _chan, \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
+ BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
+ .datasheet_name = "SAR_ADC_CH"#_chan, \
+}
+
+/* TODO: the hardware supports IIO_TEMP for channel 6 as well which is
+ * currently not supported by this driver.
+ */
+static const struct iio_chan_spec meson_saradc_iio_channels[] = {
+ MESON_SAR_ADC_CHAN(0, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(1, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(2, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(3, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(4, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(5, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(6, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(7, IIO_VOLTAGE),
+ IIO_CHAN_SOFT_TIMESTAMP(8),
+};
+
+enum meson_saradc_avg_mode {
+ NO_AVERAGING = 0x0,
+ MEAN_AVERAGING = 0x1,
+ MEDIAN_AVERAGING = 0x2,
+};
+
+enum meson_saradc_num_samples {
+ ONE_SAMPLE = 0x0,
+ TWO_SAMPLES = 0x1,
+ FOUR_SAMPLES = 0x2,
+ EIGHT_SAMPLES = 0x3,
+};
+
+enum meson_saradc_chan7_mux_sel {
+ CHAN7_MUX_VSS = 0x0,
+ CHAN7_MUX_VDD_DIV4 = 0x1,
+ CHAN7_MUX_VDD_DIV2 = 0x2,
+ CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
+ CHAN7_MUX_VDD = 0x4,
+ CHAN7_MUX_CH7_INPUT = 0x7,
+};
+
+struct meson_saradc_priv {
+ struct regmap *regmap;
+ struct clk *clkin;
+ struct clk *core_clk;
+ struct clk *sana_clk;
+ struct clk *adc_sel_clk;
+ struct clk *adc_clk;
+ struct clk_gate clk_gate;
+ struct clk *adc_div_clk;
+ struct clk_divider clk_div;
+ struct regulator *vref;
+ struct completion completion;
+ u8 resolution;
+};
+
+static const struct regmap_config meson_saradc_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = SAR_ADC_REG13,
+};
+
+static unsigned int meson_saradc_get_fifo_count(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
+
+ return FIELD_GET(SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
+}
+
+static int meson_saradc_wait_busy_clear(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int regval, timeout = 10000;
+
+ do {
+ udelay(1);
+ regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
+ } while (FIELD_GET(SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
+
+ if (timeout < 0)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static int meson_saradc_read_raw_sample(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ int *val)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0;
+
+ ret = meson_saradc_wait_busy_clear(indio_dev);
+ if (ret)
+ return ret;
+
+ regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
+
+ while (meson_saradc_get_fifo_count(indio_dev) > 0 &&
+ count < SAR_ADC_MAX_FIFO_SIZE) {
+ regmap_read(priv->regmap, SAR_ADC_FIFO_RD, ®val);
+
+ fifo_chan = FIELD_GET(SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
+ if (fifo_chan == chan->channel) {
+ fifo_val = FIELD_GET(SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK,
+ regval) & SAR_ADC_VALUE_MASK(priv);
+ sum += fifo_val;
+ count++;
+ }
+ }
+
+ if (!count)
+ return -ENOENT;
+
+ *val = sum / count;
+
+ return 0;
+}
+
+static void meson_saradc_set_averaging(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ enum meson_saradc_avg_mode mode,
+ enum meson_saradc_num_samples samples)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 val;
+
+ val = samples << SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
+ SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(chan->channel),
+ val);
+
+ val = mode << SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
+ SAR_ADC_AVG_CNTL_AVG_MODE_MASK(chan->channel), val);
+}
+
+static void meson_saradc_enable_channel(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ /* the SAR ADC engine allows sampling multiple channels at the same
+ * time. to keep it simple we're only working with one *internal*
+ * channel, which starts counting at index 0 (which means: count = 1).
+ */
+ regval = FIELD_PREP(SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
+ regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
+ SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
+
+ /* map channel index 0 to the channel which we want to read */
+ regval = FIELD_PREP(SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
+ SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), regval);
+
+ regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
+ chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
+ SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
+ regval);
+
+ regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
+ chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
+ SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
+ regval);
+
+ if (chan->channel == 6)
+ regmap_update_bits(priv->regmap, SAR_ADC_DELTA_10,
+ SAR_ADC_DELTA_10_TEMP_SEL, 0);
+}
+
+static void meson_saradc_set_channel7_mux(struct iio_dev *indio_dev,
+ enum meson_saradc_chan7_mux_sel sel)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ regval = FIELD_PREP(SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3,
+ SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
+
+ usleep_range(10, 20);
+}
+
+static void meson_saradc_start_sample_engine(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
+ SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLING_START,
+ SAR_ADC_REG0_SAMPLING_START);
+}
+
+static void meson_saradc_stop_sample_engine(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLING_STOP,
+ SAR_ADC_REG0_SAMPLING_STOP);
+
+ /* wait until all modules are stopped */
+ meson_saradc_wait_busy_clear(indio_dev);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
+}
+
+static void meson_saradc_lock(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int val;
+
+ mutex_lock(&indio_dev->mlock);
+
+ /* prevent BL30 from using the SAR ADC while we are using it */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_KERNEL_BUSY,
+ SAR_ADC_DELAY_KERNEL_BUSY);
+
+ /* wait until BL30 releases it's lock (so we can use the SAR ADC) */
+ do {
+ udelay(1);
+ regmap_read(priv->regmap, SAR_ADC_DELAY, &val);
+ } while (val & SAR_ADC_DELAY_BL30_BUSY);
+}
+
+static void meson_saradc_unlock(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ /* allow BL30 to use the SAR ADC again */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_KERNEL_BUSY, 0);
+
+ mutex_unlock(&indio_dev->mlock);
+}
+
+static int meson_saradc_get_sample(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ enum meson_saradc_avg_mode avg_mode,
+ enum meson_saradc_num_samples avg_samples,
+ int *val)
+{
+ int ret, tmp;
+
+ meson_saradc_lock(indio_dev);
+
+ /* clear old values from the FIFO buffer, ignoring errors */
+ meson_saradc_read_raw_sample(indio_dev, chan, &tmp);
+
+ meson_saradc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
+
+ meson_saradc_enable_channel(indio_dev, chan);
+
+ meson_saradc_start_sample_engine(indio_dev);
+ ret = meson_saradc_read_raw_sample(indio_dev, chan, val);
+ meson_saradc_stop_sample_engine(indio_dev);
+
+ meson_saradc_unlock(indio_dev);
+
+ if (ret) {
+ dev_warn(&indio_dev->dev,
+ "failed to read sample for channel %d: %d\n",
+ chan->channel, ret);
+ return ret;
+ }
+
+ return IIO_VAL_INT;
+}
+
+static int meson_saradc_iio_info_read_raw(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ int *val, int *val2, long mask)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int ret;
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ return meson_saradc_get_sample(indio_dev, chan, NO_AVERAGING,
+ ONE_SAMPLE, val);
+ break;
+
+ case IIO_CHAN_INFO_AVERAGE_RAW:
+ return meson_saradc_get_sample(indio_dev, chan, MEAN_AVERAGING,
+ EIGHT_SAMPLES, val);
+ break;
+
+ case IIO_CHAN_INFO_SCALE:
+ ret = regulator_get_voltage(priv->vref);
+ if (ret < 0) {
+ dev_err(&indio_dev->dev,
+ "failed to get vref voltage: %d\n", ret);
+ return ret;
+ }
+
+ *val = ret / 1000;
+ *val2 = priv->resolution;
+ return IIO_VAL_FRACTIONAL_LOG2;
+
+ default:
+ return -EINVAL;
+ }
+}
+
+static int meson_saradc_clk_init(struct iio_dev *indio_dev, void __iomem *base)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ struct clk_init_data init;
+ char clk_name[32];
+ const char *clk_parents[1];
+
+ snprintf(clk_name, sizeof(clk_name), "%s#adc_div",
+ of_node_full_name(indio_dev->dev.of_node));
+ init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
+ init.flags = 0;
+ init.ops = &clk_divider_ops;
+ clk_parents[0] = __clk_get_name(priv->clkin);
+ init.parent_names = clk_parents;
+ init.num_parents = 1;
+
+ priv->clk_div.reg = base + SAR_ADC_REG3;
+ priv->clk_div.shift = SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
+ priv->clk_div.width = SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
+ priv->clk_div.hw.init = &init;
+ priv->clk_div.flags = 0;
+
+ priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
+ &priv->clk_div.hw);
+ if (WARN_ON(IS_ERR(priv->adc_div_clk)))
+ return PTR_ERR(priv->adc_div_clk);
+
+ snprintf(clk_name, sizeof(clk_name), "%s#adc_en",
+ of_node_full_name(indio_dev->dev.of_node));
+ init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
+ init.flags = CLK_SET_RATE_PARENT;
+ init.ops = &clk_gate_ops;
+ clk_parents[0] = __clk_get_name(priv->adc_div_clk);
+ init.parent_names = clk_parents;
+ init.num_parents = 1;
+
+ priv->clk_gate.reg = base + SAR_ADC_REG3;
+ priv->clk_gate.bit_idx = fls(SAR_ADC_REG3_CLK_EN);
+ priv->clk_gate.hw.init = &init;
+
+ priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
+ if (WARN_ON(IS_ERR(priv->adc_clk)))
+ return PTR_ERR(priv->adc_clk);
+
+ return 0;
+}
+
+static int meson_saradc_init(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int regval, ret;
+
+ /* make sure we start at CH7 input */
+ meson_saradc_set_channel7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
+
+ regmap_read(priv->regmap, SAR_ADC_REG3, ®val);
+ if (regval & SAR_ADC_REG3_BL30_INITIALIZED) {
+ dev_info(&indio_dev->dev, "already initialized by BL30\n");
+ return 0;
+ }
+
+ dev_info(&indio_dev->dev, "initializing SAR ADC\n");
+
+ meson_saradc_stop_sample_engine(indio_dev);
+
+ /* update the channel 6 MUX to select the temperature sensor */
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
+ SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
+
+ /* disable all channels by default */
+ regmap_write(priv->regmap, SAR_ADC_CHAN_LIST, 0x0);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3,
+ SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3,
+ SAR_ADC_REG3_CNTL_USE_SC_DLY,
+ SAR_ADC_REG3_CNTL_USE_SC_DLY);
+
+ /* delay between two samples = (10+1) * 1uS */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK, 10));
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 0));
+
+ /* delay between two samples = (10+1) * 1uS */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 10));
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 1));
+
+ ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
+ if (ret) {
+ dev_err(&indio_dev->dev,
+ "failed to set adc parent to clkin\n");
+ return ret;
+ }
+
+ ret = clk_set_rate(priv->adc_clk, 1200000);
+ if (ret) {
+ dev_err(&indio_dev->dev, "failed to set adc clock rate\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int meson_saradc_hw_enable(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int ret;
+
+ meson_saradc_lock(indio_dev);
+
+ ret = regulator_enable(priv->vref);
+ if (ret < 0) {
+ dev_err(&indio_dev->dev, "failed to enable vref regulator\n");
+ goto err_vref;
+ }
+
+ ret = clk_prepare_enable(priv->core_clk);
+ if (ret) {
+ dev_err(&indio_dev->dev, "failed to enable core clk\n");
+ goto err_core_clk;
+ }
+
+ ret = clk_prepare_enable(priv->sana_clk);
+ if (ret) {
+ dev_err(&indio_dev->dev, "failed to enable sana clk\n");
+ goto err_sana_clk;
+ }
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG11,
+ SAR_ADC_REG11_BANDGAP_EN, SAR_ADC_REG11_BANDGAP_EN);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN,
+ SAR_ADC_REG3_ADC_EN);
+
+ udelay(5);
+
+ ret = clk_prepare_enable(priv->adc_clk);
+ if (ret) {
+ dev_err(&indio_dev->dev, "failed to enable adc_en clk\n");
+ goto err_adc_clk;
+ }
+
+ meson_saradc_unlock(indio_dev);
+
+ return 0;
+
+err_adc_clk:
+ clk_disable_unprepare(priv->sana_clk);
+err_sana_clk:
+ clk_disable_unprepare(priv->core_clk);
+err_core_clk:
+ regulator_disable(priv->vref);
+err_vref:
+ meson_saradc_unlock(indio_dev);
+ return ret;
+}
+
+static void meson_saradc_hw_disable(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ meson_saradc_lock(indio_dev);
+
+ clk_disable_unprepare(priv->adc_clk);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN, 0);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG11,
+ SAR_ADC_REG11_BANDGAP_EN, 0);
+
+ clk_disable_unprepare(priv->sana_clk);
+ clk_disable_unprepare(priv->core_clk);
+
+ regulator_disable(priv->vref);
+
+ meson_saradc_unlock(indio_dev);
+}
+
+static const struct iio_info meson_saradc_iio_info = {
+ .read_raw = meson_saradc_iio_info_read_raw,
+ .driver_module = THIS_MODULE,
+};
+
+static const struct of_device_id meson_saradc_of_match[] = {
+ {
+ .compatible = "amlogic,meson-gxbb-saradc",
+ .data = (void *)10,
+ }, {
+ .compatible = "amlogic,meson-gxl-saradc",
+ .data = (void *)12,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, meson_saradc_of_match);
+
+static int meson_saradc_probe(struct platform_device *pdev)
+{
+ struct meson_saradc_priv *priv;
+ struct iio_dev *indio_dev;
+ struct resource *res;
+ void __iomem *base;
+ const struct of_device_id *match;
+ int ret;
+
+ indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
+ if (!indio_dev) {
+ dev_err(&pdev->dev, "failed allocating iio device\n");
+ return -ENOMEM;
+ }
+
+ priv = iio_priv(indio_dev);
+
+ match = of_match_device(meson_saradc_of_match, &pdev->dev);
+ priv->resolution = (unsigned long)match->data;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
+ &meson_saradc_regmap_config);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+ init_completion(&priv->completion);
+
+ priv->clkin = devm_clk_get(&pdev->dev, "clkin");
+ if (IS_ERR(priv->clkin)) {
+ dev_err(&pdev->dev, "failed to get clkin\n");
+ return PTR_ERR(priv->clkin);
+ }
+
+ priv->core_clk = devm_clk_get(&pdev->dev, "core");
+ if (IS_ERR(priv->core_clk)) {
+ dev_err(&pdev->dev, "failed to get core clk\n");
+ return PTR_ERR(priv->core_clk);
+ }
+
+ priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
+ if (IS_ERR(priv->sana_clk)) {
+ if (PTR_ERR(priv->sana_clk) == -ENOENT) {
+ priv->sana_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get sana clk\n");
+ return PTR_ERR(priv->sana_clk);
+ }
+ }
+
+ priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
+ if (IS_ERR(priv->adc_clk)) {
+ if (PTR_ERR(priv->adc_clk) == -ENOENT) {
+ priv->adc_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get adc clk\n");
+ return PTR_ERR(priv->adc_clk);
+ }
+ }
+
+ priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
+ if (IS_ERR(priv->adc_sel_clk)) {
+ if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
+ priv->adc_sel_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get adc_sel clk\n");
+ return PTR_ERR(priv->adc_sel_clk);
+ }
+ }
+
+ /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
+ if (!priv->adc_clk) {
+ ret = meson_saradc_clk_init(indio_dev, base);
+ if (ret)
+ return ret;
+ }
+
+ priv->vref = devm_regulator_get(&pdev->dev, "vref");
+ if (IS_ERR(priv->vref)) {
+ dev_err(&pdev->dev, "failed to get vref regulator\n");
+ return PTR_ERR(priv->vref);
+ }
+
+ ret = meson_saradc_init(indio_dev);
+ if (ret)
+ goto err;
+
+ ret = meson_saradc_hw_enable(indio_dev);
+ if (ret)
+ goto err;
+
+ platform_set_drvdata(pdev, indio_dev);
+
+ indio_dev->name = dev_name(&pdev->dev);
+ indio_dev->dev.parent = &pdev->dev;
+ indio_dev->dev.of_node = pdev->dev.of_node;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->info = &meson_saradc_iio_info;
+
+ indio_dev->channels = meson_saradc_iio_channels;
+ indio_dev->num_channels = SAR_ADC_NUM_CHANNELS;
+
+ ret = iio_device_register(indio_dev);
+ if (ret)
+ goto err_hw;
+
+ return 0;
+
+err_hw:
+ meson_saradc_hw_disable(indio_dev);
+err:
+ return ret;
+}
+
+static int meson_saradc_remove(struct platform_device *pdev)
+{
+ struct iio_dev *indio_dev = platform_get_drvdata(pdev);
+
+ meson_saradc_hw_disable(indio_dev);
+ iio_device_unregister(indio_dev);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int meson_saradc_suspend(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+
+ meson_saradc_hw_disable(indio_dev);
+
+ return 0;
+}
+
+static int meson_saradc_resume(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+
+ return meson_saradc_hw_enable(indio_dev);
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(meson_saradc_pm_ops,
+ meson_saradc_suspend, meson_saradc_resume);
+
+static struct platform_driver meson_saradc_driver = {
+ .probe = meson_saradc_probe,
+ .remove = meson_saradc_remove,
+ .driver = {
+ .name = "meson-saradc",
+ .of_match_table = meson_saradc_of_match,
+ .pm = &meson_saradc_pm_ops,
+ },
+};
+
+module_platform_driver(meson_saradc_driver);
+
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
+MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
+MODULE_LICENSE("GPL v2");
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
@ 2017-01-11 17:43 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-11 17:43 UTC (permalink / raw)
To: linux-arm-kernel
This adds support for the SAR (Successive Approximation Register) ADC
on the Amlogic Meson SoCs.
The code is based on the public S805 (Meson8b) and S905 (GXBB)
datasheets, as well as by reading (various versions of) the vendor
driver and by inspecting the registers on the vendor kernels of my
testing-hardware.
Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
The code was written to support older SoCs (Meson8 and Meson8b) as well,
but due to lack of actual testing-hardware no of_device_id was added for
these.
Two "features" from the vendor driver are currently missing:
- the vendor driver uses channel #7 for calibration (this improves the
accuracy of the results - in my tests the results were less than 3%
off without calibration compared to the vendor driver). Adding support
for this should be easy, but is not required for most applications.
- channel #6 is connected to the SoCs internal temperature sensor.
Adding support for this is probably not so easy since (based on the
u-boot sources) most SoC versions are using different registers and
algorithms for the conversion from "ADC value" to temperature.
Supported by the hardware but currently not supported by the driver:
- reading multiple channels at the same time (the hardware has a FIFO
buffer which stores multiple results)
- continuous sampling (this would require a way to enable this
individually because otherwise the ADC would be drawing power
constantly)
- interrupt support (similar to the vendor driver this new driver is
polling the results. It is unclear if the IRQ-mode is supported on
older (Meson6 or Meson8) hardware as well or if there are any errata)
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/iio/adc/Kconfig | 12 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/meson_saradc.c | 860 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 873 insertions(+)
create mode 100644 drivers/iio/adc/meson_saradc.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 9c8b558ba19e..86059b9b91bf 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -371,6 +371,18 @@ config MEN_Z188_ADC
This driver can also be built as a module. If so, the module will be
called men_z188_adc.
+config MESON_SARADC
+ tristate "Amlogic Meson SAR ADC driver"
+ default ARCH_MESON
+ depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
+ select REGMAP_MMIO
+ help
+ Say yes here to build support for the SAR ADC found in Amlogic Meson
+ SoCs.
+
+ To compile this driver as a module, choose M here: the
+ module will be called meson_saradc.
+
config MXS_LRADC
tristate "Freescale i.MX23/i.MX28 LRADC"
depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index d36c4be8d1fc..de05b9e75f8f 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
obj-$(CONFIG_MCP3422) += mcp3422.o
obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
+obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
obj-$(CONFIG_NAU7802) += nau7802.o
obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
new file mode 100644
index 000000000000..06e8ac620385
--- /dev/null
+++ b/drivers/iio/adc/meson_saradc.c
@@ -0,0 +1,860 @@
+/*
+ * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
+ *
+ * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iio/iio.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/reset.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+
+#define SAR_ADC_REG0 0x00
+ #define SAR_ADC_REG0_PANEL_DETECT BIT(31)
+ #define SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
+ #define SAR_ADC_REG0_DELTA_BUSY BIT(30)
+ #define SAR_ADC_REG0_AVG_BUSY BIT(29)
+ #define SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
+ #define SAR_ADC_REG0_FIFO_FULL BIT(27)
+ #define SAR_ADC_REG0_FIFO_EMPTY BIT(26)
+ #define SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
+ #define SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
+ #define SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
+ #define SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
+ #define SAR_ADC_REG0_SAMPLING_STOP BIT(14)
+ #define SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
+ #define SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
+ #define SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
+ #define SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
+ #define SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
+ #define SAR_ADC_REG0_SAMPLING_START BIT(2)
+ #define SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
+ #define SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
+
+#define SAR_ADC_CHAN_LIST 0x04
+ #define SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
+ #define SAR_ADC_CHAN_CHAN_ENTRY_MASK(_chan) \
+ (GENMASK(2, 0) << (_chan * 3))
+
+#define SAR_ADC_AVG_CNTL 0x08
+ #define SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
+ (16 + (_chan * 2))
+ #define SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
+ (GENMASK(17, 16) << (_chan * 2))
+ #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
+ (0 + (_chan * 2))
+ #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
+ (GENMASK(1, 0) << (_chan * 2))
+
+#define SAR_ADC_REG3 0x0c
+ #define SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
+ #define SAR_ADC_REG3_CLK_EN BIT(30)
+ #define SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
+ #define SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
+ #define SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
+ #define SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
+ #define SAR_ADC_REG3_DETECT_EN BIT(22)
+ #define SAR_ADC_REG3_ADC_EN BIT(21)
+ #define SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
+ #define SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
+ #define SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
+ #define SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
+ #define SAR_ADC_REG3_ADC_CLK_DIV_MASK GENMASK(15, 10)
+ #define SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
+ #define SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
+
+#define SAR_ADC_DELAY 0x10
+ #define SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
+ #define SAR_ADC_DELAY_BL30_BUSY BIT(15)
+ #define SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
+ #define SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
+ #define SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
+ #define SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
+
+#define SAR_ADC_LAST_RD 0x14
+ #define SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
+ #define SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
+
+#define SAR_ADC_FIFO_RD 0x18
+ #define SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
+ #define SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
+
+#define SAR_ADC_AUX_SW 0x1c
+ #define SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
+ (GENMASK(10, 8) << ((_chan - 2) * 2))
+ #define SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
+ #define SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
+ #define SAR_ADC_AUX_SW_MODE_SEL BIT(4)
+ #define SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
+ #define SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
+ #define SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
+ #define SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
+
+#define SAR_ADC_CHAN_10_SW 0x20
+ #define SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
+
+#define SAR_ADC_DETECT_IDLE_SW 0x24
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK GENMASK(25, 23)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_P_MUX BIT(22)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_N_MUX BIT(21)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YP_DRIVE_SW BIT(19)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XP_DRIVE_SW BIT(18)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YM_DRIVE_SW BIT(17)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XM_DRIVE_SW BIT(16)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK GENMASK(9, 7)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_P_MUX BIT(6)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_N_MUX BIT(5)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YP_DRIVE_SW BIT(3)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XP_DRIVE_SW BIT(2)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YM_DRIVE_SW BIT(1)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XM_DRIVE_SW BIT(0)
+
+#define SAR_ADC_DELTA_10 0x28
+ #define SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
+ #define SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
+ #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_SHIFT 16
+ #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
+ #define SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
+ #define SAR_ADC_DELTA_10_TS_C_SHIFT 11
+ #define SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
+ #define SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
+ #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_SHIFT 0
+ #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
+
+/* NOTE: registers from here are undocumented (the vendor Linux kernel driver
+ * and u-boot source served as reference). These only seem to be relevant on
+ * GXBB and newer.
+ */
+#define SAR_ADC_REG11 0x2c
+ #define SAR_ADC_REG11_BANDGAP_EN BIT(13)
+
+#define SAR_ADC_REG13 0x34
+ #define SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
+
+#define SAR_ADC_MAX_FIFO_SIZE 32
+#define SAR_ADC_NUM_CHANNELS ARRAY_SIZE(meson_saradc_iio_channels)
+#define SAR_ADC_VALUE_MASK(_priv) (BIT(_priv->resolution) - 1)
+
+#define MESON_SAR_ADC_CHAN(_chan, _type) { \
+ .type = _type, \
+ .indexed = true, \
+ .channel = _chan, \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
+ BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
+ .datasheet_name = "SAR_ADC_CH"#_chan, \
+}
+
+/* TODO: the hardware supports IIO_TEMP for channel 6 as well which is
+ * currently not supported by this driver.
+ */
+static const struct iio_chan_spec meson_saradc_iio_channels[] = {
+ MESON_SAR_ADC_CHAN(0, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(1, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(2, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(3, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(4, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(5, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(6, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(7, IIO_VOLTAGE),
+ IIO_CHAN_SOFT_TIMESTAMP(8),
+};
+
+enum meson_saradc_avg_mode {
+ NO_AVERAGING = 0x0,
+ MEAN_AVERAGING = 0x1,
+ MEDIAN_AVERAGING = 0x2,
+};
+
+enum meson_saradc_num_samples {
+ ONE_SAMPLE = 0x0,
+ TWO_SAMPLES = 0x1,
+ FOUR_SAMPLES = 0x2,
+ EIGHT_SAMPLES = 0x3,
+};
+
+enum meson_saradc_chan7_mux_sel {
+ CHAN7_MUX_VSS = 0x0,
+ CHAN7_MUX_VDD_DIV4 = 0x1,
+ CHAN7_MUX_VDD_DIV2 = 0x2,
+ CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
+ CHAN7_MUX_VDD = 0x4,
+ CHAN7_MUX_CH7_INPUT = 0x7,
+};
+
+struct meson_saradc_priv {
+ struct regmap *regmap;
+ struct clk *clkin;
+ struct clk *core_clk;
+ struct clk *sana_clk;
+ struct clk *adc_sel_clk;
+ struct clk *adc_clk;
+ struct clk_gate clk_gate;
+ struct clk *adc_div_clk;
+ struct clk_divider clk_div;
+ struct regulator *vref;
+ struct completion completion;
+ u8 resolution;
+};
+
+static const struct regmap_config meson_saradc_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = SAR_ADC_REG13,
+};
+
+static unsigned int meson_saradc_get_fifo_count(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
+
+ return FIELD_GET(SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
+}
+
+static int meson_saradc_wait_busy_clear(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int regval, timeout = 10000;
+
+ do {
+ udelay(1);
+ regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
+ } while (FIELD_GET(SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
+
+ if (timeout < 0)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static int meson_saradc_read_raw_sample(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ int *val)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0;
+
+ ret = meson_saradc_wait_busy_clear(indio_dev);
+ if (ret)
+ return ret;
+
+ regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
+
+ while (meson_saradc_get_fifo_count(indio_dev) > 0 &&
+ count < SAR_ADC_MAX_FIFO_SIZE) {
+ regmap_read(priv->regmap, SAR_ADC_FIFO_RD, ®val);
+
+ fifo_chan = FIELD_GET(SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
+ if (fifo_chan == chan->channel) {
+ fifo_val = FIELD_GET(SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK,
+ regval) & SAR_ADC_VALUE_MASK(priv);
+ sum += fifo_val;
+ count++;
+ }
+ }
+
+ if (!count)
+ return -ENOENT;
+
+ *val = sum / count;
+
+ return 0;
+}
+
+static void meson_saradc_set_averaging(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ enum meson_saradc_avg_mode mode,
+ enum meson_saradc_num_samples samples)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 val;
+
+ val = samples << SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
+ SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(chan->channel),
+ val);
+
+ val = mode << SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
+ SAR_ADC_AVG_CNTL_AVG_MODE_MASK(chan->channel), val);
+}
+
+static void meson_saradc_enable_channel(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ /* the SAR ADC engine allows sampling multiple channels at the same
+ * time. to keep it simple we're only working with one *internal*
+ * channel, which starts counting at index 0 (which means: count = 1).
+ */
+ regval = FIELD_PREP(SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
+ regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
+ SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
+
+ /* map channel index 0 to the channel which we want to read */
+ regval = FIELD_PREP(SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
+ SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), regval);
+
+ regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
+ chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
+ SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
+ regval);
+
+ regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
+ chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
+ SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
+ regval);
+
+ if (chan->channel == 6)
+ regmap_update_bits(priv->regmap, SAR_ADC_DELTA_10,
+ SAR_ADC_DELTA_10_TEMP_SEL, 0);
+}
+
+static void meson_saradc_set_channel7_mux(struct iio_dev *indio_dev,
+ enum meson_saradc_chan7_mux_sel sel)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ regval = FIELD_PREP(SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3,
+ SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
+
+ usleep_range(10, 20);
+}
+
+static void meson_saradc_start_sample_engine(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
+ SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLING_START,
+ SAR_ADC_REG0_SAMPLING_START);
+}
+
+static void meson_saradc_stop_sample_engine(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLING_STOP,
+ SAR_ADC_REG0_SAMPLING_STOP);
+
+ /* wait until all modules are stopped */
+ meson_saradc_wait_busy_clear(indio_dev);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
+}
+
+static void meson_saradc_lock(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int val;
+
+ mutex_lock(&indio_dev->mlock);
+
+ /* prevent BL30 from using the SAR ADC while we are using it */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_KERNEL_BUSY,
+ SAR_ADC_DELAY_KERNEL_BUSY);
+
+ /* wait until BL30 releases it's lock (so we can use the SAR ADC) */
+ do {
+ udelay(1);
+ regmap_read(priv->regmap, SAR_ADC_DELAY, &val);
+ } while (val & SAR_ADC_DELAY_BL30_BUSY);
+}
+
+static void meson_saradc_unlock(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ /* allow BL30 to use the SAR ADC again */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_KERNEL_BUSY, 0);
+
+ mutex_unlock(&indio_dev->mlock);
+}
+
+static int meson_saradc_get_sample(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ enum meson_saradc_avg_mode avg_mode,
+ enum meson_saradc_num_samples avg_samples,
+ int *val)
+{
+ int ret, tmp;
+
+ meson_saradc_lock(indio_dev);
+
+ /* clear old values from the FIFO buffer, ignoring errors */
+ meson_saradc_read_raw_sample(indio_dev, chan, &tmp);
+
+ meson_saradc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
+
+ meson_saradc_enable_channel(indio_dev, chan);
+
+ meson_saradc_start_sample_engine(indio_dev);
+ ret = meson_saradc_read_raw_sample(indio_dev, chan, val);
+ meson_saradc_stop_sample_engine(indio_dev);
+
+ meson_saradc_unlock(indio_dev);
+
+ if (ret) {
+ dev_warn(&indio_dev->dev,
+ "failed to read sample for channel %d: %d\n",
+ chan->channel, ret);
+ return ret;
+ }
+
+ return IIO_VAL_INT;
+}
+
+static int meson_saradc_iio_info_read_raw(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ int *val, int *val2, long mask)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int ret;
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ return meson_saradc_get_sample(indio_dev, chan, NO_AVERAGING,
+ ONE_SAMPLE, val);
+ break;
+
+ case IIO_CHAN_INFO_AVERAGE_RAW:
+ return meson_saradc_get_sample(indio_dev, chan, MEAN_AVERAGING,
+ EIGHT_SAMPLES, val);
+ break;
+
+ case IIO_CHAN_INFO_SCALE:
+ ret = regulator_get_voltage(priv->vref);
+ if (ret < 0) {
+ dev_err(&indio_dev->dev,
+ "failed to get vref voltage: %d\n", ret);
+ return ret;
+ }
+
+ *val = ret / 1000;
+ *val2 = priv->resolution;
+ return IIO_VAL_FRACTIONAL_LOG2;
+
+ default:
+ return -EINVAL;
+ }
+}
+
+static int meson_saradc_clk_init(struct iio_dev *indio_dev, void __iomem *base)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ struct clk_init_data init;
+ char clk_name[32];
+ const char *clk_parents[1];
+
+ snprintf(clk_name, sizeof(clk_name), "%s#adc_div",
+ of_node_full_name(indio_dev->dev.of_node));
+ init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
+ init.flags = 0;
+ init.ops = &clk_divider_ops;
+ clk_parents[0] = __clk_get_name(priv->clkin);
+ init.parent_names = clk_parents;
+ init.num_parents = 1;
+
+ priv->clk_div.reg = base + SAR_ADC_REG3;
+ priv->clk_div.shift = SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
+ priv->clk_div.width = SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
+ priv->clk_div.hw.init = &init;
+ priv->clk_div.flags = 0;
+
+ priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
+ &priv->clk_div.hw);
+ if (WARN_ON(IS_ERR(priv->adc_div_clk)))
+ return PTR_ERR(priv->adc_div_clk);
+
+ snprintf(clk_name, sizeof(clk_name), "%s#adc_en",
+ of_node_full_name(indio_dev->dev.of_node));
+ init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
+ init.flags = CLK_SET_RATE_PARENT;
+ init.ops = &clk_gate_ops;
+ clk_parents[0] = __clk_get_name(priv->adc_div_clk);
+ init.parent_names = clk_parents;
+ init.num_parents = 1;
+
+ priv->clk_gate.reg = base + SAR_ADC_REG3;
+ priv->clk_gate.bit_idx = fls(SAR_ADC_REG3_CLK_EN);
+ priv->clk_gate.hw.init = &init;
+
+ priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
+ if (WARN_ON(IS_ERR(priv->adc_clk)))
+ return PTR_ERR(priv->adc_clk);
+
+ return 0;
+}
+
+static int meson_saradc_init(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int regval, ret;
+
+ /* make sure we start at CH7 input */
+ meson_saradc_set_channel7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
+
+ regmap_read(priv->regmap, SAR_ADC_REG3, ®val);
+ if (regval & SAR_ADC_REG3_BL30_INITIALIZED) {
+ dev_info(&indio_dev->dev, "already initialized by BL30\n");
+ return 0;
+ }
+
+ dev_info(&indio_dev->dev, "initializing SAR ADC\n");
+
+ meson_saradc_stop_sample_engine(indio_dev);
+
+ /* update the channel 6 MUX to select the temperature sensor */
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
+ SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
+
+ /* disable all channels by default */
+ regmap_write(priv->regmap, SAR_ADC_CHAN_LIST, 0x0);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3,
+ SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3,
+ SAR_ADC_REG3_CNTL_USE_SC_DLY,
+ SAR_ADC_REG3_CNTL_USE_SC_DLY);
+
+ /* delay between two samples = (10+1) * 1uS */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK, 10));
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 0));
+
+ /* delay between two samples = (10+1) * 1uS */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 10));
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 1));
+
+ ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
+ if (ret) {
+ dev_err(&indio_dev->dev,
+ "failed to set adc parent to clkin\n");
+ return ret;
+ }
+
+ ret = clk_set_rate(priv->adc_clk, 1200000);
+ if (ret) {
+ dev_err(&indio_dev->dev, "failed to set adc clock rate\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int meson_saradc_hw_enable(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int ret;
+
+ meson_saradc_lock(indio_dev);
+
+ ret = regulator_enable(priv->vref);
+ if (ret < 0) {
+ dev_err(&indio_dev->dev, "failed to enable vref regulator\n");
+ goto err_vref;
+ }
+
+ ret = clk_prepare_enable(priv->core_clk);
+ if (ret) {
+ dev_err(&indio_dev->dev, "failed to enable core clk\n");
+ goto err_core_clk;
+ }
+
+ ret = clk_prepare_enable(priv->sana_clk);
+ if (ret) {
+ dev_err(&indio_dev->dev, "failed to enable sana clk\n");
+ goto err_sana_clk;
+ }
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG11,
+ SAR_ADC_REG11_BANDGAP_EN, SAR_ADC_REG11_BANDGAP_EN);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN,
+ SAR_ADC_REG3_ADC_EN);
+
+ udelay(5);
+
+ ret = clk_prepare_enable(priv->adc_clk);
+ if (ret) {
+ dev_err(&indio_dev->dev, "failed to enable adc_en clk\n");
+ goto err_adc_clk;
+ }
+
+ meson_saradc_unlock(indio_dev);
+
+ return 0;
+
+err_adc_clk:
+ clk_disable_unprepare(priv->sana_clk);
+err_sana_clk:
+ clk_disable_unprepare(priv->core_clk);
+err_core_clk:
+ regulator_disable(priv->vref);
+err_vref:
+ meson_saradc_unlock(indio_dev);
+ return ret;
+}
+
+static void meson_saradc_hw_disable(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ meson_saradc_lock(indio_dev);
+
+ clk_disable_unprepare(priv->adc_clk);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN, 0);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG11,
+ SAR_ADC_REG11_BANDGAP_EN, 0);
+
+ clk_disable_unprepare(priv->sana_clk);
+ clk_disable_unprepare(priv->core_clk);
+
+ regulator_disable(priv->vref);
+
+ meson_saradc_unlock(indio_dev);
+}
+
+static const struct iio_info meson_saradc_iio_info = {
+ .read_raw = meson_saradc_iio_info_read_raw,
+ .driver_module = THIS_MODULE,
+};
+
+static const struct of_device_id meson_saradc_of_match[] = {
+ {
+ .compatible = "amlogic,meson-gxbb-saradc",
+ .data = (void *)10,
+ }, {
+ .compatible = "amlogic,meson-gxl-saradc",
+ .data = (void *)12,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, meson_saradc_of_match);
+
+static int meson_saradc_probe(struct platform_device *pdev)
+{
+ struct meson_saradc_priv *priv;
+ struct iio_dev *indio_dev;
+ struct resource *res;
+ void __iomem *base;
+ const struct of_device_id *match;
+ int ret;
+
+ indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
+ if (!indio_dev) {
+ dev_err(&pdev->dev, "failed allocating iio device\n");
+ return -ENOMEM;
+ }
+
+ priv = iio_priv(indio_dev);
+
+ match = of_match_device(meson_saradc_of_match, &pdev->dev);
+ priv->resolution = (unsigned long)match->data;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
+ &meson_saradc_regmap_config);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+ init_completion(&priv->completion);
+
+ priv->clkin = devm_clk_get(&pdev->dev, "clkin");
+ if (IS_ERR(priv->clkin)) {
+ dev_err(&pdev->dev, "failed to get clkin\n");
+ return PTR_ERR(priv->clkin);
+ }
+
+ priv->core_clk = devm_clk_get(&pdev->dev, "core");
+ if (IS_ERR(priv->core_clk)) {
+ dev_err(&pdev->dev, "failed to get core clk\n");
+ return PTR_ERR(priv->core_clk);
+ }
+
+ priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
+ if (IS_ERR(priv->sana_clk)) {
+ if (PTR_ERR(priv->sana_clk) == -ENOENT) {
+ priv->sana_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get sana clk\n");
+ return PTR_ERR(priv->sana_clk);
+ }
+ }
+
+ priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
+ if (IS_ERR(priv->adc_clk)) {
+ if (PTR_ERR(priv->adc_clk) == -ENOENT) {
+ priv->adc_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get adc clk\n");
+ return PTR_ERR(priv->adc_clk);
+ }
+ }
+
+ priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
+ if (IS_ERR(priv->adc_sel_clk)) {
+ if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
+ priv->adc_sel_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get adc_sel clk\n");
+ return PTR_ERR(priv->adc_sel_clk);
+ }
+ }
+
+ /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
+ if (!priv->adc_clk) {
+ ret = meson_saradc_clk_init(indio_dev, base);
+ if (ret)
+ return ret;
+ }
+
+ priv->vref = devm_regulator_get(&pdev->dev, "vref");
+ if (IS_ERR(priv->vref)) {
+ dev_err(&pdev->dev, "failed to get vref regulator\n");
+ return PTR_ERR(priv->vref);
+ }
+
+ ret = meson_saradc_init(indio_dev);
+ if (ret)
+ goto err;
+
+ ret = meson_saradc_hw_enable(indio_dev);
+ if (ret)
+ goto err;
+
+ platform_set_drvdata(pdev, indio_dev);
+
+ indio_dev->name = dev_name(&pdev->dev);
+ indio_dev->dev.parent = &pdev->dev;
+ indio_dev->dev.of_node = pdev->dev.of_node;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->info = &meson_saradc_iio_info;
+
+ indio_dev->channels = meson_saradc_iio_channels;
+ indio_dev->num_channels = SAR_ADC_NUM_CHANNELS;
+
+ ret = iio_device_register(indio_dev);
+ if (ret)
+ goto err_hw;
+
+ return 0;
+
+err_hw:
+ meson_saradc_hw_disable(indio_dev);
+err:
+ return ret;
+}
+
+static int meson_saradc_remove(struct platform_device *pdev)
+{
+ struct iio_dev *indio_dev = platform_get_drvdata(pdev);
+
+ meson_saradc_hw_disable(indio_dev);
+ iio_device_unregister(indio_dev);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int meson_saradc_suspend(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+
+ meson_saradc_hw_disable(indio_dev);
+
+ return 0;
+}
+
+static int meson_saradc_resume(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+
+ return meson_saradc_hw_enable(indio_dev);
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(meson_saradc_pm_ops,
+ meson_saradc_suspend, meson_saradc_resume);
+
+static struct platform_driver meson_saradc_driver = {
+ .probe = meson_saradc_probe,
+ .remove = meson_saradc_remove,
+ .driver = {
+ .name = "meson-saradc",
+ .of_match_table = meson_saradc_of_match,
+ .pm = &meson_saradc_pm_ops,
+ },
+};
+
+module_platform_driver(meson_saradc_driver);
+
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
+MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
+MODULE_LICENSE("GPL v2");
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
@ 2017-01-11 17:43 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-11 17:43 UTC (permalink / raw)
To: linus-amlogic
This adds support for the SAR (Successive Approximation Register) ADC
on the Amlogic Meson SoCs.
The code is based on the public S805 (Meson8b) and S905 (GXBB)
datasheets, as well as by reading (various versions of) the vendor
driver and by inspecting the registers on the vendor kernels of my
testing-hardware.
Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
The code was written to support older SoCs (Meson8 and Meson8b) as well,
but due to lack of actual testing-hardware no of_device_id was added for
these.
Two "features" from the vendor driver are currently missing:
- the vendor driver uses channel #7 for calibration (this improves the
accuracy of the results - in my tests the results were less than 3%
off without calibration compared to the vendor driver). Adding support
for this should be easy, but is not required for most applications.
- channel #6 is connected to the SoCs internal temperature sensor.
Adding support for this is probably not so easy since (based on the
u-boot sources) most SoC versions are using different registers and
algorithms for the conversion from "ADC value" to temperature.
Supported by the hardware but currently not supported by the driver:
- reading multiple channels at the same time (the hardware has a FIFO
buffer which stores multiple results)
- continuous sampling (this would require a way to enable this
individually because otherwise the ADC would be drawing power
constantly)
- interrupt support (similar to the vendor driver this new driver is
polling the results. It is unclear if the IRQ-mode is supported on
older (Meson6 or Meson8) hardware as well or if there are any errata)
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/iio/adc/Kconfig | 12 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/meson_saradc.c | 860 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 873 insertions(+)
create mode 100644 drivers/iio/adc/meson_saradc.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 9c8b558ba19e..86059b9b91bf 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -371,6 +371,18 @@ config MEN_Z188_ADC
This driver can also be built as a module. If so, the module will be
called men_z188_adc.
+config MESON_SARADC
+ tristate "Amlogic Meson SAR ADC driver"
+ default ARCH_MESON
+ depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
+ select REGMAP_MMIO
+ help
+ Say yes here to build support for the SAR ADC found in Amlogic Meson
+ SoCs.
+
+ To compile this driver as a module, choose M here: the
+ module will be called meson_saradc.
+
config MXS_LRADC
tristate "Freescale i.MX23/i.MX28 LRADC"
depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index d36c4be8d1fc..de05b9e75f8f 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
obj-$(CONFIG_MCP3422) += mcp3422.o
obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
+obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
obj-$(CONFIG_NAU7802) += nau7802.o
obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
new file mode 100644
index 000000000000..06e8ac620385
--- /dev/null
+++ b/drivers/iio/adc/meson_saradc.c
@@ -0,0 +1,860 @@
+/*
+ * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
+ *
+ * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iio/iio.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/reset.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+
+#define SAR_ADC_REG0 0x00
+ #define SAR_ADC_REG0_PANEL_DETECT BIT(31)
+ #define SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
+ #define SAR_ADC_REG0_DELTA_BUSY BIT(30)
+ #define SAR_ADC_REG0_AVG_BUSY BIT(29)
+ #define SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
+ #define SAR_ADC_REG0_FIFO_FULL BIT(27)
+ #define SAR_ADC_REG0_FIFO_EMPTY BIT(26)
+ #define SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
+ #define SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
+ #define SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
+ #define SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
+ #define SAR_ADC_REG0_SAMPLING_STOP BIT(14)
+ #define SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
+ #define SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
+ #define SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
+ #define SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
+ #define SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
+ #define SAR_ADC_REG0_SAMPLING_START BIT(2)
+ #define SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
+ #define SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
+
+#define SAR_ADC_CHAN_LIST 0x04
+ #define SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
+ #define SAR_ADC_CHAN_CHAN_ENTRY_MASK(_chan) \
+ (GENMASK(2, 0) << (_chan * 3))
+
+#define SAR_ADC_AVG_CNTL 0x08
+ #define SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
+ (16 + (_chan * 2))
+ #define SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
+ (GENMASK(17, 16) << (_chan * 2))
+ #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
+ (0 + (_chan * 2))
+ #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
+ (GENMASK(1, 0) << (_chan * 2))
+
+#define SAR_ADC_REG3 0x0c
+ #define SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
+ #define SAR_ADC_REG3_CLK_EN BIT(30)
+ #define SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
+ #define SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
+ #define SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
+ #define SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
+ #define SAR_ADC_REG3_DETECT_EN BIT(22)
+ #define SAR_ADC_REG3_ADC_EN BIT(21)
+ #define SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
+ #define SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
+ #define SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
+ #define SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
+ #define SAR_ADC_REG3_ADC_CLK_DIV_MASK GENMASK(15, 10)
+ #define SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
+ #define SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
+
+#define SAR_ADC_DELAY 0x10
+ #define SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
+ #define SAR_ADC_DELAY_BL30_BUSY BIT(15)
+ #define SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
+ #define SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
+ #define SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
+ #define SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
+
+#define SAR_ADC_LAST_RD 0x14
+ #define SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
+ #define SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
+
+#define SAR_ADC_FIFO_RD 0x18
+ #define SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
+ #define SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
+
+#define SAR_ADC_AUX_SW 0x1c
+ #define SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
+ (GENMASK(10, 8) << ((_chan - 2) * 2))
+ #define SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
+ #define SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
+ #define SAR_ADC_AUX_SW_MODE_SEL BIT(4)
+ #define SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
+ #define SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
+ #define SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
+ #define SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
+
+#define SAR_ADC_CHAN_10_SW 0x20
+ #define SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
+
+#define SAR_ADC_DETECT_IDLE_SW 0x24
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK GENMASK(25, 23)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_P_MUX BIT(22)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_N_MUX BIT(21)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YP_DRIVE_SW BIT(19)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XP_DRIVE_SW BIT(18)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YM_DRIVE_SW BIT(17)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XM_DRIVE_SW BIT(16)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK GENMASK(9, 7)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_P_MUX BIT(6)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_N_MUX BIT(5)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YP_DRIVE_SW BIT(3)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XP_DRIVE_SW BIT(2)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YM_DRIVE_SW BIT(1)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XM_DRIVE_SW BIT(0)
+
+#define SAR_ADC_DELTA_10 0x28
+ #define SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
+ #define SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
+ #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_SHIFT 16
+ #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
+ #define SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
+ #define SAR_ADC_DELTA_10_TS_C_SHIFT 11
+ #define SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
+ #define SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
+ #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_SHIFT 0
+ #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
+
+/* NOTE: registers from here are undocumented (the vendor Linux kernel driver
+ * and u-boot source served as reference). These only seem to be relevant on
+ * GXBB and newer.
+ */
+#define SAR_ADC_REG11 0x2c
+ #define SAR_ADC_REG11_BANDGAP_EN BIT(13)
+
+#define SAR_ADC_REG13 0x34
+ #define SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
+
+#define SAR_ADC_MAX_FIFO_SIZE 32
+#define SAR_ADC_NUM_CHANNELS ARRAY_SIZE(meson_saradc_iio_channels)
+#define SAR_ADC_VALUE_MASK(_priv) (BIT(_priv->resolution) - 1)
+
+#define MESON_SAR_ADC_CHAN(_chan, _type) { \
+ .type = _type, \
+ .indexed = true, \
+ .channel = _chan, \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
+ BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
+ .datasheet_name = "SAR_ADC_CH"#_chan, \
+}
+
+/* TODO: the hardware supports IIO_TEMP for channel 6 as well which is
+ * currently not supported by this driver.
+ */
+static const struct iio_chan_spec meson_saradc_iio_channels[] = {
+ MESON_SAR_ADC_CHAN(0, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(1, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(2, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(3, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(4, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(5, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(6, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(7, IIO_VOLTAGE),
+ IIO_CHAN_SOFT_TIMESTAMP(8),
+};
+
+enum meson_saradc_avg_mode {
+ NO_AVERAGING = 0x0,
+ MEAN_AVERAGING = 0x1,
+ MEDIAN_AVERAGING = 0x2,
+};
+
+enum meson_saradc_num_samples {
+ ONE_SAMPLE = 0x0,
+ TWO_SAMPLES = 0x1,
+ FOUR_SAMPLES = 0x2,
+ EIGHT_SAMPLES = 0x3,
+};
+
+enum meson_saradc_chan7_mux_sel {
+ CHAN7_MUX_VSS = 0x0,
+ CHAN7_MUX_VDD_DIV4 = 0x1,
+ CHAN7_MUX_VDD_DIV2 = 0x2,
+ CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
+ CHAN7_MUX_VDD = 0x4,
+ CHAN7_MUX_CH7_INPUT = 0x7,
+};
+
+struct meson_saradc_priv {
+ struct regmap *regmap;
+ struct clk *clkin;
+ struct clk *core_clk;
+ struct clk *sana_clk;
+ struct clk *adc_sel_clk;
+ struct clk *adc_clk;
+ struct clk_gate clk_gate;
+ struct clk *adc_div_clk;
+ struct clk_divider clk_div;
+ struct regulator *vref;
+ struct completion completion;
+ u8 resolution;
+};
+
+static const struct regmap_config meson_saradc_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = SAR_ADC_REG13,
+};
+
+static unsigned int meson_saradc_get_fifo_count(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
+
+ return FIELD_GET(SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
+}
+
+static int meson_saradc_wait_busy_clear(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int regval, timeout = 10000;
+
+ do {
+ udelay(1);
+ regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
+ } while (FIELD_GET(SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
+
+ if (timeout < 0)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static int meson_saradc_read_raw_sample(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ int *val)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0;
+
+ ret = meson_saradc_wait_busy_clear(indio_dev);
+ if (ret)
+ return ret;
+
+ regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
+
+ while (meson_saradc_get_fifo_count(indio_dev) > 0 &&
+ count < SAR_ADC_MAX_FIFO_SIZE) {
+ regmap_read(priv->regmap, SAR_ADC_FIFO_RD, ®val);
+
+ fifo_chan = FIELD_GET(SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
+ if (fifo_chan == chan->channel) {
+ fifo_val = FIELD_GET(SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK,
+ regval) & SAR_ADC_VALUE_MASK(priv);
+ sum += fifo_val;
+ count++;
+ }
+ }
+
+ if (!count)
+ return -ENOENT;
+
+ *val = sum / count;
+
+ return 0;
+}
+
+static void meson_saradc_set_averaging(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ enum meson_saradc_avg_mode mode,
+ enum meson_saradc_num_samples samples)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 val;
+
+ val = samples << SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
+ SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(chan->channel),
+ val);
+
+ val = mode << SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
+ SAR_ADC_AVG_CNTL_AVG_MODE_MASK(chan->channel), val);
+}
+
+static void meson_saradc_enable_channel(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ /* the SAR ADC engine allows sampling multiple channels at the same
+ * time. to keep it simple we're only working with one *internal*
+ * channel, which starts counting at index 0 (which means: count = 1).
+ */
+ regval = FIELD_PREP(SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
+ regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
+ SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
+
+ /* map channel index 0 to the channel which we want to read */
+ regval = FIELD_PREP(SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
+ SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), regval);
+
+ regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
+ chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
+ SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
+ regval);
+
+ regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
+ chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
+ SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
+ regval);
+
+ if (chan->channel == 6)
+ regmap_update_bits(priv->regmap, SAR_ADC_DELTA_10,
+ SAR_ADC_DELTA_10_TEMP_SEL, 0);
+}
+
+static void meson_saradc_set_channel7_mux(struct iio_dev *indio_dev,
+ enum meson_saradc_chan7_mux_sel sel)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ regval = FIELD_PREP(SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3,
+ SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
+
+ usleep_range(10, 20);
+}
+
+static void meson_saradc_start_sample_engine(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
+ SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLING_START,
+ SAR_ADC_REG0_SAMPLING_START);
+}
+
+static void meson_saradc_stop_sample_engine(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLING_STOP,
+ SAR_ADC_REG0_SAMPLING_STOP);
+
+ /* wait until all modules are stopped */
+ meson_saradc_wait_busy_clear(indio_dev);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
+}
+
+static void meson_saradc_lock(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int val;
+
+ mutex_lock(&indio_dev->mlock);
+
+ /* prevent BL30 from using the SAR ADC while we are using it */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_KERNEL_BUSY,
+ SAR_ADC_DELAY_KERNEL_BUSY);
+
+ /* wait until BL30 releases it's lock (so we can use the SAR ADC) */
+ do {
+ udelay(1);
+ regmap_read(priv->regmap, SAR_ADC_DELAY, &val);
+ } while (val & SAR_ADC_DELAY_BL30_BUSY);
+}
+
+static void meson_saradc_unlock(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ /* allow BL30 to use the SAR ADC again */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_KERNEL_BUSY, 0);
+
+ mutex_unlock(&indio_dev->mlock);
+}
+
+static int meson_saradc_get_sample(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ enum meson_saradc_avg_mode avg_mode,
+ enum meson_saradc_num_samples avg_samples,
+ int *val)
+{
+ int ret, tmp;
+
+ meson_saradc_lock(indio_dev);
+
+ /* clear old values from the FIFO buffer, ignoring errors */
+ meson_saradc_read_raw_sample(indio_dev, chan, &tmp);
+
+ meson_saradc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
+
+ meson_saradc_enable_channel(indio_dev, chan);
+
+ meson_saradc_start_sample_engine(indio_dev);
+ ret = meson_saradc_read_raw_sample(indio_dev, chan, val);
+ meson_saradc_stop_sample_engine(indio_dev);
+
+ meson_saradc_unlock(indio_dev);
+
+ if (ret) {
+ dev_warn(&indio_dev->dev,
+ "failed to read sample for channel %d: %d\n",
+ chan->channel, ret);
+ return ret;
+ }
+
+ return IIO_VAL_INT;
+}
+
+static int meson_saradc_iio_info_read_raw(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ int *val, int *val2, long mask)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int ret;
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ return meson_saradc_get_sample(indio_dev, chan, NO_AVERAGING,
+ ONE_SAMPLE, val);
+ break;
+
+ case IIO_CHAN_INFO_AVERAGE_RAW:
+ return meson_saradc_get_sample(indio_dev, chan, MEAN_AVERAGING,
+ EIGHT_SAMPLES, val);
+ break;
+
+ case IIO_CHAN_INFO_SCALE:
+ ret = regulator_get_voltage(priv->vref);
+ if (ret < 0) {
+ dev_err(&indio_dev->dev,
+ "failed to get vref voltage: %d\n", ret);
+ return ret;
+ }
+
+ *val = ret / 1000;
+ *val2 = priv->resolution;
+ return IIO_VAL_FRACTIONAL_LOG2;
+
+ default:
+ return -EINVAL;
+ }
+}
+
+static int meson_saradc_clk_init(struct iio_dev *indio_dev, void __iomem *base)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ struct clk_init_data init;
+ char clk_name[32];
+ const char *clk_parents[1];
+
+ snprintf(clk_name, sizeof(clk_name), "%s#adc_div",
+ of_node_full_name(indio_dev->dev.of_node));
+ init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
+ init.flags = 0;
+ init.ops = &clk_divider_ops;
+ clk_parents[0] = __clk_get_name(priv->clkin);
+ init.parent_names = clk_parents;
+ init.num_parents = 1;
+
+ priv->clk_div.reg = base + SAR_ADC_REG3;
+ priv->clk_div.shift = SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
+ priv->clk_div.width = SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
+ priv->clk_div.hw.init = &init;
+ priv->clk_div.flags = 0;
+
+ priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
+ &priv->clk_div.hw);
+ if (WARN_ON(IS_ERR(priv->adc_div_clk)))
+ return PTR_ERR(priv->adc_div_clk);
+
+ snprintf(clk_name, sizeof(clk_name), "%s#adc_en",
+ of_node_full_name(indio_dev->dev.of_node));
+ init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
+ init.flags = CLK_SET_RATE_PARENT;
+ init.ops = &clk_gate_ops;
+ clk_parents[0] = __clk_get_name(priv->adc_div_clk);
+ init.parent_names = clk_parents;
+ init.num_parents = 1;
+
+ priv->clk_gate.reg = base + SAR_ADC_REG3;
+ priv->clk_gate.bit_idx = fls(SAR_ADC_REG3_CLK_EN);
+ priv->clk_gate.hw.init = &init;
+
+ priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
+ if (WARN_ON(IS_ERR(priv->adc_clk)))
+ return PTR_ERR(priv->adc_clk);
+
+ return 0;
+}
+
+static int meson_saradc_init(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int regval, ret;
+
+ /* make sure we start at CH7 input */
+ meson_saradc_set_channel7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
+
+ regmap_read(priv->regmap, SAR_ADC_REG3, ®val);
+ if (regval & SAR_ADC_REG3_BL30_INITIALIZED) {
+ dev_info(&indio_dev->dev, "already initialized by BL30\n");
+ return 0;
+ }
+
+ dev_info(&indio_dev->dev, "initializing SAR ADC\n");
+
+ meson_saradc_stop_sample_engine(indio_dev);
+
+ /* update the channel 6 MUX to select the temperature sensor */
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
+ SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
+
+ /* disable all channels by default */
+ regmap_write(priv->regmap, SAR_ADC_CHAN_LIST, 0x0);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3,
+ SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3,
+ SAR_ADC_REG3_CNTL_USE_SC_DLY,
+ SAR_ADC_REG3_CNTL_USE_SC_DLY);
+
+ /* delay between two samples = (10+1) * 1uS */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK, 10));
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 0));
+
+ /* delay between two samples = (10+1) * 1uS */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 10));
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 1));
+
+ ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
+ if (ret) {
+ dev_err(&indio_dev->dev,
+ "failed to set adc parent to clkin\n");
+ return ret;
+ }
+
+ ret = clk_set_rate(priv->adc_clk, 1200000);
+ if (ret) {
+ dev_err(&indio_dev->dev, "failed to set adc clock rate\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int meson_saradc_hw_enable(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int ret;
+
+ meson_saradc_lock(indio_dev);
+
+ ret = regulator_enable(priv->vref);
+ if (ret < 0) {
+ dev_err(&indio_dev->dev, "failed to enable vref regulator\n");
+ goto err_vref;
+ }
+
+ ret = clk_prepare_enable(priv->core_clk);
+ if (ret) {
+ dev_err(&indio_dev->dev, "failed to enable core clk\n");
+ goto err_core_clk;
+ }
+
+ ret = clk_prepare_enable(priv->sana_clk);
+ if (ret) {
+ dev_err(&indio_dev->dev, "failed to enable sana clk\n");
+ goto err_sana_clk;
+ }
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG11,
+ SAR_ADC_REG11_BANDGAP_EN, SAR_ADC_REG11_BANDGAP_EN);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN,
+ SAR_ADC_REG3_ADC_EN);
+
+ udelay(5);
+
+ ret = clk_prepare_enable(priv->adc_clk);
+ if (ret) {
+ dev_err(&indio_dev->dev, "failed to enable adc_en clk\n");
+ goto err_adc_clk;
+ }
+
+ meson_saradc_unlock(indio_dev);
+
+ return 0;
+
+err_adc_clk:
+ clk_disable_unprepare(priv->sana_clk);
+err_sana_clk:
+ clk_disable_unprepare(priv->core_clk);
+err_core_clk:
+ regulator_disable(priv->vref);
+err_vref:
+ meson_saradc_unlock(indio_dev);
+ return ret;
+}
+
+static void meson_saradc_hw_disable(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ meson_saradc_lock(indio_dev);
+
+ clk_disable_unprepare(priv->adc_clk);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN, 0);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG11,
+ SAR_ADC_REG11_BANDGAP_EN, 0);
+
+ clk_disable_unprepare(priv->sana_clk);
+ clk_disable_unprepare(priv->core_clk);
+
+ regulator_disable(priv->vref);
+
+ meson_saradc_unlock(indio_dev);
+}
+
+static const struct iio_info meson_saradc_iio_info = {
+ .read_raw = meson_saradc_iio_info_read_raw,
+ .driver_module = THIS_MODULE,
+};
+
+static const struct of_device_id meson_saradc_of_match[] = {
+ {
+ .compatible = "amlogic,meson-gxbb-saradc",
+ .data = (void *)10,
+ }, {
+ .compatible = "amlogic,meson-gxl-saradc",
+ .data = (void *)12,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, meson_saradc_of_match);
+
+static int meson_saradc_probe(struct platform_device *pdev)
+{
+ struct meson_saradc_priv *priv;
+ struct iio_dev *indio_dev;
+ struct resource *res;
+ void __iomem *base;
+ const struct of_device_id *match;
+ int ret;
+
+ indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
+ if (!indio_dev) {
+ dev_err(&pdev->dev, "failed allocating iio device\n");
+ return -ENOMEM;
+ }
+
+ priv = iio_priv(indio_dev);
+
+ match = of_match_device(meson_saradc_of_match, &pdev->dev);
+ priv->resolution = (unsigned long)match->data;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
+ &meson_saradc_regmap_config);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+ init_completion(&priv->completion);
+
+ priv->clkin = devm_clk_get(&pdev->dev, "clkin");
+ if (IS_ERR(priv->clkin)) {
+ dev_err(&pdev->dev, "failed to get clkin\n");
+ return PTR_ERR(priv->clkin);
+ }
+
+ priv->core_clk = devm_clk_get(&pdev->dev, "core");
+ if (IS_ERR(priv->core_clk)) {
+ dev_err(&pdev->dev, "failed to get core clk\n");
+ return PTR_ERR(priv->core_clk);
+ }
+
+ priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
+ if (IS_ERR(priv->sana_clk)) {
+ if (PTR_ERR(priv->sana_clk) == -ENOENT) {
+ priv->sana_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get sana clk\n");
+ return PTR_ERR(priv->sana_clk);
+ }
+ }
+
+ priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
+ if (IS_ERR(priv->adc_clk)) {
+ if (PTR_ERR(priv->adc_clk) == -ENOENT) {
+ priv->adc_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get adc clk\n");
+ return PTR_ERR(priv->adc_clk);
+ }
+ }
+
+ priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
+ if (IS_ERR(priv->adc_sel_clk)) {
+ if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
+ priv->adc_sel_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get adc_sel clk\n");
+ return PTR_ERR(priv->adc_sel_clk);
+ }
+ }
+
+ /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
+ if (!priv->adc_clk) {
+ ret = meson_saradc_clk_init(indio_dev, base);
+ if (ret)
+ return ret;
+ }
+
+ priv->vref = devm_regulator_get(&pdev->dev, "vref");
+ if (IS_ERR(priv->vref)) {
+ dev_err(&pdev->dev, "failed to get vref regulator\n");
+ return PTR_ERR(priv->vref);
+ }
+
+ ret = meson_saradc_init(indio_dev);
+ if (ret)
+ goto err;
+
+ ret = meson_saradc_hw_enable(indio_dev);
+ if (ret)
+ goto err;
+
+ platform_set_drvdata(pdev, indio_dev);
+
+ indio_dev->name = dev_name(&pdev->dev);
+ indio_dev->dev.parent = &pdev->dev;
+ indio_dev->dev.of_node = pdev->dev.of_node;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->info = &meson_saradc_iio_info;
+
+ indio_dev->channels = meson_saradc_iio_channels;
+ indio_dev->num_channels = SAR_ADC_NUM_CHANNELS;
+
+ ret = iio_device_register(indio_dev);
+ if (ret)
+ goto err_hw;
+
+ return 0;
+
+err_hw:
+ meson_saradc_hw_disable(indio_dev);
+err:
+ return ret;
+}
+
+static int meson_saradc_remove(struct platform_device *pdev)
+{
+ struct iio_dev *indio_dev = platform_get_drvdata(pdev);
+
+ meson_saradc_hw_disable(indio_dev);
+ iio_device_unregister(indio_dev);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int meson_saradc_suspend(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+
+ meson_saradc_hw_disable(indio_dev);
+
+ return 0;
+}
+
+static int meson_saradc_resume(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+
+ return meson_saradc_hw_enable(indio_dev);
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(meson_saradc_pm_ops,
+ meson_saradc_suspend, meson_saradc_resume);
+
+static struct platform_driver meson_saradc_driver = {
+ .probe = meson_saradc_probe,
+ .remove = meson_saradc_remove,
+ .driver = {
+ .name = "meson-saradc",
+ .of_match_table = meson_saradc_of_match,
+ .pm = &meson_saradc_pm_ops,
+ },
+};
+
+module_platform_driver(meson_saradc_driver);
+
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
+MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
+MODULE_LICENSE("GPL v2");
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH 4/4] ARM64: dts: meson: meson-gx: add the SAR ADC
2017-01-11 17:43 ` Martin Blumenstingl
(?)
@ 2017-01-11 17:43 ` Martin Blumenstingl
-1 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-11 17:43 UTC (permalink / raw)
To: jic23, knaack.h, lars, pmeerw, robh+dt, mark.rutland, khilman,
linux-iio, devicetree, linux-amlogic, linux-clk
Cc: carlo, catalin.marinas, will.deacon, mturquette, sboyd,
narmstrong, linux-arm-kernel, Martin Blumenstingl
Add the SAR ADC to meson-gxbb.dtsi and meson-gxl.dtsi. GXBB provides a
10-bit ADC while GXL (and GXM, which uses the same ADC as GXL) provides
a 12-bit ADC.
Some boards use resistor ladder buttons connected through one of the ADC
channels. On newer devices (GXL and GXM) some boards use pull-ups/downs
to change the resistance (and thus the ADC value) on of the ADC channels
to indicate the board revision.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 ++++++++
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 ++++++++++
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 ++++++++++
3 files changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index cddad8c795ec..ed3bf29eb76a 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -237,6 +237,14 @@
status = "disabled";
};
+ saradc: adc@8680 {
+ compatible = "amlogic,meson-saradc";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ reg = <0x0 0x8680 0x0 0x34>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_EDGE_RISING>;
+ };
+
pwm_ef: pwm@86c0 {
compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
reg = <0x0 0x086c0 0x0 0x10>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 5d686334f692..114d7e1c9fc0 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -429,6 +429,16 @@
clocks = <&clkc CLKID_I2C>;
};
+&saradc {
+ compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+};
+
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index bb2842f8a08f..6b63296b6c60 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -273,6 +273,16 @@
clocks = <&clkc CLKID_I2C>;
};
+&saradc {
+ compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+};
+
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH 4/4] ARM64: dts: meson: meson-gx: add the SAR ADC
@ 2017-01-11 17:43 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-11 17:43 UTC (permalink / raw)
To: linux-arm-kernel
Add the SAR ADC to meson-gxbb.dtsi and meson-gxl.dtsi. GXBB provides a
10-bit ADC while GXL (and GXM, which uses the same ADC as GXL) provides
a 12-bit ADC.
Some boards use resistor ladder buttons connected through one of the ADC
channels. On newer devices (GXL and GXM) some boards use pull-ups/downs
to change the resistance (and thus the ADC value) on of the ADC channels
to indicate the board revision.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 ++++++++
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 ++++++++++
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 ++++++++++
3 files changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index cddad8c795ec..ed3bf29eb76a 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -237,6 +237,14 @@
status = "disabled";
};
+ saradc: adc at 8680 {
+ compatible = "amlogic,meson-saradc";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ reg = <0x0 0x8680 0x0 0x34>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_EDGE_RISING>;
+ };
+
pwm_ef: pwm at 86c0 {
compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
reg = <0x0 0x086c0 0x0 0x10>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 5d686334f692..114d7e1c9fc0 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -429,6 +429,16 @@
clocks = <&clkc CLKID_I2C>;
};
+&saradc {
+ compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+};
+
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index bb2842f8a08f..6b63296b6c60 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -273,6 +273,16 @@
clocks = <&clkc CLKID_I2C>;
};
+&saradc {
+ compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+};
+
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH 4/4] ARM64: dts: meson: meson-gx: add the SAR ADC
@ 2017-01-11 17:43 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-11 17:43 UTC (permalink / raw)
To: linus-amlogic
Add the SAR ADC to meson-gxbb.dtsi and meson-gxl.dtsi. GXBB provides a
10-bit ADC while GXL (and GXM, which uses the same ADC as GXL) provides
a 12-bit ADC.
Some boards use resistor ladder buttons connected through one of the ADC
channels. On newer devices (GXL and GXM) some boards use pull-ups/downs
to change the resistance (and thus the ADC value) on of the ADC channels
to indicate the board revision.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 ++++++++
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 ++++++++++
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 ++++++++++
3 files changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index cddad8c795ec..ed3bf29eb76a 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -237,6 +237,14 @@
status = "disabled";
};
+ saradc: adc at 8680 {
+ compatible = "amlogic,meson-saradc";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ reg = <0x0 0x8680 0x0 0x34>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_EDGE_RISING>;
+ };
+
pwm_ef: pwm at 86c0 {
compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
reg = <0x0 0x086c0 0x0 0x10>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 5d686334f692..114d7e1c9fc0 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -429,6 +429,16 @@
clocks = <&clkc CLKID_I2C>;
};
+&saradc {
+ compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+};
+
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index bb2842f8a08f..6b63296b6c60 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -273,6 +273,16 @@
clocks = <&clkc CLKID_I2C>;
};
+&saradc {
+ compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+};
+
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* Re: [PATCH 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
2017-01-11 17:43 ` Martin Blumenstingl
(?)
@ 2017-01-14 14:46 ` Jonathan Cameron
-1 siblings, 0 replies; 110+ messages in thread
From: Jonathan Cameron @ 2017-01-14 14:46 UTC (permalink / raw)
To: Martin Blumenstingl, knaack.h, lars, pmeerw, robh+dt,
mark.rutland, khilman, linux-iio, devicetree, linux-amlogic,
linux-clk
Cc: carlo, catalin.marinas, will.deacon, mturquette, sboyd,
narmstrong, linux-arm-kernel, Russell King
On 11/01/17 17:43, Martin Blumenstingl wrote:
> This adds support for the SAR (Successive Approximation Register) ADC
> on the Amlogic Meson SoCs.
>
> The code is based on the public S805 (Meson8b) and S905 (GXBB)
> datasheets, as well as by reading (various versions of) the vendor
> driver and by inspecting the registers on the vendor kernels of my
> testing-hardware.
>
> Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
> 10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
> The code was written to support older SoCs (Meson8 and Meson8b) as well,
> but due to lack of actual testing-hardware no of_device_id was added for
> these.
>
> Two "features" from the vendor driver are currently missing:
> - the vendor driver uses channel #7 for calibration (this improves the
> accuracy of the results - in my tests the results were less than 3%
> off without calibration compared to the vendor driver). Adding support
> for this should be easy, but is not required for most applications.
> - channel #6 is connected to the SoCs internal temperature sensor.
> Adding support for this is probably not so easy since (based on the
> u-boot sources) most SoC versions are using different registers and
> algorithms for the conversion from "ADC value" to temperature.
>
> Supported by the hardware but currently not supported by the driver:
> - reading multiple channels at the same time (the hardware has a FIFO
> buffer which stores multiple results)
> - continuous sampling (this would require a way to enable this
> individually because otherwise the ADC would be drawing power
> constantly)
> - interrupt support (similar to the vendor driver this new driver is
> polling the results. It is unclear if the IRQ-mode is supported on
> older (Meson6 or Meson8) hardware as well or if there are any errata)
>
Russell Cc'd for a quick question on the clk api.
Ideally include a source for datasheets if available. Saves time googling and
perhaps getting the wrong thing!
A few other minor comments inline. Pretty good V1.
Jonathan
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
> drivers/iio/adc/Kconfig | 12 +
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/meson_saradc.c | 860 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 873 insertions(+)
> create mode 100644 drivers/iio/adc/meson_saradc.c
>
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index 9c8b558ba19e..86059b9b91bf 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -371,6 +371,18 @@ config MEN_Z188_ADC
> This driver can also be built as a module. If so, the module will be
> called men_z188_adc.
>
> +config MESON_SARADC
> + tristate "Amlogic Meson SAR ADC driver"
> + default ARCH_MESON
> + depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
> + select REGMAP_MMIO
> + help
> + Say yes here to build support for the SAR ADC found in Amlogic Meson
> + SoCs.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called meson_saradc.
> +
> config MXS_LRADC
> tristate "Freescale i.MX23/i.MX28 LRADC"
> depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
> index d36c4be8d1fc..de05b9e75f8f 100644
> --- a/drivers/iio/adc/Makefile
> +++ b/drivers/iio/adc/Makefile
> @@ -36,6 +36,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
> obj-$(CONFIG_MCP3422) += mcp3422.o
> obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
> obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
> +obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
> obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
> obj-$(CONFIG_NAU7802) += nau7802.o
> obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
> diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
> new file mode 100644
> index 000000000000..06e8ac620385
> --- /dev/null
> +++ b/drivers/iio/adc/meson_saradc.c
> @@ -0,0 +1,860 @@
> +/*
> + * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
> + *
> + * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/iio/iio.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/clk.h>
> +#include <linux/completion.h>
> +#include <linux/delay.h>
> +#include <linux/reset.h>
> +#include <linux/regmap.h>
> +#include <linux/regulator/consumer.h>
> +
> +#define SAR_ADC_REG0 0x00
> + #define SAR_ADC_REG0_PANEL_DETECT BIT(31)
> + #define SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
> + #define SAR_ADC_REG0_DELTA_BUSY BIT(30)
> + #define SAR_ADC_REG0_AVG_BUSY BIT(29)
> + #define SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
> + #define SAR_ADC_REG0_FIFO_FULL BIT(27)
> + #define SAR_ADC_REG0_FIFO_EMPTY BIT(26)
> + #define SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
> + #define SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
> + #define SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
> + #define SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
> + #define SAR_ADC_REG0_SAMPLING_STOP BIT(14)
> + #define SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
> + #define SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
> + #define SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
> + #define SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
> + #define SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
> + #define SAR_ADC_REG0_SAMPLING_START BIT(2)
> + #define SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
> + #define SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
> +
> +#define SAR_ADC_CHAN_LIST 0x04
> + #define SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
> + #define SAR_ADC_CHAN_CHAN_ENTRY_MASK(_chan) \
> + (GENMASK(2, 0) << (_chan * 3))
> +
> +#define SAR_ADC_AVG_CNTL 0x08
> + #define SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
> + (16 + (_chan * 2))
> + #define SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
> + (GENMASK(17, 16) << (_chan * 2))
> + #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
> + (0 + (_chan * 2))
> + #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
> + (GENMASK(1, 0) << (_chan * 2))
> +
> +#define SAR_ADC_REG3 0x0c
> + #define SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
> + #define SAR_ADC_REG3_CLK_EN BIT(30)
> + #define SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
> + #define SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
> + #define SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
> + #define SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
> + #define SAR_ADC_REG3_DETECT_EN BIT(22)
> + #define SAR_ADC_REG3_ADC_EN BIT(21)
> + #define SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
> + #define SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
> + #define SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
> + #define SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
> + #define SAR_ADC_REG3_ADC_CLK_DIV_MASK GENMASK(15, 10)
> + #define SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
> + #define SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
> +
> +#define SAR_ADC_DELAY 0x10
> + #define SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
> + #define SAR_ADC_DELAY_BL30_BUSY BIT(15)
> + #define SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
> + #define SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
> + #define SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
> + #define SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
> +
> +#define SAR_ADC_LAST_RD 0x14
> + #define SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
> + #define SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
> +
> +#define SAR_ADC_FIFO_RD 0x18
> + #define SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
> + #define SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
> +
> +#define SAR_ADC_AUX_SW 0x1c
> + #define SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
> + (GENMASK(10, 8) << ((_chan - 2) * 2))
> + #define SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
> + #define SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
> + #define SAR_ADC_AUX_SW_MODE_SEL BIT(4)
> + #define SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
> + #define SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
> + #define SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
> + #define SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
> +
> +#define SAR_ADC_CHAN_10_SW 0x20
> + #define SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
> +
> +#define SAR_ADC_DETECT_IDLE_SW 0x24
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK GENMASK(25, 23)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_P_MUX BIT(22)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_N_MUX BIT(21)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YP_DRIVE_SW BIT(19)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XP_DRIVE_SW BIT(18)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YM_DRIVE_SW BIT(17)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XM_DRIVE_SW BIT(16)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK GENMASK(9, 7)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_P_MUX BIT(6)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_N_MUX BIT(5)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YP_DRIVE_SW BIT(3)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XP_DRIVE_SW BIT(2)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YM_DRIVE_SW BIT(1)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XM_DRIVE_SW BIT(0)
> +
> +#define SAR_ADC_DELTA_10 0x28
> + #define SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
> + #define SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
> + #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_SHIFT 16
> + #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
> + #define SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
> + #define SAR_ADC_DELTA_10_TS_C_SHIFT 11
> + #define SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
> + #define SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
> + #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_SHIFT 0
> + #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
> +
> +/* NOTE: registers from here are undocumented (the vendor Linux kernel driver
> + * and u-boot source served as reference). These only seem to be relevant on
> + * GXBB and newer.
> + */
> +#define SAR_ADC_REG11 0x2c
> + #define SAR_ADC_REG11_BANDGAP_EN BIT(13)
> +
> +#define SAR_ADC_REG13 0x34
> + #define SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
> +
> +#define SAR_ADC_MAX_FIFO_SIZE 32
> +#define SAR_ADC_NUM_CHANNELS ARRAY_SIZE(meson_saradc_iio_channels)
> +#define SAR_ADC_VALUE_MASK(_priv) (BIT(_priv->resolution) - 1)
> +
> +#define MESON_SAR_ADC_CHAN(_chan, _type) { \
> + .type = _type, \
> + .indexed = true, \
> + .channel = _chan, \
> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
> + BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
> + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
> + .datasheet_name = "SAR_ADC_CH"#_chan, \
> +}
> +
> +/* TODO: the hardware supports IIO_TEMP for channel 6 as well which is
Multline comment syntax.
> + * currently not supported by this driver.
> + */
> +static const struct iio_chan_spec meson_saradc_iio_channels[] = {
> + MESON_SAR_ADC_CHAN(0, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(1, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(2, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(3, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(4, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(5, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(6, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(7, IIO_VOLTAGE),
> + IIO_CHAN_SOFT_TIMESTAMP(8),
> +};
> +
> +enum meson_saradc_avg_mode {
> + NO_AVERAGING = 0x0,
> + MEAN_AVERAGING = 0x1,
> + MEDIAN_AVERAGING = 0x2,
> +};
> +
> +enum meson_saradc_num_samples {
> + ONE_SAMPLE = 0x0,
> + TWO_SAMPLES = 0x1,
> + FOUR_SAMPLES = 0x2,
> + EIGHT_SAMPLES = 0x3,
> +};
> +
> +enum meson_saradc_chan7_mux_sel {
> + CHAN7_MUX_VSS = 0x0,
> + CHAN7_MUX_VDD_DIV4 = 0x1,
> + CHAN7_MUX_VDD_DIV2 = 0x2,
> + CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
> + CHAN7_MUX_VDD = 0x4,
> + CHAN7_MUX_CH7_INPUT = 0x7,
> +};
> +
> +struct meson_saradc_priv {
> + struct regmap *regmap;
> + struct clk *clkin;
> + struct clk *core_clk;
> + struct clk *sana_clk;
> + struct clk *adc_sel_clk;
> + struct clk *adc_clk;
> + struct clk_gate clk_gate;
> + struct clk *adc_div_clk;
> + struct clk_divider clk_div;
> + struct regulator *vref;
> + struct completion completion;
> + u8 resolution;
> +};
> +
> +static const struct regmap_config meson_saradc_regmap_config = {
> + .reg_bits = 8,
> + .val_bits = 32,
> + .reg_stride = 4,
> + .max_register = SAR_ADC_REG13,
> +};
> +
> +static unsigned int meson_saradc_get_fifo_count(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + u32 regval;
> +
> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
> +
> + return FIELD_GET(SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
> +}
> +
> +static int meson_saradc_wait_busy_clear(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int regval, timeout = 10000;
> +
> + do {
> + udelay(1);
> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
> + } while (FIELD_GET(SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
> +
> + if (timeout < 0)
> + return -ETIMEDOUT;
> +
> + return 0;
> +}
> +
> +static int meson_saradc_read_raw_sample(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + int *val)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0;
> +
> + ret = meson_saradc_wait_busy_clear(indio_dev);
> + if (ret)
> + return ret;
> +
> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
> +
> + while (meson_saradc_get_fifo_count(indio_dev) > 0 &&
> + count < SAR_ADC_MAX_FIFO_SIZE) {
> + regmap_read(priv->regmap, SAR_ADC_FIFO_RD, ®val);
> +
> + fifo_chan = FIELD_GET(SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
> + if (fifo_chan == chan->channel) {
> + fifo_val = FIELD_GET(SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK,
> + regval) & SAR_ADC_VALUE_MASK(priv);
> + sum += fifo_val;
> + count++;
> + }
> + }
> +
> + if (!count)
> + return -ENOENT;
> +
> + *val = sum / count;
> +
> + return 0;
> +}
> +
> +static void meson_saradc_set_averaging(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + enum meson_saradc_avg_mode mode,
> + enum meson_saradc_num_samples samples)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + u32 val;
> +
> + val = samples << SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(chan->channel);
> + regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
> + SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(chan->channel),
> + val);
> +
> + val = mode << SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(chan->channel);
> + regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
> + SAR_ADC_AVG_CNTL_AVG_MODE_MASK(chan->channel), val);
> +}
> +
> +static void meson_saradc_enable_channel(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + u32 regval;
> +
> + /* the SAR ADC engine allows sampling multiple channels at the same
> + * time. to keep it simple we're only working with one *internal*
> + * channel, which starts counting at index 0 (which means: count = 1).
> + */
> + regval = FIELD_PREP(SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
> + regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
> + SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
> +
> + /* map channel index 0 to the channel which we want to read */
> + regval = FIELD_PREP(SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), chan->channel);
> + regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
> + SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), regval);
> +
> + regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
> + chan->channel);
> + regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
> + SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
> + regval);
> +
> + regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
> + chan->channel);
> + regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
> + SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
> + regval);
> +
> + if (chan->channel == 6)
> + regmap_update_bits(priv->regmap, SAR_ADC_DELTA_10,
> + SAR_ADC_DELTA_10_TEMP_SEL, 0);
> +}
> +
> +static void meson_saradc_set_channel7_mux(struct iio_dev *indio_dev,
> + enum meson_saradc_chan7_mux_sel sel)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + u32 regval;
> +
> + regval = FIELD_PREP(SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
> + SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
> +
> + usleep_range(10, 20);
> +}
> +
> +static void meson_saradc_start_sample_engine(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
> + SAR_ADC_REG0_SAMPLING_START,
> + SAR_ADC_REG0_SAMPLING_START);
> +}
> +
> +static void meson_saradc_stop_sample_engine(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
> + SAR_ADC_REG0_SAMPLING_STOP,
> + SAR_ADC_REG0_SAMPLING_STOP);
> +
> + /* wait until all modules are stopped */
> + meson_saradc_wait_busy_clear(indio_dev);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
> +}
> +
> +static void meson_saradc_lock(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int val;
> +
> + mutex_lock(&indio_dev->mlock);
> +
> + /* prevent BL30 from using the SAR ADC while we are using it */
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_KERNEL_BUSY,
> + SAR_ADC_DELAY_KERNEL_BUSY);
> +
> + /* wait until BL30 releases it's lock (so we can use the SAR ADC) */
> + do {
> + udelay(1);
> + regmap_read(priv->regmap, SAR_ADC_DELAY, &val);
> + } while (val & SAR_ADC_DELAY_BL30_BUSY);
> +}
> +
> +static void meson_saradc_unlock(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> +
> + /* allow BL30 to use the SAR ADC again */
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_KERNEL_BUSY, 0);
> +
> + mutex_unlock(&indio_dev->mlock);
> +}
> +
> +static int meson_saradc_get_sample(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + enum meson_saradc_avg_mode avg_mode,
> + enum meson_saradc_num_samples avg_samples,
> + int *val)
> +{
> + int ret, tmp;
> +
> + meson_saradc_lock(indio_dev);
> +
> + /* clear old values from the FIFO buffer, ignoring errors */
> + meson_saradc_read_raw_sample(indio_dev, chan, &tmp);
> +
> + meson_saradc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
> +
> + meson_saradc_enable_channel(indio_dev, chan);
> +
> + meson_saradc_start_sample_engine(indio_dev);
> + ret = meson_saradc_read_raw_sample(indio_dev, chan, val);
> + meson_saradc_stop_sample_engine(indio_dev);
> +
> + meson_saradc_unlock(indio_dev);
> +
> + if (ret) {
> + dev_warn(&indio_dev->dev,
> + "failed to read sample for channel %d: %d\n",
> + chan->channel, ret);
> + return ret;
> + }
> +
> + return IIO_VAL_INT;
> +}
> +
> +static int meson_saradc_iio_info_read_raw(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + int *val, int *val2, long mask)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int ret;
> +
> + switch (mask) {
> + case IIO_CHAN_INFO_RAW:
> + return meson_saradc_get_sample(indio_dev, chan, NO_AVERAGING,
> + ONE_SAMPLE, val);
> + break;
> +
> + case IIO_CHAN_INFO_AVERAGE_RAW:
> + return meson_saradc_get_sample(indio_dev, chan, MEAN_AVERAGING,
> + EIGHT_SAMPLES, val);
> + break;
> +
> + case IIO_CHAN_INFO_SCALE:
> + ret = regulator_get_voltage(priv->vref);
> + if (ret < 0) {
> + dev_err(&indio_dev->dev,
> + "failed to get vref voltage: %d\n", ret);
> + return ret;
> + }
> +
> + *val = ret / 1000;
> + *val2 = priv->resolution;
> + return IIO_VAL_FRACTIONAL_LOG2;
> +
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static int meson_saradc_clk_init(struct iio_dev *indio_dev, void __iomem *base)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + struct clk_init_data init;
> + char clk_name[32];
> + const char *clk_parents[1];
> +
> + snprintf(clk_name, sizeof(clk_name), "%s#adc_div",
> + of_node_full_name(indio_dev->dev.of_node));
> + init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
> + init.flags = 0;
> + init.ops = &clk_divider_ops;
> + clk_parents[0] = __clk_get_name(priv->clkin);
> + init.parent_names = clk_parents;
> + init.num_parents = 1;
> +
> + priv->clk_div.reg = base + SAR_ADC_REG3;
> + priv->clk_div.shift = SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
> + priv->clk_div.width = SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
> + priv->clk_div.hw.init = &init;
> + priv->clk_div.flags = 0;
> +
> + priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
> + &priv->clk_div.hw);
> + if (WARN_ON(IS_ERR(priv->adc_div_clk)))
> + return PTR_ERR(priv->adc_div_clk);
> +
> + snprintf(clk_name, sizeof(clk_name), "%s#adc_en",
> + of_node_full_name(indio_dev->dev.of_node));
> + init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
> + init.flags = CLK_SET_RATE_PARENT;
> + init.ops = &clk_gate_ops;
> + clk_parents[0] = __clk_get_name(priv->adc_div_clk);
> + init.parent_names = clk_parents;
> + init.num_parents = 1;
> +
> + priv->clk_gate.reg = base + SAR_ADC_REG3;
> + priv->clk_gate.bit_idx = fls(SAR_ADC_REG3_CLK_EN);
> + priv->clk_gate.hw.init = &init;
> +
> + priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
> + if (WARN_ON(IS_ERR(priv->adc_clk)))
> + return PTR_ERR(priv->adc_clk);
> +
> + return 0;
> +}
> +
> +static int meson_saradc_init(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int regval, ret;
> +
> + /* make sure we start at CH7 input */
why? Seems like a little more detail would be good here ;)
> + meson_saradc_set_channel7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
> +
> + regmap_read(priv->regmap, SAR_ADC_REG3, ®val);
> + if (regval & SAR_ADC_REG3_BL30_INITIALIZED) {
> + dev_info(&indio_dev->dev, "already initialized by BL30\n");
> + return 0;
> + }
> +
> + dev_info(&indio_dev->dev, "initializing SAR ADC\n");
I'd argue this provides no useful info so should be dropped.
Useful for debugging no doubt, but just noise going forward.
> +
> + meson_saradc_stop_sample_engine(indio_dev);
> +
> + /* update the channel 6 MUX to select the temperature sensor */
> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
> + SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
> + SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
> +
> + /* disable all channels by default */
> + regmap_write(priv->regmap, SAR_ADC_CHAN_LIST, 0x0);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
> + SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
> + SAR_ADC_REG3_CNTL_USE_SC_DLY,
> + SAR_ADC_REG3_CNTL_USE_SC_DLY);
> +
> + /* delay between two samples = (10+1) * 1uS */
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
> + FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK, 10));
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
> + FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 0));
> +
> + /* delay between two samples = (10+1) * 1uS */
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
> + FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 10));
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
> + FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 1));
> +
Cool. I hadn't come across FIELD_PREP before. Neater and tidier than having
a shift and a mask for at least some usecases.
> + ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
> + if (ret) {
> + dev_err(&indio_dev->dev,
> + "failed to set adc parent to clkin\n");
> + return ret;
> + }
> +
> + ret = clk_set_rate(priv->adc_clk, 1200000);
> + if (ret) {
> + dev_err(&indio_dev->dev, "failed to set adc clock rate\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int meson_saradc_hw_enable(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int ret;
> +
> + meson_saradc_lock(indio_dev);
> +
> + ret = regulator_enable(priv->vref);
> + if (ret < 0) {
> + dev_err(&indio_dev->dev, "failed to enable vref regulator\n");
> + goto err_vref;
> + }
> +
> + ret = clk_prepare_enable(priv->core_clk);
> + if (ret) {
> + dev_err(&indio_dev->dev, "failed to enable core clk\n");
> + goto err_core_clk;
> + }
> +
> + ret = clk_prepare_enable(priv->sana_clk);
> + if (ret) {
> + dev_err(&indio_dev->dev, "failed to enable sana clk\n");
> + goto err_sana_clk;
> + }
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG11,
> + SAR_ADC_REG11_BANDGAP_EN, SAR_ADC_REG11_BANDGAP_EN);
Is this controlling an offset for a bandgap or some actual electronics?
Not sure if it should be disabled on error and the datasheets I've found are
far from great! You disable it in the disable, so I'd expect it to be
unwound on error in here too.
> + regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN,
> + SAR_ADC_REG3_ADC_EN);
The fact you turn this of in the disable suggests to me that on error
you should be doing it in here too.
> +
> + udelay(5);
> +
> + ret = clk_prepare_enable(priv->adc_clk);
> + if (ret) {
> + dev_err(&indio_dev->dev, "failed to enable adc_en clk\n");
> + goto err_adc_clk;
> + }
> +
> + meson_saradc_unlock(indio_dev);
> +
> + return 0;
> +
> +err_adc_clk:
> + clk_disable_unprepare(priv->sana_clk);
> +err_sana_clk:
> + clk_disable_unprepare(priv->core_clk);
> +err_core_clk:
> + regulator_disable(priv->vref);
> +err_vref:
> + meson_saradc_unlock(indio_dev);
> + return ret;
> +}
> +
> +static void meson_saradc_hw_disable(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> +
> + meson_saradc_lock(indio_dev);
> +
> + clk_disable_unprepare(priv->adc_clk);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN, 0);
> + regmap_update_bits(priv->regmap, SAR_ADC_REG11,
> + SAR_ADC_REG11_BANDGAP_EN, 0);
> +
> + clk_disable_unprepare(priv->sana_clk);
> + clk_disable_unprepare(priv->core_clk);
> +
> + regulator_disable(priv->vref);
> +
> + meson_saradc_unlock(indio_dev);
> +}
> +
> +static const struct iio_info meson_saradc_iio_info = {
> + .read_raw = meson_saradc_iio_info_read_raw,
> + .driver_module = THIS_MODULE,
> +};
> +
> +static const struct of_device_id meson_saradc_of_match[] = {
> + {
> + .compatible = "amlogic,meson-gxbb-saradc",
> + .data = (void *)10,
Might have been worth having a structure array indexed from an enum.
For now it is overkill, but seems likely there are a few other differences
that aren't supported yet?
> + }, {
> + .compatible = "amlogic,meson-gxl-saradc",
> + .data = (void *)12,
> + },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, meson_saradc_of_match);
> +
> +static int meson_saradc_probe(struct platform_device *pdev)
> +{
> + struct meson_saradc_priv *priv;
> + struct iio_dev *indio_dev;
> + struct resource *res;
> + void __iomem *base;
> + const struct of_device_id *match;
> + int ret;
> +
> + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
> + if (!indio_dev) {
> + dev_err(&pdev->dev, "failed allocating iio device\n");
> + return -ENOMEM;
> + }
> +
> + priv = iio_priv(indio_dev);
> +
> + match = of_match_device(meson_saradc_of_match, &pdev->dev);
> + priv->resolution = (unsigned long)match->data;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
> + &meson_saradc_regmap_config);
> + if (IS_ERR(priv->regmap))
> + return PTR_ERR(priv->regmap);
> +
> + init_completion(&priv->completion);
> +
> + priv->clkin = devm_clk_get(&pdev->dev, "clkin");
> + if (IS_ERR(priv->clkin)) {
> + dev_err(&pdev->dev, "failed to get clkin\n");
> + return PTR_ERR(priv->clkin);
> + }
> +
> + priv->core_clk = devm_clk_get(&pdev->dev, "core");
> + if (IS_ERR(priv->core_clk)) {
> + dev_err(&pdev->dev, "failed to get core clk\n");
> + return PTR_ERR(priv->core_clk);
> + }
> +
> + priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
Oh for a devm_clk_get_optional to handle this boiler plate neatly.
It's been suggested before, but nothing seems to have come of it.
Some array clk get functions might also clean this up a touch.
> + if (IS_ERR(priv->sana_clk)) {
> + if (PTR_ERR(priv->sana_clk) == -ENOENT) {
> + priv->sana_clk = NULL;
> + } else {
> + dev_err(&pdev->dev, "failed to get sana clk\n");
> + return PTR_ERR(priv->sana_clk);
> + }
> + }
> +
> + priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
> + if (IS_ERR(priv->adc_clk)) {
> + if (PTR_ERR(priv->adc_clk) == -ENOENT) {
> + priv->adc_clk = NULL;
> + } else {
> + dev_err(&pdev->dev, "failed to get adc clk\n");
> + return PTR_ERR(priv->adc_clk);
> + }
> + }
> +
> + priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
> + if (IS_ERR(priv->adc_sel_clk)) {
> + if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
> + priv->adc_sel_clk = NULL;
> + } else {
> + dev_err(&pdev->dev, "failed to get adc_sel clk\n");
> + return PTR_ERR(priv->adc_sel_clk);
> + }
> + }
> +
> + /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
> + if (!priv->adc_clk) {
> + ret = meson_saradc_clk_init(indio_dev, base);
> + if (ret)
> + return ret;
> + }
> +
> + priv->vref = devm_regulator_get(&pdev->dev, "vref");
> + if (IS_ERR(priv->vref)) {
> + dev_err(&pdev->dev, "failed to get vref regulator\n");
> + return PTR_ERR(priv->vref);
> + }
> +
> + ret = meson_saradc_init(indio_dev);
> + if (ret)
> + goto err;
> +
> + ret = meson_saradc_hw_enable(indio_dev);
> + if (ret)
> + goto err;
> +
> + platform_set_drvdata(pdev, indio_dev);
> +
> + indio_dev->name = dev_name(&pdev->dev);
> + indio_dev->dev.parent = &pdev->dev;
> + indio_dev->dev.of_node = pdev->dev.of_node;
> + indio_dev->modes = INDIO_DIRECT_MODE;
> + indio_dev->info = &meson_saradc_iio_info;
> +
> + indio_dev->channels = meson_saradc_iio_channels;
> + indio_dev->num_channels = SAR_ADC_NUM_CHANNELS;
> +
> + ret = iio_device_register(indio_dev);
> + if (ret)
> + goto err_hw;
> +
> + return 0;
> +
> +err_hw:
> + meson_saradc_hw_disable(indio_dev);
> +err:
> + return ret;
> +}
> +
> +static int meson_saradc_remove(struct platform_device *pdev)
> +{
> + struct iio_dev *indio_dev = platform_get_drvdata(pdev);
> +
> + meson_saradc_hw_disable(indio_dev);
> + iio_device_unregister(indio_dev);
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int meson_saradc_suspend(struct device *dev)
> +{
> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
> +
> + meson_saradc_hw_disable(indio_dev);
> +
> + return 0;
> +}
> +
> +static int meson_saradc_resume(struct device *dev)
> +{
> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
> +
> + return meson_saradc_hw_enable(indio_dev);
> +}
> +#endif /* CONFIG_PM_SLEEP */
> +
> +static SIMPLE_DEV_PM_OPS(meson_saradc_pm_ops,
> + meson_saradc_suspend, meson_saradc_resume);
> +
> +static struct platform_driver meson_saradc_driver = {
> + .probe = meson_saradc_probe,
> + .remove = meson_saradc_remove,
> + .driver = {
> + .name = "meson-saradc",
> + .of_match_table = meson_saradc_of_match,
> + .pm = &meson_saradc_pm_ops,
> + },
> +};
> +
> +module_platform_driver(meson_saradc_driver);
> +
> +MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
> +MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
> +MODULE_LICENSE("GPL v2");
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
@ 2017-01-14 14:46 ` Jonathan Cameron
0 siblings, 0 replies; 110+ messages in thread
From: Jonathan Cameron @ 2017-01-14 14:46 UTC (permalink / raw)
To: linux-arm-kernel
On 11/01/17 17:43, Martin Blumenstingl wrote:
> This adds support for the SAR (Successive Approximation Register) ADC
> on the Amlogic Meson SoCs.
>
> The code is based on the public S805 (Meson8b) and S905 (GXBB)
> datasheets, as well as by reading (various versions of) the vendor
> driver and by inspecting the registers on the vendor kernels of my
> testing-hardware.
>
> Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
> 10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
> The code was written to support older SoCs (Meson8 and Meson8b) as well,
> but due to lack of actual testing-hardware no of_device_id was added for
> these.
>
> Two "features" from the vendor driver are currently missing:
> - the vendor driver uses channel #7 for calibration (this improves the
> accuracy of the results - in my tests the results were less than 3%
> off without calibration compared to the vendor driver). Adding support
> for this should be easy, but is not required for most applications.
> - channel #6 is connected to the SoCs internal temperature sensor.
> Adding support for this is probably not so easy since (based on the
> u-boot sources) most SoC versions are using different registers and
> algorithms for the conversion from "ADC value" to temperature.
>
> Supported by the hardware but currently not supported by the driver:
> - reading multiple channels at the same time (the hardware has a FIFO
> buffer which stores multiple results)
> - continuous sampling (this would require a way to enable this
> individually because otherwise the ADC would be drawing power
> constantly)
> - interrupt support (similar to the vendor driver this new driver is
> polling the results. It is unclear if the IRQ-mode is supported on
> older (Meson6 or Meson8) hardware as well or if there are any errata)
>
Russell Cc'd for a quick question on the clk api.
Ideally include a source for datasheets if available. Saves time googling and
perhaps getting the wrong thing!
A few other minor comments inline. Pretty good V1.
Jonathan
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
> drivers/iio/adc/Kconfig | 12 +
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/meson_saradc.c | 860 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 873 insertions(+)
> create mode 100644 drivers/iio/adc/meson_saradc.c
>
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index 9c8b558ba19e..86059b9b91bf 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -371,6 +371,18 @@ config MEN_Z188_ADC
> This driver can also be built as a module. If so, the module will be
> called men_z188_adc.
>
> +config MESON_SARADC
> + tristate "Amlogic Meson SAR ADC driver"
> + default ARCH_MESON
> + depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
> + select REGMAP_MMIO
> + help
> + Say yes here to build support for the SAR ADC found in Amlogic Meson
> + SoCs.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called meson_saradc.
> +
> config MXS_LRADC
> tristate "Freescale i.MX23/i.MX28 LRADC"
> depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
> index d36c4be8d1fc..de05b9e75f8f 100644
> --- a/drivers/iio/adc/Makefile
> +++ b/drivers/iio/adc/Makefile
> @@ -36,6 +36,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
> obj-$(CONFIG_MCP3422) += mcp3422.o
> obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
> obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
> +obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
> obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
> obj-$(CONFIG_NAU7802) += nau7802.o
> obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
> diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
> new file mode 100644
> index 000000000000..06e8ac620385
> --- /dev/null
> +++ b/drivers/iio/adc/meson_saradc.c
> @@ -0,0 +1,860 @@
> +/*
> + * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
> + *
> + * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/iio/iio.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/clk.h>
> +#include <linux/completion.h>
> +#include <linux/delay.h>
> +#include <linux/reset.h>
> +#include <linux/regmap.h>
> +#include <linux/regulator/consumer.h>
> +
> +#define SAR_ADC_REG0 0x00
> + #define SAR_ADC_REG0_PANEL_DETECT BIT(31)
> + #define SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
> + #define SAR_ADC_REG0_DELTA_BUSY BIT(30)
> + #define SAR_ADC_REG0_AVG_BUSY BIT(29)
> + #define SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
> + #define SAR_ADC_REG0_FIFO_FULL BIT(27)
> + #define SAR_ADC_REG0_FIFO_EMPTY BIT(26)
> + #define SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
> + #define SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
> + #define SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
> + #define SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
> + #define SAR_ADC_REG0_SAMPLING_STOP BIT(14)
> + #define SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
> + #define SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
> + #define SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
> + #define SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
> + #define SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
> + #define SAR_ADC_REG0_SAMPLING_START BIT(2)
> + #define SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
> + #define SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
> +
> +#define SAR_ADC_CHAN_LIST 0x04
> + #define SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
> + #define SAR_ADC_CHAN_CHAN_ENTRY_MASK(_chan) \
> + (GENMASK(2, 0) << (_chan * 3))
> +
> +#define SAR_ADC_AVG_CNTL 0x08
> + #define SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
> + (16 + (_chan * 2))
> + #define SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
> + (GENMASK(17, 16) << (_chan * 2))
> + #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
> + (0 + (_chan * 2))
> + #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
> + (GENMASK(1, 0) << (_chan * 2))
> +
> +#define SAR_ADC_REG3 0x0c
> + #define SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
> + #define SAR_ADC_REG3_CLK_EN BIT(30)
> + #define SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
> + #define SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
> + #define SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
> + #define SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
> + #define SAR_ADC_REG3_DETECT_EN BIT(22)
> + #define SAR_ADC_REG3_ADC_EN BIT(21)
> + #define SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
> + #define SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
> + #define SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
> + #define SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
> + #define SAR_ADC_REG3_ADC_CLK_DIV_MASK GENMASK(15, 10)
> + #define SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
> + #define SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
> +
> +#define SAR_ADC_DELAY 0x10
> + #define SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
> + #define SAR_ADC_DELAY_BL30_BUSY BIT(15)
> + #define SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
> + #define SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
> + #define SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
> + #define SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
> +
> +#define SAR_ADC_LAST_RD 0x14
> + #define SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
> + #define SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
> +
> +#define SAR_ADC_FIFO_RD 0x18
> + #define SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
> + #define SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
> +
> +#define SAR_ADC_AUX_SW 0x1c
> + #define SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
> + (GENMASK(10, 8) << ((_chan - 2) * 2))
> + #define SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
> + #define SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
> + #define SAR_ADC_AUX_SW_MODE_SEL BIT(4)
> + #define SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
> + #define SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
> + #define SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
> + #define SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
> +
> +#define SAR_ADC_CHAN_10_SW 0x20
> + #define SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
> +
> +#define SAR_ADC_DETECT_IDLE_SW 0x24
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK GENMASK(25, 23)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_P_MUX BIT(22)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_N_MUX BIT(21)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YP_DRIVE_SW BIT(19)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XP_DRIVE_SW BIT(18)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YM_DRIVE_SW BIT(17)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XM_DRIVE_SW BIT(16)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK GENMASK(9, 7)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_P_MUX BIT(6)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_N_MUX BIT(5)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YP_DRIVE_SW BIT(3)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XP_DRIVE_SW BIT(2)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YM_DRIVE_SW BIT(1)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XM_DRIVE_SW BIT(0)
> +
> +#define SAR_ADC_DELTA_10 0x28
> + #define SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
> + #define SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
> + #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_SHIFT 16
> + #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
> + #define SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
> + #define SAR_ADC_DELTA_10_TS_C_SHIFT 11
> + #define SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
> + #define SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
> + #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_SHIFT 0
> + #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
> +
> +/* NOTE: registers from here are undocumented (the vendor Linux kernel driver
> + * and u-boot source served as reference). These only seem to be relevant on
> + * GXBB and newer.
> + */
> +#define SAR_ADC_REG11 0x2c
> + #define SAR_ADC_REG11_BANDGAP_EN BIT(13)
> +
> +#define SAR_ADC_REG13 0x34
> + #define SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
> +
> +#define SAR_ADC_MAX_FIFO_SIZE 32
> +#define SAR_ADC_NUM_CHANNELS ARRAY_SIZE(meson_saradc_iio_channels)
> +#define SAR_ADC_VALUE_MASK(_priv) (BIT(_priv->resolution) - 1)
> +
> +#define MESON_SAR_ADC_CHAN(_chan, _type) { \
> + .type = _type, \
> + .indexed = true, \
> + .channel = _chan, \
> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
> + BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
> + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
> + .datasheet_name = "SAR_ADC_CH"#_chan, \
> +}
> +
> +/* TODO: the hardware supports IIO_TEMP for channel 6 as well which is
Multline comment syntax.
> + * currently not supported by this driver.
> + */
> +static const struct iio_chan_spec meson_saradc_iio_channels[] = {
> + MESON_SAR_ADC_CHAN(0, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(1, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(2, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(3, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(4, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(5, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(6, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(7, IIO_VOLTAGE),
> + IIO_CHAN_SOFT_TIMESTAMP(8),
> +};
> +
> +enum meson_saradc_avg_mode {
> + NO_AVERAGING = 0x0,
> + MEAN_AVERAGING = 0x1,
> + MEDIAN_AVERAGING = 0x2,
> +};
> +
> +enum meson_saradc_num_samples {
> + ONE_SAMPLE = 0x0,
> + TWO_SAMPLES = 0x1,
> + FOUR_SAMPLES = 0x2,
> + EIGHT_SAMPLES = 0x3,
> +};
> +
> +enum meson_saradc_chan7_mux_sel {
> + CHAN7_MUX_VSS = 0x0,
> + CHAN7_MUX_VDD_DIV4 = 0x1,
> + CHAN7_MUX_VDD_DIV2 = 0x2,
> + CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
> + CHAN7_MUX_VDD = 0x4,
> + CHAN7_MUX_CH7_INPUT = 0x7,
> +};
> +
> +struct meson_saradc_priv {
> + struct regmap *regmap;
> + struct clk *clkin;
> + struct clk *core_clk;
> + struct clk *sana_clk;
> + struct clk *adc_sel_clk;
> + struct clk *adc_clk;
> + struct clk_gate clk_gate;
> + struct clk *adc_div_clk;
> + struct clk_divider clk_div;
> + struct regulator *vref;
> + struct completion completion;
> + u8 resolution;
> +};
> +
> +static const struct regmap_config meson_saradc_regmap_config = {
> + .reg_bits = 8,
> + .val_bits = 32,
> + .reg_stride = 4,
> + .max_register = SAR_ADC_REG13,
> +};
> +
> +static unsigned int meson_saradc_get_fifo_count(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + u32 regval;
> +
> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
> +
> + return FIELD_GET(SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
> +}
> +
> +static int meson_saradc_wait_busy_clear(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int regval, timeout = 10000;
> +
> + do {
> + udelay(1);
> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
> + } while (FIELD_GET(SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
> +
> + if (timeout < 0)
> + return -ETIMEDOUT;
> +
> + return 0;
> +}
> +
> +static int meson_saradc_read_raw_sample(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + int *val)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0;
> +
> + ret = meson_saradc_wait_busy_clear(indio_dev);
> + if (ret)
> + return ret;
> +
> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
> +
> + while (meson_saradc_get_fifo_count(indio_dev) > 0 &&
> + count < SAR_ADC_MAX_FIFO_SIZE) {
> + regmap_read(priv->regmap, SAR_ADC_FIFO_RD, ®val);
> +
> + fifo_chan = FIELD_GET(SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
> + if (fifo_chan == chan->channel) {
> + fifo_val = FIELD_GET(SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK,
> + regval) & SAR_ADC_VALUE_MASK(priv);
> + sum += fifo_val;
> + count++;
> + }
> + }
> +
> + if (!count)
> + return -ENOENT;
> +
> + *val = sum / count;
> +
> + return 0;
> +}
> +
> +static void meson_saradc_set_averaging(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + enum meson_saradc_avg_mode mode,
> + enum meson_saradc_num_samples samples)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + u32 val;
> +
> + val = samples << SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(chan->channel);
> + regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
> + SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(chan->channel),
> + val);
> +
> + val = mode << SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(chan->channel);
> + regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
> + SAR_ADC_AVG_CNTL_AVG_MODE_MASK(chan->channel), val);
> +}
> +
> +static void meson_saradc_enable_channel(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + u32 regval;
> +
> + /* the SAR ADC engine allows sampling multiple channels at the same
> + * time. to keep it simple we're only working with one *internal*
> + * channel, which starts counting at index 0 (which means: count = 1).
> + */
> + regval = FIELD_PREP(SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
> + regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
> + SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
> +
> + /* map channel index 0 to the channel which we want to read */
> + regval = FIELD_PREP(SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), chan->channel);
> + regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
> + SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), regval);
> +
> + regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
> + chan->channel);
> + regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
> + SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
> + regval);
> +
> + regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
> + chan->channel);
> + regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
> + SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
> + regval);
> +
> + if (chan->channel == 6)
> + regmap_update_bits(priv->regmap, SAR_ADC_DELTA_10,
> + SAR_ADC_DELTA_10_TEMP_SEL, 0);
> +}
> +
> +static void meson_saradc_set_channel7_mux(struct iio_dev *indio_dev,
> + enum meson_saradc_chan7_mux_sel sel)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + u32 regval;
> +
> + regval = FIELD_PREP(SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
> + SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
> +
> + usleep_range(10, 20);
> +}
> +
> +static void meson_saradc_start_sample_engine(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
> + SAR_ADC_REG0_SAMPLING_START,
> + SAR_ADC_REG0_SAMPLING_START);
> +}
> +
> +static void meson_saradc_stop_sample_engine(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
> + SAR_ADC_REG0_SAMPLING_STOP,
> + SAR_ADC_REG0_SAMPLING_STOP);
> +
> + /* wait until all modules are stopped */
> + meson_saradc_wait_busy_clear(indio_dev);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
> +}
> +
> +static void meson_saradc_lock(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int val;
> +
> + mutex_lock(&indio_dev->mlock);
> +
> + /* prevent BL30 from using the SAR ADC while we are using it */
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_KERNEL_BUSY,
> + SAR_ADC_DELAY_KERNEL_BUSY);
> +
> + /* wait until BL30 releases it's lock (so we can use the SAR ADC) */
> + do {
> + udelay(1);
> + regmap_read(priv->regmap, SAR_ADC_DELAY, &val);
> + } while (val & SAR_ADC_DELAY_BL30_BUSY);
> +}
> +
> +static void meson_saradc_unlock(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> +
> + /* allow BL30 to use the SAR ADC again */
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_KERNEL_BUSY, 0);
> +
> + mutex_unlock(&indio_dev->mlock);
> +}
> +
> +static int meson_saradc_get_sample(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + enum meson_saradc_avg_mode avg_mode,
> + enum meson_saradc_num_samples avg_samples,
> + int *val)
> +{
> + int ret, tmp;
> +
> + meson_saradc_lock(indio_dev);
> +
> + /* clear old values from the FIFO buffer, ignoring errors */
> + meson_saradc_read_raw_sample(indio_dev, chan, &tmp);
> +
> + meson_saradc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
> +
> + meson_saradc_enable_channel(indio_dev, chan);
> +
> + meson_saradc_start_sample_engine(indio_dev);
> + ret = meson_saradc_read_raw_sample(indio_dev, chan, val);
> + meson_saradc_stop_sample_engine(indio_dev);
> +
> + meson_saradc_unlock(indio_dev);
> +
> + if (ret) {
> + dev_warn(&indio_dev->dev,
> + "failed to read sample for channel %d: %d\n",
> + chan->channel, ret);
> + return ret;
> + }
> +
> + return IIO_VAL_INT;
> +}
> +
> +static int meson_saradc_iio_info_read_raw(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + int *val, int *val2, long mask)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int ret;
> +
> + switch (mask) {
> + case IIO_CHAN_INFO_RAW:
> + return meson_saradc_get_sample(indio_dev, chan, NO_AVERAGING,
> + ONE_SAMPLE, val);
> + break;
> +
> + case IIO_CHAN_INFO_AVERAGE_RAW:
> + return meson_saradc_get_sample(indio_dev, chan, MEAN_AVERAGING,
> + EIGHT_SAMPLES, val);
> + break;
> +
> + case IIO_CHAN_INFO_SCALE:
> + ret = regulator_get_voltage(priv->vref);
> + if (ret < 0) {
> + dev_err(&indio_dev->dev,
> + "failed to get vref voltage: %d\n", ret);
> + return ret;
> + }
> +
> + *val = ret / 1000;
> + *val2 = priv->resolution;
> + return IIO_VAL_FRACTIONAL_LOG2;
> +
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static int meson_saradc_clk_init(struct iio_dev *indio_dev, void __iomem *base)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + struct clk_init_data init;
> + char clk_name[32];
> + const char *clk_parents[1];
> +
> + snprintf(clk_name, sizeof(clk_name), "%s#adc_div",
> + of_node_full_name(indio_dev->dev.of_node));
> + init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
> + init.flags = 0;
> + init.ops = &clk_divider_ops;
> + clk_parents[0] = __clk_get_name(priv->clkin);
> + init.parent_names = clk_parents;
> + init.num_parents = 1;
> +
> + priv->clk_div.reg = base + SAR_ADC_REG3;
> + priv->clk_div.shift = SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
> + priv->clk_div.width = SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
> + priv->clk_div.hw.init = &init;
> + priv->clk_div.flags = 0;
> +
> + priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
> + &priv->clk_div.hw);
> + if (WARN_ON(IS_ERR(priv->adc_div_clk)))
> + return PTR_ERR(priv->adc_div_clk);
> +
> + snprintf(clk_name, sizeof(clk_name), "%s#adc_en",
> + of_node_full_name(indio_dev->dev.of_node));
> + init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
> + init.flags = CLK_SET_RATE_PARENT;
> + init.ops = &clk_gate_ops;
> + clk_parents[0] = __clk_get_name(priv->adc_div_clk);
> + init.parent_names = clk_parents;
> + init.num_parents = 1;
> +
> + priv->clk_gate.reg = base + SAR_ADC_REG3;
> + priv->clk_gate.bit_idx = fls(SAR_ADC_REG3_CLK_EN);
> + priv->clk_gate.hw.init = &init;
> +
> + priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
> + if (WARN_ON(IS_ERR(priv->adc_clk)))
> + return PTR_ERR(priv->adc_clk);
> +
> + return 0;
> +}
> +
> +static int meson_saradc_init(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int regval, ret;
> +
> + /* make sure we start at CH7 input */
why? Seems like a little more detail would be good here ;)
> + meson_saradc_set_channel7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
> +
> + regmap_read(priv->regmap, SAR_ADC_REG3, ®val);
> + if (regval & SAR_ADC_REG3_BL30_INITIALIZED) {
> + dev_info(&indio_dev->dev, "already initialized by BL30\n");
> + return 0;
> + }
> +
> + dev_info(&indio_dev->dev, "initializing SAR ADC\n");
I'd argue this provides no useful info so should be dropped.
Useful for debugging no doubt, but just noise going forward.
> +
> + meson_saradc_stop_sample_engine(indio_dev);
> +
> + /* update the channel 6 MUX to select the temperature sensor */
> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
> + SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
> + SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
> +
> + /* disable all channels by default */
> + regmap_write(priv->regmap, SAR_ADC_CHAN_LIST, 0x0);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
> + SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
> + SAR_ADC_REG3_CNTL_USE_SC_DLY,
> + SAR_ADC_REG3_CNTL_USE_SC_DLY);
> +
> + /* delay between two samples = (10+1) * 1uS */
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
> + FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK, 10));
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
> + FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 0));
> +
> + /* delay between two samples = (10+1) * 1uS */
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
> + FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 10));
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
> + FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 1));
> +
Cool. I hadn't come across FIELD_PREP before. Neater and tidier than having
a shift and a mask for at least some usecases.
> + ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
> + if (ret) {
> + dev_err(&indio_dev->dev,
> + "failed to set adc parent to clkin\n");
> + return ret;
> + }
> +
> + ret = clk_set_rate(priv->adc_clk, 1200000);
> + if (ret) {
> + dev_err(&indio_dev->dev, "failed to set adc clock rate\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int meson_saradc_hw_enable(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int ret;
> +
> + meson_saradc_lock(indio_dev);
> +
> + ret = regulator_enable(priv->vref);
> + if (ret < 0) {
> + dev_err(&indio_dev->dev, "failed to enable vref regulator\n");
> + goto err_vref;
> + }
> +
> + ret = clk_prepare_enable(priv->core_clk);
> + if (ret) {
> + dev_err(&indio_dev->dev, "failed to enable core clk\n");
> + goto err_core_clk;
> + }
> +
> + ret = clk_prepare_enable(priv->sana_clk);
> + if (ret) {
> + dev_err(&indio_dev->dev, "failed to enable sana clk\n");
> + goto err_sana_clk;
> + }
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG11,
> + SAR_ADC_REG11_BANDGAP_EN, SAR_ADC_REG11_BANDGAP_EN);
Is this controlling an offset for a bandgap or some actual electronics?
Not sure if it should be disabled on error and the datasheets I've found are
far from great! You disable it in the disable, so I'd expect it to be
unwound on error in here too.
> + regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN,
> + SAR_ADC_REG3_ADC_EN);
The fact you turn this of in the disable suggests to me that on error
you should be doing it in here too.
> +
> + udelay(5);
> +
> + ret = clk_prepare_enable(priv->adc_clk);
> + if (ret) {
> + dev_err(&indio_dev->dev, "failed to enable adc_en clk\n");
> + goto err_adc_clk;
> + }
> +
> + meson_saradc_unlock(indio_dev);
> +
> + return 0;
> +
> +err_adc_clk:
> + clk_disable_unprepare(priv->sana_clk);
> +err_sana_clk:
> + clk_disable_unprepare(priv->core_clk);
> +err_core_clk:
> + regulator_disable(priv->vref);
> +err_vref:
> + meson_saradc_unlock(indio_dev);
> + return ret;
> +}
> +
> +static void meson_saradc_hw_disable(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> +
> + meson_saradc_lock(indio_dev);
> +
> + clk_disable_unprepare(priv->adc_clk);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN, 0);
> + regmap_update_bits(priv->regmap, SAR_ADC_REG11,
> + SAR_ADC_REG11_BANDGAP_EN, 0);
> +
> + clk_disable_unprepare(priv->sana_clk);
> + clk_disable_unprepare(priv->core_clk);
> +
> + regulator_disable(priv->vref);
> +
> + meson_saradc_unlock(indio_dev);
> +}
> +
> +static const struct iio_info meson_saradc_iio_info = {
> + .read_raw = meson_saradc_iio_info_read_raw,
> + .driver_module = THIS_MODULE,
> +};
> +
> +static const struct of_device_id meson_saradc_of_match[] = {
> + {
> + .compatible = "amlogic,meson-gxbb-saradc",
> + .data = (void *)10,
Might have been worth having a structure array indexed from an enum.
For now it is overkill, but seems likely there are a few other differences
that aren't supported yet?
> + }, {
> + .compatible = "amlogic,meson-gxl-saradc",
> + .data = (void *)12,
> + },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, meson_saradc_of_match);
> +
> +static int meson_saradc_probe(struct platform_device *pdev)
> +{
> + struct meson_saradc_priv *priv;
> + struct iio_dev *indio_dev;
> + struct resource *res;
> + void __iomem *base;
> + const struct of_device_id *match;
> + int ret;
> +
> + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
> + if (!indio_dev) {
> + dev_err(&pdev->dev, "failed allocating iio device\n");
> + return -ENOMEM;
> + }
> +
> + priv = iio_priv(indio_dev);
> +
> + match = of_match_device(meson_saradc_of_match, &pdev->dev);
> + priv->resolution = (unsigned long)match->data;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
> + &meson_saradc_regmap_config);
> + if (IS_ERR(priv->regmap))
> + return PTR_ERR(priv->regmap);
> +
> + init_completion(&priv->completion);
> +
> + priv->clkin = devm_clk_get(&pdev->dev, "clkin");
> + if (IS_ERR(priv->clkin)) {
> + dev_err(&pdev->dev, "failed to get clkin\n");
> + return PTR_ERR(priv->clkin);
> + }
> +
> + priv->core_clk = devm_clk_get(&pdev->dev, "core");
> + if (IS_ERR(priv->core_clk)) {
> + dev_err(&pdev->dev, "failed to get core clk\n");
> + return PTR_ERR(priv->core_clk);
> + }
> +
> + priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
Oh for a devm_clk_get_optional to handle this boiler plate neatly.
It's been suggested before, but nothing seems to have come of it.
Some array clk get functions might also clean this up a touch.
> + if (IS_ERR(priv->sana_clk)) {
> + if (PTR_ERR(priv->sana_clk) == -ENOENT) {
> + priv->sana_clk = NULL;
> + } else {
> + dev_err(&pdev->dev, "failed to get sana clk\n");
> + return PTR_ERR(priv->sana_clk);
> + }
> + }
> +
> + priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
> + if (IS_ERR(priv->adc_clk)) {
> + if (PTR_ERR(priv->adc_clk) == -ENOENT) {
> + priv->adc_clk = NULL;
> + } else {
> + dev_err(&pdev->dev, "failed to get adc clk\n");
> + return PTR_ERR(priv->adc_clk);
> + }
> + }
> +
> + priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
> + if (IS_ERR(priv->adc_sel_clk)) {
> + if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
> + priv->adc_sel_clk = NULL;
> + } else {
> + dev_err(&pdev->dev, "failed to get adc_sel clk\n");
> + return PTR_ERR(priv->adc_sel_clk);
> + }
> + }
> +
> + /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
> + if (!priv->adc_clk) {
> + ret = meson_saradc_clk_init(indio_dev, base);
> + if (ret)
> + return ret;
> + }
> +
> + priv->vref = devm_regulator_get(&pdev->dev, "vref");
> + if (IS_ERR(priv->vref)) {
> + dev_err(&pdev->dev, "failed to get vref regulator\n");
> + return PTR_ERR(priv->vref);
> + }
> +
> + ret = meson_saradc_init(indio_dev);
> + if (ret)
> + goto err;
> +
> + ret = meson_saradc_hw_enable(indio_dev);
> + if (ret)
> + goto err;
> +
> + platform_set_drvdata(pdev, indio_dev);
> +
> + indio_dev->name = dev_name(&pdev->dev);
> + indio_dev->dev.parent = &pdev->dev;
> + indio_dev->dev.of_node = pdev->dev.of_node;
> + indio_dev->modes = INDIO_DIRECT_MODE;
> + indio_dev->info = &meson_saradc_iio_info;
> +
> + indio_dev->channels = meson_saradc_iio_channels;
> + indio_dev->num_channels = SAR_ADC_NUM_CHANNELS;
> +
> + ret = iio_device_register(indio_dev);
> + if (ret)
> + goto err_hw;
> +
> + return 0;
> +
> +err_hw:
> + meson_saradc_hw_disable(indio_dev);
> +err:
> + return ret;
> +}
> +
> +static int meson_saradc_remove(struct platform_device *pdev)
> +{
> + struct iio_dev *indio_dev = platform_get_drvdata(pdev);
> +
> + meson_saradc_hw_disable(indio_dev);
> + iio_device_unregister(indio_dev);
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int meson_saradc_suspend(struct device *dev)
> +{
> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
> +
> + meson_saradc_hw_disable(indio_dev);
> +
> + return 0;
> +}
> +
> +static int meson_saradc_resume(struct device *dev)
> +{
> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
> +
> + return meson_saradc_hw_enable(indio_dev);
> +}
> +#endif /* CONFIG_PM_SLEEP */
> +
> +static SIMPLE_DEV_PM_OPS(meson_saradc_pm_ops,
> + meson_saradc_suspend, meson_saradc_resume);
> +
> +static struct platform_driver meson_saradc_driver = {
> + .probe = meson_saradc_probe,
> + .remove = meson_saradc_remove,
> + .driver = {
> + .name = "meson-saradc",
> + .of_match_table = meson_saradc_of_match,
> + .pm = &meson_saradc_pm_ops,
> + },
> +};
> +
> +module_platform_driver(meson_saradc_driver);
> +
> +MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
> +MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
> +MODULE_LICENSE("GPL v2");
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
@ 2017-01-14 14:46 ` Jonathan Cameron
0 siblings, 0 replies; 110+ messages in thread
From: Jonathan Cameron @ 2017-01-14 14:46 UTC (permalink / raw)
To: linus-amlogic
On 11/01/17 17:43, Martin Blumenstingl wrote:
> This adds support for the SAR (Successive Approximation Register) ADC
> on the Amlogic Meson SoCs.
>
> The code is based on the public S805 (Meson8b) and S905 (GXBB)
> datasheets, as well as by reading (various versions of) the vendor
> driver and by inspecting the registers on the vendor kernels of my
> testing-hardware.
>
> Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
> 10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
> The code was written to support older SoCs (Meson8 and Meson8b) as well,
> but due to lack of actual testing-hardware no of_device_id was added for
> these.
>
> Two "features" from the vendor driver are currently missing:
> - the vendor driver uses channel #7 for calibration (this improves the
> accuracy of the results - in my tests the results were less than 3%
> off without calibration compared to the vendor driver). Adding support
> for this should be easy, but is not required for most applications.
> - channel #6 is connected to the SoCs internal temperature sensor.
> Adding support for this is probably not so easy since (based on the
> u-boot sources) most SoC versions are using different registers and
> algorithms for the conversion from "ADC value" to temperature.
>
> Supported by the hardware but currently not supported by the driver:
> - reading multiple channels at the same time (the hardware has a FIFO
> buffer which stores multiple results)
> - continuous sampling (this would require a way to enable this
> individually because otherwise the ADC would be drawing power
> constantly)
> - interrupt support (similar to the vendor driver this new driver is
> polling the results. It is unclear if the IRQ-mode is supported on
> older (Meson6 or Meson8) hardware as well or if there are any errata)
>
Russell Cc'd for a quick question on the clk api.
Ideally include a source for datasheets if available. Saves time googling and
perhaps getting the wrong thing!
A few other minor comments inline. Pretty good V1.
Jonathan
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
> drivers/iio/adc/Kconfig | 12 +
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/meson_saradc.c | 860 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 873 insertions(+)
> create mode 100644 drivers/iio/adc/meson_saradc.c
>
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index 9c8b558ba19e..86059b9b91bf 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -371,6 +371,18 @@ config MEN_Z188_ADC
> This driver can also be built as a module. If so, the module will be
> called men_z188_adc.
>
> +config MESON_SARADC
> + tristate "Amlogic Meson SAR ADC driver"
> + default ARCH_MESON
> + depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
> + select REGMAP_MMIO
> + help
> + Say yes here to build support for the SAR ADC found in Amlogic Meson
> + SoCs.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called meson_saradc.
> +
> config MXS_LRADC
> tristate "Freescale i.MX23/i.MX28 LRADC"
> depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
> index d36c4be8d1fc..de05b9e75f8f 100644
> --- a/drivers/iio/adc/Makefile
> +++ b/drivers/iio/adc/Makefile
> @@ -36,6 +36,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
> obj-$(CONFIG_MCP3422) += mcp3422.o
> obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
> obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
> +obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
> obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
> obj-$(CONFIG_NAU7802) += nau7802.o
> obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
> diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
> new file mode 100644
> index 000000000000..06e8ac620385
> --- /dev/null
> +++ b/drivers/iio/adc/meson_saradc.c
> @@ -0,0 +1,860 @@
> +/*
> + * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
> + *
> + * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/iio/iio.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/clk.h>
> +#include <linux/completion.h>
> +#include <linux/delay.h>
> +#include <linux/reset.h>
> +#include <linux/regmap.h>
> +#include <linux/regulator/consumer.h>
> +
> +#define SAR_ADC_REG0 0x00
> + #define SAR_ADC_REG0_PANEL_DETECT BIT(31)
> + #define SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
> + #define SAR_ADC_REG0_DELTA_BUSY BIT(30)
> + #define SAR_ADC_REG0_AVG_BUSY BIT(29)
> + #define SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
> + #define SAR_ADC_REG0_FIFO_FULL BIT(27)
> + #define SAR_ADC_REG0_FIFO_EMPTY BIT(26)
> + #define SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
> + #define SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
> + #define SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
> + #define SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
> + #define SAR_ADC_REG0_SAMPLING_STOP BIT(14)
> + #define SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
> + #define SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
> + #define SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
> + #define SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
> + #define SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
> + #define SAR_ADC_REG0_SAMPLING_START BIT(2)
> + #define SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
> + #define SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
> +
> +#define SAR_ADC_CHAN_LIST 0x04
> + #define SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
> + #define SAR_ADC_CHAN_CHAN_ENTRY_MASK(_chan) \
> + (GENMASK(2, 0) << (_chan * 3))
> +
> +#define SAR_ADC_AVG_CNTL 0x08
> + #define SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
> + (16 + (_chan * 2))
> + #define SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
> + (GENMASK(17, 16) << (_chan * 2))
> + #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
> + (0 + (_chan * 2))
> + #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
> + (GENMASK(1, 0) << (_chan * 2))
> +
> +#define SAR_ADC_REG3 0x0c
> + #define SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
> + #define SAR_ADC_REG3_CLK_EN BIT(30)
> + #define SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
> + #define SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
> + #define SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
> + #define SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
> + #define SAR_ADC_REG3_DETECT_EN BIT(22)
> + #define SAR_ADC_REG3_ADC_EN BIT(21)
> + #define SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
> + #define SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
> + #define SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
> + #define SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
> + #define SAR_ADC_REG3_ADC_CLK_DIV_MASK GENMASK(15, 10)
> + #define SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
> + #define SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
> +
> +#define SAR_ADC_DELAY 0x10
> + #define SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
> + #define SAR_ADC_DELAY_BL30_BUSY BIT(15)
> + #define SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
> + #define SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
> + #define SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
> + #define SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
> +
> +#define SAR_ADC_LAST_RD 0x14
> + #define SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
> + #define SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
> +
> +#define SAR_ADC_FIFO_RD 0x18
> + #define SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
> + #define SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
> +
> +#define SAR_ADC_AUX_SW 0x1c
> + #define SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
> + (GENMASK(10, 8) << ((_chan - 2) * 2))
> + #define SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
> + #define SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
> + #define SAR_ADC_AUX_SW_MODE_SEL BIT(4)
> + #define SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
> + #define SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
> + #define SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
> + #define SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
> +
> +#define SAR_ADC_CHAN_10_SW 0x20
> + #define SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
> +
> +#define SAR_ADC_DETECT_IDLE_SW 0x24
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK GENMASK(25, 23)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_P_MUX BIT(22)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_N_MUX BIT(21)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YP_DRIVE_SW BIT(19)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XP_DRIVE_SW BIT(18)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YM_DRIVE_SW BIT(17)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XM_DRIVE_SW BIT(16)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK GENMASK(9, 7)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_P_MUX BIT(6)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_N_MUX BIT(5)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YP_DRIVE_SW BIT(3)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XP_DRIVE_SW BIT(2)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YM_DRIVE_SW BIT(1)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XM_DRIVE_SW BIT(0)
> +
> +#define SAR_ADC_DELTA_10 0x28
> + #define SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
> + #define SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
> + #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_SHIFT 16
> + #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
> + #define SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
> + #define SAR_ADC_DELTA_10_TS_C_SHIFT 11
> + #define SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
> + #define SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
> + #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_SHIFT 0
> + #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
> +
> +/* NOTE: registers from here are undocumented (the vendor Linux kernel driver
> + * and u-boot source served as reference). These only seem to be relevant on
> + * GXBB and newer.
> + */
> +#define SAR_ADC_REG11 0x2c
> + #define SAR_ADC_REG11_BANDGAP_EN BIT(13)
> +
> +#define SAR_ADC_REG13 0x34
> + #define SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
> +
> +#define SAR_ADC_MAX_FIFO_SIZE 32
> +#define SAR_ADC_NUM_CHANNELS ARRAY_SIZE(meson_saradc_iio_channels)
> +#define SAR_ADC_VALUE_MASK(_priv) (BIT(_priv->resolution) - 1)
> +
> +#define MESON_SAR_ADC_CHAN(_chan, _type) { \
> + .type = _type, \
> + .indexed = true, \
> + .channel = _chan, \
> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
> + BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
> + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
> + .datasheet_name = "SAR_ADC_CH"#_chan, \
> +}
> +
> +/* TODO: the hardware supports IIO_TEMP for channel 6 as well which is
Multline comment syntax.
> + * currently not supported by this driver.
> + */
> +static const struct iio_chan_spec meson_saradc_iio_channels[] = {
> + MESON_SAR_ADC_CHAN(0, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(1, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(2, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(3, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(4, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(5, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(6, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(7, IIO_VOLTAGE),
> + IIO_CHAN_SOFT_TIMESTAMP(8),
> +};
> +
> +enum meson_saradc_avg_mode {
> + NO_AVERAGING = 0x0,
> + MEAN_AVERAGING = 0x1,
> + MEDIAN_AVERAGING = 0x2,
> +};
> +
> +enum meson_saradc_num_samples {
> + ONE_SAMPLE = 0x0,
> + TWO_SAMPLES = 0x1,
> + FOUR_SAMPLES = 0x2,
> + EIGHT_SAMPLES = 0x3,
> +};
> +
> +enum meson_saradc_chan7_mux_sel {
> + CHAN7_MUX_VSS = 0x0,
> + CHAN7_MUX_VDD_DIV4 = 0x1,
> + CHAN7_MUX_VDD_DIV2 = 0x2,
> + CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
> + CHAN7_MUX_VDD = 0x4,
> + CHAN7_MUX_CH7_INPUT = 0x7,
> +};
> +
> +struct meson_saradc_priv {
> + struct regmap *regmap;
> + struct clk *clkin;
> + struct clk *core_clk;
> + struct clk *sana_clk;
> + struct clk *adc_sel_clk;
> + struct clk *adc_clk;
> + struct clk_gate clk_gate;
> + struct clk *adc_div_clk;
> + struct clk_divider clk_div;
> + struct regulator *vref;
> + struct completion completion;
> + u8 resolution;
> +};
> +
> +static const struct regmap_config meson_saradc_regmap_config = {
> + .reg_bits = 8,
> + .val_bits = 32,
> + .reg_stride = 4,
> + .max_register = SAR_ADC_REG13,
> +};
> +
> +static unsigned int meson_saradc_get_fifo_count(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + u32 regval;
> +
> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
> +
> + return FIELD_GET(SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
> +}
> +
> +static int meson_saradc_wait_busy_clear(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int regval, timeout = 10000;
> +
> + do {
> + udelay(1);
> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
> + } while (FIELD_GET(SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
> +
> + if (timeout < 0)
> + return -ETIMEDOUT;
> +
> + return 0;
> +}
> +
> +static int meson_saradc_read_raw_sample(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + int *val)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0;
> +
> + ret = meson_saradc_wait_busy_clear(indio_dev);
> + if (ret)
> + return ret;
> +
> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
> +
> + while (meson_saradc_get_fifo_count(indio_dev) > 0 &&
> + count < SAR_ADC_MAX_FIFO_SIZE) {
> + regmap_read(priv->regmap, SAR_ADC_FIFO_RD, ®val);
> +
> + fifo_chan = FIELD_GET(SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
> + if (fifo_chan == chan->channel) {
> + fifo_val = FIELD_GET(SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK,
> + regval) & SAR_ADC_VALUE_MASK(priv);
> + sum += fifo_val;
> + count++;
> + }
> + }
> +
> + if (!count)
> + return -ENOENT;
> +
> + *val = sum / count;
> +
> + return 0;
> +}
> +
> +static void meson_saradc_set_averaging(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + enum meson_saradc_avg_mode mode,
> + enum meson_saradc_num_samples samples)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + u32 val;
> +
> + val = samples << SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(chan->channel);
> + regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
> + SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(chan->channel),
> + val);
> +
> + val = mode << SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(chan->channel);
> + regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
> + SAR_ADC_AVG_CNTL_AVG_MODE_MASK(chan->channel), val);
> +}
> +
> +static void meson_saradc_enable_channel(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + u32 regval;
> +
> + /* the SAR ADC engine allows sampling multiple channels at the same
> + * time. to keep it simple we're only working with one *internal*
> + * channel, which starts counting at index 0 (which means: count = 1).
> + */
> + regval = FIELD_PREP(SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
> + regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
> + SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
> +
> + /* map channel index 0 to the channel which we want to read */
> + regval = FIELD_PREP(SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), chan->channel);
> + regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
> + SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), regval);
> +
> + regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
> + chan->channel);
> + regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
> + SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
> + regval);
> +
> + regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
> + chan->channel);
> + regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
> + SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
> + regval);
> +
> + if (chan->channel == 6)
> + regmap_update_bits(priv->regmap, SAR_ADC_DELTA_10,
> + SAR_ADC_DELTA_10_TEMP_SEL, 0);
> +}
> +
> +static void meson_saradc_set_channel7_mux(struct iio_dev *indio_dev,
> + enum meson_saradc_chan7_mux_sel sel)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + u32 regval;
> +
> + regval = FIELD_PREP(SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
> + SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
> +
> + usleep_range(10, 20);
> +}
> +
> +static void meson_saradc_start_sample_engine(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
> + SAR_ADC_REG0_SAMPLING_START,
> + SAR_ADC_REG0_SAMPLING_START);
> +}
> +
> +static void meson_saradc_stop_sample_engine(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
> + SAR_ADC_REG0_SAMPLING_STOP,
> + SAR_ADC_REG0_SAMPLING_STOP);
> +
> + /* wait until all modules are stopped */
> + meson_saradc_wait_busy_clear(indio_dev);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
> +}
> +
> +static void meson_saradc_lock(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int val;
> +
> + mutex_lock(&indio_dev->mlock);
> +
> + /* prevent BL30 from using the SAR ADC while we are using it */
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_KERNEL_BUSY,
> + SAR_ADC_DELAY_KERNEL_BUSY);
> +
> + /* wait until BL30 releases it's lock (so we can use the SAR ADC) */
> + do {
> + udelay(1);
> + regmap_read(priv->regmap, SAR_ADC_DELAY, &val);
> + } while (val & SAR_ADC_DELAY_BL30_BUSY);
> +}
> +
> +static void meson_saradc_unlock(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> +
> + /* allow BL30 to use the SAR ADC again */
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_KERNEL_BUSY, 0);
> +
> + mutex_unlock(&indio_dev->mlock);
> +}
> +
> +static int meson_saradc_get_sample(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + enum meson_saradc_avg_mode avg_mode,
> + enum meson_saradc_num_samples avg_samples,
> + int *val)
> +{
> + int ret, tmp;
> +
> + meson_saradc_lock(indio_dev);
> +
> + /* clear old values from the FIFO buffer, ignoring errors */
> + meson_saradc_read_raw_sample(indio_dev, chan, &tmp);
> +
> + meson_saradc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
> +
> + meson_saradc_enable_channel(indio_dev, chan);
> +
> + meson_saradc_start_sample_engine(indio_dev);
> + ret = meson_saradc_read_raw_sample(indio_dev, chan, val);
> + meson_saradc_stop_sample_engine(indio_dev);
> +
> + meson_saradc_unlock(indio_dev);
> +
> + if (ret) {
> + dev_warn(&indio_dev->dev,
> + "failed to read sample for channel %d: %d\n",
> + chan->channel, ret);
> + return ret;
> + }
> +
> + return IIO_VAL_INT;
> +}
> +
> +static int meson_saradc_iio_info_read_raw(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + int *val, int *val2, long mask)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int ret;
> +
> + switch (mask) {
> + case IIO_CHAN_INFO_RAW:
> + return meson_saradc_get_sample(indio_dev, chan, NO_AVERAGING,
> + ONE_SAMPLE, val);
> + break;
> +
> + case IIO_CHAN_INFO_AVERAGE_RAW:
> + return meson_saradc_get_sample(indio_dev, chan, MEAN_AVERAGING,
> + EIGHT_SAMPLES, val);
> + break;
> +
> + case IIO_CHAN_INFO_SCALE:
> + ret = regulator_get_voltage(priv->vref);
> + if (ret < 0) {
> + dev_err(&indio_dev->dev,
> + "failed to get vref voltage: %d\n", ret);
> + return ret;
> + }
> +
> + *val = ret / 1000;
> + *val2 = priv->resolution;
> + return IIO_VAL_FRACTIONAL_LOG2;
> +
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static int meson_saradc_clk_init(struct iio_dev *indio_dev, void __iomem *base)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + struct clk_init_data init;
> + char clk_name[32];
> + const char *clk_parents[1];
> +
> + snprintf(clk_name, sizeof(clk_name), "%s#adc_div",
> + of_node_full_name(indio_dev->dev.of_node));
> + init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
> + init.flags = 0;
> + init.ops = &clk_divider_ops;
> + clk_parents[0] = __clk_get_name(priv->clkin);
> + init.parent_names = clk_parents;
> + init.num_parents = 1;
> +
> + priv->clk_div.reg = base + SAR_ADC_REG3;
> + priv->clk_div.shift = SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
> + priv->clk_div.width = SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
> + priv->clk_div.hw.init = &init;
> + priv->clk_div.flags = 0;
> +
> + priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
> + &priv->clk_div.hw);
> + if (WARN_ON(IS_ERR(priv->adc_div_clk)))
> + return PTR_ERR(priv->adc_div_clk);
> +
> + snprintf(clk_name, sizeof(clk_name), "%s#adc_en",
> + of_node_full_name(indio_dev->dev.of_node));
> + init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
> + init.flags = CLK_SET_RATE_PARENT;
> + init.ops = &clk_gate_ops;
> + clk_parents[0] = __clk_get_name(priv->adc_div_clk);
> + init.parent_names = clk_parents;
> + init.num_parents = 1;
> +
> + priv->clk_gate.reg = base + SAR_ADC_REG3;
> + priv->clk_gate.bit_idx = fls(SAR_ADC_REG3_CLK_EN);
> + priv->clk_gate.hw.init = &init;
> +
> + priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
> + if (WARN_ON(IS_ERR(priv->adc_clk)))
> + return PTR_ERR(priv->adc_clk);
> +
> + return 0;
> +}
> +
> +static int meson_saradc_init(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int regval, ret;
> +
> + /* make sure we start at CH7 input */
why? Seems like a little more detail would be good here ;)
> + meson_saradc_set_channel7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
> +
> + regmap_read(priv->regmap, SAR_ADC_REG3, ®val);
> + if (regval & SAR_ADC_REG3_BL30_INITIALIZED) {
> + dev_info(&indio_dev->dev, "already initialized by BL30\n");
> + return 0;
> + }
> +
> + dev_info(&indio_dev->dev, "initializing SAR ADC\n");
I'd argue this provides no useful info so should be dropped.
Useful for debugging no doubt, but just noise going forward.
> +
> + meson_saradc_stop_sample_engine(indio_dev);
> +
> + /* update the channel 6 MUX to select the temperature sensor */
> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
> + SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
> + SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
> +
> + /* disable all channels by default */
> + regmap_write(priv->regmap, SAR_ADC_CHAN_LIST, 0x0);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
> + SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
> + SAR_ADC_REG3_CNTL_USE_SC_DLY,
> + SAR_ADC_REG3_CNTL_USE_SC_DLY);
> +
> + /* delay between two samples = (10+1) * 1uS */
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
> + FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK, 10));
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
> + FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 0));
> +
> + /* delay between two samples = (10+1) * 1uS */
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
> + FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 10));
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
> + FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 1));
> +
Cool. I hadn't come across FIELD_PREP before. Neater and tidier than having
a shift and a mask for at least some usecases.
> + ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
> + if (ret) {
> + dev_err(&indio_dev->dev,
> + "failed to set adc parent to clkin\n");
> + return ret;
> + }
> +
> + ret = clk_set_rate(priv->adc_clk, 1200000);
> + if (ret) {
> + dev_err(&indio_dev->dev, "failed to set adc clock rate\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int meson_saradc_hw_enable(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int ret;
> +
> + meson_saradc_lock(indio_dev);
> +
> + ret = regulator_enable(priv->vref);
> + if (ret < 0) {
> + dev_err(&indio_dev->dev, "failed to enable vref regulator\n");
> + goto err_vref;
> + }
> +
> + ret = clk_prepare_enable(priv->core_clk);
> + if (ret) {
> + dev_err(&indio_dev->dev, "failed to enable core clk\n");
> + goto err_core_clk;
> + }
> +
> + ret = clk_prepare_enable(priv->sana_clk);
> + if (ret) {
> + dev_err(&indio_dev->dev, "failed to enable sana clk\n");
> + goto err_sana_clk;
> + }
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG11,
> + SAR_ADC_REG11_BANDGAP_EN, SAR_ADC_REG11_BANDGAP_EN);
Is this controlling an offset for a bandgap or some actual electronics?
Not sure if it should be disabled on error and the datasheets I've found are
far from great! You disable it in the disable, so I'd expect it to be
unwound on error in here too.
> + regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN,
> + SAR_ADC_REG3_ADC_EN);
The fact you turn this of in the disable suggests to me that on error
you should be doing it in here too.
> +
> + udelay(5);
> +
> + ret = clk_prepare_enable(priv->adc_clk);
> + if (ret) {
> + dev_err(&indio_dev->dev, "failed to enable adc_en clk\n");
> + goto err_adc_clk;
> + }
> +
> + meson_saradc_unlock(indio_dev);
> +
> + return 0;
> +
> +err_adc_clk:
> + clk_disable_unprepare(priv->sana_clk);
> +err_sana_clk:
> + clk_disable_unprepare(priv->core_clk);
> +err_core_clk:
> + regulator_disable(priv->vref);
> +err_vref:
> + meson_saradc_unlock(indio_dev);
> + return ret;
> +}
> +
> +static void meson_saradc_hw_disable(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> +
> + meson_saradc_lock(indio_dev);
> +
> + clk_disable_unprepare(priv->adc_clk);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN, 0);
> + regmap_update_bits(priv->regmap, SAR_ADC_REG11,
> + SAR_ADC_REG11_BANDGAP_EN, 0);
> +
> + clk_disable_unprepare(priv->sana_clk);
> + clk_disable_unprepare(priv->core_clk);
> +
> + regulator_disable(priv->vref);
> +
> + meson_saradc_unlock(indio_dev);
> +}
> +
> +static const struct iio_info meson_saradc_iio_info = {
> + .read_raw = meson_saradc_iio_info_read_raw,
> + .driver_module = THIS_MODULE,
> +};
> +
> +static const struct of_device_id meson_saradc_of_match[] = {
> + {
> + .compatible = "amlogic,meson-gxbb-saradc",
> + .data = (void *)10,
Might have been worth having a structure array indexed from an enum.
For now it is overkill, but seems likely there are a few other differences
that aren't supported yet?
> + }, {
> + .compatible = "amlogic,meson-gxl-saradc",
> + .data = (void *)12,
> + },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, meson_saradc_of_match);
> +
> +static int meson_saradc_probe(struct platform_device *pdev)
> +{
> + struct meson_saradc_priv *priv;
> + struct iio_dev *indio_dev;
> + struct resource *res;
> + void __iomem *base;
> + const struct of_device_id *match;
> + int ret;
> +
> + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
> + if (!indio_dev) {
> + dev_err(&pdev->dev, "failed allocating iio device\n");
> + return -ENOMEM;
> + }
> +
> + priv = iio_priv(indio_dev);
> +
> + match = of_match_device(meson_saradc_of_match, &pdev->dev);
> + priv->resolution = (unsigned long)match->data;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
> + &meson_saradc_regmap_config);
> + if (IS_ERR(priv->regmap))
> + return PTR_ERR(priv->regmap);
> +
> + init_completion(&priv->completion);
> +
> + priv->clkin = devm_clk_get(&pdev->dev, "clkin");
> + if (IS_ERR(priv->clkin)) {
> + dev_err(&pdev->dev, "failed to get clkin\n");
> + return PTR_ERR(priv->clkin);
> + }
> +
> + priv->core_clk = devm_clk_get(&pdev->dev, "core");
> + if (IS_ERR(priv->core_clk)) {
> + dev_err(&pdev->dev, "failed to get core clk\n");
> + return PTR_ERR(priv->core_clk);
> + }
> +
> + priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
Oh for a devm_clk_get_optional to handle this boiler plate neatly.
It's been suggested before, but nothing seems to have come of it.
Some array clk get functions might also clean this up a touch.
> + if (IS_ERR(priv->sana_clk)) {
> + if (PTR_ERR(priv->sana_clk) == -ENOENT) {
> + priv->sana_clk = NULL;
> + } else {
> + dev_err(&pdev->dev, "failed to get sana clk\n");
> + return PTR_ERR(priv->sana_clk);
> + }
> + }
> +
> + priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
> + if (IS_ERR(priv->adc_clk)) {
> + if (PTR_ERR(priv->adc_clk) == -ENOENT) {
> + priv->adc_clk = NULL;
> + } else {
> + dev_err(&pdev->dev, "failed to get adc clk\n");
> + return PTR_ERR(priv->adc_clk);
> + }
> + }
> +
> + priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
> + if (IS_ERR(priv->adc_sel_clk)) {
> + if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
> + priv->adc_sel_clk = NULL;
> + } else {
> + dev_err(&pdev->dev, "failed to get adc_sel clk\n");
> + return PTR_ERR(priv->adc_sel_clk);
> + }
> + }
> +
> + /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
> + if (!priv->adc_clk) {
> + ret = meson_saradc_clk_init(indio_dev, base);
> + if (ret)
> + return ret;
> + }
> +
> + priv->vref = devm_regulator_get(&pdev->dev, "vref");
> + if (IS_ERR(priv->vref)) {
> + dev_err(&pdev->dev, "failed to get vref regulator\n");
> + return PTR_ERR(priv->vref);
> + }
> +
> + ret = meson_saradc_init(indio_dev);
> + if (ret)
> + goto err;
> +
> + ret = meson_saradc_hw_enable(indio_dev);
> + if (ret)
> + goto err;
> +
> + platform_set_drvdata(pdev, indio_dev);
> +
> + indio_dev->name = dev_name(&pdev->dev);
> + indio_dev->dev.parent = &pdev->dev;
> + indio_dev->dev.of_node = pdev->dev.of_node;
> + indio_dev->modes = INDIO_DIRECT_MODE;
> + indio_dev->info = &meson_saradc_iio_info;
> +
> + indio_dev->channels = meson_saradc_iio_channels;
> + indio_dev->num_channels = SAR_ADC_NUM_CHANNELS;
> +
> + ret = iio_device_register(indio_dev);
> + if (ret)
> + goto err_hw;
> +
> + return 0;
> +
> +err_hw:
> + meson_saradc_hw_disable(indio_dev);
> +err:
> + return ret;
> +}
> +
> +static int meson_saradc_remove(struct platform_device *pdev)
> +{
> + struct iio_dev *indio_dev = platform_get_drvdata(pdev);
> +
> + meson_saradc_hw_disable(indio_dev);
> + iio_device_unregister(indio_dev);
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int meson_saradc_suspend(struct device *dev)
> +{
> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
> +
> + meson_saradc_hw_disable(indio_dev);
> +
> + return 0;
> +}
> +
> +static int meson_saradc_resume(struct device *dev)
> +{
> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
> +
> + return meson_saradc_hw_enable(indio_dev);
> +}
> +#endif /* CONFIG_PM_SLEEP */
> +
> +static SIMPLE_DEV_PM_OPS(meson_saradc_pm_ops,
> + meson_saradc_suspend, meson_saradc_resume);
> +
> +static struct platform_driver meson_saradc_driver = {
> + .probe = meson_saradc_probe,
> + .remove = meson_saradc_remove,
> + .driver = {
> + .name = "meson-saradc",
> + .of_match_table = meson_saradc_of_match,
> + .pm = &meson_saradc_pm_ops,
> + },
> +};
> +
> +module_platform_driver(meson_saradc_driver);
> +
> +MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
> +MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
> +MODULE_LICENSE("GPL v2");
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
2017-01-14 14:46 ` Jonathan Cameron
(?)
(?)
@ 2017-01-14 17:44 ` Martin Blumenstingl
-1 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-14 17:44 UTC (permalink / raw)
To: Jonathan Cameron
Cc: knaack.h-Mmb7MZpHnFY, lars-Qo5EllUWu/uELgA04lAiVw,
pmeerw-jW+XmwGofnusTnJN9+BGXg, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, khilman-rdvid1DuHRBWk0Htik3J/w,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-clk-u79uwXL29TY76Z2rM5mHXA, carlo-KA+7E9HrN00dnm+yROfE0A,
catalin.marinas-5wv7dgnIgG8, will.deacon-5wv7dgnIgG8,
mturquette-rdvid1DuHRBWk0Htik3J/w, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
narmstrong-rdvid1DuHRBWk0Htik3J/w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Russell King
Hi Jonathan,
thank you for the review!
(further comments from me inline)
I think I'll send an updated version on Monday.
On Sat, Jan 14, 2017 at 3:46 PM, Jonathan Cameron <jic23-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> On 11/01/17 17:43, Martin Blumenstingl wrote:
>> This adds support for the SAR (Successive Approximation Register) ADC
>> on the Amlogic Meson SoCs.
>>
>> The code is based on the public S805 (Meson8b) and S905 (GXBB)
>> datasheets, as well as by reading (various versions of) the vendor
>> driver and by inspecting the registers on the vendor kernels of my
>> testing-hardware.
>>
>> Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
>> 10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
>> The code was written to support older SoCs (Meson8 and Meson8b) as well,
>> but due to lack of actual testing-hardware no of_device_id was added for
>> these.
>>
>> Two "features" from the vendor driver are currently missing:
>> - the vendor driver uses channel #7 for calibration (this improves the
>> accuracy of the results - in my tests the results were less than 3%
>> off without calibration compared to the vendor driver). Adding support
>> for this should be easy, but is not required for most applications.
>> - channel #6 is connected to the SoCs internal temperature sensor.
>> Adding support for this is probably not so easy since (based on the
>> u-boot sources) most SoC versions are using different registers and
>> algorithms for the conversion from "ADC value" to temperature.
>>
>> Supported by the hardware but currently not supported by the driver:
>> - reading multiple channels at the same time (the hardware has a FIFO
>> buffer which stores multiple results)
>> - continuous sampling (this would require a way to enable this
>> individually because otherwise the ADC would be drawing power
>> constantly)
>> - interrupt support (similar to the vendor driver this new driver is
>> polling the results. It is unclear if the IRQ-mode is supported on
>> older (Meson6 or Meson8) hardware as well or if there are any errata)
>>
> Russell Cc'd for a quick question on the clk api.
a quick side-note the clk API: my driver is a clock consumer and
provider at the same time. This seems to be a recurring pattern in
Amlogic hardware designs (as the MMC and DWMAC glue drivers are doing
this also), see [0]
> Ideally include a source for datasheets if available. Saves time googling and
> perhaps getting the wrong thing!
OK, will do this in v2
> A few other minor comments inline. Pretty good V1.
thanks :-)
> Jonathan
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>> ---
>> drivers/iio/adc/Kconfig | 12 +
>> drivers/iio/adc/Makefile | 1 +
>> drivers/iio/adc/meson_saradc.c | 860 +++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 873 insertions(+)
>> create mode 100644 drivers/iio/adc/meson_saradc.c
>>
>> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
>> index 9c8b558ba19e..86059b9b91bf 100644
>> --- a/drivers/iio/adc/Kconfig
>> +++ b/drivers/iio/adc/Kconfig
>> @@ -371,6 +371,18 @@ config MEN_Z188_ADC
>> This driver can also be built as a module. If so, the module will be
>> called men_z188_adc.
>>
>> +config MESON_SARADC
>> + tristate "Amlogic Meson SAR ADC driver"
>> + default ARCH_MESON
>> + depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
>> + select REGMAP_MMIO
>> + help
>> + Say yes here to build support for the SAR ADC found in Amlogic Meson
>> + SoCs.
>> +
>> + To compile this driver as a module, choose M here: the
>> + module will be called meson_saradc.
>> +
>> config MXS_LRADC
>> tristate "Freescale i.MX23/i.MX28 LRADC"
>> depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
>> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
>> index d36c4be8d1fc..de05b9e75f8f 100644
>> --- a/drivers/iio/adc/Makefile
>> +++ b/drivers/iio/adc/Makefile
>> @@ -36,6 +36,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
>> obj-$(CONFIG_MCP3422) += mcp3422.o
>> obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
>> obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
>> +obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
>> obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
>> obj-$(CONFIG_NAU7802) += nau7802.o
>> obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
>> diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
>> new file mode 100644
>> index 000000000000..06e8ac620385
>> --- /dev/null
>> +++ b/drivers/iio/adc/meson_saradc.c
>> @@ -0,0 +1,860 @@
>> +/*
>> + * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
>> + *
>> + * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#include <linux/bitfield.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/io.h>
>> +#include <linux/iio/iio.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>> +#include <linux/clk.h>
>> +#include <linux/completion.h>
>> +#include <linux/delay.h>
>> +#include <linux/reset.h>
>> +#include <linux/regmap.h>
>> +#include <linux/regulator/consumer.h>
>> +
>> +#define SAR_ADC_REG0 0x00
>> + #define SAR_ADC_REG0_PANEL_DETECT BIT(31)
>> + #define SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
>> + #define SAR_ADC_REG0_DELTA_BUSY BIT(30)
>> + #define SAR_ADC_REG0_AVG_BUSY BIT(29)
>> + #define SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
>> + #define SAR_ADC_REG0_FIFO_FULL BIT(27)
>> + #define SAR_ADC_REG0_FIFO_EMPTY BIT(26)
>> + #define SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
>> + #define SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
>> + #define SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
>> + #define SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
>> + #define SAR_ADC_REG0_SAMPLING_STOP BIT(14)
>> + #define SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
>> + #define SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
>> + #define SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
>> + #define SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
>> + #define SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
>> + #define SAR_ADC_REG0_SAMPLING_START BIT(2)
>> + #define SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
>> + #define SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
>> +
>> +#define SAR_ADC_CHAN_LIST 0x04
>> + #define SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
>> + #define SAR_ADC_CHAN_CHAN_ENTRY_MASK(_chan) \
>> + (GENMASK(2, 0) << (_chan * 3))
>> +
>> +#define SAR_ADC_AVG_CNTL 0x08
>> + #define SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
>> + (16 + (_chan * 2))
>> + #define SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
>> + (GENMASK(17, 16) << (_chan * 2))
>> + #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
>> + (0 + (_chan * 2))
>> + #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
>> + (GENMASK(1, 0) << (_chan * 2))
>> +
>> +#define SAR_ADC_REG3 0x0c
>> + #define SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
>> + #define SAR_ADC_REG3_CLK_EN BIT(30)
>> + #define SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
>> + #define SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
>> + #define SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
>> + #define SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
>> + #define SAR_ADC_REG3_DETECT_EN BIT(22)
>> + #define SAR_ADC_REG3_ADC_EN BIT(21)
>> + #define SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
>> + #define SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
>> + #define SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
>> + #define SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
>> + #define SAR_ADC_REG3_ADC_CLK_DIV_MASK GENMASK(15, 10)
>> + #define SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
>> + #define SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
>> +
>> +#define SAR_ADC_DELAY 0x10
>> + #define SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
>> + #define SAR_ADC_DELAY_BL30_BUSY BIT(15)
>> + #define SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
>> + #define SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
>> + #define SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
>> + #define SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
>> +
>> +#define SAR_ADC_LAST_RD 0x14
>> + #define SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
>> + #define SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
>> +
>> +#define SAR_ADC_FIFO_RD 0x18
>> + #define SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
>> + #define SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
>> +
>> +#define SAR_ADC_AUX_SW 0x1c
>> + #define SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
>> + (GENMASK(10, 8) << ((_chan - 2) * 2))
>> + #define SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
>> + #define SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
>> + #define SAR_ADC_AUX_SW_MODE_SEL BIT(4)
>> + #define SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
>> + #define SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
>> + #define SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
>> + #define SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
>> +
>> +#define SAR_ADC_CHAN_10_SW 0x20
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
>> +
>> +#define SAR_ADC_DETECT_IDLE_SW 0x24
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK GENMASK(25, 23)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_P_MUX BIT(22)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_N_MUX BIT(21)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YP_DRIVE_SW BIT(19)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XP_DRIVE_SW BIT(18)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YM_DRIVE_SW BIT(17)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XM_DRIVE_SW BIT(16)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK GENMASK(9, 7)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_P_MUX BIT(6)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_N_MUX BIT(5)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YP_DRIVE_SW BIT(3)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XP_DRIVE_SW BIT(2)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YM_DRIVE_SW BIT(1)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XM_DRIVE_SW BIT(0)
>> +
>> +#define SAR_ADC_DELTA_10 0x28
>> + #define SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
>> + #define SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
>> + #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_SHIFT 16
>> + #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
>> + #define SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
>> + #define SAR_ADC_DELTA_10_TS_C_SHIFT 11
>> + #define SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
>> + #define SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
>> + #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_SHIFT 0
>> + #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
>> +
>> +/* NOTE: registers from here are undocumented (the vendor Linux kernel driver
>> + * and u-boot source served as reference). These only seem to be relevant on
>> + * GXBB and newer.
>> + */
>> +#define SAR_ADC_REG11 0x2c
>> + #define SAR_ADC_REG11_BANDGAP_EN BIT(13)
>> +
>> +#define SAR_ADC_REG13 0x34
>> + #define SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
>> +
>> +#define SAR_ADC_MAX_FIFO_SIZE 32
>> +#define SAR_ADC_NUM_CHANNELS ARRAY_SIZE(meson_saradc_iio_channels)
>> +#define SAR_ADC_VALUE_MASK(_priv) (BIT(_priv->resolution) - 1)
>> +
>> +#define MESON_SAR_ADC_CHAN(_chan, _type) { \
>> + .type = _type, \
>> + .indexed = true, \
>> + .channel = _chan, \
>> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
>> + BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
>> + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
>> + .datasheet_name = "SAR_ADC_CH"#_chan, \
>> +}
>> +
>> +/* TODO: the hardware supports IIO_TEMP for channel 6 as well which is
> Multline comment syntax.
I got this wrong in 2 other places as well. will be fixed in v2, thanks!
>> + * currently not supported by this driver.
>> + */
>> +static const struct iio_chan_spec meson_saradc_iio_channels[] = {
>> + MESON_SAR_ADC_CHAN(0, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(1, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(2, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(3, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(4, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(5, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(6, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(7, IIO_VOLTAGE),
>> + IIO_CHAN_SOFT_TIMESTAMP(8),
>> +};
>> +
>> +enum meson_saradc_avg_mode {
>> + NO_AVERAGING = 0x0,
>> + MEAN_AVERAGING = 0x1,
>> + MEDIAN_AVERAGING = 0x2,
>> +};
>> +
>> +enum meson_saradc_num_samples {
>> + ONE_SAMPLE = 0x0,
>> + TWO_SAMPLES = 0x1,
>> + FOUR_SAMPLES = 0x2,
>> + EIGHT_SAMPLES = 0x3,
>> +};
>> +
>> +enum meson_saradc_chan7_mux_sel {
>> + CHAN7_MUX_VSS = 0x0,
>> + CHAN7_MUX_VDD_DIV4 = 0x1,
>> + CHAN7_MUX_VDD_DIV2 = 0x2,
>> + CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
>> + CHAN7_MUX_VDD = 0x4,
>> + CHAN7_MUX_CH7_INPUT = 0x7,
>> +};
>> +
>> +struct meson_saradc_priv {
>> + struct regmap *regmap;
>> + struct clk *clkin;
>> + struct clk *core_clk;
>> + struct clk *sana_clk;
>> + struct clk *adc_sel_clk;
>> + struct clk *adc_clk;
>> + struct clk_gate clk_gate;
>> + struct clk *adc_div_clk;
>> + struct clk_divider clk_div;
>> + struct regulator *vref;
>> + struct completion completion;
>> + u8 resolution;
>> +};
>> +
>> +static const struct regmap_config meson_saradc_regmap_config = {
>> + .reg_bits = 8,
>> + .val_bits = 32,
>> + .reg_stride = 4,
>> + .max_register = SAR_ADC_REG13,
>> +};
>> +
>> +static unsigned int meson_saradc_get_fifo_count(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + u32 regval;
>> +
>> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
>> +
>> + return FIELD_GET(SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
>> +}
>> +
>> +static int meson_saradc_wait_busy_clear(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + int regval, timeout = 10000;
>> +
>> + do {
>> + udelay(1);
>> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
>> + } while (FIELD_GET(SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
>> +
>> + if (timeout < 0)
>> + return -ETIMEDOUT;
>> +
>> + return 0;
>> +}
>> +
>> +static int meson_saradc_read_raw_sample(struct iio_dev *indio_dev,
>> + const struct iio_chan_spec *chan,
>> + int *val)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0;
>> +
>> + ret = meson_saradc_wait_busy_clear(indio_dev);
>> + if (ret)
>> + return ret;
>> +
>> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
>> +
>> + while (meson_saradc_get_fifo_count(indio_dev) > 0 &&
>> + count < SAR_ADC_MAX_FIFO_SIZE) {
>> + regmap_read(priv->regmap, SAR_ADC_FIFO_RD, ®val);
>> +
>> + fifo_chan = FIELD_GET(SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
>> + if (fifo_chan == chan->channel) {
>> + fifo_val = FIELD_GET(SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK,
>> + regval) & SAR_ADC_VALUE_MASK(priv);
>> + sum += fifo_val;
>> + count++;
>> + }
>> + }
>> +
>> + if (!count)
>> + return -ENOENT;
>> +
>> + *val = sum / count;
>> +
>> + return 0;
>> +}
>> +
>> +static void meson_saradc_set_averaging(struct iio_dev *indio_dev,
>> + const struct iio_chan_spec *chan,
>> + enum meson_saradc_avg_mode mode,
>> + enum meson_saradc_num_samples samples)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + u32 val;
>> +
>> + val = samples << SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(chan->channel);
>> + regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
>> + SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(chan->channel),
>> + val);
>> +
>> + val = mode << SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(chan->channel);
>> + regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
>> + SAR_ADC_AVG_CNTL_AVG_MODE_MASK(chan->channel), val);
>> +}
>> +
>> +static void meson_saradc_enable_channel(struct iio_dev *indio_dev,
>> + const struct iio_chan_spec *chan)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + u32 regval;
>> +
>> + /* the SAR ADC engine allows sampling multiple channels at the same
>> + * time. to keep it simple we're only working with one *internal*
>> + * channel, which starts counting at index 0 (which means: count = 1).
>> + */
>> + regval = FIELD_PREP(SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
>> + regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
>> + SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
>> +
>> + /* map channel index 0 to the channel which we want to read */
>> + regval = FIELD_PREP(SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), chan->channel);
>> + regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
>> + SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), regval);
>> +
>> + regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
>> + chan->channel);
>> + regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
>> + SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
>> + regval);
>> +
>> + regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
>> + chan->channel);
>> + regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
>> + SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
>> + regval);
>> +
>> + if (chan->channel == 6)
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELTA_10,
>> + SAR_ADC_DELTA_10_TEMP_SEL, 0);
>> +}
>> +
>> +static void meson_saradc_set_channel7_mux(struct iio_dev *indio_dev,
>> + enum meson_saradc_chan7_mux_sel sel)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + u32 regval;
>> +
>> + regval = FIELD_PREP(SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
>> + SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
>> +
>> + usleep_range(10, 20);
>> +}
>> +
>> +static void meson_saradc_start_sample_engine(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
>> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>> + SAR_ADC_REG0_SAMPLING_START,
>> + SAR_ADC_REG0_SAMPLING_START);
>> +}
>> +
>> +static void meson_saradc_stop_sample_engine(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>> + SAR_ADC_REG0_SAMPLING_STOP,
>> + SAR_ADC_REG0_SAMPLING_STOP);
>> +
>> + /* wait until all modules are stopped */
>> + meson_saradc_wait_busy_clear(indio_dev);
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
>> +}
>> +
>> +static void meson_saradc_lock(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + int val;
>> +
>> + mutex_lock(&indio_dev->mlock);
>> +
>> + /* prevent BL30 from using the SAR ADC while we are using it */
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>> + SAR_ADC_DELAY_KERNEL_BUSY,
>> + SAR_ADC_DELAY_KERNEL_BUSY);
>> +
>> + /* wait until BL30 releases it's lock (so we can use the SAR ADC) */
>> + do {
>> + udelay(1);
>> + regmap_read(priv->regmap, SAR_ADC_DELAY, &val);
>> + } while (val & SAR_ADC_DELAY_BL30_BUSY);
>> +}
>> +
>> +static void meson_saradc_unlock(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> +
>> + /* allow BL30 to use the SAR ADC again */
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>> + SAR_ADC_DELAY_KERNEL_BUSY, 0);
>> +
>> + mutex_unlock(&indio_dev->mlock);
>> +}
>> +
>> +static int meson_saradc_get_sample(struct iio_dev *indio_dev,
>> + const struct iio_chan_spec *chan,
>> + enum meson_saradc_avg_mode avg_mode,
>> + enum meson_saradc_num_samples avg_samples,
>> + int *val)
>> +{
>> + int ret, tmp;
>> +
>> + meson_saradc_lock(indio_dev);
>> +
>> + /* clear old values from the FIFO buffer, ignoring errors */
>> + meson_saradc_read_raw_sample(indio_dev, chan, &tmp);
>> +
>> + meson_saradc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
>> +
>> + meson_saradc_enable_channel(indio_dev, chan);
>> +
>> + meson_saradc_start_sample_engine(indio_dev);
>> + ret = meson_saradc_read_raw_sample(indio_dev, chan, val);
>> + meson_saradc_stop_sample_engine(indio_dev);
>> +
>> + meson_saradc_unlock(indio_dev);
>> +
>> + if (ret) {
>> + dev_warn(&indio_dev->dev,
>> + "failed to read sample for channel %d: %d\n",
>> + chan->channel, ret);
>> + return ret;
>> + }
>> +
>> + return IIO_VAL_INT;
>> +}
>> +
>> +static int meson_saradc_iio_info_read_raw(struct iio_dev *indio_dev,
>> + const struct iio_chan_spec *chan,
>> + int *val, int *val2, long mask)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + int ret;
>> +
>> + switch (mask) {
>> + case IIO_CHAN_INFO_RAW:
>> + return meson_saradc_get_sample(indio_dev, chan, NO_AVERAGING,
>> + ONE_SAMPLE, val);
>> + break;
>> +
>> + case IIO_CHAN_INFO_AVERAGE_RAW:
>> + return meson_saradc_get_sample(indio_dev, chan, MEAN_AVERAGING,
>> + EIGHT_SAMPLES, val);
>> + break;
>> +
>> + case IIO_CHAN_INFO_SCALE:
>> + ret = regulator_get_voltage(priv->vref);
>> + if (ret < 0) {
>> + dev_err(&indio_dev->dev,
>> + "failed to get vref voltage: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + *val = ret / 1000;
>> + *val2 = priv->resolution;
>> + return IIO_VAL_FRACTIONAL_LOG2;
>> +
>> + default:
>> + return -EINVAL;
>> + }
>> +}
>> +
>> +static int meson_saradc_clk_init(struct iio_dev *indio_dev, void __iomem *base)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + struct clk_init_data init;
>> + char clk_name[32];
>> + const char *clk_parents[1];
>> +
>> + snprintf(clk_name, sizeof(clk_name), "%s#adc_div",
>> + of_node_full_name(indio_dev->dev.of_node));
>> + init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
>> + init.flags = 0;
>> + init.ops = &clk_divider_ops;
>> + clk_parents[0] = __clk_get_name(priv->clkin);
>> + init.parent_names = clk_parents;
>> + init.num_parents = 1;
>> +
>> + priv->clk_div.reg = base + SAR_ADC_REG3;
>> + priv->clk_div.shift = SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
>> + priv->clk_div.width = SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
>> + priv->clk_div.hw.init = &init;
>> + priv->clk_div.flags = 0;
>> +
>> + priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
>> + &priv->clk_div.hw);
>> + if (WARN_ON(IS_ERR(priv->adc_div_clk)))
>> + return PTR_ERR(priv->adc_div_clk);
>> +
>> + snprintf(clk_name, sizeof(clk_name), "%s#adc_en",
>> + of_node_full_name(indio_dev->dev.of_node));
>> + init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
>> + init.flags = CLK_SET_RATE_PARENT;
>> + init.ops = &clk_gate_ops;
>> + clk_parents[0] = __clk_get_name(priv->adc_div_clk);
>> + init.parent_names = clk_parents;
>> + init.num_parents = 1;
>> +
>> + priv->clk_gate.reg = base + SAR_ADC_REG3;
>> + priv->clk_gate.bit_idx = fls(SAR_ADC_REG3_CLK_EN);
>> + priv->clk_gate.hw.init = &init;
>> +
>> + priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
>> + if (WARN_ON(IS_ERR(priv->adc_clk)))
>> + return PTR_ERR(priv->adc_clk);
>> +
>> + return 0;
>> +}
>> +
>> +static int meson_saradc_init(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + int regval, ret;
>> +
>> + /* make sure we start at CH7 input */
> why? Seems like a little more detail would be good here ;)
I'll change this to "make sure we start at CH7 input since the other
muxes are only used for internal calibration." in v2
>> + meson_saradc_set_channel7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
>> +
>> + regmap_read(priv->regmap, SAR_ADC_REG3, ®val);
>> + if (regval & SAR_ADC_REG3_BL30_INITIALIZED) {
>> + dev_info(&indio_dev->dev, "already initialized by BL30\n");
>> + return 0;
>> + }
>> +
>> + dev_info(&indio_dev->dev, "initializing SAR ADC\n");
> I'd argue this provides no useful info so should be dropped.
> Useful for debugging no doubt, but just noise going forward.
do you want me to remove them or should I turn them into dev_dbg() (so
they can be enabled for debugging purposes)?
>> +
>> + meson_saradc_stop_sample_engine(indio_dev);
>> +
>> + /* update the channel 6 MUX to select the temperature sensor */
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>> + SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
>> + SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
>> +
>> + /* disable all channels by default */
>> + regmap_write(priv->regmap, SAR_ADC_CHAN_LIST, 0x0);
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
>> + SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
>> + SAR_ADC_REG3_CNTL_USE_SC_DLY,
>> + SAR_ADC_REG3_CNTL_USE_SC_DLY);
>> +
>> + /* delay between two samples = (10+1) * 1uS */
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>> + SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
>> + FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK, 10));
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>> + SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
>> + FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 0));
>> +
>> + /* delay between two samples = (10+1) * 1uS */
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>> + SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
>> + FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 10));
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>> + SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
>> + FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 1));
>> +
> Cool. I hadn't come across FIELD_PREP before. Neater and tidier than having
> a shift and a mask for at least some usecases.
I think these were introduced with v4.9. I like them because I tend
use GENMASK() incorrectly and with those macros I get an error at
compile-time (without having to debug my code at all)
>> + ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
>> + if (ret) {
>> + dev_err(&indio_dev->dev,
>> + "failed to set adc parent to clkin\n");
>> + return ret;
>> + }
>> +
>> + ret = clk_set_rate(priv->adc_clk, 1200000);
>> + if (ret) {
>> + dev_err(&indio_dev->dev, "failed to set adc clock rate\n");
>> + return ret;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int meson_saradc_hw_enable(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + int ret;
>> +
>> + meson_saradc_lock(indio_dev);
>> +
>> + ret = regulator_enable(priv->vref);
>> + if (ret < 0) {
>> + dev_err(&indio_dev->dev, "failed to enable vref regulator\n");
>> + goto err_vref;
>> + }
>> +
>> + ret = clk_prepare_enable(priv->core_clk);
>> + if (ret) {
>> + dev_err(&indio_dev->dev, "failed to enable core clk\n");
>> + goto err_core_clk;
>> + }
>> +
>> + ret = clk_prepare_enable(priv->sana_clk);
>> + if (ret) {
>> + dev_err(&indio_dev->dev, "failed to enable sana clk\n");
>> + goto err_sana_clk;
>> + }
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG11,
>> + SAR_ADC_REG11_BANDGAP_EN, SAR_ADC_REG11_BANDGAP_EN);
> Is this controlling an offset for a bandgap or some actual electronics?
> Not sure if it should be disabled on error and the datasheets I've found are
> far from great! You disable it in the disable, so I'd expect it to be
> unwound on error in here too.
actually the bandgap is not documented at all :(
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN,
>> + SAR_ADC_REG3_ADC_EN);
> The fact you turn this of in the disable suggests to me that on error
> you should be doing it in here too.
I will disable this along with SAR_ADC_REG11_BANDGAP_EN in the
err_adc_clk label, thanks for spotting this.
>> +
>> + udelay(5);
>> +
>> + ret = clk_prepare_enable(priv->adc_clk);
>> + if (ret) {
>> + dev_err(&indio_dev->dev, "failed to enable adc_en clk\n");
>> + goto err_adc_clk;
>> + }
>> +
>> + meson_saradc_unlock(indio_dev);
>> +
>> + return 0;
>> +
>> +err_adc_clk:
>> + clk_disable_unprepare(priv->sana_clk);
>> +err_sana_clk:
>> + clk_disable_unprepare(priv->core_clk);
>> +err_core_clk:
>> + regulator_disable(priv->vref);
>> +err_vref:
>> + meson_saradc_unlock(indio_dev);
>> + return ret;
>> +}
>> +
>> +static void meson_saradc_hw_disable(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> +
>> + meson_saradc_lock(indio_dev);
>> +
>> + clk_disable_unprepare(priv->adc_clk);
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN, 0);
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG11,
>> + SAR_ADC_REG11_BANDGAP_EN, 0);
>> +
>> + clk_disable_unprepare(priv->sana_clk);
>> + clk_disable_unprepare(priv->core_clk);
>> +
>> + regulator_disable(priv->vref);
>> +
>> + meson_saradc_unlock(indio_dev);
>> +}
>> +
>> +static const struct iio_info meson_saradc_iio_info = {
>> + .read_raw = meson_saradc_iio_info_read_raw,
>> + .driver_module = THIS_MODULE,
>> +};
>> +
>> +static const struct of_device_id meson_saradc_of_match[] = {
>> + {
>> + .compatible = "amlogic,meson-gxbb-saradc",
>> + .data = (void *)10,
> Might have been worth having a structure array indexed from an enum.
> For now it is overkill, but seems likely there are a few other differences
> that aren't supported yet?
what do you mean with "structure array indexed from an enum"? I can
introduce some match-specific struct if you want (just like it's done
in rockchip_saradc.c with "struct rockchip_saradc_data").
>> + }, {
>> + .compatible = "amlogic,meson-gxl-saradc",
>> + .data = (void *)12,
>> + },
>> + {},
>> +};
>> +MODULE_DEVICE_TABLE(of, meson_saradc_of_match);
>> +
>> +static int meson_saradc_probe(struct platform_device *pdev)
>> +{
>> + struct meson_saradc_priv *priv;
>> + struct iio_dev *indio_dev;
>> + struct resource *res;
>> + void __iomem *base;
>> + const struct of_device_id *match;
>> + int ret;
>> +
>> + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
>> + if (!indio_dev) {
>> + dev_err(&pdev->dev, "failed allocating iio device\n");
>> + return -ENOMEM;
>> + }
>> +
>> + priv = iio_priv(indio_dev);
>> +
>> + match = of_match_device(meson_saradc_of_match, &pdev->dev);
>> + priv->resolution = (unsigned long)match->data;
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + base = devm_ioremap_resource(&pdev->dev, res);
>> + if (IS_ERR(base))
>> + return PTR_ERR(base);
>> +
>> + priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
>> + &meson_saradc_regmap_config);
>> + if (IS_ERR(priv->regmap))
>> + return PTR_ERR(priv->regmap);
>> +
>> + init_completion(&priv->completion);
>> +
>> + priv->clkin = devm_clk_get(&pdev->dev, "clkin");
>> + if (IS_ERR(priv->clkin)) {
>> + dev_err(&pdev->dev, "failed to get clkin\n");
>> + return PTR_ERR(priv->clkin);
>> + }
>> +
>> + priv->core_clk = devm_clk_get(&pdev->dev, "core");
>> + if (IS_ERR(priv->core_clk)) {
>> + dev_err(&pdev->dev, "failed to get core clk\n");
>> + return PTR_ERR(priv->core_clk);
>> + }
>> +
>> + priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
> Oh for a devm_clk_get_optional to handle this boiler plate neatly.
> It's been suggested before, but nothing seems to have come of it.
I guess quite a few drivers would benefit from that. maybe we should
take this to the linux-clk list again?
> Some array clk get functions might also clean this up a touch.
yes, unfortunately in this case it's not that easy as it would have to
allow a mix of mandatory and optional clocks. Additionally I cannot
bulk-enable them unconditionally since some of these are simple gates,
others need to be reparented and for some the rate has to be set.
>> + if (IS_ERR(priv->sana_clk)) {
>> + if (PTR_ERR(priv->sana_clk) == -ENOENT) {
>> + priv->sana_clk = NULL;
>> + } else {
>> + dev_err(&pdev->dev, "failed to get sana clk\n");
>> + return PTR_ERR(priv->sana_clk);
>> + }
>> + }
>> +
>> + priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
>> + if (IS_ERR(priv->adc_clk)) {
>> + if (PTR_ERR(priv->adc_clk) == -ENOENT) {
>> + priv->adc_clk = NULL;
>> + } else {
>> + dev_err(&pdev->dev, "failed to get adc clk\n");
>> + return PTR_ERR(priv->adc_clk);
>> + }
>> + }
>> +
>> + priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
>> + if (IS_ERR(priv->adc_sel_clk)) {
>> + if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
>> + priv->adc_sel_clk = NULL;
>> + } else {
>> + dev_err(&pdev->dev, "failed to get adc_sel clk\n");
>> + return PTR_ERR(priv->adc_sel_clk);
>> + }
>> + }
>> +
>> + /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
>> + if (!priv->adc_clk) {
>> + ret = meson_saradc_clk_init(indio_dev, base);
>> + if (ret)
>> + return ret;
>> + }
>> +
>> + priv->vref = devm_regulator_get(&pdev->dev, "vref");
>> + if (IS_ERR(priv->vref)) {
>> + dev_err(&pdev->dev, "failed to get vref regulator\n");
>> + return PTR_ERR(priv->vref);
>> + }
>> +
>> + ret = meson_saradc_init(indio_dev);
>> + if (ret)
>> + goto err;
>> +
>> + ret = meson_saradc_hw_enable(indio_dev);
>> + if (ret)
>> + goto err;
>> +
>> + platform_set_drvdata(pdev, indio_dev);
>> +
>> + indio_dev->name = dev_name(&pdev->dev);
>> + indio_dev->dev.parent = &pdev->dev;
>> + indio_dev->dev.of_node = pdev->dev.of_node;
>> + indio_dev->modes = INDIO_DIRECT_MODE;
>> + indio_dev->info = &meson_saradc_iio_info;
>> +
>> + indio_dev->channels = meson_saradc_iio_channels;
>> + indio_dev->num_channels = SAR_ADC_NUM_CHANNELS;
>> +
>> + ret = iio_device_register(indio_dev);
>> + if (ret)
>> + goto err_hw;
>> +
>> + return 0;
>> +
>> +err_hw:
>> + meson_saradc_hw_disable(indio_dev);
>> +err:
>> + return ret;
>> +}
>> +
>> +static int meson_saradc_remove(struct platform_device *pdev)
>> +{
>> + struct iio_dev *indio_dev = platform_get_drvdata(pdev);
>> +
>> + meson_saradc_hw_disable(indio_dev);
>> + iio_device_unregister(indio_dev);
>> +
>> + return 0;
>> +}
>> +
>> +#ifdef CONFIG_PM_SLEEP
>> +static int meson_saradc_suspend(struct device *dev)
>> +{
>> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
>> +
>> + meson_saradc_hw_disable(indio_dev);
>> +
>> + return 0;
>> +}
>> +
>> +static int meson_saradc_resume(struct device *dev)
>> +{
>> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
>> +
>> + return meson_saradc_hw_enable(indio_dev);
>> +}
>> +#endif /* CONFIG_PM_SLEEP */
>> +
>> +static SIMPLE_DEV_PM_OPS(meson_saradc_pm_ops,
>> + meson_saradc_suspend, meson_saradc_resume);
>> +
>> +static struct platform_driver meson_saradc_driver = {
>> + .probe = meson_saradc_probe,
>> + .remove = meson_saradc_remove,
>> + .driver = {
>> + .name = "meson-saradc",
>> + .of_match_table = meson_saradc_of_match,
>> + .pm = &meson_saradc_pm_ops,
>> + },
>> +};
>> +
>> +module_platform_driver(meson_saradc_driver);
>> +
>> +MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>");
>> +MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
>> +MODULE_LICENSE("GPL v2");
>>
>
Regards,
Martin
[0] http://lists.infradead.org/pipermail/linux-amlogic/2016-August/000986.html
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^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
@ 2017-01-14 17:44 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-14 17:44 UTC (permalink / raw)
To: Jonathan Cameron
Cc: knaack.h, lars, pmeerw, robh+dt, mark.rutland, khilman,
linux-iio, devicetree, linux-amlogic, linux-clk, carlo,
catalin.marinas, will.deacon, mturquette, sboyd, narmstrong,
linux-arm-kernel, Russell King
Hi Jonathan,
thank you for the review!
(further comments from me inline)
I think I'll send an updated version on Monday.
On Sat, Jan 14, 2017 at 3:46 PM, Jonathan Cameron <jic23@kernel.org> wrote:
> On 11/01/17 17:43, Martin Blumenstingl wrote:
>> This adds support for the SAR (Successive Approximation Register) ADC
>> on the Amlogic Meson SoCs.
>>
>> The code is based on the public S805 (Meson8b) and S905 (GXBB)
>> datasheets, as well as by reading (various versions of) the vendor
>> driver and by inspecting the registers on the vendor kernels of my
>> testing-hardware.
>>
>> Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
>> 10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
>> The code was written to support older SoCs (Meson8 and Meson8b) as well,
>> but due to lack of actual testing-hardware no of_device_id was added for
>> these.
>>
>> Two "features" from the vendor driver are currently missing:
>> - the vendor driver uses channel #7 for calibration (this improves the
>> accuracy of the results - in my tests the results were less than 3%
>> off without calibration compared to the vendor driver). Adding support
>> for this should be easy, but is not required for most applications.
>> - channel #6 is connected to the SoCs internal temperature sensor.
>> Adding support for this is probably not so easy since (based on the
>> u-boot sources) most SoC versions are using different registers and
>> algorithms for the conversion from "ADC value" to temperature.
>>
>> Supported by the hardware but currently not supported by the driver:
>> - reading multiple channels at the same time (the hardware has a FIFO
>> buffer which stores multiple results)
>> - continuous sampling (this would require a way to enable this
>> individually because otherwise the ADC would be drawing power
>> constantly)
>> - interrupt support (similar to the vendor driver this new driver is
>> polling the results. It is unclear if the IRQ-mode is supported on
>> older (Meson6 or Meson8) hardware as well or if there are any errata)
>>
> Russell Cc'd for a quick question on the clk api.
a quick side-note the clk API: my driver is a clock consumer and
provider at the same time. This seems to be a recurring pattern in
Amlogic hardware designs (as the MMC and DWMAC glue drivers are doing
this also), see [0]
> Ideally include a source for datasheets if available. Saves time googling and
> perhaps getting the wrong thing!
OK, will do this in v2
> A few other minor comments inline. Pretty good V1.
thanks :-)
> Jonathan
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>> ---
>> drivers/iio/adc/Kconfig | 12 +
>> drivers/iio/adc/Makefile | 1 +
>> drivers/iio/adc/meson_saradc.c | 860 +++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 873 insertions(+)
>> create mode 100644 drivers/iio/adc/meson_saradc.c
>>
>> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
>> index 9c8b558ba19e..86059b9b91bf 100644
>> --- a/drivers/iio/adc/Kconfig
>> +++ b/drivers/iio/adc/Kconfig
>> @@ -371,6 +371,18 @@ config MEN_Z188_ADC
>> This driver can also be built as a module. If so, the module will be
>> called men_z188_adc.
>>
>> +config MESON_SARADC
>> + tristate "Amlogic Meson SAR ADC driver"
>> + default ARCH_MESON
>> + depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
>> + select REGMAP_MMIO
>> + help
>> + Say yes here to build support for the SAR ADC found in Amlogic Meson
>> + SoCs.
>> +
>> + To compile this driver as a module, choose M here: the
>> + module will be called meson_saradc.
>> +
>> config MXS_LRADC
>> tristate "Freescale i.MX23/i.MX28 LRADC"
>> depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
>> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
>> index d36c4be8d1fc..de05b9e75f8f 100644
>> --- a/drivers/iio/adc/Makefile
>> +++ b/drivers/iio/adc/Makefile
>> @@ -36,6 +36,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
>> obj-$(CONFIG_MCP3422) += mcp3422.o
>> obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
>> obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
>> +obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
>> obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
>> obj-$(CONFIG_NAU7802) += nau7802.o
>> obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
>> diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
>> new file mode 100644
>> index 000000000000..06e8ac620385
>> --- /dev/null
>> +++ b/drivers/iio/adc/meson_saradc.c
>> @@ -0,0 +1,860 @@
>> +/*
>> + * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
>> + *
>> + * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#include <linux/bitfield.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/io.h>
>> +#include <linux/iio/iio.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>> +#include <linux/clk.h>
>> +#include <linux/completion.h>
>> +#include <linux/delay.h>
>> +#include <linux/reset.h>
>> +#include <linux/regmap.h>
>> +#include <linux/regulator/consumer.h>
>> +
>> +#define SAR_ADC_REG0 0x00
>> + #define SAR_ADC_REG0_PANEL_DETECT BIT(31)
>> + #define SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
>> + #define SAR_ADC_REG0_DELTA_BUSY BIT(30)
>> + #define SAR_ADC_REG0_AVG_BUSY BIT(29)
>> + #define SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
>> + #define SAR_ADC_REG0_FIFO_FULL BIT(27)
>> + #define SAR_ADC_REG0_FIFO_EMPTY BIT(26)
>> + #define SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
>> + #define SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
>> + #define SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
>> + #define SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
>> + #define SAR_ADC_REG0_SAMPLING_STOP BIT(14)
>> + #define SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
>> + #define SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
>> + #define SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
>> + #define SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
>> + #define SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
>> + #define SAR_ADC_REG0_SAMPLING_START BIT(2)
>> + #define SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
>> + #define SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
>> +
>> +#define SAR_ADC_CHAN_LIST 0x04
>> + #define SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
>> + #define SAR_ADC_CHAN_CHAN_ENTRY_MASK(_chan) \
>> + (GENMASK(2, 0) << (_chan * 3))
>> +
>> +#define SAR_ADC_AVG_CNTL 0x08
>> + #define SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
>> + (16 + (_chan * 2))
>> + #define SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
>> + (GENMASK(17, 16) << (_chan * 2))
>> + #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
>> + (0 + (_chan * 2))
>> + #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
>> + (GENMASK(1, 0) << (_chan * 2))
>> +
>> +#define SAR_ADC_REG3 0x0c
>> + #define SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
>> + #define SAR_ADC_REG3_CLK_EN BIT(30)
>> + #define SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
>> + #define SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
>> + #define SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
>> + #define SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
>> + #define SAR_ADC_REG3_DETECT_EN BIT(22)
>> + #define SAR_ADC_REG3_ADC_EN BIT(21)
>> + #define SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
>> + #define SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
>> + #define SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
>> + #define SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
>> + #define SAR_ADC_REG3_ADC_CLK_DIV_MASK GENMASK(15, 10)
>> + #define SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
>> + #define SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
>> +
>> +#define SAR_ADC_DELAY 0x10
>> + #define SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
>> + #define SAR_ADC_DELAY_BL30_BUSY BIT(15)
>> + #define SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
>> + #define SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
>> + #define SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
>> + #define SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
>> +
>> +#define SAR_ADC_LAST_RD 0x14
>> + #define SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
>> + #define SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
>> +
>> +#define SAR_ADC_FIFO_RD 0x18
>> + #define SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
>> + #define SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
>> +
>> +#define SAR_ADC_AUX_SW 0x1c
>> + #define SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
>> + (GENMASK(10, 8) << ((_chan - 2) * 2))
>> + #define SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
>> + #define SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
>> + #define SAR_ADC_AUX_SW_MODE_SEL BIT(4)
>> + #define SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
>> + #define SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
>> + #define SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
>> + #define SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
>> +
>> +#define SAR_ADC_CHAN_10_SW 0x20
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
>> +
>> +#define SAR_ADC_DETECT_IDLE_SW 0x24
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK GENMASK(25, 23)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_P_MUX BIT(22)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_N_MUX BIT(21)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YP_DRIVE_SW BIT(19)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XP_DRIVE_SW BIT(18)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YM_DRIVE_SW BIT(17)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XM_DRIVE_SW BIT(16)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK GENMASK(9, 7)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_P_MUX BIT(6)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_N_MUX BIT(5)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YP_DRIVE_SW BIT(3)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XP_DRIVE_SW BIT(2)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YM_DRIVE_SW BIT(1)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XM_DRIVE_SW BIT(0)
>> +
>> +#define SAR_ADC_DELTA_10 0x28
>> + #define SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
>> + #define SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
>> + #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_SHIFT 16
>> + #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
>> + #define SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
>> + #define SAR_ADC_DELTA_10_TS_C_SHIFT 11
>> + #define SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
>> + #define SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
>> + #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_SHIFT 0
>> + #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
>> +
>> +/* NOTE: registers from here are undocumented (the vendor Linux kernel driver
>> + * and u-boot source served as reference). These only seem to be relevant on
>> + * GXBB and newer.
>> + */
>> +#define SAR_ADC_REG11 0x2c
>> + #define SAR_ADC_REG11_BANDGAP_EN BIT(13)
>> +
>> +#define SAR_ADC_REG13 0x34
>> + #define SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
>> +
>> +#define SAR_ADC_MAX_FIFO_SIZE 32
>> +#define SAR_ADC_NUM_CHANNELS ARRAY_SIZE(meson_saradc_iio_channels)
>> +#define SAR_ADC_VALUE_MASK(_priv) (BIT(_priv->resolution) - 1)
>> +
>> +#define MESON_SAR_ADC_CHAN(_chan, _type) { \
>> + .type = _type, \
>> + .indexed = true, \
>> + .channel = _chan, \
>> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
>> + BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
>> + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
>> + .datasheet_name = "SAR_ADC_CH"#_chan, \
>> +}
>> +
>> +/* TODO: the hardware supports IIO_TEMP for channel 6 as well which is
> Multline comment syntax.
I got this wrong in 2 other places as well. will be fixed in v2, thanks!
>> + * currently not supported by this driver.
>> + */
>> +static const struct iio_chan_spec meson_saradc_iio_channels[] = {
>> + MESON_SAR_ADC_CHAN(0, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(1, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(2, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(3, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(4, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(5, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(6, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(7, IIO_VOLTAGE),
>> + IIO_CHAN_SOFT_TIMESTAMP(8),
>> +};
>> +
>> +enum meson_saradc_avg_mode {
>> + NO_AVERAGING = 0x0,
>> + MEAN_AVERAGING = 0x1,
>> + MEDIAN_AVERAGING = 0x2,
>> +};
>> +
>> +enum meson_saradc_num_samples {
>> + ONE_SAMPLE = 0x0,
>> + TWO_SAMPLES = 0x1,
>> + FOUR_SAMPLES = 0x2,
>> + EIGHT_SAMPLES = 0x3,
>> +};
>> +
>> +enum meson_saradc_chan7_mux_sel {
>> + CHAN7_MUX_VSS = 0x0,
>> + CHAN7_MUX_VDD_DIV4 = 0x1,
>> + CHAN7_MUX_VDD_DIV2 = 0x2,
>> + CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
>> + CHAN7_MUX_VDD = 0x4,
>> + CHAN7_MUX_CH7_INPUT = 0x7,
>> +};
>> +
>> +struct meson_saradc_priv {
>> + struct regmap *regmap;
>> + struct clk *clkin;
>> + struct clk *core_clk;
>> + struct clk *sana_clk;
>> + struct clk *adc_sel_clk;
>> + struct clk *adc_clk;
>> + struct clk_gate clk_gate;
>> + struct clk *adc_div_clk;
>> + struct clk_divider clk_div;
>> + struct regulator *vref;
>> + struct completion completion;
>> + u8 resolution;
>> +};
>> +
>> +static const struct regmap_config meson_saradc_regmap_config = {
>> + .reg_bits = 8,
>> + .val_bits = 32,
>> + .reg_stride = 4,
>> + .max_register = SAR_ADC_REG13,
>> +};
>> +
>> +static unsigned int meson_saradc_get_fifo_count(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + u32 regval;
>> +
>> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
>> +
>> + return FIELD_GET(SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
>> +}
>> +
>> +static int meson_saradc_wait_busy_clear(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + int regval, timeout = 10000;
>> +
>> + do {
>> + udelay(1);
>> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
>> + } while (FIELD_GET(SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
>> +
>> + if (timeout < 0)
>> + return -ETIMEDOUT;
>> +
>> + return 0;
>> +}
>> +
>> +static int meson_saradc_read_raw_sample(struct iio_dev *indio_dev,
>> + const struct iio_chan_spec *chan,
>> + int *val)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0;
>> +
>> + ret = meson_saradc_wait_busy_clear(indio_dev);
>> + if (ret)
>> + return ret;
>> +
>> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
>> +
>> + while (meson_saradc_get_fifo_count(indio_dev) > 0 &&
>> + count < SAR_ADC_MAX_FIFO_SIZE) {
>> + regmap_read(priv->regmap, SAR_ADC_FIFO_RD, ®val);
>> +
>> + fifo_chan = FIELD_GET(SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
>> + if (fifo_chan == chan->channel) {
>> + fifo_val = FIELD_GET(SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK,
>> + regval) & SAR_ADC_VALUE_MASK(priv);
>> + sum += fifo_val;
>> + count++;
>> + }
>> + }
>> +
>> + if (!count)
>> + return -ENOENT;
>> +
>> + *val = sum / count;
>> +
>> + return 0;
>> +}
>> +
>> +static void meson_saradc_set_averaging(struct iio_dev *indio_dev,
>> + const struct iio_chan_spec *chan,
>> + enum meson_saradc_avg_mode mode,
>> + enum meson_saradc_num_samples samples)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + u32 val;
>> +
>> + val = samples << SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(chan->channel);
>> + regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
>> + SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(chan->channel),
>> + val);
>> +
>> + val = mode << SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(chan->channel);
>> + regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
>> + SAR_ADC_AVG_CNTL_AVG_MODE_MASK(chan->channel), val);
>> +}
>> +
>> +static void meson_saradc_enable_channel(struct iio_dev *indio_dev,
>> + const struct iio_chan_spec *chan)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + u32 regval;
>> +
>> + /* the SAR ADC engine allows sampling multiple channels at the same
>> + * time. to keep it simple we're only working with one *internal*
>> + * channel, which starts counting at index 0 (which means: count = 1).
>> + */
>> + regval = FIELD_PREP(SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
>> + regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
>> + SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
>> +
>> + /* map channel index 0 to the channel which we want to read */
>> + regval = FIELD_PREP(SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), chan->channel);
>> + regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
>> + SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), regval);
>> +
>> + regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
>> + chan->channel);
>> + regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
>> + SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
>> + regval);
>> +
>> + regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
>> + chan->channel);
>> + regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
>> + SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
>> + regval);
>> +
>> + if (chan->channel == 6)
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELTA_10,
>> + SAR_ADC_DELTA_10_TEMP_SEL, 0);
>> +}
>> +
>> +static void meson_saradc_set_channel7_mux(struct iio_dev *indio_dev,
>> + enum meson_saradc_chan7_mux_sel sel)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + u32 regval;
>> +
>> + regval = FIELD_PREP(SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
>> + SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
>> +
>> + usleep_range(10, 20);
>> +}
>> +
>> +static void meson_saradc_start_sample_engine(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
>> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>> + SAR_ADC_REG0_SAMPLING_START,
>> + SAR_ADC_REG0_SAMPLING_START);
>> +}
>> +
>> +static void meson_saradc_stop_sample_engine(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>> + SAR_ADC_REG0_SAMPLING_STOP,
>> + SAR_ADC_REG0_SAMPLING_STOP);
>> +
>> + /* wait until all modules are stopped */
>> + meson_saradc_wait_busy_clear(indio_dev);
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
>> +}
>> +
>> +static void meson_saradc_lock(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + int val;
>> +
>> + mutex_lock(&indio_dev->mlock);
>> +
>> + /* prevent BL30 from using the SAR ADC while we are using it */
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>> + SAR_ADC_DELAY_KERNEL_BUSY,
>> + SAR_ADC_DELAY_KERNEL_BUSY);
>> +
>> + /* wait until BL30 releases it's lock (so we can use the SAR ADC) */
>> + do {
>> + udelay(1);
>> + regmap_read(priv->regmap, SAR_ADC_DELAY, &val);
>> + } while (val & SAR_ADC_DELAY_BL30_BUSY);
>> +}
>> +
>> +static void meson_saradc_unlock(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> +
>> + /* allow BL30 to use the SAR ADC again */
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>> + SAR_ADC_DELAY_KERNEL_BUSY, 0);
>> +
>> + mutex_unlock(&indio_dev->mlock);
>> +}
>> +
>> +static int meson_saradc_get_sample(struct iio_dev *indio_dev,
>> + const struct iio_chan_spec *chan,
>> + enum meson_saradc_avg_mode avg_mode,
>> + enum meson_saradc_num_samples avg_samples,
>> + int *val)
>> +{
>> + int ret, tmp;
>> +
>> + meson_saradc_lock(indio_dev);
>> +
>> + /* clear old values from the FIFO buffer, ignoring errors */
>> + meson_saradc_read_raw_sample(indio_dev, chan, &tmp);
>> +
>> + meson_saradc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
>> +
>> + meson_saradc_enable_channel(indio_dev, chan);
>> +
>> + meson_saradc_start_sample_engine(indio_dev);
>> + ret = meson_saradc_read_raw_sample(indio_dev, chan, val);
>> + meson_saradc_stop_sample_engine(indio_dev);
>> +
>> + meson_saradc_unlock(indio_dev);
>> +
>> + if (ret) {
>> + dev_warn(&indio_dev->dev,
>> + "failed to read sample for channel %d: %d\n",
>> + chan->channel, ret);
>> + return ret;
>> + }
>> +
>> + return IIO_VAL_INT;
>> +}
>> +
>> +static int meson_saradc_iio_info_read_raw(struct iio_dev *indio_dev,
>> + const struct iio_chan_spec *chan,
>> + int *val, int *val2, long mask)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + int ret;
>> +
>> + switch (mask) {
>> + case IIO_CHAN_INFO_RAW:
>> + return meson_saradc_get_sample(indio_dev, chan, NO_AVERAGING,
>> + ONE_SAMPLE, val);
>> + break;
>> +
>> + case IIO_CHAN_INFO_AVERAGE_RAW:
>> + return meson_saradc_get_sample(indio_dev, chan, MEAN_AVERAGING,
>> + EIGHT_SAMPLES, val);
>> + break;
>> +
>> + case IIO_CHAN_INFO_SCALE:
>> + ret = regulator_get_voltage(priv->vref);
>> + if (ret < 0) {
>> + dev_err(&indio_dev->dev,
>> + "failed to get vref voltage: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + *val = ret / 1000;
>> + *val2 = priv->resolution;
>> + return IIO_VAL_FRACTIONAL_LOG2;
>> +
>> + default:
>> + return -EINVAL;
>> + }
>> +}
>> +
>> +static int meson_saradc_clk_init(struct iio_dev *indio_dev, void __iomem *base)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + struct clk_init_data init;
>> + char clk_name[32];
>> + const char *clk_parents[1];
>> +
>> + snprintf(clk_name, sizeof(clk_name), "%s#adc_div",
>> + of_node_full_name(indio_dev->dev.of_node));
>> + init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
>> + init.flags = 0;
>> + init.ops = &clk_divider_ops;
>> + clk_parents[0] = __clk_get_name(priv->clkin);
>> + init.parent_names = clk_parents;
>> + init.num_parents = 1;
>> +
>> + priv->clk_div.reg = base + SAR_ADC_REG3;
>> + priv->clk_div.shift = SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
>> + priv->clk_div.width = SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
>> + priv->clk_div.hw.init = &init;
>> + priv->clk_div.flags = 0;
>> +
>> + priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
>> + &priv->clk_div.hw);
>> + if (WARN_ON(IS_ERR(priv->adc_div_clk)))
>> + return PTR_ERR(priv->adc_div_clk);
>> +
>> + snprintf(clk_name, sizeof(clk_name), "%s#adc_en",
>> + of_node_full_name(indio_dev->dev.of_node));
>> + init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
>> + init.flags = CLK_SET_RATE_PARENT;
>> + init.ops = &clk_gate_ops;
>> + clk_parents[0] = __clk_get_name(priv->adc_div_clk);
>> + init.parent_names = clk_parents;
>> + init.num_parents = 1;
>> +
>> + priv->clk_gate.reg = base + SAR_ADC_REG3;
>> + priv->clk_gate.bit_idx = fls(SAR_ADC_REG3_CLK_EN);
>> + priv->clk_gate.hw.init = &init;
>> +
>> + priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
>> + if (WARN_ON(IS_ERR(priv->adc_clk)))
>> + return PTR_ERR(priv->adc_clk);
>> +
>> + return 0;
>> +}
>> +
>> +static int meson_saradc_init(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + int regval, ret;
>> +
>> + /* make sure we start at CH7 input */
> why? Seems like a little more detail would be good here ;)
I'll change this to "make sure we start at CH7 input since the other
muxes are only used for internal calibration." in v2
>> + meson_saradc_set_channel7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
>> +
>> + regmap_read(priv->regmap, SAR_ADC_REG3, ®val);
>> + if (regval & SAR_ADC_REG3_BL30_INITIALIZED) {
>> + dev_info(&indio_dev->dev, "already initialized by BL30\n");
>> + return 0;
>> + }
>> +
>> + dev_info(&indio_dev->dev, "initializing SAR ADC\n");
> I'd argue this provides no useful info so should be dropped.
> Useful for debugging no doubt, but just noise going forward.
do you want me to remove them or should I turn them into dev_dbg() (so
they can be enabled for debugging purposes)?
>> +
>> + meson_saradc_stop_sample_engine(indio_dev);
>> +
>> + /* update the channel 6 MUX to select the temperature sensor */
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>> + SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
>> + SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
>> +
>> + /* disable all channels by default */
>> + regmap_write(priv->regmap, SAR_ADC_CHAN_LIST, 0x0);
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
>> + SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
>> + SAR_ADC_REG3_CNTL_USE_SC_DLY,
>> + SAR_ADC_REG3_CNTL_USE_SC_DLY);
>> +
>> + /* delay between two samples = (10+1) * 1uS */
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>> + SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
>> + FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK, 10));
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>> + SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
>> + FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 0));
>> +
>> + /* delay between two samples = (10+1) * 1uS */
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>> + SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
>> + FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 10));
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>> + SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
>> + FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 1));
>> +
> Cool. I hadn't come across FIELD_PREP before. Neater and tidier than having
> a shift and a mask for at least some usecases.
I think these were introduced with v4.9. I like them because I tend
use GENMASK() incorrectly and with those macros I get an error at
compile-time (without having to debug my code at all)
>> + ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
>> + if (ret) {
>> + dev_err(&indio_dev->dev,
>> + "failed to set adc parent to clkin\n");
>> + return ret;
>> + }
>> +
>> + ret = clk_set_rate(priv->adc_clk, 1200000);
>> + if (ret) {
>> + dev_err(&indio_dev->dev, "failed to set adc clock rate\n");
>> + return ret;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int meson_saradc_hw_enable(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + int ret;
>> +
>> + meson_saradc_lock(indio_dev);
>> +
>> + ret = regulator_enable(priv->vref);
>> + if (ret < 0) {
>> + dev_err(&indio_dev->dev, "failed to enable vref regulator\n");
>> + goto err_vref;
>> + }
>> +
>> + ret = clk_prepare_enable(priv->core_clk);
>> + if (ret) {
>> + dev_err(&indio_dev->dev, "failed to enable core clk\n");
>> + goto err_core_clk;
>> + }
>> +
>> + ret = clk_prepare_enable(priv->sana_clk);
>> + if (ret) {
>> + dev_err(&indio_dev->dev, "failed to enable sana clk\n");
>> + goto err_sana_clk;
>> + }
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG11,
>> + SAR_ADC_REG11_BANDGAP_EN, SAR_ADC_REG11_BANDGAP_EN);
> Is this controlling an offset for a bandgap or some actual electronics?
> Not sure if it should be disabled on error and the datasheets I've found are
> far from great! You disable it in the disable, so I'd expect it to be
> unwound on error in here too.
actually the bandgap is not documented at all :(
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN,
>> + SAR_ADC_REG3_ADC_EN);
> The fact you turn this of in the disable suggests to me that on error
> you should be doing it in here too.
I will disable this along with SAR_ADC_REG11_BANDGAP_EN in the
err_adc_clk label, thanks for spotting this.
>> +
>> + udelay(5);
>> +
>> + ret = clk_prepare_enable(priv->adc_clk);
>> + if (ret) {
>> + dev_err(&indio_dev->dev, "failed to enable adc_en clk\n");
>> + goto err_adc_clk;
>> + }
>> +
>> + meson_saradc_unlock(indio_dev);
>> +
>> + return 0;
>> +
>> +err_adc_clk:
>> + clk_disable_unprepare(priv->sana_clk);
>> +err_sana_clk:
>> + clk_disable_unprepare(priv->core_clk);
>> +err_core_clk:
>> + regulator_disable(priv->vref);
>> +err_vref:
>> + meson_saradc_unlock(indio_dev);
>> + return ret;
>> +}
>> +
>> +static void meson_saradc_hw_disable(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> +
>> + meson_saradc_lock(indio_dev);
>> +
>> + clk_disable_unprepare(priv->adc_clk);
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN, 0);
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG11,
>> + SAR_ADC_REG11_BANDGAP_EN, 0);
>> +
>> + clk_disable_unprepare(priv->sana_clk);
>> + clk_disable_unprepare(priv->core_clk);
>> +
>> + regulator_disable(priv->vref);
>> +
>> + meson_saradc_unlock(indio_dev);
>> +}
>> +
>> +static const struct iio_info meson_saradc_iio_info = {
>> + .read_raw = meson_saradc_iio_info_read_raw,
>> + .driver_module = THIS_MODULE,
>> +};
>> +
>> +static const struct of_device_id meson_saradc_of_match[] = {
>> + {
>> + .compatible = "amlogic,meson-gxbb-saradc",
>> + .data = (void *)10,
> Might have been worth having a structure array indexed from an enum.
> For now it is overkill, but seems likely there are a few other differences
> that aren't supported yet?
what do you mean with "structure array indexed from an enum"? I can
introduce some match-specific struct if you want (just like it's done
in rockchip_saradc.c with "struct rockchip_saradc_data").
>> + }, {
>> + .compatible = "amlogic,meson-gxl-saradc",
>> + .data = (void *)12,
>> + },
>> + {},
>> +};
>> +MODULE_DEVICE_TABLE(of, meson_saradc_of_match);
>> +
>> +static int meson_saradc_probe(struct platform_device *pdev)
>> +{
>> + struct meson_saradc_priv *priv;
>> + struct iio_dev *indio_dev;
>> + struct resource *res;
>> + void __iomem *base;
>> + const struct of_device_id *match;
>> + int ret;
>> +
>> + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
>> + if (!indio_dev) {
>> + dev_err(&pdev->dev, "failed allocating iio device\n");
>> + return -ENOMEM;
>> + }
>> +
>> + priv = iio_priv(indio_dev);
>> +
>> + match = of_match_device(meson_saradc_of_match, &pdev->dev);
>> + priv->resolution = (unsigned long)match->data;
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + base = devm_ioremap_resource(&pdev->dev, res);
>> + if (IS_ERR(base))
>> + return PTR_ERR(base);
>> +
>> + priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
>> + &meson_saradc_regmap_config);
>> + if (IS_ERR(priv->regmap))
>> + return PTR_ERR(priv->regmap);
>> +
>> + init_completion(&priv->completion);
>> +
>> + priv->clkin = devm_clk_get(&pdev->dev, "clkin");
>> + if (IS_ERR(priv->clkin)) {
>> + dev_err(&pdev->dev, "failed to get clkin\n");
>> + return PTR_ERR(priv->clkin);
>> + }
>> +
>> + priv->core_clk = devm_clk_get(&pdev->dev, "core");
>> + if (IS_ERR(priv->core_clk)) {
>> + dev_err(&pdev->dev, "failed to get core clk\n");
>> + return PTR_ERR(priv->core_clk);
>> + }
>> +
>> + priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
> Oh for a devm_clk_get_optional to handle this boiler plate neatly.
> It's been suggested before, but nothing seems to have come of it.
I guess quite a few drivers would benefit from that. maybe we should
take this to the linux-clk list again?
> Some array clk get functions might also clean this up a touch.
yes, unfortunately in this case it's not that easy as it would have to
allow a mix of mandatory and optional clocks. Additionally I cannot
bulk-enable them unconditionally since some of these are simple gates,
others need to be reparented and for some the rate has to be set.
>> + if (IS_ERR(priv->sana_clk)) {
>> + if (PTR_ERR(priv->sana_clk) == -ENOENT) {
>> + priv->sana_clk = NULL;
>> + } else {
>> + dev_err(&pdev->dev, "failed to get sana clk\n");
>> + return PTR_ERR(priv->sana_clk);
>> + }
>> + }
>> +
>> + priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
>> + if (IS_ERR(priv->adc_clk)) {
>> + if (PTR_ERR(priv->adc_clk) == -ENOENT) {
>> + priv->adc_clk = NULL;
>> + } else {
>> + dev_err(&pdev->dev, "failed to get adc clk\n");
>> + return PTR_ERR(priv->adc_clk);
>> + }
>> + }
>> +
>> + priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
>> + if (IS_ERR(priv->adc_sel_clk)) {
>> + if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
>> + priv->adc_sel_clk = NULL;
>> + } else {
>> + dev_err(&pdev->dev, "failed to get adc_sel clk\n");
>> + return PTR_ERR(priv->adc_sel_clk);
>> + }
>> + }
>> +
>> + /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
>> + if (!priv->adc_clk) {
>> + ret = meson_saradc_clk_init(indio_dev, base);
>> + if (ret)
>> + return ret;
>> + }
>> +
>> + priv->vref = devm_regulator_get(&pdev->dev, "vref");
>> + if (IS_ERR(priv->vref)) {
>> + dev_err(&pdev->dev, "failed to get vref regulator\n");
>> + return PTR_ERR(priv->vref);
>> + }
>> +
>> + ret = meson_saradc_init(indio_dev);
>> + if (ret)
>> + goto err;
>> +
>> + ret = meson_saradc_hw_enable(indio_dev);
>> + if (ret)
>> + goto err;
>> +
>> + platform_set_drvdata(pdev, indio_dev);
>> +
>> + indio_dev->name = dev_name(&pdev->dev);
>> + indio_dev->dev.parent = &pdev->dev;
>> + indio_dev->dev.of_node = pdev->dev.of_node;
>> + indio_dev->modes = INDIO_DIRECT_MODE;
>> + indio_dev->info = &meson_saradc_iio_info;
>> +
>> + indio_dev->channels = meson_saradc_iio_channels;
>> + indio_dev->num_channels = SAR_ADC_NUM_CHANNELS;
>> +
>> + ret = iio_device_register(indio_dev);
>> + if (ret)
>> + goto err_hw;
>> +
>> + return 0;
>> +
>> +err_hw:
>> + meson_saradc_hw_disable(indio_dev);
>> +err:
>> + return ret;
>> +}
>> +
>> +static int meson_saradc_remove(struct platform_device *pdev)
>> +{
>> + struct iio_dev *indio_dev = platform_get_drvdata(pdev);
>> +
>> + meson_saradc_hw_disable(indio_dev);
>> + iio_device_unregister(indio_dev);
>> +
>> + return 0;
>> +}
>> +
>> +#ifdef CONFIG_PM_SLEEP
>> +static int meson_saradc_suspend(struct device *dev)
>> +{
>> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
>> +
>> + meson_saradc_hw_disable(indio_dev);
>> +
>> + return 0;
>> +}
>> +
>> +static int meson_saradc_resume(struct device *dev)
>> +{
>> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
>> +
>> + return meson_saradc_hw_enable(indio_dev);
>> +}
>> +#endif /* CONFIG_PM_SLEEP */
>> +
>> +static SIMPLE_DEV_PM_OPS(meson_saradc_pm_ops,
>> + meson_saradc_suspend, meson_saradc_resume);
>> +
>> +static struct platform_driver meson_saradc_driver = {
>> + .probe = meson_saradc_probe,
>> + .remove = meson_saradc_remove,
>> + .driver = {
>> + .name = "meson-saradc",
>> + .of_match_table = meson_saradc_of_match,
>> + .pm = &meson_saradc_pm_ops,
>> + },
>> +};
>> +
>> +module_platform_driver(meson_saradc_driver);
>> +
>> +MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
>> +MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
>> +MODULE_LICENSE("GPL v2");
>>
>
Regards,
Martin
[0] http://lists.infradead.org/pipermail/linux-amlogic/2016-August/000986.html
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
@ 2017-01-14 17:44 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-14 17:44 UTC (permalink / raw)
To: linux-arm-kernel
Hi Jonathan,
thank you for the review!
(further comments from me inline)
I think I'll send an updated version on Monday.
On Sat, Jan 14, 2017 at 3:46 PM, Jonathan Cameron <jic23@kernel.org> wrote:
> On 11/01/17 17:43, Martin Blumenstingl wrote:
>> This adds support for the SAR (Successive Approximation Register) ADC
>> on the Amlogic Meson SoCs.
>>
>> The code is based on the public S805 (Meson8b) and S905 (GXBB)
>> datasheets, as well as by reading (various versions of) the vendor
>> driver and by inspecting the registers on the vendor kernels of my
>> testing-hardware.
>>
>> Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
>> 10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
>> The code was written to support older SoCs (Meson8 and Meson8b) as well,
>> but due to lack of actual testing-hardware no of_device_id was added for
>> these.
>>
>> Two "features" from the vendor driver are currently missing:
>> - the vendor driver uses channel #7 for calibration (this improves the
>> accuracy of the results - in my tests the results were less than 3%
>> off without calibration compared to the vendor driver). Adding support
>> for this should be easy, but is not required for most applications.
>> - channel #6 is connected to the SoCs internal temperature sensor.
>> Adding support for this is probably not so easy since (based on the
>> u-boot sources) most SoC versions are using different registers and
>> algorithms for the conversion from "ADC value" to temperature.
>>
>> Supported by the hardware but currently not supported by the driver:
>> - reading multiple channels at the same time (the hardware has a FIFO
>> buffer which stores multiple results)
>> - continuous sampling (this would require a way to enable this
>> individually because otherwise the ADC would be drawing power
>> constantly)
>> - interrupt support (similar to the vendor driver this new driver is
>> polling the results. It is unclear if the IRQ-mode is supported on
>> older (Meson6 or Meson8) hardware as well or if there are any errata)
>>
> Russell Cc'd for a quick question on the clk api.
a quick side-note the clk API: my driver is a clock consumer and
provider at the same time. This seems to be a recurring pattern in
Amlogic hardware designs (as the MMC and DWMAC glue drivers are doing
this also), see [0]
> Ideally include a source for datasheets if available. Saves time googling and
> perhaps getting the wrong thing!
OK, will do this in v2
> A few other minor comments inline. Pretty good V1.
thanks :-)
> Jonathan
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>> ---
>> drivers/iio/adc/Kconfig | 12 +
>> drivers/iio/adc/Makefile | 1 +
>> drivers/iio/adc/meson_saradc.c | 860 +++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 873 insertions(+)
>> create mode 100644 drivers/iio/adc/meson_saradc.c
>>
>> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
>> index 9c8b558ba19e..86059b9b91bf 100644
>> --- a/drivers/iio/adc/Kconfig
>> +++ b/drivers/iio/adc/Kconfig
>> @@ -371,6 +371,18 @@ config MEN_Z188_ADC
>> This driver can also be built as a module. If so, the module will be
>> called men_z188_adc.
>>
>> +config MESON_SARADC
>> + tristate "Amlogic Meson SAR ADC driver"
>> + default ARCH_MESON
>> + depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
>> + select REGMAP_MMIO
>> + help
>> + Say yes here to build support for the SAR ADC found in Amlogic Meson
>> + SoCs.
>> +
>> + To compile this driver as a module, choose M here: the
>> + module will be called meson_saradc.
>> +
>> config MXS_LRADC
>> tristate "Freescale i.MX23/i.MX28 LRADC"
>> depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
>> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
>> index d36c4be8d1fc..de05b9e75f8f 100644
>> --- a/drivers/iio/adc/Makefile
>> +++ b/drivers/iio/adc/Makefile
>> @@ -36,6 +36,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
>> obj-$(CONFIG_MCP3422) += mcp3422.o
>> obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
>> obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
>> +obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
>> obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
>> obj-$(CONFIG_NAU7802) += nau7802.o
>> obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
>> diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
>> new file mode 100644
>> index 000000000000..06e8ac620385
>> --- /dev/null
>> +++ b/drivers/iio/adc/meson_saradc.c
>> @@ -0,0 +1,860 @@
>> +/*
>> + * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
>> + *
>> + * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#include <linux/bitfield.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/io.h>
>> +#include <linux/iio/iio.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>> +#include <linux/clk.h>
>> +#include <linux/completion.h>
>> +#include <linux/delay.h>
>> +#include <linux/reset.h>
>> +#include <linux/regmap.h>
>> +#include <linux/regulator/consumer.h>
>> +
>> +#define SAR_ADC_REG0 0x00
>> + #define SAR_ADC_REG0_PANEL_DETECT BIT(31)
>> + #define SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
>> + #define SAR_ADC_REG0_DELTA_BUSY BIT(30)
>> + #define SAR_ADC_REG0_AVG_BUSY BIT(29)
>> + #define SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
>> + #define SAR_ADC_REG0_FIFO_FULL BIT(27)
>> + #define SAR_ADC_REG0_FIFO_EMPTY BIT(26)
>> + #define SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
>> + #define SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
>> + #define SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
>> + #define SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
>> + #define SAR_ADC_REG0_SAMPLING_STOP BIT(14)
>> + #define SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
>> + #define SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
>> + #define SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
>> + #define SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
>> + #define SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
>> + #define SAR_ADC_REG0_SAMPLING_START BIT(2)
>> + #define SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
>> + #define SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
>> +
>> +#define SAR_ADC_CHAN_LIST 0x04
>> + #define SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
>> + #define SAR_ADC_CHAN_CHAN_ENTRY_MASK(_chan) \
>> + (GENMASK(2, 0) << (_chan * 3))
>> +
>> +#define SAR_ADC_AVG_CNTL 0x08
>> + #define SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
>> + (16 + (_chan * 2))
>> + #define SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
>> + (GENMASK(17, 16) << (_chan * 2))
>> + #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
>> + (0 + (_chan * 2))
>> + #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
>> + (GENMASK(1, 0) << (_chan * 2))
>> +
>> +#define SAR_ADC_REG3 0x0c
>> + #define SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
>> + #define SAR_ADC_REG3_CLK_EN BIT(30)
>> + #define SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
>> + #define SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
>> + #define SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
>> + #define SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
>> + #define SAR_ADC_REG3_DETECT_EN BIT(22)
>> + #define SAR_ADC_REG3_ADC_EN BIT(21)
>> + #define SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
>> + #define SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
>> + #define SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
>> + #define SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
>> + #define SAR_ADC_REG3_ADC_CLK_DIV_MASK GENMASK(15, 10)
>> + #define SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
>> + #define SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
>> +
>> +#define SAR_ADC_DELAY 0x10
>> + #define SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
>> + #define SAR_ADC_DELAY_BL30_BUSY BIT(15)
>> + #define SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
>> + #define SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
>> + #define SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
>> + #define SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
>> +
>> +#define SAR_ADC_LAST_RD 0x14
>> + #define SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
>> + #define SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
>> +
>> +#define SAR_ADC_FIFO_RD 0x18
>> + #define SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
>> + #define SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
>> +
>> +#define SAR_ADC_AUX_SW 0x1c
>> + #define SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
>> + (GENMASK(10, 8) << ((_chan - 2) * 2))
>> + #define SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
>> + #define SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
>> + #define SAR_ADC_AUX_SW_MODE_SEL BIT(4)
>> + #define SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
>> + #define SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
>> + #define SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
>> + #define SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
>> +
>> +#define SAR_ADC_CHAN_10_SW 0x20
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
>> +
>> +#define SAR_ADC_DETECT_IDLE_SW 0x24
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK GENMASK(25, 23)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_P_MUX BIT(22)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_N_MUX BIT(21)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YP_DRIVE_SW BIT(19)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XP_DRIVE_SW BIT(18)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YM_DRIVE_SW BIT(17)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XM_DRIVE_SW BIT(16)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK GENMASK(9, 7)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_P_MUX BIT(6)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_N_MUX BIT(5)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YP_DRIVE_SW BIT(3)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XP_DRIVE_SW BIT(2)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YM_DRIVE_SW BIT(1)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XM_DRIVE_SW BIT(0)
>> +
>> +#define SAR_ADC_DELTA_10 0x28
>> + #define SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
>> + #define SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
>> + #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_SHIFT 16
>> + #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
>> + #define SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
>> + #define SAR_ADC_DELTA_10_TS_C_SHIFT 11
>> + #define SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
>> + #define SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
>> + #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_SHIFT 0
>> + #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
>> +
>> +/* NOTE: registers from here are undocumented (the vendor Linux kernel driver
>> + * and u-boot source served as reference). These only seem to be relevant on
>> + * GXBB and newer.
>> + */
>> +#define SAR_ADC_REG11 0x2c
>> + #define SAR_ADC_REG11_BANDGAP_EN BIT(13)
>> +
>> +#define SAR_ADC_REG13 0x34
>> + #define SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
>> +
>> +#define SAR_ADC_MAX_FIFO_SIZE 32
>> +#define SAR_ADC_NUM_CHANNELS ARRAY_SIZE(meson_saradc_iio_channels)
>> +#define SAR_ADC_VALUE_MASK(_priv) (BIT(_priv->resolution) - 1)
>> +
>> +#define MESON_SAR_ADC_CHAN(_chan, _type) { \
>> + .type = _type, \
>> + .indexed = true, \
>> + .channel = _chan, \
>> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
>> + BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
>> + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
>> + .datasheet_name = "SAR_ADC_CH"#_chan, \
>> +}
>> +
>> +/* TODO: the hardware supports IIO_TEMP for channel 6 as well which is
> Multline comment syntax.
I got this wrong in 2 other places as well. will be fixed in v2, thanks!
>> + * currently not supported by this driver.
>> + */
>> +static const struct iio_chan_spec meson_saradc_iio_channels[] = {
>> + MESON_SAR_ADC_CHAN(0, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(1, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(2, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(3, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(4, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(5, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(6, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(7, IIO_VOLTAGE),
>> + IIO_CHAN_SOFT_TIMESTAMP(8),
>> +};
>> +
>> +enum meson_saradc_avg_mode {
>> + NO_AVERAGING = 0x0,
>> + MEAN_AVERAGING = 0x1,
>> + MEDIAN_AVERAGING = 0x2,
>> +};
>> +
>> +enum meson_saradc_num_samples {
>> + ONE_SAMPLE = 0x0,
>> + TWO_SAMPLES = 0x1,
>> + FOUR_SAMPLES = 0x2,
>> + EIGHT_SAMPLES = 0x3,
>> +};
>> +
>> +enum meson_saradc_chan7_mux_sel {
>> + CHAN7_MUX_VSS = 0x0,
>> + CHAN7_MUX_VDD_DIV4 = 0x1,
>> + CHAN7_MUX_VDD_DIV2 = 0x2,
>> + CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
>> + CHAN7_MUX_VDD = 0x4,
>> + CHAN7_MUX_CH7_INPUT = 0x7,
>> +};
>> +
>> +struct meson_saradc_priv {
>> + struct regmap *regmap;
>> + struct clk *clkin;
>> + struct clk *core_clk;
>> + struct clk *sana_clk;
>> + struct clk *adc_sel_clk;
>> + struct clk *adc_clk;
>> + struct clk_gate clk_gate;
>> + struct clk *adc_div_clk;
>> + struct clk_divider clk_div;
>> + struct regulator *vref;
>> + struct completion completion;
>> + u8 resolution;
>> +};
>> +
>> +static const struct regmap_config meson_saradc_regmap_config = {
>> + .reg_bits = 8,
>> + .val_bits = 32,
>> + .reg_stride = 4,
>> + .max_register = SAR_ADC_REG13,
>> +};
>> +
>> +static unsigned int meson_saradc_get_fifo_count(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + u32 regval;
>> +
>> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
>> +
>> + return FIELD_GET(SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
>> +}
>> +
>> +static int meson_saradc_wait_busy_clear(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + int regval, timeout = 10000;
>> +
>> + do {
>> + udelay(1);
>> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
>> + } while (FIELD_GET(SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
>> +
>> + if (timeout < 0)
>> + return -ETIMEDOUT;
>> +
>> + return 0;
>> +}
>> +
>> +static int meson_saradc_read_raw_sample(struct iio_dev *indio_dev,
>> + const struct iio_chan_spec *chan,
>> + int *val)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0;
>> +
>> + ret = meson_saradc_wait_busy_clear(indio_dev);
>> + if (ret)
>> + return ret;
>> +
>> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
>> +
>> + while (meson_saradc_get_fifo_count(indio_dev) > 0 &&
>> + count < SAR_ADC_MAX_FIFO_SIZE) {
>> + regmap_read(priv->regmap, SAR_ADC_FIFO_RD, ®val);
>> +
>> + fifo_chan = FIELD_GET(SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
>> + if (fifo_chan == chan->channel) {
>> + fifo_val = FIELD_GET(SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK,
>> + regval) & SAR_ADC_VALUE_MASK(priv);
>> + sum += fifo_val;
>> + count++;
>> + }
>> + }
>> +
>> + if (!count)
>> + return -ENOENT;
>> +
>> + *val = sum / count;
>> +
>> + return 0;
>> +}
>> +
>> +static void meson_saradc_set_averaging(struct iio_dev *indio_dev,
>> + const struct iio_chan_spec *chan,
>> + enum meson_saradc_avg_mode mode,
>> + enum meson_saradc_num_samples samples)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + u32 val;
>> +
>> + val = samples << SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(chan->channel);
>> + regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
>> + SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(chan->channel),
>> + val);
>> +
>> + val = mode << SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(chan->channel);
>> + regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
>> + SAR_ADC_AVG_CNTL_AVG_MODE_MASK(chan->channel), val);
>> +}
>> +
>> +static void meson_saradc_enable_channel(struct iio_dev *indio_dev,
>> + const struct iio_chan_spec *chan)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + u32 regval;
>> +
>> + /* the SAR ADC engine allows sampling multiple channels at the same
>> + * time. to keep it simple we're only working with one *internal*
>> + * channel, which starts counting at index 0 (which means: count = 1).
>> + */
>> + regval = FIELD_PREP(SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
>> + regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
>> + SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
>> +
>> + /* map channel index 0 to the channel which we want to read */
>> + regval = FIELD_PREP(SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), chan->channel);
>> + regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
>> + SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), regval);
>> +
>> + regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
>> + chan->channel);
>> + regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
>> + SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
>> + regval);
>> +
>> + regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
>> + chan->channel);
>> + regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
>> + SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
>> + regval);
>> +
>> + if (chan->channel == 6)
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELTA_10,
>> + SAR_ADC_DELTA_10_TEMP_SEL, 0);
>> +}
>> +
>> +static void meson_saradc_set_channel7_mux(struct iio_dev *indio_dev,
>> + enum meson_saradc_chan7_mux_sel sel)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + u32 regval;
>> +
>> + regval = FIELD_PREP(SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
>> + SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
>> +
>> + usleep_range(10, 20);
>> +}
>> +
>> +static void meson_saradc_start_sample_engine(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
>> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>> + SAR_ADC_REG0_SAMPLING_START,
>> + SAR_ADC_REG0_SAMPLING_START);
>> +}
>> +
>> +static void meson_saradc_stop_sample_engine(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>> + SAR_ADC_REG0_SAMPLING_STOP,
>> + SAR_ADC_REG0_SAMPLING_STOP);
>> +
>> + /* wait until all modules are stopped */
>> + meson_saradc_wait_busy_clear(indio_dev);
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
>> +}
>> +
>> +static void meson_saradc_lock(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + int val;
>> +
>> + mutex_lock(&indio_dev->mlock);
>> +
>> + /* prevent BL30 from using the SAR ADC while we are using it */
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>> + SAR_ADC_DELAY_KERNEL_BUSY,
>> + SAR_ADC_DELAY_KERNEL_BUSY);
>> +
>> + /* wait until BL30 releases it's lock (so we can use the SAR ADC) */
>> + do {
>> + udelay(1);
>> + regmap_read(priv->regmap, SAR_ADC_DELAY, &val);
>> + } while (val & SAR_ADC_DELAY_BL30_BUSY);
>> +}
>> +
>> +static void meson_saradc_unlock(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> +
>> + /* allow BL30 to use the SAR ADC again */
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>> + SAR_ADC_DELAY_KERNEL_BUSY, 0);
>> +
>> + mutex_unlock(&indio_dev->mlock);
>> +}
>> +
>> +static int meson_saradc_get_sample(struct iio_dev *indio_dev,
>> + const struct iio_chan_spec *chan,
>> + enum meson_saradc_avg_mode avg_mode,
>> + enum meson_saradc_num_samples avg_samples,
>> + int *val)
>> +{
>> + int ret, tmp;
>> +
>> + meson_saradc_lock(indio_dev);
>> +
>> + /* clear old values from the FIFO buffer, ignoring errors */
>> + meson_saradc_read_raw_sample(indio_dev, chan, &tmp);
>> +
>> + meson_saradc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
>> +
>> + meson_saradc_enable_channel(indio_dev, chan);
>> +
>> + meson_saradc_start_sample_engine(indio_dev);
>> + ret = meson_saradc_read_raw_sample(indio_dev, chan, val);
>> + meson_saradc_stop_sample_engine(indio_dev);
>> +
>> + meson_saradc_unlock(indio_dev);
>> +
>> + if (ret) {
>> + dev_warn(&indio_dev->dev,
>> + "failed to read sample for channel %d: %d\n",
>> + chan->channel, ret);
>> + return ret;
>> + }
>> +
>> + return IIO_VAL_INT;
>> +}
>> +
>> +static int meson_saradc_iio_info_read_raw(struct iio_dev *indio_dev,
>> + const struct iio_chan_spec *chan,
>> + int *val, int *val2, long mask)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + int ret;
>> +
>> + switch (mask) {
>> + case IIO_CHAN_INFO_RAW:
>> + return meson_saradc_get_sample(indio_dev, chan, NO_AVERAGING,
>> + ONE_SAMPLE, val);
>> + break;
>> +
>> + case IIO_CHAN_INFO_AVERAGE_RAW:
>> + return meson_saradc_get_sample(indio_dev, chan, MEAN_AVERAGING,
>> + EIGHT_SAMPLES, val);
>> + break;
>> +
>> + case IIO_CHAN_INFO_SCALE:
>> + ret = regulator_get_voltage(priv->vref);
>> + if (ret < 0) {
>> + dev_err(&indio_dev->dev,
>> + "failed to get vref voltage: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + *val = ret / 1000;
>> + *val2 = priv->resolution;
>> + return IIO_VAL_FRACTIONAL_LOG2;
>> +
>> + default:
>> + return -EINVAL;
>> + }
>> +}
>> +
>> +static int meson_saradc_clk_init(struct iio_dev *indio_dev, void __iomem *base)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + struct clk_init_data init;
>> + char clk_name[32];
>> + const char *clk_parents[1];
>> +
>> + snprintf(clk_name, sizeof(clk_name), "%s#adc_div",
>> + of_node_full_name(indio_dev->dev.of_node));
>> + init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
>> + init.flags = 0;
>> + init.ops = &clk_divider_ops;
>> + clk_parents[0] = __clk_get_name(priv->clkin);
>> + init.parent_names = clk_parents;
>> + init.num_parents = 1;
>> +
>> + priv->clk_div.reg = base + SAR_ADC_REG3;
>> + priv->clk_div.shift = SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
>> + priv->clk_div.width = SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
>> + priv->clk_div.hw.init = &init;
>> + priv->clk_div.flags = 0;
>> +
>> + priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
>> + &priv->clk_div.hw);
>> + if (WARN_ON(IS_ERR(priv->adc_div_clk)))
>> + return PTR_ERR(priv->adc_div_clk);
>> +
>> + snprintf(clk_name, sizeof(clk_name), "%s#adc_en",
>> + of_node_full_name(indio_dev->dev.of_node));
>> + init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
>> + init.flags = CLK_SET_RATE_PARENT;
>> + init.ops = &clk_gate_ops;
>> + clk_parents[0] = __clk_get_name(priv->adc_div_clk);
>> + init.parent_names = clk_parents;
>> + init.num_parents = 1;
>> +
>> + priv->clk_gate.reg = base + SAR_ADC_REG3;
>> + priv->clk_gate.bit_idx = fls(SAR_ADC_REG3_CLK_EN);
>> + priv->clk_gate.hw.init = &init;
>> +
>> + priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
>> + if (WARN_ON(IS_ERR(priv->adc_clk)))
>> + return PTR_ERR(priv->adc_clk);
>> +
>> + return 0;
>> +}
>> +
>> +static int meson_saradc_init(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + int regval, ret;
>> +
>> + /* make sure we start at CH7 input */
> why? Seems like a little more detail would be good here ;)
I'll change this to "make sure we start at CH7 input since the other
muxes are only used for internal calibration." in v2
>> + meson_saradc_set_channel7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
>> +
>> + regmap_read(priv->regmap, SAR_ADC_REG3, ®val);
>> + if (regval & SAR_ADC_REG3_BL30_INITIALIZED) {
>> + dev_info(&indio_dev->dev, "already initialized by BL30\n");
>> + return 0;
>> + }
>> +
>> + dev_info(&indio_dev->dev, "initializing SAR ADC\n");
> I'd argue this provides no useful info so should be dropped.
> Useful for debugging no doubt, but just noise going forward.
do you want me to remove them or should I turn them into dev_dbg() (so
they can be enabled for debugging purposes)?
>> +
>> + meson_saradc_stop_sample_engine(indio_dev);
>> +
>> + /* update the channel 6 MUX to select the temperature sensor */
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>> + SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
>> + SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
>> +
>> + /* disable all channels by default */
>> + regmap_write(priv->regmap, SAR_ADC_CHAN_LIST, 0x0);
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
>> + SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
>> + SAR_ADC_REG3_CNTL_USE_SC_DLY,
>> + SAR_ADC_REG3_CNTL_USE_SC_DLY);
>> +
>> + /* delay between two samples = (10+1) * 1uS */
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>> + SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
>> + FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK, 10));
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>> + SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
>> + FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 0));
>> +
>> + /* delay between two samples = (10+1) * 1uS */
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>> + SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
>> + FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 10));
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>> + SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
>> + FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 1));
>> +
> Cool. I hadn't come across FIELD_PREP before. Neater and tidier than having
> a shift and a mask for at least some usecases.
I think these were introduced with v4.9. I like them because I tend
use GENMASK() incorrectly and with those macros I get an error at
compile-time (without having to debug my code at all)
>> + ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
>> + if (ret) {
>> + dev_err(&indio_dev->dev,
>> + "failed to set adc parent to clkin\n");
>> + return ret;
>> + }
>> +
>> + ret = clk_set_rate(priv->adc_clk, 1200000);
>> + if (ret) {
>> + dev_err(&indio_dev->dev, "failed to set adc clock rate\n");
>> + return ret;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int meson_saradc_hw_enable(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + int ret;
>> +
>> + meson_saradc_lock(indio_dev);
>> +
>> + ret = regulator_enable(priv->vref);
>> + if (ret < 0) {
>> + dev_err(&indio_dev->dev, "failed to enable vref regulator\n");
>> + goto err_vref;
>> + }
>> +
>> + ret = clk_prepare_enable(priv->core_clk);
>> + if (ret) {
>> + dev_err(&indio_dev->dev, "failed to enable core clk\n");
>> + goto err_core_clk;
>> + }
>> +
>> + ret = clk_prepare_enable(priv->sana_clk);
>> + if (ret) {
>> + dev_err(&indio_dev->dev, "failed to enable sana clk\n");
>> + goto err_sana_clk;
>> + }
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG11,
>> + SAR_ADC_REG11_BANDGAP_EN, SAR_ADC_REG11_BANDGAP_EN);
> Is this controlling an offset for a bandgap or some actual electronics?
> Not sure if it should be disabled on error and the datasheets I've found are
> far from great! You disable it in the disable, so I'd expect it to be
> unwound on error in here too.
actually the bandgap is not documented at all :(
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN,
>> + SAR_ADC_REG3_ADC_EN);
> The fact you turn this of in the disable suggests to me that on error
> you should be doing it in here too.
I will disable this along with SAR_ADC_REG11_BANDGAP_EN in the
err_adc_clk label, thanks for spotting this.
>> +
>> + udelay(5);
>> +
>> + ret = clk_prepare_enable(priv->adc_clk);
>> + if (ret) {
>> + dev_err(&indio_dev->dev, "failed to enable adc_en clk\n");
>> + goto err_adc_clk;
>> + }
>> +
>> + meson_saradc_unlock(indio_dev);
>> +
>> + return 0;
>> +
>> +err_adc_clk:
>> + clk_disable_unprepare(priv->sana_clk);
>> +err_sana_clk:
>> + clk_disable_unprepare(priv->core_clk);
>> +err_core_clk:
>> + regulator_disable(priv->vref);
>> +err_vref:
>> + meson_saradc_unlock(indio_dev);
>> + return ret;
>> +}
>> +
>> +static void meson_saradc_hw_disable(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> +
>> + meson_saradc_lock(indio_dev);
>> +
>> + clk_disable_unprepare(priv->adc_clk);
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN, 0);
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG11,
>> + SAR_ADC_REG11_BANDGAP_EN, 0);
>> +
>> + clk_disable_unprepare(priv->sana_clk);
>> + clk_disable_unprepare(priv->core_clk);
>> +
>> + regulator_disable(priv->vref);
>> +
>> + meson_saradc_unlock(indio_dev);
>> +}
>> +
>> +static const struct iio_info meson_saradc_iio_info = {
>> + .read_raw = meson_saradc_iio_info_read_raw,
>> + .driver_module = THIS_MODULE,
>> +};
>> +
>> +static const struct of_device_id meson_saradc_of_match[] = {
>> + {
>> + .compatible = "amlogic,meson-gxbb-saradc",
>> + .data = (void *)10,
> Might have been worth having a structure array indexed from an enum.
> For now it is overkill, but seems likely there are a few other differences
> that aren't supported yet?
what do you mean with "structure array indexed from an enum"? I can
introduce some match-specific struct if you want (just like it's done
in rockchip_saradc.c with "struct rockchip_saradc_data").
>> + }, {
>> + .compatible = "amlogic,meson-gxl-saradc",
>> + .data = (void *)12,
>> + },
>> + {},
>> +};
>> +MODULE_DEVICE_TABLE(of, meson_saradc_of_match);
>> +
>> +static int meson_saradc_probe(struct platform_device *pdev)
>> +{
>> + struct meson_saradc_priv *priv;
>> + struct iio_dev *indio_dev;
>> + struct resource *res;
>> + void __iomem *base;
>> + const struct of_device_id *match;
>> + int ret;
>> +
>> + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
>> + if (!indio_dev) {
>> + dev_err(&pdev->dev, "failed allocating iio device\n");
>> + return -ENOMEM;
>> + }
>> +
>> + priv = iio_priv(indio_dev);
>> +
>> + match = of_match_device(meson_saradc_of_match, &pdev->dev);
>> + priv->resolution = (unsigned long)match->data;
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + base = devm_ioremap_resource(&pdev->dev, res);
>> + if (IS_ERR(base))
>> + return PTR_ERR(base);
>> +
>> + priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
>> + &meson_saradc_regmap_config);
>> + if (IS_ERR(priv->regmap))
>> + return PTR_ERR(priv->regmap);
>> +
>> + init_completion(&priv->completion);
>> +
>> + priv->clkin = devm_clk_get(&pdev->dev, "clkin");
>> + if (IS_ERR(priv->clkin)) {
>> + dev_err(&pdev->dev, "failed to get clkin\n");
>> + return PTR_ERR(priv->clkin);
>> + }
>> +
>> + priv->core_clk = devm_clk_get(&pdev->dev, "core");
>> + if (IS_ERR(priv->core_clk)) {
>> + dev_err(&pdev->dev, "failed to get core clk\n");
>> + return PTR_ERR(priv->core_clk);
>> + }
>> +
>> + priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
> Oh for a devm_clk_get_optional to handle this boiler plate neatly.
> It's been suggested before, but nothing seems to have come of it.
I guess quite a few drivers would benefit from that. maybe we should
take this to the linux-clk list again?
> Some array clk get functions might also clean this up a touch.
yes, unfortunately in this case it's not that easy as it would have to
allow a mix of mandatory and optional clocks. Additionally I cannot
bulk-enable them unconditionally since some of these are simple gates,
others need to be reparented and for some the rate has to be set.
>> + if (IS_ERR(priv->sana_clk)) {
>> + if (PTR_ERR(priv->sana_clk) == -ENOENT) {
>> + priv->sana_clk = NULL;
>> + } else {
>> + dev_err(&pdev->dev, "failed to get sana clk\n");
>> + return PTR_ERR(priv->sana_clk);
>> + }
>> + }
>> +
>> + priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
>> + if (IS_ERR(priv->adc_clk)) {
>> + if (PTR_ERR(priv->adc_clk) == -ENOENT) {
>> + priv->adc_clk = NULL;
>> + } else {
>> + dev_err(&pdev->dev, "failed to get adc clk\n");
>> + return PTR_ERR(priv->adc_clk);
>> + }
>> + }
>> +
>> + priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
>> + if (IS_ERR(priv->adc_sel_clk)) {
>> + if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
>> + priv->adc_sel_clk = NULL;
>> + } else {
>> + dev_err(&pdev->dev, "failed to get adc_sel clk\n");
>> + return PTR_ERR(priv->adc_sel_clk);
>> + }
>> + }
>> +
>> + /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
>> + if (!priv->adc_clk) {
>> + ret = meson_saradc_clk_init(indio_dev, base);
>> + if (ret)
>> + return ret;
>> + }
>> +
>> + priv->vref = devm_regulator_get(&pdev->dev, "vref");
>> + if (IS_ERR(priv->vref)) {
>> + dev_err(&pdev->dev, "failed to get vref regulator\n");
>> + return PTR_ERR(priv->vref);
>> + }
>> +
>> + ret = meson_saradc_init(indio_dev);
>> + if (ret)
>> + goto err;
>> +
>> + ret = meson_saradc_hw_enable(indio_dev);
>> + if (ret)
>> + goto err;
>> +
>> + platform_set_drvdata(pdev, indio_dev);
>> +
>> + indio_dev->name = dev_name(&pdev->dev);
>> + indio_dev->dev.parent = &pdev->dev;
>> + indio_dev->dev.of_node = pdev->dev.of_node;
>> + indio_dev->modes = INDIO_DIRECT_MODE;
>> + indio_dev->info = &meson_saradc_iio_info;
>> +
>> + indio_dev->channels = meson_saradc_iio_channels;
>> + indio_dev->num_channels = SAR_ADC_NUM_CHANNELS;
>> +
>> + ret = iio_device_register(indio_dev);
>> + if (ret)
>> + goto err_hw;
>> +
>> + return 0;
>> +
>> +err_hw:
>> + meson_saradc_hw_disable(indio_dev);
>> +err:
>> + return ret;
>> +}
>> +
>> +static int meson_saradc_remove(struct platform_device *pdev)
>> +{
>> + struct iio_dev *indio_dev = platform_get_drvdata(pdev);
>> +
>> + meson_saradc_hw_disable(indio_dev);
>> + iio_device_unregister(indio_dev);
>> +
>> + return 0;
>> +}
>> +
>> +#ifdef CONFIG_PM_SLEEP
>> +static int meson_saradc_suspend(struct device *dev)
>> +{
>> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
>> +
>> + meson_saradc_hw_disable(indio_dev);
>> +
>> + return 0;
>> +}
>> +
>> +static int meson_saradc_resume(struct device *dev)
>> +{
>> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
>> +
>> + return meson_saradc_hw_enable(indio_dev);
>> +}
>> +#endif /* CONFIG_PM_SLEEP */
>> +
>> +static SIMPLE_DEV_PM_OPS(meson_saradc_pm_ops,
>> + meson_saradc_suspend, meson_saradc_resume);
>> +
>> +static struct platform_driver meson_saradc_driver = {
>> + .probe = meson_saradc_probe,
>> + .remove = meson_saradc_remove,
>> + .driver = {
>> + .name = "meson-saradc",
>> + .of_match_table = meson_saradc_of_match,
>> + .pm = &meson_saradc_pm_ops,
>> + },
>> +};
>> +
>> +module_platform_driver(meson_saradc_driver);
>> +
>> +MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
>> +MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
>> +MODULE_LICENSE("GPL v2");
>>
>
Regards,
Martin
[0] http://lists.infradead.org/pipermail/linux-amlogic/2016-August/000986.html
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
@ 2017-01-14 17:44 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-14 17:44 UTC (permalink / raw)
To: linus-amlogic
Hi Jonathan,
thank you for the review!
(further comments from me inline)
I think I'll send an updated version on Monday.
On Sat, Jan 14, 2017 at 3:46 PM, Jonathan Cameron <jic23@kernel.org> wrote:
> On 11/01/17 17:43, Martin Blumenstingl wrote:
>> This adds support for the SAR (Successive Approximation Register) ADC
>> on the Amlogic Meson SoCs.
>>
>> The code is based on the public S805 (Meson8b) and S905 (GXBB)
>> datasheets, as well as by reading (various versions of) the vendor
>> driver and by inspecting the registers on the vendor kernels of my
>> testing-hardware.
>>
>> Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
>> 10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
>> The code was written to support older SoCs (Meson8 and Meson8b) as well,
>> but due to lack of actual testing-hardware no of_device_id was added for
>> these.
>>
>> Two "features" from the vendor driver are currently missing:
>> - the vendor driver uses channel #7 for calibration (this improves the
>> accuracy of the results - in my tests the results were less than 3%
>> off without calibration compared to the vendor driver). Adding support
>> for this should be easy, but is not required for most applications.
>> - channel #6 is connected to the SoCs internal temperature sensor.
>> Adding support for this is probably not so easy since (based on the
>> u-boot sources) most SoC versions are using different registers and
>> algorithms for the conversion from "ADC value" to temperature.
>>
>> Supported by the hardware but currently not supported by the driver:
>> - reading multiple channels at the same time (the hardware has a FIFO
>> buffer which stores multiple results)
>> - continuous sampling (this would require a way to enable this
>> individually because otherwise the ADC would be drawing power
>> constantly)
>> - interrupt support (similar to the vendor driver this new driver is
>> polling the results. It is unclear if the IRQ-mode is supported on
>> older (Meson6 or Meson8) hardware as well or if there are any errata)
>>
> Russell Cc'd for a quick question on the clk api.
a quick side-note the clk API: my driver is a clock consumer and
provider at the same time. This seems to be a recurring pattern in
Amlogic hardware designs (as the MMC and DWMAC glue drivers are doing
this also), see [0]
> Ideally include a source for datasheets if available. Saves time googling and
> perhaps getting the wrong thing!
OK, will do this in v2
> A few other minor comments inline. Pretty good V1.
thanks :-)
> Jonathan
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>> ---
>> drivers/iio/adc/Kconfig | 12 +
>> drivers/iio/adc/Makefile | 1 +
>> drivers/iio/adc/meson_saradc.c | 860 +++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 873 insertions(+)
>> create mode 100644 drivers/iio/adc/meson_saradc.c
>>
>> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
>> index 9c8b558ba19e..86059b9b91bf 100644
>> --- a/drivers/iio/adc/Kconfig
>> +++ b/drivers/iio/adc/Kconfig
>> @@ -371,6 +371,18 @@ config MEN_Z188_ADC
>> This driver can also be built as a module. If so, the module will be
>> called men_z188_adc.
>>
>> +config MESON_SARADC
>> + tristate "Amlogic Meson SAR ADC driver"
>> + default ARCH_MESON
>> + depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
>> + select REGMAP_MMIO
>> + help
>> + Say yes here to build support for the SAR ADC found in Amlogic Meson
>> + SoCs.
>> +
>> + To compile this driver as a module, choose M here: the
>> + module will be called meson_saradc.
>> +
>> config MXS_LRADC
>> tristate "Freescale i.MX23/i.MX28 LRADC"
>> depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
>> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
>> index d36c4be8d1fc..de05b9e75f8f 100644
>> --- a/drivers/iio/adc/Makefile
>> +++ b/drivers/iio/adc/Makefile
>> @@ -36,6 +36,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
>> obj-$(CONFIG_MCP3422) += mcp3422.o
>> obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
>> obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
>> +obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
>> obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
>> obj-$(CONFIG_NAU7802) += nau7802.o
>> obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
>> diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
>> new file mode 100644
>> index 000000000000..06e8ac620385
>> --- /dev/null
>> +++ b/drivers/iio/adc/meson_saradc.c
>> @@ -0,0 +1,860 @@
>> +/*
>> + * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
>> + *
>> + * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#include <linux/bitfield.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/io.h>
>> +#include <linux/iio/iio.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>> +#include <linux/clk.h>
>> +#include <linux/completion.h>
>> +#include <linux/delay.h>
>> +#include <linux/reset.h>
>> +#include <linux/regmap.h>
>> +#include <linux/regulator/consumer.h>
>> +
>> +#define SAR_ADC_REG0 0x00
>> + #define SAR_ADC_REG0_PANEL_DETECT BIT(31)
>> + #define SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
>> + #define SAR_ADC_REG0_DELTA_BUSY BIT(30)
>> + #define SAR_ADC_REG0_AVG_BUSY BIT(29)
>> + #define SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
>> + #define SAR_ADC_REG0_FIFO_FULL BIT(27)
>> + #define SAR_ADC_REG0_FIFO_EMPTY BIT(26)
>> + #define SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
>> + #define SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
>> + #define SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
>> + #define SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
>> + #define SAR_ADC_REG0_SAMPLING_STOP BIT(14)
>> + #define SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
>> + #define SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
>> + #define SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
>> + #define SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
>> + #define SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
>> + #define SAR_ADC_REG0_SAMPLING_START BIT(2)
>> + #define SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
>> + #define SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
>> +
>> +#define SAR_ADC_CHAN_LIST 0x04
>> + #define SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
>> + #define SAR_ADC_CHAN_CHAN_ENTRY_MASK(_chan) \
>> + (GENMASK(2, 0) << (_chan * 3))
>> +
>> +#define SAR_ADC_AVG_CNTL 0x08
>> + #define SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
>> + (16 + (_chan * 2))
>> + #define SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
>> + (GENMASK(17, 16) << (_chan * 2))
>> + #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
>> + (0 + (_chan * 2))
>> + #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
>> + (GENMASK(1, 0) << (_chan * 2))
>> +
>> +#define SAR_ADC_REG3 0x0c
>> + #define SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
>> + #define SAR_ADC_REG3_CLK_EN BIT(30)
>> + #define SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
>> + #define SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
>> + #define SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
>> + #define SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
>> + #define SAR_ADC_REG3_DETECT_EN BIT(22)
>> + #define SAR_ADC_REG3_ADC_EN BIT(21)
>> + #define SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
>> + #define SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
>> + #define SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
>> + #define SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
>> + #define SAR_ADC_REG3_ADC_CLK_DIV_MASK GENMASK(15, 10)
>> + #define SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
>> + #define SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
>> +
>> +#define SAR_ADC_DELAY 0x10
>> + #define SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
>> + #define SAR_ADC_DELAY_BL30_BUSY BIT(15)
>> + #define SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
>> + #define SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
>> + #define SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
>> + #define SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
>> +
>> +#define SAR_ADC_LAST_RD 0x14
>> + #define SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
>> + #define SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
>> +
>> +#define SAR_ADC_FIFO_RD 0x18
>> + #define SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
>> + #define SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
>> +
>> +#define SAR_ADC_AUX_SW 0x1c
>> + #define SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
>> + (GENMASK(10, 8) << ((_chan - 2) * 2))
>> + #define SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
>> + #define SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
>> + #define SAR_ADC_AUX_SW_MODE_SEL BIT(4)
>> + #define SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
>> + #define SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
>> + #define SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
>> + #define SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
>> +
>> +#define SAR_ADC_CHAN_10_SW 0x20
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
>> + #define SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
>> + #define SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
>> +
>> +#define SAR_ADC_DETECT_IDLE_SW 0x24
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK GENMASK(25, 23)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_P_MUX BIT(22)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_N_MUX BIT(21)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YP_DRIVE_SW BIT(19)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XP_DRIVE_SW BIT(18)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YM_DRIVE_SW BIT(17)
>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XM_DRIVE_SW BIT(16)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK GENMASK(9, 7)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_P_MUX BIT(6)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_N_MUX BIT(5)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YP_DRIVE_SW BIT(3)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XP_DRIVE_SW BIT(2)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YM_DRIVE_SW BIT(1)
>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XM_DRIVE_SW BIT(0)
>> +
>> +#define SAR_ADC_DELTA_10 0x28
>> + #define SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
>> + #define SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
>> + #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_SHIFT 16
>> + #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
>> + #define SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
>> + #define SAR_ADC_DELTA_10_TS_C_SHIFT 11
>> + #define SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
>> + #define SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
>> + #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_SHIFT 0
>> + #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
>> +
>> +/* NOTE: registers from here are undocumented (the vendor Linux kernel driver
>> + * and u-boot source served as reference). These only seem to be relevant on
>> + * GXBB and newer.
>> + */
>> +#define SAR_ADC_REG11 0x2c
>> + #define SAR_ADC_REG11_BANDGAP_EN BIT(13)
>> +
>> +#define SAR_ADC_REG13 0x34
>> + #define SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
>> +
>> +#define SAR_ADC_MAX_FIFO_SIZE 32
>> +#define SAR_ADC_NUM_CHANNELS ARRAY_SIZE(meson_saradc_iio_channels)
>> +#define SAR_ADC_VALUE_MASK(_priv) (BIT(_priv->resolution) - 1)
>> +
>> +#define MESON_SAR_ADC_CHAN(_chan, _type) { \
>> + .type = _type, \
>> + .indexed = true, \
>> + .channel = _chan, \
>> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
>> + BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
>> + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
>> + .datasheet_name = "SAR_ADC_CH"#_chan, \
>> +}
>> +
>> +/* TODO: the hardware supports IIO_TEMP for channel 6 as well which is
> Multline comment syntax.
I got this wrong in 2 other places as well. will be fixed in v2, thanks!
>> + * currently not supported by this driver.
>> + */
>> +static const struct iio_chan_spec meson_saradc_iio_channels[] = {
>> + MESON_SAR_ADC_CHAN(0, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(1, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(2, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(3, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(4, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(5, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(6, IIO_VOLTAGE),
>> + MESON_SAR_ADC_CHAN(7, IIO_VOLTAGE),
>> + IIO_CHAN_SOFT_TIMESTAMP(8),
>> +};
>> +
>> +enum meson_saradc_avg_mode {
>> + NO_AVERAGING = 0x0,
>> + MEAN_AVERAGING = 0x1,
>> + MEDIAN_AVERAGING = 0x2,
>> +};
>> +
>> +enum meson_saradc_num_samples {
>> + ONE_SAMPLE = 0x0,
>> + TWO_SAMPLES = 0x1,
>> + FOUR_SAMPLES = 0x2,
>> + EIGHT_SAMPLES = 0x3,
>> +};
>> +
>> +enum meson_saradc_chan7_mux_sel {
>> + CHAN7_MUX_VSS = 0x0,
>> + CHAN7_MUX_VDD_DIV4 = 0x1,
>> + CHAN7_MUX_VDD_DIV2 = 0x2,
>> + CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
>> + CHAN7_MUX_VDD = 0x4,
>> + CHAN7_MUX_CH7_INPUT = 0x7,
>> +};
>> +
>> +struct meson_saradc_priv {
>> + struct regmap *regmap;
>> + struct clk *clkin;
>> + struct clk *core_clk;
>> + struct clk *sana_clk;
>> + struct clk *adc_sel_clk;
>> + struct clk *adc_clk;
>> + struct clk_gate clk_gate;
>> + struct clk *adc_div_clk;
>> + struct clk_divider clk_div;
>> + struct regulator *vref;
>> + struct completion completion;
>> + u8 resolution;
>> +};
>> +
>> +static const struct regmap_config meson_saradc_regmap_config = {
>> + .reg_bits = 8,
>> + .val_bits = 32,
>> + .reg_stride = 4,
>> + .max_register = SAR_ADC_REG13,
>> +};
>> +
>> +static unsigned int meson_saradc_get_fifo_count(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + u32 regval;
>> +
>> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
>> +
>> + return FIELD_GET(SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
>> +}
>> +
>> +static int meson_saradc_wait_busy_clear(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + int regval, timeout = 10000;
>> +
>> + do {
>> + udelay(1);
>> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
>> + } while (FIELD_GET(SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
>> +
>> + if (timeout < 0)
>> + return -ETIMEDOUT;
>> +
>> + return 0;
>> +}
>> +
>> +static int meson_saradc_read_raw_sample(struct iio_dev *indio_dev,
>> + const struct iio_chan_spec *chan,
>> + int *val)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0;
>> +
>> + ret = meson_saradc_wait_busy_clear(indio_dev);
>> + if (ret)
>> + return ret;
>> +
>> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
>> +
>> + while (meson_saradc_get_fifo_count(indio_dev) > 0 &&
>> + count < SAR_ADC_MAX_FIFO_SIZE) {
>> + regmap_read(priv->regmap, SAR_ADC_FIFO_RD, ®val);
>> +
>> + fifo_chan = FIELD_GET(SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
>> + if (fifo_chan == chan->channel) {
>> + fifo_val = FIELD_GET(SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK,
>> + regval) & SAR_ADC_VALUE_MASK(priv);
>> + sum += fifo_val;
>> + count++;
>> + }
>> + }
>> +
>> + if (!count)
>> + return -ENOENT;
>> +
>> + *val = sum / count;
>> +
>> + return 0;
>> +}
>> +
>> +static void meson_saradc_set_averaging(struct iio_dev *indio_dev,
>> + const struct iio_chan_spec *chan,
>> + enum meson_saradc_avg_mode mode,
>> + enum meson_saradc_num_samples samples)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + u32 val;
>> +
>> + val = samples << SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(chan->channel);
>> + regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
>> + SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(chan->channel),
>> + val);
>> +
>> + val = mode << SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(chan->channel);
>> + regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
>> + SAR_ADC_AVG_CNTL_AVG_MODE_MASK(chan->channel), val);
>> +}
>> +
>> +static void meson_saradc_enable_channel(struct iio_dev *indio_dev,
>> + const struct iio_chan_spec *chan)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + u32 regval;
>> +
>> + /* the SAR ADC engine allows sampling multiple channels at the same
>> + * time. to keep it simple we're only working with one *internal*
>> + * channel, which starts counting at index 0 (which means: count = 1).
>> + */
>> + regval = FIELD_PREP(SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
>> + regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
>> + SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
>> +
>> + /* map channel index 0 to the channel which we want to read */
>> + regval = FIELD_PREP(SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), chan->channel);
>> + regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
>> + SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), regval);
>> +
>> + regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
>> + chan->channel);
>> + regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
>> + SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
>> + regval);
>> +
>> + regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
>> + chan->channel);
>> + regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
>> + SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
>> + regval);
>> +
>> + if (chan->channel == 6)
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELTA_10,
>> + SAR_ADC_DELTA_10_TEMP_SEL, 0);
>> +}
>> +
>> +static void meson_saradc_set_channel7_mux(struct iio_dev *indio_dev,
>> + enum meson_saradc_chan7_mux_sel sel)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + u32 regval;
>> +
>> + regval = FIELD_PREP(SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
>> + SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
>> +
>> + usleep_range(10, 20);
>> +}
>> +
>> +static void meson_saradc_start_sample_engine(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
>> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>> + SAR_ADC_REG0_SAMPLING_START,
>> + SAR_ADC_REG0_SAMPLING_START);
>> +}
>> +
>> +static void meson_saradc_stop_sample_engine(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>> + SAR_ADC_REG0_SAMPLING_STOP,
>> + SAR_ADC_REG0_SAMPLING_STOP);
>> +
>> + /* wait until all modules are stopped */
>> + meson_saradc_wait_busy_clear(indio_dev);
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
>> +}
>> +
>> +static void meson_saradc_lock(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + int val;
>> +
>> + mutex_lock(&indio_dev->mlock);
>> +
>> + /* prevent BL30 from using the SAR ADC while we are using it */
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>> + SAR_ADC_DELAY_KERNEL_BUSY,
>> + SAR_ADC_DELAY_KERNEL_BUSY);
>> +
>> + /* wait until BL30 releases it's lock (so we can use the SAR ADC) */
>> + do {
>> + udelay(1);
>> + regmap_read(priv->regmap, SAR_ADC_DELAY, &val);
>> + } while (val & SAR_ADC_DELAY_BL30_BUSY);
>> +}
>> +
>> +static void meson_saradc_unlock(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> +
>> + /* allow BL30 to use the SAR ADC again */
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>> + SAR_ADC_DELAY_KERNEL_BUSY, 0);
>> +
>> + mutex_unlock(&indio_dev->mlock);
>> +}
>> +
>> +static int meson_saradc_get_sample(struct iio_dev *indio_dev,
>> + const struct iio_chan_spec *chan,
>> + enum meson_saradc_avg_mode avg_mode,
>> + enum meson_saradc_num_samples avg_samples,
>> + int *val)
>> +{
>> + int ret, tmp;
>> +
>> + meson_saradc_lock(indio_dev);
>> +
>> + /* clear old values from the FIFO buffer, ignoring errors */
>> + meson_saradc_read_raw_sample(indio_dev, chan, &tmp);
>> +
>> + meson_saradc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
>> +
>> + meson_saradc_enable_channel(indio_dev, chan);
>> +
>> + meson_saradc_start_sample_engine(indio_dev);
>> + ret = meson_saradc_read_raw_sample(indio_dev, chan, val);
>> + meson_saradc_stop_sample_engine(indio_dev);
>> +
>> + meson_saradc_unlock(indio_dev);
>> +
>> + if (ret) {
>> + dev_warn(&indio_dev->dev,
>> + "failed to read sample for channel %d: %d\n",
>> + chan->channel, ret);
>> + return ret;
>> + }
>> +
>> + return IIO_VAL_INT;
>> +}
>> +
>> +static int meson_saradc_iio_info_read_raw(struct iio_dev *indio_dev,
>> + const struct iio_chan_spec *chan,
>> + int *val, int *val2, long mask)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + int ret;
>> +
>> + switch (mask) {
>> + case IIO_CHAN_INFO_RAW:
>> + return meson_saradc_get_sample(indio_dev, chan, NO_AVERAGING,
>> + ONE_SAMPLE, val);
>> + break;
>> +
>> + case IIO_CHAN_INFO_AVERAGE_RAW:
>> + return meson_saradc_get_sample(indio_dev, chan, MEAN_AVERAGING,
>> + EIGHT_SAMPLES, val);
>> + break;
>> +
>> + case IIO_CHAN_INFO_SCALE:
>> + ret = regulator_get_voltage(priv->vref);
>> + if (ret < 0) {
>> + dev_err(&indio_dev->dev,
>> + "failed to get vref voltage: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + *val = ret / 1000;
>> + *val2 = priv->resolution;
>> + return IIO_VAL_FRACTIONAL_LOG2;
>> +
>> + default:
>> + return -EINVAL;
>> + }
>> +}
>> +
>> +static int meson_saradc_clk_init(struct iio_dev *indio_dev, void __iomem *base)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + struct clk_init_data init;
>> + char clk_name[32];
>> + const char *clk_parents[1];
>> +
>> + snprintf(clk_name, sizeof(clk_name), "%s#adc_div",
>> + of_node_full_name(indio_dev->dev.of_node));
>> + init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
>> + init.flags = 0;
>> + init.ops = &clk_divider_ops;
>> + clk_parents[0] = __clk_get_name(priv->clkin);
>> + init.parent_names = clk_parents;
>> + init.num_parents = 1;
>> +
>> + priv->clk_div.reg = base + SAR_ADC_REG3;
>> + priv->clk_div.shift = SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
>> + priv->clk_div.width = SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
>> + priv->clk_div.hw.init = &init;
>> + priv->clk_div.flags = 0;
>> +
>> + priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
>> + &priv->clk_div.hw);
>> + if (WARN_ON(IS_ERR(priv->adc_div_clk)))
>> + return PTR_ERR(priv->adc_div_clk);
>> +
>> + snprintf(clk_name, sizeof(clk_name), "%s#adc_en",
>> + of_node_full_name(indio_dev->dev.of_node));
>> + init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
>> + init.flags = CLK_SET_RATE_PARENT;
>> + init.ops = &clk_gate_ops;
>> + clk_parents[0] = __clk_get_name(priv->adc_div_clk);
>> + init.parent_names = clk_parents;
>> + init.num_parents = 1;
>> +
>> + priv->clk_gate.reg = base + SAR_ADC_REG3;
>> + priv->clk_gate.bit_idx = fls(SAR_ADC_REG3_CLK_EN);
>> + priv->clk_gate.hw.init = &init;
>> +
>> + priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
>> + if (WARN_ON(IS_ERR(priv->adc_clk)))
>> + return PTR_ERR(priv->adc_clk);
>> +
>> + return 0;
>> +}
>> +
>> +static int meson_saradc_init(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + int regval, ret;
>> +
>> + /* make sure we start at CH7 input */
> why? Seems like a little more detail would be good here ;)
I'll change this to "make sure we start at CH7 input since the other
muxes are only used for internal calibration." in v2
>> + meson_saradc_set_channel7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
>> +
>> + regmap_read(priv->regmap, SAR_ADC_REG3, ®val);
>> + if (regval & SAR_ADC_REG3_BL30_INITIALIZED) {
>> + dev_info(&indio_dev->dev, "already initialized by BL30\n");
>> + return 0;
>> + }
>> +
>> + dev_info(&indio_dev->dev, "initializing SAR ADC\n");
> I'd argue this provides no useful info so should be dropped.
> Useful for debugging no doubt, but just noise going forward.
do you want me to remove them or should I turn them into dev_dbg() (so
they can be enabled for debugging purposes)?
>> +
>> + meson_saradc_stop_sample_engine(indio_dev);
>> +
>> + /* update the channel 6 MUX to select the temperature sensor */
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>> + SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
>> + SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
>> +
>> + /* disable all channels by default */
>> + regmap_write(priv->regmap, SAR_ADC_CHAN_LIST, 0x0);
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
>> + SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
>> + SAR_ADC_REG3_CNTL_USE_SC_DLY,
>> + SAR_ADC_REG3_CNTL_USE_SC_DLY);
>> +
>> + /* delay between two samples = (10+1) * 1uS */
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>> + SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
>> + FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK, 10));
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>> + SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
>> + FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 0));
>> +
>> + /* delay between two samples = (10+1) * 1uS */
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>> + SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
>> + FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 10));
>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>> + SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
>> + FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 1));
>> +
> Cool. I hadn't come across FIELD_PREP before. Neater and tidier than having
> a shift and a mask for at least some usecases.
I think these were introduced with v4.9. I like them because I tend
use GENMASK() incorrectly and with those macros I get an error at
compile-time (without having to debug my code at all)
>> + ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
>> + if (ret) {
>> + dev_err(&indio_dev->dev,
>> + "failed to set adc parent to clkin\n");
>> + return ret;
>> + }
>> +
>> + ret = clk_set_rate(priv->adc_clk, 1200000);
>> + if (ret) {
>> + dev_err(&indio_dev->dev, "failed to set adc clock rate\n");
>> + return ret;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int meson_saradc_hw_enable(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> + int ret;
>> +
>> + meson_saradc_lock(indio_dev);
>> +
>> + ret = regulator_enable(priv->vref);
>> + if (ret < 0) {
>> + dev_err(&indio_dev->dev, "failed to enable vref regulator\n");
>> + goto err_vref;
>> + }
>> +
>> + ret = clk_prepare_enable(priv->core_clk);
>> + if (ret) {
>> + dev_err(&indio_dev->dev, "failed to enable core clk\n");
>> + goto err_core_clk;
>> + }
>> +
>> + ret = clk_prepare_enable(priv->sana_clk);
>> + if (ret) {
>> + dev_err(&indio_dev->dev, "failed to enable sana clk\n");
>> + goto err_sana_clk;
>> + }
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG11,
>> + SAR_ADC_REG11_BANDGAP_EN, SAR_ADC_REG11_BANDGAP_EN);
> Is this controlling an offset for a bandgap or some actual electronics?
> Not sure if it should be disabled on error and the datasheets I've found are
> far from great! You disable it in the disable, so I'd expect it to be
> unwound on error in here too.
actually the bandgap is not documented at all :(
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN,
>> + SAR_ADC_REG3_ADC_EN);
> The fact you turn this of in the disable suggests to me that on error
> you should be doing it in here too.
I will disable this along with SAR_ADC_REG11_BANDGAP_EN in the
err_adc_clk label, thanks for spotting this.
>> +
>> + udelay(5);
>> +
>> + ret = clk_prepare_enable(priv->adc_clk);
>> + if (ret) {
>> + dev_err(&indio_dev->dev, "failed to enable adc_en clk\n");
>> + goto err_adc_clk;
>> + }
>> +
>> + meson_saradc_unlock(indio_dev);
>> +
>> + return 0;
>> +
>> +err_adc_clk:
>> + clk_disable_unprepare(priv->sana_clk);
>> +err_sana_clk:
>> + clk_disable_unprepare(priv->core_clk);
>> +err_core_clk:
>> + regulator_disable(priv->vref);
>> +err_vref:
>> + meson_saradc_unlock(indio_dev);
>> + return ret;
>> +}
>> +
>> +static void meson_saradc_hw_disable(struct iio_dev *indio_dev)
>> +{
>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>> +
>> + meson_saradc_lock(indio_dev);
>> +
>> + clk_disable_unprepare(priv->adc_clk);
>> +
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN, 0);
>> + regmap_update_bits(priv->regmap, SAR_ADC_REG11,
>> + SAR_ADC_REG11_BANDGAP_EN, 0);
>> +
>> + clk_disable_unprepare(priv->sana_clk);
>> + clk_disable_unprepare(priv->core_clk);
>> +
>> + regulator_disable(priv->vref);
>> +
>> + meson_saradc_unlock(indio_dev);
>> +}
>> +
>> +static const struct iio_info meson_saradc_iio_info = {
>> + .read_raw = meson_saradc_iio_info_read_raw,
>> + .driver_module = THIS_MODULE,
>> +};
>> +
>> +static const struct of_device_id meson_saradc_of_match[] = {
>> + {
>> + .compatible = "amlogic,meson-gxbb-saradc",
>> + .data = (void *)10,
> Might have been worth having a structure array indexed from an enum.
> For now it is overkill, but seems likely there are a few other differences
> that aren't supported yet?
what do you mean with "structure array indexed from an enum"? I can
introduce some match-specific struct if you want (just like it's done
in rockchip_saradc.c with "struct rockchip_saradc_data").
>> + }, {
>> + .compatible = "amlogic,meson-gxl-saradc",
>> + .data = (void *)12,
>> + },
>> + {},
>> +};
>> +MODULE_DEVICE_TABLE(of, meson_saradc_of_match);
>> +
>> +static int meson_saradc_probe(struct platform_device *pdev)
>> +{
>> + struct meson_saradc_priv *priv;
>> + struct iio_dev *indio_dev;
>> + struct resource *res;
>> + void __iomem *base;
>> + const struct of_device_id *match;
>> + int ret;
>> +
>> + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
>> + if (!indio_dev) {
>> + dev_err(&pdev->dev, "failed allocating iio device\n");
>> + return -ENOMEM;
>> + }
>> +
>> + priv = iio_priv(indio_dev);
>> +
>> + match = of_match_device(meson_saradc_of_match, &pdev->dev);
>> + priv->resolution = (unsigned long)match->data;
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + base = devm_ioremap_resource(&pdev->dev, res);
>> + if (IS_ERR(base))
>> + return PTR_ERR(base);
>> +
>> + priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
>> + &meson_saradc_regmap_config);
>> + if (IS_ERR(priv->regmap))
>> + return PTR_ERR(priv->regmap);
>> +
>> + init_completion(&priv->completion);
>> +
>> + priv->clkin = devm_clk_get(&pdev->dev, "clkin");
>> + if (IS_ERR(priv->clkin)) {
>> + dev_err(&pdev->dev, "failed to get clkin\n");
>> + return PTR_ERR(priv->clkin);
>> + }
>> +
>> + priv->core_clk = devm_clk_get(&pdev->dev, "core");
>> + if (IS_ERR(priv->core_clk)) {
>> + dev_err(&pdev->dev, "failed to get core clk\n");
>> + return PTR_ERR(priv->core_clk);
>> + }
>> +
>> + priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
> Oh for a devm_clk_get_optional to handle this boiler plate neatly.
> It's been suggested before, but nothing seems to have come of it.
I guess quite a few drivers would benefit from that. maybe we should
take this to the linux-clk list again?
> Some array clk get functions might also clean this up a touch.
yes, unfortunately in this case it's not that easy as it would have to
allow a mix of mandatory and optional clocks. Additionally I cannot
bulk-enable them unconditionally since some of these are simple gates,
others need to be reparented and for some the rate has to be set.
>> + if (IS_ERR(priv->sana_clk)) {
>> + if (PTR_ERR(priv->sana_clk) == -ENOENT) {
>> + priv->sana_clk = NULL;
>> + } else {
>> + dev_err(&pdev->dev, "failed to get sana clk\n");
>> + return PTR_ERR(priv->sana_clk);
>> + }
>> + }
>> +
>> + priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
>> + if (IS_ERR(priv->adc_clk)) {
>> + if (PTR_ERR(priv->adc_clk) == -ENOENT) {
>> + priv->adc_clk = NULL;
>> + } else {
>> + dev_err(&pdev->dev, "failed to get adc clk\n");
>> + return PTR_ERR(priv->adc_clk);
>> + }
>> + }
>> +
>> + priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
>> + if (IS_ERR(priv->adc_sel_clk)) {
>> + if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
>> + priv->adc_sel_clk = NULL;
>> + } else {
>> + dev_err(&pdev->dev, "failed to get adc_sel clk\n");
>> + return PTR_ERR(priv->adc_sel_clk);
>> + }
>> + }
>> +
>> + /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
>> + if (!priv->adc_clk) {
>> + ret = meson_saradc_clk_init(indio_dev, base);
>> + if (ret)
>> + return ret;
>> + }
>> +
>> + priv->vref = devm_regulator_get(&pdev->dev, "vref");
>> + if (IS_ERR(priv->vref)) {
>> + dev_err(&pdev->dev, "failed to get vref regulator\n");
>> + return PTR_ERR(priv->vref);
>> + }
>> +
>> + ret = meson_saradc_init(indio_dev);
>> + if (ret)
>> + goto err;
>> +
>> + ret = meson_saradc_hw_enable(indio_dev);
>> + if (ret)
>> + goto err;
>> +
>> + platform_set_drvdata(pdev, indio_dev);
>> +
>> + indio_dev->name = dev_name(&pdev->dev);
>> + indio_dev->dev.parent = &pdev->dev;
>> + indio_dev->dev.of_node = pdev->dev.of_node;
>> + indio_dev->modes = INDIO_DIRECT_MODE;
>> + indio_dev->info = &meson_saradc_iio_info;
>> +
>> + indio_dev->channels = meson_saradc_iio_channels;
>> + indio_dev->num_channels = SAR_ADC_NUM_CHANNELS;
>> +
>> + ret = iio_device_register(indio_dev);
>> + if (ret)
>> + goto err_hw;
>> +
>> + return 0;
>> +
>> +err_hw:
>> + meson_saradc_hw_disable(indio_dev);
>> +err:
>> + return ret;
>> +}
>> +
>> +static int meson_saradc_remove(struct platform_device *pdev)
>> +{
>> + struct iio_dev *indio_dev = platform_get_drvdata(pdev);
>> +
>> + meson_saradc_hw_disable(indio_dev);
>> + iio_device_unregister(indio_dev);
>> +
>> + return 0;
>> +}
>> +
>> +#ifdef CONFIG_PM_SLEEP
>> +static int meson_saradc_suspend(struct device *dev)
>> +{
>> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
>> +
>> + meson_saradc_hw_disable(indio_dev);
>> +
>> + return 0;
>> +}
>> +
>> +static int meson_saradc_resume(struct device *dev)
>> +{
>> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
>> +
>> + return meson_saradc_hw_enable(indio_dev);
>> +}
>> +#endif /* CONFIG_PM_SLEEP */
>> +
>> +static SIMPLE_DEV_PM_OPS(meson_saradc_pm_ops,
>> + meson_saradc_suspend, meson_saradc_resume);
>> +
>> +static struct platform_driver meson_saradc_driver = {
>> + .probe = meson_saradc_probe,
>> + .remove = meson_saradc_remove,
>> + .driver = {
>> + .name = "meson-saradc",
>> + .of_match_table = meson_saradc_of_match,
>> + .pm = &meson_saradc_pm_ops,
>> + },
>> +};
>> +
>> +module_platform_driver(meson_saradc_driver);
>> +
>> +MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
>> +MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
>> +MODULE_LICENSE("GPL v2");
>>
>
Regards,
Martin
[0] http://lists.infradead.org/pipermail/linux-amlogic/2016-August/000986.html
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
2017-01-11 17:43 ` Martin Blumenstingl
(?)
(?)
@ 2017-01-15 12:26 ` Lars-Peter Clausen
-1 siblings, 0 replies; 110+ messages in thread
From: Lars-Peter Clausen @ 2017-01-15 12:26 UTC (permalink / raw)
To: Martin Blumenstingl, jic23-DgEjT+Ai2ygdnm+yROfE0A,
knaack.h-Mmb7MZpHnFY, pmeerw-jW+XmwGofnusTnJN9+BGXg,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
khilman-rdvid1DuHRBWk0Htik3J/w, linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-clk-u79uwXL29TY76Z2rM5mHXA
Cc: carlo-KA+7E9HrN00dnm+yROfE0A, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, mturquette-rdvid1DuHRBWk0Htik3J/w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, narmstrong-rdvid1DuHRBWk0Htik3J/w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 01/11/2017 06:43 PM, Martin Blumenstingl wrote:
> + indio_dev->name = dev_name(&pdev->dev);
The name is supposed to be the type of the device, e.g. part name, not the
name of parent device instance. E.g. meson-gxbb-saradc or meson-gxl-saradc
in this case.
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
@ 2017-01-15 12:26 ` Lars-Peter Clausen
0 siblings, 0 replies; 110+ messages in thread
From: Lars-Peter Clausen @ 2017-01-15 12:26 UTC (permalink / raw)
To: Martin Blumenstingl, jic23, knaack.h, pmeerw, robh+dt,
mark.rutland, khilman, linux-iio, devicetree, linux-amlogic,
linux-clk
Cc: carlo, catalin.marinas, will.deacon, mturquette, sboyd,
narmstrong, linux-arm-kernel
On 01/11/2017 06:43 PM, Martin Blumenstingl wrote:
> + indio_dev->name = dev_name(&pdev->dev);
The name is supposed to be the type of the device, e.g. part name, not the
name of parent device instance. E.g. meson-gxbb-saradc or meson-gxl-saradc
in this case.
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
@ 2017-01-15 12:26 ` Lars-Peter Clausen
0 siblings, 0 replies; 110+ messages in thread
From: Lars-Peter Clausen @ 2017-01-15 12:26 UTC (permalink / raw)
To: linux-arm-kernel
On 01/11/2017 06:43 PM, Martin Blumenstingl wrote:
> + indio_dev->name = dev_name(&pdev->dev);
The name is supposed to be the type of the device, e.g. part name, not the
name of parent device instance. E.g. meson-gxbb-saradc or meson-gxl-saradc
in this case.
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
@ 2017-01-15 12:26 ` Lars-Peter Clausen
0 siblings, 0 replies; 110+ messages in thread
From: Lars-Peter Clausen @ 2017-01-15 12:26 UTC (permalink / raw)
To: linus-amlogic
On 01/11/2017 06:43 PM, Martin Blumenstingl wrote:
> + indio_dev->name = dev_name(&pdev->dev);
The name is supposed to be the type of the device, e.g. part name, not the
name of parent device instance. E.g. meson-gxbb-saradc or meson-gxl-saradc
in this case.
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
2017-01-14 17:44 ` Martin Blumenstingl
(?)
@ 2017-01-15 13:08 ` Jonathan Cameron
-1 siblings, 0 replies; 110+ messages in thread
From: Jonathan Cameron @ 2017-01-15 13:08 UTC (permalink / raw)
To: Martin Blumenstingl
Cc: knaack.h, lars, pmeerw, robh+dt, mark.rutland, khilman,
linux-iio, devicetree, linux-amlogic, linux-clk, carlo,
catalin.marinas, will.deacon, mturquette, sboyd, narmstrong,
linux-arm-kernel, Russell King
On 14/01/17 17:44, Martin Blumenstingl wrote:
> Hi Jonathan,
>
> thank you for the review!
> (further comments from me inline)
> I think I'll send an updated version on Monday.
>
> On Sat, Jan 14, 2017 at 3:46 PM, Jonathan Cameron <jic23@kernel.org> wrote:
>> On 11/01/17 17:43, Martin Blumenstingl wrote:
>>> This adds support for the SAR (Successive Approximation Register) ADC
>>> on the Amlogic Meson SoCs.
>>>
>>> The code is based on the public S805 (Meson8b) and S905 (GXBB)
>>> datasheets, as well as by reading (various versions of) the vendor
>>> driver and by inspecting the registers on the vendor kernels of my
>>> testing-hardware.
>>>
>>> Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
>>> 10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
>>> The code was written to support older SoCs (Meson8 and Meson8b) as well,
>>> but due to lack of actual testing-hardware no of_device_id was added for
>>> these.
>>>
>>> Two "features" from the vendor driver are currently missing:
>>> - the vendor driver uses channel #7 for calibration (this improves the
>>> accuracy of the results - in my tests the results were less than 3%
>>> off without calibration compared to the vendor driver). Adding support
>>> for this should be easy, but is not required for most applications.
>>> - channel #6 is connected to the SoCs internal temperature sensor.
>>> Adding support for this is probably not so easy since (based on the
>>> u-boot sources) most SoC versions are using different registers and
>>> algorithms for the conversion from "ADC value" to temperature.
>>>
>>> Supported by the hardware but currently not supported by the driver:
>>> - reading multiple channels at the same time (the hardware has a FIFO
>>> buffer which stores multiple results)
>>> - continuous sampling (this would require a way to enable this
>>> individually because otherwise the ADC would be drawing power
>>> constantly)
>>> - interrupt support (similar to the vendor driver this new driver is
>>> polling the results. It is unclear if the IRQ-mode is supported on
>>> older (Meson6 or Meson8) hardware as well or if there are any errata)
>>>
>> Russell Cc'd for a quick question on the clk api.
> a quick side-note the clk API: my driver is a clock consumer and
> provider at the same time. This seems to be a recurring pattern in
> Amlogic hardware designs (as the MMC and DWMAC glue drivers are doing
> this also), see [0]
>
>> Ideally include a source for datasheets if available. Saves time googling and
>> perhaps getting the wrong thing!
> OK, will do this in v2
>
>> A few other minor comments inline. Pretty good V1.
> thanks :-)
>
>> Jonathan
>>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>> ---
>>> drivers/iio/adc/Kconfig | 12 +
>>> drivers/iio/adc/Makefile | 1 +
>>> drivers/iio/adc/meson_saradc.c | 860 +++++++++++++++++++++++++++++++++++++++++
>>> 3 files changed, 873 insertions(+)
>>> create mode 100644 drivers/iio/adc/meson_saradc.c
>>>
>>> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
>>> index 9c8b558ba19e..86059b9b91bf 100644
>>> --- a/drivers/iio/adc/Kconfig
>>> +++ b/drivers/iio/adc/Kconfig
>>> @@ -371,6 +371,18 @@ config MEN_Z188_ADC
>>> This driver can also be built as a module. If so, the module will be
>>> called men_z188_adc.
>>>
>>> +config MESON_SARADC
>>> + tristate "Amlogic Meson SAR ADC driver"
>>> + default ARCH_MESON
>>> + depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
>>> + select REGMAP_MMIO
>>> + help
>>> + Say yes here to build support for the SAR ADC found in Amlogic Meson
>>> + SoCs.
>>> +
>>> + To compile this driver as a module, choose M here: the
>>> + module will be called meson_saradc.
>>> +
>>> config MXS_LRADC
>>> tristate "Freescale i.MX23/i.MX28 LRADC"
>>> depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
>>> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
>>> index d36c4be8d1fc..de05b9e75f8f 100644
>>> --- a/drivers/iio/adc/Makefile
>>> +++ b/drivers/iio/adc/Makefile
>>> @@ -36,6 +36,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
>>> obj-$(CONFIG_MCP3422) += mcp3422.o
>>> obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
>>> obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
>>> +obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
>>> obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
>>> obj-$(CONFIG_NAU7802) += nau7802.o
>>> obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
>>> diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
>>> new file mode 100644
>>> index 000000000000..06e8ac620385
>>> --- /dev/null
>>> +++ b/drivers/iio/adc/meson_saradc.c
>>> @@ -0,0 +1,860 @@
>>> +/*
>>> + * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
>>> + *
>>> + * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License version 2 as
>>> + * published by the Free Software Foundation.
>>> + *
>>> + * You should have received a copy of the GNU General Public License
>>> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
>>> + */
>>> +
>>> +#include <linux/bitfield.h>
>>> +#include <linux/clk-provider.h>
>>> +#include <linux/module.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/interrupt.h>
>>> +#include <linux/io.h>
>>> +#include <linux/iio/iio.h>
>>> +#include <linux/of.h>
>>> +#include <linux/of_device.h>
>>> +#include <linux/clk.h>
>>> +#include <linux/completion.h>
>>> +#include <linux/delay.h>
>>> +#include <linux/reset.h>
>>> +#include <linux/regmap.h>
>>> +#include <linux/regulator/consumer.h>
>>> +
>>> +#define SAR_ADC_REG0 0x00
>>> + #define SAR_ADC_REG0_PANEL_DETECT BIT(31)
>>> + #define SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
>>> + #define SAR_ADC_REG0_DELTA_BUSY BIT(30)
>>> + #define SAR_ADC_REG0_AVG_BUSY BIT(29)
>>> + #define SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
>>> + #define SAR_ADC_REG0_FIFO_FULL BIT(27)
>>> + #define SAR_ADC_REG0_FIFO_EMPTY BIT(26)
>>> + #define SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
>>> + #define SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
>>> + #define SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
>>> + #define SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
>>> + #define SAR_ADC_REG0_SAMPLING_STOP BIT(14)
>>> + #define SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
>>> + #define SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
>>> + #define SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
>>> + #define SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
>>> + #define SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
>>> + #define SAR_ADC_REG0_SAMPLING_START BIT(2)
>>> + #define SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
>>> + #define SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
>>> +
>>> +#define SAR_ADC_CHAN_LIST 0x04
>>> + #define SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
>>> + #define SAR_ADC_CHAN_CHAN_ENTRY_MASK(_chan) \
>>> + (GENMASK(2, 0) << (_chan * 3))
>>> +
>>> +#define SAR_ADC_AVG_CNTL 0x08
>>> + #define SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
>>> + (16 + (_chan * 2))
>>> + #define SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
>>> + (GENMASK(17, 16) << (_chan * 2))
>>> + #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
>>> + (0 + (_chan * 2))
>>> + #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
>>> + (GENMASK(1, 0) << (_chan * 2))
>>> +
>>> +#define SAR_ADC_REG3 0x0c
>>> + #define SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
>>> + #define SAR_ADC_REG3_CLK_EN BIT(30)
>>> + #define SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
>>> + #define SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
>>> + #define SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
>>> + #define SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
>>> + #define SAR_ADC_REG3_DETECT_EN BIT(22)
>>> + #define SAR_ADC_REG3_ADC_EN BIT(21)
>>> + #define SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
>>> + #define SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
>>> + #define SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
>>> + #define SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
>>> + #define SAR_ADC_REG3_ADC_CLK_DIV_MASK GENMASK(15, 10)
>>> + #define SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
>>> + #define SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
>>> +
>>> +#define SAR_ADC_DELAY 0x10
>>> + #define SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
>>> + #define SAR_ADC_DELAY_BL30_BUSY BIT(15)
>>> + #define SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
>>> + #define SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
>>> + #define SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
>>> + #define SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
>>> +
>>> +#define SAR_ADC_LAST_RD 0x14
>>> + #define SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
>>> + #define SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
>>> +
>>> +#define SAR_ADC_FIFO_RD 0x18
>>> + #define SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
>>> + #define SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
>>> +
>>> +#define SAR_ADC_AUX_SW 0x1c
>>> + #define SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
>>> + (GENMASK(10, 8) << ((_chan - 2) * 2))
>>> + #define SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
>>> + #define SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
>>> + #define SAR_ADC_AUX_SW_MODE_SEL BIT(4)
>>> + #define SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
>>> + #define SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
>>> + #define SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
>>> + #define SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
>>> +
>>> +#define SAR_ADC_CHAN_10_SW 0x20
>>> + #define SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
>>> +
>>> +#define SAR_ADC_DETECT_IDLE_SW 0x24
>>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
>>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK GENMASK(25, 23)
>>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_P_MUX BIT(22)
>>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_N_MUX BIT(21)
>>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
>>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YP_DRIVE_SW BIT(19)
>>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XP_DRIVE_SW BIT(18)
>>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YM_DRIVE_SW BIT(17)
>>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XM_DRIVE_SW BIT(16)
>>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK GENMASK(9, 7)
>>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_P_MUX BIT(6)
>>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_N_MUX BIT(5)
>>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
>>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YP_DRIVE_SW BIT(3)
>>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XP_DRIVE_SW BIT(2)
>>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YM_DRIVE_SW BIT(1)
>>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XM_DRIVE_SW BIT(0)
>>> +
>>> +#define SAR_ADC_DELTA_10 0x28
>>> + #define SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
>>> + #define SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
>>> + #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_SHIFT 16
>>> + #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
>>> + #define SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
>>> + #define SAR_ADC_DELTA_10_TS_C_SHIFT 11
>>> + #define SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
>>> + #define SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
>>> + #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_SHIFT 0
>>> + #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
>>> +
>>> +/* NOTE: registers from here are undocumented (the vendor Linux kernel driver
>>> + * and u-boot source served as reference). These only seem to be relevant on
>>> + * GXBB and newer.
>>> + */
>>> +#define SAR_ADC_REG11 0x2c
>>> + #define SAR_ADC_REG11_BANDGAP_EN BIT(13)
>>> +
>>> +#define SAR_ADC_REG13 0x34
>>> + #define SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
>>> +
>>> +#define SAR_ADC_MAX_FIFO_SIZE 32
>>> +#define SAR_ADC_NUM_CHANNELS ARRAY_SIZE(meson_saradc_iio_channels)
>>> +#define SAR_ADC_VALUE_MASK(_priv) (BIT(_priv->resolution) - 1)
>>> +
>>> +#define MESON_SAR_ADC_CHAN(_chan, _type) { \
>>> + .type = _type, \
>>> + .indexed = true, \
>>> + .channel = _chan, \
>>> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
>>> + BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
>>> + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
>>> + .datasheet_name = "SAR_ADC_CH"#_chan, \
>>> +}
>>> +
>>> +/* TODO: the hardware supports IIO_TEMP for channel 6 as well which is
>> Multline comment syntax.
> I got this wrong in 2 other places as well. will be fixed in v2, thanks!
>
>>> + * currently not supported by this driver.
>>> + */
>>> +static const struct iio_chan_spec meson_saradc_iio_channels[] = {
>>> + MESON_SAR_ADC_CHAN(0, IIO_VOLTAGE),
>>> + MESON_SAR_ADC_CHAN(1, IIO_VOLTAGE),
>>> + MESON_SAR_ADC_CHAN(2, IIO_VOLTAGE),
>>> + MESON_SAR_ADC_CHAN(3, IIO_VOLTAGE),
>>> + MESON_SAR_ADC_CHAN(4, IIO_VOLTAGE),
>>> + MESON_SAR_ADC_CHAN(5, IIO_VOLTAGE),
>>> + MESON_SAR_ADC_CHAN(6, IIO_VOLTAGE),
>>> + MESON_SAR_ADC_CHAN(7, IIO_VOLTAGE),
>>> + IIO_CHAN_SOFT_TIMESTAMP(8),
>>> +};
>>> +
>>> +enum meson_saradc_avg_mode {
>>> + NO_AVERAGING = 0x0,
>>> + MEAN_AVERAGING = 0x1,
>>> + MEDIAN_AVERAGING = 0x2,
>>> +};
>>> +
>>> +enum meson_saradc_num_samples {
>>> + ONE_SAMPLE = 0x0,
>>> + TWO_SAMPLES = 0x1,
>>> + FOUR_SAMPLES = 0x2,
>>> + EIGHT_SAMPLES = 0x3,
>>> +};
>>> +
>>> +enum meson_saradc_chan7_mux_sel {
>>> + CHAN7_MUX_VSS = 0x0,
>>> + CHAN7_MUX_VDD_DIV4 = 0x1,
>>> + CHAN7_MUX_VDD_DIV2 = 0x2,
>>> + CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
>>> + CHAN7_MUX_VDD = 0x4,
>>> + CHAN7_MUX_CH7_INPUT = 0x7,
>>> +};
>>> +
>>> +struct meson_saradc_priv {
>>> + struct regmap *regmap;
>>> + struct clk *clkin;
>>> + struct clk *core_clk;
>>> + struct clk *sana_clk;
>>> + struct clk *adc_sel_clk;
>>> + struct clk *adc_clk;
>>> + struct clk_gate clk_gate;
>>> + struct clk *adc_div_clk;
>>> + struct clk_divider clk_div;
>>> + struct regulator *vref;
>>> + struct completion completion;
>>> + u8 resolution;
>>> +};
>>> +
>>> +static const struct regmap_config meson_saradc_regmap_config = {
>>> + .reg_bits = 8,
>>> + .val_bits = 32,
>>> + .reg_stride = 4,
>>> + .max_register = SAR_ADC_REG13,
>>> +};
>>> +
>>> +static unsigned int meson_saradc_get_fifo_count(struct iio_dev *indio_dev)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + u32 regval;
>>> +
>>> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
>>> +
>>> + return FIELD_GET(SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
>>> +}
>>> +
>>> +static int meson_saradc_wait_busy_clear(struct iio_dev *indio_dev)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + int regval, timeout = 10000;
>>> +
>>> + do {
>>> + udelay(1);
>>> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
>>> + } while (FIELD_GET(SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
>>> +
>>> + if (timeout < 0)
>>> + return -ETIMEDOUT;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int meson_saradc_read_raw_sample(struct iio_dev *indio_dev,
>>> + const struct iio_chan_spec *chan,
>>> + int *val)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0;
>>> +
>>> + ret = meson_saradc_wait_busy_clear(indio_dev);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
>>> +
>>> + while (meson_saradc_get_fifo_count(indio_dev) > 0 &&
>>> + count < SAR_ADC_MAX_FIFO_SIZE) {
>>> + regmap_read(priv->regmap, SAR_ADC_FIFO_RD, ®val);
>>> +
>>> + fifo_chan = FIELD_GET(SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
>>> + if (fifo_chan == chan->channel) {
>>> + fifo_val = FIELD_GET(SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK,
>>> + regval) & SAR_ADC_VALUE_MASK(priv);
>>> + sum += fifo_val;
>>> + count++;
>>> + }
>>> + }
>>> +
>>> + if (!count)
>>> + return -ENOENT;
>>> +
>>> + *val = sum / count;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static void meson_saradc_set_averaging(struct iio_dev *indio_dev,
>>> + const struct iio_chan_spec *chan,
>>> + enum meson_saradc_avg_mode mode,
>>> + enum meson_saradc_num_samples samples)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + u32 val;
>>> +
>>> + val = samples << SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(chan->channel);
>>> + regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
>>> + SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(chan->channel),
>>> + val);
>>> +
>>> + val = mode << SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(chan->channel);
>>> + regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
>>> + SAR_ADC_AVG_CNTL_AVG_MODE_MASK(chan->channel), val);
>>> +}
>>> +
>>> +static void meson_saradc_enable_channel(struct iio_dev *indio_dev,
>>> + const struct iio_chan_spec *chan)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + u32 regval;
>>> +
>>> + /* the SAR ADC engine allows sampling multiple channels at the same
>>> + * time. to keep it simple we're only working with one *internal*
>>> + * channel, which starts counting at index 0 (which means: count = 1).
>>> + */
>>> + regval = FIELD_PREP(SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
>>> + regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
>>> + SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
>>> +
>>> + /* map channel index 0 to the channel which we want to read */
>>> + regval = FIELD_PREP(SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), chan->channel);
>>> + regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
>>> + SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), regval);
>>> +
>>> + regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
>>> + chan->channel);
>>> + regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
>>> + SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
>>> + regval);
>>> +
>>> + regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
>>> + chan->channel);
>>> + regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
>>> + SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
>>> + regval);
>>> +
>>> + if (chan->channel == 6)
>>> + regmap_update_bits(priv->regmap, SAR_ADC_DELTA_10,
>>> + SAR_ADC_DELTA_10_TEMP_SEL, 0);
>>> +}
>>> +
>>> +static void meson_saradc_set_channel7_mux(struct iio_dev *indio_dev,
>>> + enum meson_saradc_chan7_mux_sel sel)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + u32 regval;
>>> +
>>> + regval = FIELD_PREP(SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
>>> + SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
>>> +
>>> + usleep_range(10, 20);
>>> +}
>>> +
>>> +static void meson_saradc_start_sample_engine(struct iio_dev *indio_dev)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> +
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>>> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
>>> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
>>> +
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>>> + SAR_ADC_REG0_SAMPLING_START,
>>> + SAR_ADC_REG0_SAMPLING_START);
>>> +}
>>> +
>>> +static void meson_saradc_stop_sample_engine(struct iio_dev *indio_dev)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> +
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>>> + SAR_ADC_REG0_SAMPLING_STOP,
>>> + SAR_ADC_REG0_SAMPLING_STOP);
>>> +
>>> + /* wait until all modules are stopped */
>>> + meson_saradc_wait_busy_clear(indio_dev);
>>> +
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>>> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
>>> +}
>>> +
>>> +static void meson_saradc_lock(struct iio_dev *indio_dev)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + int val;
>>> +
>>> + mutex_lock(&indio_dev->mlock);
>>> +
>>> + /* prevent BL30 from using the SAR ADC while we are using it */
>>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>>> + SAR_ADC_DELAY_KERNEL_BUSY,
>>> + SAR_ADC_DELAY_KERNEL_BUSY);
>>> +
>>> + /* wait until BL30 releases it's lock (so we can use the SAR ADC) */
>>> + do {
>>> + udelay(1);
>>> + regmap_read(priv->regmap, SAR_ADC_DELAY, &val);
>>> + } while (val & SAR_ADC_DELAY_BL30_BUSY);
>>> +}
>>> +
>>> +static void meson_saradc_unlock(struct iio_dev *indio_dev)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> +
>>> + /* allow BL30 to use the SAR ADC again */
>>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>>> + SAR_ADC_DELAY_KERNEL_BUSY, 0);
>>> +
>>> + mutex_unlock(&indio_dev->mlock);
>>> +}
>>> +
>>> +static int meson_saradc_get_sample(struct iio_dev *indio_dev,
>>> + const struct iio_chan_spec *chan,
>>> + enum meson_saradc_avg_mode avg_mode,
>>> + enum meson_saradc_num_samples avg_samples,
>>> + int *val)
>>> +{
>>> + int ret, tmp;
>>> +
>>> + meson_saradc_lock(indio_dev);
>>> +
>>> + /* clear old values from the FIFO buffer, ignoring errors */
>>> + meson_saradc_read_raw_sample(indio_dev, chan, &tmp);
>>> +
>>> + meson_saradc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
>>> +
>>> + meson_saradc_enable_channel(indio_dev, chan);
>>> +
>>> + meson_saradc_start_sample_engine(indio_dev);
>>> + ret = meson_saradc_read_raw_sample(indio_dev, chan, val);
>>> + meson_saradc_stop_sample_engine(indio_dev);
>>> +
>>> + meson_saradc_unlock(indio_dev);
>>> +
>>> + if (ret) {
>>> + dev_warn(&indio_dev->dev,
>>> + "failed to read sample for channel %d: %d\n",
>>> + chan->channel, ret);
>>> + return ret;
>>> + }
>>> +
>>> + return IIO_VAL_INT;
>>> +}
>>> +
>>> +static int meson_saradc_iio_info_read_raw(struct iio_dev *indio_dev,
>>> + const struct iio_chan_spec *chan,
>>> + int *val, int *val2, long mask)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + int ret;
>>> +
>>> + switch (mask) {
>>> + case IIO_CHAN_INFO_RAW:
>>> + return meson_saradc_get_sample(indio_dev, chan, NO_AVERAGING,
>>> + ONE_SAMPLE, val);
>>> + break;
>>> +
>>> + case IIO_CHAN_INFO_AVERAGE_RAW:
>>> + return meson_saradc_get_sample(indio_dev, chan, MEAN_AVERAGING,
>>> + EIGHT_SAMPLES, val);
>>> + break;
>>> +
>>> + case IIO_CHAN_INFO_SCALE:
>>> + ret = regulator_get_voltage(priv->vref);
>>> + if (ret < 0) {
>>> + dev_err(&indio_dev->dev,
>>> + "failed to get vref voltage: %d\n", ret);
>>> + return ret;
>>> + }
>>> +
>>> + *val = ret / 1000;
>>> + *val2 = priv->resolution;
>>> + return IIO_VAL_FRACTIONAL_LOG2;
>>> +
>>> + default:
>>> + return -EINVAL;
>>> + }
>>> +}
>>> +
>>> +static int meson_saradc_clk_init(struct iio_dev *indio_dev, void __iomem *base)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + struct clk_init_data init;
>>> + char clk_name[32];
>>> + const char *clk_parents[1];
>>> +
>>> + snprintf(clk_name, sizeof(clk_name), "%s#adc_div",
>>> + of_node_full_name(indio_dev->dev.of_node));
>>> + init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
>>> + init.flags = 0;
>>> + init.ops = &clk_divider_ops;
>>> + clk_parents[0] = __clk_get_name(priv->clkin);
>>> + init.parent_names = clk_parents;
>>> + init.num_parents = 1;
>>> +
>>> + priv->clk_div.reg = base + SAR_ADC_REG3;
>>> + priv->clk_div.shift = SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
>>> + priv->clk_div.width = SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
>>> + priv->clk_div.hw.init = &init;
>>> + priv->clk_div.flags = 0;
>>> +
>>> + priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
>>> + &priv->clk_div.hw);
>>> + if (WARN_ON(IS_ERR(priv->adc_div_clk)))
>>> + return PTR_ERR(priv->adc_div_clk);
>>> +
>>> + snprintf(clk_name, sizeof(clk_name), "%s#adc_en",
>>> + of_node_full_name(indio_dev->dev.of_node));
>>> + init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
>>> + init.flags = CLK_SET_RATE_PARENT;
>>> + init.ops = &clk_gate_ops;
>>> + clk_parents[0] = __clk_get_name(priv->adc_div_clk);
>>> + init.parent_names = clk_parents;
>>> + init.num_parents = 1;
>>> +
>>> + priv->clk_gate.reg = base + SAR_ADC_REG3;
>>> + priv->clk_gate.bit_idx = fls(SAR_ADC_REG3_CLK_EN);
>>> + priv->clk_gate.hw.init = &init;
>>> +
>>> + priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
>>> + if (WARN_ON(IS_ERR(priv->adc_clk)))
>>> + return PTR_ERR(priv->adc_clk);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int meson_saradc_init(struct iio_dev *indio_dev)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + int regval, ret;
>>> +
>>> + /* make sure we start at CH7 input */
>> why? Seems like a little more detail would be good here ;)
> I'll change this to "make sure we start at CH7 input since the other
> muxes are only used for internal calibration." in v2
>
>>> + meson_saradc_set_channel7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
>>> +
>>> + regmap_read(priv->regmap, SAR_ADC_REG3, ®val);
>>> + if (regval & SAR_ADC_REG3_BL30_INITIALIZED) {
>>> + dev_info(&indio_dev->dev, "already initialized by BL30\n");
>>> + return 0;
>>> + }
>>> +
>>> + dev_info(&indio_dev->dev, "initializing SAR ADC\n");
>> I'd argue this provides no useful info so should be dropped.
>> Useful for debugging no doubt, but just noise going forward.
> do you want me to remove them or should I turn them into dev_dbg() (so
> they can be enabled for debugging purposes)?
Drop it entirely.
>
>>> +
>>> + meson_saradc_stop_sample_engine(indio_dev);
>>> +
>>> + /* update the channel 6 MUX to select the temperature sensor */
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>>> + SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
>>> + SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
>>> +
>>> + /* disable all channels by default */
>>> + regmap_write(priv->regmap, SAR_ADC_CHAN_LIST, 0x0);
>>> +
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
>>> + SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
>>> + SAR_ADC_REG3_CNTL_USE_SC_DLY,
>>> + SAR_ADC_REG3_CNTL_USE_SC_DLY);
>>> +
>>> + /* delay between two samples = (10+1) * 1uS */
>>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>>> + SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
>>> + FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK, 10));
>>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>>> + SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
>>> + FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 0));
>>> +
>>> + /* delay between two samples = (10+1) * 1uS */
>>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>>> + SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
>>> + FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 10));
>>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>>> + SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
>>> + FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 1));
>>> +
>> Cool. I hadn't come across FIELD_PREP before. Neater and tidier than having
>> a shift and a mask for at least some usecases.
> I think these were introduced with v4.9. I like them because I tend
> use GENMASK() incorrectly and with those macros I get an error at
> compile-time (without having to debug my code at all)
>
>>> + ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
>>> + if (ret) {
>>> + dev_err(&indio_dev->dev,
>>> + "failed to set adc parent to clkin\n");
>>> + return ret;
>>> + }
>>> +
>>> + ret = clk_set_rate(priv->adc_clk, 1200000);
>>> + if (ret) {
>>> + dev_err(&indio_dev->dev, "failed to set adc clock rate\n");
>>> + return ret;
>>> + }
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int meson_saradc_hw_enable(struct iio_dev *indio_dev)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + int ret;
>>> +
>>> + meson_saradc_lock(indio_dev);
>>> +
>>> + ret = regulator_enable(priv->vref);
>>> + if (ret < 0) {
>>> + dev_err(&indio_dev->dev, "failed to enable vref regulator\n");
>>> + goto err_vref;
>>> + }
>>> +
>>> + ret = clk_prepare_enable(priv->core_clk);
>>> + if (ret) {
>>> + dev_err(&indio_dev->dev, "failed to enable core clk\n");
>>> + goto err_core_clk;
>>> + }
>>> +
>>> + ret = clk_prepare_enable(priv->sana_clk);
>>> + if (ret) {
>>> + dev_err(&indio_dev->dev, "failed to enable sana clk\n");
>>> + goto err_sana_clk;
>>> + }
>>> +
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG11,
>>> + SAR_ADC_REG11_BANDGAP_EN, SAR_ADC_REG11_BANDGAP_EN);
>> Is this controlling an offset for a bandgap or some actual electronics?
>> Not sure if it should be disabled on error and the datasheets I've found are
>> far from great! You disable it in the disable, so I'd expect it to be
>> unwound on error in here too.
> actually the bandgap is not documented at all :(
>
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN,
>>> + SAR_ADC_REG3_ADC_EN);
>> The fact you turn this of in the disable suggests to me that on error
>> you should be doing it in here too.
> I will disable this along with SAR_ADC_REG11_BANDGAP_EN in the
> err_adc_clk label, thanks for spotting this.
>
>>> +
>>> + udelay(5);
>>> +
>>> + ret = clk_prepare_enable(priv->adc_clk);
>>> + if (ret) {
>>> + dev_err(&indio_dev->dev, "failed to enable adc_en clk\n");
>>> + goto err_adc_clk;
>>> + }
>>> +
>>> + meson_saradc_unlock(indio_dev);
>>> +
>>> + return 0;
>>> +
>>> +err_adc_clk:
>>> + clk_disable_unprepare(priv->sana_clk);
>>> +err_sana_clk:
>>> + clk_disable_unprepare(priv->core_clk);
>>> +err_core_clk:
>>> + regulator_disable(priv->vref);
>>> +err_vref:
>>> + meson_saradc_unlock(indio_dev);
>>> + return ret;
>>> +}
>>> +
>>> +static void meson_saradc_hw_disable(struct iio_dev *indio_dev)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> +
>>> + meson_saradc_lock(indio_dev);
>>> +
>>> + clk_disable_unprepare(priv->adc_clk);
>>> +
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN, 0);
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG11,
>>> + SAR_ADC_REG11_BANDGAP_EN, 0);
>>> +
>>> + clk_disable_unprepare(priv->sana_clk);
>>> + clk_disable_unprepare(priv->core_clk);
>>> +
>>> + regulator_disable(priv->vref);
>>> +
>>> + meson_saradc_unlock(indio_dev);
>>> +}
>>> +
>>> +static const struct iio_info meson_saradc_iio_info = {
>>> + .read_raw = meson_saradc_iio_info_read_raw,
>>> + .driver_module = THIS_MODULE,
>>> +};
>>> +
>>> +static const struct of_device_id meson_saradc_of_match[] = {
>>> + {
>>> + .compatible = "amlogic,meson-gxbb-saradc",
>>> + .data = (void *)10,
>> Might have been worth having a structure array indexed from an enum.
>> For now it is overkill, but seems likely there are a few other differences
>> that aren't supported yet?
> what do you mean with "structure array indexed from an enum"? I can
> introduce some match-specific struct if you want (just like it's done
> in rockchip_saradc.c with "struct rockchip_saradc_data").
That works, or data can be an enum indexing an array of similar structures.
It doesn't really matter.
>
>>> + }, {
>>> + .compatible = "amlogic,meson-gxl-saradc",
>>> + .data = (void *)12,
>>> + },
>>> + {},
>>> +};
>>> +MODULE_DEVICE_TABLE(of, meson_saradc_of_match);
>>> +
>>> +static int meson_saradc_probe(struct platform_device *pdev)
>>> +{
>>> + struct meson_saradc_priv *priv;
>>> + struct iio_dev *indio_dev;
>>> + struct resource *res;
>>> + void __iomem *base;
>>> + const struct of_device_id *match;
>>> + int ret;
>>> +
>>> + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
>>> + if (!indio_dev) {
>>> + dev_err(&pdev->dev, "failed allocating iio device\n");
>>> + return -ENOMEM;
>>> + }
>>> +
>>> + priv = iio_priv(indio_dev);
>>> +
>>> + match = of_match_device(meson_saradc_of_match, &pdev->dev);
>>> + priv->resolution = (unsigned long)match->data;
>>> +
>>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> + base = devm_ioremap_resource(&pdev->dev, res);
>>> + if (IS_ERR(base))
>>> + return PTR_ERR(base);
>>> +
>>> + priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
>>> + &meson_saradc_regmap_config);
>>> + if (IS_ERR(priv->regmap))
>>> + return PTR_ERR(priv->regmap);
>>> +
>>> + init_completion(&priv->completion);
>>> +
>>> + priv->clkin = devm_clk_get(&pdev->dev, "clkin");
>>> + if (IS_ERR(priv->clkin)) {
>>> + dev_err(&pdev->dev, "failed to get clkin\n");
>>> + return PTR_ERR(priv->clkin);
>>> + }
>>> +
>>> + priv->core_clk = devm_clk_get(&pdev->dev, "core");
>>> + if (IS_ERR(priv->core_clk)) {
>>> + dev_err(&pdev->dev, "failed to get core clk\n");
>>> + return PTR_ERR(priv->core_clk);
>>> + }
>>> +
>>> + priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
>> Oh for a devm_clk_get_optional to handle this boiler plate neatly.
>> It's been suggested before, but nothing seems to have come of it.
> I guess quite a few drivers would benefit from that. maybe we should
> take this to the linux-clk list again?
Perhaps. I guess this has been proposed before but gone nowhere.
I haven't digged into why though.
>
>> Some array clk get functions might also clean this up a touch.
> yes, unfortunately in this case it's not that easy as it would have to
> allow a mix of mandatory and optional clocks. Additionally I cannot
> bulk-enable them unconditionally since some of these are simple gates,
> others need to be reparented and for some the rate has to be set.
>
>>> + if (IS_ERR(priv->sana_clk)) {
>>> + if (PTR_ERR(priv->sana_clk) == -ENOENT) {
>>> + priv->sana_clk = NULL;
>>> + } else {
>>> + dev_err(&pdev->dev, "failed to get sana clk\n");
>>> + return PTR_ERR(priv->sana_clk);
>>> + }
>>> + }
>>> +
>>> + priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
>>> + if (IS_ERR(priv->adc_clk)) {
>>> + if (PTR_ERR(priv->adc_clk) == -ENOENT) {
>>> + priv->adc_clk = NULL;
>>> + } else {
>>> + dev_err(&pdev->dev, "failed to get adc clk\n");
>>> + return PTR_ERR(priv->adc_clk);
>>> + }
>>> + }
>>> +
>>> + priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
>>> + if (IS_ERR(priv->adc_sel_clk)) {
>>> + if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
>>> + priv->adc_sel_clk = NULL;
>>> + } else {
>>> + dev_err(&pdev->dev, "failed to get adc_sel clk\n");
>>> + return PTR_ERR(priv->adc_sel_clk);
>>> + }
>>> + }
>>> +
>>> + /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
>>> + if (!priv->adc_clk) {
>>> + ret = meson_saradc_clk_init(indio_dev, base);
>>> + if (ret)
>>> + return ret;
>>> + }
>>> +
>>> + priv->vref = devm_regulator_get(&pdev->dev, "vref");
>>> + if (IS_ERR(priv->vref)) {
>>> + dev_err(&pdev->dev, "failed to get vref regulator\n");
>>> + return PTR_ERR(priv->vref);
>>> + }
>>> +
>>> + ret = meson_saradc_init(indio_dev);
>>> + if (ret)
>>> + goto err;
>>> +
>>> + ret = meson_saradc_hw_enable(indio_dev);
>>> + if (ret)
>>> + goto err;
>>> +
>>> + platform_set_drvdata(pdev, indio_dev);
>>> +
>>> + indio_dev->name = dev_name(&pdev->dev);
>>> + indio_dev->dev.parent = &pdev->dev;
>>> + indio_dev->dev.of_node = pdev->dev.of_node;
>>> + indio_dev->modes = INDIO_DIRECT_MODE;
>>> + indio_dev->info = &meson_saradc_iio_info;
>>> +
>>> + indio_dev->channels = meson_saradc_iio_channels;
>>> + indio_dev->num_channels = SAR_ADC_NUM_CHANNELS;
>>> +
>>> + ret = iio_device_register(indio_dev);
>>> + if (ret)
>>> + goto err_hw;
>>> +
>>> + return 0;
>>> +
>>> +err_hw:
>>> + meson_saradc_hw_disable(indio_dev);
>>> +err:
>>> + return ret;
>>> +}
>>> +
>>> +static int meson_saradc_remove(struct platform_device *pdev)
>>> +{
>>> + struct iio_dev *indio_dev = platform_get_drvdata(pdev);
>>> +
>>> + meson_saradc_hw_disable(indio_dev);
>>> + iio_device_unregister(indio_dev);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +#ifdef CONFIG_PM_SLEEP
>>> +static int meson_saradc_suspend(struct device *dev)
>>> +{
>>> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
>>> +
>>> + meson_saradc_hw_disable(indio_dev);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int meson_saradc_resume(struct device *dev)
>>> +{
>>> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
>>> +
>>> + return meson_saradc_hw_enable(indio_dev);
>>> +}
>>> +#endif /* CONFIG_PM_SLEEP */
>>> +
>>> +static SIMPLE_DEV_PM_OPS(meson_saradc_pm_ops,
>>> + meson_saradc_suspend, meson_saradc_resume);
>>> +
>>> +static struct platform_driver meson_saradc_driver = {
>>> + .probe = meson_saradc_probe,
>>> + .remove = meson_saradc_remove,
>>> + .driver = {
>>> + .name = "meson-saradc",
>>> + .of_match_table = meson_saradc_of_match,
>>> + .pm = &meson_saradc_pm_ops,
>>> + },
>>> +};
>>> +
>>> +module_platform_driver(meson_saradc_driver);
>>> +
>>> +MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
>>> +MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
>>> +MODULE_LICENSE("GPL v2");
>>>
>>
>
>
> Regards,
> Martin
>
> [0] http://lists.infradead.org/pipermail/linux-amlogic/2016-August/000986.html
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
@ 2017-01-15 13:08 ` Jonathan Cameron
0 siblings, 0 replies; 110+ messages in thread
From: Jonathan Cameron @ 2017-01-15 13:08 UTC (permalink / raw)
To: linux-arm-kernel
On 14/01/17 17:44, Martin Blumenstingl wrote:
> Hi Jonathan,
>
> thank you for the review!
> (further comments from me inline)
> I think I'll send an updated version on Monday.
>
> On Sat, Jan 14, 2017 at 3:46 PM, Jonathan Cameron <jic23@kernel.org> wrote:
>> On 11/01/17 17:43, Martin Blumenstingl wrote:
>>> This adds support for the SAR (Successive Approximation Register) ADC
>>> on the Amlogic Meson SoCs.
>>>
>>> The code is based on the public S805 (Meson8b) and S905 (GXBB)
>>> datasheets, as well as by reading (various versions of) the vendor
>>> driver and by inspecting the registers on the vendor kernels of my
>>> testing-hardware.
>>>
>>> Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
>>> 10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
>>> The code was written to support older SoCs (Meson8 and Meson8b) as well,
>>> but due to lack of actual testing-hardware no of_device_id was added for
>>> these.
>>>
>>> Two "features" from the vendor driver are currently missing:
>>> - the vendor driver uses channel #7 for calibration (this improves the
>>> accuracy of the results - in my tests the results were less than 3%
>>> off without calibration compared to the vendor driver). Adding support
>>> for this should be easy, but is not required for most applications.
>>> - channel #6 is connected to the SoCs internal temperature sensor.
>>> Adding support for this is probably not so easy since (based on the
>>> u-boot sources) most SoC versions are using different registers and
>>> algorithms for the conversion from "ADC value" to temperature.
>>>
>>> Supported by the hardware but currently not supported by the driver:
>>> - reading multiple channels at the same time (the hardware has a FIFO
>>> buffer which stores multiple results)
>>> - continuous sampling (this would require a way to enable this
>>> individually because otherwise the ADC would be drawing power
>>> constantly)
>>> - interrupt support (similar to the vendor driver this new driver is
>>> polling the results. It is unclear if the IRQ-mode is supported on
>>> older (Meson6 or Meson8) hardware as well or if there are any errata)
>>>
>> Russell Cc'd for a quick question on the clk api.
> a quick side-note the clk API: my driver is a clock consumer and
> provider at the same time. This seems to be a recurring pattern in
> Amlogic hardware designs (as the MMC and DWMAC glue drivers are doing
> this also), see [0]
>
>> Ideally include a source for datasheets if available. Saves time googling and
>> perhaps getting the wrong thing!
> OK, will do this in v2
>
>> A few other minor comments inline. Pretty good V1.
> thanks :-)
>
>> Jonathan
>>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>> ---
>>> drivers/iio/adc/Kconfig | 12 +
>>> drivers/iio/adc/Makefile | 1 +
>>> drivers/iio/adc/meson_saradc.c | 860 +++++++++++++++++++++++++++++++++++++++++
>>> 3 files changed, 873 insertions(+)
>>> create mode 100644 drivers/iio/adc/meson_saradc.c
>>>
>>> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
>>> index 9c8b558ba19e..86059b9b91bf 100644
>>> --- a/drivers/iio/adc/Kconfig
>>> +++ b/drivers/iio/adc/Kconfig
>>> @@ -371,6 +371,18 @@ config MEN_Z188_ADC
>>> This driver can also be built as a module. If so, the module will be
>>> called men_z188_adc.
>>>
>>> +config MESON_SARADC
>>> + tristate "Amlogic Meson SAR ADC driver"
>>> + default ARCH_MESON
>>> + depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
>>> + select REGMAP_MMIO
>>> + help
>>> + Say yes here to build support for the SAR ADC found in Amlogic Meson
>>> + SoCs.
>>> +
>>> + To compile this driver as a module, choose M here: the
>>> + module will be called meson_saradc.
>>> +
>>> config MXS_LRADC
>>> tristate "Freescale i.MX23/i.MX28 LRADC"
>>> depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
>>> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
>>> index d36c4be8d1fc..de05b9e75f8f 100644
>>> --- a/drivers/iio/adc/Makefile
>>> +++ b/drivers/iio/adc/Makefile
>>> @@ -36,6 +36,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
>>> obj-$(CONFIG_MCP3422) += mcp3422.o
>>> obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
>>> obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
>>> +obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
>>> obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
>>> obj-$(CONFIG_NAU7802) += nau7802.o
>>> obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
>>> diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
>>> new file mode 100644
>>> index 000000000000..06e8ac620385
>>> --- /dev/null
>>> +++ b/drivers/iio/adc/meson_saradc.c
>>> @@ -0,0 +1,860 @@
>>> +/*
>>> + * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
>>> + *
>>> + * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License version 2 as
>>> + * published by the Free Software Foundation.
>>> + *
>>> + * You should have received a copy of the GNU General Public License
>>> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
>>> + */
>>> +
>>> +#include <linux/bitfield.h>
>>> +#include <linux/clk-provider.h>
>>> +#include <linux/module.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/interrupt.h>
>>> +#include <linux/io.h>
>>> +#include <linux/iio/iio.h>
>>> +#include <linux/of.h>
>>> +#include <linux/of_device.h>
>>> +#include <linux/clk.h>
>>> +#include <linux/completion.h>
>>> +#include <linux/delay.h>
>>> +#include <linux/reset.h>
>>> +#include <linux/regmap.h>
>>> +#include <linux/regulator/consumer.h>
>>> +
>>> +#define SAR_ADC_REG0 0x00
>>> + #define SAR_ADC_REG0_PANEL_DETECT BIT(31)
>>> + #define SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
>>> + #define SAR_ADC_REG0_DELTA_BUSY BIT(30)
>>> + #define SAR_ADC_REG0_AVG_BUSY BIT(29)
>>> + #define SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
>>> + #define SAR_ADC_REG0_FIFO_FULL BIT(27)
>>> + #define SAR_ADC_REG0_FIFO_EMPTY BIT(26)
>>> + #define SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
>>> + #define SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
>>> + #define SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
>>> + #define SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
>>> + #define SAR_ADC_REG0_SAMPLING_STOP BIT(14)
>>> + #define SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
>>> + #define SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
>>> + #define SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
>>> + #define SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
>>> + #define SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
>>> + #define SAR_ADC_REG0_SAMPLING_START BIT(2)
>>> + #define SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
>>> + #define SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
>>> +
>>> +#define SAR_ADC_CHAN_LIST 0x04
>>> + #define SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
>>> + #define SAR_ADC_CHAN_CHAN_ENTRY_MASK(_chan) \
>>> + (GENMASK(2, 0) << (_chan * 3))
>>> +
>>> +#define SAR_ADC_AVG_CNTL 0x08
>>> + #define SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
>>> + (16 + (_chan * 2))
>>> + #define SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
>>> + (GENMASK(17, 16) << (_chan * 2))
>>> + #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
>>> + (0 + (_chan * 2))
>>> + #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
>>> + (GENMASK(1, 0) << (_chan * 2))
>>> +
>>> +#define SAR_ADC_REG3 0x0c
>>> + #define SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
>>> + #define SAR_ADC_REG3_CLK_EN BIT(30)
>>> + #define SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
>>> + #define SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
>>> + #define SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
>>> + #define SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
>>> + #define SAR_ADC_REG3_DETECT_EN BIT(22)
>>> + #define SAR_ADC_REG3_ADC_EN BIT(21)
>>> + #define SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
>>> + #define SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
>>> + #define SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
>>> + #define SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
>>> + #define SAR_ADC_REG3_ADC_CLK_DIV_MASK GENMASK(15, 10)
>>> + #define SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
>>> + #define SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
>>> +
>>> +#define SAR_ADC_DELAY 0x10
>>> + #define SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
>>> + #define SAR_ADC_DELAY_BL30_BUSY BIT(15)
>>> + #define SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
>>> + #define SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
>>> + #define SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
>>> + #define SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
>>> +
>>> +#define SAR_ADC_LAST_RD 0x14
>>> + #define SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
>>> + #define SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
>>> +
>>> +#define SAR_ADC_FIFO_RD 0x18
>>> + #define SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
>>> + #define SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
>>> +
>>> +#define SAR_ADC_AUX_SW 0x1c
>>> + #define SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
>>> + (GENMASK(10, 8) << ((_chan - 2) * 2))
>>> + #define SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
>>> + #define SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
>>> + #define SAR_ADC_AUX_SW_MODE_SEL BIT(4)
>>> + #define SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
>>> + #define SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
>>> + #define SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
>>> + #define SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
>>> +
>>> +#define SAR_ADC_CHAN_10_SW 0x20
>>> + #define SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
>>> +
>>> +#define SAR_ADC_DETECT_IDLE_SW 0x24
>>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
>>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK GENMASK(25, 23)
>>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_P_MUX BIT(22)
>>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_N_MUX BIT(21)
>>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
>>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YP_DRIVE_SW BIT(19)
>>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XP_DRIVE_SW BIT(18)
>>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YM_DRIVE_SW BIT(17)
>>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XM_DRIVE_SW BIT(16)
>>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK GENMASK(9, 7)
>>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_P_MUX BIT(6)
>>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_N_MUX BIT(5)
>>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
>>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YP_DRIVE_SW BIT(3)
>>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XP_DRIVE_SW BIT(2)
>>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YM_DRIVE_SW BIT(1)
>>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XM_DRIVE_SW BIT(0)
>>> +
>>> +#define SAR_ADC_DELTA_10 0x28
>>> + #define SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
>>> + #define SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
>>> + #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_SHIFT 16
>>> + #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
>>> + #define SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
>>> + #define SAR_ADC_DELTA_10_TS_C_SHIFT 11
>>> + #define SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
>>> + #define SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
>>> + #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_SHIFT 0
>>> + #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
>>> +
>>> +/* NOTE: registers from here are undocumented (the vendor Linux kernel driver
>>> + * and u-boot source served as reference). These only seem to be relevant on
>>> + * GXBB and newer.
>>> + */
>>> +#define SAR_ADC_REG11 0x2c
>>> + #define SAR_ADC_REG11_BANDGAP_EN BIT(13)
>>> +
>>> +#define SAR_ADC_REG13 0x34
>>> + #define SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
>>> +
>>> +#define SAR_ADC_MAX_FIFO_SIZE 32
>>> +#define SAR_ADC_NUM_CHANNELS ARRAY_SIZE(meson_saradc_iio_channels)
>>> +#define SAR_ADC_VALUE_MASK(_priv) (BIT(_priv->resolution) - 1)
>>> +
>>> +#define MESON_SAR_ADC_CHAN(_chan, _type) { \
>>> + .type = _type, \
>>> + .indexed = true, \
>>> + .channel = _chan, \
>>> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
>>> + BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
>>> + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
>>> + .datasheet_name = "SAR_ADC_CH"#_chan, \
>>> +}
>>> +
>>> +/* TODO: the hardware supports IIO_TEMP for channel 6 as well which is
>> Multline comment syntax.
> I got this wrong in 2 other places as well. will be fixed in v2, thanks!
>
>>> + * currently not supported by this driver.
>>> + */
>>> +static const struct iio_chan_spec meson_saradc_iio_channels[] = {
>>> + MESON_SAR_ADC_CHAN(0, IIO_VOLTAGE),
>>> + MESON_SAR_ADC_CHAN(1, IIO_VOLTAGE),
>>> + MESON_SAR_ADC_CHAN(2, IIO_VOLTAGE),
>>> + MESON_SAR_ADC_CHAN(3, IIO_VOLTAGE),
>>> + MESON_SAR_ADC_CHAN(4, IIO_VOLTAGE),
>>> + MESON_SAR_ADC_CHAN(5, IIO_VOLTAGE),
>>> + MESON_SAR_ADC_CHAN(6, IIO_VOLTAGE),
>>> + MESON_SAR_ADC_CHAN(7, IIO_VOLTAGE),
>>> + IIO_CHAN_SOFT_TIMESTAMP(8),
>>> +};
>>> +
>>> +enum meson_saradc_avg_mode {
>>> + NO_AVERAGING = 0x0,
>>> + MEAN_AVERAGING = 0x1,
>>> + MEDIAN_AVERAGING = 0x2,
>>> +};
>>> +
>>> +enum meson_saradc_num_samples {
>>> + ONE_SAMPLE = 0x0,
>>> + TWO_SAMPLES = 0x1,
>>> + FOUR_SAMPLES = 0x2,
>>> + EIGHT_SAMPLES = 0x3,
>>> +};
>>> +
>>> +enum meson_saradc_chan7_mux_sel {
>>> + CHAN7_MUX_VSS = 0x0,
>>> + CHAN7_MUX_VDD_DIV4 = 0x1,
>>> + CHAN7_MUX_VDD_DIV2 = 0x2,
>>> + CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
>>> + CHAN7_MUX_VDD = 0x4,
>>> + CHAN7_MUX_CH7_INPUT = 0x7,
>>> +};
>>> +
>>> +struct meson_saradc_priv {
>>> + struct regmap *regmap;
>>> + struct clk *clkin;
>>> + struct clk *core_clk;
>>> + struct clk *sana_clk;
>>> + struct clk *adc_sel_clk;
>>> + struct clk *adc_clk;
>>> + struct clk_gate clk_gate;
>>> + struct clk *adc_div_clk;
>>> + struct clk_divider clk_div;
>>> + struct regulator *vref;
>>> + struct completion completion;
>>> + u8 resolution;
>>> +};
>>> +
>>> +static const struct regmap_config meson_saradc_regmap_config = {
>>> + .reg_bits = 8,
>>> + .val_bits = 32,
>>> + .reg_stride = 4,
>>> + .max_register = SAR_ADC_REG13,
>>> +};
>>> +
>>> +static unsigned int meson_saradc_get_fifo_count(struct iio_dev *indio_dev)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + u32 regval;
>>> +
>>> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
>>> +
>>> + return FIELD_GET(SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
>>> +}
>>> +
>>> +static int meson_saradc_wait_busy_clear(struct iio_dev *indio_dev)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + int regval, timeout = 10000;
>>> +
>>> + do {
>>> + udelay(1);
>>> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
>>> + } while (FIELD_GET(SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
>>> +
>>> + if (timeout < 0)
>>> + return -ETIMEDOUT;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int meson_saradc_read_raw_sample(struct iio_dev *indio_dev,
>>> + const struct iio_chan_spec *chan,
>>> + int *val)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0;
>>> +
>>> + ret = meson_saradc_wait_busy_clear(indio_dev);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
>>> +
>>> + while (meson_saradc_get_fifo_count(indio_dev) > 0 &&
>>> + count < SAR_ADC_MAX_FIFO_SIZE) {
>>> + regmap_read(priv->regmap, SAR_ADC_FIFO_RD, ®val);
>>> +
>>> + fifo_chan = FIELD_GET(SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
>>> + if (fifo_chan == chan->channel) {
>>> + fifo_val = FIELD_GET(SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK,
>>> + regval) & SAR_ADC_VALUE_MASK(priv);
>>> + sum += fifo_val;
>>> + count++;
>>> + }
>>> + }
>>> +
>>> + if (!count)
>>> + return -ENOENT;
>>> +
>>> + *val = sum / count;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static void meson_saradc_set_averaging(struct iio_dev *indio_dev,
>>> + const struct iio_chan_spec *chan,
>>> + enum meson_saradc_avg_mode mode,
>>> + enum meson_saradc_num_samples samples)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + u32 val;
>>> +
>>> + val = samples << SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(chan->channel);
>>> + regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
>>> + SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(chan->channel),
>>> + val);
>>> +
>>> + val = mode << SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(chan->channel);
>>> + regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
>>> + SAR_ADC_AVG_CNTL_AVG_MODE_MASK(chan->channel), val);
>>> +}
>>> +
>>> +static void meson_saradc_enable_channel(struct iio_dev *indio_dev,
>>> + const struct iio_chan_spec *chan)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + u32 regval;
>>> +
>>> + /* the SAR ADC engine allows sampling multiple channels at the same
>>> + * time. to keep it simple we're only working with one *internal*
>>> + * channel, which starts counting at index 0 (which means: count = 1).
>>> + */
>>> + regval = FIELD_PREP(SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
>>> + regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
>>> + SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
>>> +
>>> + /* map channel index 0 to the channel which we want to read */
>>> + regval = FIELD_PREP(SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), chan->channel);
>>> + regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
>>> + SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), regval);
>>> +
>>> + regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
>>> + chan->channel);
>>> + regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
>>> + SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
>>> + regval);
>>> +
>>> + regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
>>> + chan->channel);
>>> + regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
>>> + SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
>>> + regval);
>>> +
>>> + if (chan->channel == 6)
>>> + regmap_update_bits(priv->regmap, SAR_ADC_DELTA_10,
>>> + SAR_ADC_DELTA_10_TEMP_SEL, 0);
>>> +}
>>> +
>>> +static void meson_saradc_set_channel7_mux(struct iio_dev *indio_dev,
>>> + enum meson_saradc_chan7_mux_sel sel)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + u32 regval;
>>> +
>>> + regval = FIELD_PREP(SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
>>> + SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
>>> +
>>> + usleep_range(10, 20);
>>> +}
>>> +
>>> +static void meson_saradc_start_sample_engine(struct iio_dev *indio_dev)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> +
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>>> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
>>> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
>>> +
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>>> + SAR_ADC_REG0_SAMPLING_START,
>>> + SAR_ADC_REG0_SAMPLING_START);
>>> +}
>>> +
>>> +static void meson_saradc_stop_sample_engine(struct iio_dev *indio_dev)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> +
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>>> + SAR_ADC_REG0_SAMPLING_STOP,
>>> + SAR_ADC_REG0_SAMPLING_STOP);
>>> +
>>> + /* wait until all modules are stopped */
>>> + meson_saradc_wait_busy_clear(indio_dev);
>>> +
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>>> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
>>> +}
>>> +
>>> +static void meson_saradc_lock(struct iio_dev *indio_dev)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + int val;
>>> +
>>> + mutex_lock(&indio_dev->mlock);
>>> +
>>> + /* prevent BL30 from using the SAR ADC while we are using it */
>>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>>> + SAR_ADC_DELAY_KERNEL_BUSY,
>>> + SAR_ADC_DELAY_KERNEL_BUSY);
>>> +
>>> + /* wait until BL30 releases it's lock (so we can use the SAR ADC) */
>>> + do {
>>> + udelay(1);
>>> + regmap_read(priv->regmap, SAR_ADC_DELAY, &val);
>>> + } while (val & SAR_ADC_DELAY_BL30_BUSY);
>>> +}
>>> +
>>> +static void meson_saradc_unlock(struct iio_dev *indio_dev)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> +
>>> + /* allow BL30 to use the SAR ADC again */
>>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>>> + SAR_ADC_DELAY_KERNEL_BUSY, 0);
>>> +
>>> + mutex_unlock(&indio_dev->mlock);
>>> +}
>>> +
>>> +static int meson_saradc_get_sample(struct iio_dev *indio_dev,
>>> + const struct iio_chan_spec *chan,
>>> + enum meson_saradc_avg_mode avg_mode,
>>> + enum meson_saradc_num_samples avg_samples,
>>> + int *val)
>>> +{
>>> + int ret, tmp;
>>> +
>>> + meson_saradc_lock(indio_dev);
>>> +
>>> + /* clear old values from the FIFO buffer, ignoring errors */
>>> + meson_saradc_read_raw_sample(indio_dev, chan, &tmp);
>>> +
>>> + meson_saradc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
>>> +
>>> + meson_saradc_enable_channel(indio_dev, chan);
>>> +
>>> + meson_saradc_start_sample_engine(indio_dev);
>>> + ret = meson_saradc_read_raw_sample(indio_dev, chan, val);
>>> + meson_saradc_stop_sample_engine(indio_dev);
>>> +
>>> + meson_saradc_unlock(indio_dev);
>>> +
>>> + if (ret) {
>>> + dev_warn(&indio_dev->dev,
>>> + "failed to read sample for channel %d: %d\n",
>>> + chan->channel, ret);
>>> + return ret;
>>> + }
>>> +
>>> + return IIO_VAL_INT;
>>> +}
>>> +
>>> +static int meson_saradc_iio_info_read_raw(struct iio_dev *indio_dev,
>>> + const struct iio_chan_spec *chan,
>>> + int *val, int *val2, long mask)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + int ret;
>>> +
>>> + switch (mask) {
>>> + case IIO_CHAN_INFO_RAW:
>>> + return meson_saradc_get_sample(indio_dev, chan, NO_AVERAGING,
>>> + ONE_SAMPLE, val);
>>> + break;
>>> +
>>> + case IIO_CHAN_INFO_AVERAGE_RAW:
>>> + return meson_saradc_get_sample(indio_dev, chan, MEAN_AVERAGING,
>>> + EIGHT_SAMPLES, val);
>>> + break;
>>> +
>>> + case IIO_CHAN_INFO_SCALE:
>>> + ret = regulator_get_voltage(priv->vref);
>>> + if (ret < 0) {
>>> + dev_err(&indio_dev->dev,
>>> + "failed to get vref voltage: %d\n", ret);
>>> + return ret;
>>> + }
>>> +
>>> + *val = ret / 1000;
>>> + *val2 = priv->resolution;
>>> + return IIO_VAL_FRACTIONAL_LOG2;
>>> +
>>> + default:
>>> + return -EINVAL;
>>> + }
>>> +}
>>> +
>>> +static int meson_saradc_clk_init(struct iio_dev *indio_dev, void __iomem *base)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + struct clk_init_data init;
>>> + char clk_name[32];
>>> + const char *clk_parents[1];
>>> +
>>> + snprintf(clk_name, sizeof(clk_name), "%s#adc_div",
>>> + of_node_full_name(indio_dev->dev.of_node));
>>> + init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
>>> + init.flags = 0;
>>> + init.ops = &clk_divider_ops;
>>> + clk_parents[0] = __clk_get_name(priv->clkin);
>>> + init.parent_names = clk_parents;
>>> + init.num_parents = 1;
>>> +
>>> + priv->clk_div.reg = base + SAR_ADC_REG3;
>>> + priv->clk_div.shift = SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
>>> + priv->clk_div.width = SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
>>> + priv->clk_div.hw.init = &init;
>>> + priv->clk_div.flags = 0;
>>> +
>>> + priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
>>> + &priv->clk_div.hw);
>>> + if (WARN_ON(IS_ERR(priv->adc_div_clk)))
>>> + return PTR_ERR(priv->adc_div_clk);
>>> +
>>> + snprintf(clk_name, sizeof(clk_name), "%s#adc_en",
>>> + of_node_full_name(indio_dev->dev.of_node));
>>> + init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
>>> + init.flags = CLK_SET_RATE_PARENT;
>>> + init.ops = &clk_gate_ops;
>>> + clk_parents[0] = __clk_get_name(priv->adc_div_clk);
>>> + init.parent_names = clk_parents;
>>> + init.num_parents = 1;
>>> +
>>> + priv->clk_gate.reg = base + SAR_ADC_REG3;
>>> + priv->clk_gate.bit_idx = fls(SAR_ADC_REG3_CLK_EN);
>>> + priv->clk_gate.hw.init = &init;
>>> +
>>> + priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
>>> + if (WARN_ON(IS_ERR(priv->adc_clk)))
>>> + return PTR_ERR(priv->adc_clk);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int meson_saradc_init(struct iio_dev *indio_dev)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + int regval, ret;
>>> +
>>> + /* make sure we start at CH7 input */
>> why? Seems like a little more detail would be good here ;)
> I'll change this to "make sure we start at CH7 input since the other
> muxes are only used for internal calibration." in v2
>
>>> + meson_saradc_set_channel7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
>>> +
>>> + regmap_read(priv->regmap, SAR_ADC_REG3, ®val);
>>> + if (regval & SAR_ADC_REG3_BL30_INITIALIZED) {
>>> + dev_info(&indio_dev->dev, "already initialized by BL30\n");
>>> + return 0;
>>> + }
>>> +
>>> + dev_info(&indio_dev->dev, "initializing SAR ADC\n");
>> I'd argue this provides no useful info so should be dropped.
>> Useful for debugging no doubt, but just noise going forward.
> do you want me to remove them or should I turn them into dev_dbg() (so
> they can be enabled for debugging purposes)?
Drop it entirely.
>
>>> +
>>> + meson_saradc_stop_sample_engine(indio_dev);
>>> +
>>> + /* update the channel 6 MUX to select the temperature sensor */
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>>> + SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
>>> + SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
>>> +
>>> + /* disable all channels by default */
>>> + regmap_write(priv->regmap, SAR_ADC_CHAN_LIST, 0x0);
>>> +
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
>>> + SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
>>> + SAR_ADC_REG3_CNTL_USE_SC_DLY,
>>> + SAR_ADC_REG3_CNTL_USE_SC_DLY);
>>> +
>>> + /* delay between two samples = (10+1) * 1uS */
>>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>>> + SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
>>> + FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK, 10));
>>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>>> + SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
>>> + FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 0));
>>> +
>>> + /* delay between two samples = (10+1) * 1uS */
>>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>>> + SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
>>> + FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 10));
>>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>>> + SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
>>> + FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 1));
>>> +
>> Cool. I hadn't come across FIELD_PREP before. Neater and tidier than having
>> a shift and a mask for at least some usecases.
> I think these were introduced with v4.9. I like them because I tend
> use GENMASK() incorrectly and with those macros I get an error at
> compile-time (without having to debug my code at all)
>
>>> + ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
>>> + if (ret) {
>>> + dev_err(&indio_dev->dev,
>>> + "failed to set adc parent to clkin\n");
>>> + return ret;
>>> + }
>>> +
>>> + ret = clk_set_rate(priv->adc_clk, 1200000);
>>> + if (ret) {
>>> + dev_err(&indio_dev->dev, "failed to set adc clock rate\n");
>>> + return ret;
>>> + }
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int meson_saradc_hw_enable(struct iio_dev *indio_dev)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + int ret;
>>> +
>>> + meson_saradc_lock(indio_dev);
>>> +
>>> + ret = regulator_enable(priv->vref);
>>> + if (ret < 0) {
>>> + dev_err(&indio_dev->dev, "failed to enable vref regulator\n");
>>> + goto err_vref;
>>> + }
>>> +
>>> + ret = clk_prepare_enable(priv->core_clk);
>>> + if (ret) {
>>> + dev_err(&indio_dev->dev, "failed to enable core clk\n");
>>> + goto err_core_clk;
>>> + }
>>> +
>>> + ret = clk_prepare_enable(priv->sana_clk);
>>> + if (ret) {
>>> + dev_err(&indio_dev->dev, "failed to enable sana clk\n");
>>> + goto err_sana_clk;
>>> + }
>>> +
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG11,
>>> + SAR_ADC_REG11_BANDGAP_EN, SAR_ADC_REG11_BANDGAP_EN);
>> Is this controlling an offset for a bandgap or some actual electronics?
>> Not sure if it should be disabled on error and the datasheets I've found are
>> far from great! You disable it in the disable, so I'd expect it to be
>> unwound on error in here too.
> actually the bandgap is not documented at all :(
>
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN,
>>> + SAR_ADC_REG3_ADC_EN);
>> The fact you turn this of in the disable suggests to me that on error
>> you should be doing it in here too.
> I will disable this along with SAR_ADC_REG11_BANDGAP_EN in the
> err_adc_clk label, thanks for spotting this.
>
>>> +
>>> + udelay(5);
>>> +
>>> + ret = clk_prepare_enable(priv->adc_clk);
>>> + if (ret) {
>>> + dev_err(&indio_dev->dev, "failed to enable adc_en clk\n");
>>> + goto err_adc_clk;
>>> + }
>>> +
>>> + meson_saradc_unlock(indio_dev);
>>> +
>>> + return 0;
>>> +
>>> +err_adc_clk:
>>> + clk_disable_unprepare(priv->sana_clk);
>>> +err_sana_clk:
>>> + clk_disable_unprepare(priv->core_clk);
>>> +err_core_clk:
>>> + regulator_disable(priv->vref);
>>> +err_vref:
>>> + meson_saradc_unlock(indio_dev);
>>> + return ret;
>>> +}
>>> +
>>> +static void meson_saradc_hw_disable(struct iio_dev *indio_dev)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> +
>>> + meson_saradc_lock(indio_dev);
>>> +
>>> + clk_disable_unprepare(priv->adc_clk);
>>> +
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN, 0);
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG11,
>>> + SAR_ADC_REG11_BANDGAP_EN, 0);
>>> +
>>> + clk_disable_unprepare(priv->sana_clk);
>>> + clk_disable_unprepare(priv->core_clk);
>>> +
>>> + regulator_disable(priv->vref);
>>> +
>>> + meson_saradc_unlock(indio_dev);
>>> +}
>>> +
>>> +static const struct iio_info meson_saradc_iio_info = {
>>> + .read_raw = meson_saradc_iio_info_read_raw,
>>> + .driver_module = THIS_MODULE,
>>> +};
>>> +
>>> +static const struct of_device_id meson_saradc_of_match[] = {
>>> + {
>>> + .compatible = "amlogic,meson-gxbb-saradc",
>>> + .data = (void *)10,
>> Might have been worth having a structure array indexed from an enum.
>> For now it is overkill, but seems likely there are a few other differences
>> that aren't supported yet?
> what do you mean with "structure array indexed from an enum"? I can
> introduce some match-specific struct if you want (just like it's done
> in rockchip_saradc.c with "struct rockchip_saradc_data").
That works, or data can be an enum indexing an array of similar structures.
It doesn't really matter.
>
>>> + }, {
>>> + .compatible = "amlogic,meson-gxl-saradc",
>>> + .data = (void *)12,
>>> + },
>>> + {},
>>> +};
>>> +MODULE_DEVICE_TABLE(of, meson_saradc_of_match);
>>> +
>>> +static int meson_saradc_probe(struct platform_device *pdev)
>>> +{
>>> + struct meson_saradc_priv *priv;
>>> + struct iio_dev *indio_dev;
>>> + struct resource *res;
>>> + void __iomem *base;
>>> + const struct of_device_id *match;
>>> + int ret;
>>> +
>>> + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
>>> + if (!indio_dev) {
>>> + dev_err(&pdev->dev, "failed allocating iio device\n");
>>> + return -ENOMEM;
>>> + }
>>> +
>>> + priv = iio_priv(indio_dev);
>>> +
>>> + match = of_match_device(meson_saradc_of_match, &pdev->dev);
>>> + priv->resolution = (unsigned long)match->data;
>>> +
>>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> + base = devm_ioremap_resource(&pdev->dev, res);
>>> + if (IS_ERR(base))
>>> + return PTR_ERR(base);
>>> +
>>> + priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
>>> + &meson_saradc_regmap_config);
>>> + if (IS_ERR(priv->regmap))
>>> + return PTR_ERR(priv->regmap);
>>> +
>>> + init_completion(&priv->completion);
>>> +
>>> + priv->clkin = devm_clk_get(&pdev->dev, "clkin");
>>> + if (IS_ERR(priv->clkin)) {
>>> + dev_err(&pdev->dev, "failed to get clkin\n");
>>> + return PTR_ERR(priv->clkin);
>>> + }
>>> +
>>> + priv->core_clk = devm_clk_get(&pdev->dev, "core");
>>> + if (IS_ERR(priv->core_clk)) {
>>> + dev_err(&pdev->dev, "failed to get core clk\n");
>>> + return PTR_ERR(priv->core_clk);
>>> + }
>>> +
>>> + priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
>> Oh for a devm_clk_get_optional to handle this boiler plate neatly.
>> It's been suggested before, but nothing seems to have come of it.
> I guess quite a few drivers would benefit from that. maybe we should
> take this to the linux-clk list again?
Perhaps. I guess this has been proposed before but gone nowhere.
I haven't digged into why though.
>
>> Some array clk get functions might also clean this up a touch.
> yes, unfortunately in this case it's not that easy as it would have to
> allow a mix of mandatory and optional clocks. Additionally I cannot
> bulk-enable them unconditionally since some of these are simple gates,
> others need to be reparented and for some the rate has to be set.
>
>>> + if (IS_ERR(priv->sana_clk)) {
>>> + if (PTR_ERR(priv->sana_clk) == -ENOENT) {
>>> + priv->sana_clk = NULL;
>>> + } else {
>>> + dev_err(&pdev->dev, "failed to get sana clk\n");
>>> + return PTR_ERR(priv->sana_clk);
>>> + }
>>> + }
>>> +
>>> + priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
>>> + if (IS_ERR(priv->adc_clk)) {
>>> + if (PTR_ERR(priv->adc_clk) == -ENOENT) {
>>> + priv->adc_clk = NULL;
>>> + } else {
>>> + dev_err(&pdev->dev, "failed to get adc clk\n");
>>> + return PTR_ERR(priv->adc_clk);
>>> + }
>>> + }
>>> +
>>> + priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
>>> + if (IS_ERR(priv->adc_sel_clk)) {
>>> + if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
>>> + priv->adc_sel_clk = NULL;
>>> + } else {
>>> + dev_err(&pdev->dev, "failed to get adc_sel clk\n");
>>> + return PTR_ERR(priv->adc_sel_clk);
>>> + }
>>> + }
>>> +
>>> + /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
>>> + if (!priv->adc_clk) {
>>> + ret = meson_saradc_clk_init(indio_dev, base);
>>> + if (ret)
>>> + return ret;
>>> + }
>>> +
>>> + priv->vref = devm_regulator_get(&pdev->dev, "vref");
>>> + if (IS_ERR(priv->vref)) {
>>> + dev_err(&pdev->dev, "failed to get vref regulator\n");
>>> + return PTR_ERR(priv->vref);
>>> + }
>>> +
>>> + ret = meson_saradc_init(indio_dev);
>>> + if (ret)
>>> + goto err;
>>> +
>>> + ret = meson_saradc_hw_enable(indio_dev);
>>> + if (ret)
>>> + goto err;
>>> +
>>> + platform_set_drvdata(pdev, indio_dev);
>>> +
>>> + indio_dev->name = dev_name(&pdev->dev);
>>> + indio_dev->dev.parent = &pdev->dev;
>>> + indio_dev->dev.of_node = pdev->dev.of_node;
>>> + indio_dev->modes = INDIO_DIRECT_MODE;
>>> + indio_dev->info = &meson_saradc_iio_info;
>>> +
>>> + indio_dev->channels = meson_saradc_iio_channels;
>>> + indio_dev->num_channels = SAR_ADC_NUM_CHANNELS;
>>> +
>>> + ret = iio_device_register(indio_dev);
>>> + if (ret)
>>> + goto err_hw;
>>> +
>>> + return 0;
>>> +
>>> +err_hw:
>>> + meson_saradc_hw_disable(indio_dev);
>>> +err:
>>> + return ret;
>>> +}
>>> +
>>> +static int meson_saradc_remove(struct platform_device *pdev)
>>> +{
>>> + struct iio_dev *indio_dev = platform_get_drvdata(pdev);
>>> +
>>> + meson_saradc_hw_disable(indio_dev);
>>> + iio_device_unregister(indio_dev);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +#ifdef CONFIG_PM_SLEEP
>>> +static int meson_saradc_suspend(struct device *dev)
>>> +{
>>> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
>>> +
>>> + meson_saradc_hw_disable(indio_dev);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int meson_saradc_resume(struct device *dev)
>>> +{
>>> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
>>> +
>>> + return meson_saradc_hw_enable(indio_dev);
>>> +}
>>> +#endif /* CONFIG_PM_SLEEP */
>>> +
>>> +static SIMPLE_DEV_PM_OPS(meson_saradc_pm_ops,
>>> + meson_saradc_suspend, meson_saradc_resume);
>>> +
>>> +static struct platform_driver meson_saradc_driver = {
>>> + .probe = meson_saradc_probe,
>>> + .remove = meson_saradc_remove,
>>> + .driver = {
>>> + .name = "meson-saradc",
>>> + .of_match_table = meson_saradc_of_match,
>>> + .pm = &meson_saradc_pm_ops,
>>> + },
>>> +};
>>> +
>>> +module_platform_driver(meson_saradc_driver);
>>> +
>>> +MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
>>> +MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
>>> +MODULE_LICENSE("GPL v2");
>>>
>>
>
>
> Regards,
> Martin
>
> [0] http://lists.infradead.org/pipermail/linux-amlogic/2016-August/000986.html
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
@ 2017-01-15 13:08 ` Jonathan Cameron
0 siblings, 0 replies; 110+ messages in thread
From: Jonathan Cameron @ 2017-01-15 13:08 UTC (permalink / raw)
To: linus-amlogic
On 14/01/17 17:44, Martin Blumenstingl wrote:
> Hi Jonathan,
>
> thank you for the review!
> (further comments from me inline)
> I think I'll send an updated version on Monday.
>
> On Sat, Jan 14, 2017 at 3:46 PM, Jonathan Cameron <jic23@kernel.org> wrote:
>> On 11/01/17 17:43, Martin Blumenstingl wrote:
>>> This adds support for the SAR (Successive Approximation Register) ADC
>>> on the Amlogic Meson SoCs.
>>>
>>> The code is based on the public S805 (Meson8b) and S905 (GXBB)
>>> datasheets, as well as by reading (various versions of) the vendor
>>> driver and by inspecting the registers on the vendor kernels of my
>>> testing-hardware.
>>>
>>> Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
>>> 10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
>>> The code was written to support older SoCs (Meson8 and Meson8b) as well,
>>> but due to lack of actual testing-hardware no of_device_id was added for
>>> these.
>>>
>>> Two "features" from the vendor driver are currently missing:
>>> - the vendor driver uses channel #7 for calibration (this improves the
>>> accuracy of the results - in my tests the results were less than 3%
>>> off without calibration compared to the vendor driver). Adding support
>>> for this should be easy, but is not required for most applications.
>>> - channel #6 is connected to the SoCs internal temperature sensor.
>>> Adding support for this is probably not so easy since (based on the
>>> u-boot sources) most SoC versions are using different registers and
>>> algorithms for the conversion from "ADC value" to temperature.
>>>
>>> Supported by the hardware but currently not supported by the driver:
>>> - reading multiple channels at the same time (the hardware has a FIFO
>>> buffer which stores multiple results)
>>> - continuous sampling (this would require a way to enable this
>>> individually because otherwise the ADC would be drawing power
>>> constantly)
>>> - interrupt support (similar to the vendor driver this new driver is
>>> polling the results. It is unclear if the IRQ-mode is supported on
>>> older (Meson6 or Meson8) hardware as well or if there are any errata)
>>>
>> Russell Cc'd for a quick question on the clk api.
> a quick side-note the clk API: my driver is a clock consumer and
> provider at the same time. This seems to be a recurring pattern in
> Amlogic hardware designs (as the MMC and DWMAC glue drivers are doing
> this also), see [0]
>
>> Ideally include a source for datasheets if available. Saves time googling and
>> perhaps getting the wrong thing!
> OK, will do this in v2
>
>> A few other minor comments inline. Pretty good V1.
> thanks :-)
>
>> Jonathan
>>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>> ---
>>> drivers/iio/adc/Kconfig | 12 +
>>> drivers/iio/adc/Makefile | 1 +
>>> drivers/iio/adc/meson_saradc.c | 860 +++++++++++++++++++++++++++++++++++++++++
>>> 3 files changed, 873 insertions(+)
>>> create mode 100644 drivers/iio/adc/meson_saradc.c
>>>
>>> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
>>> index 9c8b558ba19e..86059b9b91bf 100644
>>> --- a/drivers/iio/adc/Kconfig
>>> +++ b/drivers/iio/adc/Kconfig
>>> @@ -371,6 +371,18 @@ config MEN_Z188_ADC
>>> This driver can also be built as a module. If so, the module will be
>>> called men_z188_adc.
>>>
>>> +config MESON_SARADC
>>> + tristate "Amlogic Meson SAR ADC driver"
>>> + default ARCH_MESON
>>> + depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
>>> + select REGMAP_MMIO
>>> + help
>>> + Say yes here to build support for the SAR ADC found in Amlogic Meson
>>> + SoCs.
>>> +
>>> + To compile this driver as a module, choose M here: the
>>> + module will be called meson_saradc.
>>> +
>>> config MXS_LRADC
>>> tristate "Freescale i.MX23/i.MX28 LRADC"
>>> depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
>>> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
>>> index d36c4be8d1fc..de05b9e75f8f 100644
>>> --- a/drivers/iio/adc/Makefile
>>> +++ b/drivers/iio/adc/Makefile
>>> @@ -36,6 +36,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
>>> obj-$(CONFIG_MCP3422) += mcp3422.o
>>> obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
>>> obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
>>> +obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
>>> obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
>>> obj-$(CONFIG_NAU7802) += nau7802.o
>>> obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
>>> diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
>>> new file mode 100644
>>> index 000000000000..06e8ac620385
>>> --- /dev/null
>>> +++ b/drivers/iio/adc/meson_saradc.c
>>> @@ -0,0 +1,860 @@
>>> +/*
>>> + * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
>>> + *
>>> + * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License version 2 as
>>> + * published by the Free Software Foundation.
>>> + *
>>> + * You should have received a copy of the GNU General Public License
>>> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
>>> + */
>>> +
>>> +#include <linux/bitfield.h>
>>> +#include <linux/clk-provider.h>
>>> +#include <linux/module.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/interrupt.h>
>>> +#include <linux/io.h>
>>> +#include <linux/iio/iio.h>
>>> +#include <linux/of.h>
>>> +#include <linux/of_device.h>
>>> +#include <linux/clk.h>
>>> +#include <linux/completion.h>
>>> +#include <linux/delay.h>
>>> +#include <linux/reset.h>
>>> +#include <linux/regmap.h>
>>> +#include <linux/regulator/consumer.h>
>>> +
>>> +#define SAR_ADC_REG0 0x00
>>> + #define SAR_ADC_REG0_PANEL_DETECT BIT(31)
>>> + #define SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
>>> + #define SAR_ADC_REG0_DELTA_BUSY BIT(30)
>>> + #define SAR_ADC_REG0_AVG_BUSY BIT(29)
>>> + #define SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
>>> + #define SAR_ADC_REG0_FIFO_FULL BIT(27)
>>> + #define SAR_ADC_REG0_FIFO_EMPTY BIT(26)
>>> + #define SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
>>> + #define SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
>>> + #define SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
>>> + #define SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
>>> + #define SAR_ADC_REG0_SAMPLING_STOP BIT(14)
>>> + #define SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
>>> + #define SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
>>> + #define SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
>>> + #define SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
>>> + #define SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
>>> + #define SAR_ADC_REG0_SAMPLING_START BIT(2)
>>> + #define SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
>>> + #define SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
>>> +
>>> +#define SAR_ADC_CHAN_LIST 0x04
>>> + #define SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
>>> + #define SAR_ADC_CHAN_CHAN_ENTRY_MASK(_chan) \
>>> + (GENMASK(2, 0) << (_chan * 3))
>>> +
>>> +#define SAR_ADC_AVG_CNTL 0x08
>>> + #define SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
>>> + (16 + (_chan * 2))
>>> + #define SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
>>> + (GENMASK(17, 16) << (_chan * 2))
>>> + #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
>>> + (0 + (_chan * 2))
>>> + #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
>>> + (GENMASK(1, 0) << (_chan * 2))
>>> +
>>> +#define SAR_ADC_REG3 0x0c
>>> + #define SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
>>> + #define SAR_ADC_REG3_CLK_EN BIT(30)
>>> + #define SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
>>> + #define SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
>>> + #define SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
>>> + #define SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
>>> + #define SAR_ADC_REG3_DETECT_EN BIT(22)
>>> + #define SAR_ADC_REG3_ADC_EN BIT(21)
>>> + #define SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
>>> + #define SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
>>> + #define SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
>>> + #define SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
>>> + #define SAR_ADC_REG3_ADC_CLK_DIV_MASK GENMASK(15, 10)
>>> + #define SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
>>> + #define SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
>>> +
>>> +#define SAR_ADC_DELAY 0x10
>>> + #define SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
>>> + #define SAR_ADC_DELAY_BL30_BUSY BIT(15)
>>> + #define SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
>>> + #define SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
>>> + #define SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
>>> + #define SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
>>> +
>>> +#define SAR_ADC_LAST_RD 0x14
>>> + #define SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
>>> + #define SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
>>> +
>>> +#define SAR_ADC_FIFO_RD 0x18
>>> + #define SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
>>> + #define SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
>>> +
>>> +#define SAR_ADC_AUX_SW 0x1c
>>> + #define SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
>>> + (GENMASK(10, 8) << ((_chan - 2) * 2))
>>> + #define SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
>>> + #define SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
>>> + #define SAR_ADC_AUX_SW_MODE_SEL BIT(4)
>>> + #define SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
>>> + #define SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
>>> + #define SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
>>> + #define SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
>>> +
>>> +#define SAR_ADC_CHAN_10_SW 0x20
>>> + #define SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
>>> + #define SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
>>> +
>>> +#define SAR_ADC_DETECT_IDLE_SW 0x24
>>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
>>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK GENMASK(25, 23)
>>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_P_MUX BIT(22)
>>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_N_MUX BIT(21)
>>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
>>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YP_DRIVE_SW BIT(19)
>>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XP_DRIVE_SW BIT(18)
>>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YM_DRIVE_SW BIT(17)
>>> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XM_DRIVE_SW BIT(16)
>>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK GENMASK(9, 7)
>>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_P_MUX BIT(6)
>>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_N_MUX BIT(5)
>>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
>>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YP_DRIVE_SW BIT(3)
>>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XP_DRIVE_SW BIT(2)
>>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YM_DRIVE_SW BIT(1)
>>> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XM_DRIVE_SW BIT(0)
>>> +
>>> +#define SAR_ADC_DELTA_10 0x28
>>> + #define SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
>>> + #define SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
>>> + #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_SHIFT 16
>>> + #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
>>> + #define SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
>>> + #define SAR_ADC_DELTA_10_TS_C_SHIFT 11
>>> + #define SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
>>> + #define SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
>>> + #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_SHIFT 0
>>> + #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
>>> +
>>> +/* NOTE: registers from here are undocumented (the vendor Linux kernel driver
>>> + * and u-boot source served as reference). These only seem to be relevant on
>>> + * GXBB and newer.
>>> + */
>>> +#define SAR_ADC_REG11 0x2c
>>> + #define SAR_ADC_REG11_BANDGAP_EN BIT(13)
>>> +
>>> +#define SAR_ADC_REG13 0x34
>>> + #define SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
>>> +
>>> +#define SAR_ADC_MAX_FIFO_SIZE 32
>>> +#define SAR_ADC_NUM_CHANNELS ARRAY_SIZE(meson_saradc_iio_channels)
>>> +#define SAR_ADC_VALUE_MASK(_priv) (BIT(_priv->resolution) - 1)
>>> +
>>> +#define MESON_SAR_ADC_CHAN(_chan, _type) { \
>>> + .type = _type, \
>>> + .indexed = true, \
>>> + .channel = _chan, \
>>> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
>>> + BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
>>> + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
>>> + .datasheet_name = "SAR_ADC_CH"#_chan, \
>>> +}
>>> +
>>> +/* TODO: the hardware supports IIO_TEMP for channel 6 as well which is
>> Multline comment syntax.
> I got this wrong in 2 other places as well. will be fixed in v2, thanks!
>
>>> + * currently not supported by this driver.
>>> + */
>>> +static const struct iio_chan_spec meson_saradc_iio_channels[] = {
>>> + MESON_SAR_ADC_CHAN(0, IIO_VOLTAGE),
>>> + MESON_SAR_ADC_CHAN(1, IIO_VOLTAGE),
>>> + MESON_SAR_ADC_CHAN(2, IIO_VOLTAGE),
>>> + MESON_SAR_ADC_CHAN(3, IIO_VOLTAGE),
>>> + MESON_SAR_ADC_CHAN(4, IIO_VOLTAGE),
>>> + MESON_SAR_ADC_CHAN(5, IIO_VOLTAGE),
>>> + MESON_SAR_ADC_CHAN(6, IIO_VOLTAGE),
>>> + MESON_SAR_ADC_CHAN(7, IIO_VOLTAGE),
>>> + IIO_CHAN_SOFT_TIMESTAMP(8),
>>> +};
>>> +
>>> +enum meson_saradc_avg_mode {
>>> + NO_AVERAGING = 0x0,
>>> + MEAN_AVERAGING = 0x1,
>>> + MEDIAN_AVERAGING = 0x2,
>>> +};
>>> +
>>> +enum meson_saradc_num_samples {
>>> + ONE_SAMPLE = 0x0,
>>> + TWO_SAMPLES = 0x1,
>>> + FOUR_SAMPLES = 0x2,
>>> + EIGHT_SAMPLES = 0x3,
>>> +};
>>> +
>>> +enum meson_saradc_chan7_mux_sel {
>>> + CHAN7_MUX_VSS = 0x0,
>>> + CHAN7_MUX_VDD_DIV4 = 0x1,
>>> + CHAN7_MUX_VDD_DIV2 = 0x2,
>>> + CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
>>> + CHAN7_MUX_VDD = 0x4,
>>> + CHAN7_MUX_CH7_INPUT = 0x7,
>>> +};
>>> +
>>> +struct meson_saradc_priv {
>>> + struct regmap *regmap;
>>> + struct clk *clkin;
>>> + struct clk *core_clk;
>>> + struct clk *sana_clk;
>>> + struct clk *adc_sel_clk;
>>> + struct clk *adc_clk;
>>> + struct clk_gate clk_gate;
>>> + struct clk *adc_div_clk;
>>> + struct clk_divider clk_div;
>>> + struct regulator *vref;
>>> + struct completion completion;
>>> + u8 resolution;
>>> +};
>>> +
>>> +static const struct regmap_config meson_saradc_regmap_config = {
>>> + .reg_bits = 8,
>>> + .val_bits = 32,
>>> + .reg_stride = 4,
>>> + .max_register = SAR_ADC_REG13,
>>> +};
>>> +
>>> +static unsigned int meson_saradc_get_fifo_count(struct iio_dev *indio_dev)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + u32 regval;
>>> +
>>> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
>>> +
>>> + return FIELD_GET(SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
>>> +}
>>> +
>>> +static int meson_saradc_wait_busy_clear(struct iio_dev *indio_dev)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + int regval, timeout = 10000;
>>> +
>>> + do {
>>> + udelay(1);
>>> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
>>> + } while (FIELD_GET(SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
>>> +
>>> + if (timeout < 0)
>>> + return -ETIMEDOUT;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int meson_saradc_read_raw_sample(struct iio_dev *indio_dev,
>>> + const struct iio_chan_spec *chan,
>>> + int *val)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0;
>>> +
>>> + ret = meson_saradc_wait_busy_clear(indio_dev);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
>>> +
>>> + while (meson_saradc_get_fifo_count(indio_dev) > 0 &&
>>> + count < SAR_ADC_MAX_FIFO_SIZE) {
>>> + regmap_read(priv->regmap, SAR_ADC_FIFO_RD, ®val);
>>> +
>>> + fifo_chan = FIELD_GET(SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
>>> + if (fifo_chan == chan->channel) {
>>> + fifo_val = FIELD_GET(SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK,
>>> + regval) & SAR_ADC_VALUE_MASK(priv);
>>> + sum += fifo_val;
>>> + count++;
>>> + }
>>> + }
>>> +
>>> + if (!count)
>>> + return -ENOENT;
>>> +
>>> + *val = sum / count;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static void meson_saradc_set_averaging(struct iio_dev *indio_dev,
>>> + const struct iio_chan_spec *chan,
>>> + enum meson_saradc_avg_mode mode,
>>> + enum meson_saradc_num_samples samples)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + u32 val;
>>> +
>>> + val = samples << SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(chan->channel);
>>> + regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
>>> + SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(chan->channel),
>>> + val);
>>> +
>>> + val = mode << SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(chan->channel);
>>> + regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
>>> + SAR_ADC_AVG_CNTL_AVG_MODE_MASK(chan->channel), val);
>>> +}
>>> +
>>> +static void meson_saradc_enable_channel(struct iio_dev *indio_dev,
>>> + const struct iio_chan_spec *chan)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + u32 regval;
>>> +
>>> + /* the SAR ADC engine allows sampling multiple channels at the same
>>> + * time. to keep it simple we're only working with one *internal*
>>> + * channel, which starts counting at index 0 (which means: count = 1).
>>> + */
>>> + regval = FIELD_PREP(SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
>>> + regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
>>> + SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
>>> +
>>> + /* map channel index 0 to the channel which we want to read */
>>> + regval = FIELD_PREP(SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), chan->channel);
>>> + regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
>>> + SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), regval);
>>> +
>>> + regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
>>> + chan->channel);
>>> + regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
>>> + SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
>>> + regval);
>>> +
>>> + regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
>>> + chan->channel);
>>> + regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
>>> + SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
>>> + regval);
>>> +
>>> + if (chan->channel == 6)
>>> + regmap_update_bits(priv->regmap, SAR_ADC_DELTA_10,
>>> + SAR_ADC_DELTA_10_TEMP_SEL, 0);
>>> +}
>>> +
>>> +static void meson_saradc_set_channel7_mux(struct iio_dev *indio_dev,
>>> + enum meson_saradc_chan7_mux_sel sel)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + u32 regval;
>>> +
>>> + regval = FIELD_PREP(SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
>>> + SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
>>> +
>>> + usleep_range(10, 20);
>>> +}
>>> +
>>> +static void meson_saradc_start_sample_engine(struct iio_dev *indio_dev)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> +
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>>> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
>>> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
>>> +
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>>> + SAR_ADC_REG0_SAMPLING_START,
>>> + SAR_ADC_REG0_SAMPLING_START);
>>> +}
>>> +
>>> +static void meson_saradc_stop_sample_engine(struct iio_dev *indio_dev)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> +
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>>> + SAR_ADC_REG0_SAMPLING_STOP,
>>> + SAR_ADC_REG0_SAMPLING_STOP);
>>> +
>>> + /* wait until all modules are stopped */
>>> + meson_saradc_wait_busy_clear(indio_dev);
>>> +
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>>> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
>>> +}
>>> +
>>> +static void meson_saradc_lock(struct iio_dev *indio_dev)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + int val;
>>> +
>>> + mutex_lock(&indio_dev->mlock);
>>> +
>>> + /* prevent BL30 from using the SAR ADC while we are using it */
>>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>>> + SAR_ADC_DELAY_KERNEL_BUSY,
>>> + SAR_ADC_DELAY_KERNEL_BUSY);
>>> +
>>> + /* wait until BL30 releases it's lock (so we can use the SAR ADC) */
>>> + do {
>>> + udelay(1);
>>> + regmap_read(priv->regmap, SAR_ADC_DELAY, &val);
>>> + } while (val & SAR_ADC_DELAY_BL30_BUSY);
>>> +}
>>> +
>>> +static void meson_saradc_unlock(struct iio_dev *indio_dev)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> +
>>> + /* allow BL30 to use the SAR ADC again */
>>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>>> + SAR_ADC_DELAY_KERNEL_BUSY, 0);
>>> +
>>> + mutex_unlock(&indio_dev->mlock);
>>> +}
>>> +
>>> +static int meson_saradc_get_sample(struct iio_dev *indio_dev,
>>> + const struct iio_chan_spec *chan,
>>> + enum meson_saradc_avg_mode avg_mode,
>>> + enum meson_saradc_num_samples avg_samples,
>>> + int *val)
>>> +{
>>> + int ret, tmp;
>>> +
>>> + meson_saradc_lock(indio_dev);
>>> +
>>> + /* clear old values from the FIFO buffer, ignoring errors */
>>> + meson_saradc_read_raw_sample(indio_dev, chan, &tmp);
>>> +
>>> + meson_saradc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
>>> +
>>> + meson_saradc_enable_channel(indio_dev, chan);
>>> +
>>> + meson_saradc_start_sample_engine(indio_dev);
>>> + ret = meson_saradc_read_raw_sample(indio_dev, chan, val);
>>> + meson_saradc_stop_sample_engine(indio_dev);
>>> +
>>> + meson_saradc_unlock(indio_dev);
>>> +
>>> + if (ret) {
>>> + dev_warn(&indio_dev->dev,
>>> + "failed to read sample for channel %d: %d\n",
>>> + chan->channel, ret);
>>> + return ret;
>>> + }
>>> +
>>> + return IIO_VAL_INT;
>>> +}
>>> +
>>> +static int meson_saradc_iio_info_read_raw(struct iio_dev *indio_dev,
>>> + const struct iio_chan_spec *chan,
>>> + int *val, int *val2, long mask)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + int ret;
>>> +
>>> + switch (mask) {
>>> + case IIO_CHAN_INFO_RAW:
>>> + return meson_saradc_get_sample(indio_dev, chan, NO_AVERAGING,
>>> + ONE_SAMPLE, val);
>>> + break;
>>> +
>>> + case IIO_CHAN_INFO_AVERAGE_RAW:
>>> + return meson_saradc_get_sample(indio_dev, chan, MEAN_AVERAGING,
>>> + EIGHT_SAMPLES, val);
>>> + break;
>>> +
>>> + case IIO_CHAN_INFO_SCALE:
>>> + ret = regulator_get_voltage(priv->vref);
>>> + if (ret < 0) {
>>> + dev_err(&indio_dev->dev,
>>> + "failed to get vref voltage: %d\n", ret);
>>> + return ret;
>>> + }
>>> +
>>> + *val = ret / 1000;
>>> + *val2 = priv->resolution;
>>> + return IIO_VAL_FRACTIONAL_LOG2;
>>> +
>>> + default:
>>> + return -EINVAL;
>>> + }
>>> +}
>>> +
>>> +static int meson_saradc_clk_init(struct iio_dev *indio_dev, void __iomem *base)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + struct clk_init_data init;
>>> + char clk_name[32];
>>> + const char *clk_parents[1];
>>> +
>>> + snprintf(clk_name, sizeof(clk_name), "%s#adc_div",
>>> + of_node_full_name(indio_dev->dev.of_node));
>>> + init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
>>> + init.flags = 0;
>>> + init.ops = &clk_divider_ops;
>>> + clk_parents[0] = __clk_get_name(priv->clkin);
>>> + init.parent_names = clk_parents;
>>> + init.num_parents = 1;
>>> +
>>> + priv->clk_div.reg = base + SAR_ADC_REG3;
>>> + priv->clk_div.shift = SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
>>> + priv->clk_div.width = SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
>>> + priv->clk_div.hw.init = &init;
>>> + priv->clk_div.flags = 0;
>>> +
>>> + priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
>>> + &priv->clk_div.hw);
>>> + if (WARN_ON(IS_ERR(priv->adc_div_clk)))
>>> + return PTR_ERR(priv->adc_div_clk);
>>> +
>>> + snprintf(clk_name, sizeof(clk_name), "%s#adc_en",
>>> + of_node_full_name(indio_dev->dev.of_node));
>>> + init.name = devm_kstrdup(&indio_dev->dev, clk_name, GFP_KERNEL);
>>> + init.flags = CLK_SET_RATE_PARENT;
>>> + init.ops = &clk_gate_ops;
>>> + clk_parents[0] = __clk_get_name(priv->adc_div_clk);
>>> + init.parent_names = clk_parents;
>>> + init.num_parents = 1;
>>> +
>>> + priv->clk_gate.reg = base + SAR_ADC_REG3;
>>> + priv->clk_gate.bit_idx = fls(SAR_ADC_REG3_CLK_EN);
>>> + priv->clk_gate.hw.init = &init;
>>> +
>>> + priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
>>> + if (WARN_ON(IS_ERR(priv->adc_clk)))
>>> + return PTR_ERR(priv->adc_clk);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int meson_saradc_init(struct iio_dev *indio_dev)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + int regval, ret;
>>> +
>>> + /* make sure we start at CH7 input */
>> why? Seems like a little more detail would be good here ;)
> I'll change this to "make sure we start at CH7 input since the other
> muxes are only used for internal calibration." in v2
>
>>> + meson_saradc_set_channel7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
>>> +
>>> + regmap_read(priv->regmap, SAR_ADC_REG3, ®val);
>>> + if (regval & SAR_ADC_REG3_BL30_INITIALIZED) {
>>> + dev_info(&indio_dev->dev, "already initialized by BL30\n");
>>> + return 0;
>>> + }
>>> +
>>> + dev_info(&indio_dev->dev, "initializing SAR ADC\n");
>> I'd argue this provides no useful info so should be dropped.
>> Useful for debugging no doubt, but just noise going forward.
> do you want me to remove them or should I turn them into dev_dbg() (so
> they can be enabled for debugging purposes)?
Drop it entirely.
>
>>> +
>>> + meson_saradc_stop_sample_engine(indio_dev);
>>> +
>>> + /* update the channel 6 MUX to select the temperature sensor */
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
>>> + SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
>>> + SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
>>> +
>>> + /* disable all channels by default */
>>> + regmap_write(priv->regmap, SAR_ADC_CHAN_LIST, 0x0);
>>> +
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
>>> + SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
>>> + SAR_ADC_REG3_CNTL_USE_SC_DLY,
>>> + SAR_ADC_REG3_CNTL_USE_SC_DLY);
>>> +
>>> + /* delay between two samples = (10+1) * 1uS */
>>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>>> + SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
>>> + FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK, 10));
>>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>>> + SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
>>> + FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 0));
>>> +
>>> + /* delay between two samples = (10+1) * 1uS */
>>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>>> + SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
>>> + FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 10));
>>> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
>>> + SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
>>> + FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 1));
>>> +
>> Cool. I hadn't come across FIELD_PREP before. Neater and tidier than having
>> a shift and a mask for at least some usecases.
> I think these were introduced with v4.9. I like them because I tend
> use GENMASK() incorrectly and with those macros I get an error at
> compile-time (without having to debug my code at all)
>
>>> + ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
>>> + if (ret) {
>>> + dev_err(&indio_dev->dev,
>>> + "failed to set adc parent to clkin\n");
>>> + return ret;
>>> + }
>>> +
>>> + ret = clk_set_rate(priv->adc_clk, 1200000);
>>> + if (ret) {
>>> + dev_err(&indio_dev->dev, "failed to set adc clock rate\n");
>>> + return ret;
>>> + }
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int meson_saradc_hw_enable(struct iio_dev *indio_dev)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> + int ret;
>>> +
>>> + meson_saradc_lock(indio_dev);
>>> +
>>> + ret = regulator_enable(priv->vref);
>>> + if (ret < 0) {
>>> + dev_err(&indio_dev->dev, "failed to enable vref regulator\n");
>>> + goto err_vref;
>>> + }
>>> +
>>> + ret = clk_prepare_enable(priv->core_clk);
>>> + if (ret) {
>>> + dev_err(&indio_dev->dev, "failed to enable core clk\n");
>>> + goto err_core_clk;
>>> + }
>>> +
>>> + ret = clk_prepare_enable(priv->sana_clk);
>>> + if (ret) {
>>> + dev_err(&indio_dev->dev, "failed to enable sana clk\n");
>>> + goto err_sana_clk;
>>> + }
>>> +
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG11,
>>> + SAR_ADC_REG11_BANDGAP_EN, SAR_ADC_REG11_BANDGAP_EN);
>> Is this controlling an offset for a bandgap or some actual electronics?
>> Not sure if it should be disabled on error and the datasheets I've found are
>> far from great! You disable it in the disable, so I'd expect it to be
>> unwound on error in here too.
> actually the bandgap is not documented at all :(
>
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN,
>>> + SAR_ADC_REG3_ADC_EN);
>> The fact you turn this of in the disable suggests to me that on error
>> you should be doing it in here too.
> I will disable this along with SAR_ADC_REG11_BANDGAP_EN in the
> err_adc_clk label, thanks for spotting this.
>
>>> +
>>> + udelay(5);
>>> +
>>> + ret = clk_prepare_enable(priv->adc_clk);
>>> + if (ret) {
>>> + dev_err(&indio_dev->dev, "failed to enable adc_en clk\n");
>>> + goto err_adc_clk;
>>> + }
>>> +
>>> + meson_saradc_unlock(indio_dev);
>>> +
>>> + return 0;
>>> +
>>> +err_adc_clk:
>>> + clk_disable_unprepare(priv->sana_clk);
>>> +err_sana_clk:
>>> + clk_disable_unprepare(priv->core_clk);
>>> +err_core_clk:
>>> + regulator_disable(priv->vref);
>>> +err_vref:
>>> + meson_saradc_unlock(indio_dev);
>>> + return ret;
>>> +}
>>> +
>>> +static void meson_saradc_hw_disable(struct iio_dev *indio_dev)
>>> +{
>>> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
>>> +
>>> + meson_saradc_lock(indio_dev);
>>> +
>>> + clk_disable_unprepare(priv->adc_clk);
>>> +
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN, 0);
>>> + regmap_update_bits(priv->regmap, SAR_ADC_REG11,
>>> + SAR_ADC_REG11_BANDGAP_EN, 0);
>>> +
>>> + clk_disable_unprepare(priv->sana_clk);
>>> + clk_disable_unprepare(priv->core_clk);
>>> +
>>> + regulator_disable(priv->vref);
>>> +
>>> + meson_saradc_unlock(indio_dev);
>>> +}
>>> +
>>> +static const struct iio_info meson_saradc_iio_info = {
>>> + .read_raw = meson_saradc_iio_info_read_raw,
>>> + .driver_module = THIS_MODULE,
>>> +};
>>> +
>>> +static const struct of_device_id meson_saradc_of_match[] = {
>>> + {
>>> + .compatible = "amlogic,meson-gxbb-saradc",
>>> + .data = (void *)10,
>> Might have been worth having a structure array indexed from an enum.
>> For now it is overkill, but seems likely there are a few other differences
>> that aren't supported yet?
> what do you mean with "structure array indexed from an enum"? I can
> introduce some match-specific struct if you want (just like it's done
> in rockchip_saradc.c with "struct rockchip_saradc_data").
That works, or data can be an enum indexing an array of similar structures.
It doesn't really matter.
>
>>> + }, {
>>> + .compatible = "amlogic,meson-gxl-saradc",
>>> + .data = (void *)12,
>>> + },
>>> + {},
>>> +};
>>> +MODULE_DEVICE_TABLE(of, meson_saradc_of_match);
>>> +
>>> +static int meson_saradc_probe(struct platform_device *pdev)
>>> +{
>>> + struct meson_saradc_priv *priv;
>>> + struct iio_dev *indio_dev;
>>> + struct resource *res;
>>> + void __iomem *base;
>>> + const struct of_device_id *match;
>>> + int ret;
>>> +
>>> + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
>>> + if (!indio_dev) {
>>> + dev_err(&pdev->dev, "failed allocating iio device\n");
>>> + return -ENOMEM;
>>> + }
>>> +
>>> + priv = iio_priv(indio_dev);
>>> +
>>> + match = of_match_device(meson_saradc_of_match, &pdev->dev);
>>> + priv->resolution = (unsigned long)match->data;
>>> +
>>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> + base = devm_ioremap_resource(&pdev->dev, res);
>>> + if (IS_ERR(base))
>>> + return PTR_ERR(base);
>>> +
>>> + priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
>>> + &meson_saradc_regmap_config);
>>> + if (IS_ERR(priv->regmap))
>>> + return PTR_ERR(priv->regmap);
>>> +
>>> + init_completion(&priv->completion);
>>> +
>>> + priv->clkin = devm_clk_get(&pdev->dev, "clkin");
>>> + if (IS_ERR(priv->clkin)) {
>>> + dev_err(&pdev->dev, "failed to get clkin\n");
>>> + return PTR_ERR(priv->clkin);
>>> + }
>>> +
>>> + priv->core_clk = devm_clk_get(&pdev->dev, "core");
>>> + if (IS_ERR(priv->core_clk)) {
>>> + dev_err(&pdev->dev, "failed to get core clk\n");
>>> + return PTR_ERR(priv->core_clk);
>>> + }
>>> +
>>> + priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
>> Oh for a devm_clk_get_optional to handle this boiler plate neatly.
>> It's been suggested before, but nothing seems to have come of it.
> I guess quite a few drivers would benefit from that. maybe we should
> take this to the linux-clk list again?
Perhaps. I guess this has been proposed before but gone nowhere.
I haven't digged into why though.
>
>> Some array clk get functions might also clean this up a touch.
> yes, unfortunately in this case it's not that easy as it would have to
> allow a mix of mandatory and optional clocks. Additionally I cannot
> bulk-enable them unconditionally since some of these are simple gates,
> others need to be reparented and for some the rate has to be set.
>
>>> + if (IS_ERR(priv->sana_clk)) {
>>> + if (PTR_ERR(priv->sana_clk) == -ENOENT) {
>>> + priv->sana_clk = NULL;
>>> + } else {
>>> + dev_err(&pdev->dev, "failed to get sana clk\n");
>>> + return PTR_ERR(priv->sana_clk);
>>> + }
>>> + }
>>> +
>>> + priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
>>> + if (IS_ERR(priv->adc_clk)) {
>>> + if (PTR_ERR(priv->adc_clk) == -ENOENT) {
>>> + priv->adc_clk = NULL;
>>> + } else {
>>> + dev_err(&pdev->dev, "failed to get adc clk\n");
>>> + return PTR_ERR(priv->adc_clk);
>>> + }
>>> + }
>>> +
>>> + priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
>>> + if (IS_ERR(priv->adc_sel_clk)) {
>>> + if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
>>> + priv->adc_sel_clk = NULL;
>>> + } else {
>>> + dev_err(&pdev->dev, "failed to get adc_sel clk\n");
>>> + return PTR_ERR(priv->adc_sel_clk);
>>> + }
>>> + }
>>> +
>>> + /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
>>> + if (!priv->adc_clk) {
>>> + ret = meson_saradc_clk_init(indio_dev, base);
>>> + if (ret)
>>> + return ret;
>>> + }
>>> +
>>> + priv->vref = devm_regulator_get(&pdev->dev, "vref");
>>> + if (IS_ERR(priv->vref)) {
>>> + dev_err(&pdev->dev, "failed to get vref regulator\n");
>>> + return PTR_ERR(priv->vref);
>>> + }
>>> +
>>> + ret = meson_saradc_init(indio_dev);
>>> + if (ret)
>>> + goto err;
>>> +
>>> + ret = meson_saradc_hw_enable(indio_dev);
>>> + if (ret)
>>> + goto err;
>>> +
>>> + platform_set_drvdata(pdev, indio_dev);
>>> +
>>> + indio_dev->name = dev_name(&pdev->dev);
>>> + indio_dev->dev.parent = &pdev->dev;
>>> + indio_dev->dev.of_node = pdev->dev.of_node;
>>> + indio_dev->modes = INDIO_DIRECT_MODE;
>>> + indio_dev->info = &meson_saradc_iio_info;
>>> +
>>> + indio_dev->channels = meson_saradc_iio_channels;
>>> + indio_dev->num_channels = SAR_ADC_NUM_CHANNELS;
>>> +
>>> + ret = iio_device_register(indio_dev);
>>> + if (ret)
>>> + goto err_hw;
>>> +
>>> + return 0;
>>> +
>>> +err_hw:
>>> + meson_saradc_hw_disable(indio_dev);
>>> +err:
>>> + return ret;
>>> +}
>>> +
>>> +static int meson_saradc_remove(struct platform_device *pdev)
>>> +{
>>> + struct iio_dev *indio_dev = platform_get_drvdata(pdev);
>>> +
>>> + meson_saradc_hw_disable(indio_dev);
>>> + iio_device_unregister(indio_dev);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +#ifdef CONFIG_PM_SLEEP
>>> +static int meson_saradc_suspend(struct device *dev)
>>> +{
>>> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
>>> +
>>> + meson_saradc_hw_disable(indio_dev);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int meson_saradc_resume(struct device *dev)
>>> +{
>>> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
>>> +
>>> + return meson_saradc_hw_enable(indio_dev);
>>> +}
>>> +#endif /* CONFIG_PM_SLEEP */
>>> +
>>> +static SIMPLE_DEV_PM_OPS(meson_saradc_pm_ops,
>>> + meson_saradc_suspend, meson_saradc_resume);
>>> +
>>> +static struct platform_driver meson_saradc_driver = {
>>> + .probe = meson_saradc_probe,
>>> + .remove = meson_saradc_remove,
>>> + .driver = {
>>> + .name = "meson-saradc",
>>> + .of_match_table = meson_saradc_of_match,
>>> + .pm = &meson_saradc_pm_ops,
>>> + },
>>> +};
>>> +
>>> +module_platform_driver(meson_saradc_driver);
>>> +
>>> +MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
>>> +MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
>>> +MODULE_LICENSE("GPL v2");
>>>
>>
>
>
> Regards,
> Martin
>
> [0] http://lists.infradead.org/pipermail/linux-amlogic/2016-August/000986.html
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
2017-01-15 12:26 ` Lars-Peter Clausen
(?)
@ 2017-01-15 13:09 ` Jonathan Cameron
-1 siblings, 0 replies; 110+ messages in thread
From: Jonathan Cameron @ 2017-01-15 13:09 UTC (permalink / raw)
To: Lars-Peter Clausen, Martin Blumenstingl, knaack.h, pmeerw,
robh+dt, mark.rutland, khilman, linux-iio, devicetree,
linux-amlogic, linux-clk
Cc: carlo, catalin.marinas, will.deacon, mturquette, sboyd,
narmstrong, linux-arm-kernel
On 15/01/17 12:26, Lars-Peter Clausen wrote:
> On 01/11/2017 06:43 PM, Martin Blumenstingl wrote:
>> + indio_dev->name = dev_name(&pdev->dev);
>
> The name is supposed to be the type of the device, e.g. part name, not the
> name of parent device instance. E.g. meson-gxbb-saradc or meson-gxl-saradc
> in this case.
Drat. I've been missing these again. Somehow, never manage to get them
onto those things my eyes pick up whilst reviewing.
Thanks Lars,
Jonathan
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-iio" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
@ 2017-01-15 13:09 ` Jonathan Cameron
0 siblings, 0 replies; 110+ messages in thread
From: Jonathan Cameron @ 2017-01-15 13:09 UTC (permalink / raw)
To: linux-arm-kernel
On 15/01/17 12:26, Lars-Peter Clausen wrote:
> On 01/11/2017 06:43 PM, Martin Blumenstingl wrote:
>> + indio_dev->name = dev_name(&pdev->dev);
>
> The name is supposed to be the type of the device, e.g. part name, not the
> name of parent device instance. E.g. meson-gxbb-saradc or meson-gxl-saradc
> in this case.
Drat. I've been missing these again. Somehow, never manage to get them
onto those things my eyes pick up whilst reviewing.
Thanks Lars,
Jonathan
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-iio" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
@ 2017-01-15 13:09 ` Jonathan Cameron
0 siblings, 0 replies; 110+ messages in thread
From: Jonathan Cameron @ 2017-01-15 13:09 UTC (permalink / raw)
To: linus-amlogic
On 15/01/17 12:26, Lars-Peter Clausen wrote:
> On 01/11/2017 06:43 PM, Martin Blumenstingl wrote:
>> + indio_dev->name = dev_name(&pdev->dev);
>
> The name is supposed to be the type of the device, e.g. part name, not the
> name of parent device instance. E.g. meson-gxbb-saradc or meson-gxl-saradc
> in this case.
Drat. I've been missing these again. Somehow, never manage to get them
onto those things my eyes pick up whilst reviewing.
Thanks Lars,
Jonathan
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-iio" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v2 0/4] Amlogic Meson SAR ADC support
2017-01-11 17:43 ` Martin Blumenstingl
(?)
(?)
@ 2017-01-15 22:42 ` Martin Blumenstingl
-1 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-15 22:42 UTC (permalink / raw)
To: jic23-DgEjT+Ai2ygdnm+yROfE0A, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
khilman-rdvid1DuHRBWk0Htik3J/w, linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-clk-u79uwXL29TY76Z2rM5mHXA
Cc: carlo-KA+7E9HrN00dnm+yROfE0A, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, mturquette-rdvid1DuHRBWk0Htik3J/w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, narmstrong-rdvid1DuHRBWk0Htik3J/w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Martin Blumenstingl
This series add support for the SAR ADC on Amlogic Meson GXBB, GXL and
GXM SoCs.
The hardware on GXBB provides 10-bit ADC results, while GXL and GXM are
providing 12-bit results. Support for older SoCs (Meson8b and Meson8)
can be added with little effort, most of which is testing I guess (I
don't have any pre-GXBB hardware so I can't say).
A new set of clocks had to be added to the GXBB clock controller (used
by the GXBB/GXL/GXM SoCs) which are required to get the ADC working.
The ADC itself can sample multiple channels at the same time and allows
capturing multiple samples (which can be used for filtering/averaging).
The ADC results are stored inside a FIFO register. More details on what
the driver supports (or doesn't) can be found in the description of
patch #3.
The code is based on the public S805 (Meson8b) and S905 (GXBB)
datasheets, as well as by reading (various versions of) the vendor
driver and by inspecting the registers on the vendor kernels of my
testing-hardware.
Typical use-cases for the ADC on the Meson GX SoCs are:
- adc-keys ("ADC attached resistor ladder buttons")
- SoC temperature measurement (not supported by this driver yet as
the system firmware does this already and provides the values via the
SCPI protocol)
- "version-strapping" (different resistor values are used to indicate
the board-revision)
- and of course typical ADC measurements
Thanks to Heiner Kallweit, Jonathan Cameron and Lars-Peter Clausen for
reviewing this series and providing valuable input!
Changes since v1 (all changes are for patch #3, except where noted):
- fix IRQ number in meson-gx.dtsi (thanks to Heiner Kallweit for
providing the correct value), affects patch #4
- move the most used members of meson_saradc_priv to the beginning
- remove unused struct member "completion" from meson_saradc_priv
- use devm_kasprintf() instead of snprintf() + devm_kstrdup()
- initialize indio_dev->dev.parent earlier in meson_saradc_probe()
- moved meson_saradc_clear_fifo() logic to a separate function
- add comment why a do ... while loop is required in
meson_saradc_wait_busy_clear()
- remove SAR_ADC_NUM_CHANNELS and SAR_ADC_VALUE_MASK macros (each of them
was only used once and it's an unneeded level of abstraction)
- fixed multiline comment syntax violations
- dropped unneeded log messages during initialization
- set iio_dev name to "meson-gxbb-saradc" or "meson-gxl-saradc"
- use "indio_dev->dev.parent" in all kernel log calls (dev_warn/err/etc)
to make it show the OF node name (instead of the iio device name)
- introduce struct meson_saradc_data to hold platform-specific
information (such as resolution in bits and the iio_dev name)
Martin Blumenstingl (4):
Documentation: dt-bindings: add the Amlogic Meson SAR ADC
documentation
clk: gxbb: add the SAR ADC clocks and expose them
iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
ARM64: dts: meson: meson-gx: add the SAR ADC
.../bindings/iio/adc/amlogic,meson-saradc.txt | 31 +
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 +
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 +
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 +
drivers/clk/meson/gxbb.c | 48 ++
drivers/clk/meson/gxbb.h | 9 +-
drivers/iio/adc/Kconfig | 12 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/meson_saradc.c | 893 +++++++++++++++++++++
include/dt-bindings/clock/gxbb-clkc.h | 4 +
10 files changed, 1023 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
create mode 100644 drivers/iio/adc/meson_saradc.c
--
2.11.0
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v2 0/4] Amlogic Meson SAR ADC support
@ 2017-01-15 22:42 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-15 22:42 UTC (permalink / raw)
To: jic23, knaack.h, lars, pmeerw, robh+dt, mark.rutland, khilman,
linux-iio, devicetree, linux-amlogic, linux-clk
Cc: carlo, catalin.marinas, will.deacon, mturquette, sboyd,
narmstrong, linux-arm-kernel, Martin Blumenstingl
This series add support for the SAR ADC on Amlogic Meson GXBB, GXL and
GXM SoCs.
The hardware on GXBB provides 10-bit ADC results, while GXL and GXM are
providing 12-bit results. Support for older SoCs (Meson8b and Meson8)
can be added with little effort, most of which is testing I guess (I
don't have any pre-GXBB hardware so I can't say).
A new set of clocks had to be added to the GXBB clock controller (used
by the GXBB/GXL/GXM SoCs) which are required to get the ADC working.
The ADC itself can sample multiple channels at the same time and allows
capturing multiple samples (which can be used for filtering/averaging).
The ADC results are stored inside a FIFO register. More details on what
the driver supports (or doesn't) can be found in the description of
patch #3.
The code is based on the public S805 (Meson8b) and S905 (GXBB)
datasheets, as well as by reading (various versions of) the vendor
driver and by inspecting the registers on the vendor kernels of my
testing-hardware.
Typical use-cases for the ADC on the Meson GX SoCs are:
- adc-keys ("ADC attached resistor ladder buttons")
- SoC temperature measurement (not supported by this driver yet as
the system firmware does this already and provides the values via the
SCPI protocol)
- "version-strapping" (different resistor values are used to indicate
the board-revision)
- and of course typical ADC measurements
Thanks to Heiner Kallweit, Jonathan Cameron and Lars-Peter Clausen for
reviewing this series and providing valuable input!
Changes since v1 (all changes are for patch #3, except where noted):
- fix IRQ number in meson-gx.dtsi (thanks to Heiner Kallweit for
providing the correct value), affects patch #4
- move the most used members of meson_saradc_priv to the beginning
- remove unused struct member "completion" from meson_saradc_priv
- use devm_kasprintf() instead of snprintf() + devm_kstrdup()
- initialize indio_dev->dev.parent earlier in meson_saradc_probe()
- moved meson_saradc_clear_fifo() logic to a separate function
- add comment why a do ... while loop is required in
meson_saradc_wait_busy_clear()
- remove SAR_ADC_NUM_CHANNELS and SAR_ADC_VALUE_MASK macros (each of them
was only used once and it's an unneeded level of abstraction)
- fixed multiline comment syntax violations
- dropped unneeded log messages during initialization
- set iio_dev name to "meson-gxbb-saradc" or "meson-gxl-saradc"
- use "indio_dev->dev.parent" in all kernel log calls (dev_warn/err/etc)
to make it show the OF node name (instead of the iio device name)
- introduce struct meson_saradc_data to hold platform-specific
information (such as resolution in bits and the iio_dev name)
Martin Blumenstingl (4):
Documentation: dt-bindings: add the Amlogic Meson SAR ADC
documentation
clk: gxbb: add the SAR ADC clocks and expose them
iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
ARM64: dts: meson: meson-gx: add the SAR ADC
.../bindings/iio/adc/amlogic,meson-saradc.txt | 31 +
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 +
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 +
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 +
drivers/clk/meson/gxbb.c | 48 ++
drivers/clk/meson/gxbb.h | 9 +-
drivers/iio/adc/Kconfig | 12 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/meson_saradc.c | 893 +++++++++++++++++++++
include/dt-bindings/clock/gxbb-clkc.h | 4 +
10 files changed, 1023 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
create mode 100644 drivers/iio/adc/meson_saradc.c
--
2.11.0
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v2 0/4] Amlogic Meson SAR ADC support
@ 2017-01-15 22:42 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-15 22:42 UTC (permalink / raw)
To: linux-arm-kernel
This series add support for the SAR ADC on Amlogic Meson GXBB, GXL and
GXM SoCs.
The hardware on GXBB provides 10-bit ADC results, while GXL and GXM are
providing 12-bit results. Support for older SoCs (Meson8b and Meson8)
can be added with little effort, most of which is testing I guess (I
don't have any pre-GXBB hardware so I can't say).
A new set of clocks had to be added to the GXBB clock controller (used
by the GXBB/GXL/GXM SoCs) which are required to get the ADC working.
The ADC itself can sample multiple channels at the same time and allows
capturing multiple samples (which can be used for filtering/averaging).
The ADC results are stored inside a FIFO register. More details on what
the driver supports (or doesn't) can be found in the description of
patch #3.
The code is based on the public S805 (Meson8b) and S905 (GXBB)
datasheets, as well as by reading (various versions of) the vendor
driver and by inspecting the registers on the vendor kernels of my
testing-hardware.
Typical use-cases for the ADC on the Meson GX SoCs are:
- adc-keys ("ADC attached resistor ladder buttons")
- SoC temperature measurement (not supported by this driver yet as
the system firmware does this already and provides the values via the
SCPI protocol)
- "version-strapping" (different resistor values are used to indicate
the board-revision)
- and of course typical ADC measurements
Thanks to Heiner Kallweit, Jonathan Cameron and Lars-Peter Clausen for
reviewing this series and providing valuable input!
Changes since v1 (all changes are for patch #3, except where noted):
- fix IRQ number in meson-gx.dtsi (thanks to Heiner Kallweit for
providing the correct value), affects patch #4
- move the most used members of meson_saradc_priv to the beginning
- remove unused struct member "completion" from meson_saradc_priv
- use devm_kasprintf() instead of snprintf() + devm_kstrdup()
- initialize indio_dev->dev.parent earlier in meson_saradc_probe()
- moved meson_saradc_clear_fifo() logic to a separate function
- add comment why a do ... while loop is required in
meson_saradc_wait_busy_clear()
- remove SAR_ADC_NUM_CHANNELS and SAR_ADC_VALUE_MASK macros (each of them
was only used once and it's an unneeded level of abstraction)
- fixed multiline comment syntax violations
- dropped unneeded log messages during initialization
- set iio_dev name to "meson-gxbb-saradc" or "meson-gxl-saradc"
- use "indio_dev->dev.parent" in all kernel log calls (dev_warn/err/etc)
to make it show the OF node name (instead of the iio device name)
- introduce struct meson_saradc_data to hold platform-specific
information (such as resolution in bits and the iio_dev name)
Martin Blumenstingl (4):
Documentation: dt-bindings: add the Amlogic Meson SAR ADC
documentation
clk: gxbb: add the SAR ADC clocks and expose them
iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
ARM64: dts: meson: meson-gx: add the SAR ADC
.../bindings/iio/adc/amlogic,meson-saradc.txt | 31 +
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 +
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 +
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 +
drivers/clk/meson/gxbb.c | 48 ++
drivers/clk/meson/gxbb.h | 9 +-
drivers/iio/adc/Kconfig | 12 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/meson_saradc.c | 893 +++++++++++++++++++++
include/dt-bindings/clock/gxbb-clkc.h | 4 +
10 files changed, 1023 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
create mode 100644 drivers/iio/adc/meson_saradc.c
--
2.11.0
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v2 0/4] Amlogic Meson SAR ADC support
@ 2017-01-15 22:42 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-15 22:42 UTC (permalink / raw)
To: linus-amlogic
This series add support for the SAR ADC on Amlogic Meson GXBB, GXL and
GXM SoCs.
The hardware on GXBB provides 10-bit ADC results, while GXL and GXM are
providing 12-bit results. Support for older SoCs (Meson8b and Meson8)
can be added with little effort, most of which is testing I guess (I
don't have any pre-GXBB hardware so I can't say).
A new set of clocks had to be added to the GXBB clock controller (used
by the GXBB/GXL/GXM SoCs) which are required to get the ADC working.
The ADC itself can sample multiple channels at the same time and allows
capturing multiple samples (which can be used for filtering/averaging).
The ADC results are stored inside a FIFO register. More details on what
the driver supports (or doesn't) can be found in the description of
patch #3.
The code is based on the public S805 (Meson8b) and S905 (GXBB)
datasheets, as well as by reading (various versions of) the vendor
driver and by inspecting the registers on the vendor kernels of my
testing-hardware.
Typical use-cases for the ADC on the Meson GX SoCs are:
- adc-keys ("ADC attached resistor ladder buttons")
- SoC temperature measurement (not supported by this driver yet as
the system firmware does this already and provides the values via the
SCPI protocol)
- "version-strapping" (different resistor values are used to indicate
the board-revision)
- and of course typical ADC measurements
Thanks to Heiner Kallweit, Jonathan Cameron and Lars-Peter Clausen for
reviewing this series and providing valuable input!
Changes since v1 (all changes are for patch #3, except where noted):
- fix IRQ number in meson-gx.dtsi (thanks to Heiner Kallweit for
providing the correct value), affects patch #4
- move the most used members of meson_saradc_priv to the beginning
- remove unused struct member "completion" from meson_saradc_priv
- use devm_kasprintf() instead of snprintf() + devm_kstrdup()
- initialize indio_dev->dev.parent earlier in meson_saradc_probe()
- moved meson_saradc_clear_fifo() logic to a separate function
- add comment why a do ... while loop is required in
meson_saradc_wait_busy_clear()
- remove SAR_ADC_NUM_CHANNELS and SAR_ADC_VALUE_MASK macros (each of them
was only used once and it's an unneeded level of abstraction)
- fixed multiline comment syntax violations
- dropped unneeded log messages during initialization
- set iio_dev name to "meson-gxbb-saradc" or "meson-gxl-saradc"
- use "indio_dev->dev.parent" in all kernel log calls (dev_warn/err/etc)
to make it show the OF node name (instead of the iio device name)
- introduce struct meson_saradc_data to hold platform-specific
information (such as resolution in bits and the iio_dev name)
Martin Blumenstingl (4):
Documentation: dt-bindings: add the Amlogic Meson SAR ADC
documentation
clk: gxbb: add the SAR ADC clocks and expose them
iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
ARM64: dts: meson: meson-gx: add the SAR ADC
.../bindings/iio/adc/amlogic,meson-saradc.txt | 31 +
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 +
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 +
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 +
drivers/clk/meson/gxbb.c | 48 ++
drivers/clk/meson/gxbb.h | 9 +-
drivers/iio/adc/Kconfig | 12 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/meson_saradc.c | 893 +++++++++++++++++++++
include/dt-bindings/clock/gxbb-clkc.h | 4 +
10 files changed, 1023 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
create mode 100644 drivers/iio/adc/meson_saradc.c
--
2.11.0
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v2 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
2017-01-15 22:42 ` Martin Blumenstingl
(?)
(?)
@ 2017-01-15 22:42 ` Martin Blumenstingl
-1 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-15 22:42 UTC (permalink / raw)
To: jic23-DgEjT+Ai2ygdnm+yROfE0A, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
khilman-rdvid1DuHRBWk0Htik3J/w, linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-clk-u79uwXL29TY76Z2rM5mHXA
Cc: carlo-KA+7E9HrN00dnm+yROfE0A, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, mturquette-rdvid1DuHRBWk0Htik3J/w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, narmstrong-rdvid1DuHRBWk0Htik3J/w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Martin Blumenstingl
This adds the devicetree binding documentation for the SAR ADC found in
Amlogic Meson SoCs.
Currently only the GXBB, GXL and GXM SoCs are supported.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
.../bindings/iio/adc/amlogic,meson-saradc.txt | 31 ++++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
new file mode 100644
index 000000000000..9a0bec7afc63
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
@@ -0,0 +1,31 @@
+* Amlogic Meson SAR (Successive Approximation Register) A/D converter
+
+Required properties:
+- compatible: depending on the SoC this should be one of:
+ - "amlogic,meson-gxbb-saradc" for GXBB
+ - "amlogic,meson-gxl-saradc" for GXL and GXM
+ along with the generic "amlogic,meson-saradc"
+- reg: the physical base address and length of the registers
+- clocks: phandle and clock identifier (see clock-names)
+- clock-names: mandatory clocks:
+ - "clkin" for the reference clock (typically XTAL)
+ - "core" for the SAR ADC core clock
+ optional clocks:
+ - "sana" for the analog clock
+ - "adc_clk" for the ADC (sampling) clock
+ - "adc_sel" for the ADC (sampling) clock mux
+- vref-supply: the regulator supply for the ADC reference voltage
+- #io-channel-cells: must be 1, see ../iio-bindings.txt
+
+Example:
+ saradc: adc@8680 {
+ compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
+ #io-channel-cells = <1>;
+ reg = <0x0 0x8680 0x0 0x34>;
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+ };
--
2.11.0
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
@ 2017-01-15 22:42 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-15 22:42 UTC (permalink / raw)
To: jic23, knaack.h, lars, pmeerw, robh+dt, mark.rutland, khilman,
linux-iio, devicetree, linux-amlogic, linux-clk
Cc: carlo, catalin.marinas, will.deacon, mturquette, sboyd,
narmstrong, linux-arm-kernel, Martin Blumenstingl
This adds the devicetree binding documentation for the SAR ADC found in
Amlogic Meson SoCs.
Currently only the GXBB, GXL and GXM SoCs are supported.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
.../bindings/iio/adc/amlogic,meson-saradc.txt | 31 ++++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
new file mode 100644
index 000000000000..9a0bec7afc63
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
@@ -0,0 +1,31 @@
+* Amlogic Meson SAR (Successive Approximation Register) A/D converter
+
+Required properties:
+- compatible: depending on the SoC this should be one of:
+ - "amlogic,meson-gxbb-saradc" for GXBB
+ - "amlogic,meson-gxl-saradc" for GXL and GXM
+ along with the generic "amlogic,meson-saradc"
+- reg: the physical base address and length of the registers
+- clocks: phandle and clock identifier (see clock-names)
+- clock-names: mandatory clocks:
+ - "clkin" for the reference clock (typically XTAL)
+ - "core" for the SAR ADC core clock
+ optional clocks:
+ - "sana" for the analog clock
+ - "adc_clk" for the ADC (sampling) clock
+ - "adc_sel" for the ADC (sampling) clock mux
+- vref-supply: the regulator supply for the ADC reference voltage
+- #io-channel-cells: must be 1, see ../iio-bindings.txt
+
+Example:
+ saradc: adc@8680 {
+ compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
+ #io-channel-cells = <1>;
+ reg = <0x0 0x8680 0x0 0x34>;
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+ };
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
@ 2017-01-15 22:42 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-15 22:42 UTC (permalink / raw)
To: linux-arm-kernel
This adds the devicetree binding documentation for the SAR ADC found in
Amlogic Meson SoCs.
Currently only the GXBB, GXL and GXM SoCs are supported.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
.../bindings/iio/adc/amlogic,meson-saradc.txt | 31 ++++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
new file mode 100644
index 000000000000..9a0bec7afc63
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
@@ -0,0 +1,31 @@
+* Amlogic Meson SAR (Successive Approximation Register) A/D converter
+
+Required properties:
+- compatible: depending on the SoC this should be one of:
+ - "amlogic,meson-gxbb-saradc" for GXBB
+ - "amlogic,meson-gxl-saradc" for GXL and GXM
+ along with the generic "amlogic,meson-saradc"
+- reg: the physical base address and length of the registers
+- clocks: phandle and clock identifier (see clock-names)
+- clock-names: mandatory clocks:
+ - "clkin" for the reference clock (typically XTAL)
+ - "core" for the SAR ADC core clock
+ optional clocks:
+ - "sana" for the analog clock
+ - "adc_clk" for the ADC (sampling) clock
+ - "adc_sel" for the ADC (sampling) clock mux
+- vref-supply: the regulator supply for the ADC reference voltage
+- #io-channel-cells: must be 1, see ../iio-bindings.txt
+
+Example:
+ saradc: adc at 8680 {
+ compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
+ #io-channel-cells = <1>;
+ reg = <0x0 0x8680 0x0 0x34>;
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+ };
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
@ 2017-01-15 22:42 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-15 22:42 UTC (permalink / raw)
To: linus-amlogic
This adds the devicetree binding documentation for the SAR ADC found in
Amlogic Meson SoCs.
Currently only the GXBB, GXL and GXM SoCs are supported.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
.../bindings/iio/adc/amlogic,meson-saradc.txt | 31 ++++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
new file mode 100644
index 000000000000..9a0bec7afc63
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
@@ -0,0 +1,31 @@
+* Amlogic Meson SAR (Successive Approximation Register) A/D converter
+
+Required properties:
+- compatible: depending on the SoC this should be one of:
+ - "amlogic,meson-gxbb-saradc" for GXBB
+ - "amlogic,meson-gxl-saradc" for GXL and GXM
+ along with the generic "amlogic,meson-saradc"
+- reg: the physical base address and length of the registers
+- clocks: phandle and clock identifier (see clock-names)
+- clock-names: mandatory clocks:
+ - "clkin" for the reference clock (typically XTAL)
+ - "core" for the SAR ADC core clock
+ optional clocks:
+ - "sana" for the analog clock
+ - "adc_clk" for the ADC (sampling) clock
+ - "adc_sel" for the ADC (sampling) clock mux
+- vref-supply: the regulator supply for the ADC reference voltage
+- #io-channel-cells: must be 1, see ../iio-bindings.txt
+
+Example:
+ saradc: adc at 8680 {
+ compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
+ #io-channel-cells = <1>;
+ reg = <0x0 0x8680 0x0 0x34>;
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+ };
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 2/4] clk: gxbb: add the SAR ADC clocks and expose them
2017-01-15 22:42 ` Martin Blumenstingl
(?)
@ 2017-01-15 22:42 ` Martin Blumenstingl
-1 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-15 22:42 UTC (permalink / raw)
To: jic23, knaack.h, lars, pmeerw, robh+dt, mark.rutland, khilman,
linux-iio, devicetree, linux-amlogic, linux-clk
Cc: carlo, catalin.marinas, will.deacon, mturquette, sboyd,
narmstrong, linux-arm-kernel, Martin Blumenstingl
The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
- a mux clock to choose between different ADC reference clocks (this is
2-bit wide, but the datasheet only lists the parents for the first
bit)
- a divider for the input/reference clock
- a gate which enables the ADC clock
Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
CLKID_SANA (which seems to enable the analog inputs, but unfortunately
there is no documentation for this - we just mimic what the vendor
driver does).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/clk/meson/gxbb.c | 48 +++++++++++++++++++++++++++++++++++
drivers/clk/meson/gxbb.h | 9 ++++---
include/dt-bindings/clock/gxbb-clkc.h | 4 +++
3 files changed, 58 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 9d9af446bafc..1c1ec137a3cc 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -564,6 +564,46 @@ static struct clk_gate gxbb_clk81 = {
},
};
+static struct clk_mux gxbb_sar_adc_clk_sel = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .mask = 0x3,
+ .shift = 9,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk_sel",
+ .ops = &clk_mux_ops,
+ /* NOTE: The datasheet doesn't list the parents for bit 10 */
+ .parent_names = (const char *[]){ "xtal", "clk81", },
+ .num_parents = 2,
+ },
+};
+
+static struct clk_divider gxbb_sar_adc_clk_div = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .shift = 0,
+ .width = 8,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk_div",
+ .ops = &clk_divider_ops,
+ .parent_names = (const char *[]){ "sar_adc_clk_sel" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_gate gxbb_sar_adc_clk = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .bit_idx = 8,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk",
+ .ops = &clk_gate_ops,
+ .parent_names = (const char *[]){ "sar_adc_clk_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
/* Everything Else (EE) domain gates */
static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -754,6 +794,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
[CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
[CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
[CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
+ [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
+ [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
+ [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
},
.num = NR_CLKS,
};
@@ -856,6 +899,7 @@ static struct clk_gate *gxbb_clk_gates[] = {
&gxbb_emmc_a,
&gxbb_emmc_b,
&gxbb_emmc_c,
+ &gxbb_sar_adc_clk,
};
static int gxbb_clkc_probe(struct platform_device *pdev)
@@ -888,6 +932,10 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
gxbb_mpeg_clk_sel.reg = clk_base + (u64)gxbb_mpeg_clk_sel.reg;
gxbb_mpeg_clk_div.reg = clk_base + (u64)gxbb_mpeg_clk_div.reg;
+ /* Populate the base address for the SAR ADC clks */
+ gxbb_sar_adc_clk_sel.reg = clk_base + (u64)gxbb_sar_adc_clk_sel.reg;
+ gxbb_sar_adc_clk_div.reg = clk_base + (u64)gxbb_sar_adc_clk_div.reg;
+
/* Populate base address for gates */
for (i = 0; i < ARRAY_SIZE(gxbb_clk_gates); i++)
gxbb_clk_gates[i]->reg = clk_base +
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 0252939ba58f..d90052d74abd 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -191,7 +191,7 @@
#define CLKID_PERIPHS 20
#define CLKID_SPICC 21
/* CLKID_I2C */
-#define CLKID_SAR_ADC 23
+/* #define CLKID_SAR_ADC */
#define CLKID_SMART_CARD 24
#define CLKID_RNG0 25
#define CLKID_UART0 26
@@ -237,7 +237,7 @@
#define CLKID_MMC_PCLK 66
#define CLKID_DVIN 67
#define CLKID_UART2 68
-#define CLKID_SANA 69
+/* #define CLKID_SANA */
#define CLKID_VPU_INTR 70
#define CLKID_SEC_AHB_AHB3_BRIDGE 71
#define CLKID_CLK81_A53 72
@@ -265,8 +265,11 @@
/* CLKID_SD_EMMC_A */
/* CLKID_SD_EMMC_B */
/* CLKID_SD_EMMC_C */
+/* CLKID_SAR_ADC_CLK */
+/* CLKID_SAR_ADC_SEL */
+#define CLKID_SAR_ADC_DIV 99
-#define NR_CLKS 97
+#define NR_CLKS 100
/* include the CLKIDs that have been made part of the stable DT binding */
#include <dt-bindings/clock/gxbb-clkc.h>
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index baade6f429d0..c2e93676010d 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -14,15 +14,19 @@
#define CLKID_MPLL2 15
#define CLKID_SPI 34
#define CLKID_I2C 22
+#define CLKID_SAR_ADC 23
#define CLKID_ETH 36
#define CLKID_USB0 50
#define CLKID_USB1 51
#define CLKID_USB 55
#define CLKID_USB1_DDR_BRIDGE 64
#define CLKID_USB0_DDR_BRIDGE 65
+#define CLKID_SANA 69
#define CLKID_AO_I2C 93
#define CLKID_SD_EMMC_A 94
#define CLKID_SD_EMMC_B 95
#define CLKID_SD_EMMC_C 96
+#define CLKID_SAR_ADC_CLK 97
+#define CLKID_SAR_ADC_SEL 98
#endif /* __GXBB_CLKC_H */
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 2/4] clk: gxbb: add the SAR ADC clocks and expose them
@ 2017-01-15 22:42 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-15 22:42 UTC (permalink / raw)
To: linux-arm-kernel
The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
- a mux clock to choose between different ADC reference clocks (this is
2-bit wide, but the datasheet only lists the parents for the first
bit)
- a divider for the input/reference clock
- a gate which enables the ADC clock
Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
CLKID_SANA (which seems to enable the analog inputs, but unfortunately
there is no documentation for this - we just mimic what the vendor
driver does).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/clk/meson/gxbb.c | 48 +++++++++++++++++++++++++++++++++++
drivers/clk/meson/gxbb.h | 9 ++++---
include/dt-bindings/clock/gxbb-clkc.h | 4 +++
3 files changed, 58 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 9d9af446bafc..1c1ec137a3cc 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -564,6 +564,46 @@ static struct clk_gate gxbb_clk81 = {
},
};
+static struct clk_mux gxbb_sar_adc_clk_sel = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .mask = 0x3,
+ .shift = 9,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk_sel",
+ .ops = &clk_mux_ops,
+ /* NOTE: The datasheet doesn't list the parents for bit 10 */
+ .parent_names = (const char *[]){ "xtal", "clk81", },
+ .num_parents = 2,
+ },
+};
+
+static struct clk_divider gxbb_sar_adc_clk_div = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .shift = 0,
+ .width = 8,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk_div",
+ .ops = &clk_divider_ops,
+ .parent_names = (const char *[]){ "sar_adc_clk_sel" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_gate gxbb_sar_adc_clk = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .bit_idx = 8,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk",
+ .ops = &clk_gate_ops,
+ .parent_names = (const char *[]){ "sar_adc_clk_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
/* Everything Else (EE) domain gates */
static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -754,6 +794,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
[CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
[CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
[CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
+ [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
+ [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
+ [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
},
.num = NR_CLKS,
};
@@ -856,6 +899,7 @@ static struct clk_gate *gxbb_clk_gates[] = {
&gxbb_emmc_a,
&gxbb_emmc_b,
&gxbb_emmc_c,
+ &gxbb_sar_adc_clk,
};
static int gxbb_clkc_probe(struct platform_device *pdev)
@@ -888,6 +932,10 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
gxbb_mpeg_clk_sel.reg = clk_base + (u64)gxbb_mpeg_clk_sel.reg;
gxbb_mpeg_clk_div.reg = clk_base + (u64)gxbb_mpeg_clk_div.reg;
+ /* Populate the base address for the SAR ADC clks */
+ gxbb_sar_adc_clk_sel.reg = clk_base + (u64)gxbb_sar_adc_clk_sel.reg;
+ gxbb_sar_adc_clk_div.reg = clk_base + (u64)gxbb_sar_adc_clk_div.reg;
+
/* Populate base address for gates */
for (i = 0; i < ARRAY_SIZE(gxbb_clk_gates); i++)
gxbb_clk_gates[i]->reg = clk_base +
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 0252939ba58f..d90052d74abd 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -191,7 +191,7 @@
#define CLKID_PERIPHS 20
#define CLKID_SPICC 21
/* CLKID_I2C */
-#define CLKID_SAR_ADC 23
+/* #define CLKID_SAR_ADC */
#define CLKID_SMART_CARD 24
#define CLKID_RNG0 25
#define CLKID_UART0 26
@@ -237,7 +237,7 @@
#define CLKID_MMC_PCLK 66
#define CLKID_DVIN 67
#define CLKID_UART2 68
-#define CLKID_SANA 69
+/* #define CLKID_SANA */
#define CLKID_VPU_INTR 70
#define CLKID_SEC_AHB_AHB3_BRIDGE 71
#define CLKID_CLK81_A53 72
@@ -265,8 +265,11 @@
/* CLKID_SD_EMMC_A */
/* CLKID_SD_EMMC_B */
/* CLKID_SD_EMMC_C */
+/* CLKID_SAR_ADC_CLK */
+/* CLKID_SAR_ADC_SEL */
+#define CLKID_SAR_ADC_DIV 99
-#define NR_CLKS 97
+#define NR_CLKS 100
/* include the CLKIDs that have been made part of the stable DT binding */
#include <dt-bindings/clock/gxbb-clkc.h>
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index baade6f429d0..c2e93676010d 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -14,15 +14,19 @@
#define CLKID_MPLL2 15
#define CLKID_SPI 34
#define CLKID_I2C 22
+#define CLKID_SAR_ADC 23
#define CLKID_ETH 36
#define CLKID_USB0 50
#define CLKID_USB1 51
#define CLKID_USB 55
#define CLKID_USB1_DDR_BRIDGE 64
#define CLKID_USB0_DDR_BRIDGE 65
+#define CLKID_SANA 69
#define CLKID_AO_I2C 93
#define CLKID_SD_EMMC_A 94
#define CLKID_SD_EMMC_B 95
#define CLKID_SD_EMMC_C 96
+#define CLKID_SAR_ADC_CLK 97
+#define CLKID_SAR_ADC_SEL 98
#endif /* __GXBB_CLKC_H */
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 2/4] clk: gxbb: add the SAR ADC clocks and expose them
@ 2017-01-15 22:42 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-15 22:42 UTC (permalink / raw)
To: linus-amlogic
The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
- a mux clock to choose between different ADC reference clocks (this is
2-bit wide, but the datasheet only lists the parents for the first
bit)
- a divider for the input/reference clock
- a gate which enables the ADC clock
Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
CLKID_SANA (which seems to enable the analog inputs, but unfortunately
there is no documentation for this - we just mimic what the vendor
driver does).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/clk/meson/gxbb.c | 48 +++++++++++++++++++++++++++++++++++
drivers/clk/meson/gxbb.h | 9 ++++---
include/dt-bindings/clock/gxbb-clkc.h | 4 +++
3 files changed, 58 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 9d9af446bafc..1c1ec137a3cc 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -564,6 +564,46 @@ static struct clk_gate gxbb_clk81 = {
},
};
+static struct clk_mux gxbb_sar_adc_clk_sel = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .mask = 0x3,
+ .shift = 9,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk_sel",
+ .ops = &clk_mux_ops,
+ /* NOTE: The datasheet doesn't list the parents for bit 10 */
+ .parent_names = (const char *[]){ "xtal", "clk81", },
+ .num_parents = 2,
+ },
+};
+
+static struct clk_divider gxbb_sar_adc_clk_div = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .shift = 0,
+ .width = 8,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk_div",
+ .ops = &clk_divider_ops,
+ .parent_names = (const char *[]){ "sar_adc_clk_sel" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_gate gxbb_sar_adc_clk = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .bit_idx = 8,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk",
+ .ops = &clk_gate_ops,
+ .parent_names = (const char *[]){ "sar_adc_clk_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
/* Everything Else (EE) domain gates */
static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -754,6 +794,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
[CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
[CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
[CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
+ [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
+ [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
+ [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
},
.num = NR_CLKS,
};
@@ -856,6 +899,7 @@ static struct clk_gate *gxbb_clk_gates[] = {
&gxbb_emmc_a,
&gxbb_emmc_b,
&gxbb_emmc_c,
+ &gxbb_sar_adc_clk,
};
static int gxbb_clkc_probe(struct platform_device *pdev)
@@ -888,6 +932,10 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
gxbb_mpeg_clk_sel.reg = clk_base + (u64)gxbb_mpeg_clk_sel.reg;
gxbb_mpeg_clk_div.reg = clk_base + (u64)gxbb_mpeg_clk_div.reg;
+ /* Populate the base address for the SAR ADC clks */
+ gxbb_sar_adc_clk_sel.reg = clk_base + (u64)gxbb_sar_adc_clk_sel.reg;
+ gxbb_sar_adc_clk_div.reg = clk_base + (u64)gxbb_sar_adc_clk_div.reg;
+
/* Populate base address for gates */
for (i = 0; i < ARRAY_SIZE(gxbb_clk_gates); i++)
gxbb_clk_gates[i]->reg = clk_base +
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 0252939ba58f..d90052d74abd 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -191,7 +191,7 @@
#define CLKID_PERIPHS 20
#define CLKID_SPICC 21
/* CLKID_I2C */
-#define CLKID_SAR_ADC 23
+/* #define CLKID_SAR_ADC */
#define CLKID_SMART_CARD 24
#define CLKID_RNG0 25
#define CLKID_UART0 26
@@ -237,7 +237,7 @@
#define CLKID_MMC_PCLK 66
#define CLKID_DVIN 67
#define CLKID_UART2 68
-#define CLKID_SANA 69
+/* #define CLKID_SANA */
#define CLKID_VPU_INTR 70
#define CLKID_SEC_AHB_AHB3_BRIDGE 71
#define CLKID_CLK81_A53 72
@@ -265,8 +265,11 @@
/* CLKID_SD_EMMC_A */
/* CLKID_SD_EMMC_B */
/* CLKID_SD_EMMC_C */
+/* CLKID_SAR_ADC_CLK */
+/* CLKID_SAR_ADC_SEL */
+#define CLKID_SAR_ADC_DIV 99
-#define NR_CLKS 97
+#define NR_CLKS 100
/* include the CLKIDs that have been made part of the stable DT binding */
#include <dt-bindings/clock/gxbb-clkc.h>
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index baade6f429d0..c2e93676010d 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -14,15 +14,19 @@
#define CLKID_MPLL2 15
#define CLKID_SPI 34
#define CLKID_I2C 22
+#define CLKID_SAR_ADC 23
#define CLKID_ETH 36
#define CLKID_USB0 50
#define CLKID_USB1 51
#define CLKID_USB 55
#define CLKID_USB1_DDR_BRIDGE 64
#define CLKID_USB0_DDR_BRIDGE 65
+#define CLKID_SANA 69
#define CLKID_AO_I2C 93
#define CLKID_SD_EMMC_A 94
#define CLKID_SD_EMMC_B 95
#define CLKID_SD_EMMC_C 96
+#define CLKID_SAR_ADC_CLK 97
+#define CLKID_SAR_ADC_SEL 98
#endif /* __GXBB_CLKC_H */
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
2017-01-15 22:42 ` Martin Blumenstingl
(?)
(?)
@ 2017-01-15 22:42 ` Martin Blumenstingl
-1 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-15 22:42 UTC (permalink / raw)
To: jic23-DgEjT+Ai2ygdnm+yROfE0A, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
khilman-rdvid1DuHRBWk0Htik3J/w, linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-clk-u79uwXL29TY76Z2rM5mHXA
Cc: carlo-KA+7E9HrN00dnm+yROfE0A, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, mturquette-rdvid1DuHRBWk0Htik3J/w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, narmstrong-rdvid1DuHRBWk0Htik3J/w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Martin Blumenstingl
This adds support for the SAR (Successive Approximation Register) ADC
on the Amlogic Meson SoCs.
The code is based on the public S805 (Meson8b) and S905 (GXBB)
datasheets (see [0] and [1]), as well as by reading (various versions
of) the vendor driver and by inspecting the registers on the vendor
kernels of my testing-hardware.
Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
The code was written to support older SoCs (Meson8 and Meson8b) as well,
but due to lack of actual testing-hardware no of_device_id was added for
these.
Two "features" from the vendor driver are currently missing:
- the vendor driver uses channel #7 for calibration (this improves the
accuracy of the results - in my tests the results were less than 3%
off without calibration compared to the vendor driver). Adding support
for this should be easy, but is not required for most applications.
- channel #6 is connected to the SoCs internal temperature sensor.
Adding support for this is probably not so easy since (based on the
u-boot sources) most SoC versions are using different registers and
algorithms for the conversion from "ADC value" to temperature.
Supported by the hardware but currently not supported by the driver:
- reading multiple channels at the same time (the hardware has a FIFO
buffer which stores multiple results)
- continuous sampling (this would require a way to enable this
individually because otherwise the ADC would be drawing power
constantly)
- interrupt support (similar to the vendor driver this new driver is
polling the results. It is unclear if the IRQ-mode is supported on
older (Meson6 or Meson8) hardware as well or if there are any errata)
[0]
http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
[1] http://dn.odroid.com/S905/DataSheet/S905_Public_Datasheet_V1.1.4.pdf
Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
drivers/iio/adc/Kconfig | 12 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/meson_saradc.c | 893 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 906 insertions(+)
create mode 100644 drivers/iio/adc/meson_saradc.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 9c8b558ba19e..86059b9b91bf 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -371,6 +371,18 @@ config MEN_Z188_ADC
This driver can also be built as a module. If so, the module will be
called men_z188_adc.
+config MESON_SARADC
+ tristate "Amlogic Meson SAR ADC driver"
+ default ARCH_MESON
+ depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
+ select REGMAP_MMIO
+ help
+ Say yes here to build support for the SAR ADC found in Amlogic Meson
+ SoCs.
+
+ To compile this driver as a module, choose M here: the
+ module will be called meson_saradc.
+
config MXS_LRADC
tristate "Freescale i.MX23/i.MX28 LRADC"
depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index d36c4be8d1fc..de05b9e75f8f 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
obj-$(CONFIG_MCP3422) += mcp3422.o
obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
+obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
obj-$(CONFIG_NAU7802) += nau7802.o
obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
new file mode 100644
index 000000000000..4c189e5fd7cc
--- /dev/null
+++ b/drivers/iio/adc/meson_saradc.c
@@ -0,0 +1,893 @@
+/*
+ * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
+ *
+ * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/iio/iio.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+
+#define SAR_ADC_REG0 0x00
+ #define SAR_ADC_REG0_PANEL_DETECT BIT(31)
+ #define SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
+ #define SAR_ADC_REG0_DELTA_BUSY BIT(30)
+ #define SAR_ADC_REG0_AVG_BUSY BIT(29)
+ #define SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
+ #define SAR_ADC_REG0_FIFO_FULL BIT(27)
+ #define SAR_ADC_REG0_FIFO_EMPTY BIT(26)
+ #define SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
+ #define SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
+ #define SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
+ #define SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
+ #define SAR_ADC_REG0_SAMPLING_STOP BIT(14)
+ #define SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
+ #define SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
+ #define SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
+ #define SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
+ #define SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
+ #define SAR_ADC_REG0_SAMPLING_START BIT(2)
+ #define SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
+ #define SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
+
+#define SAR_ADC_CHAN_LIST 0x04
+ #define SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
+ #define SAR_ADC_CHAN_CHAN_ENTRY_MASK(_chan) \
+ (GENMASK(2, 0) << (_chan * 3))
+
+#define SAR_ADC_AVG_CNTL 0x08
+ #define SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
+ (16 + (_chan * 2))
+ #define SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
+ (GENMASK(17, 16) << (_chan * 2))
+ #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
+ (0 + (_chan * 2))
+ #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
+ (GENMASK(1, 0) << (_chan * 2))
+
+#define SAR_ADC_REG3 0x0c
+ #define SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
+ #define SAR_ADC_REG3_CLK_EN BIT(30)
+ #define SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
+ #define SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
+ #define SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
+ #define SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
+ #define SAR_ADC_REG3_DETECT_EN BIT(22)
+ #define SAR_ADC_REG3_ADC_EN BIT(21)
+ #define SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
+ #define SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
+ #define SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
+ #define SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
+ #define SAR_ADC_REG3_ADC_CLK_DIV_MASK GENMASK(15, 10)
+ #define SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
+ #define SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
+
+#define SAR_ADC_DELAY 0x10
+ #define SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
+ #define SAR_ADC_DELAY_BL30_BUSY BIT(15)
+ #define SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
+ #define SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
+ #define SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
+ #define SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
+
+#define SAR_ADC_LAST_RD 0x14
+ #define SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
+ #define SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
+
+#define SAR_ADC_FIFO_RD 0x18
+ #define SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
+ #define SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
+
+#define SAR_ADC_AUX_SW 0x1c
+ #define SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
+ (GENMASK(10, 8) << ((_chan - 2) * 2))
+ #define SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
+ #define SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
+ #define SAR_ADC_AUX_SW_MODE_SEL BIT(4)
+ #define SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
+ #define SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
+ #define SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
+ #define SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
+
+#define SAR_ADC_CHAN_10_SW 0x20
+ #define SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
+
+#define SAR_ADC_DETECT_IDLE_SW 0x24
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK GENMASK(25, 23)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_P_MUX BIT(22)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_N_MUX BIT(21)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YP_DRIVE_SW BIT(19)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XP_DRIVE_SW BIT(18)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YM_DRIVE_SW BIT(17)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XM_DRIVE_SW BIT(16)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK GENMASK(9, 7)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_P_MUX BIT(6)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_N_MUX BIT(5)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YP_DRIVE_SW BIT(3)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XP_DRIVE_SW BIT(2)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YM_DRIVE_SW BIT(1)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XM_DRIVE_SW BIT(0)
+
+#define SAR_ADC_DELTA_10 0x28
+ #define SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
+ #define SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
+ #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_SHIFT 16
+ #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
+ #define SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
+ #define SAR_ADC_DELTA_10_TS_C_SHIFT 11
+ #define SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
+ #define SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
+ #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_SHIFT 0
+ #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
+
+/*
+ * NOTE: registers from here are undocumented (the vendor Linux kernel driver
+ * and u-boot source served as reference). These only seem to be relevant on
+ * GXBB and newer.
+ */
+#define SAR_ADC_REG11 0x2c
+ #define SAR_ADC_REG11_BANDGAP_EN BIT(13)
+
+#define SAR_ADC_REG13 0x34
+ #define SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
+
+#define SAR_ADC_MAX_FIFO_SIZE 32
+
+#define MESON_SAR_ADC_CHAN(_chan, _type) { \
+ .type = _type, \
+ .indexed = true, \
+ .channel = _chan, \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
+ BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
+ .datasheet_name = "SAR_ADC_CH"#_chan, \
+}
+
+/*
+ * TODO: the hardware supports IIO_TEMP for channel 6 as well which is
+ * currently not supported by this driver.
+ */
+static const struct iio_chan_spec meson_saradc_iio_channels[] = {
+ MESON_SAR_ADC_CHAN(0, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(1, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(2, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(3, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(4, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(5, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(6, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(7, IIO_VOLTAGE),
+ IIO_CHAN_SOFT_TIMESTAMP(8),
+};
+
+enum meson_saradc_avg_mode {
+ NO_AVERAGING = 0x0,
+ MEAN_AVERAGING = 0x1,
+ MEDIAN_AVERAGING = 0x2,
+};
+
+enum meson_saradc_num_samples {
+ ONE_SAMPLE = 0x0,
+ TWO_SAMPLES = 0x1,
+ FOUR_SAMPLES = 0x2,
+ EIGHT_SAMPLES = 0x3,
+};
+
+enum meson_saradc_chan7_mux_sel {
+ CHAN7_MUX_VSS = 0x0,
+ CHAN7_MUX_VDD_DIV4 = 0x1,
+ CHAN7_MUX_VDD_DIV2 = 0x2,
+ CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
+ CHAN7_MUX_VDD = 0x4,
+ CHAN7_MUX_CH7_INPUT = 0x7,
+};
+
+struct meson_saradc_data {
+ unsigned int resolution;
+ const char *name;
+};
+
+struct meson_saradc_priv {
+ struct regmap *regmap;
+ struct regulator *vref;
+ const struct meson_saradc_data *data;
+ struct clk *clkin;
+ struct clk *core_clk;
+ struct clk *sana_clk;
+ struct clk *adc_sel_clk;
+ struct clk *adc_clk;
+ struct clk_gate clk_gate;
+ struct clk *adc_div_clk;
+ struct clk_divider clk_div;
+};
+
+static const struct regmap_config meson_saradc_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = SAR_ADC_REG13,
+};
+
+static unsigned int meson_saradc_get_fifo_count(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
+
+ return FIELD_GET(SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
+}
+
+static int meson_saradc_wait_busy_clear(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int regval, timeout = 10000;
+
+ /*
+ * NOTE: we need a small delay before reading the status, otherwise
+ * the sample engine may not have started internally (which would
+ * seem to us that sampling is already finished).
+ */
+ do {
+ udelay(1);
+ regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
+ } while (FIELD_GET(SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
+
+ if (timeout < 0)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static int meson_saradc_read_raw_sample(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ int *val)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0;
+
+ ret = meson_saradc_wait_busy_clear(indio_dev);
+ if (ret)
+ return ret;
+
+ while (meson_saradc_get_fifo_count(indio_dev) > 0 &&
+ count < SAR_ADC_MAX_FIFO_SIZE) {
+ regmap_read(priv->regmap, SAR_ADC_FIFO_RD, ®val);
+
+ fifo_chan = FIELD_GET(SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
+ if (fifo_chan == chan->channel) {
+ fifo_val = FIELD_GET(SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK,
+ regval);
+ fifo_val &= (BIT(priv->data->resolution) - 1);
+
+ sum += fifo_val;
+ count++;
+ }
+ }
+
+ if (!count)
+ return -ENOENT;
+
+ *val = sum / count;
+
+ return 0;
+}
+
+static void meson_saradc_set_averaging(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ enum meson_saradc_avg_mode mode,
+ enum meson_saradc_num_samples samples)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 val;
+
+ val = samples << SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
+ SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(chan->channel),
+ val);
+
+ val = mode << SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
+ SAR_ADC_AVG_CNTL_AVG_MODE_MASK(chan->channel), val);
+}
+
+static void meson_saradc_enable_channel(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ /* the SAR ADC engine allows sampling multiple channels at the same
+ * time. to keep it simple we're only working with one *internal*
+ * channel, which starts counting at index 0 (which means: count = 1).
+ */
+ regval = FIELD_PREP(SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
+ regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
+ SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
+
+ /* map channel index 0 to the channel which we want to read */
+ regval = FIELD_PREP(SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
+ SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), regval);
+
+ regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
+ chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
+ SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
+ regval);
+
+ regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
+ chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
+ SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
+ regval);
+
+ if (chan->channel == 6)
+ regmap_update_bits(priv->regmap, SAR_ADC_DELTA_10,
+ SAR_ADC_DELTA_10_TEMP_SEL, 0);
+}
+
+static void meson_saradc_set_channel7_mux(struct iio_dev *indio_dev,
+ enum meson_saradc_chan7_mux_sel sel)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ regval = FIELD_PREP(SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3,
+ SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
+
+ usleep_range(10, 20);
+}
+
+static void meson_saradc_start_sample_engine(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
+ SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLING_START,
+ SAR_ADC_REG0_SAMPLING_START);
+}
+
+static void meson_saradc_stop_sample_engine(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLING_STOP,
+ SAR_ADC_REG0_SAMPLING_STOP);
+
+ /* wait until all modules are stopped */
+ meson_saradc_wait_busy_clear(indio_dev);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
+}
+
+static void meson_saradc_lock(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int val;
+
+ mutex_lock(&indio_dev->mlock);
+
+ /* prevent BL30 from using the SAR ADC while we are using it */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_KERNEL_BUSY,
+ SAR_ADC_DELAY_KERNEL_BUSY);
+
+ /* wait until BL30 releases it's lock (so we can use the SAR ADC) */
+ do {
+ udelay(1);
+ regmap_read(priv->regmap, SAR_ADC_DELAY, &val);
+ } while (val & SAR_ADC_DELAY_BL30_BUSY);
+}
+
+static void meson_saradc_unlock(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ /* allow BL30 to use the SAR ADC again */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_KERNEL_BUSY, 0);
+
+ mutex_unlock(&indio_dev->mlock);
+}
+
+static void meson_saradc_clear_fifo(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int count;
+
+ for (count = 0; count < SAR_ADC_MAX_FIFO_SIZE; count++) {
+ if (!meson_saradc_get_fifo_count(indio_dev))
+ break;
+
+ regmap_read(priv->regmap, SAR_ADC_FIFO_RD, 0);
+ }
+}
+
+static int meson_saradc_get_sample(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ enum meson_saradc_avg_mode avg_mode,
+ enum meson_saradc_num_samples avg_samples,
+ int *val)
+{
+ int ret;
+
+ meson_saradc_lock(indio_dev);
+
+ /* clear the FIFO to make sure we're not reading old values */
+ meson_saradc_clear_fifo(indio_dev);
+
+ meson_saradc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
+
+ meson_saradc_enable_channel(indio_dev, chan);
+
+ meson_saradc_start_sample_engine(indio_dev);
+ ret = meson_saradc_read_raw_sample(indio_dev, chan, val);
+ meson_saradc_stop_sample_engine(indio_dev);
+
+ meson_saradc_unlock(indio_dev);
+
+ if (ret) {
+ dev_warn(indio_dev->dev.parent,
+ "failed to read sample for channel %d: %d\n",
+ chan->channel, ret);
+ return ret;
+ }
+
+ return IIO_VAL_INT;
+}
+
+static int meson_saradc_iio_info_read_raw(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ int *val, int *val2, long mask)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int ret;
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ return meson_saradc_get_sample(indio_dev, chan, NO_AVERAGING,
+ ONE_SAMPLE, val);
+ break;
+
+ case IIO_CHAN_INFO_AVERAGE_RAW:
+ return meson_saradc_get_sample(indio_dev, chan, MEAN_AVERAGING,
+ EIGHT_SAMPLES, val);
+ break;
+
+ case IIO_CHAN_INFO_SCALE:
+ ret = regulator_get_voltage(priv->vref);
+ if (ret < 0) {
+ dev_err(indio_dev->dev.parent,
+ "failed to get vref voltage: %d\n", ret);
+ return ret;
+ }
+
+ *val = ret / 1000;
+ *val2 = priv->data->resolution;
+ return IIO_VAL_FRACTIONAL_LOG2;
+
+ default:
+ return -EINVAL;
+ }
+}
+
+static int meson_saradc_clk_init(struct iio_dev *indio_dev, void __iomem *base)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ struct clk_init_data init;
+ const char *clk_parents[1];
+
+ init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_div",
+ of_node_full_name(indio_dev->dev.of_node));
+ init.flags = 0;
+ init.ops = &clk_divider_ops;
+ clk_parents[0] = __clk_get_name(priv->clkin);
+ init.parent_names = clk_parents;
+ init.num_parents = 1;
+
+ priv->clk_div.reg = base + SAR_ADC_REG3;
+ priv->clk_div.shift = SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
+ priv->clk_div.width = SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
+ priv->clk_div.hw.init = &init;
+ priv->clk_div.flags = 0;
+
+ priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
+ &priv->clk_div.hw);
+ if (WARN_ON(IS_ERR(priv->adc_div_clk)))
+ return PTR_ERR(priv->adc_div_clk);
+
+ init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_en",
+ of_node_full_name(indio_dev->dev.of_node));
+ init.flags = CLK_SET_RATE_PARENT;
+ init.ops = &clk_gate_ops;
+ clk_parents[0] = __clk_get_name(priv->adc_div_clk);
+ init.parent_names = clk_parents;
+ init.num_parents = 1;
+
+ priv->clk_gate.reg = base + SAR_ADC_REG3;
+ priv->clk_gate.bit_idx = fls(SAR_ADC_REG3_CLK_EN);
+ priv->clk_gate.hw.init = &init;
+
+ priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
+ if (WARN_ON(IS_ERR(priv->adc_clk)))
+ return PTR_ERR(priv->adc_clk);
+
+ return 0;
+}
+
+static int meson_saradc_init(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int regval, ret;
+
+ /*
+ * make sure we start at CH7 input since the other muxes are only used
+ * for internal calibration.
+ */
+ meson_saradc_set_channel7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
+
+ /*
+ * leave sampling delay and the input clocks as configured by BL30 to
+ * make sure BL30 gets the values it expects when reading the
+ * temperature sensor.
+ */
+ regmap_read(priv->regmap, SAR_ADC_REG3, ®val);
+ if (regval & SAR_ADC_REG3_BL30_INITIALIZED)
+ return 0;
+
+ meson_saradc_stop_sample_engine(indio_dev);
+
+ /* update the channel 6 MUX to select the temperature sensor */
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
+ SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
+
+ /* disable all channels by default */
+ regmap_write(priv->regmap, SAR_ADC_CHAN_LIST, 0x0);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3,
+ SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3,
+ SAR_ADC_REG3_CNTL_USE_SC_DLY,
+ SAR_ADC_REG3_CNTL_USE_SC_DLY);
+
+ /* delay between two samples = (10+1) * 1uS */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK, 10));
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 0));
+
+ /* delay between two samples = (10+1) * 1uS */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 10));
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 1));
+
+ ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
+ if (ret) {
+ dev_err(indio_dev->dev.parent,
+ "failed to set adc parent to clkin\n");
+ return ret;
+ }
+
+ ret = clk_set_rate(priv->adc_clk, 1200000);
+ if (ret) {
+ dev_err(indio_dev->dev.parent,
+ "failed to set adc clock rate\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int meson_saradc_hw_enable(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int ret;
+
+ meson_saradc_lock(indio_dev);
+
+ ret = regulator_enable(priv->vref);
+ if (ret < 0) {
+ dev_err(indio_dev->dev.parent,
+ "failed to enable vref regulator\n");
+ goto err_vref;
+ }
+
+ ret = clk_prepare_enable(priv->core_clk);
+ if (ret) {
+ dev_err(indio_dev->dev.parent, "failed to enable core clk\n");
+ goto err_core_clk;
+ }
+
+ ret = clk_prepare_enable(priv->sana_clk);
+ if (ret) {
+ dev_err(indio_dev->dev.parent, "failed to enable sana clk\n");
+ goto err_sana_clk;
+ }
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG11,
+ SAR_ADC_REG11_BANDGAP_EN, SAR_ADC_REG11_BANDGAP_EN);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN,
+ SAR_ADC_REG3_ADC_EN);
+
+ udelay(5);
+
+ ret = clk_prepare_enable(priv->adc_clk);
+ if (ret) {
+ dev_err(indio_dev->dev.parent, "failed to enable adc clk\n");
+ goto err_adc_clk;
+ }
+
+ meson_saradc_unlock(indio_dev);
+
+ return 0;
+
+err_adc_clk:
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN, 0);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG11,
+ SAR_ADC_REG11_BANDGAP_EN, 0);
+ clk_disable_unprepare(priv->sana_clk);
+err_sana_clk:
+ clk_disable_unprepare(priv->core_clk);
+err_core_clk:
+ regulator_disable(priv->vref);
+err_vref:
+ meson_saradc_unlock(indio_dev);
+ return ret;
+}
+
+static void meson_saradc_hw_disable(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ meson_saradc_lock(indio_dev);
+
+ clk_disable_unprepare(priv->adc_clk);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN, 0);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG11,
+ SAR_ADC_REG11_BANDGAP_EN, 0);
+
+ clk_disable_unprepare(priv->sana_clk);
+ clk_disable_unprepare(priv->core_clk);
+
+ regulator_disable(priv->vref);
+
+ meson_saradc_unlock(indio_dev);
+}
+
+static const struct iio_info meson_saradc_iio_info = {
+ .read_raw = meson_saradc_iio_info_read_raw,
+ .driver_module = THIS_MODULE,
+};
+
+struct meson_saradc_data meson_saradc_gxbb_data = {
+ .resolution = 10,
+ .name = "meson-gxbb-saradc",
+};
+
+struct meson_saradc_data meson_saradc_gxl_data = {
+ .resolution = 12,
+ .name = "meson-gxl-saradc",
+};
+
+static const struct of_device_id meson_saradc_of_match[] = {
+ {
+ .compatible = "amlogic,meson-gxbb-saradc",
+ .data = &meson_saradc_gxbb_data,
+ }, {
+ .compatible = "amlogic,meson-gxl-saradc",
+ .data = &meson_saradc_gxl_data,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, meson_saradc_of_match);
+
+static int meson_saradc_probe(struct platform_device *pdev)
+{
+ struct meson_saradc_priv *priv;
+ struct iio_dev *indio_dev;
+ struct resource *res;
+ void __iomem *base;
+ const struct of_device_id *match;
+ int ret;
+
+ indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
+ if (!indio_dev) {
+ dev_err(&pdev->dev, "failed allocating iio device\n");
+ return -ENOMEM;
+ }
+
+ priv = iio_priv(indio_dev);
+
+ match = of_match_device(meson_saradc_of_match, &pdev->dev);
+ priv->data = match->data;
+
+ indio_dev->name = priv->data->name;
+ indio_dev->dev.parent = &pdev->dev;
+ indio_dev->dev.of_node = pdev->dev.of_node;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->info = &meson_saradc_iio_info;
+
+ indio_dev->channels = meson_saradc_iio_channels;
+ indio_dev->num_channels = ARRAY_SIZE(meson_saradc_iio_channels);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
+ &meson_saradc_regmap_config);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+ priv->clkin = devm_clk_get(&pdev->dev, "clkin");
+ if (IS_ERR(priv->clkin)) {
+ dev_err(&pdev->dev, "failed to get clkin\n");
+ return PTR_ERR(priv->clkin);
+ }
+
+ priv->core_clk = devm_clk_get(&pdev->dev, "core");
+ if (IS_ERR(priv->core_clk)) {
+ dev_err(&pdev->dev, "failed to get core clk\n");
+ return PTR_ERR(priv->core_clk);
+ }
+
+ priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
+ if (IS_ERR(priv->sana_clk)) {
+ if (PTR_ERR(priv->sana_clk) == -ENOENT) {
+ priv->sana_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get sana clk\n");
+ return PTR_ERR(priv->sana_clk);
+ }
+ }
+
+ priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
+ if (IS_ERR(priv->adc_clk)) {
+ if (PTR_ERR(priv->adc_clk) == -ENOENT) {
+ priv->adc_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get adc clk\n");
+ return PTR_ERR(priv->adc_clk);
+ }
+ }
+
+ priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
+ if (IS_ERR(priv->adc_sel_clk)) {
+ if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
+ priv->adc_sel_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get adc_sel clk\n");
+ return PTR_ERR(priv->adc_sel_clk);
+ }
+ }
+
+ /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
+ if (!priv->adc_clk) {
+ ret = meson_saradc_clk_init(indio_dev, base);
+ if (ret)
+ return ret;
+ }
+
+ priv->vref = devm_regulator_get(&pdev->dev, "vref");
+ if (IS_ERR(priv->vref)) {
+ dev_err(&pdev->dev, "failed to get vref regulator\n");
+ return PTR_ERR(priv->vref);
+ }
+
+ ret = meson_saradc_init(indio_dev);
+ if (ret)
+ goto err;
+
+ ret = meson_saradc_hw_enable(indio_dev);
+ if (ret)
+ goto err;
+
+ platform_set_drvdata(pdev, indio_dev);
+
+ ret = iio_device_register(indio_dev);
+ if (ret)
+ goto err_hw;
+
+ return 0;
+
+err_hw:
+ meson_saradc_hw_disable(indio_dev);
+err:
+ return ret;
+}
+
+static int meson_saradc_remove(struct platform_device *pdev)
+{
+ struct iio_dev *indio_dev = platform_get_drvdata(pdev);
+
+ meson_saradc_hw_disable(indio_dev);
+ iio_device_unregister(indio_dev);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int meson_saradc_suspend(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+
+ meson_saradc_hw_disable(indio_dev);
+
+ return 0;
+}
+
+static int meson_saradc_resume(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+
+ return meson_saradc_hw_enable(indio_dev);
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(meson_saradc_pm_ops,
+ meson_saradc_suspend, meson_saradc_resume);
+
+static struct platform_driver meson_saradc_driver = {
+ .probe = meson_saradc_probe,
+ .remove = meson_saradc_remove,
+ .driver = {
+ .name = "meson-saradc",
+ .of_match_table = meson_saradc_of_match,
+ .pm = &meson_saradc_pm_ops,
+ },
+};
+
+module_platform_driver(meson_saradc_driver);
+
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>");
+MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
+MODULE_LICENSE("GPL v2");
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
@ 2017-01-15 22:42 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-15 22:42 UTC (permalink / raw)
To: jic23, knaack.h, lars, pmeerw, robh+dt, mark.rutland, khilman,
linux-iio, devicetree, linux-amlogic, linux-clk
Cc: carlo, catalin.marinas, will.deacon, mturquette, sboyd,
narmstrong, linux-arm-kernel, Martin Blumenstingl
This adds support for the SAR (Successive Approximation Register) ADC
on the Amlogic Meson SoCs.
The code is based on the public S805 (Meson8b) and S905 (GXBB)
datasheets (see [0] and [1]), as well as by reading (various versions
of) the vendor driver and by inspecting the registers on the vendor
kernels of my testing-hardware.
Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
The code was written to support older SoCs (Meson8 and Meson8b) as well,
but due to lack of actual testing-hardware no of_device_id was added for
these.
Two "features" from the vendor driver are currently missing:
- the vendor driver uses channel #7 for calibration (this improves the
accuracy of the results - in my tests the results were less than 3%
off without calibration compared to the vendor driver). Adding support
for this should be easy, but is not required for most applications.
- channel #6 is connected to the SoCs internal temperature sensor.
Adding support for this is probably not so easy since (based on the
u-boot sources) most SoC versions are using different registers and
algorithms for the conversion from "ADC value" to temperature.
Supported by the hardware but currently not supported by the driver:
- reading multiple channels at the same time (the hardware has a FIFO
buffer which stores multiple results)
- continuous sampling (this would require a way to enable this
individually because otherwise the ADC would be drawing power
constantly)
- interrupt support (similar to the vendor driver this new driver is
polling the results. It is unclear if the IRQ-mode is supported on
older (Meson6 or Meson8) hardware as well or if there are any errata)
[0]
http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
[1] http://dn.odroid.com/S905/DataSheet/S905_Public_Datasheet_V1.1.4.pdf
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/iio/adc/Kconfig | 12 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/meson_saradc.c | 893 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 906 insertions(+)
create mode 100644 drivers/iio/adc/meson_saradc.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 9c8b558ba19e..86059b9b91bf 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -371,6 +371,18 @@ config MEN_Z188_ADC
This driver can also be built as a module. If so, the module will be
called men_z188_adc.
+config MESON_SARADC
+ tristate "Amlogic Meson SAR ADC driver"
+ default ARCH_MESON
+ depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
+ select REGMAP_MMIO
+ help
+ Say yes here to build support for the SAR ADC found in Amlogic Meson
+ SoCs.
+
+ To compile this driver as a module, choose M here: the
+ module will be called meson_saradc.
+
config MXS_LRADC
tristate "Freescale i.MX23/i.MX28 LRADC"
depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index d36c4be8d1fc..de05b9e75f8f 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
obj-$(CONFIG_MCP3422) += mcp3422.o
obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
+obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
obj-$(CONFIG_NAU7802) += nau7802.o
obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
new file mode 100644
index 000000000000..4c189e5fd7cc
--- /dev/null
+++ b/drivers/iio/adc/meson_saradc.c
@@ -0,0 +1,893 @@
+/*
+ * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
+ *
+ * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/iio/iio.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+
+#define SAR_ADC_REG0 0x00
+ #define SAR_ADC_REG0_PANEL_DETECT BIT(31)
+ #define SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
+ #define SAR_ADC_REG0_DELTA_BUSY BIT(30)
+ #define SAR_ADC_REG0_AVG_BUSY BIT(29)
+ #define SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
+ #define SAR_ADC_REG0_FIFO_FULL BIT(27)
+ #define SAR_ADC_REG0_FIFO_EMPTY BIT(26)
+ #define SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
+ #define SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
+ #define SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
+ #define SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
+ #define SAR_ADC_REG0_SAMPLING_STOP BIT(14)
+ #define SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
+ #define SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
+ #define SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
+ #define SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
+ #define SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
+ #define SAR_ADC_REG0_SAMPLING_START BIT(2)
+ #define SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
+ #define SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
+
+#define SAR_ADC_CHAN_LIST 0x04
+ #define SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
+ #define SAR_ADC_CHAN_CHAN_ENTRY_MASK(_chan) \
+ (GENMASK(2, 0) << (_chan * 3))
+
+#define SAR_ADC_AVG_CNTL 0x08
+ #define SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
+ (16 + (_chan * 2))
+ #define SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
+ (GENMASK(17, 16) << (_chan * 2))
+ #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
+ (0 + (_chan * 2))
+ #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
+ (GENMASK(1, 0) << (_chan * 2))
+
+#define SAR_ADC_REG3 0x0c
+ #define SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
+ #define SAR_ADC_REG3_CLK_EN BIT(30)
+ #define SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
+ #define SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
+ #define SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
+ #define SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
+ #define SAR_ADC_REG3_DETECT_EN BIT(22)
+ #define SAR_ADC_REG3_ADC_EN BIT(21)
+ #define SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
+ #define SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
+ #define SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
+ #define SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
+ #define SAR_ADC_REG3_ADC_CLK_DIV_MASK GENMASK(15, 10)
+ #define SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
+ #define SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
+
+#define SAR_ADC_DELAY 0x10
+ #define SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
+ #define SAR_ADC_DELAY_BL30_BUSY BIT(15)
+ #define SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
+ #define SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
+ #define SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
+ #define SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
+
+#define SAR_ADC_LAST_RD 0x14
+ #define SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
+ #define SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
+
+#define SAR_ADC_FIFO_RD 0x18
+ #define SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
+ #define SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
+
+#define SAR_ADC_AUX_SW 0x1c
+ #define SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
+ (GENMASK(10, 8) << ((_chan - 2) * 2))
+ #define SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
+ #define SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
+ #define SAR_ADC_AUX_SW_MODE_SEL BIT(4)
+ #define SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
+ #define SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
+ #define SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
+ #define SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
+
+#define SAR_ADC_CHAN_10_SW 0x20
+ #define SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
+
+#define SAR_ADC_DETECT_IDLE_SW 0x24
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK GENMASK(25, 23)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_P_MUX BIT(22)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_N_MUX BIT(21)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YP_DRIVE_SW BIT(19)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XP_DRIVE_SW BIT(18)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YM_DRIVE_SW BIT(17)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XM_DRIVE_SW BIT(16)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK GENMASK(9, 7)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_P_MUX BIT(6)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_N_MUX BIT(5)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YP_DRIVE_SW BIT(3)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XP_DRIVE_SW BIT(2)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YM_DRIVE_SW BIT(1)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XM_DRIVE_SW BIT(0)
+
+#define SAR_ADC_DELTA_10 0x28
+ #define SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
+ #define SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
+ #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_SHIFT 16
+ #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
+ #define SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
+ #define SAR_ADC_DELTA_10_TS_C_SHIFT 11
+ #define SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
+ #define SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
+ #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_SHIFT 0
+ #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
+
+/*
+ * NOTE: registers from here are undocumented (the vendor Linux kernel driver
+ * and u-boot source served as reference). These only seem to be relevant on
+ * GXBB and newer.
+ */
+#define SAR_ADC_REG11 0x2c
+ #define SAR_ADC_REG11_BANDGAP_EN BIT(13)
+
+#define SAR_ADC_REG13 0x34
+ #define SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
+
+#define SAR_ADC_MAX_FIFO_SIZE 32
+
+#define MESON_SAR_ADC_CHAN(_chan, _type) { \
+ .type = _type, \
+ .indexed = true, \
+ .channel = _chan, \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
+ BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
+ .datasheet_name = "SAR_ADC_CH"#_chan, \
+}
+
+/*
+ * TODO: the hardware supports IIO_TEMP for channel 6 as well which is
+ * currently not supported by this driver.
+ */
+static const struct iio_chan_spec meson_saradc_iio_channels[] = {
+ MESON_SAR_ADC_CHAN(0, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(1, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(2, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(3, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(4, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(5, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(6, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(7, IIO_VOLTAGE),
+ IIO_CHAN_SOFT_TIMESTAMP(8),
+};
+
+enum meson_saradc_avg_mode {
+ NO_AVERAGING = 0x0,
+ MEAN_AVERAGING = 0x1,
+ MEDIAN_AVERAGING = 0x2,
+};
+
+enum meson_saradc_num_samples {
+ ONE_SAMPLE = 0x0,
+ TWO_SAMPLES = 0x1,
+ FOUR_SAMPLES = 0x2,
+ EIGHT_SAMPLES = 0x3,
+};
+
+enum meson_saradc_chan7_mux_sel {
+ CHAN7_MUX_VSS = 0x0,
+ CHAN7_MUX_VDD_DIV4 = 0x1,
+ CHAN7_MUX_VDD_DIV2 = 0x2,
+ CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
+ CHAN7_MUX_VDD = 0x4,
+ CHAN7_MUX_CH7_INPUT = 0x7,
+};
+
+struct meson_saradc_data {
+ unsigned int resolution;
+ const char *name;
+};
+
+struct meson_saradc_priv {
+ struct regmap *regmap;
+ struct regulator *vref;
+ const struct meson_saradc_data *data;
+ struct clk *clkin;
+ struct clk *core_clk;
+ struct clk *sana_clk;
+ struct clk *adc_sel_clk;
+ struct clk *adc_clk;
+ struct clk_gate clk_gate;
+ struct clk *adc_div_clk;
+ struct clk_divider clk_div;
+};
+
+static const struct regmap_config meson_saradc_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = SAR_ADC_REG13,
+};
+
+static unsigned int meson_saradc_get_fifo_count(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
+
+ return FIELD_GET(SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
+}
+
+static int meson_saradc_wait_busy_clear(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int regval, timeout = 10000;
+
+ /*
+ * NOTE: we need a small delay before reading the status, otherwise
+ * the sample engine may not have started internally (which would
+ * seem to us that sampling is already finished).
+ */
+ do {
+ udelay(1);
+ regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
+ } while (FIELD_GET(SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
+
+ if (timeout < 0)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static int meson_saradc_read_raw_sample(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ int *val)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0;
+
+ ret = meson_saradc_wait_busy_clear(indio_dev);
+ if (ret)
+ return ret;
+
+ while (meson_saradc_get_fifo_count(indio_dev) > 0 &&
+ count < SAR_ADC_MAX_FIFO_SIZE) {
+ regmap_read(priv->regmap, SAR_ADC_FIFO_RD, ®val);
+
+ fifo_chan = FIELD_GET(SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
+ if (fifo_chan == chan->channel) {
+ fifo_val = FIELD_GET(SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK,
+ regval);
+ fifo_val &= (BIT(priv->data->resolution) - 1);
+
+ sum += fifo_val;
+ count++;
+ }
+ }
+
+ if (!count)
+ return -ENOENT;
+
+ *val = sum / count;
+
+ return 0;
+}
+
+static void meson_saradc_set_averaging(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ enum meson_saradc_avg_mode mode,
+ enum meson_saradc_num_samples samples)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 val;
+
+ val = samples << SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
+ SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(chan->channel),
+ val);
+
+ val = mode << SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
+ SAR_ADC_AVG_CNTL_AVG_MODE_MASK(chan->channel), val);
+}
+
+static void meson_saradc_enable_channel(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ /* the SAR ADC engine allows sampling multiple channels at the same
+ * time. to keep it simple we're only working with one *internal*
+ * channel, which starts counting at index 0 (which means: count = 1).
+ */
+ regval = FIELD_PREP(SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
+ regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
+ SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
+
+ /* map channel index 0 to the channel which we want to read */
+ regval = FIELD_PREP(SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
+ SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), regval);
+
+ regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
+ chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
+ SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
+ regval);
+
+ regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
+ chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
+ SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
+ regval);
+
+ if (chan->channel == 6)
+ regmap_update_bits(priv->regmap, SAR_ADC_DELTA_10,
+ SAR_ADC_DELTA_10_TEMP_SEL, 0);
+}
+
+static void meson_saradc_set_channel7_mux(struct iio_dev *indio_dev,
+ enum meson_saradc_chan7_mux_sel sel)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ regval = FIELD_PREP(SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3,
+ SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
+
+ usleep_range(10, 20);
+}
+
+static void meson_saradc_start_sample_engine(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
+ SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLING_START,
+ SAR_ADC_REG0_SAMPLING_START);
+}
+
+static void meson_saradc_stop_sample_engine(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLING_STOP,
+ SAR_ADC_REG0_SAMPLING_STOP);
+
+ /* wait until all modules are stopped */
+ meson_saradc_wait_busy_clear(indio_dev);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
+}
+
+static void meson_saradc_lock(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int val;
+
+ mutex_lock(&indio_dev->mlock);
+
+ /* prevent BL30 from using the SAR ADC while we are using it */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_KERNEL_BUSY,
+ SAR_ADC_DELAY_KERNEL_BUSY);
+
+ /* wait until BL30 releases it's lock (so we can use the SAR ADC) */
+ do {
+ udelay(1);
+ regmap_read(priv->regmap, SAR_ADC_DELAY, &val);
+ } while (val & SAR_ADC_DELAY_BL30_BUSY);
+}
+
+static void meson_saradc_unlock(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ /* allow BL30 to use the SAR ADC again */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_KERNEL_BUSY, 0);
+
+ mutex_unlock(&indio_dev->mlock);
+}
+
+static void meson_saradc_clear_fifo(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int count;
+
+ for (count = 0; count < SAR_ADC_MAX_FIFO_SIZE; count++) {
+ if (!meson_saradc_get_fifo_count(indio_dev))
+ break;
+
+ regmap_read(priv->regmap, SAR_ADC_FIFO_RD, 0);
+ }
+}
+
+static int meson_saradc_get_sample(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ enum meson_saradc_avg_mode avg_mode,
+ enum meson_saradc_num_samples avg_samples,
+ int *val)
+{
+ int ret;
+
+ meson_saradc_lock(indio_dev);
+
+ /* clear the FIFO to make sure we're not reading old values */
+ meson_saradc_clear_fifo(indio_dev);
+
+ meson_saradc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
+
+ meson_saradc_enable_channel(indio_dev, chan);
+
+ meson_saradc_start_sample_engine(indio_dev);
+ ret = meson_saradc_read_raw_sample(indio_dev, chan, val);
+ meson_saradc_stop_sample_engine(indio_dev);
+
+ meson_saradc_unlock(indio_dev);
+
+ if (ret) {
+ dev_warn(indio_dev->dev.parent,
+ "failed to read sample for channel %d: %d\n",
+ chan->channel, ret);
+ return ret;
+ }
+
+ return IIO_VAL_INT;
+}
+
+static int meson_saradc_iio_info_read_raw(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ int *val, int *val2, long mask)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int ret;
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ return meson_saradc_get_sample(indio_dev, chan, NO_AVERAGING,
+ ONE_SAMPLE, val);
+ break;
+
+ case IIO_CHAN_INFO_AVERAGE_RAW:
+ return meson_saradc_get_sample(indio_dev, chan, MEAN_AVERAGING,
+ EIGHT_SAMPLES, val);
+ break;
+
+ case IIO_CHAN_INFO_SCALE:
+ ret = regulator_get_voltage(priv->vref);
+ if (ret < 0) {
+ dev_err(indio_dev->dev.parent,
+ "failed to get vref voltage: %d\n", ret);
+ return ret;
+ }
+
+ *val = ret / 1000;
+ *val2 = priv->data->resolution;
+ return IIO_VAL_FRACTIONAL_LOG2;
+
+ default:
+ return -EINVAL;
+ }
+}
+
+static int meson_saradc_clk_init(struct iio_dev *indio_dev, void __iomem *base)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ struct clk_init_data init;
+ const char *clk_parents[1];
+
+ init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_div",
+ of_node_full_name(indio_dev->dev.of_node));
+ init.flags = 0;
+ init.ops = &clk_divider_ops;
+ clk_parents[0] = __clk_get_name(priv->clkin);
+ init.parent_names = clk_parents;
+ init.num_parents = 1;
+
+ priv->clk_div.reg = base + SAR_ADC_REG3;
+ priv->clk_div.shift = SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
+ priv->clk_div.width = SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
+ priv->clk_div.hw.init = &init;
+ priv->clk_div.flags = 0;
+
+ priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
+ &priv->clk_div.hw);
+ if (WARN_ON(IS_ERR(priv->adc_div_clk)))
+ return PTR_ERR(priv->adc_div_clk);
+
+ init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_en",
+ of_node_full_name(indio_dev->dev.of_node));
+ init.flags = CLK_SET_RATE_PARENT;
+ init.ops = &clk_gate_ops;
+ clk_parents[0] = __clk_get_name(priv->adc_div_clk);
+ init.parent_names = clk_parents;
+ init.num_parents = 1;
+
+ priv->clk_gate.reg = base + SAR_ADC_REG3;
+ priv->clk_gate.bit_idx = fls(SAR_ADC_REG3_CLK_EN);
+ priv->clk_gate.hw.init = &init;
+
+ priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
+ if (WARN_ON(IS_ERR(priv->adc_clk)))
+ return PTR_ERR(priv->adc_clk);
+
+ return 0;
+}
+
+static int meson_saradc_init(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int regval, ret;
+
+ /*
+ * make sure we start at CH7 input since the other muxes are only used
+ * for internal calibration.
+ */
+ meson_saradc_set_channel7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
+
+ /*
+ * leave sampling delay and the input clocks as configured by BL30 to
+ * make sure BL30 gets the values it expects when reading the
+ * temperature sensor.
+ */
+ regmap_read(priv->regmap, SAR_ADC_REG3, ®val);
+ if (regval & SAR_ADC_REG3_BL30_INITIALIZED)
+ return 0;
+
+ meson_saradc_stop_sample_engine(indio_dev);
+
+ /* update the channel 6 MUX to select the temperature sensor */
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
+ SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
+
+ /* disable all channels by default */
+ regmap_write(priv->regmap, SAR_ADC_CHAN_LIST, 0x0);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3,
+ SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3,
+ SAR_ADC_REG3_CNTL_USE_SC_DLY,
+ SAR_ADC_REG3_CNTL_USE_SC_DLY);
+
+ /* delay between two samples = (10+1) * 1uS */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK, 10));
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 0));
+
+ /* delay between two samples = (10+1) * 1uS */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 10));
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 1));
+
+ ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
+ if (ret) {
+ dev_err(indio_dev->dev.parent,
+ "failed to set adc parent to clkin\n");
+ return ret;
+ }
+
+ ret = clk_set_rate(priv->adc_clk, 1200000);
+ if (ret) {
+ dev_err(indio_dev->dev.parent,
+ "failed to set adc clock rate\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int meson_saradc_hw_enable(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int ret;
+
+ meson_saradc_lock(indio_dev);
+
+ ret = regulator_enable(priv->vref);
+ if (ret < 0) {
+ dev_err(indio_dev->dev.parent,
+ "failed to enable vref regulator\n");
+ goto err_vref;
+ }
+
+ ret = clk_prepare_enable(priv->core_clk);
+ if (ret) {
+ dev_err(indio_dev->dev.parent, "failed to enable core clk\n");
+ goto err_core_clk;
+ }
+
+ ret = clk_prepare_enable(priv->sana_clk);
+ if (ret) {
+ dev_err(indio_dev->dev.parent, "failed to enable sana clk\n");
+ goto err_sana_clk;
+ }
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG11,
+ SAR_ADC_REG11_BANDGAP_EN, SAR_ADC_REG11_BANDGAP_EN);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN,
+ SAR_ADC_REG3_ADC_EN);
+
+ udelay(5);
+
+ ret = clk_prepare_enable(priv->adc_clk);
+ if (ret) {
+ dev_err(indio_dev->dev.parent, "failed to enable adc clk\n");
+ goto err_adc_clk;
+ }
+
+ meson_saradc_unlock(indio_dev);
+
+ return 0;
+
+err_adc_clk:
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN, 0);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG11,
+ SAR_ADC_REG11_BANDGAP_EN, 0);
+ clk_disable_unprepare(priv->sana_clk);
+err_sana_clk:
+ clk_disable_unprepare(priv->core_clk);
+err_core_clk:
+ regulator_disable(priv->vref);
+err_vref:
+ meson_saradc_unlock(indio_dev);
+ return ret;
+}
+
+static void meson_saradc_hw_disable(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ meson_saradc_lock(indio_dev);
+
+ clk_disable_unprepare(priv->adc_clk);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN, 0);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG11,
+ SAR_ADC_REG11_BANDGAP_EN, 0);
+
+ clk_disable_unprepare(priv->sana_clk);
+ clk_disable_unprepare(priv->core_clk);
+
+ regulator_disable(priv->vref);
+
+ meson_saradc_unlock(indio_dev);
+}
+
+static const struct iio_info meson_saradc_iio_info = {
+ .read_raw = meson_saradc_iio_info_read_raw,
+ .driver_module = THIS_MODULE,
+};
+
+struct meson_saradc_data meson_saradc_gxbb_data = {
+ .resolution = 10,
+ .name = "meson-gxbb-saradc",
+};
+
+struct meson_saradc_data meson_saradc_gxl_data = {
+ .resolution = 12,
+ .name = "meson-gxl-saradc",
+};
+
+static const struct of_device_id meson_saradc_of_match[] = {
+ {
+ .compatible = "amlogic,meson-gxbb-saradc",
+ .data = &meson_saradc_gxbb_data,
+ }, {
+ .compatible = "amlogic,meson-gxl-saradc",
+ .data = &meson_saradc_gxl_data,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, meson_saradc_of_match);
+
+static int meson_saradc_probe(struct platform_device *pdev)
+{
+ struct meson_saradc_priv *priv;
+ struct iio_dev *indio_dev;
+ struct resource *res;
+ void __iomem *base;
+ const struct of_device_id *match;
+ int ret;
+
+ indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
+ if (!indio_dev) {
+ dev_err(&pdev->dev, "failed allocating iio device\n");
+ return -ENOMEM;
+ }
+
+ priv = iio_priv(indio_dev);
+
+ match = of_match_device(meson_saradc_of_match, &pdev->dev);
+ priv->data = match->data;
+
+ indio_dev->name = priv->data->name;
+ indio_dev->dev.parent = &pdev->dev;
+ indio_dev->dev.of_node = pdev->dev.of_node;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->info = &meson_saradc_iio_info;
+
+ indio_dev->channels = meson_saradc_iio_channels;
+ indio_dev->num_channels = ARRAY_SIZE(meson_saradc_iio_channels);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
+ &meson_saradc_regmap_config);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+ priv->clkin = devm_clk_get(&pdev->dev, "clkin");
+ if (IS_ERR(priv->clkin)) {
+ dev_err(&pdev->dev, "failed to get clkin\n");
+ return PTR_ERR(priv->clkin);
+ }
+
+ priv->core_clk = devm_clk_get(&pdev->dev, "core");
+ if (IS_ERR(priv->core_clk)) {
+ dev_err(&pdev->dev, "failed to get core clk\n");
+ return PTR_ERR(priv->core_clk);
+ }
+
+ priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
+ if (IS_ERR(priv->sana_clk)) {
+ if (PTR_ERR(priv->sana_clk) == -ENOENT) {
+ priv->sana_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get sana clk\n");
+ return PTR_ERR(priv->sana_clk);
+ }
+ }
+
+ priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
+ if (IS_ERR(priv->adc_clk)) {
+ if (PTR_ERR(priv->adc_clk) == -ENOENT) {
+ priv->adc_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get adc clk\n");
+ return PTR_ERR(priv->adc_clk);
+ }
+ }
+
+ priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
+ if (IS_ERR(priv->adc_sel_clk)) {
+ if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
+ priv->adc_sel_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get adc_sel clk\n");
+ return PTR_ERR(priv->adc_sel_clk);
+ }
+ }
+
+ /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
+ if (!priv->adc_clk) {
+ ret = meson_saradc_clk_init(indio_dev, base);
+ if (ret)
+ return ret;
+ }
+
+ priv->vref = devm_regulator_get(&pdev->dev, "vref");
+ if (IS_ERR(priv->vref)) {
+ dev_err(&pdev->dev, "failed to get vref regulator\n");
+ return PTR_ERR(priv->vref);
+ }
+
+ ret = meson_saradc_init(indio_dev);
+ if (ret)
+ goto err;
+
+ ret = meson_saradc_hw_enable(indio_dev);
+ if (ret)
+ goto err;
+
+ platform_set_drvdata(pdev, indio_dev);
+
+ ret = iio_device_register(indio_dev);
+ if (ret)
+ goto err_hw;
+
+ return 0;
+
+err_hw:
+ meson_saradc_hw_disable(indio_dev);
+err:
+ return ret;
+}
+
+static int meson_saradc_remove(struct platform_device *pdev)
+{
+ struct iio_dev *indio_dev = platform_get_drvdata(pdev);
+
+ meson_saradc_hw_disable(indio_dev);
+ iio_device_unregister(indio_dev);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int meson_saradc_suspend(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+
+ meson_saradc_hw_disable(indio_dev);
+
+ return 0;
+}
+
+static int meson_saradc_resume(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+
+ return meson_saradc_hw_enable(indio_dev);
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(meson_saradc_pm_ops,
+ meson_saradc_suspend, meson_saradc_resume);
+
+static struct platform_driver meson_saradc_driver = {
+ .probe = meson_saradc_probe,
+ .remove = meson_saradc_remove,
+ .driver = {
+ .name = "meson-saradc",
+ .of_match_table = meson_saradc_of_match,
+ .pm = &meson_saradc_pm_ops,
+ },
+};
+
+module_platform_driver(meson_saradc_driver);
+
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
+MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
+MODULE_LICENSE("GPL v2");
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
@ 2017-01-15 22:42 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-15 22:42 UTC (permalink / raw)
To: linux-arm-kernel
This adds support for the SAR (Successive Approximation Register) ADC
on the Amlogic Meson SoCs.
The code is based on the public S805 (Meson8b) and S905 (GXBB)
datasheets (see [0] and [1]), as well as by reading (various versions
of) the vendor driver and by inspecting the registers on the vendor
kernels of my testing-hardware.
Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
The code was written to support older SoCs (Meson8 and Meson8b) as well,
but due to lack of actual testing-hardware no of_device_id was added for
these.
Two "features" from the vendor driver are currently missing:
- the vendor driver uses channel #7 for calibration (this improves the
accuracy of the results - in my tests the results were less than 3%
off without calibration compared to the vendor driver). Adding support
for this should be easy, but is not required for most applications.
- channel #6 is connected to the SoCs internal temperature sensor.
Adding support for this is probably not so easy since (based on the
u-boot sources) most SoC versions are using different registers and
algorithms for the conversion from "ADC value" to temperature.
Supported by the hardware but currently not supported by the driver:
- reading multiple channels at the same time (the hardware has a FIFO
buffer which stores multiple results)
- continuous sampling (this would require a way to enable this
individually because otherwise the ADC would be drawing power
constantly)
- interrupt support (similar to the vendor driver this new driver is
polling the results. It is unclear if the IRQ-mode is supported on
older (Meson6 or Meson8) hardware as well or if there are any errata)
[0]
http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
[1] http://dn.odroid.com/S905/DataSheet/S905_Public_Datasheet_V1.1.4.pdf
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/iio/adc/Kconfig | 12 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/meson_saradc.c | 893 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 906 insertions(+)
create mode 100644 drivers/iio/adc/meson_saradc.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 9c8b558ba19e..86059b9b91bf 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -371,6 +371,18 @@ config MEN_Z188_ADC
This driver can also be built as a module. If so, the module will be
called men_z188_adc.
+config MESON_SARADC
+ tristate "Amlogic Meson SAR ADC driver"
+ default ARCH_MESON
+ depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
+ select REGMAP_MMIO
+ help
+ Say yes here to build support for the SAR ADC found in Amlogic Meson
+ SoCs.
+
+ To compile this driver as a module, choose M here: the
+ module will be called meson_saradc.
+
config MXS_LRADC
tristate "Freescale i.MX23/i.MX28 LRADC"
depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index d36c4be8d1fc..de05b9e75f8f 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
obj-$(CONFIG_MCP3422) += mcp3422.o
obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
+obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
obj-$(CONFIG_NAU7802) += nau7802.o
obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
new file mode 100644
index 000000000000..4c189e5fd7cc
--- /dev/null
+++ b/drivers/iio/adc/meson_saradc.c
@@ -0,0 +1,893 @@
+/*
+ * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
+ *
+ * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/iio/iio.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+
+#define SAR_ADC_REG0 0x00
+ #define SAR_ADC_REG0_PANEL_DETECT BIT(31)
+ #define SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
+ #define SAR_ADC_REG0_DELTA_BUSY BIT(30)
+ #define SAR_ADC_REG0_AVG_BUSY BIT(29)
+ #define SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
+ #define SAR_ADC_REG0_FIFO_FULL BIT(27)
+ #define SAR_ADC_REG0_FIFO_EMPTY BIT(26)
+ #define SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
+ #define SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
+ #define SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
+ #define SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
+ #define SAR_ADC_REG0_SAMPLING_STOP BIT(14)
+ #define SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
+ #define SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
+ #define SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
+ #define SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
+ #define SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
+ #define SAR_ADC_REG0_SAMPLING_START BIT(2)
+ #define SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
+ #define SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
+
+#define SAR_ADC_CHAN_LIST 0x04
+ #define SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
+ #define SAR_ADC_CHAN_CHAN_ENTRY_MASK(_chan) \
+ (GENMASK(2, 0) << (_chan * 3))
+
+#define SAR_ADC_AVG_CNTL 0x08
+ #define SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
+ (16 + (_chan * 2))
+ #define SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
+ (GENMASK(17, 16) << (_chan * 2))
+ #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
+ (0 + (_chan * 2))
+ #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
+ (GENMASK(1, 0) << (_chan * 2))
+
+#define SAR_ADC_REG3 0x0c
+ #define SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
+ #define SAR_ADC_REG3_CLK_EN BIT(30)
+ #define SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
+ #define SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
+ #define SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
+ #define SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
+ #define SAR_ADC_REG3_DETECT_EN BIT(22)
+ #define SAR_ADC_REG3_ADC_EN BIT(21)
+ #define SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
+ #define SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
+ #define SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
+ #define SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
+ #define SAR_ADC_REG3_ADC_CLK_DIV_MASK GENMASK(15, 10)
+ #define SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
+ #define SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
+
+#define SAR_ADC_DELAY 0x10
+ #define SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
+ #define SAR_ADC_DELAY_BL30_BUSY BIT(15)
+ #define SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
+ #define SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
+ #define SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
+ #define SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
+
+#define SAR_ADC_LAST_RD 0x14
+ #define SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
+ #define SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
+
+#define SAR_ADC_FIFO_RD 0x18
+ #define SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
+ #define SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
+
+#define SAR_ADC_AUX_SW 0x1c
+ #define SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
+ (GENMASK(10, 8) << ((_chan - 2) * 2))
+ #define SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
+ #define SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
+ #define SAR_ADC_AUX_SW_MODE_SEL BIT(4)
+ #define SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
+ #define SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
+ #define SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
+ #define SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
+
+#define SAR_ADC_CHAN_10_SW 0x20
+ #define SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
+
+#define SAR_ADC_DETECT_IDLE_SW 0x24
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK GENMASK(25, 23)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_P_MUX BIT(22)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_N_MUX BIT(21)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YP_DRIVE_SW BIT(19)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XP_DRIVE_SW BIT(18)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YM_DRIVE_SW BIT(17)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XM_DRIVE_SW BIT(16)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK GENMASK(9, 7)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_P_MUX BIT(6)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_N_MUX BIT(5)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YP_DRIVE_SW BIT(3)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XP_DRIVE_SW BIT(2)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YM_DRIVE_SW BIT(1)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XM_DRIVE_SW BIT(0)
+
+#define SAR_ADC_DELTA_10 0x28
+ #define SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
+ #define SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
+ #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_SHIFT 16
+ #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
+ #define SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
+ #define SAR_ADC_DELTA_10_TS_C_SHIFT 11
+ #define SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
+ #define SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
+ #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_SHIFT 0
+ #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
+
+/*
+ * NOTE: registers from here are undocumented (the vendor Linux kernel driver
+ * and u-boot source served as reference). These only seem to be relevant on
+ * GXBB and newer.
+ */
+#define SAR_ADC_REG11 0x2c
+ #define SAR_ADC_REG11_BANDGAP_EN BIT(13)
+
+#define SAR_ADC_REG13 0x34
+ #define SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
+
+#define SAR_ADC_MAX_FIFO_SIZE 32
+
+#define MESON_SAR_ADC_CHAN(_chan, _type) { \
+ .type = _type, \
+ .indexed = true, \
+ .channel = _chan, \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
+ BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
+ .datasheet_name = "SAR_ADC_CH"#_chan, \
+}
+
+/*
+ * TODO: the hardware supports IIO_TEMP for channel 6 as well which is
+ * currently not supported by this driver.
+ */
+static const struct iio_chan_spec meson_saradc_iio_channels[] = {
+ MESON_SAR_ADC_CHAN(0, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(1, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(2, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(3, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(4, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(5, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(6, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(7, IIO_VOLTAGE),
+ IIO_CHAN_SOFT_TIMESTAMP(8),
+};
+
+enum meson_saradc_avg_mode {
+ NO_AVERAGING = 0x0,
+ MEAN_AVERAGING = 0x1,
+ MEDIAN_AVERAGING = 0x2,
+};
+
+enum meson_saradc_num_samples {
+ ONE_SAMPLE = 0x0,
+ TWO_SAMPLES = 0x1,
+ FOUR_SAMPLES = 0x2,
+ EIGHT_SAMPLES = 0x3,
+};
+
+enum meson_saradc_chan7_mux_sel {
+ CHAN7_MUX_VSS = 0x0,
+ CHAN7_MUX_VDD_DIV4 = 0x1,
+ CHAN7_MUX_VDD_DIV2 = 0x2,
+ CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
+ CHAN7_MUX_VDD = 0x4,
+ CHAN7_MUX_CH7_INPUT = 0x7,
+};
+
+struct meson_saradc_data {
+ unsigned int resolution;
+ const char *name;
+};
+
+struct meson_saradc_priv {
+ struct regmap *regmap;
+ struct regulator *vref;
+ const struct meson_saradc_data *data;
+ struct clk *clkin;
+ struct clk *core_clk;
+ struct clk *sana_clk;
+ struct clk *adc_sel_clk;
+ struct clk *adc_clk;
+ struct clk_gate clk_gate;
+ struct clk *adc_div_clk;
+ struct clk_divider clk_div;
+};
+
+static const struct regmap_config meson_saradc_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = SAR_ADC_REG13,
+};
+
+static unsigned int meson_saradc_get_fifo_count(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
+
+ return FIELD_GET(SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
+}
+
+static int meson_saradc_wait_busy_clear(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int regval, timeout = 10000;
+
+ /*
+ * NOTE: we need a small delay before reading the status, otherwise
+ * the sample engine may not have started internally (which would
+ * seem to us that sampling is already finished).
+ */
+ do {
+ udelay(1);
+ regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
+ } while (FIELD_GET(SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
+
+ if (timeout < 0)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static int meson_saradc_read_raw_sample(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ int *val)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0;
+
+ ret = meson_saradc_wait_busy_clear(indio_dev);
+ if (ret)
+ return ret;
+
+ while (meson_saradc_get_fifo_count(indio_dev) > 0 &&
+ count < SAR_ADC_MAX_FIFO_SIZE) {
+ regmap_read(priv->regmap, SAR_ADC_FIFO_RD, ®val);
+
+ fifo_chan = FIELD_GET(SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
+ if (fifo_chan == chan->channel) {
+ fifo_val = FIELD_GET(SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK,
+ regval);
+ fifo_val &= (BIT(priv->data->resolution) - 1);
+
+ sum += fifo_val;
+ count++;
+ }
+ }
+
+ if (!count)
+ return -ENOENT;
+
+ *val = sum / count;
+
+ return 0;
+}
+
+static void meson_saradc_set_averaging(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ enum meson_saradc_avg_mode mode,
+ enum meson_saradc_num_samples samples)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 val;
+
+ val = samples << SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
+ SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(chan->channel),
+ val);
+
+ val = mode << SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
+ SAR_ADC_AVG_CNTL_AVG_MODE_MASK(chan->channel), val);
+}
+
+static void meson_saradc_enable_channel(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ /* the SAR ADC engine allows sampling multiple channels at the same
+ * time. to keep it simple we're only working with one *internal*
+ * channel, which starts counting at index 0 (which means: count = 1).
+ */
+ regval = FIELD_PREP(SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
+ regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
+ SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
+
+ /* map channel index 0 to the channel which we want to read */
+ regval = FIELD_PREP(SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
+ SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), regval);
+
+ regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
+ chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
+ SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
+ regval);
+
+ regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
+ chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
+ SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
+ regval);
+
+ if (chan->channel == 6)
+ regmap_update_bits(priv->regmap, SAR_ADC_DELTA_10,
+ SAR_ADC_DELTA_10_TEMP_SEL, 0);
+}
+
+static void meson_saradc_set_channel7_mux(struct iio_dev *indio_dev,
+ enum meson_saradc_chan7_mux_sel sel)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ regval = FIELD_PREP(SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3,
+ SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
+
+ usleep_range(10, 20);
+}
+
+static void meson_saradc_start_sample_engine(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
+ SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLING_START,
+ SAR_ADC_REG0_SAMPLING_START);
+}
+
+static void meson_saradc_stop_sample_engine(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLING_STOP,
+ SAR_ADC_REG0_SAMPLING_STOP);
+
+ /* wait until all modules are stopped */
+ meson_saradc_wait_busy_clear(indio_dev);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
+}
+
+static void meson_saradc_lock(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int val;
+
+ mutex_lock(&indio_dev->mlock);
+
+ /* prevent BL30 from using the SAR ADC while we are using it */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_KERNEL_BUSY,
+ SAR_ADC_DELAY_KERNEL_BUSY);
+
+ /* wait until BL30 releases it's lock (so we can use the SAR ADC) */
+ do {
+ udelay(1);
+ regmap_read(priv->regmap, SAR_ADC_DELAY, &val);
+ } while (val & SAR_ADC_DELAY_BL30_BUSY);
+}
+
+static void meson_saradc_unlock(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ /* allow BL30 to use the SAR ADC again */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_KERNEL_BUSY, 0);
+
+ mutex_unlock(&indio_dev->mlock);
+}
+
+static void meson_saradc_clear_fifo(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int count;
+
+ for (count = 0; count < SAR_ADC_MAX_FIFO_SIZE; count++) {
+ if (!meson_saradc_get_fifo_count(indio_dev))
+ break;
+
+ regmap_read(priv->regmap, SAR_ADC_FIFO_RD, 0);
+ }
+}
+
+static int meson_saradc_get_sample(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ enum meson_saradc_avg_mode avg_mode,
+ enum meson_saradc_num_samples avg_samples,
+ int *val)
+{
+ int ret;
+
+ meson_saradc_lock(indio_dev);
+
+ /* clear the FIFO to make sure we're not reading old values */
+ meson_saradc_clear_fifo(indio_dev);
+
+ meson_saradc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
+
+ meson_saradc_enable_channel(indio_dev, chan);
+
+ meson_saradc_start_sample_engine(indio_dev);
+ ret = meson_saradc_read_raw_sample(indio_dev, chan, val);
+ meson_saradc_stop_sample_engine(indio_dev);
+
+ meson_saradc_unlock(indio_dev);
+
+ if (ret) {
+ dev_warn(indio_dev->dev.parent,
+ "failed to read sample for channel %d: %d\n",
+ chan->channel, ret);
+ return ret;
+ }
+
+ return IIO_VAL_INT;
+}
+
+static int meson_saradc_iio_info_read_raw(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ int *val, int *val2, long mask)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int ret;
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ return meson_saradc_get_sample(indio_dev, chan, NO_AVERAGING,
+ ONE_SAMPLE, val);
+ break;
+
+ case IIO_CHAN_INFO_AVERAGE_RAW:
+ return meson_saradc_get_sample(indio_dev, chan, MEAN_AVERAGING,
+ EIGHT_SAMPLES, val);
+ break;
+
+ case IIO_CHAN_INFO_SCALE:
+ ret = regulator_get_voltage(priv->vref);
+ if (ret < 0) {
+ dev_err(indio_dev->dev.parent,
+ "failed to get vref voltage: %d\n", ret);
+ return ret;
+ }
+
+ *val = ret / 1000;
+ *val2 = priv->data->resolution;
+ return IIO_VAL_FRACTIONAL_LOG2;
+
+ default:
+ return -EINVAL;
+ }
+}
+
+static int meson_saradc_clk_init(struct iio_dev *indio_dev, void __iomem *base)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ struct clk_init_data init;
+ const char *clk_parents[1];
+
+ init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_div",
+ of_node_full_name(indio_dev->dev.of_node));
+ init.flags = 0;
+ init.ops = &clk_divider_ops;
+ clk_parents[0] = __clk_get_name(priv->clkin);
+ init.parent_names = clk_parents;
+ init.num_parents = 1;
+
+ priv->clk_div.reg = base + SAR_ADC_REG3;
+ priv->clk_div.shift = SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
+ priv->clk_div.width = SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
+ priv->clk_div.hw.init = &init;
+ priv->clk_div.flags = 0;
+
+ priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
+ &priv->clk_div.hw);
+ if (WARN_ON(IS_ERR(priv->adc_div_clk)))
+ return PTR_ERR(priv->adc_div_clk);
+
+ init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_en",
+ of_node_full_name(indio_dev->dev.of_node));
+ init.flags = CLK_SET_RATE_PARENT;
+ init.ops = &clk_gate_ops;
+ clk_parents[0] = __clk_get_name(priv->adc_div_clk);
+ init.parent_names = clk_parents;
+ init.num_parents = 1;
+
+ priv->clk_gate.reg = base + SAR_ADC_REG3;
+ priv->clk_gate.bit_idx = fls(SAR_ADC_REG3_CLK_EN);
+ priv->clk_gate.hw.init = &init;
+
+ priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
+ if (WARN_ON(IS_ERR(priv->adc_clk)))
+ return PTR_ERR(priv->adc_clk);
+
+ return 0;
+}
+
+static int meson_saradc_init(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int regval, ret;
+
+ /*
+ * make sure we start at CH7 input since the other muxes are only used
+ * for internal calibration.
+ */
+ meson_saradc_set_channel7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
+
+ /*
+ * leave sampling delay and the input clocks as configured by BL30 to
+ * make sure BL30 gets the values it expects when reading the
+ * temperature sensor.
+ */
+ regmap_read(priv->regmap, SAR_ADC_REG3, ®val);
+ if (regval & SAR_ADC_REG3_BL30_INITIALIZED)
+ return 0;
+
+ meson_saradc_stop_sample_engine(indio_dev);
+
+ /* update the channel 6 MUX to select the temperature sensor */
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
+ SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
+
+ /* disable all channels by default */
+ regmap_write(priv->regmap, SAR_ADC_CHAN_LIST, 0x0);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3,
+ SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3,
+ SAR_ADC_REG3_CNTL_USE_SC_DLY,
+ SAR_ADC_REG3_CNTL_USE_SC_DLY);
+
+ /* delay between two samples = (10+1) * 1uS */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK, 10));
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 0));
+
+ /* delay between two samples = (10+1) * 1uS */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 10));
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 1));
+
+ ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
+ if (ret) {
+ dev_err(indio_dev->dev.parent,
+ "failed to set adc parent to clkin\n");
+ return ret;
+ }
+
+ ret = clk_set_rate(priv->adc_clk, 1200000);
+ if (ret) {
+ dev_err(indio_dev->dev.parent,
+ "failed to set adc clock rate\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int meson_saradc_hw_enable(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int ret;
+
+ meson_saradc_lock(indio_dev);
+
+ ret = regulator_enable(priv->vref);
+ if (ret < 0) {
+ dev_err(indio_dev->dev.parent,
+ "failed to enable vref regulator\n");
+ goto err_vref;
+ }
+
+ ret = clk_prepare_enable(priv->core_clk);
+ if (ret) {
+ dev_err(indio_dev->dev.parent, "failed to enable core clk\n");
+ goto err_core_clk;
+ }
+
+ ret = clk_prepare_enable(priv->sana_clk);
+ if (ret) {
+ dev_err(indio_dev->dev.parent, "failed to enable sana clk\n");
+ goto err_sana_clk;
+ }
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG11,
+ SAR_ADC_REG11_BANDGAP_EN, SAR_ADC_REG11_BANDGAP_EN);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN,
+ SAR_ADC_REG3_ADC_EN);
+
+ udelay(5);
+
+ ret = clk_prepare_enable(priv->adc_clk);
+ if (ret) {
+ dev_err(indio_dev->dev.parent, "failed to enable adc clk\n");
+ goto err_adc_clk;
+ }
+
+ meson_saradc_unlock(indio_dev);
+
+ return 0;
+
+err_adc_clk:
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN, 0);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG11,
+ SAR_ADC_REG11_BANDGAP_EN, 0);
+ clk_disable_unprepare(priv->sana_clk);
+err_sana_clk:
+ clk_disable_unprepare(priv->core_clk);
+err_core_clk:
+ regulator_disable(priv->vref);
+err_vref:
+ meson_saradc_unlock(indio_dev);
+ return ret;
+}
+
+static void meson_saradc_hw_disable(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ meson_saradc_lock(indio_dev);
+
+ clk_disable_unprepare(priv->adc_clk);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN, 0);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG11,
+ SAR_ADC_REG11_BANDGAP_EN, 0);
+
+ clk_disable_unprepare(priv->sana_clk);
+ clk_disable_unprepare(priv->core_clk);
+
+ regulator_disable(priv->vref);
+
+ meson_saradc_unlock(indio_dev);
+}
+
+static const struct iio_info meson_saradc_iio_info = {
+ .read_raw = meson_saradc_iio_info_read_raw,
+ .driver_module = THIS_MODULE,
+};
+
+struct meson_saradc_data meson_saradc_gxbb_data = {
+ .resolution = 10,
+ .name = "meson-gxbb-saradc",
+};
+
+struct meson_saradc_data meson_saradc_gxl_data = {
+ .resolution = 12,
+ .name = "meson-gxl-saradc",
+};
+
+static const struct of_device_id meson_saradc_of_match[] = {
+ {
+ .compatible = "amlogic,meson-gxbb-saradc",
+ .data = &meson_saradc_gxbb_data,
+ }, {
+ .compatible = "amlogic,meson-gxl-saradc",
+ .data = &meson_saradc_gxl_data,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, meson_saradc_of_match);
+
+static int meson_saradc_probe(struct platform_device *pdev)
+{
+ struct meson_saradc_priv *priv;
+ struct iio_dev *indio_dev;
+ struct resource *res;
+ void __iomem *base;
+ const struct of_device_id *match;
+ int ret;
+
+ indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
+ if (!indio_dev) {
+ dev_err(&pdev->dev, "failed allocating iio device\n");
+ return -ENOMEM;
+ }
+
+ priv = iio_priv(indio_dev);
+
+ match = of_match_device(meson_saradc_of_match, &pdev->dev);
+ priv->data = match->data;
+
+ indio_dev->name = priv->data->name;
+ indio_dev->dev.parent = &pdev->dev;
+ indio_dev->dev.of_node = pdev->dev.of_node;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->info = &meson_saradc_iio_info;
+
+ indio_dev->channels = meson_saradc_iio_channels;
+ indio_dev->num_channels = ARRAY_SIZE(meson_saradc_iio_channels);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
+ &meson_saradc_regmap_config);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+ priv->clkin = devm_clk_get(&pdev->dev, "clkin");
+ if (IS_ERR(priv->clkin)) {
+ dev_err(&pdev->dev, "failed to get clkin\n");
+ return PTR_ERR(priv->clkin);
+ }
+
+ priv->core_clk = devm_clk_get(&pdev->dev, "core");
+ if (IS_ERR(priv->core_clk)) {
+ dev_err(&pdev->dev, "failed to get core clk\n");
+ return PTR_ERR(priv->core_clk);
+ }
+
+ priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
+ if (IS_ERR(priv->sana_clk)) {
+ if (PTR_ERR(priv->sana_clk) == -ENOENT) {
+ priv->sana_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get sana clk\n");
+ return PTR_ERR(priv->sana_clk);
+ }
+ }
+
+ priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
+ if (IS_ERR(priv->adc_clk)) {
+ if (PTR_ERR(priv->adc_clk) == -ENOENT) {
+ priv->adc_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get adc clk\n");
+ return PTR_ERR(priv->adc_clk);
+ }
+ }
+
+ priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
+ if (IS_ERR(priv->adc_sel_clk)) {
+ if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
+ priv->adc_sel_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get adc_sel clk\n");
+ return PTR_ERR(priv->adc_sel_clk);
+ }
+ }
+
+ /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
+ if (!priv->adc_clk) {
+ ret = meson_saradc_clk_init(indio_dev, base);
+ if (ret)
+ return ret;
+ }
+
+ priv->vref = devm_regulator_get(&pdev->dev, "vref");
+ if (IS_ERR(priv->vref)) {
+ dev_err(&pdev->dev, "failed to get vref regulator\n");
+ return PTR_ERR(priv->vref);
+ }
+
+ ret = meson_saradc_init(indio_dev);
+ if (ret)
+ goto err;
+
+ ret = meson_saradc_hw_enable(indio_dev);
+ if (ret)
+ goto err;
+
+ platform_set_drvdata(pdev, indio_dev);
+
+ ret = iio_device_register(indio_dev);
+ if (ret)
+ goto err_hw;
+
+ return 0;
+
+err_hw:
+ meson_saradc_hw_disable(indio_dev);
+err:
+ return ret;
+}
+
+static int meson_saradc_remove(struct platform_device *pdev)
+{
+ struct iio_dev *indio_dev = platform_get_drvdata(pdev);
+
+ meson_saradc_hw_disable(indio_dev);
+ iio_device_unregister(indio_dev);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int meson_saradc_suspend(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+
+ meson_saradc_hw_disable(indio_dev);
+
+ return 0;
+}
+
+static int meson_saradc_resume(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+
+ return meson_saradc_hw_enable(indio_dev);
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(meson_saradc_pm_ops,
+ meson_saradc_suspend, meson_saradc_resume);
+
+static struct platform_driver meson_saradc_driver = {
+ .probe = meson_saradc_probe,
+ .remove = meson_saradc_remove,
+ .driver = {
+ .name = "meson-saradc",
+ .of_match_table = meson_saradc_of_match,
+ .pm = &meson_saradc_pm_ops,
+ },
+};
+
+module_platform_driver(meson_saradc_driver);
+
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
+MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
+MODULE_LICENSE("GPL v2");
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
@ 2017-01-15 22:42 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-15 22:42 UTC (permalink / raw)
To: linus-amlogic
This adds support for the SAR (Successive Approximation Register) ADC
on the Amlogic Meson SoCs.
The code is based on the public S805 (Meson8b) and S905 (GXBB)
datasheets (see [0] and [1]), as well as by reading (various versions
of) the vendor driver and by inspecting the registers on the vendor
kernels of my testing-hardware.
Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
The code was written to support older SoCs (Meson8 and Meson8b) as well,
but due to lack of actual testing-hardware no of_device_id was added for
these.
Two "features" from the vendor driver are currently missing:
- the vendor driver uses channel #7 for calibration (this improves the
accuracy of the results - in my tests the results were less than 3%
off without calibration compared to the vendor driver). Adding support
for this should be easy, but is not required for most applications.
- channel #6 is connected to the SoCs internal temperature sensor.
Adding support for this is probably not so easy since (based on the
u-boot sources) most SoC versions are using different registers and
algorithms for the conversion from "ADC value" to temperature.
Supported by the hardware but currently not supported by the driver:
- reading multiple channels at the same time (the hardware has a FIFO
buffer which stores multiple results)
- continuous sampling (this would require a way to enable this
individually because otherwise the ADC would be drawing power
constantly)
- interrupt support (similar to the vendor driver this new driver is
polling the results. It is unclear if the IRQ-mode is supported on
older (Meson6 or Meson8) hardware as well or if there are any errata)
[0]
http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
[1] http://dn.odroid.com/S905/DataSheet/S905_Public_Datasheet_V1.1.4.pdf
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/iio/adc/Kconfig | 12 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/meson_saradc.c | 893 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 906 insertions(+)
create mode 100644 drivers/iio/adc/meson_saradc.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 9c8b558ba19e..86059b9b91bf 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -371,6 +371,18 @@ config MEN_Z188_ADC
This driver can also be built as a module. If so, the module will be
called men_z188_adc.
+config MESON_SARADC
+ tristate "Amlogic Meson SAR ADC driver"
+ default ARCH_MESON
+ depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
+ select REGMAP_MMIO
+ help
+ Say yes here to build support for the SAR ADC found in Amlogic Meson
+ SoCs.
+
+ To compile this driver as a module, choose M here: the
+ module will be called meson_saradc.
+
config MXS_LRADC
tristate "Freescale i.MX23/i.MX28 LRADC"
depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index d36c4be8d1fc..de05b9e75f8f 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
obj-$(CONFIG_MCP3422) += mcp3422.o
obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
+obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
obj-$(CONFIG_NAU7802) += nau7802.o
obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
new file mode 100644
index 000000000000..4c189e5fd7cc
--- /dev/null
+++ b/drivers/iio/adc/meson_saradc.c
@@ -0,0 +1,893 @@
+/*
+ * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
+ *
+ * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/iio/iio.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+
+#define SAR_ADC_REG0 0x00
+ #define SAR_ADC_REG0_PANEL_DETECT BIT(31)
+ #define SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
+ #define SAR_ADC_REG0_DELTA_BUSY BIT(30)
+ #define SAR_ADC_REG0_AVG_BUSY BIT(29)
+ #define SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
+ #define SAR_ADC_REG0_FIFO_FULL BIT(27)
+ #define SAR_ADC_REG0_FIFO_EMPTY BIT(26)
+ #define SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
+ #define SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
+ #define SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
+ #define SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
+ #define SAR_ADC_REG0_SAMPLING_STOP BIT(14)
+ #define SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
+ #define SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
+ #define SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
+ #define SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
+ #define SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
+ #define SAR_ADC_REG0_SAMPLING_START BIT(2)
+ #define SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
+ #define SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
+
+#define SAR_ADC_CHAN_LIST 0x04
+ #define SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
+ #define SAR_ADC_CHAN_CHAN_ENTRY_MASK(_chan) \
+ (GENMASK(2, 0) << (_chan * 3))
+
+#define SAR_ADC_AVG_CNTL 0x08
+ #define SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
+ (16 + (_chan * 2))
+ #define SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
+ (GENMASK(17, 16) << (_chan * 2))
+ #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
+ (0 + (_chan * 2))
+ #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
+ (GENMASK(1, 0) << (_chan * 2))
+
+#define SAR_ADC_REG3 0x0c
+ #define SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
+ #define SAR_ADC_REG3_CLK_EN BIT(30)
+ #define SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
+ #define SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
+ #define SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
+ #define SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
+ #define SAR_ADC_REG3_DETECT_EN BIT(22)
+ #define SAR_ADC_REG3_ADC_EN BIT(21)
+ #define SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
+ #define SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
+ #define SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
+ #define SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
+ #define SAR_ADC_REG3_ADC_CLK_DIV_MASK GENMASK(15, 10)
+ #define SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
+ #define SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
+
+#define SAR_ADC_DELAY 0x10
+ #define SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
+ #define SAR_ADC_DELAY_BL30_BUSY BIT(15)
+ #define SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
+ #define SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
+ #define SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
+ #define SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
+
+#define SAR_ADC_LAST_RD 0x14
+ #define SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
+ #define SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
+
+#define SAR_ADC_FIFO_RD 0x18
+ #define SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
+ #define SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
+
+#define SAR_ADC_AUX_SW 0x1c
+ #define SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
+ (GENMASK(10, 8) << ((_chan - 2) * 2))
+ #define SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
+ #define SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
+ #define SAR_ADC_AUX_SW_MODE_SEL BIT(4)
+ #define SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
+ #define SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
+ #define SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
+ #define SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
+
+#define SAR_ADC_CHAN_10_SW 0x20
+ #define SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
+ #define SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
+ #define SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
+
+#define SAR_ADC_DETECT_IDLE_SW 0x24
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK GENMASK(25, 23)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_P_MUX BIT(22)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_N_MUX BIT(21)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YP_DRIVE_SW BIT(19)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XP_DRIVE_SW BIT(18)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YM_DRIVE_SW BIT(17)
+ #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XM_DRIVE_SW BIT(16)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK GENMASK(9, 7)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_P_MUX BIT(6)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_N_MUX BIT(5)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YP_DRIVE_SW BIT(3)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XP_DRIVE_SW BIT(2)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YM_DRIVE_SW BIT(1)
+ #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XM_DRIVE_SW BIT(0)
+
+#define SAR_ADC_DELTA_10 0x28
+ #define SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
+ #define SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
+ #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_SHIFT 16
+ #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
+ #define SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
+ #define SAR_ADC_DELTA_10_TS_C_SHIFT 11
+ #define SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
+ #define SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
+ #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_SHIFT 0
+ #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
+
+/*
+ * NOTE: registers from here are undocumented (the vendor Linux kernel driver
+ * and u-boot source served as reference). These only seem to be relevant on
+ * GXBB and newer.
+ */
+#define SAR_ADC_REG11 0x2c
+ #define SAR_ADC_REG11_BANDGAP_EN BIT(13)
+
+#define SAR_ADC_REG13 0x34
+ #define SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
+
+#define SAR_ADC_MAX_FIFO_SIZE 32
+
+#define MESON_SAR_ADC_CHAN(_chan, _type) { \
+ .type = _type, \
+ .indexed = true, \
+ .channel = _chan, \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
+ BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
+ .datasheet_name = "SAR_ADC_CH"#_chan, \
+}
+
+/*
+ * TODO: the hardware supports IIO_TEMP for channel 6 as well which is
+ * currently not supported by this driver.
+ */
+static const struct iio_chan_spec meson_saradc_iio_channels[] = {
+ MESON_SAR_ADC_CHAN(0, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(1, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(2, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(3, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(4, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(5, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(6, IIO_VOLTAGE),
+ MESON_SAR_ADC_CHAN(7, IIO_VOLTAGE),
+ IIO_CHAN_SOFT_TIMESTAMP(8),
+};
+
+enum meson_saradc_avg_mode {
+ NO_AVERAGING = 0x0,
+ MEAN_AVERAGING = 0x1,
+ MEDIAN_AVERAGING = 0x2,
+};
+
+enum meson_saradc_num_samples {
+ ONE_SAMPLE = 0x0,
+ TWO_SAMPLES = 0x1,
+ FOUR_SAMPLES = 0x2,
+ EIGHT_SAMPLES = 0x3,
+};
+
+enum meson_saradc_chan7_mux_sel {
+ CHAN7_MUX_VSS = 0x0,
+ CHAN7_MUX_VDD_DIV4 = 0x1,
+ CHAN7_MUX_VDD_DIV2 = 0x2,
+ CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
+ CHAN7_MUX_VDD = 0x4,
+ CHAN7_MUX_CH7_INPUT = 0x7,
+};
+
+struct meson_saradc_data {
+ unsigned int resolution;
+ const char *name;
+};
+
+struct meson_saradc_priv {
+ struct regmap *regmap;
+ struct regulator *vref;
+ const struct meson_saradc_data *data;
+ struct clk *clkin;
+ struct clk *core_clk;
+ struct clk *sana_clk;
+ struct clk *adc_sel_clk;
+ struct clk *adc_clk;
+ struct clk_gate clk_gate;
+ struct clk *adc_div_clk;
+ struct clk_divider clk_div;
+};
+
+static const struct regmap_config meson_saradc_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = SAR_ADC_REG13,
+};
+
+static unsigned int meson_saradc_get_fifo_count(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
+
+ return FIELD_GET(SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
+}
+
+static int meson_saradc_wait_busy_clear(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int regval, timeout = 10000;
+
+ /*
+ * NOTE: we need a small delay before reading the status, otherwise
+ * the sample engine may not have started internally (which would
+ * seem to us that sampling is already finished).
+ */
+ do {
+ udelay(1);
+ regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
+ } while (FIELD_GET(SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
+
+ if (timeout < 0)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static int meson_saradc_read_raw_sample(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ int *val)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0;
+
+ ret = meson_saradc_wait_busy_clear(indio_dev);
+ if (ret)
+ return ret;
+
+ while (meson_saradc_get_fifo_count(indio_dev) > 0 &&
+ count < SAR_ADC_MAX_FIFO_SIZE) {
+ regmap_read(priv->regmap, SAR_ADC_FIFO_RD, ®val);
+
+ fifo_chan = FIELD_GET(SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
+ if (fifo_chan == chan->channel) {
+ fifo_val = FIELD_GET(SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK,
+ regval);
+ fifo_val &= (BIT(priv->data->resolution) - 1);
+
+ sum += fifo_val;
+ count++;
+ }
+ }
+
+ if (!count)
+ return -ENOENT;
+
+ *val = sum / count;
+
+ return 0;
+}
+
+static void meson_saradc_set_averaging(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ enum meson_saradc_avg_mode mode,
+ enum meson_saradc_num_samples samples)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 val;
+
+ val = samples << SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
+ SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(chan->channel),
+ val);
+
+ val = mode << SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
+ SAR_ADC_AVG_CNTL_AVG_MODE_MASK(chan->channel), val);
+}
+
+static void meson_saradc_enable_channel(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ /* the SAR ADC engine allows sampling multiple channels at the same
+ * time. to keep it simple we're only working with one *internal*
+ * channel, which starts counting at index 0 (which means: count = 1).
+ */
+ regval = FIELD_PREP(SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
+ regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
+ SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
+
+ /* map channel index 0 to the channel which we want to read */
+ regval = FIELD_PREP(SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
+ SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), regval);
+
+ regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
+ chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
+ SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
+ regval);
+
+ regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
+ chan->channel);
+ regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
+ SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
+ regval);
+
+ if (chan->channel == 6)
+ regmap_update_bits(priv->regmap, SAR_ADC_DELTA_10,
+ SAR_ADC_DELTA_10_TEMP_SEL, 0);
+}
+
+static void meson_saradc_set_channel7_mux(struct iio_dev *indio_dev,
+ enum meson_saradc_chan7_mux_sel sel)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ regval = FIELD_PREP(SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3,
+ SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
+
+ usleep_range(10, 20);
+}
+
+static void meson_saradc_start_sample_engine(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
+ SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLING_START,
+ SAR_ADC_REG0_SAMPLING_START);
+}
+
+static void meson_saradc_stop_sample_engine(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLING_STOP,
+ SAR_ADC_REG0_SAMPLING_STOP);
+
+ /* wait until all modules are stopped */
+ meson_saradc_wait_busy_clear(indio_dev);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
+}
+
+static void meson_saradc_lock(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int val;
+
+ mutex_lock(&indio_dev->mlock);
+
+ /* prevent BL30 from using the SAR ADC while we are using it */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_KERNEL_BUSY,
+ SAR_ADC_DELAY_KERNEL_BUSY);
+
+ /* wait until BL30 releases it's lock (so we can use the SAR ADC) */
+ do {
+ udelay(1);
+ regmap_read(priv->regmap, SAR_ADC_DELAY, &val);
+ } while (val & SAR_ADC_DELAY_BL30_BUSY);
+}
+
+static void meson_saradc_unlock(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ /* allow BL30 to use the SAR ADC again */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_KERNEL_BUSY, 0);
+
+ mutex_unlock(&indio_dev->mlock);
+}
+
+static void meson_saradc_clear_fifo(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int count;
+
+ for (count = 0; count < SAR_ADC_MAX_FIFO_SIZE; count++) {
+ if (!meson_saradc_get_fifo_count(indio_dev))
+ break;
+
+ regmap_read(priv->regmap, SAR_ADC_FIFO_RD, 0);
+ }
+}
+
+static int meson_saradc_get_sample(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ enum meson_saradc_avg_mode avg_mode,
+ enum meson_saradc_num_samples avg_samples,
+ int *val)
+{
+ int ret;
+
+ meson_saradc_lock(indio_dev);
+
+ /* clear the FIFO to make sure we're not reading old values */
+ meson_saradc_clear_fifo(indio_dev);
+
+ meson_saradc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
+
+ meson_saradc_enable_channel(indio_dev, chan);
+
+ meson_saradc_start_sample_engine(indio_dev);
+ ret = meson_saradc_read_raw_sample(indio_dev, chan, val);
+ meson_saradc_stop_sample_engine(indio_dev);
+
+ meson_saradc_unlock(indio_dev);
+
+ if (ret) {
+ dev_warn(indio_dev->dev.parent,
+ "failed to read sample for channel %d: %d\n",
+ chan->channel, ret);
+ return ret;
+ }
+
+ return IIO_VAL_INT;
+}
+
+static int meson_saradc_iio_info_read_raw(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ int *val, int *val2, long mask)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int ret;
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ return meson_saradc_get_sample(indio_dev, chan, NO_AVERAGING,
+ ONE_SAMPLE, val);
+ break;
+
+ case IIO_CHAN_INFO_AVERAGE_RAW:
+ return meson_saradc_get_sample(indio_dev, chan, MEAN_AVERAGING,
+ EIGHT_SAMPLES, val);
+ break;
+
+ case IIO_CHAN_INFO_SCALE:
+ ret = regulator_get_voltage(priv->vref);
+ if (ret < 0) {
+ dev_err(indio_dev->dev.parent,
+ "failed to get vref voltage: %d\n", ret);
+ return ret;
+ }
+
+ *val = ret / 1000;
+ *val2 = priv->data->resolution;
+ return IIO_VAL_FRACTIONAL_LOG2;
+
+ default:
+ return -EINVAL;
+ }
+}
+
+static int meson_saradc_clk_init(struct iio_dev *indio_dev, void __iomem *base)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ struct clk_init_data init;
+ const char *clk_parents[1];
+
+ init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_div",
+ of_node_full_name(indio_dev->dev.of_node));
+ init.flags = 0;
+ init.ops = &clk_divider_ops;
+ clk_parents[0] = __clk_get_name(priv->clkin);
+ init.parent_names = clk_parents;
+ init.num_parents = 1;
+
+ priv->clk_div.reg = base + SAR_ADC_REG3;
+ priv->clk_div.shift = SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
+ priv->clk_div.width = SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
+ priv->clk_div.hw.init = &init;
+ priv->clk_div.flags = 0;
+
+ priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
+ &priv->clk_div.hw);
+ if (WARN_ON(IS_ERR(priv->adc_div_clk)))
+ return PTR_ERR(priv->adc_div_clk);
+
+ init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_en",
+ of_node_full_name(indio_dev->dev.of_node));
+ init.flags = CLK_SET_RATE_PARENT;
+ init.ops = &clk_gate_ops;
+ clk_parents[0] = __clk_get_name(priv->adc_div_clk);
+ init.parent_names = clk_parents;
+ init.num_parents = 1;
+
+ priv->clk_gate.reg = base + SAR_ADC_REG3;
+ priv->clk_gate.bit_idx = fls(SAR_ADC_REG3_CLK_EN);
+ priv->clk_gate.hw.init = &init;
+
+ priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
+ if (WARN_ON(IS_ERR(priv->adc_clk)))
+ return PTR_ERR(priv->adc_clk);
+
+ return 0;
+}
+
+static int meson_saradc_init(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int regval, ret;
+
+ /*
+ * make sure we start at CH7 input since the other muxes are only used
+ * for internal calibration.
+ */
+ meson_saradc_set_channel7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
+
+ /*
+ * leave sampling delay and the input clocks as configured by BL30 to
+ * make sure BL30 gets the values it expects when reading the
+ * temperature sensor.
+ */
+ regmap_read(priv->regmap, SAR_ADC_REG3, ®val);
+ if (regval & SAR_ADC_REG3_BL30_INITIALIZED)
+ return 0;
+
+ meson_saradc_stop_sample_engine(indio_dev);
+
+ /* update the channel 6 MUX to select the temperature sensor */
+ regmap_update_bits(priv->regmap, SAR_ADC_REG0,
+ SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
+ SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
+
+ /* disable all channels by default */
+ regmap_write(priv->regmap, SAR_ADC_CHAN_LIST, 0x0);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3,
+ SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3,
+ SAR_ADC_REG3_CNTL_USE_SC_DLY,
+ SAR_ADC_REG3_CNTL_USE_SC_DLY);
+
+ /* delay between two samples = (10+1) * 1uS */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK, 10));
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 0));
+
+ /* delay between two samples = (10+1) * 1uS */
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 10));
+ regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
+ SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
+ FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 1));
+
+ ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
+ if (ret) {
+ dev_err(indio_dev->dev.parent,
+ "failed to set adc parent to clkin\n");
+ return ret;
+ }
+
+ ret = clk_set_rate(priv->adc_clk, 1200000);
+ if (ret) {
+ dev_err(indio_dev->dev.parent,
+ "failed to set adc clock rate\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int meson_saradc_hw_enable(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+ int ret;
+
+ meson_saradc_lock(indio_dev);
+
+ ret = regulator_enable(priv->vref);
+ if (ret < 0) {
+ dev_err(indio_dev->dev.parent,
+ "failed to enable vref regulator\n");
+ goto err_vref;
+ }
+
+ ret = clk_prepare_enable(priv->core_clk);
+ if (ret) {
+ dev_err(indio_dev->dev.parent, "failed to enable core clk\n");
+ goto err_core_clk;
+ }
+
+ ret = clk_prepare_enable(priv->sana_clk);
+ if (ret) {
+ dev_err(indio_dev->dev.parent, "failed to enable sana clk\n");
+ goto err_sana_clk;
+ }
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG11,
+ SAR_ADC_REG11_BANDGAP_EN, SAR_ADC_REG11_BANDGAP_EN);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN,
+ SAR_ADC_REG3_ADC_EN);
+
+ udelay(5);
+
+ ret = clk_prepare_enable(priv->adc_clk);
+ if (ret) {
+ dev_err(indio_dev->dev.parent, "failed to enable adc clk\n");
+ goto err_adc_clk;
+ }
+
+ meson_saradc_unlock(indio_dev);
+
+ return 0;
+
+err_adc_clk:
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN, 0);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG11,
+ SAR_ADC_REG11_BANDGAP_EN, 0);
+ clk_disable_unprepare(priv->sana_clk);
+err_sana_clk:
+ clk_disable_unprepare(priv->core_clk);
+err_core_clk:
+ regulator_disable(priv->vref);
+err_vref:
+ meson_saradc_unlock(indio_dev);
+ return ret;
+}
+
+static void meson_saradc_hw_disable(struct iio_dev *indio_dev)
+{
+ struct meson_saradc_priv *priv = iio_priv(indio_dev);
+
+ meson_saradc_lock(indio_dev);
+
+ clk_disable_unprepare(priv->adc_clk);
+
+ regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN, 0);
+ regmap_update_bits(priv->regmap, SAR_ADC_REG11,
+ SAR_ADC_REG11_BANDGAP_EN, 0);
+
+ clk_disable_unprepare(priv->sana_clk);
+ clk_disable_unprepare(priv->core_clk);
+
+ regulator_disable(priv->vref);
+
+ meson_saradc_unlock(indio_dev);
+}
+
+static const struct iio_info meson_saradc_iio_info = {
+ .read_raw = meson_saradc_iio_info_read_raw,
+ .driver_module = THIS_MODULE,
+};
+
+struct meson_saradc_data meson_saradc_gxbb_data = {
+ .resolution = 10,
+ .name = "meson-gxbb-saradc",
+};
+
+struct meson_saradc_data meson_saradc_gxl_data = {
+ .resolution = 12,
+ .name = "meson-gxl-saradc",
+};
+
+static const struct of_device_id meson_saradc_of_match[] = {
+ {
+ .compatible = "amlogic,meson-gxbb-saradc",
+ .data = &meson_saradc_gxbb_data,
+ }, {
+ .compatible = "amlogic,meson-gxl-saradc",
+ .data = &meson_saradc_gxl_data,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, meson_saradc_of_match);
+
+static int meson_saradc_probe(struct platform_device *pdev)
+{
+ struct meson_saradc_priv *priv;
+ struct iio_dev *indio_dev;
+ struct resource *res;
+ void __iomem *base;
+ const struct of_device_id *match;
+ int ret;
+
+ indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
+ if (!indio_dev) {
+ dev_err(&pdev->dev, "failed allocating iio device\n");
+ return -ENOMEM;
+ }
+
+ priv = iio_priv(indio_dev);
+
+ match = of_match_device(meson_saradc_of_match, &pdev->dev);
+ priv->data = match->data;
+
+ indio_dev->name = priv->data->name;
+ indio_dev->dev.parent = &pdev->dev;
+ indio_dev->dev.of_node = pdev->dev.of_node;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->info = &meson_saradc_iio_info;
+
+ indio_dev->channels = meson_saradc_iio_channels;
+ indio_dev->num_channels = ARRAY_SIZE(meson_saradc_iio_channels);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
+ &meson_saradc_regmap_config);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+ priv->clkin = devm_clk_get(&pdev->dev, "clkin");
+ if (IS_ERR(priv->clkin)) {
+ dev_err(&pdev->dev, "failed to get clkin\n");
+ return PTR_ERR(priv->clkin);
+ }
+
+ priv->core_clk = devm_clk_get(&pdev->dev, "core");
+ if (IS_ERR(priv->core_clk)) {
+ dev_err(&pdev->dev, "failed to get core clk\n");
+ return PTR_ERR(priv->core_clk);
+ }
+
+ priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
+ if (IS_ERR(priv->sana_clk)) {
+ if (PTR_ERR(priv->sana_clk) == -ENOENT) {
+ priv->sana_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get sana clk\n");
+ return PTR_ERR(priv->sana_clk);
+ }
+ }
+
+ priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
+ if (IS_ERR(priv->adc_clk)) {
+ if (PTR_ERR(priv->adc_clk) == -ENOENT) {
+ priv->adc_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get adc clk\n");
+ return PTR_ERR(priv->adc_clk);
+ }
+ }
+
+ priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
+ if (IS_ERR(priv->adc_sel_clk)) {
+ if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
+ priv->adc_sel_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get adc_sel clk\n");
+ return PTR_ERR(priv->adc_sel_clk);
+ }
+ }
+
+ /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
+ if (!priv->adc_clk) {
+ ret = meson_saradc_clk_init(indio_dev, base);
+ if (ret)
+ return ret;
+ }
+
+ priv->vref = devm_regulator_get(&pdev->dev, "vref");
+ if (IS_ERR(priv->vref)) {
+ dev_err(&pdev->dev, "failed to get vref regulator\n");
+ return PTR_ERR(priv->vref);
+ }
+
+ ret = meson_saradc_init(indio_dev);
+ if (ret)
+ goto err;
+
+ ret = meson_saradc_hw_enable(indio_dev);
+ if (ret)
+ goto err;
+
+ platform_set_drvdata(pdev, indio_dev);
+
+ ret = iio_device_register(indio_dev);
+ if (ret)
+ goto err_hw;
+
+ return 0;
+
+err_hw:
+ meson_saradc_hw_disable(indio_dev);
+err:
+ return ret;
+}
+
+static int meson_saradc_remove(struct platform_device *pdev)
+{
+ struct iio_dev *indio_dev = platform_get_drvdata(pdev);
+
+ meson_saradc_hw_disable(indio_dev);
+ iio_device_unregister(indio_dev);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int meson_saradc_suspend(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+
+ meson_saradc_hw_disable(indio_dev);
+
+ return 0;
+}
+
+static int meson_saradc_resume(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+
+ return meson_saradc_hw_enable(indio_dev);
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(meson_saradc_pm_ops,
+ meson_saradc_suspend, meson_saradc_resume);
+
+static struct platform_driver meson_saradc_driver = {
+ .probe = meson_saradc_probe,
+ .remove = meson_saradc_remove,
+ .driver = {
+ .name = "meson-saradc",
+ .of_match_table = meson_saradc_of_match,
+ .pm = &meson_saradc_pm_ops,
+ },
+};
+
+module_platform_driver(meson_saradc_driver);
+
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
+MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
+MODULE_LICENSE("GPL v2");
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 4/4] ARM64: dts: meson: meson-gx: add the SAR ADC
2017-01-15 22:42 ` Martin Blumenstingl
(?)
@ 2017-01-15 22:42 ` Martin Blumenstingl
-1 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-15 22:42 UTC (permalink / raw)
To: jic23, knaack.h, lars, pmeerw, robh+dt, mark.rutland, khilman,
linux-iio, devicetree, linux-amlogic, linux-clk
Cc: carlo, catalin.marinas, will.deacon, mturquette, sboyd,
narmstrong, linux-arm-kernel, Martin Blumenstingl
Add the SAR ADC to meson-gxbb.dtsi and meson-gxl.dtsi. GXBB provides a
10-bit ADC while GXL (and GXM, which uses the same ADC as GXL) provides
a 12-bit ADC.
Some boards use resistor ladder buttons connected through one of the ADC
channels. On newer devices (GXL and GXM) some boards use pull-ups/downs
to change the resistance (and thus the ADC value) on of the ADC channels
to indicate the board revision.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 ++++++++
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 ++++++++++
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 ++++++++++
3 files changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index cddad8c795ec..041e4f0ed7d7 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -237,6 +237,14 @@
status = "disabled";
};
+ saradc: adc@8680 {
+ compatible = "amlogic,meson-saradc";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ reg = <0x0 0x8680 0x0 0x34>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
+ };
+
pwm_ef: pwm@86c0 {
compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
reg = <0x0 0x086c0 0x0 0x10>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 5d686334f692..114d7e1c9fc0 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -429,6 +429,16 @@
clocks = <&clkc CLKID_I2C>;
};
+&saradc {
+ compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+};
+
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index bb2842f8a08f..6b63296b6c60 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -273,6 +273,16 @@
clocks = <&clkc CLKID_I2C>;
};
+&saradc {
+ compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+};
+
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 4/4] ARM64: dts: meson: meson-gx: add the SAR ADC
@ 2017-01-15 22:42 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-15 22:42 UTC (permalink / raw)
To: linux-arm-kernel
Add the SAR ADC to meson-gxbb.dtsi and meson-gxl.dtsi. GXBB provides a
10-bit ADC while GXL (and GXM, which uses the same ADC as GXL) provides
a 12-bit ADC.
Some boards use resistor ladder buttons connected through one of the ADC
channels. On newer devices (GXL and GXM) some boards use pull-ups/downs
to change the resistance (and thus the ADC value) on of the ADC channels
to indicate the board revision.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 ++++++++
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 ++++++++++
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 ++++++++++
3 files changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index cddad8c795ec..041e4f0ed7d7 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -237,6 +237,14 @@
status = "disabled";
};
+ saradc: adc at 8680 {
+ compatible = "amlogic,meson-saradc";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ reg = <0x0 0x8680 0x0 0x34>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
+ };
+
pwm_ef: pwm at 86c0 {
compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
reg = <0x0 0x086c0 0x0 0x10>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 5d686334f692..114d7e1c9fc0 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -429,6 +429,16 @@
clocks = <&clkc CLKID_I2C>;
};
+&saradc {
+ compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+};
+
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index bb2842f8a08f..6b63296b6c60 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -273,6 +273,16 @@
clocks = <&clkc CLKID_I2C>;
};
+&saradc {
+ compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+};
+
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 4/4] ARM64: dts: meson: meson-gx: add the SAR ADC
@ 2017-01-15 22:42 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-15 22:42 UTC (permalink / raw)
To: linus-amlogic
Add the SAR ADC to meson-gxbb.dtsi and meson-gxl.dtsi. GXBB provides a
10-bit ADC while GXL (and GXM, which uses the same ADC as GXL) provides
a 12-bit ADC.
Some boards use resistor ladder buttons connected through one of the ADC
channels. On newer devices (GXL and GXM) some boards use pull-ups/downs
to change the resistance (and thus the ADC value) on of the ADC channels
to indicate the board revision.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 ++++++++
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 ++++++++++
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 ++++++++++
3 files changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index cddad8c795ec..041e4f0ed7d7 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -237,6 +237,14 @@
status = "disabled";
};
+ saradc: adc at 8680 {
+ compatible = "amlogic,meson-saradc";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ reg = <0x0 0x8680 0x0 0x34>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
+ };
+
pwm_ef: pwm at 86c0 {
compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
reg = <0x0 0x086c0 0x0 0x10>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 5d686334f692..114d7e1c9fc0 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -429,6 +429,16 @@
clocks = <&clkc CLKID_I2C>;
};
+&saradc {
+ compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+};
+
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index bb2842f8a08f..6b63296b6c60 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -273,6 +273,16 @@
clocks = <&clkc CLKID_I2C>;
};
+&saradc {
+ compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+};
+
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* Re: [PATCH v2 0/4] Amlogic Meson SAR ADC support
2017-01-15 22:42 ` Martin Blumenstingl
(?)
(?)
@ 2017-01-16 10:18 ` Neil Armstrong
-1 siblings, 0 replies; 110+ messages in thread
From: Neil Armstrong @ 2017-01-16 10:18 UTC (permalink / raw)
To: Martin Blumenstingl, jic23-DgEjT+Ai2ygdnm+yROfE0A,
knaack.h-Mmb7MZpHnFY, lars-Qo5EllUWu/uELgA04lAiVw,
pmeerw-jW+XmwGofnusTnJN9+BGXg, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, khilman-rdvid1DuHRBWk0Htik3J/w,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-clk-u79uwXL29TY76Z2rM5mHXA
Cc: carlo-KA+7E9HrN00dnm+yROfE0A, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, mturquette-rdvid1DuHRBWk0Htik3J/w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 01/15/2017 11:42 PM, Martin Blumenstingl wrote:
> This series add support for the SAR ADC on Amlogic Meson GXBB, GXL and
> GXM SoCs.
> The hardware on GXBB provides 10-bit ADC results, while GXL and GXM are
> providing 12-bit results. Support for older SoCs (Meson8b and Meson8)
> can be added with little effort, most of which is testing I guess (I
> don't have any pre-GXBB hardware so I can't say).
>
> A new set of clocks had to be added to the GXBB clock controller (used
> by the GXBB/GXL/GXM SoCs) which are required to get the ADC working.
>
> The ADC itself can sample multiple channels at the same time and allows
> capturing multiple samples (which can be used for filtering/averaging).
> The ADC results are stored inside a FIFO register. More details on what
> the driver supports (or doesn't) can be found in the description of
> patch #3.
>
> The code is based on the public S805 (Meson8b) and S905 (GXBB)
> datasheets, as well as by reading (various versions of) the vendor
> driver and by inspecting the registers on the vendor kernels of my
> testing-hardware.
>
> Typical use-cases for the ADC on the Meson GX SoCs are:
> - adc-keys ("ADC attached resistor ladder buttons")
> - SoC temperature measurement (not supported by this driver yet as
> the system firmware does this already and provides the values via the
> SCPI protocol)
> - "version-strapping" (different resistor values are used to indicate
> the board-revision)
> - and of course typical ADC measurements
>
> Thanks to Heiner Kallweit, Jonathan Cameron and Lars-Peter Clausen for
> reviewing this series and providing valuable input!
>
> Changes since v1 (all changes are for patch #3, except where noted):
> - fix IRQ number in meson-gx.dtsi (thanks to Heiner Kallweit for
> providing the correct value), affects patch #4
> - move the most used members of meson_saradc_priv to the beginning
> - remove unused struct member "completion" from meson_saradc_priv
> - use devm_kasprintf() instead of snprintf() + devm_kstrdup()
> - initialize indio_dev->dev.parent earlier in meson_saradc_probe()
> - moved meson_saradc_clear_fifo() logic to a separate function
> - add comment why a do ... while loop is required in
> meson_saradc_wait_busy_clear()
> - remove SAR_ADC_NUM_CHANNELS and SAR_ADC_VALUE_MASK macros (each of them
> was only used once and it's an unneeded level of abstraction)
> - fixed multiline comment syntax violations
> - dropped unneeded log messages during initialization
> - set iio_dev name to "meson-gxbb-saradc" or "meson-gxl-saradc"
> - use "indio_dev->dev.parent" in all kernel log calls (dev_warn/err/etc)
> to make it show the OF node name (instead of the iio device name)
> - introduce struct meson_saradc_data to hold platform-specific
> information (such as resolution in bits and the iio_dev name)
>
>
> Martin Blumenstingl (4):
> Documentation: dt-bindings: add the Amlogic Meson SAR ADC
> documentation
> clk: gxbb: add the SAR ADC clocks and expose them
> iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
> ARM64: dts: meson: meson-gx: add the SAR ADC
>
> .../bindings/iio/adc/amlogic,meson-saradc.txt | 31 +
> arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 +
> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 +
> arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 +
> drivers/clk/meson/gxbb.c | 48 ++
> drivers/clk/meson/gxbb.h | 9 +-
> drivers/iio/adc/Kconfig | 12 +
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/meson_saradc.c | 893 +++++++++++++++++++++
> include/dt-bindings/clock/gxbb-clkc.h | 4 +
> 10 files changed, 1023 insertions(+), 3 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
> create mode 100644 drivers/iio/adc/meson_saradc.c
>
Good work martin !
Tested on the P200 board with the resistor ladderred key matrix, patch will be posted shortly.
For all the serie :
Tested-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v2 0/4] Amlogic Meson SAR ADC support
@ 2017-01-16 10:18 ` Neil Armstrong
0 siblings, 0 replies; 110+ messages in thread
From: Neil Armstrong @ 2017-01-16 10:18 UTC (permalink / raw)
To: Martin Blumenstingl, jic23, knaack.h, lars, pmeerw, robh+dt,
mark.rutland, khilman, linux-iio, devicetree, linux-amlogic,
linux-clk
Cc: carlo, catalin.marinas, will.deacon, mturquette, sboyd, linux-arm-kernel
On 01/15/2017 11:42 PM, Martin Blumenstingl wrote:
> This series add support for the SAR ADC on Amlogic Meson GXBB, GXL and
> GXM SoCs.
> The hardware on GXBB provides 10-bit ADC results, while GXL and GXM are
> providing 12-bit results. Support for older SoCs (Meson8b and Meson8)
> can be added with little effort, most of which is testing I guess (I
> don't have any pre-GXBB hardware so I can't say).
>
> A new set of clocks had to be added to the GXBB clock controller (used
> by the GXBB/GXL/GXM SoCs) which are required to get the ADC working.
>
> The ADC itself can sample multiple channels at the same time and allows
> capturing multiple samples (which can be used for filtering/averaging).
> The ADC results are stored inside a FIFO register. More details on what
> the driver supports (or doesn't) can be found in the description of
> patch #3.
>
> The code is based on the public S805 (Meson8b) and S905 (GXBB)
> datasheets, as well as by reading (various versions of) the vendor
> driver and by inspecting the registers on the vendor kernels of my
> testing-hardware.
>
> Typical use-cases for the ADC on the Meson GX SoCs are:
> - adc-keys ("ADC attached resistor ladder buttons")
> - SoC temperature measurement (not supported by this driver yet as
> the system firmware does this already and provides the values via the
> SCPI protocol)
> - "version-strapping" (different resistor values are used to indicate
> the board-revision)
> - and of course typical ADC measurements
>
> Thanks to Heiner Kallweit, Jonathan Cameron and Lars-Peter Clausen for
> reviewing this series and providing valuable input!
>
> Changes since v1 (all changes are for patch #3, except where noted):
> - fix IRQ number in meson-gx.dtsi (thanks to Heiner Kallweit for
> providing the correct value), affects patch #4
> - move the most used members of meson_saradc_priv to the beginning
> - remove unused struct member "completion" from meson_saradc_priv
> - use devm_kasprintf() instead of snprintf() + devm_kstrdup()
> - initialize indio_dev->dev.parent earlier in meson_saradc_probe()
> - moved meson_saradc_clear_fifo() logic to a separate function
> - add comment why a do ... while loop is required in
> meson_saradc_wait_busy_clear()
> - remove SAR_ADC_NUM_CHANNELS and SAR_ADC_VALUE_MASK macros (each of them
> was only used once and it's an unneeded level of abstraction)
> - fixed multiline comment syntax violations
> - dropped unneeded log messages during initialization
> - set iio_dev name to "meson-gxbb-saradc" or "meson-gxl-saradc"
> - use "indio_dev->dev.parent" in all kernel log calls (dev_warn/err/etc)
> to make it show the OF node name (instead of the iio device name)
> - introduce struct meson_saradc_data to hold platform-specific
> information (such as resolution in bits and the iio_dev name)
>
>
> Martin Blumenstingl (4):
> Documentation: dt-bindings: add the Amlogic Meson SAR ADC
> documentation
> clk: gxbb: add the SAR ADC clocks and expose them
> iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
> ARM64: dts: meson: meson-gx: add the SAR ADC
>
> .../bindings/iio/adc/amlogic,meson-saradc.txt | 31 +
> arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 +
> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 +
> arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 +
> drivers/clk/meson/gxbb.c | 48 ++
> drivers/clk/meson/gxbb.h | 9 +-
> drivers/iio/adc/Kconfig | 12 +
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/meson_saradc.c | 893 +++++++++++++++++++++
> include/dt-bindings/clock/gxbb-clkc.h | 4 +
> 10 files changed, 1023 insertions(+), 3 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
> create mode 100644 drivers/iio/adc/meson_saradc.c
>
Good work martin !
Tested on the P200 board with the resistor ladderred key matrix, patch will be posted shortly.
For all the serie :
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v2 0/4] Amlogic Meson SAR ADC support
@ 2017-01-16 10:18 ` Neil Armstrong
0 siblings, 0 replies; 110+ messages in thread
From: Neil Armstrong @ 2017-01-16 10:18 UTC (permalink / raw)
To: linux-arm-kernel
On 01/15/2017 11:42 PM, Martin Blumenstingl wrote:
> This series add support for the SAR ADC on Amlogic Meson GXBB, GXL and
> GXM SoCs.
> The hardware on GXBB provides 10-bit ADC results, while GXL and GXM are
> providing 12-bit results. Support for older SoCs (Meson8b and Meson8)
> can be added with little effort, most of which is testing I guess (I
> don't have any pre-GXBB hardware so I can't say).
>
> A new set of clocks had to be added to the GXBB clock controller (used
> by the GXBB/GXL/GXM SoCs) which are required to get the ADC working.
>
> The ADC itself can sample multiple channels at the same time and allows
> capturing multiple samples (which can be used for filtering/averaging).
> The ADC results are stored inside a FIFO register. More details on what
> the driver supports (or doesn't) can be found in the description of
> patch #3.
>
> The code is based on the public S805 (Meson8b) and S905 (GXBB)
> datasheets, as well as by reading (various versions of) the vendor
> driver and by inspecting the registers on the vendor kernels of my
> testing-hardware.
>
> Typical use-cases for the ADC on the Meson GX SoCs are:
> - adc-keys ("ADC attached resistor ladder buttons")
> - SoC temperature measurement (not supported by this driver yet as
> the system firmware does this already and provides the values via the
> SCPI protocol)
> - "version-strapping" (different resistor values are used to indicate
> the board-revision)
> - and of course typical ADC measurements
>
> Thanks to Heiner Kallweit, Jonathan Cameron and Lars-Peter Clausen for
> reviewing this series and providing valuable input!
>
> Changes since v1 (all changes are for patch #3, except where noted):
> - fix IRQ number in meson-gx.dtsi (thanks to Heiner Kallweit for
> providing the correct value), affects patch #4
> - move the most used members of meson_saradc_priv to the beginning
> - remove unused struct member "completion" from meson_saradc_priv
> - use devm_kasprintf() instead of snprintf() + devm_kstrdup()
> - initialize indio_dev->dev.parent earlier in meson_saradc_probe()
> - moved meson_saradc_clear_fifo() logic to a separate function
> - add comment why a do ... while loop is required in
> meson_saradc_wait_busy_clear()
> - remove SAR_ADC_NUM_CHANNELS and SAR_ADC_VALUE_MASK macros (each of them
> was only used once and it's an unneeded level of abstraction)
> - fixed multiline comment syntax violations
> - dropped unneeded log messages during initialization
> - set iio_dev name to "meson-gxbb-saradc" or "meson-gxl-saradc"
> - use "indio_dev->dev.parent" in all kernel log calls (dev_warn/err/etc)
> to make it show the OF node name (instead of the iio device name)
> - introduce struct meson_saradc_data to hold platform-specific
> information (such as resolution in bits and the iio_dev name)
>
>
> Martin Blumenstingl (4):
> Documentation: dt-bindings: add the Amlogic Meson SAR ADC
> documentation
> clk: gxbb: add the SAR ADC clocks and expose them
> iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
> ARM64: dts: meson: meson-gx: add the SAR ADC
>
> .../bindings/iio/adc/amlogic,meson-saradc.txt | 31 +
> arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 +
> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 +
> arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 +
> drivers/clk/meson/gxbb.c | 48 ++
> drivers/clk/meson/gxbb.h | 9 +-
> drivers/iio/adc/Kconfig | 12 +
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/meson_saradc.c | 893 +++++++++++++++++++++
> include/dt-bindings/clock/gxbb-clkc.h | 4 +
> 10 files changed, 1023 insertions(+), 3 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
> create mode 100644 drivers/iio/adc/meson_saradc.c
>
Good work martin !
Tested on the P200 board with the resistor ladderred key matrix, patch will be posted shortly.
For all the serie :
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v2 0/4] Amlogic Meson SAR ADC support
@ 2017-01-16 10:18 ` Neil Armstrong
0 siblings, 0 replies; 110+ messages in thread
From: Neil Armstrong @ 2017-01-16 10:18 UTC (permalink / raw)
To: linus-amlogic
On 01/15/2017 11:42 PM, Martin Blumenstingl wrote:
> This series add support for the SAR ADC on Amlogic Meson GXBB, GXL and
> GXM SoCs.
> The hardware on GXBB provides 10-bit ADC results, while GXL and GXM are
> providing 12-bit results. Support for older SoCs (Meson8b and Meson8)
> can be added with little effort, most of which is testing I guess (I
> don't have any pre-GXBB hardware so I can't say).
>
> A new set of clocks had to be added to the GXBB clock controller (used
> by the GXBB/GXL/GXM SoCs) which are required to get the ADC working.
>
> The ADC itself can sample multiple channels at the same time and allows
> capturing multiple samples (which can be used for filtering/averaging).
> The ADC results are stored inside a FIFO register. More details on what
> the driver supports (or doesn't) can be found in the description of
> patch #3.
>
> The code is based on the public S805 (Meson8b) and S905 (GXBB)
> datasheets, as well as by reading (various versions of) the vendor
> driver and by inspecting the registers on the vendor kernels of my
> testing-hardware.
>
> Typical use-cases for the ADC on the Meson GX SoCs are:
> - adc-keys ("ADC attached resistor ladder buttons")
> - SoC temperature measurement (not supported by this driver yet as
> the system firmware does this already and provides the values via the
> SCPI protocol)
> - "version-strapping" (different resistor values are used to indicate
> the board-revision)
> - and of course typical ADC measurements
>
> Thanks to Heiner Kallweit, Jonathan Cameron and Lars-Peter Clausen for
> reviewing this series and providing valuable input!
>
> Changes since v1 (all changes are for patch #3, except where noted):
> - fix IRQ number in meson-gx.dtsi (thanks to Heiner Kallweit for
> providing the correct value), affects patch #4
> - move the most used members of meson_saradc_priv to the beginning
> - remove unused struct member "completion" from meson_saradc_priv
> - use devm_kasprintf() instead of snprintf() + devm_kstrdup()
> - initialize indio_dev->dev.parent earlier in meson_saradc_probe()
> - moved meson_saradc_clear_fifo() logic to a separate function
> - add comment why a do ... while loop is required in
> meson_saradc_wait_busy_clear()
> - remove SAR_ADC_NUM_CHANNELS and SAR_ADC_VALUE_MASK macros (each of them
> was only used once and it's an unneeded level of abstraction)
> - fixed multiline comment syntax violations
> - dropped unneeded log messages during initialization
> - set iio_dev name to "meson-gxbb-saradc" or "meson-gxl-saradc"
> - use "indio_dev->dev.parent" in all kernel log calls (dev_warn/err/etc)
> to make it show the OF node name (instead of the iio device name)
> - introduce struct meson_saradc_data to hold platform-specific
> information (such as resolution in bits and the iio_dev name)
>
>
> Martin Blumenstingl (4):
> Documentation: dt-bindings: add the Amlogic Meson SAR ADC
> documentation
> clk: gxbb: add the SAR ADC clocks and expose them
> iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
> ARM64: dts: meson: meson-gx: add the SAR ADC
>
> .../bindings/iio/adc/amlogic,meson-saradc.txt | 31 +
> arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 +
> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 +
> arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 +
> drivers/clk/meson/gxbb.c | 48 ++
> drivers/clk/meson/gxbb.h | 9 +-
> drivers/iio/adc/Kconfig | 12 +
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/meson_saradc.c | 893 +++++++++++++++++++++
> include/dt-bindings/clock/gxbb-clkc.h | 4 +
> 10 files changed, 1023 insertions(+), 3 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
> create mode 100644 drivers/iio/adc/meson_saradc.c
>
Good work martin !
Tested on the P200 board with the resistor ladderred key matrix, patch will be posted shortly.
For all the serie :
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v2 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
2017-01-15 22:42 ` Martin Blumenstingl
@ 2017-01-16 17:41 ` Peter Meerwald-Stadler
-1 siblings, 0 replies; 110+ messages in thread
From: Peter Meerwald-Stadler @ 2017-01-16 17:41 UTC (permalink / raw)
To: Martin Blumenstingl; +Cc: jic23, lars, linux-iio, linux-amlogic
> This adds support for the SAR (Successive Approximation Register) ADC
> on the Amlogic Meson SoCs.
minor comments below
> The code is based on the public S805 (Meson8b) and S905 (GXBB)
> datasheets (see [0] and [1]), as well as by reading (various versions
> of) the vendor driver and by inspecting the registers on the vendor
> kernels of my testing-hardware.
>
> Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
> 10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
> The code was written to support older SoCs (Meson8 and Meson8b) as well,
> but due to lack of actual testing-hardware no of_device_id was added for
> these.
>
> Two "features" from the vendor driver are currently missing:
> - the vendor driver uses channel #7 for calibration (this improves the
> accuracy of the results - in my tests the results were less than 3%
> off without calibration compared to the vendor driver). Adding support
> for this should be easy, but is not required for most applications.
> - channel #6 is connected to the SoCs internal temperature sensor.
> Adding support for this is probably not so easy since (based on the
> u-boot sources) most SoC versions are using different registers and
> algorithms for the conversion from "ADC value" to temperature.
>
> Supported by the hardware but currently not supported by the driver:
> - reading multiple channels at the same time (the hardware has a FIFO
> buffer which stores multiple results)
> - continuous sampling (this would require a way to enable this
> individually because otherwise the ADC would be drawing power
> constantly)
> - interrupt support (similar to the vendor driver this new driver is
> polling the results. It is unclear if the IRQ-mode is supported on
> older (Meson6 or Meson8) hardware as well or if there are any errata)
>
> [0]
> http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
> [1] http://dn.odroid.com/S905/DataSheet/S905_Public_Datasheet_V1.1.4.pdf
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
> drivers/iio/adc/Kconfig | 12 +
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/meson_saradc.c | 893 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 906 insertions(+)
> create mode 100644 drivers/iio/adc/meson_saradc.c
>
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index 9c8b558ba19e..86059b9b91bf 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -371,6 +371,18 @@ config MEN_Z188_ADC
> This driver can also be built as a module. If so, the module will be
> called men_z188_adc.
>
> +config MESON_SARADC
> + tristate "Amlogic Meson SAR ADC driver"
> + default ARCH_MESON
> + depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
> + select REGMAP_MMIO
> + help
> + Say yes here to build support for the SAR ADC found in Amlogic Meson
> + SoCs.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called meson_saradc.
> +
> config MXS_LRADC
> tristate "Freescale i.MX23/i.MX28 LRADC"
> depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
> index d36c4be8d1fc..de05b9e75f8f 100644
> --- a/drivers/iio/adc/Makefile
> +++ b/drivers/iio/adc/Makefile
> @@ -36,6 +36,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
> obj-$(CONFIG_MCP3422) += mcp3422.o
> obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
> obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
> +obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
> obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
> obj-$(CONFIG_NAU7802) += nau7802.o
> obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
> diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
> new file mode 100644
> index 000000000000..4c189e5fd7cc
> --- /dev/null
> +++ b/drivers/iio/adc/meson_saradc.c
> @@ -0,0 +1,893 @@
> +/*
> + * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
> + *
> + * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/iio/iio.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/regulator/consumer.h>
> +
> +#define SAR_ADC_REG0 0x00
prefix should be MESON_SARADC_ (making it even longer, doe MESON_ADC_
perhaps)
> + #define SAR_ADC_REG0_PANEL_DETECT BIT(31)
> + #define SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
> + #define SAR_ADC_REG0_DELTA_BUSY BIT(30)
> + #define SAR_ADC_REG0_AVG_BUSY BIT(29)
> + #define SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
> + #define SAR_ADC_REG0_FIFO_FULL BIT(27)
> + #define SAR_ADC_REG0_FIFO_EMPTY BIT(26)
> + #define SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
> + #define SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
> + #define SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
> + #define SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
> + #define SAR_ADC_REG0_SAMPLING_STOP BIT(14)
> + #define SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
> + #define SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
> + #define SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
> + #define SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
> + #define SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
> + #define SAR_ADC_REG0_SAMPLING_START BIT(2)
> + #define SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
> + #define SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
> +
> +#define SAR_ADC_CHAN_LIST 0x04
> + #define SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
> + #define SAR_ADC_CHAN_CHAN_ENTRY_MASK(_chan) \
> + (GENMASK(2, 0) << (_chan * 3))
maybe parenthesis around _chan for extra MACRO safety
> +
> +#define SAR_ADC_AVG_CNTL 0x08
> + #define SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
> + (16 + (_chan * 2))
> + #define SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
> + (GENMASK(17, 16) << (_chan * 2))
> + #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
> + (0 + (_chan * 2))
> + #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
> + (GENMASK(1, 0) << (_chan * 2))
> +
> +#define SAR_ADC_REG3 0x0c
> + #define SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
> + #define SAR_ADC_REG3_CLK_EN BIT(30)
> + #define SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
> + #define SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
> + #define SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
> + #define SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
> + #define SAR_ADC_REG3_DETECT_EN BIT(22)
> + #define SAR_ADC_REG3_ADC_EN BIT(21)
> + #define SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
> + #define SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
> + #define SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
> + #define SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
> + #define SAR_ADC_REG3_ADC_CLK_DIV_MASK GENMASK(15, 10)
15 would be _SHIFT + _WIDTH?
> + #define SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
> + #define SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
> +
> +#define SAR_ADC_DELAY 0x10
> + #define SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
> + #define SAR_ADC_DELAY_BL30_BUSY BIT(15)
> + #define SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
> + #define SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
> + #define SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
> + #define SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
> +
> +#define SAR_ADC_LAST_RD 0x14
> + #define SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
> + #define SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
> +
> +#define SAR_ADC_FIFO_RD 0x18
> + #define SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
> + #define SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
> +
> +#define SAR_ADC_AUX_SW 0x1c
> + #define SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
> + (GENMASK(10, 8) << ((_chan - 2) * 2))
> + #define SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
> + #define SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
> + #define SAR_ADC_AUX_SW_MODE_SEL BIT(4)
> + #define SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
> + #define SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
> + #define SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
> + #define SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
> +
> +#define SAR_ADC_CHAN_10_SW 0x20
> + #define SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
> +
> +#define SAR_ADC_DETECT_IDLE_SW 0x24
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK GENMASK(25, 23)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_P_MUX BIT(22)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_N_MUX BIT(21)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YP_DRIVE_SW BIT(19)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XP_DRIVE_SW BIT(18)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YM_DRIVE_SW BIT(17)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XM_DRIVE_SW BIT(16)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK GENMASK(9, 7)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_P_MUX BIT(6)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_N_MUX BIT(5)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YP_DRIVE_SW BIT(3)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XP_DRIVE_SW BIT(2)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YM_DRIVE_SW BIT(1)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XM_DRIVE_SW BIT(0)
> +
> +#define SAR_ADC_DELTA_10 0x28
> + #define SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
> + #define SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
> + #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_SHIFT 16
> + #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
> + #define SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
> + #define SAR_ADC_DELTA_10_TS_C_SHIFT 11
> + #define SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
> + #define SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
> + #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_SHIFT 0
> + #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
> +
> +/*
> + * NOTE: registers from here are undocumented (the vendor Linux kernel driver
> + * and u-boot source served as reference). These only seem to be relevant on
> + * GXBB and newer.
> + */
> +#define SAR_ADC_REG11 0x2c
> + #define SAR_ADC_REG11_BANDGAP_EN BIT(13)
> +
> +#define SAR_ADC_REG13 0x34
> + #define SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
> +
> +#define SAR_ADC_MAX_FIFO_SIZE 32
> +
> +#define MESON_SAR_ADC_CHAN(_chan, _type) { \
> + .type = _type, \
> + .indexed = true, \
most drivers have 1 here (unsigned indexed:1;)
> + .channel = _chan, \
> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
> + BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
> + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
> + .datasheet_name = "SAR_ADC_CH"#_chan, \
> +}
> +
> +/*
> + * TODO: the hardware supports IIO_TEMP for channel 6 as well which is
> + * currently not supported by this driver.
> + */
> +static const struct iio_chan_spec meson_saradc_iio_channels[] = {
consistent prefixing would be nice
type is always IIO_VOLTAGE
> + MESON_SAR_ADC_CHAN(0, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(1, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(2, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(3, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(4, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(5, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(6, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(7, IIO_VOLTAGE),
> + IIO_CHAN_SOFT_TIMESTAMP(8),
> +};
> +
> +enum meson_saradc_avg_mode {
> + NO_AVERAGING = 0x0,
> + MEAN_AVERAGING = 0x1,
> + MEDIAN_AVERAGING = 0x2,
> +};
> +
> +enum meson_saradc_num_samples {
> + ONE_SAMPLE = 0x0,
> + TWO_SAMPLES = 0x1,
> + FOUR_SAMPLES = 0x2,
> + EIGHT_SAMPLES = 0x3,
> +};
> +
> +enum meson_saradc_chan7_mux_sel {
> + CHAN7_MUX_VSS = 0x0,
> + CHAN7_MUX_VDD_DIV4 = 0x1,
> + CHAN7_MUX_VDD_DIV2 = 0x2,
> + CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
> + CHAN7_MUX_VDD = 0x4,
> + CHAN7_MUX_CH7_INPUT = 0x7,
> +};
> +
> +struct meson_saradc_data {
> + unsigned int resolution;
> + const char *name;
> +};
> +
> +struct meson_saradc_priv {
> + struct regmap *regmap;
> + struct regulator *vref;
> + const struct meson_saradc_data *data;
> + struct clk *clkin;
> + struct clk *core_clk;
> + struct clk *sana_clk;
> + struct clk *adc_sel_clk;
> + struct clk *adc_clk;
> + struct clk_gate clk_gate;
> + struct clk *adc_div_clk;
> + struct clk_divider clk_div;
> +};
> +
> +static const struct regmap_config meson_saradc_regmap_config = {
> + .reg_bits = 8,
> + .val_bits = 32,
> + .reg_stride = 4,
> + .max_register = SAR_ADC_REG13,
> +};
> +
> +static unsigned int meson_saradc_get_fifo_count(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + u32 regval;
> +
> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
> +
> + return FIELD_GET(SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
> +}
> +
> +static int meson_saradc_wait_busy_clear(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int regval, timeout = 10000;
> +
> + /*
> + * NOTE: we need a small delay before reading the status, otherwise
> + * the sample engine may not have started internally (which would
> + * seem to us that sampling is already finished).
> + */
> + do {
> + udelay(1);
> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
> + } while (FIELD_GET(SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
> +
> + if (timeout < 0)
> + return -ETIMEDOUT;
> +
> + return 0;
> +}
> +
> +static int meson_saradc_read_raw_sample(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + int *val)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0;
> +
> + ret = meson_saradc_wait_busy_clear(indio_dev);
> + if (ret)
> + return ret;
> +
> + while (meson_saradc_get_fifo_count(indio_dev) > 0 &&
> + count < SAR_ADC_MAX_FIFO_SIZE) {
> + regmap_read(priv->regmap, SAR_ADC_FIFO_RD, ®val);
> +
> + fifo_chan = FIELD_GET(SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
> + if (fifo_chan == chan->channel) {
> + fifo_val = FIELD_GET(SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK,
> + regval);
> + fifo_val &= (BIT(priv->data->resolution) - 1);
> +
> + sum += fifo_val;
> + count++;
> + }
> + }
> +
> + if (!count)
> + return -ENOENT;
> +
> + *val = sum / count;
> +
> + return 0;
> +}
> +
> +static void meson_saradc_set_averaging(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + enum meson_saradc_avg_mode mode,
> + enum meson_saradc_num_samples samples)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + u32 val;
> +
> + val = samples << SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(chan->channel);
> + regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
> + SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(chan->channel),
> + val);
> +
> + val = mode << SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(chan->channel);
> + regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
> + SAR_ADC_AVG_CNTL_AVG_MODE_MASK(chan->channel), val);
> +}
> +
> +static void meson_saradc_enable_channel(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + u32 regval;
> +
> + /* the SAR ADC engine allows sampling multiple channels at the same
multi-line comment style
> + * time. to keep it simple we're only working with one *internal*
> + * channel, which starts counting at index 0 (which means: count = 1).
> + */
> + regval = FIELD_PREP(SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
> + regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
> + SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
> +
> + /* map channel index 0 to the channel which we want to read */
> + regval = FIELD_PREP(SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), chan->channel);
> + regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
> + SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), regval);
> +
> + regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
> + chan->channel);
> + regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
> + SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
> + regval);
> +
> + regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
> + chan->channel);
> + regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
> + SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
> + regval);
> +
> + if (chan->channel == 6)
> + regmap_update_bits(priv->regmap, SAR_ADC_DELTA_10,
> + SAR_ADC_DELTA_10_TEMP_SEL, 0);
> +}
> +
> +static void meson_saradc_set_channel7_mux(struct iio_dev *indio_dev,
> + enum meson_saradc_chan7_mux_sel sel)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + u32 regval;
> +
> + regval = FIELD_PREP(SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
> + SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
> +
> + usleep_range(10, 20);
> +}
> +
> +static void meson_saradc_start_sample_engine(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
> + SAR_ADC_REG0_SAMPLING_START,
> + SAR_ADC_REG0_SAMPLING_START);
> +}
> +
> +static void meson_saradc_stop_sample_engine(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
> + SAR_ADC_REG0_SAMPLING_STOP,
> + SAR_ADC_REG0_SAMPLING_STOP);
> +
> + /* wait until all modules are stopped */
> + meson_saradc_wait_busy_clear(indio_dev);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
> +}
> +
> +static void meson_saradc_lock(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int val;
> +
> + mutex_lock(&indio_dev->mlock);
> +
> + /* prevent BL30 from using the SAR ADC while we are using it */
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_KERNEL_BUSY,
> + SAR_ADC_DELAY_KERNEL_BUSY);
> +
> + /* wait until BL30 releases it's lock (so we can use the SAR ADC) */
> + do {
> + udelay(1);
> + regmap_read(priv->regmap, SAR_ADC_DELAY, &val);
> + } while (val & SAR_ADC_DELAY_BL30_BUSY);
no timeout here?
> +}
> +
> +static void meson_saradc_unlock(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> +
> + /* allow BL30 to use the SAR ADC again */
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_KERNEL_BUSY, 0);
> +
> + mutex_unlock(&indio_dev->mlock);
> +}
> +
> +static void meson_saradc_clear_fifo(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int count;
> +
> + for (count = 0; count < SAR_ADC_MAX_FIFO_SIZE; count++) {
> + if (!meson_saradc_get_fifo_count(indio_dev))
> + break;
> +
> + regmap_read(priv->regmap, SAR_ADC_FIFO_RD, 0);
> + }
> +}
> +
> +static int meson_saradc_get_sample(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + enum meson_saradc_avg_mode avg_mode,
> + enum meson_saradc_num_samples avg_samples,
> + int *val)
> +{
> + int ret;
> +
> + meson_saradc_lock(indio_dev);
> +
> + /* clear the FIFO to make sure we're not reading old values */
> + meson_saradc_clear_fifo(indio_dev);
> +
> + meson_saradc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
> +
> + meson_saradc_enable_channel(indio_dev, chan);
> +
> + meson_saradc_start_sample_engine(indio_dev);
> + ret = meson_saradc_read_raw_sample(indio_dev, chan, val);
> + meson_saradc_stop_sample_engine(indio_dev);
> +
> + meson_saradc_unlock(indio_dev);
> +
> + if (ret) {
> + dev_warn(indio_dev->dev.parent,
> + "failed to read sample for channel %d: %d\n",
> + chan->channel, ret);
> + return ret;
> + }
> +
> + return IIO_VAL_INT;
> +}
> +
> +static int meson_saradc_iio_info_read_raw(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + int *val, int *val2, long mask)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int ret;
> +
> + switch (mask) {
> + case IIO_CHAN_INFO_RAW:
> + return meson_saradc_get_sample(indio_dev, chan, NO_AVERAGING,
> + ONE_SAMPLE, val);
> + break;
> +
> + case IIO_CHAN_INFO_AVERAGE_RAW:
> + return meson_saradc_get_sample(indio_dev, chan, MEAN_AVERAGING,
> + EIGHT_SAMPLES, val);
> + break;
> +
> + case IIO_CHAN_INFO_SCALE:
> + ret = regulator_get_voltage(priv->vref);
> + if (ret < 0) {
> + dev_err(indio_dev->dev.parent,
> + "failed to get vref voltage: %d\n", ret);
> + return ret;
> + }
> +
> + *val = ret / 1000;
> + *val2 = priv->data->resolution;
> + return IIO_VAL_FRACTIONAL_LOG2;
> +
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static int meson_saradc_clk_init(struct iio_dev *indio_dev, void __iomem *base)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + struct clk_init_data init;
> + const char *clk_parents[1];
> +
> + init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_div",
> + of_node_full_name(indio_dev->dev.of_node));
> + init.flags = 0;
> + init.ops = &clk_divider_ops;
> + clk_parents[0] = __clk_get_name(priv->clkin);
> + init.parent_names = clk_parents;
> + init.num_parents = 1;
> +
> + priv->clk_div.reg = base + SAR_ADC_REG3;
> + priv->clk_div.shift = SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
> + priv->clk_div.width = SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
> + priv->clk_div.hw.init = &init;
> + priv->clk_div.flags = 0;
> +
> + priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
> + &priv->clk_div.hw);
> + if (WARN_ON(IS_ERR(priv->adc_div_clk)))
> + return PTR_ERR(priv->adc_div_clk);
> +
> + init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_en",
> + of_node_full_name(indio_dev->dev.of_node));
> + init.flags = CLK_SET_RATE_PARENT;
> + init.ops = &clk_gate_ops;
> + clk_parents[0] = __clk_get_name(priv->adc_div_clk);
> + init.parent_names = clk_parents;
> + init.num_parents = 1;
> +
> + priv->clk_gate.reg = base + SAR_ADC_REG3;
> + priv->clk_gate.bit_idx = fls(SAR_ADC_REG3_CLK_EN);
> + priv->clk_gate.hw.init = &init;
> +
> + priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
> + if (WARN_ON(IS_ERR(priv->adc_clk)))
> + return PTR_ERR(priv->adc_clk);
> +
> + return 0;
> +}
> +
> +static int meson_saradc_init(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int regval, ret;
> +
> + /*
> + * make sure we start at CH7 input since the other muxes are only used
> + * for internal calibration.
> + */
> + meson_saradc_set_channel7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
> +
> + /*
> + * leave sampling delay and the input clocks as configured by BL30 to
> + * make sure BL30 gets the values it expects when reading the
> + * temperature sensor.
> + */
> + regmap_read(priv->regmap, SAR_ADC_REG3, ®val);
> + if (regval & SAR_ADC_REG3_BL30_INITIALIZED)
> + return 0;
> +
> + meson_saradc_stop_sample_engine(indio_dev);
> +
> + /* update the channel 6 MUX to select the temperature sensor */
> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
> + SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
> + SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
> +
> + /* disable all channels by default */
> + regmap_write(priv->regmap, SAR_ADC_CHAN_LIST, 0x0);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
> + SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
> + SAR_ADC_REG3_CNTL_USE_SC_DLY,
> + SAR_ADC_REG3_CNTL_USE_SC_DLY);
> +
> + /* delay between two samples = (10+1) * 1uS */
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
> + FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK, 10));
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
> + FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 0));
> +
> + /* delay between two samples = (10+1) * 1uS */
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
> + FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 10));
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
> + FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 1));
> +
> + ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
> + if (ret) {
> + dev_err(indio_dev->dev.parent,
> + "failed to set adc parent to clkin\n");
> + return ret;
> + }
> +
> + ret = clk_set_rate(priv->adc_clk, 1200000);
> + if (ret) {
> + dev_err(indio_dev->dev.parent,
> + "failed to set adc clock rate\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int meson_saradc_hw_enable(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int ret;
> +
> + meson_saradc_lock(indio_dev);
> +
> + ret = regulator_enable(priv->vref);
> + if (ret < 0) {
> + dev_err(indio_dev->dev.parent,
> + "failed to enable vref regulator\n");
> + goto err_vref;
> + }
> +
> + ret = clk_prepare_enable(priv->core_clk);
> + if (ret) {
> + dev_err(indio_dev->dev.parent, "failed to enable core clk\n");
> + goto err_core_clk;
> + }
> +
> + ret = clk_prepare_enable(priv->sana_clk);
> + if (ret) {
> + dev_err(indio_dev->dev.parent, "failed to enable sana clk\n");
> + goto err_sana_clk;
> + }
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG11,
> + SAR_ADC_REG11_BANDGAP_EN, SAR_ADC_REG11_BANDGAP_EN);
> + regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN,
> + SAR_ADC_REG3_ADC_EN);
> +
> + udelay(5);
> +
> + ret = clk_prepare_enable(priv->adc_clk);
> + if (ret) {
> + dev_err(indio_dev->dev.parent, "failed to enable adc clk\n");
> + goto err_adc_clk;
> + }
> +
> + meson_saradc_unlock(indio_dev);
> +
> + return 0;
> +
> +err_adc_clk:
> + regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN, 0);
> + regmap_update_bits(priv->regmap, SAR_ADC_REG11,
> + SAR_ADC_REG11_BANDGAP_EN, 0);
> + clk_disable_unprepare(priv->sana_clk);
> +err_sana_clk:
> + clk_disable_unprepare(priv->core_clk);
> +err_core_clk:
> + regulator_disable(priv->vref);
> +err_vref:
> + meson_saradc_unlock(indio_dev);
> + return ret;
> +}
> +
> +static void meson_saradc_hw_disable(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> +
> + meson_saradc_lock(indio_dev);
> +
> + clk_disable_unprepare(priv->adc_clk);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN, 0);
> + regmap_update_bits(priv->regmap, SAR_ADC_REG11,
> + SAR_ADC_REG11_BANDGAP_EN, 0);
> +
> + clk_disable_unprepare(priv->sana_clk);
> + clk_disable_unprepare(priv->core_clk);
> +
> + regulator_disable(priv->vref);
> +
> + meson_saradc_unlock(indio_dev);
> +}
> +
> +static const struct iio_info meson_saradc_iio_info = {
> + .read_raw = meson_saradc_iio_info_read_raw,
> + .driver_module = THIS_MODULE,
> +};
> +
> +struct meson_saradc_data meson_saradc_gxbb_data = {
> + .resolution = 10,
> + .name = "meson-gxbb-saradc",
> +};
> +
> +struct meson_saradc_data meson_saradc_gxl_data = {
> + .resolution = 12,
> + .name = "meson-gxl-saradc",
> +};
> +
> +static const struct of_device_id meson_saradc_of_match[] = {
> + {
> + .compatible = "amlogic,meson-gxbb-saradc",
> + .data = &meson_saradc_gxbb_data,
> + }, {
> + .compatible = "amlogic,meson-gxl-saradc",
> + .data = &meson_saradc_gxl_data,
> + },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, meson_saradc_of_match);
> +
> +static int meson_saradc_probe(struct platform_device *pdev)
> +{
> + struct meson_saradc_priv *priv;
> + struct iio_dev *indio_dev;
> + struct resource *res;
> + void __iomem *base;
> + const struct of_device_id *match;
> + int ret;
> +
> + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
> + if (!indio_dev) {
> + dev_err(&pdev->dev, "failed allocating iio device\n");
> + return -ENOMEM;
> + }
> +
> + priv = iio_priv(indio_dev);
> +
> + match = of_match_device(meson_saradc_of_match, &pdev->dev);
> + priv->data = match->data;
> +
> + indio_dev->name = priv->data->name;
> + indio_dev->dev.parent = &pdev->dev;
> + indio_dev->dev.of_node = pdev->dev.of_node;
> + indio_dev->modes = INDIO_DIRECT_MODE;
> + indio_dev->info = &meson_saradc_iio_info;
> +
> + indio_dev->channels = meson_saradc_iio_channels;
> + indio_dev->num_channels = ARRAY_SIZE(meson_saradc_iio_channels);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
> + &meson_saradc_regmap_config);
> + if (IS_ERR(priv->regmap))
> + return PTR_ERR(priv->regmap);
> +
> + priv->clkin = devm_clk_get(&pdev->dev, "clkin");
> + if (IS_ERR(priv->clkin)) {
> + dev_err(&pdev->dev, "failed to get clkin\n");
> + return PTR_ERR(priv->clkin);
> + }
> +
> + priv->core_clk = devm_clk_get(&pdev->dev, "core");
> + if (IS_ERR(priv->core_clk)) {
> + dev_err(&pdev->dev, "failed to get core clk\n");
> + return PTR_ERR(priv->core_clk);
> + }
> +
> + priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
> + if (IS_ERR(priv->sana_clk)) {
> + if (PTR_ERR(priv->sana_clk) == -ENOENT) {
> + priv->sana_clk = NULL;
> + } else {
> + dev_err(&pdev->dev, "failed to get sana clk\n");
> + return PTR_ERR(priv->sana_clk);
> + }
> + }
> +
> + priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
> + if (IS_ERR(priv->adc_clk)) {
> + if (PTR_ERR(priv->adc_clk) == -ENOENT) {
> + priv->adc_clk = NULL;
> + } else {
> + dev_err(&pdev->dev, "failed to get adc clk\n");
> + return PTR_ERR(priv->adc_clk);
> + }
> + }
> +
> + priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
> + if (IS_ERR(priv->adc_sel_clk)) {
> + if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
> + priv->adc_sel_clk = NULL;
> + } else {
> + dev_err(&pdev->dev, "failed to get adc_sel clk\n");
> + return PTR_ERR(priv->adc_sel_clk);
> + }
> + }
> +
> + /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
> + if (!priv->adc_clk) {
> + ret = meson_saradc_clk_init(indio_dev, base);
> + if (ret)
> + return ret;
> + }
> +
> + priv->vref = devm_regulator_get(&pdev->dev, "vref");
> + if (IS_ERR(priv->vref)) {
> + dev_err(&pdev->dev, "failed to get vref regulator\n");
> + return PTR_ERR(priv->vref);
> + }
> +
> + ret = meson_saradc_init(indio_dev);
> + if (ret)
> + goto err;
> +
> + ret = meson_saradc_hw_enable(indio_dev);
> + if (ret)
> + goto err;
> +
> + platform_set_drvdata(pdev, indio_dev);
> +
> + ret = iio_device_register(indio_dev);
> + if (ret)
> + goto err_hw;
> +
> + return 0;
> +
> +err_hw:
> + meson_saradc_hw_disable(indio_dev);
> +err:
> + return ret;
> +}
> +
> +static int meson_saradc_remove(struct platform_device *pdev)
> +{
> + struct iio_dev *indio_dev = platform_get_drvdata(pdev);
> +
> + meson_saradc_hw_disable(indio_dev);
> + iio_device_unregister(indio_dev);
should be the other way around
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int meson_saradc_suspend(struct device *dev)
> +{
> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
> +
> + meson_saradc_hw_disable(indio_dev);
> +
> + return 0;
> +}
> +
> +static int meson_saradc_resume(struct device *dev)
> +{
> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
> +
> + return meson_saradc_hw_enable(indio_dev);
> +}
> +#endif /* CONFIG_PM_SLEEP */
> +
> +static SIMPLE_DEV_PM_OPS(meson_saradc_pm_ops,
> + meson_saradc_suspend, meson_saradc_resume);
> +
> +static struct platform_driver meson_saradc_driver = {
> + .probe = meson_saradc_probe,
> + .remove = meson_saradc_remove,
> + .driver = {
> + .name = "meson-saradc",
> + .of_match_table = meson_saradc_of_match,
> + .pm = &meson_saradc_pm_ops,
> + },
> +};
> +
> +module_platform_driver(meson_saradc_driver);
> +
> +MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
> +MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
> +MODULE_LICENSE("GPL v2");
>
--
Peter Meerwald-Stadler
+43-664-2444418 (mobile)
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v2 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
@ 2017-01-16 17:41 ` Peter Meerwald-Stadler
0 siblings, 0 replies; 110+ messages in thread
From: Peter Meerwald-Stadler @ 2017-01-16 17:41 UTC (permalink / raw)
To: linus-amlogic
> This adds support for the SAR (Successive Approximation Register) ADC
> on the Amlogic Meson SoCs.
minor comments below
> The code is based on the public S805 (Meson8b) and S905 (GXBB)
> datasheets (see [0] and [1]), as well as by reading (various versions
> of) the vendor driver and by inspecting the registers on the vendor
> kernels of my testing-hardware.
>
> Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
> 10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
> The code was written to support older SoCs (Meson8 and Meson8b) as well,
> but due to lack of actual testing-hardware no of_device_id was added for
> these.
>
> Two "features" from the vendor driver are currently missing:
> - the vendor driver uses channel #7 for calibration (this improves the
> accuracy of the results - in my tests the results were less than 3%
> off without calibration compared to the vendor driver). Adding support
> for this should be easy, but is not required for most applications.
> - channel #6 is connected to the SoCs internal temperature sensor.
> Adding support for this is probably not so easy since (based on the
> u-boot sources) most SoC versions are using different registers and
> algorithms for the conversion from "ADC value" to temperature.
>
> Supported by the hardware but currently not supported by the driver:
> - reading multiple channels at the same time (the hardware has a FIFO
> buffer which stores multiple results)
> - continuous sampling (this would require a way to enable this
> individually because otherwise the ADC would be drawing power
> constantly)
> - interrupt support (similar to the vendor driver this new driver is
> polling the results. It is unclear if the IRQ-mode is supported on
> older (Meson6 or Meson8) hardware as well or if there are any errata)
>
> [0]
> http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
> [1] http://dn.odroid.com/S905/DataSheet/S905_Public_Datasheet_V1.1.4.pdf
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
> drivers/iio/adc/Kconfig | 12 +
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/meson_saradc.c | 893 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 906 insertions(+)
> create mode 100644 drivers/iio/adc/meson_saradc.c
>
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index 9c8b558ba19e..86059b9b91bf 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -371,6 +371,18 @@ config MEN_Z188_ADC
> This driver can also be built as a module. If so, the module will be
> called men_z188_adc.
>
> +config MESON_SARADC
> + tristate "Amlogic Meson SAR ADC driver"
> + default ARCH_MESON
> + depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
> + select REGMAP_MMIO
> + help
> + Say yes here to build support for the SAR ADC found in Amlogic Meson
> + SoCs.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called meson_saradc.
> +
> config MXS_LRADC
> tristate "Freescale i.MX23/i.MX28 LRADC"
> depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
> index d36c4be8d1fc..de05b9e75f8f 100644
> --- a/drivers/iio/adc/Makefile
> +++ b/drivers/iio/adc/Makefile
> @@ -36,6 +36,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
> obj-$(CONFIG_MCP3422) += mcp3422.o
> obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
> obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
> +obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
> obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
> obj-$(CONFIG_NAU7802) += nau7802.o
> obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
> diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
> new file mode 100644
> index 000000000000..4c189e5fd7cc
> --- /dev/null
> +++ b/drivers/iio/adc/meson_saradc.c
> @@ -0,0 +1,893 @@
> +/*
> + * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
> + *
> + * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/iio/iio.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/regulator/consumer.h>
> +
> +#define SAR_ADC_REG0 0x00
prefix should be MESON_SARADC_ (making it even longer, doe MESON_ADC_
perhaps)
> + #define SAR_ADC_REG0_PANEL_DETECT BIT(31)
> + #define SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
> + #define SAR_ADC_REG0_DELTA_BUSY BIT(30)
> + #define SAR_ADC_REG0_AVG_BUSY BIT(29)
> + #define SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
> + #define SAR_ADC_REG0_FIFO_FULL BIT(27)
> + #define SAR_ADC_REG0_FIFO_EMPTY BIT(26)
> + #define SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
> + #define SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
> + #define SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
> + #define SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
> + #define SAR_ADC_REG0_SAMPLING_STOP BIT(14)
> + #define SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
> + #define SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
> + #define SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
> + #define SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
> + #define SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
> + #define SAR_ADC_REG0_SAMPLING_START BIT(2)
> + #define SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
> + #define SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
> +
> +#define SAR_ADC_CHAN_LIST 0x04
> + #define SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
> + #define SAR_ADC_CHAN_CHAN_ENTRY_MASK(_chan) \
> + (GENMASK(2, 0) << (_chan * 3))
maybe parenthesis around _chan for extra MACRO safety
> +
> +#define SAR_ADC_AVG_CNTL 0x08
> + #define SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
> + (16 + (_chan * 2))
> + #define SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
> + (GENMASK(17, 16) << (_chan * 2))
> + #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
> + (0 + (_chan * 2))
> + #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
> + (GENMASK(1, 0) << (_chan * 2))
> +
> +#define SAR_ADC_REG3 0x0c
> + #define SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
> + #define SAR_ADC_REG3_CLK_EN BIT(30)
> + #define SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
> + #define SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
> + #define SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
> + #define SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
> + #define SAR_ADC_REG3_DETECT_EN BIT(22)
> + #define SAR_ADC_REG3_ADC_EN BIT(21)
> + #define SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
> + #define SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
> + #define SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
> + #define SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
> + #define SAR_ADC_REG3_ADC_CLK_DIV_MASK GENMASK(15, 10)
15 would be _SHIFT + _WIDTH?
> + #define SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
> + #define SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
> +
> +#define SAR_ADC_DELAY 0x10
> + #define SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
> + #define SAR_ADC_DELAY_BL30_BUSY BIT(15)
> + #define SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
> + #define SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
> + #define SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
> + #define SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
> +
> +#define SAR_ADC_LAST_RD 0x14
> + #define SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
> + #define SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
> +
> +#define SAR_ADC_FIFO_RD 0x18
> + #define SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
> + #define SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
> +
> +#define SAR_ADC_AUX_SW 0x1c
> + #define SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
> + (GENMASK(10, 8) << ((_chan - 2) * 2))
> + #define SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
> + #define SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
> + #define SAR_ADC_AUX_SW_MODE_SEL BIT(4)
> + #define SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
> + #define SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
> + #define SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
> + #define SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
> +
> +#define SAR_ADC_CHAN_10_SW 0x20
> + #define SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
> + #define SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
> + #define SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
> +
> +#define SAR_ADC_DETECT_IDLE_SW 0x24
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK GENMASK(25, 23)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_P_MUX BIT(22)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_VREF_N_MUX BIT(21)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YP_DRIVE_SW BIT(19)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XP_DRIVE_SW BIT(18)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_YM_DRIVE_SW BIT(17)
> + #define SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_XM_DRIVE_SW BIT(16)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK GENMASK(9, 7)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_P_MUX BIT(6)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_VREF_N_MUX BIT(5)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YP_DRIVE_SW BIT(3)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XP_DRIVE_SW BIT(2)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_YM_DRIVE_SW BIT(1)
> + #define SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_XM_DRIVE_SW BIT(0)
> +
> +#define SAR_ADC_DELTA_10 0x28
> + #define SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
> + #define SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
> + #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_SHIFT 16
> + #define SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
> + #define SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
> + #define SAR_ADC_DELTA_10_TS_C_SHIFT 11
> + #define SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
> + #define SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
> + #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_SHIFT 0
> + #define SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
> +
> +/*
> + * NOTE: registers from here are undocumented (the vendor Linux kernel driver
> + * and u-boot source served as reference). These only seem to be relevant on
> + * GXBB and newer.
> + */
> +#define SAR_ADC_REG11 0x2c
> + #define SAR_ADC_REG11_BANDGAP_EN BIT(13)
> +
> +#define SAR_ADC_REG13 0x34
> + #define SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
> +
> +#define SAR_ADC_MAX_FIFO_SIZE 32
> +
> +#define MESON_SAR_ADC_CHAN(_chan, _type) { \
> + .type = _type, \
> + .indexed = true, \
most drivers have 1 here (unsigned indexed:1;)
> + .channel = _chan, \
> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
> + BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
> + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
> + .datasheet_name = "SAR_ADC_CH"#_chan, \
> +}
> +
> +/*
> + * TODO: the hardware supports IIO_TEMP for channel 6 as well which is
> + * currently not supported by this driver.
> + */
> +static const struct iio_chan_spec meson_saradc_iio_channels[] = {
consistent prefixing would be nice
type is always IIO_VOLTAGE
> + MESON_SAR_ADC_CHAN(0, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(1, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(2, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(3, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(4, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(5, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(6, IIO_VOLTAGE),
> + MESON_SAR_ADC_CHAN(7, IIO_VOLTAGE),
> + IIO_CHAN_SOFT_TIMESTAMP(8),
> +};
> +
> +enum meson_saradc_avg_mode {
> + NO_AVERAGING = 0x0,
> + MEAN_AVERAGING = 0x1,
> + MEDIAN_AVERAGING = 0x2,
> +};
> +
> +enum meson_saradc_num_samples {
> + ONE_SAMPLE = 0x0,
> + TWO_SAMPLES = 0x1,
> + FOUR_SAMPLES = 0x2,
> + EIGHT_SAMPLES = 0x3,
> +};
> +
> +enum meson_saradc_chan7_mux_sel {
> + CHAN7_MUX_VSS = 0x0,
> + CHAN7_MUX_VDD_DIV4 = 0x1,
> + CHAN7_MUX_VDD_DIV2 = 0x2,
> + CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
> + CHAN7_MUX_VDD = 0x4,
> + CHAN7_MUX_CH7_INPUT = 0x7,
> +};
> +
> +struct meson_saradc_data {
> + unsigned int resolution;
> + const char *name;
> +};
> +
> +struct meson_saradc_priv {
> + struct regmap *regmap;
> + struct regulator *vref;
> + const struct meson_saradc_data *data;
> + struct clk *clkin;
> + struct clk *core_clk;
> + struct clk *sana_clk;
> + struct clk *adc_sel_clk;
> + struct clk *adc_clk;
> + struct clk_gate clk_gate;
> + struct clk *adc_div_clk;
> + struct clk_divider clk_div;
> +};
> +
> +static const struct regmap_config meson_saradc_regmap_config = {
> + .reg_bits = 8,
> + .val_bits = 32,
> + .reg_stride = 4,
> + .max_register = SAR_ADC_REG13,
> +};
> +
> +static unsigned int meson_saradc_get_fifo_count(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + u32 regval;
> +
> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
> +
> + return FIELD_GET(SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
> +}
> +
> +static int meson_saradc_wait_busy_clear(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int regval, timeout = 10000;
> +
> + /*
> + * NOTE: we need a small delay before reading the status, otherwise
> + * the sample engine may not have started internally (which would
> + * seem to us that sampling is already finished).
> + */
> + do {
> + udelay(1);
> + regmap_read(priv->regmap, SAR_ADC_REG0, ®val);
> + } while (FIELD_GET(SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
> +
> + if (timeout < 0)
> + return -ETIMEDOUT;
> +
> + return 0;
> +}
> +
> +static int meson_saradc_read_raw_sample(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + int *val)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0;
> +
> + ret = meson_saradc_wait_busy_clear(indio_dev);
> + if (ret)
> + return ret;
> +
> + while (meson_saradc_get_fifo_count(indio_dev) > 0 &&
> + count < SAR_ADC_MAX_FIFO_SIZE) {
> + regmap_read(priv->regmap, SAR_ADC_FIFO_RD, ®val);
> +
> + fifo_chan = FIELD_GET(SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
> + if (fifo_chan == chan->channel) {
> + fifo_val = FIELD_GET(SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK,
> + regval);
> + fifo_val &= (BIT(priv->data->resolution) - 1);
> +
> + sum += fifo_val;
> + count++;
> + }
> + }
> +
> + if (!count)
> + return -ENOENT;
> +
> + *val = sum / count;
> +
> + return 0;
> +}
> +
> +static void meson_saradc_set_averaging(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + enum meson_saradc_avg_mode mode,
> + enum meson_saradc_num_samples samples)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + u32 val;
> +
> + val = samples << SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(chan->channel);
> + regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
> + SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(chan->channel),
> + val);
> +
> + val = mode << SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(chan->channel);
> + regmap_update_bits(priv->regmap, SAR_ADC_AVG_CNTL,
> + SAR_ADC_AVG_CNTL_AVG_MODE_MASK(chan->channel), val);
> +}
> +
> +static void meson_saradc_enable_channel(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + u32 regval;
> +
> + /* the SAR ADC engine allows sampling multiple channels at the same
multi-line comment style
> + * time. to keep it simple we're only working with one *internal*
> + * channel, which starts counting at index 0 (which means: count = 1).
> + */
> + regval = FIELD_PREP(SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
> + regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
> + SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
> +
> + /* map channel index 0 to the channel which we want to read */
> + regval = FIELD_PREP(SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), chan->channel);
> + regmap_update_bits(priv->regmap, SAR_ADC_CHAN_LIST,
> + SAR_ADC_CHAN_CHAN_ENTRY_MASK(0), regval);
> +
> + regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
> + chan->channel);
> + regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
> + SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_MUX_MASK,
> + regval);
> +
> + regval = FIELD_PREP(SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
> + chan->channel);
> + regmap_update_bits(priv->regmap, SAR_ADC_DETECT_IDLE_SW,
> + SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_MUX_SEL_MASK,
> + regval);
> +
> + if (chan->channel == 6)
> + regmap_update_bits(priv->regmap, SAR_ADC_DELTA_10,
> + SAR_ADC_DELTA_10_TEMP_SEL, 0);
> +}
> +
> +static void meson_saradc_set_channel7_mux(struct iio_dev *indio_dev,
> + enum meson_saradc_chan7_mux_sel sel)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + u32 regval;
> +
> + regval = FIELD_PREP(SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
> + SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
> +
> + usleep_range(10, 20);
> +}
> +
> +static void meson_saradc_start_sample_engine(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
> + SAR_ADC_REG0_SAMPLING_START,
> + SAR_ADC_REG0_SAMPLING_START);
> +}
> +
> +static void meson_saradc_stop_sample_engine(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
> + SAR_ADC_REG0_SAMPLING_STOP,
> + SAR_ADC_REG0_SAMPLING_STOP);
> +
> + /* wait until all modules are stopped */
> + meson_saradc_wait_busy_clear(indio_dev);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
> + SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
> +}
> +
> +static void meson_saradc_lock(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int val;
> +
> + mutex_lock(&indio_dev->mlock);
> +
> + /* prevent BL30 from using the SAR ADC while we are using it */
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_KERNEL_BUSY,
> + SAR_ADC_DELAY_KERNEL_BUSY);
> +
> + /* wait until BL30 releases it's lock (so we can use the SAR ADC) */
> + do {
> + udelay(1);
> + regmap_read(priv->regmap, SAR_ADC_DELAY, &val);
> + } while (val & SAR_ADC_DELAY_BL30_BUSY);
no timeout here?
> +}
> +
> +static void meson_saradc_unlock(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> +
> + /* allow BL30 to use the SAR ADC again */
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_KERNEL_BUSY, 0);
> +
> + mutex_unlock(&indio_dev->mlock);
> +}
> +
> +static void meson_saradc_clear_fifo(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int count;
> +
> + for (count = 0; count < SAR_ADC_MAX_FIFO_SIZE; count++) {
> + if (!meson_saradc_get_fifo_count(indio_dev))
> + break;
> +
> + regmap_read(priv->regmap, SAR_ADC_FIFO_RD, 0);
> + }
> +}
> +
> +static int meson_saradc_get_sample(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + enum meson_saradc_avg_mode avg_mode,
> + enum meson_saradc_num_samples avg_samples,
> + int *val)
> +{
> + int ret;
> +
> + meson_saradc_lock(indio_dev);
> +
> + /* clear the FIFO to make sure we're not reading old values */
> + meson_saradc_clear_fifo(indio_dev);
> +
> + meson_saradc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
> +
> + meson_saradc_enable_channel(indio_dev, chan);
> +
> + meson_saradc_start_sample_engine(indio_dev);
> + ret = meson_saradc_read_raw_sample(indio_dev, chan, val);
> + meson_saradc_stop_sample_engine(indio_dev);
> +
> + meson_saradc_unlock(indio_dev);
> +
> + if (ret) {
> + dev_warn(indio_dev->dev.parent,
> + "failed to read sample for channel %d: %d\n",
> + chan->channel, ret);
> + return ret;
> + }
> +
> + return IIO_VAL_INT;
> +}
> +
> +static int meson_saradc_iio_info_read_raw(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + int *val, int *val2, long mask)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int ret;
> +
> + switch (mask) {
> + case IIO_CHAN_INFO_RAW:
> + return meson_saradc_get_sample(indio_dev, chan, NO_AVERAGING,
> + ONE_SAMPLE, val);
> + break;
> +
> + case IIO_CHAN_INFO_AVERAGE_RAW:
> + return meson_saradc_get_sample(indio_dev, chan, MEAN_AVERAGING,
> + EIGHT_SAMPLES, val);
> + break;
> +
> + case IIO_CHAN_INFO_SCALE:
> + ret = regulator_get_voltage(priv->vref);
> + if (ret < 0) {
> + dev_err(indio_dev->dev.parent,
> + "failed to get vref voltage: %d\n", ret);
> + return ret;
> + }
> +
> + *val = ret / 1000;
> + *val2 = priv->data->resolution;
> + return IIO_VAL_FRACTIONAL_LOG2;
> +
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static int meson_saradc_clk_init(struct iio_dev *indio_dev, void __iomem *base)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + struct clk_init_data init;
> + const char *clk_parents[1];
> +
> + init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_div",
> + of_node_full_name(indio_dev->dev.of_node));
> + init.flags = 0;
> + init.ops = &clk_divider_ops;
> + clk_parents[0] = __clk_get_name(priv->clkin);
> + init.parent_names = clk_parents;
> + init.num_parents = 1;
> +
> + priv->clk_div.reg = base + SAR_ADC_REG3;
> + priv->clk_div.shift = SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
> + priv->clk_div.width = SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
> + priv->clk_div.hw.init = &init;
> + priv->clk_div.flags = 0;
> +
> + priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
> + &priv->clk_div.hw);
> + if (WARN_ON(IS_ERR(priv->adc_div_clk)))
> + return PTR_ERR(priv->adc_div_clk);
> +
> + init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_en",
> + of_node_full_name(indio_dev->dev.of_node));
> + init.flags = CLK_SET_RATE_PARENT;
> + init.ops = &clk_gate_ops;
> + clk_parents[0] = __clk_get_name(priv->adc_div_clk);
> + init.parent_names = clk_parents;
> + init.num_parents = 1;
> +
> + priv->clk_gate.reg = base + SAR_ADC_REG3;
> + priv->clk_gate.bit_idx = fls(SAR_ADC_REG3_CLK_EN);
> + priv->clk_gate.hw.init = &init;
> +
> + priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
> + if (WARN_ON(IS_ERR(priv->adc_clk)))
> + return PTR_ERR(priv->adc_clk);
> +
> + return 0;
> +}
> +
> +static int meson_saradc_init(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int regval, ret;
> +
> + /*
> + * make sure we start at CH7 input since the other muxes are only used
> + * for internal calibration.
> + */
> + meson_saradc_set_channel7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
> +
> + /*
> + * leave sampling delay and the input clocks as configured by BL30 to
> + * make sure BL30 gets the values it expects when reading the
> + * temperature sensor.
> + */
> + regmap_read(priv->regmap, SAR_ADC_REG3, ®val);
> + if (regval & SAR_ADC_REG3_BL30_INITIALIZED)
> + return 0;
> +
> + meson_saradc_stop_sample_engine(indio_dev);
> +
> + /* update the channel 6 MUX to select the temperature sensor */
> + regmap_update_bits(priv->regmap, SAR_ADC_REG0,
> + SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
> + SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
> +
> + /* disable all channels by default */
> + regmap_write(priv->regmap, SAR_ADC_CHAN_LIST, 0x0);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
> + SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
> + regmap_update_bits(priv->regmap, SAR_ADC_REG3,
> + SAR_ADC_REG3_CNTL_USE_SC_DLY,
> + SAR_ADC_REG3_CNTL_USE_SC_DLY);
> +
> + /* delay between two samples = (10+1) * 1uS */
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
> + FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK, 10));
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
> + FIELD_PREP(SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 0));
> +
> + /* delay between two samples = (10+1) * 1uS */
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
> + FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 10));
> + regmap_update_bits(priv->regmap, SAR_ADC_DELAY,
> + SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
> + FIELD_PREP(SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 1));
> +
> + ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
> + if (ret) {
> + dev_err(indio_dev->dev.parent,
> + "failed to set adc parent to clkin\n");
> + return ret;
> + }
> +
> + ret = clk_set_rate(priv->adc_clk, 1200000);
> + if (ret) {
> + dev_err(indio_dev->dev.parent,
> + "failed to set adc clock rate\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int meson_saradc_hw_enable(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> + int ret;
> +
> + meson_saradc_lock(indio_dev);
> +
> + ret = regulator_enable(priv->vref);
> + if (ret < 0) {
> + dev_err(indio_dev->dev.parent,
> + "failed to enable vref regulator\n");
> + goto err_vref;
> + }
> +
> + ret = clk_prepare_enable(priv->core_clk);
> + if (ret) {
> + dev_err(indio_dev->dev.parent, "failed to enable core clk\n");
> + goto err_core_clk;
> + }
> +
> + ret = clk_prepare_enable(priv->sana_clk);
> + if (ret) {
> + dev_err(indio_dev->dev.parent, "failed to enable sana clk\n");
> + goto err_sana_clk;
> + }
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG11,
> + SAR_ADC_REG11_BANDGAP_EN, SAR_ADC_REG11_BANDGAP_EN);
> + regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN,
> + SAR_ADC_REG3_ADC_EN);
> +
> + udelay(5);
> +
> + ret = clk_prepare_enable(priv->adc_clk);
> + if (ret) {
> + dev_err(indio_dev->dev.parent, "failed to enable adc clk\n");
> + goto err_adc_clk;
> + }
> +
> + meson_saradc_unlock(indio_dev);
> +
> + return 0;
> +
> +err_adc_clk:
> + regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN, 0);
> + regmap_update_bits(priv->regmap, SAR_ADC_REG11,
> + SAR_ADC_REG11_BANDGAP_EN, 0);
> + clk_disable_unprepare(priv->sana_clk);
> +err_sana_clk:
> + clk_disable_unprepare(priv->core_clk);
> +err_core_clk:
> + regulator_disable(priv->vref);
> +err_vref:
> + meson_saradc_unlock(indio_dev);
> + return ret;
> +}
> +
> +static void meson_saradc_hw_disable(struct iio_dev *indio_dev)
> +{
> + struct meson_saradc_priv *priv = iio_priv(indio_dev);
> +
> + meson_saradc_lock(indio_dev);
> +
> + clk_disable_unprepare(priv->adc_clk);
> +
> + regmap_update_bits(priv->regmap, SAR_ADC_REG3, SAR_ADC_REG3_ADC_EN, 0);
> + regmap_update_bits(priv->regmap, SAR_ADC_REG11,
> + SAR_ADC_REG11_BANDGAP_EN, 0);
> +
> + clk_disable_unprepare(priv->sana_clk);
> + clk_disable_unprepare(priv->core_clk);
> +
> + regulator_disable(priv->vref);
> +
> + meson_saradc_unlock(indio_dev);
> +}
> +
> +static const struct iio_info meson_saradc_iio_info = {
> + .read_raw = meson_saradc_iio_info_read_raw,
> + .driver_module = THIS_MODULE,
> +};
> +
> +struct meson_saradc_data meson_saradc_gxbb_data = {
> + .resolution = 10,
> + .name = "meson-gxbb-saradc",
> +};
> +
> +struct meson_saradc_data meson_saradc_gxl_data = {
> + .resolution = 12,
> + .name = "meson-gxl-saradc",
> +};
> +
> +static const struct of_device_id meson_saradc_of_match[] = {
> + {
> + .compatible = "amlogic,meson-gxbb-saradc",
> + .data = &meson_saradc_gxbb_data,
> + }, {
> + .compatible = "amlogic,meson-gxl-saradc",
> + .data = &meson_saradc_gxl_data,
> + },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, meson_saradc_of_match);
> +
> +static int meson_saradc_probe(struct platform_device *pdev)
> +{
> + struct meson_saradc_priv *priv;
> + struct iio_dev *indio_dev;
> + struct resource *res;
> + void __iomem *base;
> + const struct of_device_id *match;
> + int ret;
> +
> + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
> + if (!indio_dev) {
> + dev_err(&pdev->dev, "failed allocating iio device\n");
> + return -ENOMEM;
> + }
> +
> + priv = iio_priv(indio_dev);
> +
> + match = of_match_device(meson_saradc_of_match, &pdev->dev);
> + priv->data = match->data;
> +
> + indio_dev->name = priv->data->name;
> + indio_dev->dev.parent = &pdev->dev;
> + indio_dev->dev.of_node = pdev->dev.of_node;
> + indio_dev->modes = INDIO_DIRECT_MODE;
> + indio_dev->info = &meson_saradc_iio_info;
> +
> + indio_dev->channels = meson_saradc_iio_channels;
> + indio_dev->num_channels = ARRAY_SIZE(meson_saradc_iio_channels);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
> + &meson_saradc_regmap_config);
> + if (IS_ERR(priv->regmap))
> + return PTR_ERR(priv->regmap);
> +
> + priv->clkin = devm_clk_get(&pdev->dev, "clkin");
> + if (IS_ERR(priv->clkin)) {
> + dev_err(&pdev->dev, "failed to get clkin\n");
> + return PTR_ERR(priv->clkin);
> + }
> +
> + priv->core_clk = devm_clk_get(&pdev->dev, "core");
> + if (IS_ERR(priv->core_clk)) {
> + dev_err(&pdev->dev, "failed to get core clk\n");
> + return PTR_ERR(priv->core_clk);
> + }
> +
> + priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
> + if (IS_ERR(priv->sana_clk)) {
> + if (PTR_ERR(priv->sana_clk) == -ENOENT) {
> + priv->sana_clk = NULL;
> + } else {
> + dev_err(&pdev->dev, "failed to get sana clk\n");
> + return PTR_ERR(priv->sana_clk);
> + }
> + }
> +
> + priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
> + if (IS_ERR(priv->adc_clk)) {
> + if (PTR_ERR(priv->adc_clk) == -ENOENT) {
> + priv->adc_clk = NULL;
> + } else {
> + dev_err(&pdev->dev, "failed to get adc clk\n");
> + return PTR_ERR(priv->adc_clk);
> + }
> + }
> +
> + priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
> + if (IS_ERR(priv->adc_sel_clk)) {
> + if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
> + priv->adc_sel_clk = NULL;
> + } else {
> + dev_err(&pdev->dev, "failed to get adc_sel clk\n");
> + return PTR_ERR(priv->adc_sel_clk);
> + }
> + }
> +
> + /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
> + if (!priv->adc_clk) {
> + ret = meson_saradc_clk_init(indio_dev, base);
> + if (ret)
> + return ret;
> + }
> +
> + priv->vref = devm_regulator_get(&pdev->dev, "vref");
> + if (IS_ERR(priv->vref)) {
> + dev_err(&pdev->dev, "failed to get vref regulator\n");
> + return PTR_ERR(priv->vref);
> + }
> +
> + ret = meson_saradc_init(indio_dev);
> + if (ret)
> + goto err;
> +
> + ret = meson_saradc_hw_enable(indio_dev);
> + if (ret)
> + goto err;
> +
> + platform_set_drvdata(pdev, indio_dev);
> +
> + ret = iio_device_register(indio_dev);
> + if (ret)
> + goto err_hw;
> +
> + return 0;
> +
> +err_hw:
> + meson_saradc_hw_disable(indio_dev);
> +err:
> + return ret;
> +}
> +
> +static int meson_saradc_remove(struct platform_device *pdev)
> +{
> + struct iio_dev *indio_dev = platform_get_drvdata(pdev);
> +
> + meson_saradc_hw_disable(indio_dev);
> + iio_device_unregister(indio_dev);
should be the other way around
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int meson_saradc_suspend(struct device *dev)
> +{
> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
> +
> + meson_saradc_hw_disable(indio_dev);
> +
> + return 0;
> +}
> +
> +static int meson_saradc_resume(struct device *dev)
> +{
> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
> +
> + return meson_saradc_hw_enable(indio_dev);
> +}
> +#endif /* CONFIG_PM_SLEEP */
> +
> +static SIMPLE_DEV_PM_OPS(meson_saradc_pm_ops,
> + meson_saradc_suspend, meson_saradc_resume);
> +
> +static struct platform_driver meson_saradc_driver = {
> + .probe = meson_saradc_probe,
> + .remove = meson_saradc_remove,
> + .driver = {
> + .name = "meson-saradc",
> + .of_match_table = meson_saradc_of_match,
> + .pm = &meson_saradc_pm_ops,
> + },
> +};
> +
> +module_platform_driver(meson_saradc_driver);
> +
> +MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
> +MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
> +MODULE_LICENSE("GPL v2");
>
--
Peter Meerwald-Stadler
+43-664-2444418 (mobile)
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v3 0/4] Amlogic Meson SAR ADC support
2017-01-15 22:42 ` Martin Blumenstingl
(?)
@ 2017-01-19 14:58 ` Martin Blumenstingl
-1 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-19 14:58 UTC (permalink / raw)
To: jic23, knaack.h, lars, pmeerw, robh+dt, mark.rutland, khilman,
linux-iio, devicetree, linux-amlogic, linux-clk
Cc: carlo, catalin.marinas, will.deacon, mturquette, sboyd,
narmstrong, linux-arm-kernel, Martin Blumenstingl
This series add support for the SAR ADC on Amlogic Meson GXBB, GXL and
GXM SoCs.
The hardware on GXBB provides 10-bit ADC results, while GXL and GXM are
providing 12-bit results. Support for older SoCs (Meson8b and Meson8)
can be added with little effort, most of which is testing I guess (I
don't have any pre-GXBB hardware so I can't say).
A new set of clocks had to be added to the GXBB clock controller (used
by the GXBB/GXL/GXM SoCs) which are required to get the ADC working.
The ADC itself can sample multiple channels at the same time and allows
capturing multiple samples (which can be used for filtering/averaging).
The ADC results are stored inside a FIFO register. More details on what
the driver supports (or doesn't) can be found in the description of
patch #3.
The code is based on the public S805 (Meson8b) and S905 (GXBB)
datasheets, as well as by reading (various versions of) the vendor
driver and by inspecting the registers on the vendor kernels of my
testing-hardware.
Typical use-cases for the ADC on the Meson GX SoCs are:
- adc-keys ("ADC attached resistor ladder buttons")
- SoC temperature measurement (not supported by this driver yet as
the system firmware does this already and provides the values via the
SCPI protocol)
- "version-strapping" (different resistor values are used to indicate
the board-revision)
- and of course typical ADC measurements
Thanks to Heiner Kallweit, Jonathan Cameron, Lars-Peter Clausen and
Peter Meerwald-Stadler for reviewing this series and providing valuable
input!
Changes since v2 (all changes are for patch #3, except where noted):
- fixed another typo in the interrupt (patch #4, thanks again Heiner
Kallweit)
- change namespace of all register #defines to MESON_SAR_ADC (I
intentionally decided to keep SAR_ADC in it because that's the way
registers are named in the datasheet, thus making it easy to match the
registers without having to look up the offset all the time)
- added additional parenthesis around MACRO parameters for extra safety
- removed unused definition for SAR_ADC_REG3_ADC_CLK_DIV_MASK (as we
already have SAR_ADC_REG3_ADC_CLK_DIV_SHIFT and
SAR_ADC_REG3_ADC_CLK_DIV_WIDTH which are used instead)
- change value of "indexed" from "true" to "1"
- remove type parameter from MESON_SAR_ADC_CHAN macro as all channels are
currently IIO_VOLTAGE channels
- fixed another multi-line comment style violation
- added timeout to meson_saradc_lock() (unlikely to be triggered, but
better safe then sorry - which would mean that we'd be keeping one core
busy infinitely)
- fixed meson_saradc_remove() call order (first unregister the iio_dev,
then disable the hardware instead of the other way around)
- use "consistent prefixing", which means that all #defines now use
MESON_SAR_ADC_ as prefix, while all enums, static global variables,
structs and functions use meson_sar_adc_ as prefix
- rebased .dts and clk patches to apply to khilman's latest v4.11/dt64
(a minor conflict had to be resolved in the clk patch due to
"clk: meson-gxbb: Export HDMI clocks")
- added Tested-by: Neil Armstrong <narmstrong@baylibre.com> to all
patches (thanks for testing!)
Changes since v1 (all changes are for patch #3, except where noted):
- fix IRQ number in meson-gx.dtsi (thanks to Heiner Kallweit for
providing the correct value), affects patch #4
- move the most used members of meson_saradc_priv to the beginning
- remove unused struct member "completion" from meson_saradc_priv
- use devm_kasprintf() instead of snprintf() + devm_kstrdup()
- initialize indio_dev->dev.parent earlier in meson_saradc_probe()
- moved meson_saradc_clear_fifo() logic to a separate function
- add comment why a do ... while loop is required in
meson_saradc_wait_busy_clear()
- remove SAR_ADC_NUM_CHANNELS and SAR_ADC_VALUE_MASK macros (each of them
was only used once and it's an unneeded level of abstraction)
- fixed multiline comment syntax violations
- dropped unneeded log messages during initialization
- set iio_dev name to "meson-gxbb-saradc" or "meson-gxl-saradc"
- use "indio_dev->dev.parent" in all kernel log calls (dev_warn/err/etc)
to make it show the OF node name (instead of the iio device name)
- introduce struct meson_saradc_data to hold platform-specific
information (such as resolution in bits and the iio_dev name)
Martin Blumenstingl (4):
Documentation: dt-bindings: add the Amlogic Meson SAR ADC
documentation
clk: gxbb: add the SAR ADC clocks and expose them
iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
ARM64: dts: meson: meson-gx: add the SAR ADC
.../bindings/iio/adc/amlogic,meson-saradc.txt | 31 +
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 +
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 +
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 +
drivers/clk/meson/gxbb.c | 48 ++
drivers/clk/meson/gxbb.h | 9 +-
drivers/iio/adc/Kconfig | 12 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/meson_saradc.c | 916 +++++++++++++++++++++
include/dt-bindings/clock/gxbb-clkc.h | 4 +
10 files changed, 1046 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
create mode 100644 drivers/iio/adc/meson_saradc.c
--
2.11.0
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v3 0/4] Amlogic Meson SAR ADC support
@ 2017-01-19 14:58 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-19 14:58 UTC (permalink / raw)
To: linux-arm-kernel
This series add support for the SAR ADC on Amlogic Meson GXBB, GXL and
GXM SoCs.
The hardware on GXBB provides 10-bit ADC results, while GXL and GXM are
providing 12-bit results. Support for older SoCs (Meson8b and Meson8)
can be added with little effort, most of which is testing I guess (I
don't have any pre-GXBB hardware so I can't say).
A new set of clocks had to be added to the GXBB clock controller (used
by the GXBB/GXL/GXM SoCs) which are required to get the ADC working.
The ADC itself can sample multiple channels at the same time and allows
capturing multiple samples (which can be used for filtering/averaging).
The ADC results are stored inside a FIFO register. More details on what
the driver supports (or doesn't) can be found in the description of
patch #3.
The code is based on the public S805 (Meson8b) and S905 (GXBB)
datasheets, as well as by reading (various versions of) the vendor
driver and by inspecting the registers on the vendor kernels of my
testing-hardware.
Typical use-cases for the ADC on the Meson GX SoCs are:
- adc-keys ("ADC attached resistor ladder buttons")
- SoC temperature measurement (not supported by this driver yet as
the system firmware does this already and provides the values via the
SCPI protocol)
- "version-strapping" (different resistor values are used to indicate
the board-revision)
- and of course typical ADC measurements
Thanks to Heiner Kallweit, Jonathan Cameron, Lars-Peter Clausen and
Peter Meerwald-Stadler for reviewing this series and providing valuable
input!
Changes since v2 (all changes are for patch #3, except where noted):
- fixed another typo in the interrupt (patch #4, thanks again Heiner
Kallweit)
- change namespace of all register #defines to MESON_SAR_ADC (I
intentionally decided to keep SAR_ADC in it because that's the way
registers are named in the datasheet, thus making it easy to match the
registers without having to look up the offset all the time)
- added additional parenthesis around MACRO parameters for extra safety
- removed unused definition for SAR_ADC_REG3_ADC_CLK_DIV_MASK (as we
already have SAR_ADC_REG3_ADC_CLK_DIV_SHIFT and
SAR_ADC_REG3_ADC_CLK_DIV_WIDTH which are used instead)
- change value of "indexed" from "true" to "1"
- remove type parameter from MESON_SAR_ADC_CHAN macro as all channels are
currently IIO_VOLTAGE channels
- fixed another multi-line comment style violation
- added timeout to meson_saradc_lock() (unlikely to be triggered, but
better safe then sorry - which would mean that we'd be keeping one core
busy infinitely)
- fixed meson_saradc_remove() call order (first unregister the iio_dev,
then disable the hardware instead of the other way around)
- use "consistent prefixing", which means that all #defines now use
MESON_SAR_ADC_ as prefix, while all enums, static global variables,
structs and functions use meson_sar_adc_ as prefix
- rebased .dts and clk patches to apply to khilman's latest v4.11/dt64
(a minor conflict had to be resolved in the clk patch due to
"clk: meson-gxbb: Export HDMI clocks")
- added Tested-by: Neil Armstrong <narmstrong@baylibre.com> to all
patches (thanks for testing!)
Changes since v1 (all changes are for patch #3, except where noted):
- fix IRQ number in meson-gx.dtsi (thanks to Heiner Kallweit for
providing the correct value), affects patch #4
- move the most used members of meson_saradc_priv to the beginning
- remove unused struct member "completion" from meson_saradc_priv
- use devm_kasprintf() instead of snprintf() + devm_kstrdup()
- initialize indio_dev->dev.parent earlier in meson_saradc_probe()
- moved meson_saradc_clear_fifo() logic to a separate function
- add comment why a do ... while loop is required in
meson_saradc_wait_busy_clear()
- remove SAR_ADC_NUM_CHANNELS and SAR_ADC_VALUE_MASK macros (each of them
was only used once and it's an unneeded level of abstraction)
- fixed multiline comment syntax violations
- dropped unneeded log messages during initialization
- set iio_dev name to "meson-gxbb-saradc" or "meson-gxl-saradc"
- use "indio_dev->dev.parent" in all kernel log calls (dev_warn/err/etc)
to make it show the OF node name (instead of the iio device name)
- introduce struct meson_saradc_data to hold platform-specific
information (such as resolution in bits and the iio_dev name)
Martin Blumenstingl (4):
Documentation: dt-bindings: add the Amlogic Meson SAR ADC
documentation
clk: gxbb: add the SAR ADC clocks and expose them
iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
ARM64: dts: meson: meson-gx: add the SAR ADC
.../bindings/iio/adc/amlogic,meson-saradc.txt | 31 +
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 +
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 +
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 +
drivers/clk/meson/gxbb.c | 48 ++
drivers/clk/meson/gxbb.h | 9 +-
drivers/iio/adc/Kconfig | 12 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/meson_saradc.c | 916 +++++++++++++++++++++
include/dt-bindings/clock/gxbb-clkc.h | 4 +
10 files changed, 1046 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
create mode 100644 drivers/iio/adc/meson_saradc.c
--
2.11.0
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v3 0/4] Amlogic Meson SAR ADC support
@ 2017-01-19 14:58 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-19 14:58 UTC (permalink / raw)
To: linus-amlogic
This series add support for the SAR ADC on Amlogic Meson GXBB, GXL and
GXM SoCs.
The hardware on GXBB provides 10-bit ADC results, while GXL and GXM are
providing 12-bit results. Support for older SoCs (Meson8b and Meson8)
can be added with little effort, most of which is testing I guess (I
don't have any pre-GXBB hardware so I can't say).
A new set of clocks had to be added to the GXBB clock controller (used
by the GXBB/GXL/GXM SoCs) which are required to get the ADC working.
The ADC itself can sample multiple channels at the same time and allows
capturing multiple samples (which can be used for filtering/averaging).
The ADC results are stored inside a FIFO register. More details on what
the driver supports (or doesn't) can be found in the description of
patch #3.
The code is based on the public S805 (Meson8b) and S905 (GXBB)
datasheets, as well as by reading (various versions of) the vendor
driver and by inspecting the registers on the vendor kernels of my
testing-hardware.
Typical use-cases for the ADC on the Meson GX SoCs are:
- adc-keys ("ADC attached resistor ladder buttons")
- SoC temperature measurement (not supported by this driver yet as
the system firmware does this already and provides the values via the
SCPI protocol)
- "version-strapping" (different resistor values are used to indicate
the board-revision)
- and of course typical ADC measurements
Thanks to Heiner Kallweit, Jonathan Cameron, Lars-Peter Clausen and
Peter Meerwald-Stadler for reviewing this series and providing valuable
input!
Changes since v2 (all changes are for patch #3, except where noted):
- fixed another typo in the interrupt (patch #4, thanks again Heiner
Kallweit)
- change namespace of all register #defines to MESON_SAR_ADC (I
intentionally decided to keep SAR_ADC in it because that's the way
registers are named in the datasheet, thus making it easy to match the
registers without having to look up the offset all the time)
- added additional parenthesis around MACRO parameters for extra safety
- removed unused definition for SAR_ADC_REG3_ADC_CLK_DIV_MASK (as we
already have SAR_ADC_REG3_ADC_CLK_DIV_SHIFT and
SAR_ADC_REG3_ADC_CLK_DIV_WIDTH which are used instead)
- change value of "indexed" from "true" to "1"
- remove type parameter from MESON_SAR_ADC_CHAN macro as all channels are
currently IIO_VOLTAGE channels
- fixed another multi-line comment style violation
- added timeout to meson_saradc_lock() (unlikely to be triggered, but
better safe then sorry - which would mean that we'd be keeping one core
busy infinitely)
- fixed meson_saradc_remove() call order (first unregister the iio_dev,
then disable the hardware instead of the other way around)
- use "consistent prefixing", which means that all #defines now use
MESON_SAR_ADC_ as prefix, while all enums, static global variables,
structs and functions use meson_sar_adc_ as prefix
- rebased .dts and clk patches to apply to khilman's latest v4.11/dt64
(a minor conflict had to be resolved in the clk patch due to
"clk: meson-gxbb: Export HDMI clocks")
- added Tested-by: Neil Armstrong <narmstrong@baylibre.com> to all
patches (thanks for testing!)
Changes since v1 (all changes are for patch #3, except where noted):
- fix IRQ number in meson-gx.dtsi (thanks to Heiner Kallweit for
providing the correct value), affects patch #4
- move the most used members of meson_saradc_priv to the beginning
- remove unused struct member "completion" from meson_saradc_priv
- use devm_kasprintf() instead of snprintf() + devm_kstrdup()
- initialize indio_dev->dev.parent earlier in meson_saradc_probe()
- moved meson_saradc_clear_fifo() logic to a separate function
- add comment why a do ... while loop is required in
meson_saradc_wait_busy_clear()
- remove SAR_ADC_NUM_CHANNELS and SAR_ADC_VALUE_MASK macros (each of them
was only used once and it's an unneeded level of abstraction)
- fixed multiline comment syntax violations
- dropped unneeded log messages during initialization
- set iio_dev name to "meson-gxbb-saradc" or "meson-gxl-saradc"
- use "indio_dev->dev.parent" in all kernel log calls (dev_warn/err/etc)
to make it show the OF node name (instead of the iio device name)
- introduce struct meson_saradc_data to hold platform-specific
information (such as resolution in bits and the iio_dev name)
Martin Blumenstingl (4):
Documentation: dt-bindings: add the Amlogic Meson SAR ADC
documentation
clk: gxbb: add the SAR ADC clocks and expose them
iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
ARM64: dts: meson: meson-gx: add the SAR ADC
.../bindings/iio/adc/amlogic,meson-saradc.txt | 31 +
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 +
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 +
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 +
drivers/clk/meson/gxbb.c | 48 ++
drivers/clk/meson/gxbb.h | 9 +-
drivers/iio/adc/Kconfig | 12 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/meson_saradc.c | 916 +++++++++++++++++++++
include/dt-bindings/clock/gxbb-clkc.h | 4 +
10 files changed, 1046 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
create mode 100644 drivers/iio/adc/meson_saradc.c
--
2.11.0
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v3 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
2017-01-19 14:58 ` Martin Blumenstingl
(?)
@ 2017-01-19 14:58 ` Martin Blumenstingl
-1 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-19 14:58 UTC (permalink / raw)
To: jic23, knaack.h, lars, pmeerw, robh+dt, mark.rutland, khilman,
linux-iio, devicetree, linux-amlogic, linux-clk
Cc: carlo, catalin.marinas, will.deacon, mturquette, sboyd,
narmstrong, linux-arm-kernel, Martin Blumenstingl
This adds the devicetree binding documentation for the SAR ADC found in
Amlogic Meson SoCs.
Currently only the GXBB, GXL and GXM SoCs are supported.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
---
.../bindings/iio/adc/amlogic,meson-saradc.txt | 31 ++++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
new file mode 100644
index 000000000000..9a0bec7afc63
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
@@ -0,0 +1,31 @@
+* Amlogic Meson SAR (Successive Approximation Register) A/D converter
+
+Required properties:
+- compatible: depending on the SoC this should be one of:
+ - "amlogic,meson-gxbb-saradc" for GXBB
+ - "amlogic,meson-gxl-saradc" for GXL and GXM
+ along with the generic "amlogic,meson-saradc"
+- reg: the physical base address and length of the registers
+- clocks: phandle and clock identifier (see clock-names)
+- clock-names: mandatory clocks:
+ - "clkin" for the reference clock (typically XTAL)
+ - "core" for the SAR ADC core clock
+ optional clocks:
+ - "sana" for the analog clock
+ - "adc_clk" for the ADC (sampling) clock
+ - "adc_sel" for the ADC (sampling) clock mux
+- vref-supply: the regulator supply for the ADC reference voltage
+- #io-channel-cells: must be 1, see ../iio-bindings.txt
+
+Example:
+ saradc: adc@8680 {
+ compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
+ #io-channel-cells = <1>;
+ reg = <0x0 0x8680 0x0 0x34>;
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+ };
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v3 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
@ 2017-01-19 14:58 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-19 14:58 UTC (permalink / raw)
To: linux-arm-kernel
This adds the devicetree binding documentation for the SAR ADC found in
Amlogic Meson SoCs.
Currently only the GXBB, GXL and GXM SoCs are supported.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
---
.../bindings/iio/adc/amlogic,meson-saradc.txt | 31 ++++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
new file mode 100644
index 000000000000..9a0bec7afc63
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
@@ -0,0 +1,31 @@
+* Amlogic Meson SAR (Successive Approximation Register) A/D converter
+
+Required properties:
+- compatible: depending on the SoC this should be one of:
+ - "amlogic,meson-gxbb-saradc" for GXBB
+ - "amlogic,meson-gxl-saradc" for GXL and GXM
+ along with the generic "amlogic,meson-saradc"
+- reg: the physical base address and length of the registers
+- clocks: phandle and clock identifier (see clock-names)
+- clock-names: mandatory clocks:
+ - "clkin" for the reference clock (typically XTAL)
+ - "core" for the SAR ADC core clock
+ optional clocks:
+ - "sana" for the analog clock
+ - "adc_clk" for the ADC (sampling) clock
+ - "adc_sel" for the ADC (sampling) clock mux
+- vref-supply: the regulator supply for the ADC reference voltage
+- #io-channel-cells: must be 1, see ../iio-bindings.txt
+
+Example:
+ saradc: adc at 8680 {
+ compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
+ #io-channel-cells = <1>;
+ reg = <0x0 0x8680 0x0 0x34>;
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+ };
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v3 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
@ 2017-01-19 14:58 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-19 14:58 UTC (permalink / raw)
To: linus-amlogic
This adds the devicetree binding documentation for the SAR ADC found in
Amlogic Meson SoCs.
Currently only the GXBB, GXL and GXM SoCs are supported.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
---
.../bindings/iio/adc/amlogic,meson-saradc.txt | 31 ++++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
new file mode 100644
index 000000000000..9a0bec7afc63
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
@@ -0,0 +1,31 @@
+* Amlogic Meson SAR (Successive Approximation Register) A/D converter
+
+Required properties:
+- compatible: depending on the SoC this should be one of:
+ - "amlogic,meson-gxbb-saradc" for GXBB
+ - "amlogic,meson-gxl-saradc" for GXL and GXM
+ along with the generic "amlogic,meson-saradc"
+- reg: the physical base address and length of the registers
+- clocks: phandle and clock identifier (see clock-names)
+- clock-names: mandatory clocks:
+ - "clkin" for the reference clock (typically XTAL)
+ - "core" for the SAR ADC core clock
+ optional clocks:
+ - "sana" for the analog clock
+ - "adc_clk" for the ADC (sampling) clock
+ - "adc_sel" for the ADC (sampling) clock mux
+- vref-supply: the regulator supply for the ADC reference voltage
+- #io-channel-cells: must be 1, see ../iio-bindings.txt
+
+Example:
+ saradc: adc at 8680 {
+ compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
+ #io-channel-cells = <1>;
+ reg = <0x0 0x8680 0x0 0x34>;
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+ };
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v3 2/4] clk: gxbb: add the SAR ADC clocks and expose them
2017-01-19 14:58 ` Martin Blumenstingl
(?)
@ 2017-01-19 14:58 ` Martin Blumenstingl
-1 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-19 14:58 UTC (permalink / raw)
To: jic23, knaack.h, lars, pmeerw, robh+dt, mark.rutland, khilman,
linux-iio, devicetree, linux-amlogic, linux-clk
Cc: carlo, catalin.marinas, will.deacon, mturquette, sboyd,
narmstrong, linux-arm-kernel, Martin Blumenstingl
The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
- a mux clock to choose between different ADC reference clocks (this is
2-bit wide, but the datasheet only lists the parents for the first
bit)
- a divider for the input/reference clock
- a gate which enables the ADC clock
Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
CLKID_SANA (which seems to enable the analog inputs, but unfortunately
there is no documentation for this - we just mimic what the vendor
driver does).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/clk/meson/gxbb.c | 48 +++++++++++++++++++++++++++++++++++
drivers/clk/meson/gxbb.h | 9 ++++---
include/dt-bindings/clock/gxbb-clkc.h | 4 +++
3 files changed, 58 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 9d9af446bafc..1c1ec137a3cc 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -564,6 +564,46 @@ static struct clk_gate gxbb_clk81 = {
},
};
+static struct clk_mux gxbb_sar_adc_clk_sel = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .mask = 0x3,
+ .shift = 9,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk_sel",
+ .ops = &clk_mux_ops,
+ /* NOTE: The datasheet doesn't list the parents for bit 10 */
+ .parent_names = (const char *[]){ "xtal", "clk81", },
+ .num_parents = 2,
+ },
+};
+
+static struct clk_divider gxbb_sar_adc_clk_div = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .shift = 0,
+ .width = 8,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk_div",
+ .ops = &clk_divider_ops,
+ .parent_names = (const char *[]){ "sar_adc_clk_sel" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_gate gxbb_sar_adc_clk = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .bit_idx = 8,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk",
+ .ops = &clk_gate_ops,
+ .parent_names = (const char *[]){ "sar_adc_clk_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
/* Everything Else (EE) domain gates */
static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -754,6 +794,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
[CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
[CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
[CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
+ [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
+ [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
+ [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
},
.num = NR_CLKS,
};
@@ -856,6 +899,7 @@ static struct clk_gate *gxbb_clk_gates[] = {
&gxbb_emmc_a,
&gxbb_emmc_b,
&gxbb_emmc_c,
+ &gxbb_sar_adc_clk,
};
static int gxbb_clkc_probe(struct platform_device *pdev)
@@ -888,6 +932,10 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
gxbb_mpeg_clk_sel.reg = clk_base + (u64)gxbb_mpeg_clk_sel.reg;
gxbb_mpeg_clk_div.reg = clk_base + (u64)gxbb_mpeg_clk_div.reg;
+ /* Populate the base address for the SAR ADC clks */
+ gxbb_sar_adc_clk_sel.reg = clk_base + (u64)gxbb_sar_adc_clk_sel.reg;
+ gxbb_sar_adc_clk_div.reg = clk_base + (u64)gxbb_sar_adc_clk_div.reg;
+
/* Populate base address for gates */
for (i = 0; i < ARRAY_SIZE(gxbb_clk_gates); i++)
gxbb_clk_gates[i]->reg = clk_base +
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 2139e97f5e39..dc487180f847 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -191,7 +191,7 @@
#define CLKID_PERIPHS 20
#define CLKID_SPICC 21
/* CLKID_I2C */
-#define CLKID_SAR_ADC 23
+/* #define CLKID_SAR_ADC */
#define CLKID_SMART_CARD 24
#define CLKID_RNG0 25
#define CLKID_UART0 26
@@ -237,7 +237,7 @@
#define CLKID_MMC_PCLK 66
#define CLKID_DVIN 67
#define CLKID_UART2 68
-#define CLKID_SANA 69
+/* #define CLKID_SANA */
#define CLKID_VPU_INTR 70
#define CLKID_SEC_AHB_AHB3_BRIDGE 71
#define CLKID_CLK81_A53 72
@@ -265,8 +265,11 @@
/* CLKID_SD_EMMC_A */
/* CLKID_SD_EMMC_B */
/* CLKID_SD_EMMC_C */
+/* CLKID_SAR_ADC_CLK */
+/* CLKID_SAR_ADC_SEL */
+#define CLKID_SAR_ADC_DIV 99
-#define NR_CLKS 97
+#define NR_CLKS 100
/* include the CLKIDs that have been made part of the stable DT binding */
#include <dt-bindings/clock/gxbb-clkc.h>
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index da1d473a5a3a..692846c7941b 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -14,6 +14,7 @@
#define CLKID_MPLL2 15
#define CLKID_SPI 34
#define CLKID_I2C 22
+#define CLKID_SAR_ADC 23
#define CLKID_ETH 36
#define CLKID_USB0 50
#define CLKID_USB1 51
@@ -21,10 +22,13 @@
#define CLKID_HDMI_PCLK 63
#define CLKID_USB1_DDR_BRIDGE 64
#define CLKID_USB0_DDR_BRIDGE 65
+#define CLKID_SANA 69
#define CLKID_GCLK_VENCI_INT0 77
#define CLKID_AO_I2C 93
#define CLKID_SD_EMMC_A 94
#define CLKID_SD_EMMC_B 95
#define CLKID_SD_EMMC_C 96
+#define CLKID_SAR_ADC_CLK 97
+#define CLKID_SAR_ADC_SEL 98
#endif /* __GXBB_CLKC_H */
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v3 2/4] clk: gxbb: add the SAR ADC clocks and expose them
@ 2017-01-19 14:58 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-19 14:58 UTC (permalink / raw)
To: linux-arm-kernel
The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
- a mux clock to choose between different ADC reference clocks (this is
2-bit wide, but the datasheet only lists the parents for the first
bit)
- a divider for the input/reference clock
- a gate which enables the ADC clock
Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
CLKID_SANA (which seems to enable the analog inputs, but unfortunately
there is no documentation for this - we just mimic what the vendor
driver does).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/clk/meson/gxbb.c | 48 +++++++++++++++++++++++++++++++++++
drivers/clk/meson/gxbb.h | 9 ++++---
include/dt-bindings/clock/gxbb-clkc.h | 4 +++
3 files changed, 58 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 9d9af446bafc..1c1ec137a3cc 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -564,6 +564,46 @@ static struct clk_gate gxbb_clk81 = {
},
};
+static struct clk_mux gxbb_sar_adc_clk_sel = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .mask = 0x3,
+ .shift = 9,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk_sel",
+ .ops = &clk_mux_ops,
+ /* NOTE: The datasheet doesn't list the parents for bit 10 */
+ .parent_names = (const char *[]){ "xtal", "clk81", },
+ .num_parents = 2,
+ },
+};
+
+static struct clk_divider gxbb_sar_adc_clk_div = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .shift = 0,
+ .width = 8,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk_div",
+ .ops = &clk_divider_ops,
+ .parent_names = (const char *[]){ "sar_adc_clk_sel" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_gate gxbb_sar_adc_clk = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .bit_idx = 8,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk",
+ .ops = &clk_gate_ops,
+ .parent_names = (const char *[]){ "sar_adc_clk_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
/* Everything Else (EE) domain gates */
static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -754,6 +794,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
[CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
[CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
[CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
+ [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
+ [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
+ [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
},
.num = NR_CLKS,
};
@@ -856,6 +899,7 @@ static struct clk_gate *gxbb_clk_gates[] = {
&gxbb_emmc_a,
&gxbb_emmc_b,
&gxbb_emmc_c,
+ &gxbb_sar_adc_clk,
};
static int gxbb_clkc_probe(struct platform_device *pdev)
@@ -888,6 +932,10 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
gxbb_mpeg_clk_sel.reg = clk_base + (u64)gxbb_mpeg_clk_sel.reg;
gxbb_mpeg_clk_div.reg = clk_base + (u64)gxbb_mpeg_clk_div.reg;
+ /* Populate the base address for the SAR ADC clks */
+ gxbb_sar_adc_clk_sel.reg = clk_base + (u64)gxbb_sar_adc_clk_sel.reg;
+ gxbb_sar_adc_clk_div.reg = clk_base + (u64)gxbb_sar_adc_clk_div.reg;
+
/* Populate base address for gates */
for (i = 0; i < ARRAY_SIZE(gxbb_clk_gates); i++)
gxbb_clk_gates[i]->reg = clk_base +
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 2139e97f5e39..dc487180f847 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -191,7 +191,7 @@
#define CLKID_PERIPHS 20
#define CLKID_SPICC 21
/* CLKID_I2C */
-#define CLKID_SAR_ADC 23
+/* #define CLKID_SAR_ADC */
#define CLKID_SMART_CARD 24
#define CLKID_RNG0 25
#define CLKID_UART0 26
@@ -237,7 +237,7 @@
#define CLKID_MMC_PCLK 66
#define CLKID_DVIN 67
#define CLKID_UART2 68
-#define CLKID_SANA 69
+/* #define CLKID_SANA */
#define CLKID_VPU_INTR 70
#define CLKID_SEC_AHB_AHB3_BRIDGE 71
#define CLKID_CLK81_A53 72
@@ -265,8 +265,11 @@
/* CLKID_SD_EMMC_A */
/* CLKID_SD_EMMC_B */
/* CLKID_SD_EMMC_C */
+/* CLKID_SAR_ADC_CLK */
+/* CLKID_SAR_ADC_SEL */
+#define CLKID_SAR_ADC_DIV 99
-#define NR_CLKS 97
+#define NR_CLKS 100
/* include the CLKIDs that have been made part of the stable DT binding */
#include <dt-bindings/clock/gxbb-clkc.h>
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index da1d473a5a3a..692846c7941b 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -14,6 +14,7 @@
#define CLKID_MPLL2 15
#define CLKID_SPI 34
#define CLKID_I2C 22
+#define CLKID_SAR_ADC 23
#define CLKID_ETH 36
#define CLKID_USB0 50
#define CLKID_USB1 51
@@ -21,10 +22,13 @@
#define CLKID_HDMI_PCLK 63
#define CLKID_USB1_DDR_BRIDGE 64
#define CLKID_USB0_DDR_BRIDGE 65
+#define CLKID_SANA 69
#define CLKID_GCLK_VENCI_INT0 77
#define CLKID_AO_I2C 93
#define CLKID_SD_EMMC_A 94
#define CLKID_SD_EMMC_B 95
#define CLKID_SD_EMMC_C 96
+#define CLKID_SAR_ADC_CLK 97
+#define CLKID_SAR_ADC_SEL 98
#endif /* __GXBB_CLKC_H */
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v3 2/4] clk: gxbb: add the SAR ADC clocks and expose them
@ 2017-01-19 14:58 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-19 14:58 UTC (permalink / raw)
To: linus-amlogic
The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
- a mux clock to choose between different ADC reference clocks (this is
2-bit wide, but the datasheet only lists the parents for the first
bit)
- a divider for the input/reference clock
- a gate which enables the ADC clock
Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
CLKID_SANA (which seems to enable the analog inputs, but unfortunately
there is no documentation for this - we just mimic what the vendor
driver does).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/clk/meson/gxbb.c | 48 +++++++++++++++++++++++++++++++++++
drivers/clk/meson/gxbb.h | 9 ++++---
include/dt-bindings/clock/gxbb-clkc.h | 4 +++
3 files changed, 58 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 9d9af446bafc..1c1ec137a3cc 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -564,6 +564,46 @@ static struct clk_gate gxbb_clk81 = {
},
};
+static struct clk_mux gxbb_sar_adc_clk_sel = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .mask = 0x3,
+ .shift = 9,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk_sel",
+ .ops = &clk_mux_ops,
+ /* NOTE: The datasheet doesn't list the parents for bit 10 */
+ .parent_names = (const char *[]){ "xtal", "clk81", },
+ .num_parents = 2,
+ },
+};
+
+static struct clk_divider gxbb_sar_adc_clk_div = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .shift = 0,
+ .width = 8,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk_div",
+ .ops = &clk_divider_ops,
+ .parent_names = (const char *[]){ "sar_adc_clk_sel" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_gate gxbb_sar_adc_clk = {
+ .reg = (void *)HHI_SAR_CLK_CNTL,
+ .bit_idx = 8,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sar_adc_clk",
+ .ops = &clk_gate_ops,
+ .parent_names = (const char *[]){ "sar_adc_clk_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
/* Everything Else (EE) domain gates */
static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -754,6 +794,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
[CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
[CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
[CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
+ [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
+ [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
+ [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
},
.num = NR_CLKS,
};
@@ -856,6 +899,7 @@ static struct clk_gate *gxbb_clk_gates[] = {
&gxbb_emmc_a,
&gxbb_emmc_b,
&gxbb_emmc_c,
+ &gxbb_sar_adc_clk,
};
static int gxbb_clkc_probe(struct platform_device *pdev)
@@ -888,6 +932,10 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
gxbb_mpeg_clk_sel.reg = clk_base + (u64)gxbb_mpeg_clk_sel.reg;
gxbb_mpeg_clk_div.reg = clk_base + (u64)gxbb_mpeg_clk_div.reg;
+ /* Populate the base address for the SAR ADC clks */
+ gxbb_sar_adc_clk_sel.reg = clk_base + (u64)gxbb_sar_adc_clk_sel.reg;
+ gxbb_sar_adc_clk_div.reg = clk_base + (u64)gxbb_sar_adc_clk_div.reg;
+
/* Populate base address for gates */
for (i = 0; i < ARRAY_SIZE(gxbb_clk_gates); i++)
gxbb_clk_gates[i]->reg = clk_base +
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 2139e97f5e39..dc487180f847 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -191,7 +191,7 @@
#define CLKID_PERIPHS 20
#define CLKID_SPICC 21
/* CLKID_I2C */
-#define CLKID_SAR_ADC 23
+/* #define CLKID_SAR_ADC */
#define CLKID_SMART_CARD 24
#define CLKID_RNG0 25
#define CLKID_UART0 26
@@ -237,7 +237,7 @@
#define CLKID_MMC_PCLK 66
#define CLKID_DVIN 67
#define CLKID_UART2 68
-#define CLKID_SANA 69
+/* #define CLKID_SANA */
#define CLKID_VPU_INTR 70
#define CLKID_SEC_AHB_AHB3_BRIDGE 71
#define CLKID_CLK81_A53 72
@@ -265,8 +265,11 @@
/* CLKID_SD_EMMC_A */
/* CLKID_SD_EMMC_B */
/* CLKID_SD_EMMC_C */
+/* CLKID_SAR_ADC_CLK */
+/* CLKID_SAR_ADC_SEL */
+#define CLKID_SAR_ADC_DIV 99
-#define NR_CLKS 97
+#define NR_CLKS 100
/* include the CLKIDs that have been made part of the stable DT binding */
#include <dt-bindings/clock/gxbb-clkc.h>
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index da1d473a5a3a..692846c7941b 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -14,6 +14,7 @@
#define CLKID_MPLL2 15
#define CLKID_SPI 34
#define CLKID_I2C 22
+#define CLKID_SAR_ADC 23
#define CLKID_ETH 36
#define CLKID_USB0 50
#define CLKID_USB1 51
@@ -21,10 +22,13 @@
#define CLKID_HDMI_PCLK 63
#define CLKID_USB1_DDR_BRIDGE 64
#define CLKID_USB0_DDR_BRIDGE 65
+#define CLKID_SANA 69
#define CLKID_GCLK_VENCI_INT0 77
#define CLKID_AO_I2C 93
#define CLKID_SD_EMMC_A 94
#define CLKID_SD_EMMC_B 95
#define CLKID_SD_EMMC_C 96
+#define CLKID_SAR_ADC_CLK 97
+#define CLKID_SAR_ADC_SEL 98
#endif /* __GXBB_CLKC_H */
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v3 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
2017-01-19 14:58 ` Martin Blumenstingl
(?)
@ 2017-01-19 14:58 ` Martin Blumenstingl
-1 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-19 14:58 UTC (permalink / raw)
To: jic23, knaack.h, lars, pmeerw, robh+dt, mark.rutland, khilman,
linux-iio, devicetree, linux-amlogic, linux-clk
Cc: carlo, catalin.marinas, will.deacon, mturquette, sboyd,
narmstrong, linux-arm-kernel, Martin Blumenstingl
This adds support for the SAR (Successive Approximation Register) ADC
on the Amlogic Meson SoCs.
The code is based on the public S805 (Meson8b) and S905 (GXBB)
datasheets (see [0] and [1]), as well as by reading (various versions
of) the vendor driver and by inspecting the registers on the vendor
kernels of my testing-hardware.
Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
The code was written to support older SoCs (Meson8 and Meson8b) as well,
but due to lack of actual testing-hardware no of_device_id was added for
these.
Two "features" from the vendor driver are currently missing:
- the vendor driver uses channel #7 for calibration (this improves the
accuracy of the results - in my tests the results were less than 3%
off without calibration compared to the vendor driver). Adding support
for this should be easy, but is not required for most applications.
- channel #6 is connected to the SoCs internal temperature sensor.
Adding support for this is probably not so easy since (based on the
u-boot sources) most SoC versions are using different registers and
algorithms for the conversion from "ADC value" to temperature.
Supported by the hardware but currently not supported by the driver:
- reading multiple channels at the same time (the hardware has a FIFO
buffer which stores multiple results)
- continuous sampling (this would require a way to enable this
individually because otherwise the ADC would be drawing power
constantly)
- interrupt support (similar to the vendor driver this new driver is
polling the results. It is unclear if the IRQ-mode is supported on
older (Meson6 or Meson8) hardware as well or if there are any errata)
[0]
http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
[1] http://dn.odroid.com/S905/DataSheet/S905_Public_Datasheet_V1.1.4.pdf
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/iio/adc/Kconfig | 12 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/meson_saradc.c | 916 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 929 insertions(+)
create mode 100644 drivers/iio/adc/meson_saradc.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 9c8b558ba19e..86059b9b91bf 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -371,6 +371,18 @@ config MEN_Z188_ADC
This driver can also be built as a module. If so, the module will be
called men_z188_adc.
+config MESON_SARADC
+ tristate "Amlogic Meson SAR ADC driver"
+ default ARCH_MESON
+ depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
+ select REGMAP_MMIO
+ help
+ Say yes here to build support for the SAR ADC found in Amlogic Meson
+ SoCs.
+
+ To compile this driver as a module, choose M here: the
+ module will be called meson_saradc.
+
config MXS_LRADC
tristate "Freescale i.MX23/i.MX28 LRADC"
depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index d36c4be8d1fc..de05b9e75f8f 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
obj-$(CONFIG_MCP3422) += mcp3422.o
obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
+obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
obj-$(CONFIG_NAU7802) += nau7802.o
obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
new file mode 100644
index 000000000000..11a9686d2a9c
--- /dev/null
+++ b/drivers/iio/adc/meson_saradc.c
@@ -0,0 +1,916 @@
+/*
+ * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
+ *
+ * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/iio/iio.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+
+#define MESON_SAR_ADC_REG0 0x00
+ #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31)
+ #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
+ #define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30)
+ #define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29)
+ #define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
+ #define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27)
+ #define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26)
+ #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
+ #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
+ #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
+ #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
+ #define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14)
+ #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
+ #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
+ #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
+ #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
+ #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
+ #define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2)
+ #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
+ #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
+
+#define MESON_SAR_ADC_CHAN_LIST 0x04
+ #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
+ #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \
+ (GENMASK(2, 0) << ((_chan) * 3))
+
+#define MESON_SAR_ADC_AVG_CNTL 0x08
+ #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
+ (16 + ((_chan) * 2))
+ #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
+ (GENMASK(17, 16) << ((_chan) * 2))
+ #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
+ (0 + ((_chan) * 2))
+ #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
+ (GENMASK(1, 0) << ((_chan) * 2))
+
+#define MESON_SAR_ADC_REG3 0x0c
+ #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
+ #define MESON_SAR_ADC_REG3_CLK_EN BIT(30)
+ #define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
+ #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
+ #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
+ #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
+ #define MESON_SAR_ADC_REG3_DETECT_EN BIT(22)
+ #define MESON_SAR_ADC_REG3_ADC_EN BIT(21)
+ #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
+ #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
+ #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
+ #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
+ #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
+ #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
+
+#define MESON_SAR_ADC_DELAY 0x10
+ #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
+ #define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15)
+ #define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
+ #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
+ #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
+ #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
+
+#define MESON_SAR_ADC_LAST_RD 0x14
+ #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
+ #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
+
+#define MESON_SAR_ADC_FIFO_RD 0x18
+ #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
+ #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
+
+#define MESON_SAR_ADC_AUX_SW 0x1c
+ #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
+ (GENMASK(10, 8) << (((_chan) - 2) * 2))
+ #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
+ #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
+ #define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4)
+ #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
+ #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
+ #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
+ #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
+
+#define MESON_SAR_ADC_CHAN_10_SW 0x20
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
+
+#define MESON_SAR_ADC_DETECT_IDLE_SW 0x24
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0)
+
+#define MESON_SAR_ADC_DELTA_10 0x28
+ #define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
+ #define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
+ #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
+ #define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
+ #define MESON_SAR_ADC_DELTA_10_TS_C_SHIFT 11
+ #define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
+ #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
+ #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
+
+/*
+ * NOTE: registers from here are undocumented (the vendor Linux kernel driver
+ * and u-boot source served as reference). These only seem to be relevant on
+ * GXBB and newer.
+ */
+#define MESON_SAR_ADC_REG11 0x2c
+ #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13)
+
+#define MESON_SAR_ADC_REG13 0x34
+ #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
+
+#define MESON_SAR_ADC_MAX_FIFO_SIZE 32
+
+#define MESON_SAR_ADC_CHAN(_chan) { \
+ .type = IIO_VOLTAGE, \
+ .indexed = 1, \
+ .channel = _chan, \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
+ BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
+ .datasheet_name = "SAR_ADC_CH"#_chan, \
+}
+
+/*
+ * TODO: the hardware supports IIO_TEMP for channel 6 as well which is
+ * currently not supported by this driver.
+ */
+static const struct iio_chan_spec meson_sar_adc_iio_channels[] = {
+ MESON_SAR_ADC_CHAN(0),
+ MESON_SAR_ADC_CHAN(1),
+ MESON_SAR_ADC_CHAN(2),
+ MESON_SAR_ADC_CHAN(3),
+ MESON_SAR_ADC_CHAN(4),
+ MESON_SAR_ADC_CHAN(5),
+ MESON_SAR_ADC_CHAN(6),
+ MESON_SAR_ADC_CHAN(7),
+ IIO_CHAN_SOFT_TIMESTAMP(8),
+};
+
+enum meson_sar_adc_avg_mode {
+ NO_AVERAGING = 0x0,
+ MEAN_AVERAGING = 0x1,
+ MEDIAN_AVERAGING = 0x2,
+};
+
+enum meson_sar_adc_num_samples {
+ ONE_SAMPLE = 0x0,
+ TWO_SAMPLES = 0x1,
+ FOUR_SAMPLES = 0x2,
+ EIGHT_SAMPLES = 0x3,
+};
+
+enum meson_sar_adc_chan7_mux_sel {
+ CHAN7_MUX_VSS = 0x0,
+ CHAN7_MUX_VDD_DIV4 = 0x1,
+ CHAN7_MUX_VDD_DIV2 = 0x2,
+ CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
+ CHAN7_MUX_VDD = 0x4,
+ CHAN7_MUX_CH7_INPUT = 0x7,
+};
+
+struct meson_sar_adc_data {
+ unsigned int resolution;
+ const char *name;
+};
+
+struct meson_sar_adc_priv {
+ struct regmap *regmap;
+ struct regulator *vref;
+ const struct meson_sar_adc_data *data;
+ struct clk *clkin;
+ struct clk *core_clk;
+ struct clk *sana_clk;
+ struct clk *adc_sel_clk;
+ struct clk *adc_clk;
+ struct clk_gate clk_gate;
+ struct clk *adc_div_clk;
+ struct clk_divider clk_div;
+};
+
+static const struct regmap_config meson_sar_adc_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = MESON_SAR_ADC_REG13,
+};
+
+static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);
+
+ return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
+}
+
+static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ int regval, timeout = 10000;
+
+ /*
+ * NOTE: we need a small delay before reading the status, otherwise
+ * the sample engine may not have started internally (which would
+ * seem to us that sampling is already finished).
+ */
+ do {
+ udelay(1);
+ regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);
+ } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
+
+ if (timeout < 0)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ int *val)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0;
+
+ ret = meson_sar_adc_wait_busy_clear(indio_dev);
+ if (ret)
+ return ret;
+
+ while (meson_sar_adc_get_fifo_count(indio_dev) > 0 &&
+ count < MESON_SAR_ADC_MAX_FIFO_SIZE) {
+ regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val);
+
+ fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK,
+ regval);
+ if (fifo_chan != chan->channel)
+ continue;
+
+ fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK,
+ regval);
+ fifo_val &= (BIT(priv->data->resolution) - 1);
+
+ sum += fifo_val;
+ count++;
+ }
+
+ if (!count)
+ return -ENOENT;
+
+ *val = sum / count;
+
+ return 0;
+}
+
+static void meson_sar_adc_set_averaging(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ enum meson_sar_adc_avg_mode mode,
+ enum meson_sar_adc_num_samples samples)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ int val, channel = chan->channel;
+
+ val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(channel);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
+ MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(channel),
+ val);
+
+ val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(channel);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
+ MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(channel), val);
+}
+
+static void meson_sar_adc_enable_channel(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ /*
+ * the SAR ADC engine allows sampling multiple channels at the same
+ * time. to keep it simple we're only working with one *internal*
+ * channel, which starts counting at index 0 (which means: count = 1).
+ */
+ regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
+ MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
+
+ /* map channel index 0 to the channel which we want to read */
+ regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0),
+ chan->channel);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
+ MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval);
+
+ regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
+ chan->channel);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
+ MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
+ regval);
+
+ regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
+ chan->channel);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
+ MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
+ regval);
+
+ if (chan->channel == 6)
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
+ MESON_SAR_ADC_DELTA_10_TEMP_SEL, 0);
+}
+
+static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev,
+ enum meson_sar_adc_chan7_mux_sel sel)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
+ MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
+
+ usleep_range(10, 20);
+}
+
+static void meson_sar_adc_start_sample_engine(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
+ MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
+ MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
+
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
+ MESON_SAR_ADC_REG0_SAMPLING_START,
+ MESON_SAR_ADC_REG0_SAMPLING_START);
+}
+
+static void meson_sar_adc_stop_sample_engine(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
+ MESON_SAR_ADC_REG0_SAMPLING_STOP,
+ MESON_SAR_ADC_REG0_SAMPLING_STOP);
+
+ /* wait until all modules are stopped */
+ meson_sar_adc_wait_busy_clear(indio_dev);
+
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
+ MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
+}
+
+static int meson_sar_adc_lock(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ int val, timeout = 10000;
+
+ mutex_lock(&indio_dev->mlock);
+
+ /* prevent BL30 from using the SAR ADC while we are using it */
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
+ MESON_SAR_ADC_DELAY_KERNEL_BUSY,
+ MESON_SAR_ADC_DELAY_KERNEL_BUSY);
+
+ /* wait until BL30 releases it's lock (so we can use the SAR ADC) */
+ do {
+ udelay(1);
+ regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val);
+ } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--);
+
+ if (timeout < 0)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static void meson_sar_adc_unlock(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+
+ /* allow BL30 to use the SAR ADC again */
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
+ MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0);
+
+ mutex_unlock(&indio_dev->mlock);
+}
+
+static void meson_sar_adc_clear_fifo(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ int count;
+
+ for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {
+ if (!meson_sar_adc_get_fifo_count(indio_dev))
+ break;
+
+ regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, 0);
+ }
+}
+
+static int meson_sar_adc_get_sample(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ enum meson_sar_adc_avg_mode avg_mode,
+ enum meson_sar_adc_num_samples avg_samples,
+ int *val)
+{
+ int ret;
+
+ ret = meson_sar_adc_lock(indio_dev);
+ if (ret)
+ return ret;
+
+ /* clear the FIFO to make sure we're not reading old values */
+ meson_sar_adc_clear_fifo(indio_dev);
+
+ meson_sar_adc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
+
+ meson_sar_adc_enable_channel(indio_dev, chan);
+
+ meson_sar_adc_start_sample_engine(indio_dev);
+ ret = meson_sar_adc_read_raw_sample(indio_dev, chan, val);
+ meson_sar_adc_stop_sample_engine(indio_dev);
+
+ meson_sar_adc_unlock(indio_dev);
+
+ if (ret) {
+ dev_warn(indio_dev->dev.parent,
+ "failed to read sample for channel %d: %d\n",
+ chan->channel, ret);
+ return ret;
+ }
+
+ return IIO_VAL_INT;
+}
+
+static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ int *val, int *val2, long mask)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ int ret;
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ return meson_sar_adc_get_sample(indio_dev, chan, NO_AVERAGING,
+ ONE_SAMPLE, val);
+ break;
+
+ case IIO_CHAN_INFO_AVERAGE_RAW:
+ return meson_sar_adc_get_sample(indio_dev, chan,
+ MEAN_AVERAGING, EIGHT_SAMPLES,
+ val);
+ break;
+
+ case IIO_CHAN_INFO_SCALE:
+ ret = regulator_get_voltage(priv->vref);
+ if (ret < 0) {
+ dev_err(indio_dev->dev.parent,
+ "failed to get vref voltage: %d\n", ret);
+ return ret;
+ }
+
+ *val = ret / 1000;
+ *val2 = priv->data->resolution;
+ return IIO_VAL_FRACTIONAL_LOG2;
+
+ default:
+ return -EINVAL;
+ }
+}
+
+static int meson_sar_adc_clk_init(struct iio_dev *indio_dev,
+ void __iomem *base)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ struct clk_init_data init;
+ const char *clk_parents[1];
+
+ init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_div",
+ of_node_full_name(indio_dev->dev.of_node));
+ init.flags = 0;
+ init.ops = &clk_divider_ops;
+ clk_parents[0] = __clk_get_name(priv->clkin);
+ init.parent_names = clk_parents;
+ init.num_parents = 1;
+
+ priv->clk_div.reg = base + MESON_SAR_ADC_REG3;
+ priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
+ priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
+ priv->clk_div.hw.init = &init;
+ priv->clk_div.flags = 0;
+
+ priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
+ &priv->clk_div.hw);
+ if (WARN_ON(IS_ERR(priv->adc_div_clk)))
+ return PTR_ERR(priv->adc_div_clk);
+
+ init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_en",
+ of_node_full_name(indio_dev->dev.of_node));
+ init.flags = CLK_SET_RATE_PARENT;
+ init.ops = &clk_gate_ops;
+ clk_parents[0] = __clk_get_name(priv->adc_div_clk);
+ init.parent_names = clk_parents;
+ init.num_parents = 1;
+
+ priv->clk_gate.reg = base + MESON_SAR_ADC_REG3;
+ priv->clk_gate.bit_idx = fls(MESON_SAR_ADC_REG3_CLK_EN);
+ priv->clk_gate.hw.init = &init;
+
+ priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
+ if (WARN_ON(IS_ERR(priv->adc_clk)))
+ return PTR_ERR(priv->adc_clk);
+
+ return 0;
+}
+
+static int meson_sar_adc_init(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ int regval, ret;
+
+ /*
+ * make sure we start at CH7 input since the other muxes are only used
+ * for internal calibration.
+ */
+ meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
+
+ /*
+ * leave sampling delay and the input clocks as configured by BL30 to
+ * make sure BL30 gets the values it expects when reading the
+ * temperature sensor.
+ */
+ regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val);
+ if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED)
+ return 0;
+
+ meson_sar_adc_stop_sample_engine(indio_dev);
+
+ /* update the channel 6 MUX to select the temperature sensor */
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
+ MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
+ MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
+
+ /* disable all channels by default */
+ regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);
+
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
+ MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
+ MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY,
+ MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY);
+
+ /* delay between two samples = (10+1) * 1uS */
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
+ MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+ FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,
+ 10));
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
+ MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
+ FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
+ 0));
+
+ /* delay between two samples = (10+1) * 1uS */
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
+ MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+ FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+ 10));
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
+ MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
+ FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
+ 1));
+
+ ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
+ if (ret) {
+ dev_err(indio_dev->dev.parent,
+ "failed to set adc parent to clkin\n");
+ return ret;
+ }
+
+ ret = clk_set_rate(priv->adc_clk, 1200000);
+ if (ret) {
+ dev_err(indio_dev->dev.parent,
+ "failed to set adc clock rate\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ int ret;
+
+ ret = meson_sar_adc_lock(indio_dev);
+ if (ret)
+ goto err_lock;
+
+ ret = regulator_enable(priv->vref);
+ if (ret < 0) {
+ dev_err(indio_dev->dev.parent,
+ "failed to enable vref regulator\n");
+ goto err_vref;
+ }
+
+ ret = clk_prepare_enable(priv->core_clk);
+ if (ret) {
+ dev_err(indio_dev->dev.parent, "failed to enable core clk\n");
+ goto err_core_clk;
+ }
+
+ ret = clk_prepare_enable(priv->sana_clk);
+ if (ret) {
+ dev_err(indio_dev->dev.parent, "failed to enable sana clk\n");
+ goto err_sana_clk;
+ }
+
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
+ MESON_SAR_ADC_REG11_BANDGAP_EN,
+ MESON_SAR_ADC_REG11_BANDGAP_EN);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
+ MESON_SAR_ADC_REG3_ADC_EN,
+ MESON_SAR_ADC_REG3_ADC_EN);
+
+ udelay(5);
+
+ ret = clk_prepare_enable(priv->adc_clk);
+ if (ret) {
+ dev_err(indio_dev->dev.parent, "failed to enable adc clk\n");
+ goto err_adc_clk;
+ }
+
+ meson_sar_adc_unlock(indio_dev);
+
+ return 0;
+
+err_adc_clk:
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
+ MESON_SAR_ADC_REG3_ADC_EN, 0);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
+ MESON_SAR_ADC_REG11_BANDGAP_EN, 0);
+ clk_disable_unprepare(priv->sana_clk);
+err_sana_clk:
+ clk_disable_unprepare(priv->core_clk);
+err_core_clk:
+ regulator_disable(priv->vref);
+err_vref:
+ meson_sar_adc_unlock(indio_dev);
+err_lock:
+ return ret;
+}
+
+static int meson_sar_adc_hw_disable(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ int ret;
+
+ ret = meson_sar_adc_lock(indio_dev);
+ if (ret)
+ return ret;
+
+ clk_disable_unprepare(priv->adc_clk);
+
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
+ MESON_SAR_ADC_REG3_ADC_EN, 0);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
+ MESON_SAR_ADC_REG11_BANDGAP_EN, 0);
+
+ clk_disable_unprepare(priv->sana_clk);
+ clk_disable_unprepare(priv->core_clk);
+
+ regulator_disable(priv->vref);
+
+ meson_sar_adc_unlock(indio_dev);
+
+ return 0;
+}
+
+static const struct iio_info meson_sar_adc_iio_info = {
+ .read_raw = meson_sar_adc_iio_info_read_raw,
+ .driver_module = THIS_MODULE,
+};
+
+struct meson_sar_adc_data meson_sar_adc_gxbb_data = {
+ .resolution = 10,
+ .name = "meson-gxbb-saradc",
+};
+
+struct meson_sar_adc_data meson_sar_adc_gxl_data = {
+ .resolution = 12,
+ .name = "meson-gxl-saradc",
+};
+
+static const struct of_device_id meson_sar_adc_of_match[] = {
+ {
+ .compatible = "amlogic,meson-gxbb-saradc",
+ .data = &meson_sar_adc_gxbb_data,
+ }, {
+ .compatible = "amlogic,meson-gxl-saradc",
+ .data = &meson_sar_adc_gxl_data,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, meson_sar_adc_of_match);
+
+static int meson_sar_adc_probe(struct platform_device *pdev)
+{
+ struct meson_sar_adc_priv *priv;
+ struct iio_dev *indio_dev;
+ struct resource *res;
+ void __iomem *base;
+ const struct of_device_id *match;
+ int ret;
+
+ indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
+ if (!indio_dev) {
+ dev_err(&pdev->dev, "failed allocating iio device\n");
+ return -ENOMEM;
+ }
+
+ priv = iio_priv(indio_dev);
+
+ match = of_match_device(meson_sar_adc_of_match, &pdev->dev);
+ priv->data = match->data;
+
+ indio_dev->name = priv->data->name;
+ indio_dev->dev.parent = &pdev->dev;
+ indio_dev->dev.of_node = pdev->dev.of_node;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->info = &meson_sar_adc_iio_info;
+
+ indio_dev->channels = meson_sar_adc_iio_channels;
+ indio_dev->num_channels = ARRAY_SIZE(meson_sar_adc_iio_channels);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
+ &meson_sar_adc_regmap_config);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+ priv->clkin = devm_clk_get(&pdev->dev, "clkin");
+ if (IS_ERR(priv->clkin)) {
+ dev_err(&pdev->dev, "failed to get clkin\n");
+ return PTR_ERR(priv->clkin);
+ }
+
+ priv->core_clk = devm_clk_get(&pdev->dev, "core");
+ if (IS_ERR(priv->core_clk)) {
+ dev_err(&pdev->dev, "failed to get core clk\n");
+ return PTR_ERR(priv->core_clk);
+ }
+
+ priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
+ if (IS_ERR(priv->sana_clk)) {
+ if (PTR_ERR(priv->sana_clk) == -ENOENT) {
+ priv->sana_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get sana clk\n");
+ return PTR_ERR(priv->sana_clk);
+ }
+ }
+
+ priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
+ if (IS_ERR(priv->adc_clk)) {
+ if (PTR_ERR(priv->adc_clk) == -ENOENT) {
+ priv->adc_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get adc clk\n");
+ return PTR_ERR(priv->adc_clk);
+ }
+ }
+
+ priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
+ if (IS_ERR(priv->adc_sel_clk)) {
+ if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
+ priv->adc_sel_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get adc_sel clk\n");
+ return PTR_ERR(priv->adc_sel_clk);
+ }
+ }
+
+ /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
+ if (!priv->adc_clk) {
+ ret = meson_sar_adc_clk_init(indio_dev, base);
+ if (ret)
+ return ret;
+ }
+
+ priv->vref = devm_regulator_get(&pdev->dev, "vref");
+ if (IS_ERR(priv->vref)) {
+ dev_err(&pdev->dev, "failed to get vref regulator\n");
+ return PTR_ERR(priv->vref);
+ }
+
+ ret = meson_sar_adc_init(indio_dev);
+ if (ret)
+ goto err;
+
+ ret = meson_sar_adc_hw_enable(indio_dev);
+ if (ret)
+ goto err;
+
+ platform_set_drvdata(pdev, indio_dev);
+
+ ret = iio_device_register(indio_dev);
+ if (ret)
+ goto err_hw;
+
+ return 0;
+
+err_hw:
+ meson_sar_adc_hw_disable(indio_dev);
+err:
+ return ret;
+}
+
+static int meson_sar_adc_remove(struct platform_device *pdev)
+{
+ struct iio_dev *indio_dev = platform_get_drvdata(pdev);
+
+ iio_device_unregister(indio_dev);
+
+ return meson_sar_adc_hw_disable(indio_dev);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int meson_sar_adc_suspend(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+
+ return meson_sar_adc_hw_disable(indio_dev);
+}
+
+static int meson_sar_adc_resume(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+
+ return meson_sar_adc_hw_enable(indio_dev);
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops,
+ meson_sar_adc_suspend, meson_sar_adc_resume);
+
+static struct platform_driver meson_sar_adc_driver = {
+ .probe = meson_sar_adc_probe,
+ .remove = meson_sar_adc_remove,
+ .driver = {
+ .name = "meson-saradc",
+ .of_match_table = meson_sar_adc_of_match,
+ .pm = &meson_sar_adc_pm_ops,
+ },
+};
+
+module_platform_driver(meson_sar_adc_driver);
+
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
+MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
+MODULE_LICENSE("GPL v2");
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v3 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
@ 2017-01-19 14:58 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-19 14:58 UTC (permalink / raw)
To: linux-arm-kernel
This adds support for the SAR (Successive Approximation Register) ADC
on the Amlogic Meson SoCs.
The code is based on the public S805 (Meson8b) and S905 (GXBB)
datasheets (see [0] and [1]), as well as by reading (various versions
of) the vendor driver and by inspecting the registers on the vendor
kernels of my testing-hardware.
Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
The code was written to support older SoCs (Meson8 and Meson8b) as well,
but due to lack of actual testing-hardware no of_device_id was added for
these.
Two "features" from the vendor driver are currently missing:
- the vendor driver uses channel #7 for calibration (this improves the
accuracy of the results - in my tests the results were less than 3%
off without calibration compared to the vendor driver). Adding support
for this should be easy, but is not required for most applications.
- channel #6 is connected to the SoCs internal temperature sensor.
Adding support for this is probably not so easy since (based on the
u-boot sources) most SoC versions are using different registers and
algorithms for the conversion from "ADC value" to temperature.
Supported by the hardware but currently not supported by the driver:
- reading multiple channels at the same time (the hardware has a FIFO
buffer which stores multiple results)
- continuous sampling (this would require a way to enable this
individually because otherwise the ADC would be drawing power
constantly)
- interrupt support (similar to the vendor driver this new driver is
polling the results. It is unclear if the IRQ-mode is supported on
older (Meson6 or Meson8) hardware as well or if there are any errata)
[0]
http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
[1] http://dn.odroid.com/S905/DataSheet/S905_Public_Datasheet_V1.1.4.pdf
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/iio/adc/Kconfig | 12 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/meson_saradc.c | 916 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 929 insertions(+)
create mode 100644 drivers/iio/adc/meson_saradc.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 9c8b558ba19e..86059b9b91bf 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -371,6 +371,18 @@ config MEN_Z188_ADC
This driver can also be built as a module. If so, the module will be
called men_z188_adc.
+config MESON_SARADC
+ tristate "Amlogic Meson SAR ADC driver"
+ default ARCH_MESON
+ depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
+ select REGMAP_MMIO
+ help
+ Say yes here to build support for the SAR ADC found in Amlogic Meson
+ SoCs.
+
+ To compile this driver as a module, choose M here: the
+ module will be called meson_saradc.
+
config MXS_LRADC
tristate "Freescale i.MX23/i.MX28 LRADC"
depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index d36c4be8d1fc..de05b9e75f8f 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
obj-$(CONFIG_MCP3422) += mcp3422.o
obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
+obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
obj-$(CONFIG_NAU7802) += nau7802.o
obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
new file mode 100644
index 000000000000..11a9686d2a9c
--- /dev/null
+++ b/drivers/iio/adc/meson_saradc.c
@@ -0,0 +1,916 @@
+/*
+ * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
+ *
+ * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/iio/iio.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+
+#define MESON_SAR_ADC_REG0 0x00
+ #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31)
+ #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
+ #define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30)
+ #define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29)
+ #define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
+ #define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27)
+ #define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26)
+ #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
+ #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
+ #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
+ #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
+ #define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14)
+ #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
+ #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
+ #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
+ #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
+ #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
+ #define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2)
+ #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
+ #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
+
+#define MESON_SAR_ADC_CHAN_LIST 0x04
+ #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
+ #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \
+ (GENMASK(2, 0) << ((_chan) * 3))
+
+#define MESON_SAR_ADC_AVG_CNTL 0x08
+ #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
+ (16 + ((_chan) * 2))
+ #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
+ (GENMASK(17, 16) << ((_chan) * 2))
+ #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
+ (0 + ((_chan) * 2))
+ #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
+ (GENMASK(1, 0) << ((_chan) * 2))
+
+#define MESON_SAR_ADC_REG3 0x0c
+ #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
+ #define MESON_SAR_ADC_REG3_CLK_EN BIT(30)
+ #define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
+ #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
+ #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
+ #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
+ #define MESON_SAR_ADC_REG3_DETECT_EN BIT(22)
+ #define MESON_SAR_ADC_REG3_ADC_EN BIT(21)
+ #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
+ #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
+ #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
+ #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
+ #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
+ #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
+
+#define MESON_SAR_ADC_DELAY 0x10
+ #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
+ #define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15)
+ #define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
+ #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
+ #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
+ #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
+
+#define MESON_SAR_ADC_LAST_RD 0x14
+ #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
+ #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
+
+#define MESON_SAR_ADC_FIFO_RD 0x18
+ #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
+ #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
+
+#define MESON_SAR_ADC_AUX_SW 0x1c
+ #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
+ (GENMASK(10, 8) << (((_chan) - 2) * 2))
+ #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
+ #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
+ #define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4)
+ #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
+ #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
+ #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
+ #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
+
+#define MESON_SAR_ADC_CHAN_10_SW 0x20
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
+
+#define MESON_SAR_ADC_DETECT_IDLE_SW 0x24
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0)
+
+#define MESON_SAR_ADC_DELTA_10 0x28
+ #define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
+ #define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
+ #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
+ #define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
+ #define MESON_SAR_ADC_DELTA_10_TS_C_SHIFT 11
+ #define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
+ #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
+ #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
+
+/*
+ * NOTE: registers from here are undocumented (the vendor Linux kernel driver
+ * and u-boot source served as reference). These only seem to be relevant on
+ * GXBB and newer.
+ */
+#define MESON_SAR_ADC_REG11 0x2c
+ #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13)
+
+#define MESON_SAR_ADC_REG13 0x34
+ #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
+
+#define MESON_SAR_ADC_MAX_FIFO_SIZE 32
+
+#define MESON_SAR_ADC_CHAN(_chan) { \
+ .type = IIO_VOLTAGE, \
+ .indexed = 1, \
+ .channel = _chan, \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
+ BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
+ .datasheet_name = "SAR_ADC_CH"#_chan, \
+}
+
+/*
+ * TODO: the hardware supports IIO_TEMP for channel 6 as well which is
+ * currently not supported by this driver.
+ */
+static const struct iio_chan_spec meson_sar_adc_iio_channels[] = {
+ MESON_SAR_ADC_CHAN(0),
+ MESON_SAR_ADC_CHAN(1),
+ MESON_SAR_ADC_CHAN(2),
+ MESON_SAR_ADC_CHAN(3),
+ MESON_SAR_ADC_CHAN(4),
+ MESON_SAR_ADC_CHAN(5),
+ MESON_SAR_ADC_CHAN(6),
+ MESON_SAR_ADC_CHAN(7),
+ IIO_CHAN_SOFT_TIMESTAMP(8),
+};
+
+enum meson_sar_adc_avg_mode {
+ NO_AVERAGING = 0x0,
+ MEAN_AVERAGING = 0x1,
+ MEDIAN_AVERAGING = 0x2,
+};
+
+enum meson_sar_adc_num_samples {
+ ONE_SAMPLE = 0x0,
+ TWO_SAMPLES = 0x1,
+ FOUR_SAMPLES = 0x2,
+ EIGHT_SAMPLES = 0x3,
+};
+
+enum meson_sar_adc_chan7_mux_sel {
+ CHAN7_MUX_VSS = 0x0,
+ CHAN7_MUX_VDD_DIV4 = 0x1,
+ CHAN7_MUX_VDD_DIV2 = 0x2,
+ CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
+ CHAN7_MUX_VDD = 0x4,
+ CHAN7_MUX_CH7_INPUT = 0x7,
+};
+
+struct meson_sar_adc_data {
+ unsigned int resolution;
+ const char *name;
+};
+
+struct meson_sar_adc_priv {
+ struct regmap *regmap;
+ struct regulator *vref;
+ const struct meson_sar_adc_data *data;
+ struct clk *clkin;
+ struct clk *core_clk;
+ struct clk *sana_clk;
+ struct clk *adc_sel_clk;
+ struct clk *adc_clk;
+ struct clk_gate clk_gate;
+ struct clk *adc_div_clk;
+ struct clk_divider clk_div;
+};
+
+static const struct regmap_config meson_sar_adc_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = MESON_SAR_ADC_REG13,
+};
+
+static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);
+
+ return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
+}
+
+static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ int regval, timeout = 10000;
+
+ /*
+ * NOTE: we need a small delay before reading the status, otherwise
+ * the sample engine may not have started internally (which would
+ * seem to us that sampling is already finished).
+ */
+ do {
+ udelay(1);
+ regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);
+ } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
+
+ if (timeout < 0)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ int *val)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0;
+
+ ret = meson_sar_adc_wait_busy_clear(indio_dev);
+ if (ret)
+ return ret;
+
+ while (meson_sar_adc_get_fifo_count(indio_dev) > 0 &&
+ count < MESON_SAR_ADC_MAX_FIFO_SIZE) {
+ regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val);
+
+ fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK,
+ regval);
+ if (fifo_chan != chan->channel)
+ continue;
+
+ fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK,
+ regval);
+ fifo_val &= (BIT(priv->data->resolution) - 1);
+
+ sum += fifo_val;
+ count++;
+ }
+
+ if (!count)
+ return -ENOENT;
+
+ *val = sum / count;
+
+ return 0;
+}
+
+static void meson_sar_adc_set_averaging(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ enum meson_sar_adc_avg_mode mode,
+ enum meson_sar_adc_num_samples samples)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ int val, channel = chan->channel;
+
+ val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(channel);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
+ MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(channel),
+ val);
+
+ val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(channel);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
+ MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(channel), val);
+}
+
+static void meson_sar_adc_enable_channel(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ /*
+ * the SAR ADC engine allows sampling multiple channels at the same
+ * time. to keep it simple we're only working with one *internal*
+ * channel, which starts counting at index 0 (which means: count = 1).
+ */
+ regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
+ MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
+
+ /* map channel index 0 to the channel which we want to read */
+ regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0),
+ chan->channel);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
+ MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval);
+
+ regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
+ chan->channel);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
+ MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
+ regval);
+
+ regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
+ chan->channel);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
+ MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
+ regval);
+
+ if (chan->channel == 6)
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
+ MESON_SAR_ADC_DELTA_10_TEMP_SEL, 0);
+}
+
+static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev,
+ enum meson_sar_adc_chan7_mux_sel sel)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
+ MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
+
+ usleep_range(10, 20);
+}
+
+static void meson_sar_adc_start_sample_engine(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
+ MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
+ MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
+
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
+ MESON_SAR_ADC_REG0_SAMPLING_START,
+ MESON_SAR_ADC_REG0_SAMPLING_START);
+}
+
+static void meson_sar_adc_stop_sample_engine(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
+ MESON_SAR_ADC_REG0_SAMPLING_STOP,
+ MESON_SAR_ADC_REG0_SAMPLING_STOP);
+
+ /* wait until all modules are stopped */
+ meson_sar_adc_wait_busy_clear(indio_dev);
+
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
+ MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
+}
+
+static int meson_sar_adc_lock(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ int val, timeout = 10000;
+
+ mutex_lock(&indio_dev->mlock);
+
+ /* prevent BL30 from using the SAR ADC while we are using it */
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
+ MESON_SAR_ADC_DELAY_KERNEL_BUSY,
+ MESON_SAR_ADC_DELAY_KERNEL_BUSY);
+
+ /* wait until BL30 releases it's lock (so we can use the SAR ADC) */
+ do {
+ udelay(1);
+ regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val);
+ } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--);
+
+ if (timeout < 0)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static void meson_sar_adc_unlock(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+
+ /* allow BL30 to use the SAR ADC again */
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
+ MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0);
+
+ mutex_unlock(&indio_dev->mlock);
+}
+
+static void meson_sar_adc_clear_fifo(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ int count;
+
+ for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {
+ if (!meson_sar_adc_get_fifo_count(indio_dev))
+ break;
+
+ regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, 0);
+ }
+}
+
+static int meson_sar_adc_get_sample(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ enum meson_sar_adc_avg_mode avg_mode,
+ enum meson_sar_adc_num_samples avg_samples,
+ int *val)
+{
+ int ret;
+
+ ret = meson_sar_adc_lock(indio_dev);
+ if (ret)
+ return ret;
+
+ /* clear the FIFO to make sure we're not reading old values */
+ meson_sar_adc_clear_fifo(indio_dev);
+
+ meson_sar_adc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
+
+ meson_sar_adc_enable_channel(indio_dev, chan);
+
+ meson_sar_adc_start_sample_engine(indio_dev);
+ ret = meson_sar_adc_read_raw_sample(indio_dev, chan, val);
+ meson_sar_adc_stop_sample_engine(indio_dev);
+
+ meson_sar_adc_unlock(indio_dev);
+
+ if (ret) {
+ dev_warn(indio_dev->dev.parent,
+ "failed to read sample for channel %d: %d\n",
+ chan->channel, ret);
+ return ret;
+ }
+
+ return IIO_VAL_INT;
+}
+
+static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ int *val, int *val2, long mask)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ int ret;
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ return meson_sar_adc_get_sample(indio_dev, chan, NO_AVERAGING,
+ ONE_SAMPLE, val);
+ break;
+
+ case IIO_CHAN_INFO_AVERAGE_RAW:
+ return meson_sar_adc_get_sample(indio_dev, chan,
+ MEAN_AVERAGING, EIGHT_SAMPLES,
+ val);
+ break;
+
+ case IIO_CHAN_INFO_SCALE:
+ ret = regulator_get_voltage(priv->vref);
+ if (ret < 0) {
+ dev_err(indio_dev->dev.parent,
+ "failed to get vref voltage: %d\n", ret);
+ return ret;
+ }
+
+ *val = ret / 1000;
+ *val2 = priv->data->resolution;
+ return IIO_VAL_FRACTIONAL_LOG2;
+
+ default:
+ return -EINVAL;
+ }
+}
+
+static int meson_sar_adc_clk_init(struct iio_dev *indio_dev,
+ void __iomem *base)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ struct clk_init_data init;
+ const char *clk_parents[1];
+
+ init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_div",
+ of_node_full_name(indio_dev->dev.of_node));
+ init.flags = 0;
+ init.ops = &clk_divider_ops;
+ clk_parents[0] = __clk_get_name(priv->clkin);
+ init.parent_names = clk_parents;
+ init.num_parents = 1;
+
+ priv->clk_div.reg = base + MESON_SAR_ADC_REG3;
+ priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
+ priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
+ priv->clk_div.hw.init = &init;
+ priv->clk_div.flags = 0;
+
+ priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
+ &priv->clk_div.hw);
+ if (WARN_ON(IS_ERR(priv->adc_div_clk)))
+ return PTR_ERR(priv->adc_div_clk);
+
+ init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_en",
+ of_node_full_name(indio_dev->dev.of_node));
+ init.flags = CLK_SET_RATE_PARENT;
+ init.ops = &clk_gate_ops;
+ clk_parents[0] = __clk_get_name(priv->adc_div_clk);
+ init.parent_names = clk_parents;
+ init.num_parents = 1;
+
+ priv->clk_gate.reg = base + MESON_SAR_ADC_REG3;
+ priv->clk_gate.bit_idx = fls(MESON_SAR_ADC_REG3_CLK_EN);
+ priv->clk_gate.hw.init = &init;
+
+ priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
+ if (WARN_ON(IS_ERR(priv->adc_clk)))
+ return PTR_ERR(priv->adc_clk);
+
+ return 0;
+}
+
+static int meson_sar_adc_init(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ int regval, ret;
+
+ /*
+ * make sure we start at CH7 input since the other muxes are only used
+ * for internal calibration.
+ */
+ meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
+
+ /*
+ * leave sampling delay and the input clocks as configured by BL30 to
+ * make sure BL30 gets the values it expects when reading the
+ * temperature sensor.
+ */
+ regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val);
+ if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED)
+ return 0;
+
+ meson_sar_adc_stop_sample_engine(indio_dev);
+
+ /* update the channel 6 MUX to select the temperature sensor */
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
+ MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
+ MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
+
+ /* disable all channels by default */
+ regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);
+
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
+ MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
+ MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY,
+ MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY);
+
+ /* delay between two samples = (10+1) * 1uS */
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
+ MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+ FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,
+ 10));
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
+ MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
+ FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
+ 0));
+
+ /* delay between two samples = (10+1) * 1uS */
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
+ MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+ FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+ 10));
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
+ MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
+ FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
+ 1));
+
+ ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
+ if (ret) {
+ dev_err(indio_dev->dev.parent,
+ "failed to set adc parent to clkin\n");
+ return ret;
+ }
+
+ ret = clk_set_rate(priv->adc_clk, 1200000);
+ if (ret) {
+ dev_err(indio_dev->dev.parent,
+ "failed to set adc clock rate\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ int ret;
+
+ ret = meson_sar_adc_lock(indio_dev);
+ if (ret)
+ goto err_lock;
+
+ ret = regulator_enable(priv->vref);
+ if (ret < 0) {
+ dev_err(indio_dev->dev.parent,
+ "failed to enable vref regulator\n");
+ goto err_vref;
+ }
+
+ ret = clk_prepare_enable(priv->core_clk);
+ if (ret) {
+ dev_err(indio_dev->dev.parent, "failed to enable core clk\n");
+ goto err_core_clk;
+ }
+
+ ret = clk_prepare_enable(priv->sana_clk);
+ if (ret) {
+ dev_err(indio_dev->dev.parent, "failed to enable sana clk\n");
+ goto err_sana_clk;
+ }
+
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
+ MESON_SAR_ADC_REG11_BANDGAP_EN,
+ MESON_SAR_ADC_REG11_BANDGAP_EN);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
+ MESON_SAR_ADC_REG3_ADC_EN,
+ MESON_SAR_ADC_REG3_ADC_EN);
+
+ udelay(5);
+
+ ret = clk_prepare_enable(priv->adc_clk);
+ if (ret) {
+ dev_err(indio_dev->dev.parent, "failed to enable adc clk\n");
+ goto err_adc_clk;
+ }
+
+ meson_sar_adc_unlock(indio_dev);
+
+ return 0;
+
+err_adc_clk:
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
+ MESON_SAR_ADC_REG3_ADC_EN, 0);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
+ MESON_SAR_ADC_REG11_BANDGAP_EN, 0);
+ clk_disable_unprepare(priv->sana_clk);
+err_sana_clk:
+ clk_disable_unprepare(priv->core_clk);
+err_core_clk:
+ regulator_disable(priv->vref);
+err_vref:
+ meson_sar_adc_unlock(indio_dev);
+err_lock:
+ return ret;
+}
+
+static int meson_sar_adc_hw_disable(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ int ret;
+
+ ret = meson_sar_adc_lock(indio_dev);
+ if (ret)
+ return ret;
+
+ clk_disable_unprepare(priv->adc_clk);
+
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
+ MESON_SAR_ADC_REG3_ADC_EN, 0);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
+ MESON_SAR_ADC_REG11_BANDGAP_EN, 0);
+
+ clk_disable_unprepare(priv->sana_clk);
+ clk_disable_unprepare(priv->core_clk);
+
+ regulator_disable(priv->vref);
+
+ meson_sar_adc_unlock(indio_dev);
+
+ return 0;
+}
+
+static const struct iio_info meson_sar_adc_iio_info = {
+ .read_raw = meson_sar_adc_iio_info_read_raw,
+ .driver_module = THIS_MODULE,
+};
+
+struct meson_sar_adc_data meson_sar_adc_gxbb_data = {
+ .resolution = 10,
+ .name = "meson-gxbb-saradc",
+};
+
+struct meson_sar_adc_data meson_sar_adc_gxl_data = {
+ .resolution = 12,
+ .name = "meson-gxl-saradc",
+};
+
+static const struct of_device_id meson_sar_adc_of_match[] = {
+ {
+ .compatible = "amlogic,meson-gxbb-saradc",
+ .data = &meson_sar_adc_gxbb_data,
+ }, {
+ .compatible = "amlogic,meson-gxl-saradc",
+ .data = &meson_sar_adc_gxl_data,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, meson_sar_adc_of_match);
+
+static int meson_sar_adc_probe(struct platform_device *pdev)
+{
+ struct meson_sar_adc_priv *priv;
+ struct iio_dev *indio_dev;
+ struct resource *res;
+ void __iomem *base;
+ const struct of_device_id *match;
+ int ret;
+
+ indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
+ if (!indio_dev) {
+ dev_err(&pdev->dev, "failed allocating iio device\n");
+ return -ENOMEM;
+ }
+
+ priv = iio_priv(indio_dev);
+
+ match = of_match_device(meson_sar_adc_of_match, &pdev->dev);
+ priv->data = match->data;
+
+ indio_dev->name = priv->data->name;
+ indio_dev->dev.parent = &pdev->dev;
+ indio_dev->dev.of_node = pdev->dev.of_node;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->info = &meson_sar_adc_iio_info;
+
+ indio_dev->channels = meson_sar_adc_iio_channels;
+ indio_dev->num_channels = ARRAY_SIZE(meson_sar_adc_iio_channels);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
+ &meson_sar_adc_regmap_config);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+ priv->clkin = devm_clk_get(&pdev->dev, "clkin");
+ if (IS_ERR(priv->clkin)) {
+ dev_err(&pdev->dev, "failed to get clkin\n");
+ return PTR_ERR(priv->clkin);
+ }
+
+ priv->core_clk = devm_clk_get(&pdev->dev, "core");
+ if (IS_ERR(priv->core_clk)) {
+ dev_err(&pdev->dev, "failed to get core clk\n");
+ return PTR_ERR(priv->core_clk);
+ }
+
+ priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
+ if (IS_ERR(priv->sana_clk)) {
+ if (PTR_ERR(priv->sana_clk) == -ENOENT) {
+ priv->sana_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get sana clk\n");
+ return PTR_ERR(priv->sana_clk);
+ }
+ }
+
+ priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
+ if (IS_ERR(priv->adc_clk)) {
+ if (PTR_ERR(priv->adc_clk) == -ENOENT) {
+ priv->adc_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get adc clk\n");
+ return PTR_ERR(priv->adc_clk);
+ }
+ }
+
+ priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
+ if (IS_ERR(priv->adc_sel_clk)) {
+ if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
+ priv->adc_sel_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get adc_sel clk\n");
+ return PTR_ERR(priv->adc_sel_clk);
+ }
+ }
+
+ /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
+ if (!priv->adc_clk) {
+ ret = meson_sar_adc_clk_init(indio_dev, base);
+ if (ret)
+ return ret;
+ }
+
+ priv->vref = devm_regulator_get(&pdev->dev, "vref");
+ if (IS_ERR(priv->vref)) {
+ dev_err(&pdev->dev, "failed to get vref regulator\n");
+ return PTR_ERR(priv->vref);
+ }
+
+ ret = meson_sar_adc_init(indio_dev);
+ if (ret)
+ goto err;
+
+ ret = meson_sar_adc_hw_enable(indio_dev);
+ if (ret)
+ goto err;
+
+ platform_set_drvdata(pdev, indio_dev);
+
+ ret = iio_device_register(indio_dev);
+ if (ret)
+ goto err_hw;
+
+ return 0;
+
+err_hw:
+ meson_sar_adc_hw_disable(indio_dev);
+err:
+ return ret;
+}
+
+static int meson_sar_adc_remove(struct platform_device *pdev)
+{
+ struct iio_dev *indio_dev = platform_get_drvdata(pdev);
+
+ iio_device_unregister(indio_dev);
+
+ return meson_sar_adc_hw_disable(indio_dev);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int meson_sar_adc_suspend(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+
+ return meson_sar_adc_hw_disable(indio_dev);
+}
+
+static int meson_sar_adc_resume(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+
+ return meson_sar_adc_hw_enable(indio_dev);
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops,
+ meson_sar_adc_suspend, meson_sar_adc_resume);
+
+static struct platform_driver meson_sar_adc_driver = {
+ .probe = meson_sar_adc_probe,
+ .remove = meson_sar_adc_remove,
+ .driver = {
+ .name = "meson-saradc",
+ .of_match_table = meson_sar_adc_of_match,
+ .pm = &meson_sar_adc_pm_ops,
+ },
+};
+
+module_platform_driver(meson_sar_adc_driver);
+
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
+MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
+MODULE_LICENSE("GPL v2");
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v3 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
@ 2017-01-19 14:58 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-19 14:58 UTC (permalink / raw)
To: linus-amlogic
This adds support for the SAR (Successive Approximation Register) ADC
on the Amlogic Meson SoCs.
The code is based on the public S805 (Meson8b) and S905 (GXBB)
datasheets (see [0] and [1]), as well as by reading (various versions
of) the vendor driver and by inspecting the registers on the vendor
kernels of my testing-hardware.
Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
The code was written to support older SoCs (Meson8 and Meson8b) as well,
but due to lack of actual testing-hardware no of_device_id was added for
these.
Two "features" from the vendor driver are currently missing:
- the vendor driver uses channel #7 for calibration (this improves the
accuracy of the results - in my tests the results were less than 3%
off without calibration compared to the vendor driver). Adding support
for this should be easy, but is not required for most applications.
- channel #6 is connected to the SoCs internal temperature sensor.
Adding support for this is probably not so easy since (based on the
u-boot sources) most SoC versions are using different registers and
algorithms for the conversion from "ADC value" to temperature.
Supported by the hardware but currently not supported by the driver:
- reading multiple channels at the same time (the hardware has a FIFO
buffer which stores multiple results)
- continuous sampling (this would require a way to enable this
individually because otherwise the ADC would be drawing power
constantly)
- interrupt support (similar to the vendor driver this new driver is
polling the results. It is unclear if the IRQ-mode is supported on
older (Meson6 or Meson8) hardware as well or if there are any errata)
[0]
http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
[1] http://dn.odroid.com/S905/DataSheet/S905_Public_Datasheet_V1.1.4.pdf
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/iio/adc/Kconfig | 12 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/meson_saradc.c | 916 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 929 insertions(+)
create mode 100644 drivers/iio/adc/meson_saradc.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 9c8b558ba19e..86059b9b91bf 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -371,6 +371,18 @@ config MEN_Z188_ADC
This driver can also be built as a module. If so, the module will be
called men_z188_adc.
+config MESON_SARADC
+ tristate "Amlogic Meson SAR ADC driver"
+ default ARCH_MESON
+ depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
+ select REGMAP_MMIO
+ help
+ Say yes here to build support for the SAR ADC found in Amlogic Meson
+ SoCs.
+
+ To compile this driver as a module, choose M here: the
+ module will be called meson_saradc.
+
config MXS_LRADC
tristate "Freescale i.MX23/i.MX28 LRADC"
depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index d36c4be8d1fc..de05b9e75f8f 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
obj-$(CONFIG_MCP3422) += mcp3422.o
obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
+obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
obj-$(CONFIG_NAU7802) += nau7802.o
obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
new file mode 100644
index 000000000000..11a9686d2a9c
--- /dev/null
+++ b/drivers/iio/adc/meson_saradc.c
@@ -0,0 +1,916 @@
+/*
+ * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
+ *
+ * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/iio/iio.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+
+#define MESON_SAR_ADC_REG0 0x00
+ #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31)
+ #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
+ #define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30)
+ #define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29)
+ #define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
+ #define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27)
+ #define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26)
+ #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
+ #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
+ #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
+ #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
+ #define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14)
+ #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
+ #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
+ #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
+ #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
+ #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
+ #define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2)
+ #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
+ #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
+
+#define MESON_SAR_ADC_CHAN_LIST 0x04
+ #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
+ #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \
+ (GENMASK(2, 0) << ((_chan) * 3))
+
+#define MESON_SAR_ADC_AVG_CNTL 0x08
+ #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
+ (16 + ((_chan) * 2))
+ #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
+ (GENMASK(17, 16) << ((_chan) * 2))
+ #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
+ (0 + ((_chan) * 2))
+ #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
+ (GENMASK(1, 0) << ((_chan) * 2))
+
+#define MESON_SAR_ADC_REG3 0x0c
+ #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
+ #define MESON_SAR_ADC_REG3_CLK_EN BIT(30)
+ #define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
+ #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
+ #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
+ #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
+ #define MESON_SAR_ADC_REG3_DETECT_EN BIT(22)
+ #define MESON_SAR_ADC_REG3_ADC_EN BIT(21)
+ #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
+ #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
+ #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
+ #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
+ #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
+ #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
+
+#define MESON_SAR_ADC_DELAY 0x10
+ #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
+ #define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15)
+ #define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
+ #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
+ #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
+ #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
+
+#define MESON_SAR_ADC_LAST_RD 0x14
+ #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
+ #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
+
+#define MESON_SAR_ADC_FIFO_RD 0x18
+ #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
+ #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
+
+#define MESON_SAR_ADC_AUX_SW 0x1c
+ #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
+ (GENMASK(10, 8) << (((_chan) - 2) * 2))
+ #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
+ #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
+ #define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4)
+ #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
+ #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
+ #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
+ #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
+
+#define MESON_SAR_ADC_CHAN_10_SW 0x20
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
+ #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
+
+#define MESON_SAR_ADC_DETECT_IDLE_SW 0x24
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1)
+ #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0)
+
+#define MESON_SAR_ADC_DELTA_10 0x28
+ #define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
+ #define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
+ #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
+ #define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
+ #define MESON_SAR_ADC_DELTA_10_TS_C_SHIFT 11
+ #define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
+ #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
+ #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
+
+/*
+ * NOTE: registers from here are undocumented (the vendor Linux kernel driver
+ * and u-boot source served as reference). These only seem to be relevant on
+ * GXBB and newer.
+ */
+#define MESON_SAR_ADC_REG11 0x2c
+ #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13)
+
+#define MESON_SAR_ADC_REG13 0x34
+ #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
+
+#define MESON_SAR_ADC_MAX_FIFO_SIZE 32
+
+#define MESON_SAR_ADC_CHAN(_chan) { \
+ .type = IIO_VOLTAGE, \
+ .indexed = 1, \
+ .channel = _chan, \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
+ BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
+ .datasheet_name = "SAR_ADC_CH"#_chan, \
+}
+
+/*
+ * TODO: the hardware supports IIO_TEMP for channel 6 as well which is
+ * currently not supported by this driver.
+ */
+static const struct iio_chan_spec meson_sar_adc_iio_channels[] = {
+ MESON_SAR_ADC_CHAN(0),
+ MESON_SAR_ADC_CHAN(1),
+ MESON_SAR_ADC_CHAN(2),
+ MESON_SAR_ADC_CHAN(3),
+ MESON_SAR_ADC_CHAN(4),
+ MESON_SAR_ADC_CHAN(5),
+ MESON_SAR_ADC_CHAN(6),
+ MESON_SAR_ADC_CHAN(7),
+ IIO_CHAN_SOFT_TIMESTAMP(8),
+};
+
+enum meson_sar_adc_avg_mode {
+ NO_AVERAGING = 0x0,
+ MEAN_AVERAGING = 0x1,
+ MEDIAN_AVERAGING = 0x2,
+};
+
+enum meson_sar_adc_num_samples {
+ ONE_SAMPLE = 0x0,
+ TWO_SAMPLES = 0x1,
+ FOUR_SAMPLES = 0x2,
+ EIGHT_SAMPLES = 0x3,
+};
+
+enum meson_sar_adc_chan7_mux_sel {
+ CHAN7_MUX_VSS = 0x0,
+ CHAN7_MUX_VDD_DIV4 = 0x1,
+ CHAN7_MUX_VDD_DIV2 = 0x2,
+ CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
+ CHAN7_MUX_VDD = 0x4,
+ CHAN7_MUX_CH7_INPUT = 0x7,
+};
+
+struct meson_sar_adc_data {
+ unsigned int resolution;
+ const char *name;
+};
+
+struct meson_sar_adc_priv {
+ struct regmap *regmap;
+ struct regulator *vref;
+ const struct meson_sar_adc_data *data;
+ struct clk *clkin;
+ struct clk *core_clk;
+ struct clk *sana_clk;
+ struct clk *adc_sel_clk;
+ struct clk *adc_clk;
+ struct clk_gate clk_gate;
+ struct clk *adc_div_clk;
+ struct clk_divider clk_div;
+};
+
+static const struct regmap_config meson_sar_adc_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = MESON_SAR_ADC_REG13,
+};
+
+static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);
+
+ return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
+}
+
+static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ int regval, timeout = 10000;
+
+ /*
+ * NOTE: we need a small delay before reading the status, otherwise
+ * the sample engine may not have started internally (which would
+ * seem to us that sampling is already finished).
+ */
+ do {
+ udelay(1);
+ regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);
+ } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
+
+ if (timeout < 0)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ int *val)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0;
+
+ ret = meson_sar_adc_wait_busy_clear(indio_dev);
+ if (ret)
+ return ret;
+
+ while (meson_sar_adc_get_fifo_count(indio_dev) > 0 &&
+ count < MESON_SAR_ADC_MAX_FIFO_SIZE) {
+ regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val);
+
+ fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK,
+ regval);
+ if (fifo_chan != chan->channel)
+ continue;
+
+ fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK,
+ regval);
+ fifo_val &= (BIT(priv->data->resolution) - 1);
+
+ sum += fifo_val;
+ count++;
+ }
+
+ if (!count)
+ return -ENOENT;
+
+ *val = sum / count;
+
+ return 0;
+}
+
+static void meson_sar_adc_set_averaging(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ enum meson_sar_adc_avg_mode mode,
+ enum meson_sar_adc_num_samples samples)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ int val, channel = chan->channel;
+
+ val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(channel);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
+ MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(channel),
+ val);
+
+ val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(channel);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
+ MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(channel), val);
+}
+
+static void meson_sar_adc_enable_channel(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ /*
+ * the SAR ADC engine allows sampling multiple channels at the same
+ * time. to keep it simple we're only working with one *internal*
+ * channel, which starts counting at index 0 (which means: count = 1).
+ */
+ regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
+ MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
+
+ /* map channel index 0 to the channel which we want to read */
+ regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0),
+ chan->channel);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
+ MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval);
+
+ regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
+ chan->channel);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
+ MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
+ regval);
+
+ regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
+ chan->channel);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
+ MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
+ regval);
+
+ if (chan->channel == 6)
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
+ MESON_SAR_ADC_DELTA_10_TEMP_SEL, 0);
+}
+
+static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev,
+ enum meson_sar_adc_chan7_mux_sel sel)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ u32 regval;
+
+ regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
+ MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
+
+ usleep_range(10, 20);
+}
+
+static void meson_sar_adc_start_sample_engine(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
+ MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
+ MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
+
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
+ MESON_SAR_ADC_REG0_SAMPLING_START,
+ MESON_SAR_ADC_REG0_SAMPLING_START);
+}
+
+static void meson_sar_adc_stop_sample_engine(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
+ MESON_SAR_ADC_REG0_SAMPLING_STOP,
+ MESON_SAR_ADC_REG0_SAMPLING_STOP);
+
+ /* wait until all modules are stopped */
+ meson_sar_adc_wait_busy_clear(indio_dev);
+
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
+ MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
+}
+
+static int meson_sar_adc_lock(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ int val, timeout = 10000;
+
+ mutex_lock(&indio_dev->mlock);
+
+ /* prevent BL30 from using the SAR ADC while we are using it */
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
+ MESON_SAR_ADC_DELAY_KERNEL_BUSY,
+ MESON_SAR_ADC_DELAY_KERNEL_BUSY);
+
+ /* wait until BL30 releases it's lock (so we can use the SAR ADC) */
+ do {
+ udelay(1);
+ regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val);
+ } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--);
+
+ if (timeout < 0)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static void meson_sar_adc_unlock(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+
+ /* allow BL30 to use the SAR ADC again */
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
+ MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0);
+
+ mutex_unlock(&indio_dev->mlock);
+}
+
+static void meson_sar_adc_clear_fifo(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ int count;
+
+ for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {
+ if (!meson_sar_adc_get_fifo_count(indio_dev))
+ break;
+
+ regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, 0);
+ }
+}
+
+static int meson_sar_adc_get_sample(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ enum meson_sar_adc_avg_mode avg_mode,
+ enum meson_sar_adc_num_samples avg_samples,
+ int *val)
+{
+ int ret;
+
+ ret = meson_sar_adc_lock(indio_dev);
+ if (ret)
+ return ret;
+
+ /* clear the FIFO to make sure we're not reading old values */
+ meson_sar_adc_clear_fifo(indio_dev);
+
+ meson_sar_adc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
+
+ meson_sar_adc_enable_channel(indio_dev, chan);
+
+ meson_sar_adc_start_sample_engine(indio_dev);
+ ret = meson_sar_adc_read_raw_sample(indio_dev, chan, val);
+ meson_sar_adc_stop_sample_engine(indio_dev);
+
+ meson_sar_adc_unlock(indio_dev);
+
+ if (ret) {
+ dev_warn(indio_dev->dev.parent,
+ "failed to read sample for channel %d: %d\n",
+ chan->channel, ret);
+ return ret;
+ }
+
+ return IIO_VAL_INT;
+}
+
+static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ int *val, int *val2, long mask)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ int ret;
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ return meson_sar_adc_get_sample(indio_dev, chan, NO_AVERAGING,
+ ONE_SAMPLE, val);
+ break;
+
+ case IIO_CHAN_INFO_AVERAGE_RAW:
+ return meson_sar_adc_get_sample(indio_dev, chan,
+ MEAN_AVERAGING, EIGHT_SAMPLES,
+ val);
+ break;
+
+ case IIO_CHAN_INFO_SCALE:
+ ret = regulator_get_voltage(priv->vref);
+ if (ret < 0) {
+ dev_err(indio_dev->dev.parent,
+ "failed to get vref voltage: %d\n", ret);
+ return ret;
+ }
+
+ *val = ret / 1000;
+ *val2 = priv->data->resolution;
+ return IIO_VAL_FRACTIONAL_LOG2;
+
+ default:
+ return -EINVAL;
+ }
+}
+
+static int meson_sar_adc_clk_init(struct iio_dev *indio_dev,
+ void __iomem *base)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ struct clk_init_data init;
+ const char *clk_parents[1];
+
+ init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_div",
+ of_node_full_name(indio_dev->dev.of_node));
+ init.flags = 0;
+ init.ops = &clk_divider_ops;
+ clk_parents[0] = __clk_get_name(priv->clkin);
+ init.parent_names = clk_parents;
+ init.num_parents = 1;
+
+ priv->clk_div.reg = base + MESON_SAR_ADC_REG3;
+ priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
+ priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
+ priv->clk_div.hw.init = &init;
+ priv->clk_div.flags = 0;
+
+ priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
+ &priv->clk_div.hw);
+ if (WARN_ON(IS_ERR(priv->adc_div_clk)))
+ return PTR_ERR(priv->adc_div_clk);
+
+ init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_en",
+ of_node_full_name(indio_dev->dev.of_node));
+ init.flags = CLK_SET_RATE_PARENT;
+ init.ops = &clk_gate_ops;
+ clk_parents[0] = __clk_get_name(priv->adc_div_clk);
+ init.parent_names = clk_parents;
+ init.num_parents = 1;
+
+ priv->clk_gate.reg = base + MESON_SAR_ADC_REG3;
+ priv->clk_gate.bit_idx = fls(MESON_SAR_ADC_REG3_CLK_EN);
+ priv->clk_gate.hw.init = &init;
+
+ priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
+ if (WARN_ON(IS_ERR(priv->adc_clk)))
+ return PTR_ERR(priv->adc_clk);
+
+ return 0;
+}
+
+static int meson_sar_adc_init(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ int regval, ret;
+
+ /*
+ * make sure we start at CH7 input since the other muxes are only used
+ * for internal calibration.
+ */
+ meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
+
+ /*
+ * leave sampling delay and the input clocks as configured by BL30 to
+ * make sure BL30 gets the values it expects when reading the
+ * temperature sensor.
+ */
+ regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val);
+ if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED)
+ return 0;
+
+ meson_sar_adc_stop_sample_engine(indio_dev);
+
+ /* update the channel 6 MUX to select the temperature sensor */
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
+ MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
+ MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
+
+ /* disable all channels by default */
+ regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);
+
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
+ MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
+ MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY,
+ MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY);
+
+ /* delay between two samples = (10+1) * 1uS */
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
+ MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+ FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,
+ 10));
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
+ MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
+ FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
+ 0));
+
+ /* delay between two samples = (10+1) * 1uS */
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
+ MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+ FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+ 10));
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
+ MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
+ FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
+ 1));
+
+ ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
+ if (ret) {
+ dev_err(indio_dev->dev.parent,
+ "failed to set adc parent to clkin\n");
+ return ret;
+ }
+
+ ret = clk_set_rate(priv->adc_clk, 1200000);
+ if (ret) {
+ dev_err(indio_dev->dev.parent,
+ "failed to set adc clock rate\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ int ret;
+
+ ret = meson_sar_adc_lock(indio_dev);
+ if (ret)
+ goto err_lock;
+
+ ret = regulator_enable(priv->vref);
+ if (ret < 0) {
+ dev_err(indio_dev->dev.parent,
+ "failed to enable vref regulator\n");
+ goto err_vref;
+ }
+
+ ret = clk_prepare_enable(priv->core_clk);
+ if (ret) {
+ dev_err(indio_dev->dev.parent, "failed to enable core clk\n");
+ goto err_core_clk;
+ }
+
+ ret = clk_prepare_enable(priv->sana_clk);
+ if (ret) {
+ dev_err(indio_dev->dev.parent, "failed to enable sana clk\n");
+ goto err_sana_clk;
+ }
+
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
+ MESON_SAR_ADC_REG11_BANDGAP_EN,
+ MESON_SAR_ADC_REG11_BANDGAP_EN);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
+ MESON_SAR_ADC_REG3_ADC_EN,
+ MESON_SAR_ADC_REG3_ADC_EN);
+
+ udelay(5);
+
+ ret = clk_prepare_enable(priv->adc_clk);
+ if (ret) {
+ dev_err(indio_dev->dev.parent, "failed to enable adc clk\n");
+ goto err_adc_clk;
+ }
+
+ meson_sar_adc_unlock(indio_dev);
+
+ return 0;
+
+err_adc_clk:
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
+ MESON_SAR_ADC_REG3_ADC_EN, 0);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
+ MESON_SAR_ADC_REG11_BANDGAP_EN, 0);
+ clk_disable_unprepare(priv->sana_clk);
+err_sana_clk:
+ clk_disable_unprepare(priv->core_clk);
+err_core_clk:
+ regulator_disable(priv->vref);
+err_vref:
+ meson_sar_adc_unlock(indio_dev);
+err_lock:
+ return ret;
+}
+
+static int meson_sar_adc_hw_disable(struct iio_dev *indio_dev)
+{
+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
+ int ret;
+
+ ret = meson_sar_adc_lock(indio_dev);
+ if (ret)
+ return ret;
+
+ clk_disable_unprepare(priv->adc_clk);
+
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
+ MESON_SAR_ADC_REG3_ADC_EN, 0);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
+ MESON_SAR_ADC_REG11_BANDGAP_EN, 0);
+
+ clk_disable_unprepare(priv->sana_clk);
+ clk_disable_unprepare(priv->core_clk);
+
+ regulator_disable(priv->vref);
+
+ meson_sar_adc_unlock(indio_dev);
+
+ return 0;
+}
+
+static const struct iio_info meson_sar_adc_iio_info = {
+ .read_raw = meson_sar_adc_iio_info_read_raw,
+ .driver_module = THIS_MODULE,
+};
+
+struct meson_sar_adc_data meson_sar_adc_gxbb_data = {
+ .resolution = 10,
+ .name = "meson-gxbb-saradc",
+};
+
+struct meson_sar_adc_data meson_sar_adc_gxl_data = {
+ .resolution = 12,
+ .name = "meson-gxl-saradc",
+};
+
+static const struct of_device_id meson_sar_adc_of_match[] = {
+ {
+ .compatible = "amlogic,meson-gxbb-saradc",
+ .data = &meson_sar_adc_gxbb_data,
+ }, {
+ .compatible = "amlogic,meson-gxl-saradc",
+ .data = &meson_sar_adc_gxl_data,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, meson_sar_adc_of_match);
+
+static int meson_sar_adc_probe(struct platform_device *pdev)
+{
+ struct meson_sar_adc_priv *priv;
+ struct iio_dev *indio_dev;
+ struct resource *res;
+ void __iomem *base;
+ const struct of_device_id *match;
+ int ret;
+
+ indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
+ if (!indio_dev) {
+ dev_err(&pdev->dev, "failed allocating iio device\n");
+ return -ENOMEM;
+ }
+
+ priv = iio_priv(indio_dev);
+
+ match = of_match_device(meson_sar_adc_of_match, &pdev->dev);
+ priv->data = match->data;
+
+ indio_dev->name = priv->data->name;
+ indio_dev->dev.parent = &pdev->dev;
+ indio_dev->dev.of_node = pdev->dev.of_node;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->info = &meson_sar_adc_iio_info;
+
+ indio_dev->channels = meson_sar_adc_iio_channels;
+ indio_dev->num_channels = ARRAY_SIZE(meson_sar_adc_iio_channels);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
+ &meson_sar_adc_regmap_config);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+ priv->clkin = devm_clk_get(&pdev->dev, "clkin");
+ if (IS_ERR(priv->clkin)) {
+ dev_err(&pdev->dev, "failed to get clkin\n");
+ return PTR_ERR(priv->clkin);
+ }
+
+ priv->core_clk = devm_clk_get(&pdev->dev, "core");
+ if (IS_ERR(priv->core_clk)) {
+ dev_err(&pdev->dev, "failed to get core clk\n");
+ return PTR_ERR(priv->core_clk);
+ }
+
+ priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
+ if (IS_ERR(priv->sana_clk)) {
+ if (PTR_ERR(priv->sana_clk) == -ENOENT) {
+ priv->sana_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get sana clk\n");
+ return PTR_ERR(priv->sana_clk);
+ }
+ }
+
+ priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
+ if (IS_ERR(priv->adc_clk)) {
+ if (PTR_ERR(priv->adc_clk) == -ENOENT) {
+ priv->adc_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get adc clk\n");
+ return PTR_ERR(priv->adc_clk);
+ }
+ }
+
+ priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
+ if (IS_ERR(priv->adc_sel_clk)) {
+ if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
+ priv->adc_sel_clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "failed to get adc_sel clk\n");
+ return PTR_ERR(priv->adc_sel_clk);
+ }
+ }
+
+ /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
+ if (!priv->adc_clk) {
+ ret = meson_sar_adc_clk_init(indio_dev, base);
+ if (ret)
+ return ret;
+ }
+
+ priv->vref = devm_regulator_get(&pdev->dev, "vref");
+ if (IS_ERR(priv->vref)) {
+ dev_err(&pdev->dev, "failed to get vref regulator\n");
+ return PTR_ERR(priv->vref);
+ }
+
+ ret = meson_sar_adc_init(indio_dev);
+ if (ret)
+ goto err;
+
+ ret = meson_sar_adc_hw_enable(indio_dev);
+ if (ret)
+ goto err;
+
+ platform_set_drvdata(pdev, indio_dev);
+
+ ret = iio_device_register(indio_dev);
+ if (ret)
+ goto err_hw;
+
+ return 0;
+
+err_hw:
+ meson_sar_adc_hw_disable(indio_dev);
+err:
+ return ret;
+}
+
+static int meson_sar_adc_remove(struct platform_device *pdev)
+{
+ struct iio_dev *indio_dev = platform_get_drvdata(pdev);
+
+ iio_device_unregister(indio_dev);
+
+ return meson_sar_adc_hw_disable(indio_dev);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int meson_sar_adc_suspend(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+
+ return meson_sar_adc_hw_disable(indio_dev);
+}
+
+static int meson_sar_adc_resume(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+
+ return meson_sar_adc_hw_enable(indio_dev);
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops,
+ meson_sar_adc_suspend, meson_sar_adc_resume);
+
+static struct platform_driver meson_sar_adc_driver = {
+ .probe = meson_sar_adc_probe,
+ .remove = meson_sar_adc_remove,
+ .driver = {
+ .name = "meson-saradc",
+ .of_match_table = meson_sar_adc_of_match,
+ .pm = &meson_sar_adc_pm_ops,
+ },
+};
+
+module_platform_driver(meson_sar_adc_driver);
+
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
+MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
+MODULE_LICENSE("GPL v2");
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v3 4/4] ARM64: dts: meson: meson-gx: add the SAR ADC
2017-01-19 14:58 ` Martin Blumenstingl
(?)
@ 2017-01-19 14:58 ` Martin Blumenstingl
-1 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-19 14:58 UTC (permalink / raw)
To: jic23, knaack.h, lars, pmeerw, robh+dt, mark.rutland, khilman,
linux-iio, devicetree, linux-amlogic, linux-clk
Cc: carlo, catalin.marinas, will.deacon, mturquette, sboyd,
narmstrong, linux-arm-kernel, Martin Blumenstingl
Add the SAR ADC to meson-gxbb.dtsi and meson-gxl.dtsi. GXBB provides a
10-bit ADC while GXL (and GXM, which uses the same ADC as GXL) provides
a 12-bit ADC.
Some boards use resistor ladder buttons connected through one of the ADC
channels. On newer devices (GXL and GXM) some boards use pull-ups/downs
to change the resistance (and thus the ADC value) on of the ADC channels
to indicate the board revision.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 ++++++++
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 ++++++++++
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 ++++++++++
3 files changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 99e6a8d5cb9e..55abfb74aab2 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -255,6 +255,14 @@
status = "disabled";
};
+ saradc: adc@8680 {
+ compatible = "amlogic,meson-saradc";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ reg = <0x0 0x8680 0x0 0x34>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
+ };
+
pwm_ef: pwm@86c0 {
compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
reg = <0x0 0x086c0 0x0 0x10>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 39a774ad83ce..04b3324bc132 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -490,6 +490,16 @@
clocks = <&clkc CLKID_I2C>;
};
+&saradc {
+ compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+};
+
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index bdf2305a2e25..7c72dbcef1ba 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -340,6 +340,16 @@
clocks = <&clkc CLKID_I2C>;
};
+&saradc {
+ compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+};
+
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v3 4/4] ARM64: dts: meson: meson-gx: add the SAR ADC
@ 2017-01-19 14:58 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-19 14:58 UTC (permalink / raw)
To: linux-arm-kernel
Add the SAR ADC to meson-gxbb.dtsi and meson-gxl.dtsi. GXBB provides a
10-bit ADC while GXL (and GXM, which uses the same ADC as GXL) provides
a 12-bit ADC.
Some boards use resistor ladder buttons connected through one of the ADC
channels. On newer devices (GXL and GXM) some boards use pull-ups/downs
to change the resistance (and thus the ADC value) on of the ADC channels
to indicate the board revision.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 ++++++++
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 ++++++++++
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 ++++++++++
3 files changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 99e6a8d5cb9e..55abfb74aab2 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -255,6 +255,14 @@
status = "disabled";
};
+ saradc: adc at 8680 {
+ compatible = "amlogic,meson-saradc";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ reg = <0x0 0x8680 0x0 0x34>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
+ };
+
pwm_ef: pwm at 86c0 {
compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
reg = <0x0 0x086c0 0x0 0x10>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 39a774ad83ce..04b3324bc132 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -490,6 +490,16 @@
clocks = <&clkc CLKID_I2C>;
};
+&saradc {
+ compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+};
+
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index bdf2305a2e25..7c72dbcef1ba 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -340,6 +340,16 @@
clocks = <&clkc CLKID_I2C>;
};
+&saradc {
+ compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+};
+
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v3 4/4] ARM64: dts: meson: meson-gx: add the SAR ADC
@ 2017-01-19 14:58 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-19 14:58 UTC (permalink / raw)
To: linus-amlogic
Add the SAR ADC to meson-gxbb.dtsi and meson-gxl.dtsi. GXBB provides a
10-bit ADC while GXL (and GXM, which uses the same ADC as GXL) provides
a 12-bit ADC.
Some boards use resistor ladder buttons connected through one of the ADC
channels. On newer devices (GXL and GXM) some boards use pull-ups/downs
to change the resistance (and thus the ADC value) on of the ADC channels
to indicate the board revision.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 ++++++++
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 ++++++++++
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 ++++++++++
3 files changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 99e6a8d5cb9e..55abfb74aab2 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -255,6 +255,14 @@
status = "disabled";
};
+ saradc: adc at 8680 {
+ compatible = "amlogic,meson-saradc";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ reg = <0x0 0x8680 0x0 0x34>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
+ };
+
pwm_ef: pwm at 86c0 {
compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
reg = <0x0 0x086c0 0x0 0x10>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 39a774ad83ce..04b3324bc132 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -490,6 +490,16 @@
clocks = <&clkc CLKID_I2C>;
};
+&saradc {
+ compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+};
+
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index bdf2305a2e25..7c72dbcef1ba 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -340,6 +340,16 @@
clocks = <&clkc CLKID_I2C>;
};
+&saradc {
+ compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+};
+
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
--
2.11.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* Re: [PATCH v3 2/4] clk: gxbb: add the SAR ADC clocks and expose them
2017-01-19 14:58 ` Martin Blumenstingl
(?)
(?)
@ 2017-01-19 19:13 ` Stephen Boyd
-1 siblings, 0 replies; 110+ messages in thread
From: Stephen Boyd @ 2017-01-19 19:13 UTC (permalink / raw)
To: Martin Blumenstingl
Cc: jic23-DgEjT+Ai2ygdnm+yROfE0A, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
khilman-rdvid1DuHRBWk0Htik3J/w, linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-clk-u79uwXL29TY76Z2rM5mHXA, carlo-KA+7E9HrN00dnm+yROfE0A,
catalin.marinas-5wv7dgnIgG8, will.deacon-5wv7dgnIgG8,
mturquette-rdvid1DuHRBWk0Htik3J/w,
narmstrong-rdvid1DuHRBWk0Htik3J/w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 01/19, Martin Blumenstingl wrote:
> The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
> - a mux clock to choose between different ADC reference clocks (this is
> 2-bit wide, but the datasheet only lists the parents for the first
> bit)
> - a divider for the input/reference clock
> - a gate which enables the ADC clock
>
> Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
> CLKID_SANA (which seems to enable the analog inputs, but unfortunately
> there is no documentation for this - we just mimic what the vendor
> driver does).
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> Tested-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> ---
Acked-by: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
This should go through arm-soc along with the other patch to dts.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
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^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v3 2/4] clk: gxbb: add the SAR ADC clocks and expose them
@ 2017-01-19 19:13 ` Stephen Boyd
0 siblings, 0 replies; 110+ messages in thread
From: Stephen Boyd @ 2017-01-19 19:13 UTC (permalink / raw)
To: Martin Blumenstingl
Cc: jic23, knaack.h, lars, pmeerw, robh+dt, mark.rutland, khilman,
linux-iio, devicetree, linux-amlogic, linux-clk, carlo,
catalin.marinas, will.deacon, mturquette, narmstrong,
linux-arm-kernel
On 01/19, Martin Blumenstingl wrote:
> The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
> - a mux clock to choose between different ADC reference clocks (this is
> 2-bit wide, but the datasheet only lists the parents for the first
> bit)
> - a divider for the input/reference clock
> - a gate which enables the ADC clock
>
> Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
> CLKID_SANA (which seems to enable the analog inputs, but unfortunately
> there is no documentation for this - we just mimic what the vendor
> driver does).
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
This should go through arm-soc along with the other patch to dts.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v3 2/4] clk: gxbb: add the SAR ADC clocks and expose them
@ 2017-01-19 19:13 ` Stephen Boyd
0 siblings, 0 replies; 110+ messages in thread
From: Stephen Boyd @ 2017-01-19 19:13 UTC (permalink / raw)
To: linux-arm-kernel
On 01/19, Martin Blumenstingl wrote:
> The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
> - a mux clock to choose between different ADC reference clocks (this is
> 2-bit wide, but the datasheet only lists the parents for the first
> bit)
> - a divider for the input/reference clock
> - a gate which enables the ADC clock
>
> Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
> CLKID_SANA (which seems to enable the analog inputs, but unfortunately
> there is no documentation for this - we just mimic what the vendor
> driver does).
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
This should go through arm-soc along with the other patch to dts.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v3 2/4] clk: gxbb: add the SAR ADC clocks and expose them
@ 2017-01-19 19:13 ` Stephen Boyd
0 siblings, 0 replies; 110+ messages in thread
From: Stephen Boyd @ 2017-01-19 19:13 UTC (permalink / raw)
To: linus-amlogic
On 01/19, Martin Blumenstingl wrote:
> The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
> - a mux clock to choose between different ADC reference clocks (this is
> 2-bit wide, but the datasheet only lists the parents for the first
> bit)
> - a divider for the input/reference clock
> - a gate which enables the ADC clock
>
> Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
> CLKID_SANA (which seems to enable the analog inputs, but unfortunately
> there is no documentation for this - we just mimic what the vendor
> driver does).
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
This should go through arm-soc along with the other patch to dts.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v3 2/4] clk: gxbb: add the SAR ADC clocks and expose them
2017-01-19 19:13 ` Stephen Boyd
(?)
(?)
@ 2017-01-20 15:46 ` Kevin Hilman
-1 siblings, 0 replies; 110+ messages in thread
From: Kevin Hilman @ 2017-01-20 15:46 UTC (permalink / raw)
To: Stephen Boyd
Cc: Martin Blumenstingl, jic23, knaack.h, lars, pmeerw, robh+dt,
mark.rutland, linux-iio, devicetree, linux-amlogic, linux-clk,
carlo, catalin.marinas, will.deacon, mturquette, narmstrong,
linux-arm-kernel
Stephen Boyd <sboyd@codeaurora.org> writes:
> On 01/19, Martin Blumenstingl wrote:
>> The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
>> - a mux clock to choose between different ADC reference clocks (this is
>> 2-bit wide, but the datasheet only lists the parents for the first
>> bit)
>> - a divider for the input/reference clock
>> - a gate which enables the ADC clock
>>
>> Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
>> CLKID_SANA (which seems to enable the analog inputs, but unfortunately
>> there is no documentation for this - we just mimic what the vendor
>> driver does).
>>
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
>> ---
>
> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
>
> This should go through arm-soc along with the other patch to dts.
Applied to v4.11/dt64 of the amlogic tree.
Kevin
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v3 2/4] clk: gxbb: add the SAR ADC clocks and expose them
@ 2017-01-20 15:46 ` Kevin Hilman
0 siblings, 0 replies; 110+ messages in thread
From: Kevin Hilman @ 2017-01-20 15:46 UTC (permalink / raw)
To: Stephen Boyd
Cc: Martin Blumenstingl, jic23, knaack.h, lars, pmeerw, robh+dt,
mark.rutland, linux-iio, devicetree, linux-amlogic, linux-clk,
carlo, catalin.marinas, will.deacon, mturquette, narmstrong,
linux-arm-kernel
Stephen Boyd <sboyd@codeaurora.org> writes:
> On 01/19, Martin Blumenstingl wrote:
>> The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
>> - a mux clock to choose between different ADC reference clocks (this is
>> 2-bit wide, but the datasheet only lists the parents for the first
>> bit)
>> - a divider for the input/reference clock
>> - a gate which enables the ADC clock
>>
>> Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
>> CLKID_SANA (which seems to enable the analog inputs, but unfortunately
>> there is no documentation for this - we just mimic what the vendor
>> driver does).
>>
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
>> ---
>
> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
>
> This should go through arm-soc along with the other patch to dts.
Applied to v4.11/dt64 of the amlogic tree.
Kevin
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v3 2/4] clk: gxbb: add the SAR ADC clocks and expose them
@ 2017-01-20 15:46 ` Kevin Hilman
0 siblings, 0 replies; 110+ messages in thread
From: Kevin Hilman @ 2017-01-20 15:46 UTC (permalink / raw)
To: linux-arm-kernel
Stephen Boyd <sboyd@codeaurora.org> writes:
> On 01/19, Martin Blumenstingl wrote:
>> The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
>> - a mux clock to choose between different ADC reference clocks (this is
>> 2-bit wide, but the datasheet only lists the parents for the first
>> bit)
>> - a divider for the input/reference clock
>> - a gate which enables the ADC clock
>>
>> Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
>> CLKID_SANA (which seems to enable the analog inputs, but unfortunately
>> there is no documentation for this - we just mimic what the vendor
>> driver does).
>>
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
>> ---
>
> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
>
> This should go through arm-soc along with the other patch to dts.
Applied to v4.11/dt64 of the amlogic tree.
Kevin
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v3 2/4] clk: gxbb: add the SAR ADC clocks and expose them
@ 2017-01-20 15:46 ` Kevin Hilman
0 siblings, 0 replies; 110+ messages in thread
From: Kevin Hilman @ 2017-01-20 15:46 UTC (permalink / raw)
To: linus-amlogic
Stephen Boyd <sboyd@codeaurora.org> writes:
> On 01/19, Martin Blumenstingl wrote:
>> The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
>> - a mux clock to choose between different ADC reference clocks (this is
>> 2-bit wide, but the datasheet only lists the parents for the first
>> bit)
>> - a divider for the input/reference clock
>> - a gate which enables the ADC clock
>>
>> Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
>> CLKID_SANA (which seems to enable the analog inputs, but unfortunately
>> there is no documentation for this - we just mimic what the vendor
>> driver does).
>>
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
>> ---
>
> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
>
> This should go through arm-soc along with the other patch to dts.
Applied to v4.11/dt64 of the amlogic tree.
Kevin
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v3 0/4] Amlogic Meson SAR ADC support
2017-01-19 14:58 ` Martin Blumenstingl
(?)
(?)
@ 2017-01-21 12:37 ` Jonathan Cameron
-1 siblings, 0 replies; 110+ messages in thread
From: Jonathan Cameron @ 2017-01-21 12:37 UTC (permalink / raw)
To: Martin Blumenstingl, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
khilman-rdvid1DuHRBWk0Htik3J/w, linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-clk-u79uwXL29TY76Z2rM5mHXA
Cc: carlo-KA+7E9HrN00dnm+yROfE0A, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, mturquette-rdvid1DuHRBWk0Htik3J/w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, narmstrong-rdvid1DuHRBWk0Htik3J/w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Hi Martin,
Quick process point. Personally I'd much prefer it if new versions
fo the patch are not posted as replies to earlier versions. It gets
awfully deep and hard to follow very quickly!
Thanks,
Jonathan
On 19/01/17 14:58, Martin Blumenstingl wrote:
> This series add support for the SAR ADC on Amlogic Meson GXBB, GXL and
> GXM SoCs.
> The hardware on GXBB provides 10-bit ADC results, while GXL and GXM are
> providing 12-bit results. Support for older SoCs (Meson8b and Meson8)
> can be added with little effort, most of which is testing I guess (I
> don't have any pre-GXBB hardware so I can't say).
>
> A new set of clocks had to be added to the GXBB clock controller (used
> by the GXBB/GXL/GXM SoCs) which are required to get the ADC working.
>
> The ADC itself can sample multiple channels at the same time and allows
> capturing multiple samples (which can be used for filtering/averaging).
> The ADC results are stored inside a FIFO register. More details on what
> the driver supports (or doesn't) can be found in the description of
> patch #3.
>
> The code is based on the public S805 (Meson8b) and S905 (GXBB)
> datasheets, as well as by reading (various versions of) the vendor
> driver and by inspecting the registers on the vendor kernels of my
> testing-hardware.
>
> Typical use-cases for the ADC on the Meson GX SoCs are:
> - adc-keys ("ADC attached resistor ladder buttons")
> - SoC temperature measurement (not supported by this driver yet as
> the system firmware does this already and provides the values via the
> SCPI protocol)
> - "version-strapping" (different resistor values are used to indicate
> the board-revision)
> - and of course typical ADC measurements
>
> Thanks to Heiner Kallweit, Jonathan Cameron, Lars-Peter Clausen and
> Peter Meerwald-Stadler for reviewing this series and providing valuable
> input!
>
> Changes since v2 (all changes are for patch #3, except where noted):
> - fixed another typo in the interrupt (patch #4, thanks again Heiner
> Kallweit)
> - change namespace of all register #defines to MESON_SAR_ADC (I
> intentionally decided to keep SAR_ADC in it because that's the way
> registers are named in the datasheet, thus making it easy to match the
> registers without having to look up the offset all the time)
> - added additional parenthesis around MACRO parameters for extra safety
> - removed unused definition for SAR_ADC_REG3_ADC_CLK_DIV_MASK (as we
> already have SAR_ADC_REG3_ADC_CLK_DIV_SHIFT and
> SAR_ADC_REG3_ADC_CLK_DIV_WIDTH which are used instead)
> - change value of "indexed" from "true" to "1"
> - remove type parameter from MESON_SAR_ADC_CHAN macro as all channels are
> currently IIO_VOLTAGE channels
> - fixed another multi-line comment style violation
> - added timeout to meson_saradc_lock() (unlikely to be triggered, but
> better safe then sorry - which would mean that we'd be keeping one core
> busy infinitely)
> - fixed meson_saradc_remove() call order (first unregister the iio_dev,
> then disable the hardware instead of the other way around)
> - use "consistent prefixing", which means that all #defines now use
> MESON_SAR_ADC_ as prefix, while all enums, static global variables,
> structs and functions use meson_sar_adc_ as prefix
> - rebased .dts and clk patches to apply to khilman's latest v4.11/dt64
> (a minor conflict had to be resolved in the clk patch due to
> "clk: meson-gxbb: Export HDMI clocks")
> - added Tested-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> to all
> patches (thanks for testing!)
>
> Changes since v1 (all changes are for patch #3, except where noted):
> - fix IRQ number in meson-gx.dtsi (thanks to Heiner Kallweit for
> providing the correct value), affects patch #4
> - move the most used members of meson_saradc_priv to the beginning
> - remove unused struct member "completion" from meson_saradc_priv
> - use devm_kasprintf() instead of snprintf() + devm_kstrdup()
> - initialize indio_dev->dev.parent earlier in meson_saradc_probe()
> - moved meson_saradc_clear_fifo() logic to a separate function
> - add comment why a do ... while loop is required in
> meson_saradc_wait_busy_clear()
> - remove SAR_ADC_NUM_CHANNELS and SAR_ADC_VALUE_MASK macros (each of them
> was only used once and it's an unneeded level of abstraction)
> - fixed multiline comment syntax violations
> - dropped unneeded log messages during initialization
> - set iio_dev name to "meson-gxbb-saradc" or "meson-gxl-saradc"
> - use "indio_dev->dev.parent" in all kernel log calls (dev_warn/err/etc)
> to make it show the OF node name (instead of the iio device name)
> - introduce struct meson_saradc_data to hold platform-specific
> information (such as resolution in bits and the iio_dev name)
>
>
> Martin Blumenstingl (4):
> Documentation: dt-bindings: add the Amlogic Meson SAR ADC
> documentation
> clk: gxbb: add the SAR ADC clocks and expose them
> iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
> ARM64: dts: meson: meson-gx: add the SAR ADC
>
> .../bindings/iio/adc/amlogic,meson-saradc.txt | 31 +
> arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 +
> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 +
> arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 +
> drivers/clk/meson/gxbb.c | 48 ++
> drivers/clk/meson/gxbb.h | 9 +-
> drivers/iio/adc/Kconfig | 12 +
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/meson_saradc.c | 916 +++++++++++++++++++++
> include/dt-bindings/clock/gxbb-clkc.h | 4 +
> 10 files changed, 1046 insertions(+), 3 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
> create mode 100644 drivers/iio/adc/meson_saradc.c
>
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^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v3 0/4] Amlogic Meson SAR ADC support
@ 2017-01-21 12:37 ` Jonathan Cameron
0 siblings, 0 replies; 110+ messages in thread
From: Jonathan Cameron @ 2017-01-21 12:37 UTC (permalink / raw)
To: Martin Blumenstingl, knaack.h, lars, pmeerw, robh+dt,
mark.rutland, khilman, linux-iio, devicetree, linux-amlogic,
linux-clk
Cc: carlo, catalin.marinas, will.deacon, mturquette, sboyd,
narmstrong, linux-arm-kernel
Hi Martin,
Quick process point. Personally I'd much prefer it if new versions
fo the patch are not posted as replies to earlier versions. It gets
awfully deep and hard to follow very quickly!
Thanks,
Jonathan
On 19/01/17 14:58, Martin Blumenstingl wrote:
> This series add support for the SAR ADC on Amlogic Meson GXBB, GXL and
> GXM SoCs.
> The hardware on GXBB provides 10-bit ADC results, while GXL and GXM are
> providing 12-bit results. Support for older SoCs (Meson8b and Meson8)
> can be added with little effort, most of which is testing I guess (I
> don't have any pre-GXBB hardware so I can't say).
>
> A new set of clocks had to be added to the GXBB clock controller (used
> by the GXBB/GXL/GXM SoCs) which are required to get the ADC working.
>
> The ADC itself can sample multiple channels at the same time and allows
> capturing multiple samples (which can be used for filtering/averaging).
> The ADC results are stored inside a FIFO register. More details on what
> the driver supports (or doesn't) can be found in the description of
> patch #3.
>
> The code is based on the public S805 (Meson8b) and S905 (GXBB)
> datasheets, as well as by reading (various versions of) the vendor
> driver and by inspecting the registers on the vendor kernels of my
> testing-hardware.
>
> Typical use-cases for the ADC on the Meson GX SoCs are:
> - adc-keys ("ADC attached resistor ladder buttons")
> - SoC temperature measurement (not supported by this driver yet as
> the system firmware does this already and provides the values via the
> SCPI protocol)
> - "version-strapping" (different resistor values are used to indicate
> the board-revision)
> - and of course typical ADC measurements
>
> Thanks to Heiner Kallweit, Jonathan Cameron, Lars-Peter Clausen and
> Peter Meerwald-Stadler for reviewing this series and providing valuable
> input!
>
> Changes since v2 (all changes are for patch #3, except where noted):
> - fixed another typo in the interrupt (patch #4, thanks again Heiner
> Kallweit)
> - change namespace of all register #defines to MESON_SAR_ADC (I
> intentionally decided to keep SAR_ADC in it because that's the way
> registers are named in the datasheet, thus making it easy to match the
> registers without having to look up the offset all the time)
> - added additional parenthesis around MACRO parameters for extra safety
> - removed unused definition for SAR_ADC_REG3_ADC_CLK_DIV_MASK (as we
> already have SAR_ADC_REG3_ADC_CLK_DIV_SHIFT and
> SAR_ADC_REG3_ADC_CLK_DIV_WIDTH which are used instead)
> - change value of "indexed" from "true" to "1"
> - remove type parameter from MESON_SAR_ADC_CHAN macro as all channels are
> currently IIO_VOLTAGE channels
> - fixed another multi-line comment style violation
> - added timeout to meson_saradc_lock() (unlikely to be triggered, but
> better safe then sorry - which would mean that we'd be keeping one core
> busy infinitely)
> - fixed meson_saradc_remove() call order (first unregister the iio_dev,
> then disable the hardware instead of the other way around)
> - use "consistent prefixing", which means that all #defines now use
> MESON_SAR_ADC_ as prefix, while all enums, static global variables,
> structs and functions use meson_sar_adc_ as prefix
> - rebased .dts and clk patches to apply to khilman's latest v4.11/dt64
> (a minor conflict had to be resolved in the clk patch due to
> "clk: meson-gxbb: Export HDMI clocks")
> - added Tested-by: Neil Armstrong <narmstrong@baylibre.com> to all
> patches (thanks for testing!)
>
> Changes since v1 (all changes are for patch #3, except where noted):
> - fix IRQ number in meson-gx.dtsi (thanks to Heiner Kallweit for
> providing the correct value), affects patch #4
> - move the most used members of meson_saradc_priv to the beginning
> - remove unused struct member "completion" from meson_saradc_priv
> - use devm_kasprintf() instead of snprintf() + devm_kstrdup()
> - initialize indio_dev->dev.parent earlier in meson_saradc_probe()
> - moved meson_saradc_clear_fifo() logic to a separate function
> - add comment why a do ... while loop is required in
> meson_saradc_wait_busy_clear()
> - remove SAR_ADC_NUM_CHANNELS and SAR_ADC_VALUE_MASK macros (each of them
> was only used once and it's an unneeded level of abstraction)
> - fixed multiline comment syntax violations
> - dropped unneeded log messages during initialization
> - set iio_dev name to "meson-gxbb-saradc" or "meson-gxl-saradc"
> - use "indio_dev->dev.parent" in all kernel log calls (dev_warn/err/etc)
> to make it show the OF node name (instead of the iio device name)
> - introduce struct meson_saradc_data to hold platform-specific
> information (such as resolution in bits and the iio_dev name)
>
>
> Martin Blumenstingl (4):
> Documentation: dt-bindings: add the Amlogic Meson SAR ADC
> documentation
> clk: gxbb: add the SAR ADC clocks and expose them
> iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
> ARM64: dts: meson: meson-gx: add the SAR ADC
>
> .../bindings/iio/adc/amlogic,meson-saradc.txt | 31 +
> arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 +
> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 +
> arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 +
> drivers/clk/meson/gxbb.c | 48 ++
> drivers/clk/meson/gxbb.h | 9 +-
> drivers/iio/adc/Kconfig | 12 +
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/meson_saradc.c | 916 +++++++++++++++++++++
> include/dt-bindings/clock/gxbb-clkc.h | 4 +
> 10 files changed, 1046 insertions(+), 3 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
> create mode 100644 drivers/iio/adc/meson_saradc.c
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v3 0/4] Amlogic Meson SAR ADC support
@ 2017-01-21 12:37 ` Jonathan Cameron
0 siblings, 0 replies; 110+ messages in thread
From: Jonathan Cameron @ 2017-01-21 12:37 UTC (permalink / raw)
To: linux-arm-kernel
Hi Martin,
Quick process point. Personally I'd much prefer it if new versions
fo the patch are not posted as replies to earlier versions. It gets
awfully deep and hard to follow very quickly!
Thanks,
Jonathan
On 19/01/17 14:58, Martin Blumenstingl wrote:
> This series add support for the SAR ADC on Amlogic Meson GXBB, GXL and
> GXM SoCs.
> The hardware on GXBB provides 10-bit ADC results, while GXL and GXM are
> providing 12-bit results. Support for older SoCs (Meson8b and Meson8)
> can be added with little effort, most of which is testing I guess (I
> don't have any pre-GXBB hardware so I can't say).
>
> A new set of clocks had to be added to the GXBB clock controller (used
> by the GXBB/GXL/GXM SoCs) which are required to get the ADC working.
>
> The ADC itself can sample multiple channels at the same time and allows
> capturing multiple samples (which can be used for filtering/averaging).
> The ADC results are stored inside a FIFO register. More details on what
> the driver supports (or doesn't) can be found in the description of
> patch #3.
>
> The code is based on the public S805 (Meson8b) and S905 (GXBB)
> datasheets, as well as by reading (various versions of) the vendor
> driver and by inspecting the registers on the vendor kernels of my
> testing-hardware.
>
> Typical use-cases for the ADC on the Meson GX SoCs are:
> - adc-keys ("ADC attached resistor ladder buttons")
> - SoC temperature measurement (not supported by this driver yet as
> the system firmware does this already and provides the values via the
> SCPI protocol)
> - "version-strapping" (different resistor values are used to indicate
> the board-revision)
> - and of course typical ADC measurements
>
> Thanks to Heiner Kallweit, Jonathan Cameron, Lars-Peter Clausen and
> Peter Meerwald-Stadler for reviewing this series and providing valuable
> input!
>
> Changes since v2 (all changes are for patch #3, except where noted):
> - fixed another typo in the interrupt (patch #4, thanks again Heiner
> Kallweit)
> - change namespace of all register #defines to MESON_SAR_ADC (I
> intentionally decided to keep SAR_ADC in it because that's the way
> registers are named in the datasheet, thus making it easy to match the
> registers without having to look up the offset all the time)
> - added additional parenthesis around MACRO parameters for extra safety
> - removed unused definition for SAR_ADC_REG3_ADC_CLK_DIV_MASK (as we
> already have SAR_ADC_REG3_ADC_CLK_DIV_SHIFT and
> SAR_ADC_REG3_ADC_CLK_DIV_WIDTH which are used instead)
> - change value of "indexed" from "true" to "1"
> - remove type parameter from MESON_SAR_ADC_CHAN macro as all channels are
> currently IIO_VOLTAGE channels
> - fixed another multi-line comment style violation
> - added timeout to meson_saradc_lock() (unlikely to be triggered, but
> better safe then sorry - which would mean that we'd be keeping one core
> busy infinitely)
> - fixed meson_saradc_remove() call order (first unregister the iio_dev,
> then disable the hardware instead of the other way around)
> - use "consistent prefixing", which means that all #defines now use
> MESON_SAR_ADC_ as prefix, while all enums, static global variables,
> structs and functions use meson_sar_adc_ as prefix
> - rebased .dts and clk patches to apply to khilman's latest v4.11/dt64
> (a minor conflict had to be resolved in the clk patch due to
> "clk: meson-gxbb: Export HDMI clocks")
> - added Tested-by: Neil Armstrong <narmstrong@baylibre.com> to all
> patches (thanks for testing!)
>
> Changes since v1 (all changes are for patch #3, except where noted):
> - fix IRQ number in meson-gx.dtsi (thanks to Heiner Kallweit for
> providing the correct value), affects patch #4
> - move the most used members of meson_saradc_priv to the beginning
> - remove unused struct member "completion" from meson_saradc_priv
> - use devm_kasprintf() instead of snprintf() + devm_kstrdup()
> - initialize indio_dev->dev.parent earlier in meson_saradc_probe()
> - moved meson_saradc_clear_fifo() logic to a separate function
> - add comment why a do ... while loop is required in
> meson_saradc_wait_busy_clear()
> - remove SAR_ADC_NUM_CHANNELS and SAR_ADC_VALUE_MASK macros (each of them
> was only used once and it's an unneeded level of abstraction)
> - fixed multiline comment syntax violations
> - dropped unneeded log messages during initialization
> - set iio_dev name to "meson-gxbb-saradc" or "meson-gxl-saradc"
> - use "indio_dev->dev.parent" in all kernel log calls (dev_warn/err/etc)
> to make it show the OF node name (instead of the iio device name)
> - introduce struct meson_saradc_data to hold platform-specific
> information (such as resolution in bits and the iio_dev name)
>
>
> Martin Blumenstingl (4):
> Documentation: dt-bindings: add the Amlogic Meson SAR ADC
> documentation
> clk: gxbb: add the SAR ADC clocks and expose them
> iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
> ARM64: dts: meson: meson-gx: add the SAR ADC
>
> .../bindings/iio/adc/amlogic,meson-saradc.txt | 31 +
> arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 +
> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 +
> arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 +
> drivers/clk/meson/gxbb.c | 48 ++
> drivers/clk/meson/gxbb.h | 9 +-
> drivers/iio/adc/Kconfig | 12 +
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/meson_saradc.c | 916 +++++++++++++++++++++
> include/dt-bindings/clock/gxbb-clkc.h | 4 +
> 10 files changed, 1046 insertions(+), 3 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
> create mode 100644 drivers/iio/adc/meson_saradc.c
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v3 0/4] Amlogic Meson SAR ADC support
@ 2017-01-21 12:37 ` Jonathan Cameron
0 siblings, 0 replies; 110+ messages in thread
From: Jonathan Cameron @ 2017-01-21 12:37 UTC (permalink / raw)
To: linus-amlogic
Hi Martin,
Quick process point. Personally I'd much prefer it if new versions
fo the patch are not posted as replies to earlier versions. It gets
awfully deep and hard to follow very quickly!
Thanks,
Jonathan
On 19/01/17 14:58, Martin Blumenstingl wrote:
> This series add support for the SAR ADC on Amlogic Meson GXBB, GXL and
> GXM SoCs.
> The hardware on GXBB provides 10-bit ADC results, while GXL and GXM are
> providing 12-bit results. Support for older SoCs (Meson8b and Meson8)
> can be added with little effort, most of which is testing I guess (I
> don't have any pre-GXBB hardware so I can't say).
>
> A new set of clocks had to be added to the GXBB clock controller (used
> by the GXBB/GXL/GXM SoCs) which are required to get the ADC working.
>
> The ADC itself can sample multiple channels at the same time and allows
> capturing multiple samples (which can be used for filtering/averaging).
> The ADC results are stored inside a FIFO register. More details on what
> the driver supports (or doesn't) can be found in the description of
> patch #3.
>
> The code is based on the public S805 (Meson8b) and S905 (GXBB)
> datasheets, as well as by reading (various versions of) the vendor
> driver and by inspecting the registers on the vendor kernels of my
> testing-hardware.
>
> Typical use-cases for the ADC on the Meson GX SoCs are:
> - adc-keys ("ADC attached resistor ladder buttons")
> - SoC temperature measurement (not supported by this driver yet as
> the system firmware does this already and provides the values via the
> SCPI protocol)
> - "version-strapping" (different resistor values are used to indicate
> the board-revision)
> - and of course typical ADC measurements
>
> Thanks to Heiner Kallweit, Jonathan Cameron, Lars-Peter Clausen and
> Peter Meerwald-Stadler for reviewing this series and providing valuable
> input!
>
> Changes since v2 (all changes are for patch #3, except where noted):
> - fixed another typo in the interrupt (patch #4, thanks again Heiner
> Kallweit)
> - change namespace of all register #defines to MESON_SAR_ADC (I
> intentionally decided to keep SAR_ADC in it because that's the way
> registers are named in the datasheet, thus making it easy to match the
> registers without having to look up the offset all the time)
> - added additional parenthesis around MACRO parameters for extra safety
> - removed unused definition for SAR_ADC_REG3_ADC_CLK_DIV_MASK (as we
> already have SAR_ADC_REG3_ADC_CLK_DIV_SHIFT and
> SAR_ADC_REG3_ADC_CLK_DIV_WIDTH which are used instead)
> - change value of "indexed" from "true" to "1"
> - remove type parameter from MESON_SAR_ADC_CHAN macro as all channels are
> currently IIO_VOLTAGE channels
> - fixed another multi-line comment style violation
> - added timeout to meson_saradc_lock() (unlikely to be triggered, but
> better safe then sorry - which would mean that we'd be keeping one core
> busy infinitely)
> - fixed meson_saradc_remove() call order (first unregister the iio_dev,
> then disable the hardware instead of the other way around)
> - use "consistent prefixing", which means that all #defines now use
> MESON_SAR_ADC_ as prefix, while all enums, static global variables,
> structs and functions use meson_sar_adc_ as prefix
> - rebased .dts and clk patches to apply to khilman's latest v4.11/dt64
> (a minor conflict had to be resolved in the clk patch due to
> "clk: meson-gxbb: Export HDMI clocks")
> - added Tested-by: Neil Armstrong <narmstrong@baylibre.com> to all
> patches (thanks for testing!)
>
> Changes since v1 (all changes are for patch #3, except where noted):
> - fix IRQ number in meson-gx.dtsi (thanks to Heiner Kallweit for
> providing the correct value), affects patch #4
> - move the most used members of meson_saradc_priv to the beginning
> - remove unused struct member "completion" from meson_saradc_priv
> - use devm_kasprintf() instead of snprintf() + devm_kstrdup()
> - initialize indio_dev->dev.parent earlier in meson_saradc_probe()
> - moved meson_saradc_clear_fifo() logic to a separate function
> - add comment why a do ... while loop is required in
> meson_saradc_wait_busy_clear()
> - remove SAR_ADC_NUM_CHANNELS and SAR_ADC_VALUE_MASK macros (each of them
> was only used once and it's an unneeded level of abstraction)
> - fixed multiline comment syntax violations
> - dropped unneeded log messages during initialization
> - set iio_dev name to "meson-gxbb-saradc" or "meson-gxl-saradc"
> - use "indio_dev->dev.parent" in all kernel log calls (dev_warn/err/etc)
> to make it show the OF node name (instead of the iio device name)
> - introduce struct meson_saradc_data to hold platform-specific
> information (such as resolution in bits and the iio_dev name)
>
>
> Martin Blumenstingl (4):
> Documentation: dt-bindings: add the Amlogic Meson SAR ADC
> documentation
> clk: gxbb: add the SAR ADC clocks and expose them
> iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
> ARM64: dts: meson: meson-gx: add the SAR ADC
>
> .../bindings/iio/adc/amlogic,meson-saradc.txt | 31 +
> arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 +
> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 +
> arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 +
> drivers/clk/meson/gxbb.c | 48 ++
> drivers/clk/meson/gxbb.h | 9 +-
> drivers/iio/adc/Kconfig | 12 +
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/meson_saradc.c | 916 +++++++++++++++++++++
> include/dt-bindings/clock/gxbb-clkc.h | 4 +
> 10 files changed, 1046 insertions(+), 3 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
> create mode 100644 drivers/iio/adc/meson_saradc.c
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v3 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
2017-01-19 14:58 ` Martin Blumenstingl
(?)
(?)
@ 2017-01-21 12:39 ` Jonathan Cameron
-1 siblings, 0 replies; 110+ messages in thread
From: Jonathan Cameron @ 2017-01-21 12:39 UTC (permalink / raw)
To: Martin Blumenstingl, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
khilman-rdvid1DuHRBWk0Htik3J/w, linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-clk-u79uwXL29TY76Z2rM5mHXA
Cc: carlo-KA+7E9HrN00dnm+yROfE0A, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, mturquette-rdvid1DuHRBWk0Htik3J/w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, narmstrong-rdvid1DuHRBWk0Htik3J/w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 19/01/17 14:58, Martin Blumenstingl wrote:
> This adds the devicetree binding documentation for the SAR ADC found in
> Amlogic Meson SoCs.
> Currently only the GXBB, GXL and GXM SoCs are supported.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> Tested-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
Looks straight forward to me, but there is just enough here that I'm looking
for an Ack from Rob or Mark.
Thanks,
Jonathan
> ---
> .../bindings/iio/adc/amlogic,meson-saradc.txt | 31 ++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
> new file mode 100644
> index 000000000000..9a0bec7afc63
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
> @@ -0,0 +1,31 @@
> +* Amlogic Meson SAR (Successive Approximation Register) A/D converter
> +
> +Required properties:
> +- compatible: depending on the SoC this should be one of:
> + - "amlogic,meson-gxbb-saradc" for GXBB
> + - "amlogic,meson-gxl-saradc" for GXL and GXM
> + along with the generic "amlogic,meson-saradc"
> +- reg: the physical base address and length of the registers
> +- clocks: phandle and clock identifier (see clock-names)
> +- clock-names: mandatory clocks:
> + - "clkin" for the reference clock (typically XTAL)
> + - "core" for the SAR ADC core clock
> + optional clocks:
> + - "sana" for the analog clock
> + - "adc_clk" for the ADC (sampling) clock
> + - "adc_sel" for the ADC (sampling) clock mux
> +- vref-supply: the regulator supply for the ADC reference voltage
> +- #io-channel-cells: must be 1, see ../iio-bindings.txt
> +
> +Example:
> + saradc: adc@8680 {
> + compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
> + #io-channel-cells = <1>;
> + reg = <0x0 0x8680 0x0 0x34>;
> + clocks = <&xtal>,
> + <&clkc CLKID_SAR_ADC>,
> + <&clkc CLKID_SANA>,
> + <&clkc CLKID_SAR_ADC_CLK>,
> + <&clkc CLKID_SAR_ADC_SEL>;
> + clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
> + };
>
--
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^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v3 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
@ 2017-01-21 12:39 ` Jonathan Cameron
0 siblings, 0 replies; 110+ messages in thread
From: Jonathan Cameron @ 2017-01-21 12:39 UTC (permalink / raw)
To: Martin Blumenstingl, knaack.h, lars, pmeerw, robh+dt,
mark.rutland, khilman, linux-iio, devicetree, linux-amlogic,
linux-clk
Cc: carlo, catalin.marinas, will.deacon, mturquette, sboyd,
narmstrong, linux-arm-kernel
On 19/01/17 14:58, Martin Blumenstingl wrote:
> This adds the devicetree binding documentation for the SAR ADC found in
> Amlogic Meson SoCs.
> Currently only the GXBB, GXL and GXM SoCs are supported.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Looks straight forward to me, but there is just enough here that I'm looking
for an Ack from Rob or Mark.
Thanks,
Jonathan
> ---
> .../bindings/iio/adc/amlogic,meson-saradc.txt | 31 ++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
> new file mode 100644
> index 000000000000..9a0bec7afc63
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
> @@ -0,0 +1,31 @@
> +* Amlogic Meson SAR (Successive Approximation Register) A/D converter
> +
> +Required properties:
> +- compatible: depending on the SoC this should be one of:
> + - "amlogic,meson-gxbb-saradc" for GXBB
> + - "amlogic,meson-gxl-saradc" for GXL and GXM
> + along with the generic "amlogic,meson-saradc"
> +- reg: the physical base address and length of the registers
> +- clocks: phandle and clock identifier (see clock-names)
> +- clock-names: mandatory clocks:
> + - "clkin" for the reference clock (typically XTAL)
> + - "core" for the SAR ADC core clock
> + optional clocks:
> + - "sana" for the analog clock
> + - "adc_clk" for the ADC (sampling) clock
> + - "adc_sel" for the ADC (sampling) clock mux
> +- vref-supply: the regulator supply for the ADC reference voltage
> +- #io-channel-cells: must be 1, see ../iio-bindings.txt
> +
> +Example:
> + saradc: adc@8680 {
> + compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
> + #io-channel-cells = <1>;
> + reg = <0x0 0x8680 0x0 0x34>;
> + clocks = <&xtal>,
> + <&clkc CLKID_SAR_ADC>,
> + <&clkc CLKID_SANA>,
> + <&clkc CLKID_SAR_ADC_CLK>,
> + <&clkc CLKID_SAR_ADC_SEL>;
> + clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
> + };
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v3 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
@ 2017-01-21 12:39 ` Jonathan Cameron
0 siblings, 0 replies; 110+ messages in thread
From: Jonathan Cameron @ 2017-01-21 12:39 UTC (permalink / raw)
To: linux-arm-kernel
On 19/01/17 14:58, Martin Blumenstingl wrote:
> This adds the devicetree binding documentation for the SAR ADC found in
> Amlogic Meson SoCs.
> Currently only the GXBB, GXL and GXM SoCs are supported.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Looks straight forward to me, but there is just enough here that I'm looking
for an Ack from Rob or Mark.
Thanks,
Jonathan
> ---
> .../bindings/iio/adc/amlogic,meson-saradc.txt | 31 ++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
> new file mode 100644
> index 000000000000..9a0bec7afc63
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
> @@ -0,0 +1,31 @@
> +* Amlogic Meson SAR (Successive Approximation Register) A/D converter
> +
> +Required properties:
> +- compatible: depending on the SoC this should be one of:
> + - "amlogic,meson-gxbb-saradc" for GXBB
> + - "amlogic,meson-gxl-saradc" for GXL and GXM
> + along with the generic "amlogic,meson-saradc"
> +- reg: the physical base address and length of the registers
> +- clocks: phandle and clock identifier (see clock-names)
> +- clock-names: mandatory clocks:
> + - "clkin" for the reference clock (typically XTAL)
> + - "core" for the SAR ADC core clock
> + optional clocks:
> + - "sana" for the analog clock
> + - "adc_clk" for the ADC (sampling) clock
> + - "adc_sel" for the ADC (sampling) clock mux
> +- vref-supply: the regulator supply for the ADC reference voltage
> +- #io-channel-cells: must be 1, see ../iio-bindings.txt
> +
> +Example:
> + saradc: adc at 8680 {
> + compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
> + #io-channel-cells = <1>;
> + reg = <0x0 0x8680 0x0 0x34>;
> + clocks = <&xtal>,
> + <&clkc CLKID_SAR_ADC>,
> + <&clkc CLKID_SANA>,
> + <&clkc CLKID_SAR_ADC_CLK>,
> + <&clkc CLKID_SAR_ADC_SEL>;
> + clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
> + };
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v3 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
@ 2017-01-21 12:39 ` Jonathan Cameron
0 siblings, 0 replies; 110+ messages in thread
From: Jonathan Cameron @ 2017-01-21 12:39 UTC (permalink / raw)
To: linus-amlogic
On 19/01/17 14:58, Martin Blumenstingl wrote:
> This adds the devicetree binding documentation for the SAR ADC found in
> Amlogic Meson SoCs.
> Currently only the GXBB, GXL and GXM SoCs are supported.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Looks straight forward to me, but there is just enough here that I'm looking
for an Ack from Rob or Mark.
Thanks,
Jonathan
> ---
> .../bindings/iio/adc/amlogic,meson-saradc.txt | 31 ++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
> new file mode 100644
> index 000000000000..9a0bec7afc63
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
> @@ -0,0 +1,31 @@
> +* Amlogic Meson SAR (Successive Approximation Register) A/D converter
> +
> +Required properties:
> +- compatible: depending on the SoC this should be one of:
> + - "amlogic,meson-gxbb-saradc" for GXBB
> + - "amlogic,meson-gxl-saradc" for GXL and GXM
> + along with the generic "amlogic,meson-saradc"
> +- reg: the physical base address and length of the registers
> +- clocks: phandle and clock identifier (see clock-names)
> +- clock-names: mandatory clocks:
> + - "clkin" for the reference clock (typically XTAL)
> + - "core" for the SAR ADC core clock
> + optional clocks:
> + - "sana" for the analog clock
> + - "adc_clk" for the ADC (sampling) clock
> + - "adc_sel" for the ADC (sampling) clock mux
> +- vref-supply: the regulator supply for the ADC reference voltage
> +- #io-channel-cells: must be 1, see ../iio-bindings.txt
> +
> +Example:
> + saradc: adc at 8680 {
> + compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
> + #io-channel-cells = <1>;
> + reg = <0x0 0x8680 0x0 0x34>;
> + clocks = <&xtal>,
> + <&clkc CLKID_SAR_ADC>,
> + <&clkc CLKID_SANA>,
> + <&clkc CLKID_SAR_ADC_CLK>,
> + <&clkc CLKID_SAR_ADC_SEL>;
> + clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
> + };
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v3 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
2017-01-19 14:58 ` Martin Blumenstingl
(?)
(?)
@ 2017-01-21 12:52 ` Jonathan Cameron
-1 siblings, 0 replies; 110+ messages in thread
From: Jonathan Cameron @ 2017-01-21 12:52 UTC (permalink / raw)
To: Martin Blumenstingl, knaack.h, lars, pmeerw, robh+dt,
mark.rutland, khilman, linux-iio, devicetree, linux-amlogic,
linux-clk
Cc: narmstrong, catalin.marinas, mturquette, will.deacon, carlo,
sboyd, linux-arm-kernel
On 19/01/17 14:58, Martin Blumenstingl wrote:
> This adds support for the SAR (Successive Approximation Register) ADC
> on the Amlogic Meson SoCs.
>
> The code is based on the public S805 (Meson8b) and S905 (GXBB)
> datasheets (see [0] and [1]), as well as by reading (various versions
> of) the vendor driver and by inspecting the registers on the vendor
> kernels of my testing-hardware.
>
> Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
> 10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
> The code was written to support older SoCs (Meson8 and Meson8b) as well,
> but due to lack of actual testing-hardware no of_device_id was added for
> these.
>
> Two "features" from the vendor driver are currently missing:
> - the vendor driver uses channel #7 for calibration (this improves the
> accuracy of the results - in my tests the results were less than 3%
> off without calibration compared to the vendor driver). Adding support
> for this should be easy, but is not required for most applications.
> - channel #6 is connected to the SoCs internal temperature sensor.
> Adding support for this is probably not so easy since (based on the
> u-boot sources) most SoC versions are using different registers and
> algorithms for the conversion from "ADC value" to temperature.
>
> Supported by the hardware but currently not supported by the driver:
> - reading multiple channels at the same time (the hardware has a FIFO
> buffer which stores multiple results)
> - continuous sampling (this would require a way to enable this
> individually because otherwise the ADC would be drawing power
> constantly)
> - interrupt support (similar to the vendor driver this new driver is
> polling the results. It is unclear if the IRQ-mode is supported on
> older (Meson6 or Meson8) hardware as well or if there are any errata)
>
> [0]
> http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
> [1] http://dn.odroid.com/S905/DataSheet/S905_Public_Datasheet_V1.1.4.pdf
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Very nice. One really minor comment inline, that I'd only bother
dealing with should you be rolling a V4 for some other reason.
I'll take this if Rob / Mark are happy with the device tree bindings.
Give me a bump if we see nothing from them in the next week or so (or if
I miss it!)
thanks
Jonathan
> ---
> drivers/iio/adc/Kconfig | 12 +
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/meson_saradc.c | 916 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 929 insertions(+)
> create mode 100644 drivers/iio/adc/meson_saradc.c
>
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index 9c8b558ba19e..86059b9b91bf 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -371,6 +371,18 @@ config MEN_Z188_ADC
> This driver can also be built as a module. If so, the module will be
> called men_z188_adc.
>
> +config MESON_SARADC
> + tristate "Amlogic Meson SAR ADC driver"
> + default ARCH_MESON
> + depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
> + select REGMAP_MMIO
> + help
> + Say yes here to build support for the SAR ADC found in Amlogic Meson
> + SoCs.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called meson_saradc.
> +
> config MXS_LRADC
> tristate "Freescale i.MX23/i.MX28 LRADC"
> depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
> index d36c4be8d1fc..de05b9e75f8f 100644
> --- a/drivers/iio/adc/Makefile
> +++ b/drivers/iio/adc/Makefile
> @@ -36,6 +36,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
> obj-$(CONFIG_MCP3422) += mcp3422.o
> obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
> obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
> +obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
> obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
> obj-$(CONFIG_NAU7802) += nau7802.o
> obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
> diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
> new file mode 100644
> index 000000000000..11a9686d2a9c
> --- /dev/null
> +++ b/drivers/iio/adc/meson_saradc.c
> @@ -0,0 +1,916 @@
> +/*
> + * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
> + *
> + * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/iio/iio.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/regulator/consumer.h>
> +
> +#define MESON_SAR_ADC_REG0 0x00
> + #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31)
> + #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
> + #define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30)
> + #define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29)
> + #define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
> + #define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27)
> + #define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26)
> + #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
> + #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
> + #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
> + #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
> + #define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14)
> + #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
> + #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
> + #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
> + #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
> + #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
> + #define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2)
> + #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
> + #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
> +
> +#define MESON_SAR_ADC_CHAN_LIST 0x04
> + #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
> + #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \
> + (GENMASK(2, 0) << ((_chan) * 3))
> +
> +#define MESON_SAR_ADC_AVG_CNTL 0x08
> + #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
> + (16 + ((_chan) * 2))
> + #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
> + (GENMASK(17, 16) << ((_chan) * 2))
> + #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
> + (0 + ((_chan) * 2))
> + #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
> + (GENMASK(1, 0) << ((_chan) * 2))
> +
> +#define MESON_SAR_ADC_REG3 0x0c
> + #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
> + #define MESON_SAR_ADC_REG3_CLK_EN BIT(30)
> + #define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
> + #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
> + #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
> + #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
> + #define MESON_SAR_ADC_REG3_DETECT_EN BIT(22)
> + #define MESON_SAR_ADC_REG3_ADC_EN BIT(21)
> + #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
> + #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
> + #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
> + #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
> + #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
> + #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
> +
> +#define MESON_SAR_ADC_DELAY 0x10
> + #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
> + #define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15)
> + #define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
> + #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
> + #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
> + #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
> +
> +#define MESON_SAR_ADC_LAST_RD 0x14
> + #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
> + #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
> +
> +#define MESON_SAR_ADC_FIFO_RD 0x18
> + #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
> + #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
> +
> +#define MESON_SAR_ADC_AUX_SW 0x1c
> + #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
> + (GENMASK(10, 8) << (((_chan) - 2) * 2))
> + #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
> + #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
> + #define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4)
> + #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
> + #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
> + #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
> + #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
> +
> +#define MESON_SAR_ADC_CHAN_10_SW 0x20
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
> +
> +#define MESON_SAR_ADC_DETECT_IDLE_SW 0x24
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0)
> +
> +#define MESON_SAR_ADC_DELTA_10 0x28
> + #define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
> + #define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
> + #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
> + #define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
> + #define MESON_SAR_ADC_DELTA_10_TS_C_SHIFT 11
> + #define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
> + #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
> + #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
> +
> +/*
> + * NOTE: registers from here are undocumented (the vendor Linux kernel driver
> + * and u-boot source served as reference). These only seem to be relevant on
> + * GXBB and newer.
> + */
> +#define MESON_SAR_ADC_REG11 0x2c
> + #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13)
> +
> +#define MESON_SAR_ADC_REG13 0x34
> + #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
> +
> +#define MESON_SAR_ADC_MAX_FIFO_SIZE 32
> +
> +#define MESON_SAR_ADC_CHAN(_chan) { \
> + .type = IIO_VOLTAGE, \
> + .indexed = 1, \
> + .channel = _chan, \
> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
> + BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
> + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
> + .datasheet_name = "SAR_ADC_CH"#_chan, \
> +}
> +
> +/*
> + * TODO: the hardware supports IIO_TEMP for channel 6 as well which is
> + * currently not supported by this driver.
> + */
> +static const struct iio_chan_spec meson_sar_adc_iio_channels[] = {
> + MESON_SAR_ADC_CHAN(0),
> + MESON_SAR_ADC_CHAN(1),
> + MESON_SAR_ADC_CHAN(2),
> + MESON_SAR_ADC_CHAN(3),
> + MESON_SAR_ADC_CHAN(4),
> + MESON_SAR_ADC_CHAN(5),
> + MESON_SAR_ADC_CHAN(6),
> + MESON_SAR_ADC_CHAN(7),
> + IIO_CHAN_SOFT_TIMESTAMP(8),
> +};
> +
> +enum meson_sar_adc_avg_mode {
> + NO_AVERAGING = 0x0,
> + MEAN_AVERAGING = 0x1,
> + MEDIAN_AVERAGING = 0x2,
> +};
> +
> +enum meson_sar_adc_num_samples {
> + ONE_SAMPLE = 0x0,
> + TWO_SAMPLES = 0x1,
> + FOUR_SAMPLES = 0x2,
> + EIGHT_SAMPLES = 0x3,
> +};
> +
> +enum meson_sar_adc_chan7_mux_sel {
> + CHAN7_MUX_VSS = 0x0,
> + CHAN7_MUX_VDD_DIV4 = 0x1,
> + CHAN7_MUX_VDD_DIV2 = 0x2,
> + CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
> + CHAN7_MUX_VDD = 0x4,
> + CHAN7_MUX_CH7_INPUT = 0x7,
> +};
> +
> +struct meson_sar_adc_data {
> + unsigned int resolution;
> + const char *name;
> +};
> +
> +struct meson_sar_adc_priv {
> + struct regmap *regmap;
> + struct regulator *vref;
> + const struct meson_sar_adc_data *data;
> + struct clk *clkin;
> + struct clk *core_clk;
> + struct clk *sana_clk;
> + struct clk *adc_sel_clk;
> + struct clk *adc_clk;
> + struct clk_gate clk_gate;
> + struct clk *adc_div_clk;
> + struct clk_divider clk_div;
> +};
> +
> +static const struct regmap_config meson_sar_adc_regmap_config = {
> + .reg_bits = 8,
> + .val_bits = 32,
> + .reg_stride = 4,
> + .max_register = MESON_SAR_ADC_REG13,
> +};
> +
> +static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + u32 regval;
> +
> + regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);
> +
> + return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
> +}
> +
> +static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int regval, timeout = 10000;
> +
> + /*
> + * NOTE: we need a small delay before reading the status, otherwise
> + * the sample engine may not have started internally (which would
> + * seem to us that sampling is already finished).
> + */
> + do {
> + udelay(1);
> + regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);
> + } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
> +
> + if (timeout < 0)
> + return -ETIMEDOUT;
> +
> + return 0;
> +}
> +
> +static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + int *val)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0;
> +
> + ret = meson_sar_adc_wait_busy_clear(indio_dev);
> + if (ret)
> + return ret;
> +
> + while (meson_sar_adc_get_fifo_count(indio_dev) > 0 &&
> + count < MESON_SAR_ADC_MAX_FIFO_SIZE) {
> + regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val);
> +
> + fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK,
> + regval);
> + if (fifo_chan != chan->channel)
> + continue;
> +
> + fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK,
> + regval);
> + fifo_val &= (BIT(priv->data->resolution) - 1);
> +
> + sum += fifo_val;
> + count++;
> + }
> +
> + if (!count)
> + return -ENOENT;
> +
> + *val = sum / count;
> +
> + return 0;
> +}
> +
> +static void meson_sar_adc_set_averaging(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + enum meson_sar_adc_avg_mode mode,
> + enum meson_sar_adc_num_samples samples)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int val, channel = chan->channel;
> +
> + val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(channel);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
> + MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(channel),
> + val);
> +
> + val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(channel);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
> + MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(channel), val);
> +}
> +
> +static void meson_sar_adc_enable_channel(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + u32 regval;
> +
> + /*
> + * the SAR ADC engine allows sampling multiple channels at the same
> + * time. to keep it simple we're only working with one *internal*
> + * channel, which starts counting at index 0 (which means: count = 1).
> + */
> + regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
> + MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
> +
> + /* map channel index 0 to the channel which we want to read */
> + regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0),
> + chan->channel);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
> + MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval);
> +
> + regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
> + chan->channel);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
> + MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
> + regval);
> +
> + regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
> + chan->channel);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
> + MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
> + regval);
> +
> + if (chan->channel == 6)
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
> + MESON_SAR_ADC_DELTA_10_TEMP_SEL, 0);
> +}
> +
> +static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev,
> + enum meson_sar_adc_chan7_mux_sel sel)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + u32 regval;
> +
> + regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
> + MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
> +
> + usleep_range(10, 20);
> +}
> +
> +static void meson_sar_adc_start_sample_engine(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
> + MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
> + MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
> + MESON_SAR_ADC_REG0_SAMPLING_START,
> + MESON_SAR_ADC_REG0_SAMPLING_START);
> +}
> +
> +static void meson_sar_adc_stop_sample_engine(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
> + MESON_SAR_ADC_REG0_SAMPLING_STOP,
> + MESON_SAR_ADC_REG0_SAMPLING_STOP);
> +
> + /* wait until all modules are stopped */
> + meson_sar_adc_wait_busy_clear(indio_dev);
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
> + MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
> +}
> +
> +static int meson_sar_adc_lock(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int val, timeout = 10000;
> +
> + mutex_lock(&indio_dev->mlock);
> +
> + /* prevent BL30 from using the SAR ADC while we are using it */
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
> + MESON_SAR_ADC_DELAY_KERNEL_BUSY,
> + MESON_SAR_ADC_DELAY_KERNEL_BUSY);
> +
> + /* wait until BL30 releases it's lock (so we can use the SAR ADC) */
> + do {
> + udelay(1);
> + regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val);
> + } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--);
> +
> + if (timeout < 0)
> + return -ETIMEDOUT;
> +
> + return 0;
> +}
> +
> +static void meson_sar_adc_unlock(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> +
> + /* allow BL30 to use the SAR ADC again */
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
> + MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0);
> +
> + mutex_unlock(&indio_dev->mlock);
> +}
> +
> +static void meson_sar_adc_clear_fifo(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int count;
> +
> + for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {
> + if (!meson_sar_adc_get_fifo_count(indio_dev))
> + break;
> +
> + regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, 0);
> + }
> +}
> +
> +static int meson_sar_adc_get_sample(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + enum meson_sar_adc_avg_mode avg_mode,
> + enum meson_sar_adc_num_samples avg_samples,
> + int *val)
> +{
> + int ret;
> +
> + ret = meson_sar_adc_lock(indio_dev);
> + if (ret)
> + return ret;
> +
> + /* clear the FIFO to make sure we're not reading old values */
> + meson_sar_adc_clear_fifo(indio_dev);
> +
> + meson_sar_adc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
> +
> + meson_sar_adc_enable_channel(indio_dev, chan);
> +
> + meson_sar_adc_start_sample_engine(indio_dev);
> + ret = meson_sar_adc_read_raw_sample(indio_dev, chan, val);
> + meson_sar_adc_stop_sample_engine(indio_dev);
> +
> + meson_sar_adc_unlock(indio_dev);
> +
> + if (ret) {
> + dev_warn(indio_dev->dev.parent,
> + "failed to read sample for channel %d: %d\n",
> + chan->channel, ret);
> + return ret;
> + }
> +
> + return IIO_VAL_INT;
> +}
> +
> +static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + int *val, int *val2, long mask)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int ret;
> +
> + switch (mask) {
> + case IIO_CHAN_INFO_RAW:
> + return meson_sar_adc_get_sample(indio_dev, chan, NO_AVERAGING,
> + ONE_SAMPLE, val);
> + break;
> +
> + case IIO_CHAN_INFO_AVERAGE_RAW:
> + return meson_sar_adc_get_sample(indio_dev, chan,
> + MEAN_AVERAGING, EIGHT_SAMPLES,
> + val);
> + break;
> +
> + case IIO_CHAN_INFO_SCALE:
> + ret = regulator_get_voltage(priv->vref);
> + if (ret < 0) {
> + dev_err(indio_dev->dev.parent,
> + "failed to get vref voltage: %d\n", ret);
> + return ret;
> + }
> +
> + *val = ret / 1000;
> + *val2 = priv->data->resolution;
> + return IIO_VAL_FRACTIONAL_LOG2;
> +
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static int meson_sar_adc_clk_init(struct iio_dev *indio_dev,
> + void __iomem *base)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + struct clk_init_data init;
> + const char *clk_parents[1];
> +
> + init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_div",
> + of_node_full_name(indio_dev->dev.of_node));
> + init.flags = 0;
> + init.ops = &clk_divider_ops;
> + clk_parents[0] = __clk_get_name(priv->clkin);
> + init.parent_names = clk_parents;
> + init.num_parents = 1;
> +
> + priv->clk_div.reg = base + MESON_SAR_ADC_REG3;
> + priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
> + priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
> + priv->clk_div.hw.init = &init;
> + priv->clk_div.flags = 0;
> +
> + priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
> + &priv->clk_div.hw);
> + if (WARN_ON(IS_ERR(priv->adc_div_clk)))
> + return PTR_ERR(priv->adc_div_clk);
> +
> + init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_en",
> + of_node_full_name(indio_dev->dev.of_node));
> + init.flags = CLK_SET_RATE_PARENT;
> + init.ops = &clk_gate_ops;
> + clk_parents[0] = __clk_get_name(priv->adc_div_clk);
> + init.parent_names = clk_parents;
> + init.num_parents = 1;
> +
> + priv->clk_gate.reg = base + MESON_SAR_ADC_REG3;
> + priv->clk_gate.bit_idx = fls(MESON_SAR_ADC_REG3_CLK_EN);
> + priv->clk_gate.hw.init = &init;
> +
> + priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
> + if (WARN_ON(IS_ERR(priv->adc_clk)))
> + return PTR_ERR(priv->adc_clk);
> +
> + return 0;
> +}
> +
> +static int meson_sar_adc_init(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int regval, ret;
> +
> + /*
> + * make sure we start at CH7 input since the other muxes are only used
> + * for internal calibration.
> + */
> + meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
> +
> + /*
> + * leave sampling delay and the input clocks as configured by BL30 to
> + * make sure BL30 gets the values it expects when reading the
> + * temperature sensor.
> + */
> + regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val);
> + if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED)
> + return 0;
> +
> + meson_sar_adc_stop_sample_engine(indio_dev);
> +
> + /* update the channel 6 MUX to select the temperature sensor */
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
> + MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
> + MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
> +
> + /* disable all channels by default */
> + regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
> + MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
> + MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY,
> + MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY);
> +
> + /* delay between two samples = (10+1) * 1uS */
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
> + MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
> + FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,
> + 10));
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
> + MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
> + FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
> + 0));
> +
> + /* delay between two samples = (10+1) * 1uS */
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
> + MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
> + FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
> + 10));
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
> + MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
> + FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
> + 1));
> +
> + ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
> + if (ret) {
> + dev_err(indio_dev->dev.parent,
> + "failed to set adc parent to clkin\n");
> + return ret;
> + }
> +
> + ret = clk_set_rate(priv->adc_clk, 1200000);
> + if (ret) {
> + dev_err(indio_dev->dev.parent,
> + "failed to set adc clock rate\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int ret;
> +
> + ret = meson_sar_adc_lock(indio_dev);
> + if (ret)
> + goto err_lock;
> +
> + ret = regulator_enable(priv->vref);
> + if (ret < 0) {
> + dev_err(indio_dev->dev.parent,
> + "failed to enable vref regulator\n");
> + goto err_vref;
> + }
> +
> + ret = clk_prepare_enable(priv->core_clk);
> + if (ret) {
> + dev_err(indio_dev->dev.parent, "failed to enable core clk\n");
> + goto err_core_clk;
> + }
> +
> + ret = clk_prepare_enable(priv->sana_clk);
> + if (ret) {
> + dev_err(indio_dev->dev.parent, "failed to enable sana clk\n");
> + goto err_sana_clk;
> + }
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
> + MESON_SAR_ADC_REG11_BANDGAP_EN,
> + MESON_SAR_ADC_REG11_BANDGAP_EN);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
> + MESON_SAR_ADC_REG3_ADC_EN,
> + MESON_SAR_ADC_REG3_ADC_EN);
> +
> + udelay(5);
> +
> + ret = clk_prepare_enable(priv->adc_clk);
> + if (ret) {
> + dev_err(indio_dev->dev.parent, "failed to enable adc clk\n");
> + goto err_adc_clk;
> + }
> +
> + meson_sar_adc_unlock(indio_dev);
> +
> + return 0;
> +
> +err_adc_clk:
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
> + MESON_SAR_ADC_REG3_ADC_EN, 0);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
> + MESON_SAR_ADC_REG11_BANDGAP_EN, 0);
> + clk_disable_unprepare(priv->sana_clk);
> +err_sana_clk:
> + clk_disable_unprepare(priv->core_clk);
> +err_core_clk:
> + regulator_disable(priv->vref);
> +err_vref:
> + meson_sar_adc_unlock(indio_dev);
> +err_lock:
> + return ret;
> +}
> +
> +static int meson_sar_adc_hw_disable(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int ret;
> +
> + ret = meson_sar_adc_lock(indio_dev);
> + if (ret)
> + return ret;
> +
> + clk_disable_unprepare(priv->adc_clk);
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
> + MESON_SAR_ADC_REG3_ADC_EN, 0);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
> + MESON_SAR_ADC_REG11_BANDGAP_EN, 0);
> +
> + clk_disable_unprepare(priv->sana_clk);
> + clk_disable_unprepare(priv->core_clk);
> +
> + regulator_disable(priv->vref);
> +
> + meson_sar_adc_unlock(indio_dev);
> +
> + return 0;
> +}
> +
> +static const struct iio_info meson_sar_adc_iio_info = {
> + .read_raw = meson_sar_adc_iio_info_read_raw,
> + .driver_module = THIS_MODULE,
> +};
> +
> +struct meson_sar_adc_data meson_sar_adc_gxbb_data = {
> + .resolution = 10,
> + .name = "meson-gxbb-saradc",
> +};
> +
> +struct meson_sar_adc_data meson_sar_adc_gxl_data = {
> + .resolution = 12,
> + .name = "meson-gxl-saradc",
> +};
> +
> +static const struct of_device_id meson_sar_adc_of_match[] = {
> + {
> + .compatible = "amlogic,meson-gxbb-saradc",
> + .data = &meson_sar_adc_gxbb_data,
> + }, {
> + .compatible = "amlogic,meson-gxl-saradc",
> + .data = &meson_sar_adc_gxl_data,
> + },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, meson_sar_adc_of_match);
> +
> +static int meson_sar_adc_probe(struct platform_device *pdev)
> +{
> + struct meson_sar_adc_priv *priv;
> + struct iio_dev *indio_dev;
> + struct resource *res;
> + void __iomem *base;
> + const struct of_device_id *match;
> + int ret;
> +
> + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
> + if (!indio_dev) {
> + dev_err(&pdev->dev, "failed allocating iio device\n");
> + return -ENOMEM;
> + }
> +
> + priv = iio_priv(indio_dev);
> +
> + match = of_match_device(meson_sar_adc_of_match, &pdev->dev);
> + priv->data = match->data;
> +
> + indio_dev->name = priv->data->name;
> + indio_dev->dev.parent = &pdev->dev;
> + indio_dev->dev.of_node = pdev->dev.of_node;
> + indio_dev->modes = INDIO_DIRECT_MODE;
> + indio_dev->info = &meson_sar_adc_iio_info;
> +
> + indio_dev->channels = meson_sar_adc_iio_channels;
> + indio_dev->num_channels = ARRAY_SIZE(meson_sar_adc_iio_channels);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
> + &meson_sar_adc_regmap_config);
> + if (IS_ERR(priv->regmap))
> + return PTR_ERR(priv->regmap);
> +
> + priv->clkin = devm_clk_get(&pdev->dev, "clkin");
> + if (IS_ERR(priv->clkin)) {
> + dev_err(&pdev->dev, "failed to get clkin\n");
> + return PTR_ERR(priv->clkin);
> + }
> +
> + priv->core_clk = devm_clk_get(&pdev->dev, "core");
> + if (IS_ERR(priv->core_clk)) {
> + dev_err(&pdev->dev, "failed to get core clk\n");
> + return PTR_ERR(priv->core_clk);
> + }
> +
> + priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
> + if (IS_ERR(priv->sana_clk)) {
> + if (PTR_ERR(priv->sana_clk) == -ENOENT) {
> + priv->sana_clk = NULL;
> + } else {
> + dev_err(&pdev->dev, "failed to get sana clk\n");
> + return PTR_ERR(priv->sana_clk);
> + }
> + }
> +
> + priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
> + if (IS_ERR(priv->adc_clk)) {
> + if (PTR_ERR(priv->adc_clk) == -ENOENT) {
> + priv->adc_clk = NULL;
> + } else {
> + dev_err(&pdev->dev, "failed to get adc clk\n");
> + return PTR_ERR(priv->adc_clk);
> + }
> + }
> +
> + priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
> + if (IS_ERR(priv->adc_sel_clk)) {
> + if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
> + priv->adc_sel_clk = NULL;
> + } else {
> + dev_err(&pdev->dev, "failed to get adc_sel clk\n");
> + return PTR_ERR(priv->adc_sel_clk);
> + }
> + }
> +
> + /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
> + if (!priv->adc_clk) {
> + ret = meson_sar_adc_clk_init(indio_dev, base);
> + if (ret)
> + return ret;
> + }
> +
> + priv->vref = devm_regulator_get(&pdev->dev, "vref");
> + if (IS_ERR(priv->vref)) {
> + dev_err(&pdev->dev, "failed to get vref regulator\n");
> + return PTR_ERR(priv->vref);
> + }
> +
> + ret = meson_sar_adc_init(indio_dev);
> + if (ret)
> + goto err;
> +
> + ret = meson_sar_adc_hw_enable(indio_dev);
> + if (ret)
> + goto err;
> +
> + platform_set_drvdata(pdev, indio_dev);
> +
> + ret = iio_device_register(indio_dev);
> + if (ret)
> + goto err_hw;
> +
> + return 0;
> +
> +err_hw:
> + meson_sar_adc_hw_disable(indio_dev);
> +err:
> + return ret;
> +}
> +
> +static int meson_sar_adc_remove(struct platform_device *pdev)
> +{
> + struct iio_dev *indio_dev = platform_get_drvdata(pdev);
> +
> + iio_device_unregister(indio_dev);
> +
> + return meson_sar_adc_hw_disable(indio_dev);
> +}
> +
> +#ifdef CONFIG_PM_SLEEP
Slight perference for not bothing with the if def fun which
can go wrong, but instead use __maybe_unused.
Arnd is busy pushing this into lots of drivers and I think it
is neater.
I don't care about this enough to insist on a respin if it's all
that anyone comes up with.
> +static int meson_sar_adc_suspend(struct device *dev)
> +{
> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
> +
> + return meson_sar_adc_hw_disable(indio_dev);
> +}
> +
> +static int meson_sar_adc_resume(struct device *dev)
> +{
> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
> +
> + return meson_sar_adc_hw_enable(indio_dev);
> +}
> +#endif /* CONFIG_PM_SLEEP */
> +
> +static SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops,
> + meson_sar_adc_suspend, meson_sar_adc_resume);
> +
> +static struct platform_driver meson_sar_adc_driver = {
> + .probe = meson_sar_adc_probe,
> + .remove = meson_sar_adc_remove,
> + .driver = {
> + .name = "meson-saradc",
> + .of_match_table = meson_sar_adc_of_match,
> + .pm = &meson_sar_adc_pm_ops,
> + },
> +};
> +
> +module_platform_driver(meson_sar_adc_driver);
> +
> +MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
> +MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
> +MODULE_LICENSE("GPL v2");
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v3 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
@ 2017-01-21 12:52 ` Jonathan Cameron
0 siblings, 0 replies; 110+ messages in thread
From: Jonathan Cameron @ 2017-01-21 12:52 UTC (permalink / raw)
To: Martin Blumenstingl, knaack.h, lars, pmeerw, robh+dt,
mark.rutland, khilman, linux-iio, devicetree, linux-amlogic,
linux-clk
Cc: carlo, catalin.marinas, will.deacon, mturquette, sboyd,
narmstrong, linux-arm-kernel
On 19/01/17 14:58, Martin Blumenstingl wrote:
> This adds support for the SAR (Successive Approximation Register) ADC
> on the Amlogic Meson SoCs.
>
> The code is based on the public S805 (Meson8b) and S905 (GXBB)
> datasheets (see [0] and [1]), as well as by reading (various versions
> of) the vendor driver and by inspecting the registers on the vendor
> kernels of my testing-hardware.
>
> Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
> 10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
> The code was written to support older SoCs (Meson8 and Meson8b) as well,
> but due to lack of actual testing-hardware no of_device_id was added for
> these.
>
> Two "features" from the vendor driver are currently missing:
> - the vendor driver uses channel #7 for calibration (this improves the
> accuracy of the results - in my tests the results were less than 3%
> off without calibration compared to the vendor driver). Adding support
> for this should be easy, but is not required for most applications.
> - channel #6 is connected to the SoCs internal temperature sensor.
> Adding support for this is probably not so easy since (based on the
> u-boot sources) most SoC versions are using different registers and
> algorithms for the conversion from "ADC value" to temperature.
>
> Supported by the hardware but currently not supported by the driver:
> - reading multiple channels at the same time (the hardware has a FIFO
> buffer which stores multiple results)
> - continuous sampling (this would require a way to enable this
> individually because otherwise the ADC would be drawing power
> constantly)
> - interrupt support (similar to the vendor driver this new driver is
> polling the results. It is unclear if the IRQ-mode is supported on
> older (Meson6 or Meson8) hardware as well or if there are any errata)
>
> [0]
> http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
> [1] http://dn.odroid.com/S905/DataSheet/S905_Public_Datasheet_V1.1.4.pdf
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Very nice. One really minor comment inline, that I'd only bother
dealing with should you be rolling a V4 for some other reason.
I'll take this if Rob / Mark are happy with the device tree bindings.
Give me a bump if we see nothing from them in the next week or so (or if
I miss it!)
thanks
Jonathan
> ---
> drivers/iio/adc/Kconfig | 12 +
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/meson_saradc.c | 916 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 929 insertions(+)
> create mode 100644 drivers/iio/adc/meson_saradc.c
>
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index 9c8b558ba19e..86059b9b91bf 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -371,6 +371,18 @@ config MEN_Z188_ADC
> This driver can also be built as a module. If so, the module will be
> called men_z188_adc.
>
> +config MESON_SARADC
> + tristate "Amlogic Meson SAR ADC driver"
> + default ARCH_MESON
> + depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
> + select REGMAP_MMIO
> + help
> + Say yes here to build support for the SAR ADC found in Amlogic Meson
> + SoCs.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called meson_saradc.
> +
> config MXS_LRADC
> tristate "Freescale i.MX23/i.MX28 LRADC"
> depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
> index d36c4be8d1fc..de05b9e75f8f 100644
> --- a/drivers/iio/adc/Makefile
> +++ b/drivers/iio/adc/Makefile
> @@ -36,6 +36,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
> obj-$(CONFIG_MCP3422) += mcp3422.o
> obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
> obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
> +obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
> obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
> obj-$(CONFIG_NAU7802) += nau7802.o
> obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
> diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
> new file mode 100644
> index 000000000000..11a9686d2a9c
> --- /dev/null
> +++ b/drivers/iio/adc/meson_saradc.c
> @@ -0,0 +1,916 @@
> +/*
> + * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
> + *
> + * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/iio/iio.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/regulator/consumer.h>
> +
> +#define MESON_SAR_ADC_REG0 0x00
> + #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31)
> + #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
> + #define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30)
> + #define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29)
> + #define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
> + #define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27)
> + #define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26)
> + #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
> + #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
> + #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
> + #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
> + #define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14)
> + #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
> + #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
> + #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
> + #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
> + #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
> + #define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2)
> + #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
> + #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
> +
> +#define MESON_SAR_ADC_CHAN_LIST 0x04
> + #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
> + #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \
> + (GENMASK(2, 0) << ((_chan) * 3))
> +
> +#define MESON_SAR_ADC_AVG_CNTL 0x08
> + #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
> + (16 + ((_chan) * 2))
> + #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
> + (GENMASK(17, 16) << ((_chan) * 2))
> + #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
> + (0 + ((_chan) * 2))
> + #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
> + (GENMASK(1, 0) << ((_chan) * 2))
> +
> +#define MESON_SAR_ADC_REG3 0x0c
> + #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
> + #define MESON_SAR_ADC_REG3_CLK_EN BIT(30)
> + #define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
> + #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
> + #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
> + #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
> + #define MESON_SAR_ADC_REG3_DETECT_EN BIT(22)
> + #define MESON_SAR_ADC_REG3_ADC_EN BIT(21)
> + #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
> + #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
> + #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
> + #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
> + #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
> + #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
> +
> +#define MESON_SAR_ADC_DELAY 0x10
> + #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
> + #define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15)
> + #define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
> + #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
> + #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
> + #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
> +
> +#define MESON_SAR_ADC_LAST_RD 0x14
> + #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
> + #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
> +
> +#define MESON_SAR_ADC_FIFO_RD 0x18
> + #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
> + #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
> +
> +#define MESON_SAR_ADC_AUX_SW 0x1c
> + #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
> + (GENMASK(10, 8) << (((_chan) - 2) * 2))
> + #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
> + #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
> + #define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4)
> + #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
> + #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
> + #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
> + #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
> +
> +#define MESON_SAR_ADC_CHAN_10_SW 0x20
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
> +
> +#define MESON_SAR_ADC_DETECT_IDLE_SW 0x24
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0)
> +
> +#define MESON_SAR_ADC_DELTA_10 0x28
> + #define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
> + #define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
> + #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
> + #define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
> + #define MESON_SAR_ADC_DELTA_10_TS_C_SHIFT 11
> + #define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
> + #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
> + #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
> +
> +/*
> + * NOTE: registers from here are undocumented (the vendor Linux kernel driver
> + * and u-boot source served as reference). These only seem to be relevant on
> + * GXBB and newer.
> + */
> +#define MESON_SAR_ADC_REG11 0x2c
> + #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13)
> +
> +#define MESON_SAR_ADC_REG13 0x34
> + #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
> +
> +#define MESON_SAR_ADC_MAX_FIFO_SIZE 32
> +
> +#define MESON_SAR_ADC_CHAN(_chan) { \
> + .type = IIO_VOLTAGE, \
> + .indexed = 1, \
> + .channel = _chan, \
> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
> + BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
> + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
> + .datasheet_name = "SAR_ADC_CH"#_chan, \
> +}
> +
> +/*
> + * TODO: the hardware supports IIO_TEMP for channel 6 as well which is
> + * currently not supported by this driver.
> + */
> +static const struct iio_chan_spec meson_sar_adc_iio_channels[] = {
> + MESON_SAR_ADC_CHAN(0),
> + MESON_SAR_ADC_CHAN(1),
> + MESON_SAR_ADC_CHAN(2),
> + MESON_SAR_ADC_CHAN(3),
> + MESON_SAR_ADC_CHAN(4),
> + MESON_SAR_ADC_CHAN(5),
> + MESON_SAR_ADC_CHAN(6),
> + MESON_SAR_ADC_CHAN(7),
> + IIO_CHAN_SOFT_TIMESTAMP(8),
> +};
> +
> +enum meson_sar_adc_avg_mode {
> + NO_AVERAGING = 0x0,
> + MEAN_AVERAGING = 0x1,
> + MEDIAN_AVERAGING = 0x2,
> +};
> +
> +enum meson_sar_adc_num_samples {
> + ONE_SAMPLE = 0x0,
> + TWO_SAMPLES = 0x1,
> + FOUR_SAMPLES = 0x2,
> + EIGHT_SAMPLES = 0x3,
> +};
> +
> +enum meson_sar_adc_chan7_mux_sel {
> + CHAN7_MUX_VSS = 0x0,
> + CHAN7_MUX_VDD_DIV4 = 0x1,
> + CHAN7_MUX_VDD_DIV2 = 0x2,
> + CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
> + CHAN7_MUX_VDD = 0x4,
> + CHAN7_MUX_CH7_INPUT = 0x7,
> +};
> +
> +struct meson_sar_adc_data {
> + unsigned int resolution;
> + const char *name;
> +};
> +
> +struct meson_sar_adc_priv {
> + struct regmap *regmap;
> + struct regulator *vref;
> + const struct meson_sar_adc_data *data;
> + struct clk *clkin;
> + struct clk *core_clk;
> + struct clk *sana_clk;
> + struct clk *adc_sel_clk;
> + struct clk *adc_clk;
> + struct clk_gate clk_gate;
> + struct clk *adc_div_clk;
> + struct clk_divider clk_div;
> +};
> +
> +static const struct regmap_config meson_sar_adc_regmap_config = {
> + .reg_bits = 8,
> + .val_bits = 32,
> + .reg_stride = 4,
> + .max_register = MESON_SAR_ADC_REG13,
> +};
> +
> +static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + u32 regval;
> +
> + regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);
> +
> + return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
> +}
> +
> +static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int regval, timeout = 10000;
> +
> + /*
> + * NOTE: we need a small delay before reading the status, otherwise
> + * the sample engine may not have started internally (which would
> + * seem to us that sampling is already finished).
> + */
> + do {
> + udelay(1);
> + regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);
> + } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
> +
> + if (timeout < 0)
> + return -ETIMEDOUT;
> +
> + return 0;
> +}
> +
> +static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + int *val)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0;
> +
> + ret = meson_sar_adc_wait_busy_clear(indio_dev);
> + if (ret)
> + return ret;
> +
> + while (meson_sar_adc_get_fifo_count(indio_dev) > 0 &&
> + count < MESON_SAR_ADC_MAX_FIFO_SIZE) {
> + regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val);
> +
> + fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK,
> + regval);
> + if (fifo_chan != chan->channel)
> + continue;
> +
> + fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK,
> + regval);
> + fifo_val &= (BIT(priv->data->resolution) - 1);
> +
> + sum += fifo_val;
> + count++;
> + }
> +
> + if (!count)
> + return -ENOENT;
> +
> + *val = sum / count;
> +
> + return 0;
> +}
> +
> +static void meson_sar_adc_set_averaging(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + enum meson_sar_adc_avg_mode mode,
> + enum meson_sar_adc_num_samples samples)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int val, channel = chan->channel;
> +
> + val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(channel);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
> + MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(channel),
> + val);
> +
> + val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(channel);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
> + MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(channel), val);
> +}
> +
> +static void meson_sar_adc_enable_channel(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + u32 regval;
> +
> + /*
> + * the SAR ADC engine allows sampling multiple channels at the same
> + * time. to keep it simple we're only working with one *internal*
> + * channel, which starts counting at index 0 (which means: count = 1).
> + */
> + regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
> + MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
> +
> + /* map channel index 0 to the channel which we want to read */
> + regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0),
> + chan->channel);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
> + MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval);
> +
> + regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
> + chan->channel);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
> + MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
> + regval);
> +
> + regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
> + chan->channel);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
> + MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
> + regval);
> +
> + if (chan->channel == 6)
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
> + MESON_SAR_ADC_DELTA_10_TEMP_SEL, 0);
> +}
> +
> +static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev,
> + enum meson_sar_adc_chan7_mux_sel sel)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + u32 regval;
> +
> + regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
> + MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
> +
> + usleep_range(10, 20);
> +}
> +
> +static void meson_sar_adc_start_sample_engine(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
> + MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
> + MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
> + MESON_SAR_ADC_REG0_SAMPLING_START,
> + MESON_SAR_ADC_REG0_SAMPLING_START);
> +}
> +
> +static void meson_sar_adc_stop_sample_engine(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
> + MESON_SAR_ADC_REG0_SAMPLING_STOP,
> + MESON_SAR_ADC_REG0_SAMPLING_STOP);
> +
> + /* wait until all modules are stopped */
> + meson_sar_adc_wait_busy_clear(indio_dev);
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
> + MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
> +}
> +
> +static int meson_sar_adc_lock(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int val, timeout = 10000;
> +
> + mutex_lock(&indio_dev->mlock);
> +
> + /* prevent BL30 from using the SAR ADC while we are using it */
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
> + MESON_SAR_ADC_DELAY_KERNEL_BUSY,
> + MESON_SAR_ADC_DELAY_KERNEL_BUSY);
> +
> + /* wait until BL30 releases it's lock (so we can use the SAR ADC) */
> + do {
> + udelay(1);
> + regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val);
> + } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--);
> +
> + if (timeout < 0)
> + return -ETIMEDOUT;
> +
> + return 0;
> +}
> +
> +static void meson_sar_adc_unlock(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> +
> + /* allow BL30 to use the SAR ADC again */
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
> + MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0);
> +
> + mutex_unlock(&indio_dev->mlock);
> +}
> +
> +static void meson_sar_adc_clear_fifo(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int count;
> +
> + for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {
> + if (!meson_sar_adc_get_fifo_count(indio_dev))
> + break;
> +
> + regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, 0);
> + }
> +}
> +
> +static int meson_sar_adc_get_sample(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + enum meson_sar_adc_avg_mode avg_mode,
> + enum meson_sar_adc_num_samples avg_samples,
> + int *val)
> +{
> + int ret;
> +
> + ret = meson_sar_adc_lock(indio_dev);
> + if (ret)
> + return ret;
> +
> + /* clear the FIFO to make sure we're not reading old values */
> + meson_sar_adc_clear_fifo(indio_dev);
> +
> + meson_sar_adc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
> +
> + meson_sar_adc_enable_channel(indio_dev, chan);
> +
> + meson_sar_adc_start_sample_engine(indio_dev);
> + ret = meson_sar_adc_read_raw_sample(indio_dev, chan, val);
> + meson_sar_adc_stop_sample_engine(indio_dev);
> +
> + meson_sar_adc_unlock(indio_dev);
> +
> + if (ret) {
> + dev_warn(indio_dev->dev.parent,
> + "failed to read sample for channel %d: %d\n",
> + chan->channel, ret);
> + return ret;
> + }
> +
> + return IIO_VAL_INT;
> +}
> +
> +static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + int *val, int *val2, long mask)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int ret;
> +
> + switch (mask) {
> + case IIO_CHAN_INFO_RAW:
> + return meson_sar_adc_get_sample(indio_dev, chan, NO_AVERAGING,
> + ONE_SAMPLE, val);
> + break;
> +
> + case IIO_CHAN_INFO_AVERAGE_RAW:
> + return meson_sar_adc_get_sample(indio_dev, chan,
> + MEAN_AVERAGING, EIGHT_SAMPLES,
> + val);
> + break;
> +
> + case IIO_CHAN_INFO_SCALE:
> + ret = regulator_get_voltage(priv->vref);
> + if (ret < 0) {
> + dev_err(indio_dev->dev.parent,
> + "failed to get vref voltage: %d\n", ret);
> + return ret;
> + }
> +
> + *val = ret / 1000;
> + *val2 = priv->data->resolution;
> + return IIO_VAL_FRACTIONAL_LOG2;
> +
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static int meson_sar_adc_clk_init(struct iio_dev *indio_dev,
> + void __iomem *base)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + struct clk_init_data init;
> + const char *clk_parents[1];
> +
> + init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_div",
> + of_node_full_name(indio_dev->dev.of_node));
> + init.flags = 0;
> + init.ops = &clk_divider_ops;
> + clk_parents[0] = __clk_get_name(priv->clkin);
> + init.parent_names = clk_parents;
> + init.num_parents = 1;
> +
> + priv->clk_div.reg = base + MESON_SAR_ADC_REG3;
> + priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
> + priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
> + priv->clk_div.hw.init = &init;
> + priv->clk_div.flags = 0;
> +
> + priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
> + &priv->clk_div.hw);
> + if (WARN_ON(IS_ERR(priv->adc_div_clk)))
> + return PTR_ERR(priv->adc_div_clk);
> +
> + init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_en",
> + of_node_full_name(indio_dev->dev.of_node));
> + init.flags = CLK_SET_RATE_PARENT;
> + init.ops = &clk_gate_ops;
> + clk_parents[0] = __clk_get_name(priv->adc_div_clk);
> + init.parent_names = clk_parents;
> + init.num_parents = 1;
> +
> + priv->clk_gate.reg = base + MESON_SAR_ADC_REG3;
> + priv->clk_gate.bit_idx = fls(MESON_SAR_ADC_REG3_CLK_EN);
> + priv->clk_gate.hw.init = &init;
> +
> + priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
> + if (WARN_ON(IS_ERR(priv->adc_clk)))
> + return PTR_ERR(priv->adc_clk);
> +
> + return 0;
> +}
> +
> +static int meson_sar_adc_init(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int regval, ret;
> +
> + /*
> + * make sure we start at CH7 input since the other muxes are only used
> + * for internal calibration.
> + */
> + meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
> +
> + /*
> + * leave sampling delay and the input clocks as configured by BL30 to
> + * make sure BL30 gets the values it expects when reading the
> + * temperature sensor.
> + */
> + regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val);
> + if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED)
> + return 0;
> +
> + meson_sar_adc_stop_sample_engine(indio_dev);
> +
> + /* update the channel 6 MUX to select the temperature sensor */
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
> + MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
> + MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
> +
> + /* disable all channels by default */
> + regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
> + MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
> + MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY,
> + MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY);
> +
> + /* delay between two samples = (10+1) * 1uS */
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
> + MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
> + FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,
> + 10));
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
> + MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
> + FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
> + 0));
> +
> + /* delay between two samples = (10+1) * 1uS */
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
> + MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
> + FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
> + 10));
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
> + MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
> + FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
> + 1));
> +
> + ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
> + if (ret) {
> + dev_err(indio_dev->dev.parent,
> + "failed to set adc parent to clkin\n");
> + return ret;
> + }
> +
> + ret = clk_set_rate(priv->adc_clk, 1200000);
> + if (ret) {
> + dev_err(indio_dev->dev.parent,
> + "failed to set adc clock rate\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int ret;
> +
> + ret = meson_sar_adc_lock(indio_dev);
> + if (ret)
> + goto err_lock;
> +
> + ret = regulator_enable(priv->vref);
> + if (ret < 0) {
> + dev_err(indio_dev->dev.parent,
> + "failed to enable vref regulator\n");
> + goto err_vref;
> + }
> +
> + ret = clk_prepare_enable(priv->core_clk);
> + if (ret) {
> + dev_err(indio_dev->dev.parent, "failed to enable core clk\n");
> + goto err_core_clk;
> + }
> +
> + ret = clk_prepare_enable(priv->sana_clk);
> + if (ret) {
> + dev_err(indio_dev->dev.parent, "failed to enable sana clk\n");
> + goto err_sana_clk;
> + }
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
> + MESON_SAR_ADC_REG11_BANDGAP_EN,
> + MESON_SAR_ADC_REG11_BANDGAP_EN);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
> + MESON_SAR_ADC_REG3_ADC_EN,
> + MESON_SAR_ADC_REG3_ADC_EN);
> +
> + udelay(5);
> +
> + ret = clk_prepare_enable(priv->adc_clk);
> + if (ret) {
> + dev_err(indio_dev->dev.parent, "failed to enable adc clk\n");
> + goto err_adc_clk;
> + }
> +
> + meson_sar_adc_unlock(indio_dev);
> +
> + return 0;
> +
> +err_adc_clk:
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
> + MESON_SAR_ADC_REG3_ADC_EN, 0);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
> + MESON_SAR_ADC_REG11_BANDGAP_EN, 0);
> + clk_disable_unprepare(priv->sana_clk);
> +err_sana_clk:
> + clk_disable_unprepare(priv->core_clk);
> +err_core_clk:
> + regulator_disable(priv->vref);
> +err_vref:
> + meson_sar_adc_unlock(indio_dev);
> +err_lock:
> + return ret;
> +}
> +
> +static int meson_sar_adc_hw_disable(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int ret;
> +
> + ret = meson_sar_adc_lock(indio_dev);
> + if (ret)
> + return ret;
> +
> + clk_disable_unprepare(priv->adc_clk);
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
> + MESON_SAR_ADC_REG3_ADC_EN, 0);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
> + MESON_SAR_ADC_REG11_BANDGAP_EN, 0);
> +
> + clk_disable_unprepare(priv->sana_clk);
> + clk_disable_unprepare(priv->core_clk);
> +
> + regulator_disable(priv->vref);
> +
> + meson_sar_adc_unlock(indio_dev);
> +
> + return 0;
> +}
> +
> +static const struct iio_info meson_sar_adc_iio_info = {
> + .read_raw = meson_sar_adc_iio_info_read_raw,
> + .driver_module = THIS_MODULE,
> +};
> +
> +struct meson_sar_adc_data meson_sar_adc_gxbb_data = {
> + .resolution = 10,
> + .name = "meson-gxbb-saradc",
> +};
> +
> +struct meson_sar_adc_data meson_sar_adc_gxl_data = {
> + .resolution = 12,
> + .name = "meson-gxl-saradc",
> +};
> +
> +static const struct of_device_id meson_sar_adc_of_match[] = {
> + {
> + .compatible = "amlogic,meson-gxbb-saradc",
> + .data = &meson_sar_adc_gxbb_data,
> + }, {
> + .compatible = "amlogic,meson-gxl-saradc",
> + .data = &meson_sar_adc_gxl_data,
> + },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, meson_sar_adc_of_match);
> +
> +static int meson_sar_adc_probe(struct platform_device *pdev)
> +{
> + struct meson_sar_adc_priv *priv;
> + struct iio_dev *indio_dev;
> + struct resource *res;
> + void __iomem *base;
> + const struct of_device_id *match;
> + int ret;
> +
> + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
> + if (!indio_dev) {
> + dev_err(&pdev->dev, "failed allocating iio device\n");
> + return -ENOMEM;
> + }
> +
> + priv = iio_priv(indio_dev);
> +
> + match = of_match_device(meson_sar_adc_of_match, &pdev->dev);
> + priv->data = match->data;
> +
> + indio_dev->name = priv->data->name;
> + indio_dev->dev.parent = &pdev->dev;
> + indio_dev->dev.of_node = pdev->dev.of_node;
> + indio_dev->modes = INDIO_DIRECT_MODE;
> + indio_dev->info = &meson_sar_adc_iio_info;
> +
> + indio_dev->channels = meson_sar_adc_iio_channels;
> + indio_dev->num_channels = ARRAY_SIZE(meson_sar_adc_iio_channels);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
> + &meson_sar_adc_regmap_config);
> + if (IS_ERR(priv->regmap))
> + return PTR_ERR(priv->regmap);
> +
> + priv->clkin = devm_clk_get(&pdev->dev, "clkin");
> + if (IS_ERR(priv->clkin)) {
> + dev_err(&pdev->dev, "failed to get clkin\n");
> + return PTR_ERR(priv->clkin);
> + }
> +
> + priv->core_clk = devm_clk_get(&pdev->dev, "core");
> + if (IS_ERR(priv->core_clk)) {
> + dev_err(&pdev->dev, "failed to get core clk\n");
> + return PTR_ERR(priv->core_clk);
> + }
> +
> + priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
> + if (IS_ERR(priv->sana_clk)) {
> + if (PTR_ERR(priv->sana_clk) == -ENOENT) {
> + priv->sana_clk = NULL;
> + } else {
> + dev_err(&pdev->dev, "failed to get sana clk\n");
> + return PTR_ERR(priv->sana_clk);
> + }
> + }
> +
> + priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
> + if (IS_ERR(priv->adc_clk)) {
> + if (PTR_ERR(priv->adc_clk) == -ENOENT) {
> + priv->adc_clk = NULL;
> + } else {
> + dev_err(&pdev->dev, "failed to get adc clk\n");
> + return PTR_ERR(priv->adc_clk);
> + }
> + }
> +
> + priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
> + if (IS_ERR(priv->adc_sel_clk)) {
> + if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
> + priv->adc_sel_clk = NULL;
> + } else {
> + dev_err(&pdev->dev, "failed to get adc_sel clk\n");
> + return PTR_ERR(priv->adc_sel_clk);
> + }
> + }
> +
> + /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
> + if (!priv->adc_clk) {
> + ret = meson_sar_adc_clk_init(indio_dev, base);
> + if (ret)
> + return ret;
> + }
> +
> + priv->vref = devm_regulator_get(&pdev->dev, "vref");
> + if (IS_ERR(priv->vref)) {
> + dev_err(&pdev->dev, "failed to get vref regulator\n");
> + return PTR_ERR(priv->vref);
> + }
> +
> + ret = meson_sar_adc_init(indio_dev);
> + if (ret)
> + goto err;
> +
> + ret = meson_sar_adc_hw_enable(indio_dev);
> + if (ret)
> + goto err;
> +
> + platform_set_drvdata(pdev, indio_dev);
> +
> + ret = iio_device_register(indio_dev);
> + if (ret)
> + goto err_hw;
> +
> + return 0;
> +
> +err_hw:
> + meson_sar_adc_hw_disable(indio_dev);
> +err:
> + return ret;
> +}
> +
> +static int meson_sar_adc_remove(struct platform_device *pdev)
> +{
> + struct iio_dev *indio_dev = platform_get_drvdata(pdev);
> +
> + iio_device_unregister(indio_dev);
> +
> + return meson_sar_adc_hw_disable(indio_dev);
> +}
> +
> +#ifdef CONFIG_PM_SLEEP
Slight perference for not bothing with the if def fun which
can go wrong, but instead use __maybe_unused.
Arnd is busy pushing this into lots of drivers and I think it
is neater.
I don't care about this enough to insist on a respin if it's all
that anyone comes up with.
> +static int meson_sar_adc_suspend(struct device *dev)
> +{
> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
> +
> + return meson_sar_adc_hw_disable(indio_dev);
> +}
> +
> +static int meson_sar_adc_resume(struct device *dev)
> +{
> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
> +
> + return meson_sar_adc_hw_enable(indio_dev);
> +}
> +#endif /* CONFIG_PM_SLEEP */
> +
> +static SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops,
> + meson_sar_adc_suspend, meson_sar_adc_resume);
> +
> +static struct platform_driver meson_sar_adc_driver = {
> + .probe = meson_sar_adc_probe,
> + .remove = meson_sar_adc_remove,
> + .driver = {
> + .name = "meson-saradc",
> + .of_match_table = meson_sar_adc_of_match,
> + .pm = &meson_sar_adc_pm_ops,
> + },
> +};
> +
> +module_platform_driver(meson_sar_adc_driver);
> +
> +MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
> +MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
> +MODULE_LICENSE("GPL v2");
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v3 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
@ 2017-01-21 12:52 ` Jonathan Cameron
0 siblings, 0 replies; 110+ messages in thread
From: Jonathan Cameron @ 2017-01-21 12:52 UTC (permalink / raw)
To: linux-arm-kernel
On 19/01/17 14:58, Martin Blumenstingl wrote:
> This adds support for the SAR (Successive Approximation Register) ADC
> on the Amlogic Meson SoCs.
>
> The code is based on the public S805 (Meson8b) and S905 (GXBB)
> datasheets (see [0] and [1]), as well as by reading (various versions
> of) the vendor driver and by inspecting the registers on the vendor
> kernels of my testing-hardware.
>
> Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
> 10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
> The code was written to support older SoCs (Meson8 and Meson8b) as well,
> but due to lack of actual testing-hardware no of_device_id was added for
> these.
>
> Two "features" from the vendor driver are currently missing:
> - the vendor driver uses channel #7 for calibration (this improves the
> accuracy of the results - in my tests the results were less than 3%
> off without calibration compared to the vendor driver). Adding support
> for this should be easy, but is not required for most applications.
> - channel #6 is connected to the SoCs internal temperature sensor.
> Adding support for this is probably not so easy since (based on the
> u-boot sources) most SoC versions are using different registers and
> algorithms for the conversion from "ADC value" to temperature.
>
> Supported by the hardware but currently not supported by the driver:
> - reading multiple channels at the same time (the hardware has a FIFO
> buffer which stores multiple results)
> - continuous sampling (this would require a way to enable this
> individually because otherwise the ADC would be drawing power
> constantly)
> - interrupt support (similar to the vendor driver this new driver is
> polling the results. It is unclear if the IRQ-mode is supported on
> older (Meson6 or Meson8) hardware as well or if there are any errata)
>
> [0]
> http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
> [1] http://dn.odroid.com/S905/DataSheet/S905_Public_Datasheet_V1.1.4.pdf
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Very nice. One really minor comment inline, that I'd only bother
dealing with should you be rolling a V4 for some other reason.
I'll take this if Rob / Mark are happy with the device tree bindings.
Give me a bump if we see nothing from them in the next week or so (or if
I miss it!)
thanks
Jonathan
> ---
> drivers/iio/adc/Kconfig | 12 +
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/meson_saradc.c | 916 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 929 insertions(+)
> create mode 100644 drivers/iio/adc/meson_saradc.c
>
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index 9c8b558ba19e..86059b9b91bf 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -371,6 +371,18 @@ config MEN_Z188_ADC
> This driver can also be built as a module. If so, the module will be
> called men_z188_adc.
>
> +config MESON_SARADC
> + tristate "Amlogic Meson SAR ADC driver"
> + default ARCH_MESON
> + depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
> + select REGMAP_MMIO
> + help
> + Say yes here to build support for the SAR ADC found in Amlogic Meson
> + SoCs.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called meson_saradc.
> +
> config MXS_LRADC
> tristate "Freescale i.MX23/i.MX28 LRADC"
> depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
> index d36c4be8d1fc..de05b9e75f8f 100644
> --- a/drivers/iio/adc/Makefile
> +++ b/drivers/iio/adc/Makefile
> @@ -36,6 +36,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
> obj-$(CONFIG_MCP3422) += mcp3422.o
> obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
> obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
> +obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
> obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
> obj-$(CONFIG_NAU7802) += nau7802.o
> obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
> diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
> new file mode 100644
> index 000000000000..11a9686d2a9c
> --- /dev/null
> +++ b/drivers/iio/adc/meson_saradc.c
> @@ -0,0 +1,916 @@
> +/*
> + * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
> + *
> + * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/iio/iio.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/regulator/consumer.h>
> +
> +#define MESON_SAR_ADC_REG0 0x00
> + #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31)
> + #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
> + #define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30)
> + #define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29)
> + #define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
> + #define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27)
> + #define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26)
> + #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
> + #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
> + #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
> + #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
> + #define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14)
> + #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
> + #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
> + #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
> + #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
> + #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
> + #define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2)
> + #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
> + #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
> +
> +#define MESON_SAR_ADC_CHAN_LIST 0x04
> + #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
> + #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \
> + (GENMASK(2, 0) << ((_chan) * 3))
> +
> +#define MESON_SAR_ADC_AVG_CNTL 0x08
> + #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
> + (16 + ((_chan) * 2))
> + #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
> + (GENMASK(17, 16) << ((_chan) * 2))
> + #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
> + (0 + ((_chan) * 2))
> + #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
> + (GENMASK(1, 0) << ((_chan) * 2))
> +
> +#define MESON_SAR_ADC_REG3 0x0c
> + #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
> + #define MESON_SAR_ADC_REG3_CLK_EN BIT(30)
> + #define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
> + #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
> + #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
> + #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
> + #define MESON_SAR_ADC_REG3_DETECT_EN BIT(22)
> + #define MESON_SAR_ADC_REG3_ADC_EN BIT(21)
> + #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
> + #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
> + #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
> + #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
> + #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
> + #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
> +
> +#define MESON_SAR_ADC_DELAY 0x10
> + #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
> + #define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15)
> + #define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
> + #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
> + #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
> + #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
> +
> +#define MESON_SAR_ADC_LAST_RD 0x14
> + #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
> + #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
> +
> +#define MESON_SAR_ADC_FIFO_RD 0x18
> + #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
> + #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
> +
> +#define MESON_SAR_ADC_AUX_SW 0x1c
> + #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
> + (GENMASK(10, 8) << (((_chan) - 2) * 2))
> + #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
> + #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
> + #define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4)
> + #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
> + #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
> + #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
> + #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
> +
> +#define MESON_SAR_ADC_CHAN_10_SW 0x20
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
> +
> +#define MESON_SAR_ADC_DETECT_IDLE_SW 0x24
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0)
> +
> +#define MESON_SAR_ADC_DELTA_10 0x28
> + #define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
> + #define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
> + #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
> + #define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
> + #define MESON_SAR_ADC_DELTA_10_TS_C_SHIFT 11
> + #define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
> + #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
> + #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
> +
> +/*
> + * NOTE: registers from here are undocumented (the vendor Linux kernel driver
> + * and u-boot source served as reference). These only seem to be relevant on
> + * GXBB and newer.
> + */
> +#define MESON_SAR_ADC_REG11 0x2c
> + #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13)
> +
> +#define MESON_SAR_ADC_REG13 0x34
> + #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
> +
> +#define MESON_SAR_ADC_MAX_FIFO_SIZE 32
> +
> +#define MESON_SAR_ADC_CHAN(_chan) { \
> + .type = IIO_VOLTAGE, \
> + .indexed = 1, \
> + .channel = _chan, \
> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
> + BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
> + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
> + .datasheet_name = "SAR_ADC_CH"#_chan, \
> +}
> +
> +/*
> + * TODO: the hardware supports IIO_TEMP for channel 6 as well which is
> + * currently not supported by this driver.
> + */
> +static const struct iio_chan_spec meson_sar_adc_iio_channels[] = {
> + MESON_SAR_ADC_CHAN(0),
> + MESON_SAR_ADC_CHAN(1),
> + MESON_SAR_ADC_CHAN(2),
> + MESON_SAR_ADC_CHAN(3),
> + MESON_SAR_ADC_CHAN(4),
> + MESON_SAR_ADC_CHAN(5),
> + MESON_SAR_ADC_CHAN(6),
> + MESON_SAR_ADC_CHAN(7),
> + IIO_CHAN_SOFT_TIMESTAMP(8),
> +};
> +
> +enum meson_sar_adc_avg_mode {
> + NO_AVERAGING = 0x0,
> + MEAN_AVERAGING = 0x1,
> + MEDIAN_AVERAGING = 0x2,
> +};
> +
> +enum meson_sar_adc_num_samples {
> + ONE_SAMPLE = 0x0,
> + TWO_SAMPLES = 0x1,
> + FOUR_SAMPLES = 0x2,
> + EIGHT_SAMPLES = 0x3,
> +};
> +
> +enum meson_sar_adc_chan7_mux_sel {
> + CHAN7_MUX_VSS = 0x0,
> + CHAN7_MUX_VDD_DIV4 = 0x1,
> + CHAN7_MUX_VDD_DIV2 = 0x2,
> + CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
> + CHAN7_MUX_VDD = 0x4,
> + CHAN7_MUX_CH7_INPUT = 0x7,
> +};
> +
> +struct meson_sar_adc_data {
> + unsigned int resolution;
> + const char *name;
> +};
> +
> +struct meson_sar_adc_priv {
> + struct regmap *regmap;
> + struct regulator *vref;
> + const struct meson_sar_adc_data *data;
> + struct clk *clkin;
> + struct clk *core_clk;
> + struct clk *sana_clk;
> + struct clk *adc_sel_clk;
> + struct clk *adc_clk;
> + struct clk_gate clk_gate;
> + struct clk *adc_div_clk;
> + struct clk_divider clk_div;
> +};
> +
> +static const struct regmap_config meson_sar_adc_regmap_config = {
> + .reg_bits = 8,
> + .val_bits = 32,
> + .reg_stride = 4,
> + .max_register = MESON_SAR_ADC_REG13,
> +};
> +
> +static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + u32 regval;
> +
> + regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);
> +
> + return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
> +}
> +
> +static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int regval, timeout = 10000;
> +
> + /*
> + * NOTE: we need a small delay before reading the status, otherwise
> + * the sample engine may not have started internally (which would
> + * seem to us that sampling is already finished).
> + */
> + do {
> + udelay(1);
> + regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);
> + } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
> +
> + if (timeout < 0)
> + return -ETIMEDOUT;
> +
> + return 0;
> +}
> +
> +static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + int *val)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0;
> +
> + ret = meson_sar_adc_wait_busy_clear(indio_dev);
> + if (ret)
> + return ret;
> +
> + while (meson_sar_adc_get_fifo_count(indio_dev) > 0 &&
> + count < MESON_SAR_ADC_MAX_FIFO_SIZE) {
> + regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val);
> +
> + fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK,
> + regval);
> + if (fifo_chan != chan->channel)
> + continue;
> +
> + fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK,
> + regval);
> + fifo_val &= (BIT(priv->data->resolution) - 1);
> +
> + sum += fifo_val;
> + count++;
> + }
> +
> + if (!count)
> + return -ENOENT;
> +
> + *val = sum / count;
> +
> + return 0;
> +}
> +
> +static void meson_sar_adc_set_averaging(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + enum meson_sar_adc_avg_mode mode,
> + enum meson_sar_adc_num_samples samples)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int val, channel = chan->channel;
> +
> + val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(channel);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
> + MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(channel),
> + val);
> +
> + val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(channel);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
> + MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(channel), val);
> +}
> +
> +static void meson_sar_adc_enable_channel(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + u32 regval;
> +
> + /*
> + * the SAR ADC engine allows sampling multiple channels at the same
> + * time. to keep it simple we're only working with one *internal*
> + * channel, which starts counting at index 0 (which means: count = 1).
> + */
> + regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
> + MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
> +
> + /* map channel index 0 to the channel which we want to read */
> + regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0),
> + chan->channel);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
> + MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval);
> +
> + regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
> + chan->channel);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
> + MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
> + regval);
> +
> + regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
> + chan->channel);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
> + MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
> + regval);
> +
> + if (chan->channel == 6)
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
> + MESON_SAR_ADC_DELTA_10_TEMP_SEL, 0);
> +}
> +
> +static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev,
> + enum meson_sar_adc_chan7_mux_sel sel)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + u32 regval;
> +
> + regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
> + MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
> +
> + usleep_range(10, 20);
> +}
> +
> +static void meson_sar_adc_start_sample_engine(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
> + MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
> + MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
> + MESON_SAR_ADC_REG0_SAMPLING_START,
> + MESON_SAR_ADC_REG0_SAMPLING_START);
> +}
> +
> +static void meson_sar_adc_stop_sample_engine(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
> + MESON_SAR_ADC_REG0_SAMPLING_STOP,
> + MESON_SAR_ADC_REG0_SAMPLING_STOP);
> +
> + /* wait until all modules are stopped */
> + meson_sar_adc_wait_busy_clear(indio_dev);
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
> + MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
> +}
> +
> +static int meson_sar_adc_lock(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int val, timeout = 10000;
> +
> + mutex_lock(&indio_dev->mlock);
> +
> + /* prevent BL30 from using the SAR ADC while we are using it */
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
> + MESON_SAR_ADC_DELAY_KERNEL_BUSY,
> + MESON_SAR_ADC_DELAY_KERNEL_BUSY);
> +
> + /* wait until BL30 releases it's lock (so we can use the SAR ADC) */
> + do {
> + udelay(1);
> + regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val);
> + } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--);
> +
> + if (timeout < 0)
> + return -ETIMEDOUT;
> +
> + return 0;
> +}
> +
> +static void meson_sar_adc_unlock(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> +
> + /* allow BL30 to use the SAR ADC again */
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
> + MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0);
> +
> + mutex_unlock(&indio_dev->mlock);
> +}
> +
> +static void meson_sar_adc_clear_fifo(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int count;
> +
> + for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {
> + if (!meson_sar_adc_get_fifo_count(indio_dev))
> + break;
> +
> + regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, 0);
> + }
> +}
> +
> +static int meson_sar_adc_get_sample(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + enum meson_sar_adc_avg_mode avg_mode,
> + enum meson_sar_adc_num_samples avg_samples,
> + int *val)
> +{
> + int ret;
> +
> + ret = meson_sar_adc_lock(indio_dev);
> + if (ret)
> + return ret;
> +
> + /* clear the FIFO to make sure we're not reading old values */
> + meson_sar_adc_clear_fifo(indio_dev);
> +
> + meson_sar_adc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
> +
> + meson_sar_adc_enable_channel(indio_dev, chan);
> +
> + meson_sar_adc_start_sample_engine(indio_dev);
> + ret = meson_sar_adc_read_raw_sample(indio_dev, chan, val);
> + meson_sar_adc_stop_sample_engine(indio_dev);
> +
> + meson_sar_adc_unlock(indio_dev);
> +
> + if (ret) {
> + dev_warn(indio_dev->dev.parent,
> + "failed to read sample for channel %d: %d\n",
> + chan->channel, ret);
> + return ret;
> + }
> +
> + return IIO_VAL_INT;
> +}
> +
> +static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + int *val, int *val2, long mask)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int ret;
> +
> + switch (mask) {
> + case IIO_CHAN_INFO_RAW:
> + return meson_sar_adc_get_sample(indio_dev, chan, NO_AVERAGING,
> + ONE_SAMPLE, val);
> + break;
> +
> + case IIO_CHAN_INFO_AVERAGE_RAW:
> + return meson_sar_adc_get_sample(indio_dev, chan,
> + MEAN_AVERAGING, EIGHT_SAMPLES,
> + val);
> + break;
> +
> + case IIO_CHAN_INFO_SCALE:
> + ret = regulator_get_voltage(priv->vref);
> + if (ret < 0) {
> + dev_err(indio_dev->dev.parent,
> + "failed to get vref voltage: %d\n", ret);
> + return ret;
> + }
> +
> + *val = ret / 1000;
> + *val2 = priv->data->resolution;
> + return IIO_VAL_FRACTIONAL_LOG2;
> +
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static int meson_sar_adc_clk_init(struct iio_dev *indio_dev,
> + void __iomem *base)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + struct clk_init_data init;
> + const char *clk_parents[1];
> +
> + init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_div",
> + of_node_full_name(indio_dev->dev.of_node));
> + init.flags = 0;
> + init.ops = &clk_divider_ops;
> + clk_parents[0] = __clk_get_name(priv->clkin);
> + init.parent_names = clk_parents;
> + init.num_parents = 1;
> +
> + priv->clk_div.reg = base + MESON_SAR_ADC_REG3;
> + priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
> + priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
> + priv->clk_div.hw.init = &init;
> + priv->clk_div.flags = 0;
> +
> + priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
> + &priv->clk_div.hw);
> + if (WARN_ON(IS_ERR(priv->adc_div_clk)))
> + return PTR_ERR(priv->adc_div_clk);
> +
> + init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_en",
> + of_node_full_name(indio_dev->dev.of_node));
> + init.flags = CLK_SET_RATE_PARENT;
> + init.ops = &clk_gate_ops;
> + clk_parents[0] = __clk_get_name(priv->adc_div_clk);
> + init.parent_names = clk_parents;
> + init.num_parents = 1;
> +
> + priv->clk_gate.reg = base + MESON_SAR_ADC_REG3;
> + priv->clk_gate.bit_idx = fls(MESON_SAR_ADC_REG3_CLK_EN);
> + priv->clk_gate.hw.init = &init;
> +
> + priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
> + if (WARN_ON(IS_ERR(priv->adc_clk)))
> + return PTR_ERR(priv->adc_clk);
> +
> + return 0;
> +}
> +
> +static int meson_sar_adc_init(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int regval, ret;
> +
> + /*
> + * make sure we start at CH7 input since the other muxes are only used
> + * for internal calibration.
> + */
> + meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
> +
> + /*
> + * leave sampling delay and the input clocks as configured by BL30 to
> + * make sure BL30 gets the values it expects when reading the
> + * temperature sensor.
> + */
> + regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val);
> + if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED)
> + return 0;
> +
> + meson_sar_adc_stop_sample_engine(indio_dev);
> +
> + /* update the channel 6 MUX to select the temperature sensor */
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
> + MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
> + MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
> +
> + /* disable all channels by default */
> + regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
> + MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
> + MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY,
> + MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY);
> +
> + /* delay between two samples = (10+1) * 1uS */
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
> + MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
> + FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,
> + 10));
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
> + MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
> + FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
> + 0));
> +
> + /* delay between two samples = (10+1) * 1uS */
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
> + MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
> + FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
> + 10));
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
> + MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
> + FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
> + 1));
> +
> + ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
> + if (ret) {
> + dev_err(indio_dev->dev.parent,
> + "failed to set adc parent to clkin\n");
> + return ret;
> + }
> +
> + ret = clk_set_rate(priv->adc_clk, 1200000);
> + if (ret) {
> + dev_err(indio_dev->dev.parent,
> + "failed to set adc clock rate\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int ret;
> +
> + ret = meson_sar_adc_lock(indio_dev);
> + if (ret)
> + goto err_lock;
> +
> + ret = regulator_enable(priv->vref);
> + if (ret < 0) {
> + dev_err(indio_dev->dev.parent,
> + "failed to enable vref regulator\n");
> + goto err_vref;
> + }
> +
> + ret = clk_prepare_enable(priv->core_clk);
> + if (ret) {
> + dev_err(indio_dev->dev.parent, "failed to enable core clk\n");
> + goto err_core_clk;
> + }
> +
> + ret = clk_prepare_enable(priv->sana_clk);
> + if (ret) {
> + dev_err(indio_dev->dev.parent, "failed to enable sana clk\n");
> + goto err_sana_clk;
> + }
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
> + MESON_SAR_ADC_REG11_BANDGAP_EN,
> + MESON_SAR_ADC_REG11_BANDGAP_EN);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
> + MESON_SAR_ADC_REG3_ADC_EN,
> + MESON_SAR_ADC_REG3_ADC_EN);
> +
> + udelay(5);
> +
> + ret = clk_prepare_enable(priv->adc_clk);
> + if (ret) {
> + dev_err(indio_dev->dev.parent, "failed to enable adc clk\n");
> + goto err_adc_clk;
> + }
> +
> + meson_sar_adc_unlock(indio_dev);
> +
> + return 0;
> +
> +err_adc_clk:
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
> + MESON_SAR_ADC_REG3_ADC_EN, 0);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
> + MESON_SAR_ADC_REG11_BANDGAP_EN, 0);
> + clk_disable_unprepare(priv->sana_clk);
> +err_sana_clk:
> + clk_disable_unprepare(priv->core_clk);
> +err_core_clk:
> + regulator_disable(priv->vref);
> +err_vref:
> + meson_sar_adc_unlock(indio_dev);
> +err_lock:
> + return ret;
> +}
> +
> +static int meson_sar_adc_hw_disable(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int ret;
> +
> + ret = meson_sar_adc_lock(indio_dev);
> + if (ret)
> + return ret;
> +
> + clk_disable_unprepare(priv->adc_clk);
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
> + MESON_SAR_ADC_REG3_ADC_EN, 0);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
> + MESON_SAR_ADC_REG11_BANDGAP_EN, 0);
> +
> + clk_disable_unprepare(priv->sana_clk);
> + clk_disable_unprepare(priv->core_clk);
> +
> + regulator_disable(priv->vref);
> +
> + meson_sar_adc_unlock(indio_dev);
> +
> + return 0;
> +}
> +
> +static const struct iio_info meson_sar_adc_iio_info = {
> + .read_raw = meson_sar_adc_iio_info_read_raw,
> + .driver_module = THIS_MODULE,
> +};
> +
> +struct meson_sar_adc_data meson_sar_adc_gxbb_data = {
> + .resolution = 10,
> + .name = "meson-gxbb-saradc",
> +};
> +
> +struct meson_sar_adc_data meson_sar_adc_gxl_data = {
> + .resolution = 12,
> + .name = "meson-gxl-saradc",
> +};
> +
> +static const struct of_device_id meson_sar_adc_of_match[] = {
> + {
> + .compatible = "amlogic,meson-gxbb-saradc",
> + .data = &meson_sar_adc_gxbb_data,
> + }, {
> + .compatible = "amlogic,meson-gxl-saradc",
> + .data = &meson_sar_adc_gxl_data,
> + },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, meson_sar_adc_of_match);
> +
> +static int meson_sar_adc_probe(struct platform_device *pdev)
> +{
> + struct meson_sar_adc_priv *priv;
> + struct iio_dev *indio_dev;
> + struct resource *res;
> + void __iomem *base;
> + const struct of_device_id *match;
> + int ret;
> +
> + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
> + if (!indio_dev) {
> + dev_err(&pdev->dev, "failed allocating iio device\n");
> + return -ENOMEM;
> + }
> +
> + priv = iio_priv(indio_dev);
> +
> + match = of_match_device(meson_sar_adc_of_match, &pdev->dev);
> + priv->data = match->data;
> +
> + indio_dev->name = priv->data->name;
> + indio_dev->dev.parent = &pdev->dev;
> + indio_dev->dev.of_node = pdev->dev.of_node;
> + indio_dev->modes = INDIO_DIRECT_MODE;
> + indio_dev->info = &meson_sar_adc_iio_info;
> +
> + indio_dev->channels = meson_sar_adc_iio_channels;
> + indio_dev->num_channels = ARRAY_SIZE(meson_sar_adc_iio_channels);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
> + &meson_sar_adc_regmap_config);
> + if (IS_ERR(priv->regmap))
> + return PTR_ERR(priv->regmap);
> +
> + priv->clkin = devm_clk_get(&pdev->dev, "clkin");
> + if (IS_ERR(priv->clkin)) {
> + dev_err(&pdev->dev, "failed to get clkin\n");
> + return PTR_ERR(priv->clkin);
> + }
> +
> + priv->core_clk = devm_clk_get(&pdev->dev, "core");
> + if (IS_ERR(priv->core_clk)) {
> + dev_err(&pdev->dev, "failed to get core clk\n");
> + return PTR_ERR(priv->core_clk);
> + }
> +
> + priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
> + if (IS_ERR(priv->sana_clk)) {
> + if (PTR_ERR(priv->sana_clk) == -ENOENT) {
> + priv->sana_clk = NULL;
> + } else {
> + dev_err(&pdev->dev, "failed to get sana clk\n");
> + return PTR_ERR(priv->sana_clk);
> + }
> + }
> +
> + priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
> + if (IS_ERR(priv->adc_clk)) {
> + if (PTR_ERR(priv->adc_clk) == -ENOENT) {
> + priv->adc_clk = NULL;
> + } else {
> + dev_err(&pdev->dev, "failed to get adc clk\n");
> + return PTR_ERR(priv->adc_clk);
> + }
> + }
> +
> + priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
> + if (IS_ERR(priv->adc_sel_clk)) {
> + if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
> + priv->adc_sel_clk = NULL;
> + } else {
> + dev_err(&pdev->dev, "failed to get adc_sel clk\n");
> + return PTR_ERR(priv->adc_sel_clk);
> + }
> + }
> +
> + /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
> + if (!priv->adc_clk) {
> + ret = meson_sar_adc_clk_init(indio_dev, base);
> + if (ret)
> + return ret;
> + }
> +
> + priv->vref = devm_regulator_get(&pdev->dev, "vref");
> + if (IS_ERR(priv->vref)) {
> + dev_err(&pdev->dev, "failed to get vref regulator\n");
> + return PTR_ERR(priv->vref);
> + }
> +
> + ret = meson_sar_adc_init(indio_dev);
> + if (ret)
> + goto err;
> +
> + ret = meson_sar_adc_hw_enable(indio_dev);
> + if (ret)
> + goto err;
> +
> + platform_set_drvdata(pdev, indio_dev);
> +
> + ret = iio_device_register(indio_dev);
> + if (ret)
> + goto err_hw;
> +
> + return 0;
> +
> +err_hw:
> + meson_sar_adc_hw_disable(indio_dev);
> +err:
> + return ret;
> +}
> +
> +static int meson_sar_adc_remove(struct platform_device *pdev)
> +{
> + struct iio_dev *indio_dev = platform_get_drvdata(pdev);
> +
> + iio_device_unregister(indio_dev);
> +
> + return meson_sar_adc_hw_disable(indio_dev);
> +}
> +
> +#ifdef CONFIG_PM_SLEEP
Slight perference for not bothing with the if def fun which
can go wrong, but instead use __maybe_unused.
Arnd is busy pushing this into lots of drivers and I think it
is neater.
I don't care about this enough to insist on a respin if it's all
that anyone comes up with.
> +static int meson_sar_adc_suspend(struct device *dev)
> +{
> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
> +
> + return meson_sar_adc_hw_disable(indio_dev);
> +}
> +
> +static int meson_sar_adc_resume(struct device *dev)
> +{
> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
> +
> + return meson_sar_adc_hw_enable(indio_dev);
> +}
> +#endif /* CONFIG_PM_SLEEP */
> +
> +static SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops,
> + meson_sar_adc_suspend, meson_sar_adc_resume);
> +
> +static struct platform_driver meson_sar_adc_driver = {
> + .probe = meson_sar_adc_probe,
> + .remove = meson_sar_adc_remove,
> + .driver = {
> + .name = "meson-saradc",
> + .of_match_table = meson_sar_adc_of_match,
> + .pm = &meson_sar_adc_pm_ops,
> + },
> +};
> +
> +module_platform_driver(meson_sar_adc_driver);
> +
> +MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
> +MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
> +MODULE_LICENSE("GPL v2");
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v3 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs
@ 2017-01-21 12:52 ` Jonathan Cameron
0 siblings, 0 replies; 110+ messages in thread
From: Jonathan Cameron @ 2017-01-21 12:52 UTC (permalink / raw)
To: linus-amlogic
On 19/01/17 14:58, Martin Blumenstingl wrote:
> This adds support for the SAR (Successive Approximation Register) ADC
> on the Amlogic Meson SoCs.
>
> The code is based on the public S805 (Meson8b) and S905 (GXBB)
> datasheets (see [0] and [1]), as well as by reading (various versions
> of) the vendor driver and by inspecting the registers on the vendor
> kernels of my testing-hardware.
>
> Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
> 10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
> The code was written to support older SoCs (Meson8 and Meson8b) as well,
> but due to lack of actual testing-hardware no of_device_id was added for
> these.
>
> Two "features" from the vendor driver are currently missing:
> - the vendor driver uses channel #7 for calibration (this improves the
> accuracy of the results - in my tests the results were less than 3%
> off without calibration compared to the vendor driver). Adding support
> for this should be easy, but is not required for most applications.
> - channel #6 is connected to the SoCs internal temperature sensor.
> Adding support for this is probably not so easy since (based on the
> u-boot sources) most SoC versions are using different registers and
> algorithms for the conversion from "ADC value" to temperature.
>
> Supported by the hardware but currently not supported by the driver:
> - reading multiple channels at the same time (the hardware has a FIFO
> buffer which stores multiple results)
> - continuous sampling (this would require a way to enable this
> individually because otherwise the ADC would be drawing power
> constantly)
> - interrupt support (similar to the vendor driver this new driver is
> polling the results. It is unclear if the IRQ-mode is supported on
> older (Meson6 or Meson8) hardware as well or if there are any errata)
>
> [0]
> http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
> [1] http://dn.odroid.com/S905/DataSheet/S905_Public_Datasheet_V1.1.4.pdf
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Very nice. One really minor comment inline, that I'd only bother
dealing with should you be rolling a V4 for some other reason.
I'll take this if Rob / Mark are happy with the device tree bindings.
Give me a bump if we see nothing from them in the next week or so (or if
I miss it!)
thanks
Jonathan
> ---
> drivers/iio/adc/Kconfig | 12 +
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/meson_saradc.c | 916 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 929 insertions(+)
> create mode 100644 drivers/iio/adc/meson_saradc.c
>
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index 9c8b558ba19e..86059b9b91bf 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -371,6 +371,18 @@ config MEN_Z188_ADC
> This driver can also be built as a module. If so, the module will be
> called men_z188_adc.
>
> +config MESON_SARADC
> + tristate "Amlogic Meson SAR ADC driver"
> + default ARCH_MESON
> + depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
> + select REGMAP_MMIO
> + help
> + Say yes here to build support for the SAR ADC found in Amlogic Meson
> + SoCs.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called meson_saradc.
> +
> config MXS_LRADC
> tristate "Freescale i.MX23/i.MX28 LRADC"
> depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
> index d36c4be8d1fc..de05b9e75f8f 100644
> --- a/drivers/iio/adc/Makefile
> +++ b/drivers/iio/adc/Makefile
> @@ -36,6 +36,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
> obj-$(CONFIG_MCP3422) += mcp3422.o
> obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
> obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
> +obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
> obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
> obj-$(CONFIG_NAU7802) += nau7802.o
> obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
> diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
> new file mode 100644
> index 000000000000..11a9686d2a9c
> --- /dev/null
> +++ b/drivers/iio/adc/meson_saradc.c
> @@ -0,0 +1,916 @@
> +/*
> + * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
> + *
> + * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/iio/iio.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/regulator/consumer.h>
> +
> +#define MESON_SAR_ADC_REG0 0x00
> + #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31)
> + #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
> + #define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30)
> + #define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29)
> + #define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
> + #define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27)
> + #define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26)
> + #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
> + #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
> + #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
> + #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
> + #define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14)
> + #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
> + #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
> + #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
> + #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
> + #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
> + #define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2)
> + #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
> + #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
> +
> +#define MESON_SAR_ADC_CHAN_LIST 0x04
> + #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
> + #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \
> + (GENMASK(2, 0) << ((_chan) * 3))
> +
> +#define MESON_SAR_ADC_AVG_CNTL 0x08
> + #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
> + (16 + ((_chan) * 2))
> + #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
> + (GENMASK(17, 16) << ((_chan) * 2))
> + #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
> + (0 + ((_chan) * 2))
> + #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
> + (GENMASK(1, 0) << ((_chan) * 2))
> +
> +#define MESON_SAR_ADC_REG3 0x0c
> + #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
> + #define MESON_SAR_ADC_REG3_CLK_EN BIT(30)
> + #define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
> + #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
> + #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
> + #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
> + #define MESON_SAR_ADC_REG3_DETECT_EN BIT(22)
> + #define MESON_SAR_ADC_REG3_ADC_EN BIT(21)
> + #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
> + #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
> + #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
> + #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
> + #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
> + #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
> +
> +#define MESON_SAR_ADC_DELAY 0x10
> + #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
> + #define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15)
> + #define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
> + #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
> + #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
> + #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
> +
> +#define MESON_SAR_ADC_LAST_RD 0x14
> + #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
> + #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
> +
> +#define MESON_SAR_ADC_FIFO_RD 0x18
> + #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
> + #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
> +
> +#define MESON_SAR_ADC_AUX_SW 0x1c
> + #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
> + (GENMASK(10, 8) << (((_chan) - 2) * 2))
> + #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
> + #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
> + #define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4)
> + #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
> + #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
> + #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
> + #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
> +
> +#define MESON_SAR_ADC_CHAN_10_SW 0x20
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
> + #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
> +
> +#define MESON_SAR_ADC_DETECT_IDLE_SW 0x24
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1)
> + #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0)
> +
> +#define MESON_SAR_ADC_DELTA_10 0x28
> + #define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
> + #define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
> + #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
> + #define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
> + #define MESON_SAR_ADC_DELTA_10_TS_C_SHIFT 11
> + #define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
> + #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
> + #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
> +
> +/*
> + * NOTE: registers from here are undocumented (the vendor Linux kernel driver
> + * and u-boot source served as reference). These only seem to be relevant on
> + * GXBB and newer.
> + */
> +#define MESON_SAR_ADC_REG11 0x2c
> + #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13)
> +
> +#define MESON_SAR_ADC_REG13 0x34
> + #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
> +
> +#define MESON_SAR_ADC_MAX_FIFO_SIZE 32
> +
> +#define MESON_SAR_ADC_CHAN(_chan) { \
> + .type = IIO_VOLTAGE, \
> + .indexed = 1, \
> + .channel = _chan, \
> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
> + BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
> + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
> + .datasheet_name = "SAR_ADC_CH"#_chan, \
> +}
> +
> +/*
> + * TODO: the hardware supports IIO_TEMP for channel 6 as well which is
> + * currently not supported by this driver.
> + */
> +static const struct iio_chan_spec meson_sar_adc_iio_channels[] = {
> + MESON_SAR_ADC_CHAN(0),
> + MESON_SAR_ADC_CHAN(1),
> + MESON_SAR_ADC_CHAN(2),
> + MESON_SAR_ADC_CHAN(3),
> + MESON_SAR_ADC_CHAN(4),
> + MESON_SAR_ADC_CHAN(5),
> + MESON_SAR_ADC_CHAN(6),
> + MESON_SAR_ADC_CHAN(7),
> + IIO_CHAN_SOFT_TIMESTAMP(8),
> +};
> +
> +enum meson_sar_adc_avg_mode {
> + NO_AVERAGING = 0x0,
> + MEAN_AVERAGING = 0x1,
> + MEDIAN_AVERAGING = 0x2,
> +};
> +
> +enum meson_sar_adc_num_samples {
> + ONE_SAMPLE = 0x0,
> + TWO_SAMPLES = 0x1,
> + FOUR_SAMPLES = 0x2,
> + EIGHT_SAMPLES = 0x3,
> +};
> +
> +enum meson_sar_adc_chan7_mux_sel {
> + CHAN7_MUX_VSS = 0x0,
> + CHAN7_MUX_VDD_DIV4 = 0x1,
> + CHAN7_MUX_VDD_DIV2 = 0x2,
> + CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
> + CHAN7_MUX_VDD = 0x4,
> + CHAN7_MUX_CH7_INPUT = 0x7,
> +};
> +
> +struct meson_sar_adc_data {
> + unsigned int resolution;
> + const char *name;
> +};
> +
> +struct meson_sar_adc_priv {
> + struct regmap *regmap;
> + struct regulator *vref;
> + const struct meson_sar_adc_data *data;
> + struct clk *clkin;
> + struct clk *core_clk;
> + struct clk *sana_clk;
> + struct clk *adc_sel_clk;
> + struct clk *adc_clk;
> + struct clk_gate clk_gate;
> + struct clk *adc_div_clk;
> + struct clk_divider clk_div;
> +};
> +
> +static const struct regmap_config meson_sar_adc_regmap_config = {
> + .reg_bits = 8,
> + .val_bits = 32,
> + .reg_stride = 4,
> + .max_register = MESON_SAR_ADC_REG13,
> +};
> +
> +static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + u32 regval;
> +
> + regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);
> +
> + return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
> +}
> +
> +static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int regval, timeout = 10000;
> +
> + /*
> + * NOTE: we need a small delay before reading the status, otherwise
> + * the sample engine may not have started internally (which would
> + * seem to us that sampling is already finished).
> + */
> + do {
> + udelay(1);
> + regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);
> + } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
> +
> + if (timeout < 0)
> + return -ETIMEDOUT;
> +
> + return 0;
> +}
> +
> +static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + int *val)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0;
> +
> + ret = meson_sar_adc_wait_busy_clear(indio_dev);
> + if (ret)
> + return ret;
> +
> + while (meson_sar_adc_get_fifo_count(indio_dev) > 0 &&
> + count < MESON_SAR_ADC_MAX_FIFO_SIZE) {
> + regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val);
> +
> + fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK,
> + regval);
> + if (fifo_chan != chan->channel)
> + continue;
> +
> + fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK,
> + regval);
> + fifo_val &= (BIT(priv->data->resolution) - 1);
> +
> + sum += fifo_val;
> + count++;
> + }
> +
> + if (!count)
> + return -ENOENT;
> +
> + *val = sum / count;
> +
> + return 0;
> +}
> +
> +static void meson_sar_adc_set_averaging(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + enum meson_sar_adc_avg_mode mode,
> + enum meson_sar_adc_num_samples samples)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int val, channel = chan->channel;
> +
> + val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(channel);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
> + MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(channel),
> + val);
> +
> + val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(channel);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
> + MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(channel), val);
> +}
> +
> +static void meson_sar_adc_enable_channel(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + u32 regval;
> +
> + /*
> + * the SAR ADC engine allows sampling multiple channels at the same
> + * time. to keep it simple we're only working with one *internal*
> + * channel, which starts counting at index 0 (which means: count = 1).
> + */
> + regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
> + MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
> +
> + /* map channel index 0 to the channel which we want to read */
> + regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0),
> + chan->channel);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
> + MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval);
> +
> + regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
> + chan->channel);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
> + MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
> + regval);
> +
> + regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
> + chan->channel);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
> + MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
> + regval);
> +
> + if (chan->channel == 6)
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
> + MESON_SAR_ADC_DELTA_10_TEMP_SEL, 0);
> +}
> +
> +static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev,
> + enum meson_sar_adc_chan7_mux_sel sel)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + u32 regval;
> +
> + regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
> + MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
> +
> + usleep_range(10, 20);
> +}
> +
> +static void meson_sar_adc_start_sample_engine(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
> + MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
> + MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
> + MESON_SAR_ADC_REG0_SAMPLING_START,
> + MESON_SAR_ADC_REG0_SAMPLING_START);
> +}
> +
> +static void meson_sar_adc_stop_sample_engine(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
> + MESON_SAR_ADC_REG0_SAMPLING_STOP,
> + MESON_SAR_ADC_REG0_SAMPLING_STOP);
> +
> + /* wait until all modules are stopped */
> + meson_sar_adc_wait_busy_clear(indio_dev);
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
> + MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
> +}
> +
> +static int meson_sar_adc_lock(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int val, timeout = 10000;
> +
> + mutex_lock(&indio_dev->mlock);
> +
> + /* prevent BL30 from using the SAR ADC while we are using it */
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
> + MESON_SAR_ADC_DELAY_KERNEL_BUSY,
> + MESON_SAR_ADC_DELAY_KERNEL_BUSY);
> +
> + /* wait until BL30 releases it's lock (so we can use the SAR ADC) */
> + do {
> + udelay(1);
> + regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val);
> + } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--);
> +
> + if (timeout < 0)
> + return -ETIMEDOUT;
> +
> + return 0;
> +}
> +
> +static void meson_sar_adc_unlock(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> +
> + /* allow BL30 to use the SAR ADC again */
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
> + MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0);
> +
> + mutex_unlock(&indio_dev->mlock);
> +}
> +
> +static void meson_sar_adc_clear_fifo(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int count;
> +
> + for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {
> + if (!meson_sar_adc_get_fifo_count(indio_dev))
> + break;
> +
> + regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, 0);
> + }
> +}
> +
> +static int meson_sar_adc_get_sample(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + enum meson_sar_adc_avg_mode avg_mode,
> + enum meson_sar_adc_num_samples avg_samples,
> + int *val)
> +{
> + int ret;
> +
> + ret = meson_sar_adc_lock(indio_dev);
> + if (ret)
> + return ret;
> +
> + /* clear the FIFO to make sure we're not reading old values */
> + meson_sar_adc_clear_fifo(indio_dev);
> +
> + meson_sar_adc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
> +
> + meson_sar_adc_enable_channel(indio_dev, chan);
> +
> + meson_sar_adc_start_sample_engine(indio_dev);
> + ret = meson_sar_adc_read_raw_sample(indio_dev, chan, val);
> + meson_sar_adc_stop_sample_engine(indio_dev);
> +
> + meson_sar_adc_unlock(indio_dev);
> +
> + if (ret) {
> + dev_warn(indio_dev->dev.parent,
> + "failed to read sample for channel %d: %d\n",
> + chan->channel, ret);
> + return ret;
> + }
> +
> + return IIO_VAL_INT;
> +}
> +
> +static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + int *val, int *val2, long mask)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int ret;
> +
> + switch (mask) {
> + case IIO_CHAN_INFO_RAW:
> + return meson_sar_adc_get_sample(indio_dev, chan, NO_AVERAGING,
> + ONE_SAMPLE, val);
> + break;
> +
> + case IIO_CHAN_INFO_AVERAGE_RAW:
> + return meson_sar_adc_get_sample(indio_dev, chan,
> + MEAN_AVERAGING, EIGHT_SAMPLES,
> + val);
> + break;
> +
> + case IIO_CHAN_INFO_SCALE:
> + ret = regulator_get_voltage(priv->vref);
> + if (ret < 0) {
> + dev_err(indio_dev->dev.parent,
> + "failed to get vref voltage: %d\n", ret);
> + return ret;
> + }
> +
> + *val = ret / 1000;
> + *val2 = priv->data->resolution;
> + return IIO_VAL_FRACTIONAL_LOG2;
> +
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static int meson_sar_adc_clk_init(struct iio_dev *indio_dev,
> + void __iomem *base)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + struct clk_init_data init;
> + const char *clk_parents[1];
> +
> + init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_div",
> + of_node_full_name(indio_dev->dev.of_node));
> + init.flags = 0;
> + init.ops = &clk_divider_ops;
> + clk_parents[0] = __clk_get_name(priv->clkin);
> + init.parent_names = clk_parents;
> + init.num_parents = 1;
> +
> + priv->clk_div.reg = base + MESON_SAR_ADC_REG3;
> + priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
> + priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
> + priv->clk_div.hw.init = &init;
> + priv->clk_div.flags = 0;
> +
> + priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
> + &priv->clk_div.hw);
> + if (WARN_ON(IS_ERR(priv->adc_div_clk)))
> + return PTR_ERR(priv->adc_div_clk);
> +
> + init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_en",
> + of_node_full_name(indio_dev->dev.of_node));
> + init.flags = CLK_SET_RATE_PARENT;
> + init.ops = &clk_gate_ops;
> + clk_parents[0] = __clk_get_name(priv->adc_div_clk);
> + init.parent_names = clk_parents;
> + init.num_parents = 1;
> +
> + priv->clk_gate.reg = base + MESON_SAR_ADC_REG3;
> + priv->clk_gate.bit_idx = fls(MESON_SAR_ADC_REG3_CLK_EN);
> + priv->clk_gate.hw.init = &init;
> +
> + priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
> + if (WARN_ON(IS_ERR(priv->adc_clk)))
> + return PTR_ERR(priv->adc_clk);
> +
> + return 0;
> +}
> +
> +static int meson_sar_adc_init(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int regval, ret;
> +
> + /*
> + * make sure we start at CH7 input since the other muxes are only used
> + * for internal calibration.
> + */
> + meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
> +
> + /*
> + * leave sampling delay and the input clocks as configured by BL30 to
> + * make sure BL30 gets the values it expects when reading the
> + * temperature sensor.
> + */
> + regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val);
> + if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED)
> + return 0;
> +
> + meson_sar_adc_stop_sample_engine(indio_dev);
> +
> + /* update the channel 6 MUX to select the temperature sensor */
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
> + MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
> + MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
> +
> + /* disable all channels by default */
> + regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
> + MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
> + MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY,
> + MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY);
> +
> + /* delay between two samples = (10+1) * 1uS */
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
> + MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
> + FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,
> + 10));
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
> + MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
> + FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
> + 0));
> +
> + /* delay between two samples = (10+1) * 1uS */
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
> + MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
> + FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
> + 10));
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
> + MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
> + FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
> + 1));
> +
> + ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
> + if (ret) {
> + dev_err(indio_dev->dev.parent,
> + "failed to set adc parent to clkin\n");
> + return ret;
> + }
> +
> + ret = clk_set_rate(priv->adc_clk, 1200000);
> + if (ret) {
> + dev_err(indio_dev->dev.parent,
> + "failed to set adc clock rate\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int ret;
> +
> + ret = meson_sar_adc_lock(indio_dev);
> + if (ret)
> + goto err_lock;
> +
> + ret = regulator_enable(priv->vref);
> + if (ret < 0) {
> + dev_err(indio_dev->dev.parent,
> + "failed to enable vref regulator\n");
> + goto err_vref;
> + }
> +
> + ret = clk_prepare_enable(priv->core_clk);
> + if (ret) {
> + dev_err(indio_dev->dev.parent, "failed to enable core clk\n");
> + goto err_core_clk;
> + }
> +
> + ret = clk_prepare_enable(priv->sana_clk);
> + if (ret) {
> + dev_err(indio_dev->dev.parent, "failed to enable sana clk\n");
> + goto err_sana_clk;
> + }
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
> + MESON_SAR_ADC_REG11_BANDGAP_EN,
> + MESON_SAR_ADC_REG11_BANDGAP_EN);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
> + MESON_SAR_ADC_REG3_ADC_EN,
> + MESON_SAR_ADC_REG3_ADC_EN);
> +
> + udelay(5);
> +
> + ret = clk_prepare_enable(priv->adc_clk);
> + if (ret) {
> + dev_err(indio_dev->dev.parent, "failed to enable adc clk\n");
> + goto err_adc_clk;
> + }
> +
> + meson_sar_adc_unlock(indio_dev);
> +
> + return 0;
> +
> +err_adc_clk:
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
> + MESON_SAR_ADC_REG3_ADC_EN, 0);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
> + MESON_SAR_ADC_REG11_BANDGAP_EN, 0);
> + clk_disable_unprepare(priv->sana_clk);
> +err_sana_clk:
> + clk_disable_unprepare(priv->core_clk);
> +err_core_clk:
> + regulator_disable(priv->vref);
> +err_vref:
> + meson_sar_adc_unlock(indio_dev);
> +err_lock:
> + return ret;
> +}
> +
> +static int meson_sar_adc_hw_disable(struct iio_dev *indio_dev)
> +{
> + struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
> + int ret;
> +
> + ret = meson_sar_adc_lock(indio_dev);
> + if (ret)
> + return ret;
> +
> + clk_disable_unprepare(priv->adc_clk);
> +
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
> + MESON_SAR_ADC_REG3_ADC_EN, 0);
> + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
> + MESON_SAR_ADC_REG11_BANDGAP_EN, 0);
> +
> + clk_disable_unprepare(priv->sana_clk);
> + clk_disable_unprepare(priv->core_clk);
> +
> + regulator_disable(priv->vref);
> +
> + meson_sar_adc_unlock(indio_dev);
> +
> + return 0;
> +}
> +
> +static const struct iio_info meson_sar_adc_iio_info = {
> + .read_raw = meson_sar_adc_iio_info_read_raw,
> + .driver_module = THIS_MODULE,
> +};
> +
> +struct meson_sar_adc_data meson_sar_adc_gxbb_data = {
> + .resolution = 10,
> + .name = "meson-gxbb-saradc",
> +};
> +
> +struct meson_sar_adc_data meson_sar_adc_gxl_data = {
> + .resolution = 12,
> + .name = "meson-gxl-saradc",
> +};
> +
> +static const struct of_device_id meson_sar_adc_of_match[] = {
> + {
> + .compatible = "amlogic,meson-gxbb-saradc",
> + .data = &meson_sar_adc_gxbb_data,
> + }, {
> + .compatible = "amlogic,meson-gxl-saradc",
> + .data = &meson_sar_adc_gxl_data,
> + },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, meson_sar_adc_of_match);
> +
> +static int meson_sar_adc_probe(struct platform_device *pdev)
> +{
> + struct meson_sar_adc_priv *priv;
> + struct iio_dev *indio_dev;
> + struct resource *res;
> + void __iomem *base;
> + const struct of_device_id *match;
> + int ret;
> +
> + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
> + if (!indio_dev) {
> + dev_err(&pdev->dev, "failed allocating iio device\n");
> + return -ENOMEM;
> + }
> +
> + priv = iio_priv(indio_dev);
> +
> + match = of_match_device(meson_sar_adc_of_match, &pdev->dev);
> + priv->data = match->data;
> +
> + indio_dev->name = priv->data->name;
> + indio_dev->dev.parent = &pdev->dev;
> + indio_dev->dev.of_node = pdev->dev.of_node;
> + indio_dev->modes = INDIO_DIRECT_MODE;
> + indio_dev->info = &meson_sar_adc_iio_info;
> +
> + indio_dev->channels = meson_sar_adc_iio_channels;
> + indio_dev->num_channels = ARRAY_SIZE(meson_sar_adc_iio_channels);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
> + &meson_sar_adc_regmap_config);
> + if (IS_ERR(priv->regmap))
> + return PTR_ERR(priv->regmap);
> +
> + priv->clkin = devm_clk_get(&pdev->dev, "clkin");
> + if (IS_ERR(priv->clkin)) {
> + dev_err(&pdev->dev, "failed to get clkin\n");
> + return PTR_ERR(priv->clkin);
> + }
> +
> + priv->core_clk = devm_clk_get(&pdev->dev, "core");
> + if (IS_ERR(priv->core_clk)) {
> + dev_err(&pdev->dev, "failed to get core clk\n");
> + return PTR_ERR(priv->core_clk);
> + }
> +
> + priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
> + if (IS_ERR(priv->sana_clk)) {
> + if (PTR_ERR(priv->sana_clk) == -ENOENT) {
> + priv->sana_clk = NULL;
> + } else {
> + dev_err(&pdev->dev, "failed to get sana clk\n");
> + return PTR_ERR(priv->sana_clk);
> + }
> + }
> +
> + priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
> + if (IS_ERR(priv->adc_clk)) {
> + if (PTR_ERR(priv->adc_clk) == -ENOENT) {
> + priv->adc_clk = NULL;
> + } else {
> + dev_err(&pdev->dev, "failed to get adc clk\n");
> + return PTR_ERR(priv->adc_clk);
> + }
> + }
> +
> + priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
> + if (IS_ERR(priv->adc_sel_clk)) {
> + if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
> + priv->adc_sel_clk = NULL;
> + } else {
> + dev_err(&pdev->dev, "failed to get adc_sel clk\n");
> + return PTR_ERR(priv->adc_sel_clk);
> + }
> + }
> +
> + /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
> + if (!priv->adc_clk) {
> + ret = meson_sar_adc_clk_init(indio_dev, base);
> + if (ret)
> + return ret;
> + }
> +
> + priv->vref = devm_regulator_get(&pdev->dev, "vref");
> + if (IS_ERR(priv->vref)) {
> + dev_err(&pdev->dev, "failed to get vref regulator\n");
> + return PTR_ERR(priv->vref);
> + }
> +
> + ret = meson_sar_adc_init(indio_dev);
> + if (ret)
> + goto err;
> +
> + ret = meson_sar_adc_hw_enable(indio_dev);
> + if (ret)
> + goto err;
> +
> + platform_set_drvdata(pdev, indio_dev);
> +
> + ret = iio_device_register(indio_dev);
> + if (ret)
> + goto err_hw;
> +
> + return 0;
> +
> +err_hw:
> + meson_sar_adc_hw_disable(indio_dev);
> +err:
> + return ret;
> +}
> +
> +static int meson_sar_adc_remove(struct platform_device *pdev)
> +{
> + struct iio_dev *indio_dev = platform_get_drvdata(pdev);
> +
> + iio_device_unregister(indio_dev);
> +
> + return meson_sar_adc_hw_disable(indio_dev);
> +}
> +
> +#ifdef CONFIG_PM_SLEEP
Slight perference for not bothing with the if def fun which
can go wrong, but instead use __maybe_unused.
Arnd is busy pushing this into lots of drivers and I think it
is neater.
I don't care about this enough to insist on a respin if it's all
that anyone comes up with.
> +static int meson_sar_adc_suspend(struct device *dev)
> +{
> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
> +
> + return meson_sar_adc_hw_disable(indio_dev);
> +}
> +
> +static int meson_sar_adc_resume(struct device *dev)
> +{
> + struct iio_dev *indio_dev = dev_get_drvdata(dev);
> +
> + return meson_sar_adc_hw_enable(indio_dev);
> +}
> +#endif /* CONFIG_PM_SLEEP */
> +
> +static SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops,
> + meson_sar_adc_suspend, meson_sar_adc_resume);
> +
> +static struct platform_driver meson_sar_adc_driver = {
> + .probe = meson_sar_adc_probe,
> + .remove = meson_sar_adc_remove,
> + .driver = {
> + .name = "meson-saradc",
> + .of_match_table = meson_sar_adc_of_match,
> + .pm = &meson_sar_adc_pm_ops,
> + },
> +};
> +
> +module_platform_driver(meson_sar_adc_driver);
> +
> +MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
> +MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
> +MODULE_LICENSE("GPL v2");
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v3 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
2017-01-19 14:58 ` Martin Blumenstingl
(?)
@ 2017-01-21 13:21 ` Andreas Färber
-1 siblings, 0 replies; 110+ messages in thread
From: Andreas Färber @ 2017-01-21 13:21 UTC (permalink / raw)
To: Martin Blumenstingl, jic23, knaack.h, lars, pmeerw, robh+dt,
mark.rutland, khilman, linux-iio, devicetree, linux-amlogic,
linux-clk
Cc: narmstrong, catalin.marinas, mturquette, will.deacon, carlo,
sboyd, linux-arm-kernel
Am 19.01.2017 um 15:58 schrieb Martin Blumenstingl:
> This adds the devicetree binding documentation for the SAR ADC found in
> Amlogic Meson SoCs.
> Currently only the GXBB, GXL and GXM SoCs are supported.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Regards,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v3 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
@ 2017-01-21 13:21 ` Andreas Färber
0 siblings, 0 replies; 110+ messages in thread
From: Andreas Färber @ 2017-01-21 13:21 UTC (permalink / raw)
To: linux-arm-kernel
Am 19.01.2017 um 15:58 schrieb Martin Blumenstingl:
> This adds the devicetree binding documentation for the SAR ADC found in
> Amlogic Meson SoCs.
> Currently only the GXBB, GXL and GXM SoCs are supported.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Andreas F?rber <afaerber@suse.de>
Regards,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany
GF: Felix Imend?rffer, Jane Smithard, Graham Norton
HRB 21284 (AG N?rnberg)
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v3 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
@ 2017-01-21 13:21 ` Andreas Färber
0 siblings, 0 replies; 110+ messages in thread
From: Andreas Färber @ 2017-01-21 13:21 UTC (permalink / raw)
To: linus-amlogic
Am 19.01.2017 um 15:58 schrieb Martin Blumenstingl:
> This adds the devicetree binding documentation for the SAR ADC found in
> Amlogic Meson SoCs.
> Currently only the GXBB, GXL and GXM SoCs are supported.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Andreas F?rber <afaerber@suse.de>
Regards,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany
GF: Felix Imend?rffer, Jane Smithard, Graham Norton
HRB 21284 (AG N?rnberg)
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v3 4/4] ARM64: dts: meson: meson-gx: add the SAR ADC
2017-01-19 14:58 ` Martin Blumenstingl
(?)
@ 2017-01-21 13:28 ` Andreas Färber
-1 siblings, 0 replies; 110+ messages in thread
From: Andreas Färber @ 2017-01-21 13:28 UTC (permalink / raw)
To: Martin Blumenstingl, jic23, knaack.h, lars, pmeerw, robh+dt,
mark.rutland, khilman, linux-iio, devicetree, linux-amlogic,
linux-clk
Cc: narmstrong, catalin.marinas, mturquette, will.deacon, carlo,
sboyd, linux-arm-kernel
Am 19.01.2017 um 15:58 schrieb Martin Blumenstingl:
> Add the SAR ADC to meson-gxbb.dtsi and meson-gxl.dtsi. GXBB provides a
> 10-bit ADC while GXL (and GXM, which uses the same ADC as GXL) provides
> a 12-bit ADC.
> Some boards use resistor ladder buttons connected through one of the ADC
> channels. On newer devices (GXL and GXM) some boards use pull-ups/downs
> to change the resistance (and thus the ADC value) on of the ADC channels
"on one of"?
> to indicate the board revision.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 ++++++++
> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 ++++++++++
> arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 ++++++++++
> 3 files changed, 28 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> index 99e6a8d5cb9e..55abfb74aab2 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> @@ -255,6 +255,14 @@
> status = "disabled";
> };
>
> + saradc: adc@8680 {
> + compatible = "amlogic,meson-saradc";
> + #io-channel-cells = <1>;
Personally I think it makes more sense to keep reg after compatible for
consistency (same in example) and any #... "output" properties last.
> + status = "disabled";
> + reg = <0x0 0x8680 0x0 0x34>;
> + interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
> + };
> +
> pwm_ef: pwm@86c0 {
> compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
> reg = <0x0 0x086c0 0x0 0x10>;
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> index 39a774ad83ce..04b3324bc132 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> @@ -490,6 +490,16 @@
> clocks = <&clkc CLKID_I2C>;
> };
>
> +&saradc {
> + compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
> + clocks = <&xtal>,
> + <&clkc CLKID_SAR_ADC>,
> + <&clkc CLKID_SANA>,
> + <&clkc CLKID_SAR_ADC_CLK>,
> + <&clkc CLKID_SAR_ADC_SEL>;
> + clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
> +};
> +
> &sd_emmc_a {
> clocks = <&clkc CLKID_SD_EMMC_A>,
> <&xtal>,
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
> index bdf2305a2e25..7c72dbcef1ba 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
> @@ -340,6 +340,16 @@
> clocks = <&clkc CLKID_I2C>;
> };
>
> +&saradc {
> + compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
> + clocks = <&xtal>,
> + <&clkc CLKID_SAR_ADC>,
> + <&clkc CLKID_SANA>,
> + <&clkc CLKID_SAR_ADC_CLK>,
> + <&clkc CLKID_SAR_ADC_SEL>;
> + clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
> +};
> +
> &sd_emmc_a {
> clocks = <&clkc CLKID_SD_EMMC_A>,
> <&xtal>,
Anyway, saradc before sd_emmc_a looks fine,
Reviewed-by: Andreas Färber <afaerber@suse.de>
Regards,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v3 4/4] ARM64: dts: meson: meson-gx: add the SAR ADC
@ 2017-01-21 13:28 ` Andreas Färber
0 siblings, 0 replies; 110+ messages in thread
From: Andreas Färber @ 2017-01-21 13:28 UTC (permalink / raw)
To: linux-arm-kernel
Am 19.01.2017 um 15:58 schrieb Martin Blumenstingl:
> Add the SAR ADC to meson-gxbb.dtsi and meson-gxl.dtsi. GXBB provides a
> 10-bit ADC while GXL (and GXM, which uses the same ADC as GXL) provides
> a 12-bit ADC.
> Some boards use resistor ladder buttons connected through one of the ADC
> channels. On newer devices (GXL and GXM) some boards use pull-ups/downs
> to change the resistance (and thus the ADC value) on of the ADC channels
"on one of"?
> to indicate the board revision.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 ++++++++
> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 ++++++++++
> arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 ++++++++++
> 3 files changed, 28 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> index 99e6a8d5cb9e..55abfb74aab2 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> @@ -255,6 +255,14 @@
> status = "disabled";
> };
>
> + saradc: adc at 8680 {
> + compatible = "amlogic,meson-saradc";
> + #io-channel-cells = <1>;
Personally I think it makes more sense to keep reg after compatible for
consistency (same in example) and any #... "output" properties last.
> + status = "disabled";
> + reg = <0x0 0x8680 0x0 0x34>;
> + interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
> + };
> +
> pwm_ef: pwm at 86c0 {
> compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
> reg = <0x0 0x086c0 0x0 0x10>;
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> index 39a774ad83ce..04b3324bc132 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> @@ -490,6 +490,16 @@
> clocks = <&clkc CLKID_I2C>;
> };
>
> +&saradc {
> + compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
> + clocks = <&xtal>,
> + <&clkc CLKID_SAR_ADC>,
> + <&clkc CLKID_SANA>,
> + <&clkc CLKID_SAR_ADC_CLK>,
> + <&clkc CLKID_SAR_ADC_SEL>;
> + clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
> +};
> +
> &sd_emmc_a {
> clocks = <&clkc CLKID_SD_EMMC_A>,
> <&xtal>,
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
> index bdf2305a2e25..7c72dbcef1ba 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
> @@ -340,6 +340,16 @@
> clocks = <&clkc CLKID_I2C>;
> };
>
> +&saradc {
> + compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
> + clocks = <&xtal>,
> + <&clkc CLKID_SAR_ADC>,
> + <&clkc CLKID_SANA>,
> + <&clkc CLKID_SAR_ADC_CLK>,
> + <&clkc CLKID_SAR_ADC_SEL>;
> + clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
> +};
> +
> &sd_emmc_a {
> clocks = <&clkc CLKID_SD_EMMC_A>,
> <&xtal>,
Anyway, saradc before sd_emmc_a looks fine,
Reviewed-by: Andreas F?rber <afaerber@suse.de>
Regards,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany
GF: Felix Imend?rffer, Jane Smithard, Graham Norton
HRB 21284 (AG N?rnberg)
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v3 4/4] ARM64: dts: meson: meson-gx: add the SAR ADC
@ 2017-01-21 13:28 ` Andreas Färber
0 siblings, 0 replies; 110+ messages in thread
From: Andreas Färber @ 2017-01-21 13:28 UTC (permalink / raw)
To: linus-amlogic
Am 19.01.2017 um 15:58 schrieb Martin Blumenstingl:
> Add the SAR ADC to meson-gxbb.dtsi and meson-gxl.dtsi. GXBB provides a
> 10-bit ADC while GXL (and GXM, which uses the same ADC as GXL) provides
> a 12-bit ADC.
> Some boards use resistor ladder buttons connected through one of the ADC
> channels. On newer devices (GXL and GXM) some boards use pull-ups/downs
> to change the resistance (and thus the ADC value) on of the ADC channels
"on one of"?
> to indicate the board revision.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 ++++++++
> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 ++++++++++
> arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 ++++++++++
> 3 files changed, 28 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> index 99e6a8d5cb9e..55abfb74aab2 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> @@ -255,6 +255,14 @@
> status = "disabled";
> };
>
> + saradc: adc at 8680 {
> + compatible = "amlogic,meson-saradc";
> + #io-channel-cells = <1>;
Personally I think it makes more sense to keep reg after compatible for
consistency (same in example) and any #... "output" properties last.
> + status = "disabled";
> + reg = <0x0 0x8680 0x0 0x34>;
> + interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
> + };
> +
> pwm_ef: pwm at 86c0 {
> compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
> reg = <0x0 0x086c0 0x0 0x10>;
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> index 39a774ad83ce..04b3324bc132 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> @@ -490,6 +490,16 @@
> clocks = <&clkc CLKID_I2C>;
> };
>
> +&saradc {
> + compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
> + clocks = <&xtal>,
> + <&clkc CLKID_SAR_ADC>,
> + <&clkc CLKID_SANA>,
> + <&clkc CLKID_SAR_ADC_CLK>,
> + <&clkc CLKID_SAR_ADC_SEL>;
> + clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
> +};
> +
> &sd_emmc_a {
> clocks = <&clkc CLKID_SD_EMMC_A>,
> <&xtal>,
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
> index bdf2305a2e25..7c72dbcef1ba 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
> @@ -340,6 +340,16 @@
> clocks = <&clkc CLKID_I2C>;
> };
>
> +&saradc {
> + compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
> + clocks = <&xtal>,
> + <&clkc CLKID_SAR_ADC>,
> + <&clkc CLKID_SANA>,
> + <&clkc CLKID_SAR_ADC_CLK>,
> + <&clkc CLKID_SAR_ADC_SEL>;
> + clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
> +};
> +
> &sd_emmc_a {
> clocks = <&clkc CLKID_SD_EMMC_A>,
> <&xtal>,
Anyway, saradc before sd_emmc_a looks fine,
Reviewed-by: Andreas F?rber <afaerber@suse.de>
Regards,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany
GF: Felix Imend?rffer, Jane Smithard, Graham Norton
HRB 21284 (AG N?rnberg)
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v3 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
2017-01-19 14:58 ` Martin Blumenstingl
(?)
(?)
@ 2017-01-21 20:56 ` Rob Herring
-1 siblings, 0 replies; 110+ messages in thread
From: Rob Herring @ 2017-01-21 20:56 UTC (permalink / raw)
To: Martin Blumenstingl
Cc: mark.rutland, devicetree, sboyd, lars, catalin.marinas,
narmstrong, linux-iio, khilman, mturquette, will.deacon,
linux-arm-kernel, pmeerw, knaack.h, carlo, linux-amlogic,
linux-clk, jic23
On Thu, Jan 19, 2017 at 03:58:19PM +0100, Martin Blumenstingl wrote:
> This adds the devicetree binding documentation for the SAR ADC found in
> Amlogic Meson SoCs.
> Currently only the GXBB, GXL and GXM SoCs are supported.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> .../bindings/iio/adc/amlogic,meson-saradc.txt | 31 ++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
> new file mode 100644
> index 000000000000..9a0bec7afc63
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
> @@ -0,0 +1,31 @@
> +* Amlogic Meson SAR (Successive Approximation Register) A/D converter
> +
> +Required properties:
> +- compatible: depending on the SoC this should be one of:
> + - "amlogic,meson-gxbb-saradc" for GXBB
> + - "amlogic,meson-gxl-saradc" for GXL and GXM
GXL and GXM should probably be 2 compatibles.
> + along with the generic "amlogic,meson-saradc"
> +- reg: the physical base address and length of the registers
> +- clocks: phandle and clock identifier (see clock-names)
> +- clock-names: mandatory clocks:
> + - "clkin" for the reference clock (typically XTAL)
> + - "core" for the SAR ADC core clock
> + optional clocks:
> + - "sana" for the analog clock
> + - "adc_clk" for the ADC (sampling) clock
> + - "adc_sel" for the ADC (sampling) clock mux
> +- vref-supply: the regulator supply for the ADC reference voltage
> +- #io-channel-cells: must be 1, see ../iio-bindings.txt
> +
> +Example:
> + saradc: adc@8680 {
> + compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
> + #io-channel-cells = <1>;
> + reg = <0x0 0x8680 0x0 0x34>;
> + clocks = <&xtal>,
> + <&clkc CLKID_SAR_ADC>,
> + <&clkc CLKID_SANA>,
> + <&clkc CLKID_SAR_ADC_CLK>,
> + <&clkc CLKID_SAR_ADC_SEL>;
> + clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
> + };
> --
> 2.11.0
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v3 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
@ 2017-01-21 20:56 ` Rob Herring
0 siblings, 0 replies; 110+ messages in thread
From: Rob Herring @ 2017-01-21 20:56 UTC (permalink / raw)
To: Martin Blumenstingl
Cc: jic23, knaack.h, lars, pmeerw, mark.rutland, khilman, linux-iio,
devicetree, linux-amlogic, linux-clk, carlo, catalin.marinas,
will.deacon, mturquette, sboyd, narmstrong, linux-arm-kernel
On Thu, Jan 19, 2017 at 03:58:19PM +0100, Martin Blumenstingl wrote:
> This adds the devicetree binding documentation for the SAR ADC found in
> Amlogic Meson SoCs.
> Currently only the GXBB, GXL and GXM SoCs are supported.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> .../bindings/iio/adc/amlogic,meson-saradc.txt | 31 ++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
> new file mode 100644
> index 000000000000..9a0bec7afc63
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
> @@ -0,0 +1,31 @@
> +* Amlogic Meson SAR (Successive Approximation Register) A/D converter
> +
> +Required properties:
> +- compatible: depending on the SoC this should be one of:
> + - "amlogic,meson-gxbb-saradc" for GXBB
> + - "amlogic,meson-gxl-saradc" for GXL and GXM
GXL and GXM should probably be 2 compatibles.
> + along with the generic "amlogic,meson-saradc"
> +- reg: the physical base address and length of the registers
> +- clocks: phandle and clock identifier (see clock-names)
> +- clock-names: mandatory clocks:
> + - "clkin" for the reference clock (typically XTAL)
> + - "core" for the SAR ADC core clock
> + optional clocks:
> + - "sana" for the analog clock
> + - "adc_clk" for the ADC (sampling) clock
> + - "adc_sel" for the ADC (sampling) clock mux
> +- vref-supply: the regulator supply for the ADC reference voltage
> +- #io-channel-cells: must be 1, see ../iio-bindings.txt
> +
> +Example:
> + saradc: adc@8680 {
> + compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
> + #io-channel-cells = <1>;
> + reg = <0x0 0x8680 0x0 0x34>;
> + clocks = <&xtal>,
> + <&clkc CLKID_SAR_ADC>,
> + <&clkc CLKID_SANA>,
> + <&clkc CLKID_SAR_ADC_CLK>,
> + <&clkc CLKID_SAR_ADC_SEL>;
> + clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
> + };
> --
> 2.11.0
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v3 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
@ 2017-01-21 20:56 ` Rob Herring
0 siblings, 0 replies; 110+ messages in thread
From: Rob Herring @ 2017-01-21 20:56 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jan 19, 2017 at 03:58:19PM +0100, Martin Blumenstingl wrote:
> This adds the devicetree binding documentation for the SAR ADC found in
> Amlogic Meson SoCs.
> Currently only the GXBB, GXL and GXM SoCs are supported.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> .../bindings/iio/adc/amlogic,meson-saradc.txt | 31 ++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
> new file mode 100644
> index 000000000000..9a0bec7afc63
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
> @@ -0,0 +1,31 @@
> +* Amlogic Meson SAR (Successive Approximation Register) A/D converter
> +
> +Required properties:
> +- compatible: depending on the SoC this should be one of:
> + - "amlogic,meson-gxbb-saradc" for GXBB
> + - "amlogic,meson-gxl-saradc" for GXL and GXM
GXL and GXM should probably be 2 compatibles.
> + along with the generic "amlogic,meson-saradc"
> +- reg: the physical base address and length of the registers
> +- clocks: phandle and clock identifier (see clock-names)
> +- clock-names: mandatory clocks:
> + - "clkin" for the reference clock (typically XTAL)
> + - "core" for the SAR ADC core clock
> + optional clocks:
> + - "sana" for the analog clock
> + - "adc_clk" for the ADC (sampling) clock
> + - "adc_sel" for the ADC (sampling) clock mux
> +- vref-supply: the regulator supply for the ADC reference voltage
> +- #io-channel-cells: must be 1, see ../iio-bindings.txt
> +
> +Example:
> + saradc: adc at 8680 {
> + compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
> + #io-channel-cells = <1>;
> + reg = <0x0 0x8680 0x0 0x34>;
> + clocks = <&xtal>,
> + <&clkc CLKID_SAR_ADC>,
> + <&clkc CLKID_SANA>,
> + <&clkc CLKID_SAR_ADC_CLK>,
> + <&clkc CLKID_SAR_ADC_SEL>;
> + clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
> + };
> --
> 2.11.0
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v3 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
@ 2017-01-21 20:56 ` Rob Herring
0 siblings, 0 replies; 110+ messages in thread
From: Rob Herring @ 2017-01-21 20:56 UTC (permalink / raw)
To: linus-amlogic
On Thu, Jan 19, 2017 at 03:58:19PM +0100, Martin Blumenstingl wrote:
> This adds the devicetree binding documentation for the SAR ADC found in
> Amlogic Meson SoCs.
> Currently only the GXBB, GXL and GXM SoCs are supported.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> .../bindings/iio/adc/amlogic,meson-saradc.txt | 31 ++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
> new file mode 100644
> index 000000000000..9a0bec7afc63
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
> @@ -0,0 +1,31 @@
> +* Amlogic Meson SAR (Successive Approximation Register) A/D converter
> +
> +Required properties:
> +- compatible: depending on the SoC this should be one of:
> + - "amlogic,meson-gxbb-saradc" for GXBB
> + - "amlogic,meson-gxl-saradc" for GXL and GXM
GXL and GXM should probably be 2 compatibles.
> + along with the generic "amlogic,meson-saradc"
> +- reg: the physical base address and length of the registers
> +- clocks: phandle and clock identifier (see clock-names)
> +- clock-names: mandatory clocks:
> + - "clkin" for the reference clock (typically XTAL)
> + - "core" for the SAR ADC core clock
> + optional clocks:
> + - "sana" for the analog clock
> + - "adc_clk" for the ADC (sampling) clock
> + - "adc_sel" for the ADC (sampling) clock mux
> +- vref-supply: the regulator supply for the ADC reference voltage
> +- #io-channel-cells: must be 1, see ../iio-bindings.txt
> +
> +Example:
> + saradc: adc at 8680 {
> + compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
> + #io-channel-cells = <1>;
> + reg = <0x0 0x8680 0x0 0x34>;
> + clocks = <&xtal>,
> + <&clkc CLKID_SAR_ADC>,
> + <&clkc CLKID_SANA>,
> + <&clkc CLKID_SAR_ADC_CLK>,
> + <&clkc CLKID_SAR_ADC_SEL>;
> + clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
> + };
> --
> 2.11.0
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v3 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
2017-01-21 20:56 ` Rob Herring
(?)
@ 2017-01-21 23:10 ` Martin Blumenstingl
-1 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-21 23:10 UTC (permalink / raw)
To: Rob Herring
Cc: jic23, knaack.h, lars, pmeerw, mark.rutland, khilman, linux-iio,
devicetree, linux-amlogic, linux-clk, carlo, catalin.marinas,
will.deacon, mturquette, sboyd, narmstrong, linux-arm-kernel
Hi Rob,
thanks for reviewing this!
On Sat, Jan 21, 2017 at 9:56 PM, Rob Herring <robh@kernel.org> wrote:
> On Thu, Jan 19, 2017 at 03:58:19PM +0100, Martin Blumenstingl wrote:
>> This adds the devicetree binding documentation for the SAR ADC found in
>> Amlogic Meson SoCs.
>> Currently only the GXBB, GXL and GXM SoCs are supported.
>>
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
>> ---
>> .../bindings/iio/adc/amlogic,meson-saradc.txt | 31 ++++++++++++++++++++++
>> 1 file changed, 31 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
>>
>> diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
>> new file mode 100644
>> index 000000000000..9a0bec7afc63
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
>> @@ -0,0 +1,31 @@
>> +* Amlogic Meson SAR (Successive Approximation Register) A/D converter
>> +
>> +Required properties:
>> +- compatible: depending on the SoC this should be one of:
>> + - "amlogic,meson-gxbb-saradc" for GXBB
>> + - "amlogic,meson-gxl-saradc" for GXL and GXM
>
> GXL and GXM should probably be 2 compatibles.
Amlogic's ADC driver does not differentiate between GXL and GXM
(because both SoCs are identical except the CPU and GPU cores).
I can still introduce a separate binding for GXM if you want (better
safe than sorry and takes less than 5 minutes) - just let me know
>> + along with the generic "amlogic,meson-saradc"
>> +- reg: the physical base address and length of the registers
>> +- clocks: phandle and clock identifier (see clock-names)
>> +- clock-names: mandatory clocks:
>> + - "clkin" for the reference clock (typically XTAL)
>> + - "core" for the SAR ADC core clock
>> + optional clocks:
>> + - "sana" for the analog clock
>> + - "adc_clk" for the ADC (sampling) clock
>> + - "adc_sel" for the ADC (sampling) clock mux
>> +- vref-supply: the regulator supply for the ADC reference voltage
>> +- #io-channel-cells: must be 1, see ../iio-bindings.txt
>> +
>> +Example:
>> + saradc: adc@8680 {
>> + compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
>> + #io-channel-cells = <1>;
>> + reg = <0x0 0x8680 0x0 0x34>;
>> + clocks = <&xtal>,
>> + <&clkc CLKID_SAR_ADC>,
>> + <&clkc CLKID_SANA>,
>> + <&clkc CLKID_SAR_ADC_CLK>,
>> + <&clkc CLKID_SAR_ADC_SEL>;
>> + clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
>> + };
>> --
>> 2.11.0
>>
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v3 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
@ 2017-01-21 23:10 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-21 23:10 UTC (permalink / raw)
To: linux-arm-kernel
Hi Rob,
thanks for reviewing this!
On Sat, Jan 21, 2017 at 9:56 PM, Rob Herring <robh@kernel.org> wrote:
> On Thu, Jan 19, 2017 at 03:58:19PM +0100, Martin Blumenstingl wrote:
>> This adds the devicetree binding documentation for the SAR ADC found in
>> Amlogic Meson SoCs.
>> Currently only the GXBB, GXL and GXM SoCs are supported.
>>
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
>> ---
>> .../bindings/iio/adc/amlogic,meson-saradc.txt | 31 ++++++++++++++++++++++
>> 1 file changed, 31 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
>>
>> diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
>> new file mode 100644
>> index 000000000000..9a0bec7afc63
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
>> @@ -0,0 +1,31 @@
>> +* Amlogic Meson SAR (Successive Approximation Register) A/D converter
>> +
>> +Required properties:
>> +- compatible: depending on the SoC this should be one of:
>> + - "amlogic,meson-gxbb-saradc" for GXBB
>> + - "amlogic,meson-gxl-saradc" for GXL and GXM
>
> GXL and GXM should probably be 2 compatibles.
Amlogic's ADC driver does not differentiate between GXL and GXM
(because both SoCs are identical except the CPU and GPU cores).
I can still introduce a separate binding for GXM if you want (better
safe than sorry and takes less than 5 minutes) - just let me know
>> + along with the generic "amlogic,meson-saradc"
>> +- reg: the physical base address and length of the registers
>> +- clocks: phandle and clock identifier (see clock-names)
>> +- clock-names: mandatory clocks:
>> + - "clkin" for the reference clock (typically XTAL)
>> + - "core" for the SAR ADC core clock
>> + optional clocks:
>> + - "sana" for the analog clock
>> + - "adc_clk" for the ADC (sampling) clock
>> + - "adc_sel" for the ADC (sampling) clock mux
>> +- vref-supply: the regulator supply for the ADC reference voltage
>> +- #io-channel-cells: must be 1, see ../iio-bindings.txt
>> +
>> +Example:
>> + saradc: adc at 8680 {
>> + compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
>> + #io-channel-cells = <1>;
>> + reg = <0x0 0x8680 0x0 0x34>;
>> + clocks = <&xtal>,
>> + <&clkc CLKID_SAR_ADC>,
>> + <&clkc CLKID_SANA>,
>> + <&clkc CLKID_SAR_ADC_CLK>,
>> + <&clkc CLKID_SAR_ADC_SEL>;
>> + clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
>> + };
>> --
>> 2.11.0
>>
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v3 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
@ 2017-01-21 23:10 ` Martin Blumenstingl
0 siblings, 0 replies; 110+ messages in thread
From: Martin Blumenstingl @ 2017-01-21 23:10 UTC (permalink / raw)
To: linus-amlogic
Hi Rob,
thanks for reviewing this!
On Sat, Jan 21, 2017 at 9:56 PM, Rob Herring <robh@kernel.org> wrote:
> On Thu, Jan 19, 2017 at 03:58:19PM +0100, Martin Blumenstingl wrote:
>> This adds the devicetree binding documentation for the SAR ADC found in
>> Amlogic Meson SoCs.
>> Currently only the GXBB, GXL and GXM SoCs are supported.
>>
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
>> ---
>> .../bindings/iio/adc/amlogic,meson-saradc.txt | 31 ++++++++++++++++++++++
>> 1 file changed, 31 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
>>
>> diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
>> new file mode 100644
>> index 000000000000..9a0bec7afc63
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
>> @@ -0,0 +1,31 @@
>> +* Amlogic Meson SAR (Successive Approximation Register) A/D converter
>> +
>> +Required properties:
>> +- compatible: depending on the SoC this should be one of:
>> + - "amlogic,meson-gxbb-saradc" for GXBB
>> + - "amlogic,meson-gxl-saradc" for GXL and GXM
>
> GXL and GXM should probably be 2 compatibles.
Amlogic's ADC driver does not differentiate between GXL and GXM
(because both SoCs are identical except the CPU and GPU cores).
I can still introduce a separate binding for GXM if you want (better
safe than sorry and takes less than 5 minutes) - just let me know
>> + along with the generic "amlogic,meson-saradc"
>> +- reg: the physical base address and length of the registers
>> +- clocks: phandle and clock identifier (see clock-names)
>> +- clock-names: mandatory clocks:
>> + - "clkin" for the reference clock (typically XTAL)
>> + - "core" for the SAR ADC core clock
>> + optional clocks:
>> + - "sana" for the analog clock
>> + - "adc_clk" for the ADC (sampling) clock
>> + - "adc_sel" for the ADC (sampling) clock mux
>> +- vref-supply: the regulator supply for the ADC reference voltage
>> +- #io-channel-cells: must be 1, see ../iio-bindings.txt
>> +
>> +Example:
>> + saradc: adc at 8680 {
>> + compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
>> + #io-channel-cells = <1>;
>> + reg = <0x0 0x8680 0x0 0x34>;
>> + clocks = <&xtal>,
>> + <&clkc CLKID_SAR_ADC>,
>> + <&clkc CLKID_SANA>,
>> + <&clkc CLKID_SAR_ADC_CLK>,
>> + <&clkc CLKID_SAR_ADC_SEL>;
>> + clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
>> + };
>> --
>> 2.11.0
>>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v3 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
2017-01-21 23:10 ` Martin Blumenstingl
(?)
@ 2017-01-22 12:30 ` Jonathan Cameron
-1 siblings, 0 replies; 110+ messages in thread
From: Jonathan Cameron @ 2017-01-22 12:30 UTC (permalink / raw)
To: Martin Blumenstingl, Rob Herring
Cc: knaack.h, lars, pmeerw, mark.rutland, khilman, linux-iio,
devicetree, linux-amlogic, linux-clk, carlo, catalin.marinas,
will.deacon, mturquette, sboyd, narmstrong, linux-arm-kernel
On 21/01/17 23:10, Martin Blumenstingl wrote:
> Hi Rob,
>
> thanks for reviewing this!
>
> On Sat, Jan 21, 2017 at 9:56 PM, Rob Herring <robh@kernel.org> wrote:
>> On Thu, Jan 19, 2017 at 03:58:19PM +0100, Martin Blumenstingl wrote:
>>> This adds the devicetree binding documentation for the SAR ADC found in
>>> Amlogic Meson SoCs.
>>> Currently only the GXBB, GXL and GXM SoCs are supported.
>>>
>>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
>>> ---
>>> .../bindings/iio/adc/amlogic,meson-saradc.txt | 31 ++++++++++++++++++++++
>>> 1 file changed, 31 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
>>> new file mode 100644
>>> index 000000000000..9a0bec7afc63
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
>>> @@ -0,0 +1,31 @@
>>> +* Amlogic Meson SAR (Successive Approximation Register) A/D converter
>>> +
>>> +Required properties:
>>> +- compatible: depending on the SoC this should be one of:
>>> + - "amlogic,meson-gxbb-saradc" for GXBB
>>> + - "amlogic,meson-gxl-saradc" for GXL and GXM
>>
>> GXL and GXM should probably be 2 compatibles.
> Amlogic's ADC driver does not differentiate between GXL and GXM
> (because both SoCs are identical except the CPU and GPU cores).
> I can still introduce a separate binding for GXM if you want (better
> safe than sorry and takes less than 5 minutes) - just let me know
Probably best to do so as it's just conceivable there will be a hardware
bug in the the silicon or similar. Also makes things a little more
'obviously correct'.
Jonathan
>
>>> + along with the generic "amlogic,meson-saradc"
>>> +- reg: the physical base address and length of the registers
>>> +- clocks: phandle and clock identifier (see clock-names)
>>> +- clock-names: mandatory clocks:
>>> + - "clkin" for the reference clock (typically XTAL)
>>> + - "core" for the SAR ADC core clock
>>> + optional clocks:
>>> + - "sana" for the analog clock
>>> + - "adc_clk" for the ADC (sampling) clock
>>> + - "adc_sel" for the ADC (sampling) clock mux
>>> +- vref-supply: the regulator supply for the ADC reference voltage
>>> +- #io-channel-cells: must be 1, see ../iio-bindings.txt
>>> +
>>> +Example:
>>> + saradc: adc@8680 {
>>> + compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
>>> + #io-channel-cells = <1>;
>>> + reg = <0x0 0x8680 0x0 0x34>;
>>> + clocks = <&xtal>,
>>> + <&clkc CLKID_SAR_ADC>,
>>> + <&clkc CLKID_SANA>,
>>> + <&clkc CLKID_SAR_ADC_CLK>,
>>> + <&clkc CLKID_SAR_ADC_SEL>;
>>> + clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
>>> + };
>>> --
>>> 2.11.0
>>>
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v3 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
@ 2017-01-22 12:30 ` Jonathan Cameron
0 siblings, 0 replies; 110+ messages in thread
From: Jonathan Cameron @ 2017-01-22 12:30 UTC (permalink / raw)
To: linux-arm-kernel
On 21/01/17 23:10, Martin Blumenstingl wrote:
> Hi Rob,
>
> thanks for reviewing this!
>
> On Sat, Jan 21, 2017 at 9:56 PM, Rob Herring <robh@kernel.org> wrote:
>> On Thu, Jan 19, 2017 at 03:58:19PM +0100, Martin Blumenstingl wrote:
>>> This adds the devicetree binding documentation for the SAR ADC found in
>>> Amlogic Meson SoCs.
>>> Currently only the GXBB, GXL and GXM SoCs are supported.
>>>
>>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
>>> ---
>>> .../bindings/iio/adc/amlogic,meson-saradc.txt | 31 ++++++++++++++++++++++
>>> 1 file changed, 31 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
>>> new file mode 100644
>>> index 000000000000..9a0bec7afc63
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
>>> @@ -0,0 +1,31 @@
>>> +* Amlogic Meson SAR (Successive Approximation Register) A/D converter
>>> +
>>> +Required properties:
>>> +- compatible: depending on the SoC this should be one of:
>>> + - "amlogic,meson-gxbb-saradc" for GXBB
>>> + - "amlogic,meson-gxl-saradc" for GXL and GXM
>>
>> GXL and GXM should probably be 2 compatibles.
> Amlogic's ADC driver does not differentiate between GXL and GXM
> (because both SoCs are identical except the CPU and GPU cores).
> I can still introduce a separate binding for GXM if you want (better
> safe than sorry and takes less than 5 minutes) - just let me know
Probably best to do so as it's just conceivable there will be a hardware
bug in the the silicon or similar. Also makes things a little more
'obviously correct'.
Jonathan
>
>>> + along with the generic "amlogic,meson-saradc"
>>> +- reg: the physical base address and length of the registers
>>> +- clocks: phandle and clock identifier (see clock-names)
>>> +- clock-names: mandatory clocks:
>>> + - "clkin" for the reference clock (typically XTAL)
>>> + - "core" for the SAR ADC core clock
>>> + optional clocks:
>>> + - "sana" for the analog clock
>>> + - "adc_clk" for the ADC (sampling) clock
>>> + - "adc_sel" for the ADC (sampling) clock mux
>>> +- vref-supply: the regulator supply for the ADC reference voltage
>>> +- #io-channel-cells: must be 1, see ../iio-bindings.txt
>>> +
>>> +Example:
>>> + saradc: adc at 8680 {
>>> + compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
>>> + #io-channel-cells = <1>;
>>> + reg = <0x0 0x8680 0x0 0x34>;
>>> + clocks = <&xtal>,
>>> + <&clkc CLKID_SAR_ADC>,
>>> + <&clkc CLKID_SANA>,
>>> + <&clkc CLKID_SAR_ADC_CLK>,
>>> + <&clkc CLKID_SAR_ADC_SEL>;
>>> + clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
>>> + };
>>> --
>>> 2.11.0
>>>
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v3 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation
@ 2017-01-22 12:30 ` Jonathan Cameron
0 siblings, 0 replies; 110+ messages in thread
From: Jonathan Cameron @ 2017-01-22 12:30 UTC (permalink / raw)
To: linus-amlogic
On 21/01/17 23:10, Martin Blumenstingl wrote:
> Hi Rob,
>
> thanks for reviewing this!
>
> On Sat, Jan 21, 2017 at 9:56 PM, Rob Herring <robh@kernel.org> wrote:
>> On Thu, Jan 19, 2017 at 03:58:19PM +0100, Martin Blumenstingl wrote:
>>> This adds the devicetree binding documentation for the SAR ADC found in
>>> Amlogic Meson SoCs.
>>> Currently only the GXBB, GXL and GXM SoCs are supported.
>>>
>>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
>>> ---
>>> .../bindings/iio/adc/amlogic,meson-saradc.txt | 31 ++++++++++++++++++++++
>>> 1 file changed, 31 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
>>> new file mode 100644
>>> index 000000000000..9a0bec7afc63
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
>>> @@ -0,0 +1,31 @@
>>> +* Amlogic Meson SAR (Successive Approximation Register) A/D converter
>>> +
>>> +Required properties:
>>> +- compatible: depending on the SoC this should be one of:
>>> + - "amlogic,meson-gxbb-saradc" for GXBB
>>> + - "amlogic,meson-gxl-saradc" for GXL and GXM
>>
>> GXL and GXM should probably be 2 compatibles.
> Amlogic's ADC driver does not differentiate between GXL and GXM
> (because both SoCs are identical except the CPU and GPU cores).
> I can still introduce a separate binding for GXM if you want (better
> safe than sorry and takes less than 5 minutes) - just let me know
Probably best to do so as it's just conceivable there will be a hardware
bug in the the silicon or similar. Also makes things a little more
'obviously correct'.
Jonathan
>
>>> + along with the generic "amlogic,meson-saradc"
>>> +- reg: the physical base address and length of the registers
>>> +- clocks: phandle and clock identifier (see clock-names)
>>> +- clock-names: mandatory clocks:
>>> + - "clkin" for the reference clock (typically XTAL)
>>> + - "core" for the SAR ADC core clock
>>> + optional clocks:
>>> + - "sana" for the analog clock
>>> + - "adc_clk" for the ADC (sampling) clock
>>> + - "adc_sel" for the ADC (sampling) clock mux
>>> +- vref-supply: the regulator supply for the ADC reference voltage
>>> +- #io-channel-cells: must be 1, see ../iio-bindings.txt
>>> +
>>> +Example:
>>> + saradc: adc at 8680 {
>>> + compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
>>> + #io-channel-cells = <1>;
>>> + reg = <0x0 0x8680 0x0 0x34>;
>>> + clocks = <&xtal>,
>>> + <&clkc CLKID_SAR_ADC>,
>>> + <&clkc CLKID_SANA>,
>>> + <&clkc CLKID_SAR_ADC_CLK>,
>>> + <&clkc CLKID_SAR_ADC_SEL>;
>>> + clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
>>> + };
>>> --
>>> 2.11.0
>>>
^ permalink raw reply [flat|nested] 110+ messages in thread
end of thread, other threads:[~2017-01-22 12:30 UTC | newest]
Thread overview: 110+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-01-11 17:43 [PATCH 0/4] Amlogic Meson SAR ADC support Martin Blumenstingl
2017-01-11 17:43 ` Martin Blumenstingl
2017-01-11 17:43 ` Martin Blumenstingl
2017-01-11 17:43 ` Martin Blumenstingl
2017-01-11 17:43 ` [PATCH 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs Martin Blumenstingl
2017-01-11 17:43 ` Martin Blumenstingl
2017-01-11 17:43 ` Martin Blumenstingl
2017-01-14 14:46 ` Jonathan Cameron
2017-01-14 14:46 ` Jonathan Cameron
2017-01-14 14:46 ` Jonathan Cameron
[not found] ` <870f8899-b3a1-153a-5953-88ac23ff6942-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
2017-01-14 17:44 ` Martin Blumenstingl
2017-01-14 17:44 ` Martin Blumenstingl
2017-01-14 17:44 ` Martin Blumenstingl
2017-01-14 17:44 ` Martin Blumenstingl
2017-01-15 13:08 ` Jonathan Cameron
2017-01-15 13:08 ` Jonathan Cameron
2017-01-15 13:08 ` Jonathan Cameron
[not found] ` <20170111174334.24343-4-martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
2017-01-15 12:26 ` Lars-Peter Clausen
2017-01-15 12:26 ` Lars-Peter Clausen
2017-01-15 12:26 ` Lars-Peter Clausen
2017-01-15 12:26 ` Lars-Peter Clausen
2017-01-15 13:09 ` Jonathan Cameron
2017-01-15 13:09 ` Jonathan Cameron
2017-01-15 13:09 ` Jonathan Cameron
2017-01-11 17:43 ` [PATCH 4/4] ARM64: dts: meson: meson-gx: add the SAR ADC Martin Blumenstingl
2017-01-11 17:43 ` Martin Blumenstingl
2017-01-11 17:43 ` Martin Blumenstingl
[not found] ` <20170111174334.24343-1-martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
2017-01-11 17:43 ` [PATCH 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation Martin Blumenstingl
2017-01-11 17:43 ` Martin Blumenstingl
2017-01-11 17:43 ` Martin Blumenstingl
2017-01-11 17:43 ` Martin Blumenstingl
2017-01-11 17:43 ` [PATCH 2/4] clk: gxbb: add the SAR ADC clocks and expose them Martin Blumenstingl
2017-01-11 17:43 ` Martin Blumenstingl
2017-01-11 17:43 ` Martin Blumenstingl
2017-01-11 17:43 ` Martin Blumenstingl
2017-01-15 22:42 ` [PATCH v2 0/4] Amlogic Meson SAR ADC support Martin Blumenstingl
2017-01-15 22:42 ` Martin Blumenstingl
2017-01-15 22:42 ` Martin Blumenstingl
2017-01-15 22:42 ` Martin Blumenstingl
[not found] ` <20170115224221.15510-1-martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
2017-01-15 22:42 ` [PATCH v2 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation Martin Blumenstingl
2017-01-15 22:42 ` Martin Blumenstingl
2017-01-15 22:42 ` Martin Blumenstingl
2017-01-15 22:42 ` Martin Blumenstingl
2017-01-15 22:42 ` [PATCH v2 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs Martin Blumenstingl
2017-01-15 22:42 ` Martin Blumenstingl
2017-01-15 22:42 ` Martin Blumenstingl
2017-01-15 22:42 ` Martin Blumenstingl
2017-01-16 17:41 ` Peter Meerwald-Stadler
2017-01-16 17:41 ` Peter Meerwald-Stadler
2017-01-16 10:18 ` [PATCH v2 0/4] Amlogic Meson SAR ADC support Neil Armstrong
2017-01-16 10:18 ` Neil Armstrong
2017-01-16 10:18 ` Neil Armstrong
2017-01-16 10:18 ` Neil Armstrong
2017-01-15 22:42 ` [PATCH v2 2/4] clk: gxbb: add the SAR ADC clocks and expose them Martin Blumenstingl
2017-01-15 22:42 ` Martin Blumenstingl
2017-01-15 22:42 ` Martin Blumenstingl
2017-01-15 22:42 ` [PATCH v2 4/4] ARM64: dts: meson: meson-gx: add the SAR ADC Martin Blumenstingl
2017-01-15 22:42 ` Martin Blumenstingl
2017-01-15 22:42 ` Martin Blumenstingl
2017-01-19 14:58 ` [PATCH v3 0/4] Amlogic Meson SAR ADC support Martin Blumenstingl
2017-01-19 14:58 ` Martin Blumenstingl
2017-01-19 14:58 ` Martin Blumenstingl
2017-01-19 14:58 ` [PATCH v3 1/4] Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentation Martin Blumenstingl
2017-01-19 14:58 ` Martin Blumenstingl
2017-01-19 14:58 ` Martin Blumenstingl
[not found] ` <20170119145822.26239-2-martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
2017-01-21 12:39 ` Jonathan Cameron
2017-01-21 12:39 ` Jonathan Cameron
2017-01-21 12:39 ` Jonathan Cameron
2017-01-21 12:39 ` Jonathan Cameron
2017-01-21 13:21 ` Andreas Färber
2017-01-21 13:21 ` Andreas Färber
2017-01-21 13:21 ` Andreas Färber
2017-01-21 20:56 ` Rob Herring
2017-01-21 20:56 ` Rob Herring
2017-01-21 20:56 ` Rob Herring
2017-01-21 20:56 ` Rob Herring
2017-01-21 23:10 ` Martin Blumenstingl
2017-01-21 23:10 ` Martin Blumenstingl
2017-01-21 23:10 ` Martin Blumenstingl
2017-01-22 12:30 ` Jonathan Cameron
2017-01-22 12:30 ` Jonathan Cameron
2017-01-22 12:30 ` Jonathan Cameron
2017-01-19 14:58 ` [PATCH v3 2/4] clk: gxbb: add the SAR ADC clocks and expose them Martin Blumenstingl
2017-01-19 14:58 ` Martin Blumenstingl
2017-01-19 14:58 ` Martin Blumenstingl
[not found] ` <20170119145822.26239-3-martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
2017-01-19 19:13 ` Stephen Boyd
2017-01-19 19:13 ` Stephen Boyd
2017-01-19 19:13 ` Stephen Boyd
2017-01-19 19:13 ` Stephen Boyd
2017-01-20 15:46 ` Kevin Hilman
2017-01-20 15:46 ` Kevin Hilman
2017-01-20 15:46 ` Kevin Hilman
2017-01-20 15:46 ` Kevin Hilman
2017-01-19 14:58 ` [PATCH v3 3/4] iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs Martin Blumenstingl
2017-01-19 14:58 ` Martin Blumenstingl
2017-01-19 14:58 ` Martin Blumenstingl
2017-01-21 12:52 ` Jonathan Cameron
2017-01-21 12:52 ` Jonathan Cameron
2017-01-21 12:52 ` Jonathan Cameron
2017-01-21 12:52 ` Jonathan Cameron
2017-01-19 14:58 ` [PATCH v3 4/4] ARM64: dts: meson: meson-gx: add the SAR ADC Martin Blumenstingl
2017-01-19 14:58 ` Martin Blumenstingl
2017-01-19 14:58 ` Martin Blumenstingl
2017-01-21 13:28 ` Andreas Färber
2017-01-21 13:28 ` Andreas Färber
2017-01-21 13:28 ` Andreas Färber
[not found] ` <20170119145822.26239-1-martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
2017-01-21 12:37 ` [PATCH v3 0/4] Amlogic Meson SAR ADC support Jonathan Cameron
2017-01-21 12:37 ` Jonathan Cameron
2017-01-21 12:37 ` Jonathan Cameron
2017-01-21 12:37 ` Jonathan Cameron
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