* [PATCH 0/9] ARM: sun5i: Cleanup and reorganisation of the DTSI
@ 2017-02-05 18:49 ` Maxime Ripard
0 siblings, 0 replies; 44+ messages in thread
From: Maxime Ripard @ 2017-02-05 18:49 UTC (permalink / raw)
To: Chen-Yu Tsai, Maxime Ripard; +Cc: linux-arm-kernel, linux-kernel
Hi,
Most of the sun5i DTSI have grown organically, some nodes being added to
SoC DTSI because they were not properly tested, some because old datasheet
were wrong, and some times because we were not even sure whether it could
be shared at all, or how to share it.
Now that we have much more details, we can use that opportunity to
refactor all our DTSI so that we reduce greatly the duplication, especially
with the GR8 DTSI.
Let me know what you think,
Maxime
Maxime Ripard (9):
ARM: sun5i: A10s: Switch the EMAC pins indices
ARM: sun5i: a10s: switch simple framebuffer indices
ARM: sunxi: Rename pwm0_pins to match our usual pattern
ARM: sun5i: Add UART2 pin group
ARM: sun5i: Rename UART3 flow control pins
ARM: sun5i: a13: Merge common controllers into the common DTSI
ARM: sun5i: a10s: Merge common controllers into the common DTSI
ARM: sun5i: r8: Merge common controllers into the common DTSI
ARM: sun5i: gr8: Use common sun5i DTSI
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 4 +-
arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts | 2 +-
arch/arm/boot/dts/sun5i-a10s.dtsi | 76 +-
arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts | 2 +-
arch/arm/boot/dts/sun5i-a13.dtsi | 139 +--
arch/arm/boot/dts/sun5i-gr8-chip-pro.dts | 2 +-
arch/arm/boot/dts/sun5i-gr8-evb.dts | 2 +-
arch/arm/boot/dts/sun5i-gr8.dtsi | 617 +----------
arch/arm/boot/dts/sun5i-r8-chip.dts | 2 +-
arch/arm/boot/dts/sun5i-r8.dtsi | 40 +-
arch/arm/boot/dts/sun5i.dtsi | 292 ++++-
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi | 2 +-
13 files changed, 327 insertions(+), 855 deletions(-)
base-commit: 2a6e628efb37432a83bb42b00e3c403b1d8873dd
--
git-series 0.8.11
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 0/9] ARM: sun5i: Cleanup and reorganisation of the DTSI
@ 2017-02-05 18:49 ` Maxime Ripard
0 siblings, 0 replies; 44+ messages in thread
From: Maxime Ripard @ 2017-02-05 18:49 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Most of the sun5i DTSI have grown organically, some nodes being added to
SoC DTSI because they were not properly tested, some because old datasheet
were wrong, and some times because we were not even sure whether it could
be shared at all, or how to share it.
Now that we have much more details, we can use that opportunity to
refactor all our DTSI so that we reduce greatly the duplication, especially
with the GR8 DTSI.
Let me know what you think,
Maxime
Maxime Ripard (9):
ARM: sun5i: A10s: Switch the EMAC pins indices
ARM: sun5i: a10s: switch simple framebuffer indices
ARM: sunxi: Rename pwm0_pins to match our usual pattern
ARM: sun5i: Add UART2 pin group
ARM: sun5i: Rename UART3 flow control pins
ARM: sun5i: a13: Merge common controllers into the common DTSI
ARM: sun5i: a10s: Merge common controllers into the common DTSI
ARM: sun5i: r8: Merge common controllers into the common DTSI
ARM: sun5i: gr8: Use common sun5i DTSI
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 4 +-
arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts | 2 +-
arch/arm/boot/dts/sun5i-a10s.dtsi | 76 +-
arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts | 2 +-
arch/arm/boot/dts/sun5i-a13.dtsi | 139 +--
arch/arm/boot/dts/sun5i-gr8-chip-pro.dts | 2 +-
arch/arm/boot/dts/sun5i-gr8-evb.dts | 2 +-
arch/arm/boot/dts/sun5i-gr8.dtsi | 617 +----------
arch/arm/boot/dts/sun5i-r8-chip.dts | 2 +-
arch/arm/boot/dts/sun5i-r8.dtsi | 40 +-
arch/arm/boot/dts/sun5i.dtsi | 292 ++++-
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi | 2 +-
13 files changed, 327 insertions(+), 855 deletions(-)
base-commit: 2a6e628efb37432a83bb42b00e3c403b1d8873dd
--
git-series 0.8.11
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 1/9] ARM: sun5i: A10s: Switch the EMAC pins indices
2017-02-05 18:49 ` Maxime Ripard
@ 2017-02-05 18:49 ` Maxime Ripard
-1 siblings, 0 replies; 44+ messages in thread
From: Maxime Ripard @ 2017-02-05 18:49 UTC (permalink / raw)
To: Chen-Yu Tsai, Maxime Ripard; +Cc: linux-arm-kernel, linux-kernel
One of the pins group for the EMAC can be used by all the SoCs of the sun5i
family, and as such can be moved to the common DTSI.
Unfortunately, this group is the second one we declare in our DT for now.
Make it the first one so that it's more logical and consistent with the
rest of our DTs before moving it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 2 +-
arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts | 2 +-
arch/arm/boot/dts/sun5i-a10s.dtsi | 4 ++--
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index d8245c6314a7..9fbeb584abf5 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -83,7 +83,7 @@
&emac {
pinctrl-names = "default";
- pinctrl-0 = <&emac_pins_a>;
+ pinctrl-0 = <&emac_pins_b>;
phy = <&phy1>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts
index 2b8adda0deda..99c84e870d91 100644
--- a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts
@@ -95,7 +95,7 @@
&emac {
pinctrl-names = "default";
- pinctrl-0 = <&emac_pins_b>;
+ pinctrl-0 = <&emac_pins_a>;
phy = <&phy1>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 24b0f5f556f8..df2ba63d4ff9 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -156,7 +156,7 @@
function = "uart2";
};
- emac_pins_a: emac0@0 {
+ emac_pins_b: emac0@1 {
pins = "PA0", "PA1", "PA2",
"PA3", "PA4", "PA5", "PA6",
"PA7", "PA8", "PA9", "PA10",
@@ -165,7 +165,7 @@
function = "emac";
};
- emac_pins_b: emac0@1 {
+ emac_pins_a: emac0@0 {
pins = "PD6", "PD7", "PD10",
"PD11", "PD12", "PD13", "PD14",
"PD15", "PD18", "PD19", "PD20",
--
git-series 0.8.11
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 1/9] ARM: sun5i: A10s: Switch the EMAC pins indices
@ 2017-02-05 18:49 ` Maxime Ripard
0 siblings, 0 replies; 44+ messages in thread
From: Maxime Ripard @ 2017-02-05 18:49 UTC (permalink / raw)
To: linux-arm-kernel
One of the pins group for the EMAC can be used by all the SoCs of the sun5i
family, and as such can be moved to the common DTSI.
Unfortunately, this group is the second one we declare in our DT for now.
Make it the first one so that it's more logical and consistent with the
rest of our DTs before moving it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 2 +-
arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts | 2 +-
arch/arm/boot/dts/sun5i-a10s.dtsi | 4 ++--
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index d8245c6314a7..9fbeb584abf5 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -83,7 +83,7 @@
&emac {
pinctrl-names = "default";
- pinctrl-0 = <&emac_pins_a>;
+ pinctrl-0 = <&emac_pins_b>;
phy = <&phy1>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts
index 2b8adda0deda..99c84e870d91 100644
--- a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts
@@ -95,7 +95,7 @@
&emac {
pinctrl-names = "default";
- pinctrl-0 = <&emac_pins_b>;
+ pinctrl-0 = <&emac_pins_a>;
phy = <&phy1>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 24b0f5f556f8..df2ba63d4ff9 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -156,7 +156,7 @@
function = "uart2";
};
- emac_pins_a: emac0 at 0 {
+ emac_pins_b: emac0 at 1 {
pins = "PA0", "PA1", "PA2",
"PA3", "PA4", "PA5", "PA6",
"PA7", "PA8", "PA9", "PA10",
@@ -165,7 +165,7 @@
function = "emac";
};
- emac_pins_b: emac0 at 1 {
+ emac_pins_a: emac0 at 0 {
pins = "PD6", "PD7", "PD10",
"PD11", "PD12", "PD13", "PD14",
"PD15", "PD18", "PD19", "PD20",
--
git-series 0.8.11
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 2/9] ARM: sun5i: a10s: switch simple framebuffer indices
2017-02-05 18:49 ` Maxime Ripard
@ 2017-02-05 18:49 ` Maxime Ripard
-1 siblings, 0 replies; 44+ messages in thread
From: Maxime Ripard @ 2017-02-05 18:49 UTC (permalink / raw)
To: Chen-Yu Tsai, Maxime Ripard; +Cc: linux-arm-kernel, linux-kernel
Of the three simple framebuffer setups we have in the A10s, two of them can
be shared with the other SoCs from the sun5i family (LCD panel and
composite output).
However, the only one we cannot share is the HDMI, which is the first
listed in the A10s DTSI. In order to make it more logical and so that we
can share the framebuffer nodes in the common DTSI, reorder those nodes.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index df2ba63d4ff9..0c08b6173d9c 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -61,7 +61,7 @@
#size-cells = <1>;
ranges;
- framebuffer@0 {
+ framebuffer@2 {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
@@ -71,7 +71,7 @@
status = "disabled";
};
- framebuffer@1 {
+ framebuffer@0 {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
@@ -80,7 +80,7 @@
status = "disabled";
};
- framebuffer@2 {
+ framebuffer@1 {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-tve0";
--
git-series 0.8.11
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 2/9] ARM: sun5i: a10s: switch simple framebuffer indices
@ 2017-02-05 18:49 ` Maxime Ripard
0 siblings, 0 replies; 44+ messages in thread
From: Maxime Ripard @ 2017-02-05 18:49 UTC (permalink / raw)
To: linux-arm-kernel
Of the three simple framebuffer setups we have in the A10s, two of them can
be shared with the other SoCs from the sun5i family (LCD panel and
composite output).
However, the only one we cannot share is the HDMI, which is the first
listed in the A10s DTSI. In order to make it more logical and so that we
can share the framebuffer nodes in the common DTSI, reorder those nodes.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index df2ba63d4ff9..0c08b6173d9c 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -61,7 +61,7 @@
#size-cells = <1>;
ranges;
- framebuffer at 0 {
+ framebuffer at 2 {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
@@ -71,7 +71,7 @@
status = "disabled";
};
- framebuffer at 1 {
+ framebuffer at 0 {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
@@ -80,7 +80,7 @@
status = "disabled";
};
- framebuffer at 2 {
+ framebuffer at 1 {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-tve0";
--
git-series 0.8.11
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 3/9] ARM: sunxi: Rename pwm0_pins to match our usual pattern
2017-02-05 18:49 ` Maxime Ripard
@ 2017-02-05 18:49 ` Maxime Ripard
-1 siblings, 0 replies; 44+ messages in thread
From: Maxime Ripard @ 2017-02-05 18:49 UTC (permalink / raw)
To: Chen-Yu Tsai, Maxime Ripard; +Cc: linux-arm-kernel, linux-kernel
The pwm0_pins group name is suggesting that this is the only option usable
for the PWM0 on the SoCs it's declared on. However, this is not the case
and defining a second pwm0 group would be quite weird given the name of the
first group.
Rename it so that it matches our usual pattern.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts | 2 +-
arch/arm/boot/dts/sun5i.dtsi | 10 +++++-----
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi | 2 +-
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
index 42435454acef..1bc87523b37c 100644
--- a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
+++ b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
@@ -157,7 +157,7 @@
&pwm {
pinctrl-names = "default";
- pinctrl-0 = <&pwm0_pins>;
+ pinctrl-0 = <&pwm0_pins_a>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index a9574a6cd95c..fce3ec693531 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -321,6 +321,11 @@
bias-pull-up;
};
+ pwm0_pins_a: pwm0@0 {
+ pins = "PB2";
+ function = "pwm0";
+ };
+
spi2_pins_a: spi2@0 {
pins = "PE1", "PE2", "PE3";
function = "spi2";
@@ -340,11 +345,6 @@
pins = "PG11", "PG12";
function = "uart3";
};
-
- pwm0_pins: pwm0 {
- pins = "PB2";
- function = "pwm";
- };
};
timer@01c20c00 {
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 35008b78d899..b558d318a72e 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -316,7 +316,7 @@
bias-pull-up;
};
- pwm0_pins: pwm0 {
+ pwm0_pins_a: pwm0 {
pins = "PH0";
function = "pwm0";
};
diff --git a/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi b/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi
index b8241462fcea..5cd891942fe3 100644
--- a/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi
+++ b/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi
@@ -78,6 +78,6 @@
&pwm {
pinctrl-names = "default";
- pinctrl-0 = <&pwm0_pins>;
+ pinctrl-0 = <&pwm0_pins_a>;
status = "okay";
};
--
git-series 0.8.11
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 3/9] ARM: sunxi: Rename pwm0_pins to match our usual pattern
@ 2017-02-05 18:49 ` Maxime Ripard
0 siblings, 0 replies; 44+ messages in thread
From: Maxime Ripard @ 2017-02-05 18:49 UTC (permalink / raw)
To: linux-arm-kernel
The pwm0_pins group name is suggesting that this is the only option usable
for the PWM0 on the SoCs it's declared on. However, this is not the case
and defining a second pwm0 group would be quite weird given the name of the
first group.
Rename it so that it matches our usual pattern.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts | 2 +-
arch/arm/boot/dts/sun5i.dtsi | 10 +++++-----
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi | 2 +-
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
index 42435454acef..1bc87523b37c 100644
--- a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
+++ b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
@@ -157,7 +157,7 @@
&pwm {
pinctrl-names = "default";
- pinctrl-0 = <&pwm0_pins>;
+ pinctrl-0 = <&pwm0_pins_a>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index a9574a6cd95c..fce3ec693531 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -321,6 +321,11 @@
bias-pull-up;
};
+ pwm0_pins_a: pwm0 at 0 {
+ pins = "PB2";
+ function = "pwm0";
+ };
+
spi2_pins_a: spi2 at 0 {
pins = "PE1", "PE2", "PE3";
function = "spi2";
@@ -340,11 +345,6 @@
pins = "PG11", "PG12";
function = "uart3";
};
-
- pwm0_pins: pwm0 {
- pins = "PB2";
- function = "pwm";
- };
};
timer at 01c20c00 {
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 35008b78d899..b558d318a72e 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -316,7 +316,7 @@
bias-pull-up;
};
- pwm0_pins: pwm0 {
+ pwm0_pins_a: pwm0 {
pins = "PH0";
function = "pwm0";
};
diff --git a/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi b/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi
index b8241462fcea..5cd891942fe3 100644
--- a/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi
+++ b/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi
@@ -78,6 +78,6 @@
&pwm {
pinctrl-names = "default";
- pinctrl-0 = <&pwm0_pins>;
+ pinctrl-0 = <&pwm0_pins_a>;
status = "okay";
};
--
git-series 0.8.11
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 4/9] ARM: sun5i: Add UART2 pin group
2017-02-05 18:49 ` Maxime Ripard
@ 2017-02-05 18:49 ` Maxime Ripard
-1 siblings, 0 replies; 44+ messages in thread
From: Maxime Ripard @ 2017-02-05 18:49 UTC (permalink / raw)
To: Chen-Yu Tsai, Maxime Ripard; +Cc: linux-arm-kernel, linux-kernel
There's one UART2 pin group that can be used across all sun5i SoCs.
However, the A10s already has one pin group for that controller.
Change the index of the one in the A10s DTSI, and add the common one to
sun5i.dtsi
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 2 +-
arch/arm/boot/dts/sun5i-a10s.dtsi | 2 +-
arch/arm/boot/dts/sun5i.dtsi | 10 ++++++++++
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index 9fbeb584abf5..baee64d61f6d 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -257,7 +257,7 @@
&uart2 {
pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins_a>;
+ pinctrl-0 = <&uart2_pins_b>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 0c08b6173d9c..5122d1179e59 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -151,7 +151,7 @@
function = "uart0";
};
- uart2_pins_a: uart2@0 {
+ uart2_pins_b: uart2@1 {
pins = "PC18", "PC19";
function = "uart2";
};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index fce3ec693531..cd951e2cdbe7 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -336,6 +336,16 @@
function = "spi2";
};
+ uart2_pins_a: uart2@0 {
+ pins = "PD2", "PD3";
+ function = "uart2";
+ };
+
+ uart2_cts_rts_pins_a: uart2-cts-rts@0 {
+ pins = "PD4", "PD5";
+ function = "uart2";
+ };
+
uart3_pins_a: uart3@0 {
pins = "PG9", "PG10";
function = "uart3";
--
git-series 0.8.11
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 4/9] ARM: sun5i: Add UART2 pin group
@ 2017-02-05 18:49 ` Maxime Ripard
0 siblings, 0 replies; 44+ messages in thread
From: Maxime Ripard @ 2017-02-05 18:49 UTC (permalink / raw)
To: linux-arm-kernel
There's one UART2 pin group that can be used across all sun5i SoCs.
However, the A10s already has one pin group for that controller.
Change the index of the one in the A10s DTSI, and add the common one to
sun5i.dtsi
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 2 +-
arch/arm/boot/dts/sun5i-a10s.dtsi | 2 +-
arch/arm/boot/dts/sun5i.dtsi | 10 ++++++++++
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index 9fbeb584abf5..baee64d61f6d 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -257,7 +257,7 @@
&uart2 {
pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins_a>;
+ pinctrl-0 = <&uart2_pins_b>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 0c08b6173d9c..5122d1179e59 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -151,7 +151,7 @@
function = "uart0";
};
- uart2_pins_a: uart2 at 0 {
+ uart2_pins_b: uart2 at 1 {
pins = "PC18", "PC19";
function = "uart2";
};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index fce3ec693531..cd951e2cdbe7 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -336,6 +336,16 @@
function = "spi2";
};
+ uart2_pins_a: uart2 at 0 {
+ pins = "PD2", "PD3";
+ function = "uart2";
+ };
+
+ uart2_cts_rts_pins_a: uart2-cts-rts at 0 {
+ pins = "PD4", "PD5";
+ function = "uart2";
+ };
+
uart3_pins_a: uart3 at 0 {
pins = "PG9", "PG10";
function = "uart3";
--
git-series 0.8.11
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 5/9] ARM: sun5i: Rename UART3 flow control pins
2017-02-05 18:49 ` Maxime Ripard
@ 2017-02-05 18:49 ` Maxime Ripard
-1 siblings, 0 replies; 44+ messages in thread
From: Maxime Ripard @ 2017-02-05 18:49 UTC (permalink / raw)
To: Chen-Yu Tsai, Maxime Ripard; +Cc: linux-arm-kernel, linux-kernel
The UART3 pin group for the CTS and RTS signals doesn't follow our usual
pattern. Rename it so that it matches.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-r8-chip.dts | 2 +-
arch/arm/boot/dts/sun5i.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts
index e86fa46fdd45..c9a18216674a 100644
--- a/arch/arm/boot/dts/sun5i-r8-chip.dts
+++ b/arch/arm/boot/dts/sun5i-r8-chip.dts
@@ -281,7 +281,7 @@
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins_a>,
- <&uart3_pins_cts_rts_a>;
+ <&uart3_cts_rts_pins_a>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index cd951e2cdbe7..d4888e0a0a13 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -351,7 +351,7 @@
function = "uart3";
};
- uart3_pins_cts_rts_a: uart3-cts-rts@0 {
+ uart3_cts_rts_pins_a: uart3-cts-rts@0 {
pins = "PG11", "PG12";
function = "uart3";
};
--
git-series 0.8.11
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 5/9] ARM: sun5i: Rename UART3 flow control pins
@ 2017-02-05 18:49 ` Maxime Ripard
0 siblings, 0 replies; 44+ messages in thread
From: Maxime Ripard @ 2017-02-05 18:49 UTC (permalink / raw)
To: linux-arm-kernel
The UART3 pin group for the CTS and RTS signals doesn't follow our usual
pattern. Rename it so that it matches.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-r8-chip.dts | 2 +-
arch/arm/boot/dts/sun5i.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts
index e86fa46fdd45..c9a18216674a 100644
--- a/arch/arm/boot/dts/sun5i-r8-chip.dts
+++ b/arch/arm/boot/dts/sun5i-r8-chip.dts
@@ -281,7 +281,7 @@
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins_a>,
- <&uart3_pins_cts_rts_a>;
+ <&uart3_cts_rts_pins_a>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index cd951e2cdbe7..d4888e0a0a13 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -351,7 +351,7 @@
function = "uart3";
};
- uart3_pins_cts_rts_a: uart3-cts-rts at 0 {
+ uart3_cts_rts_pins_a: uart3-cts-rts at 0 {
pins = "PG11", "PG12";
function = "uart3";
};
--
git-series 0.8.11
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 6/9] ARM: sun5i: a13: Merge common controllers into the common DTSI
2017-02-05 18:49 ` Maxime Ripard
@ 2017-02-05 18:49 ` Maxime Ripard
-1 siblings, 0 replies; 44+ messages in thread
From: Maxime Ripard @ 2017-02-05 18:49 UTC (permalink / raw)
To: Chen-Yu Tsai, Maxime Ripard; +Cc: linux-arm-kernel, linux-kernel
Some controllers found in the A13 DTSI actually apply to all of the sun5i
family. Move those into the common DTSI so that all SoCs can benefit from
it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-a13.dtsi | 139 +--------------------------------
arch/arm/boot/dts/sun5i.dtsi | 140 ++++++++++++++++++++++++++++++++-
2 files changed, 140 insertions(+), 139 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index fb2ddb9a04c9..6f8c508e8e70 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -52,21 +52,6 @@
/ {
interrupt-parent = <&intc>;
- chosen {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- framebuffer@0 {
- compatible = "allwinner,simple-framebuffer",
- "simple-framebuffer";
- allwinner,pipeline = "de_be0-lcd0";
- clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
- <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
- status = "disabled";
- };
- };
-
thermal-zones {
cpu_thermal {
/* milliseconds */
@@ -105,44 +90,6 @@
};
soc@01c00000 {
- tcon0: lcd-controller@01c0c000 {
- compatible = "allwinner,sun5i-a13-tcon";
- reg = <0x01c0c000 0x1000>;
- interrupts = <44>;
- resets = <&ccu RST_LCD>;
- reset-names = "lcd";
- clocks = <&ccu CLK_AHB_LCD>,
- <&ccu CLK_TCON_CH0>,
- <&ccu CLK_TCON_CH1>;
- clock-names = "ahb",
- "tcon-ch0",
- "tcon-ch1";
- clock-output-names = "tcon-pixel-clock";
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- tcon0_in: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- tcon0_in_be0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&be0_out_tcon0>;
- };
- };
-
- tcon0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
- };
- };
- };
-
pwm: pwm@01c20e00 {
compatible = "allwinner,sun5i-a13-pwm";
reg = <0x01c20e00 0xc>;
@@ -151,74 +98,6 @@
status = "disabled";
};
- fe0: display-frontend@01e00000 {
- compatible = "allwinner,sun5i-a13-display-frontend";
- reg = <0x01e00000 0x20000>;
- interrupts = <47>;
- clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
- <&ccu CLK_DRAM_DE_FE>;
- clock-names = "ahb", "mod",
- "ram";
- resets = <&ccu RST_DE_FE>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- fe0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- fe0_out_be0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&be0_in_fe0>;
- };
- };
- };
- };
-
- be0: display-backend@01e60000 {
- compatible = "allwinner,sun5i-a13-display-backend";
- reg = <0x01e60000 0x10000>;
- clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
- <&ccu CLK_DRAM_DE_BE>;
- clock-names = "ahb", "mod",
- "ram";
- resets = <&ccu RST_DE_BE>;
- status = "disabled";
-
- assigned-clocks = <&ccu CLK_DE_BE>;
- assigned-clock-rates = <300000000>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- be0_in: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- be0_in_fe0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&fe0_out_be0>;
- };
- };
-
- be0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- be0_out_tcon0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&tcon0_in_be0>;
- };
- };
- };
- };
};
};
@@ -244,22 +123,4 @@
&pio {
compatible = "allwinner,sun5i-a13-pinctrl";
-
- lcd_rgb666_pins: lcd_rgb666@0 {
- pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
- "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
- "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
- "PD24", "PD25", "PD26", "PD27";
- function = "lcd0";
- };
-
- uart1_pins_a: uart1@0 {
- pins = "PE10", "PE11";
- function = "uart1";
- };
-
- uart1_pins_b: uart1@1 {
- pins = "PG3", "PG4";
- function = "uart1";
- };
};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index d4888e0a0a13..f27ca0be5835 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -64,6 +64,21 @@
};
};
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ framebuffer@0 {
+ compatible = "allwinner,simple-framebuffer",
+ "simple-framebuffer";
+ allwinner,pipeline = "de_be0-lcd0";
+ clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
+ <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
+ status = "disabled";
+ };
+ };
+
clocks {
#address-cells = <1>;
#size-cells = <1>;
@@ -156,6 +171,44 @@
#size-cells = <0>;
};
+ tcon0: lcd-controller@01c0c000 {
+ compatible = "allwinner,sun5i-a13-tcon";
+ reg = <0x01c0c000 0x1000>;
+ interrupts = <44>;
+ resets = <&ccu RST_LCD>;
+ reset-names = "lcd";
+ clocks = <&ccu CLK_AHB_LCD>,
+ <&ccu CLK_TCON_CH0>,
+ <&ccu CLK_TCON_CH1>;
+ clock-names = "ahb",
+ "tcon-ch0",
+ "tcon-ch1";
+ clock-output-names = "tcon-pixel-clock";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon0_in_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_out_tcon0>;
+ };
+ };
+
+ tcon0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+
mmc0: mmc@01c0f000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c0f000 0x1000>;
@@ -296,6 +349,14 @@
function = "lcd0";
};
+ lcd_rgb666_pins: lcd_rgb666@0 {
+ pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
+ "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
+ "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
+ "PD24", "PD25", "PD26", "PD27";
+ function = "lcd0";
+ };
+
mmc0_pins_a: mmc0@0 {
pins = "PF0", "PF1", "PF2", "PF3",
"PF4", "PF5";
@@ -336,6 +397,16 @@
function = "spi2";
};
+ uart1_pins_a: uart1@0 {
+ pins = "PE10", "PE11";
+ function = "uart1";
+ };
+
+ uart1_pins_b: uart1@1 {
+ pins = "PG3", "PG4";
+ function = "uart1";
+ };
+
uart2_pins_a: uart2@0 {
pins = "PD2", "PD3";
function = "uart2";
@@ -457,5 +528,74 @@
interrupts = <82>, <83>;
clocks = <&ccu CLK_AHB_HSTIMER>;
};
+
+ fe0: display-frontend@01e00000 {
+ compatible = "allwinner,sun5i-a13-display-frontend";
+ reg = <0x01e00000 0x20000>;
+ interrupts = <47>;
+ clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
+ <&ccu CLK_DRAM_DE_FE>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_DE_FE>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fe0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ fe0_out_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_in_fe0>;
+ };
+ };
+ };
+ };
+
+ be0: display-backend@01e60000 {
+ compatible = "allwinner,sun5i-a13-display-backend";
+ reg = <0x01e60000 0x10000>;
+ clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
+ <&ccu CLK_DRAM_DE_BE>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_DE_BE>;
+ status = "disabled";
+
+ assigned-clocks = <&ccu CLK_DE_BE>;
+ assigned-clock-rates = <300000000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ be0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ be0_in_fe0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&fe0_out_be0>;
+ };
+ };
+
+ be0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ be0_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_in_be0>;
+ };
+ };
+ };
+ };
};
};
--
git-series 0.8.11
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 6/9] ARM: sun5i: a13: Merge common controllers into the common DTSI
@ 2017-02-05 18:49 ` Maxime Ripard
0 siblings, 0 replies; 44+ messages in thread
From: Maxime Ripard @ 2017-02-05 18:49 UTC (permalink / raw)
To: linux-arm-kernel
Some controllers found in the A13 DTSI actually apply to all of the sun5i
family. Move those into the common DTSI so that all SoCs can benefit from
it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-a13.dtsi | 139 +--------------------------------
arch/arm/boot/dts/sun5i.dtsi | 140 ++++++++++++++++++++++++++++++++-
2 files changed, 140 insertions(+), 139 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index fb2ddb9a04c9..6f8c508e8e70 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -52,21 +52,6 @@
/ {
interrupt-parent = <&intc>;
- chosen {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- framebuffer at 0 {
- compatible = "allwinner,simple-framebuffer",
- "simple-framebuffer";
- allwinner,pipeline = "de_be0-lcd0";
- clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
- <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
- status = "disabled";
- };
- };
-
thermal-zones {
cpu_thermal {
/* milliseconds */
@@ -105,44 +90,6 @@
};
soc at 01c00000 {
- tcon0: lcd-controller at 01c0c000 {
- compatible = "allwinner,sun5i-a13-tcon";
- reg = <0x01c0c000 0x1000>;
- interrupts = <44>;
- resets = <&ccu RST_LCD>;
- reset-names = "lcd";
- clocks = <&ccu CLK_AHB_LCD>,
- <&ccu CLK_TCON_CH0>,
- <&ccu CLK_TCON_CH1>;
- clock-names = "ahb",
- "tcon-ch0",
- "tcon-ch1";
- clock-output-names = "tcon-pixel-clock";
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- tcon0_in: port at 0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- tcon0_in_be0: endpoint at 0 {
- reg = <0>;
- remote-endpoint = <&be0_out_tcon0>;
- };
- };
-
- tcon0_out: port at 1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
- };
- };
- };
-
pwm: pwm at 01c20e00 {
compatible = "allwinner,sun5i-a13-pwm";
reg = <0x01c20e00 0xc>;
@@ -151,74 +98,6 @@
status = "disabled";
};
- fe0: display-frontend at 01e00000 {
- compatible = "allwinner,sun5i-a13-display-frontend";
- reg = <0x01e00000 0x20000>;
- interrupts = <47>;
- clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
- <&ccu CLK_DRAM_DE_FE>;
- clock-names = "ahb", "mod",
- "ram";
- resets = <&ccu RST_DE_FE>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- fe0_out: port at 1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- fe0_out_be0: endpoint at 0 {
- reg = <0>;
- remote-endpoint = <&be0_in_fe0>;
- };
- };
- };
- };
-
- be0: display-backend at 01e60000 {
- compatible = "allwinner,sun5i-a13-display-backend";
- reg = <0x01e60000 0x10000>;
- clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
- <&ccu CLK_DRAM_DE_BE>;
- clock-names = "ahb", "mod",
- "ram";
- resets = <&ccu RST_DE_BE>;
- status = "disabled";
-
- assigned-clocks = <&ccu CLK_DE_BE>;
- assigned-clock-rates = <300000000>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- be0_in: port at 0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- be0_in_fe0: endpoint at 0 {
- reg = <0>;
- remote-endpoint = <&fe0_out_be0>;
- };
- };
-
- be0_out: port at 1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- be0_out_tcon0: endpoint at 0 {
- reg = <0>;
- remote-endpoint = <&tcon0_in_be0>;
- };
- };
- };
- };
};
};
@@ -244,22 +123,4 @@
&pio {
compatible = "allwinner,sun5i-a13-pinctrl";
-
- lcd_rgb666_pins: lcd_rgb666 at 0 {
- pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
- "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
- "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
- "PD24", "PD25", "PD26", "PD27";
- function = "lcd0";
- };
-
- uart1_pins_a: uart1 at 0 {
- pins = "PE10", "PE11";
- function = "uart1";
- };
-
- uart1_pins_b: uart1 at 1 {
- pins = "PG3", "PG4";
- function = "uart1";
- };
};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index d4888e0a0a13..f27ca0be5835 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -64,6 +64,21 @@
};
};
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ framebuffer at 0 {
+ compatible = "allwinner,simple-framebuffer",
+ "simple-framebuffer";
+ allwinner,pipeline = "de_be0-lcd0";
+ clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
+ <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
+ status = "disabled";
+ };
+ };
+
clocks {
#address-cells = <1>;
#size-cells = <1>;
@@ -156,6 +171,44 @@
#size-cells = <0>;
};
+ tcon0: lcd-controller at 01c0c000 {
+ compatible = "allwinner,sun5i-a13-tcon";
+ reg = <0x01c0c000 0x1000>;
+ interrupts = <44>;
+ resets = <&ccu RST_LCD>;
+ reset-names = "lcd";
+ clocks = <&ccu CLK_AHB_LCD>,
+ <&ccu CLK_TCON_CH0>,
+ <&ccu CLK_TCON_CH1>;
+ clock-names = "ahb",
+ "tcon-ch0",
+ "tcon-ch1";
+ clock-output-names = "tcon-pixel-clock";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon0_in_be0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&be0_out_tcon0>;
+ };
+ };
+
+ tcon0_out: port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+
mmc0: mmc at 01c0f000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c0f000 0x1000>;
@@ -296,6 +349,14 @@
function = "lcd0";
};
+ lcd_rgb666_pins: lcd_rgb666 at 0 {
+ pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
+ "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
+ "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
+ "PD24", "PD25", "PD26", "PD27";
+ function = "lcd0";
+ };
+
mmc0_pins_a: mmc0 at 0 {
pins = "PF0", "PF1", "PF2", "PF3",
"PF4", "PF5";
@@ -336,6 +397,16 @@
function = "spi2";
};
+ uart1_pins_a: uart1 at 0 {
+ pins = "PE10", "PE11";
+ function = "uart1";
+ };
+
+ uart1_pins_b: uart1 at 1 {
+ pins = "PG3", "PG4";
+ function = "uart1";
+ };
+
uart2_pins_a: uart2 at 0 {
pins = "PD2", "PD3";
function = "uart2";
@@ -457,5 +528,74 @@
interrupts = <82>, <83>;
clocks = <&ccu CLK_AHB_HSTIMER>;
};
+
+ fe0: display-frontend at 01e00000 {
+ compatible = "allwinner,sun5i-a13-display-frontend";
+ reg = <0x01e00000 0x20000>;
+ interrupts = <47>;
+ clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
+ <&ccu CLK_DRAM_DE_FE>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_DE_FE>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fe0_out: port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ fe0_out_be0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&be0_in_fe0>;
+ };
+ };
+ };
+ };
+
+ be0: display-backend at 01e60000 {
+ compatible = "allwinner,sun5i-a13-display-backend";
+ reg = <0x01e60000 0x10000>;
+ clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
+ <&ccu CLK_DRAM_DE_BE>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_DE_BE>;
+ status = "disabled";
+
+ assigned-clocks = <&ccu CLK_DE_BE>;
+ assigned-clock-rates = <300000000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ be0_in: port at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ be0_in_fe0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&fe0_out_be0>;
+ };
+ };
+
+ be0_out: port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ be0_out_tcon0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_in_be0>;
+ };
+ };
+ };
+ };
};
};
--
git-series 0.8.11
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 7/9] ARM: sun5i: a10s: Merge common controllers into the common DTSI
2017-02-05 18:49 ` Maxime Ripard
@ 2017-02-05 18:49 ` Maxime Ripard
-1 siblings, 0 replies; 44+ messages in thread
From: Maxime Ripard @ 2017-02-05 18:49 UTC (permalink / raw)
To: Chen-Yu Tsai, Maxime Ripard; +Cc: linux-arm-kernel, linux-kernel
Some controllers found in the A10s DTSI actually apply to all of the sun5i
family. Move those into the common DTSI so that all SoCs can benefit from
it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 70 +--------------------------------
arch/arm/boot/dts/sun5i.dtsi | 62 ++++++++++++++++++++++++++++-
2 files changed, 62 insertions(+), 70 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 5122d1179e59..074485782a4a 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -70,45 +70,9 @@
<&ccu CLK_DE_BE>, <&ccu CLK_HDMI>;
status = "disabled";
};
-
- framebuffer@0 {
- compatible = "allwinner,simple-framebuffer",
- "simple-framebuffer";
- allwinner,pipeline = "de_be0-lcd0";
- clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
- <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
- status = "disabled";
- };
-
- framebuffer@1 {
- compatible = "allwinner,simple-framebuffer",
- "simple-framebuffer";
- allwinner,pipeline = "de_be0-lcd0-tve0";
- clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
- <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
- <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
- status = "disabled";
- };
};
soc@01c00000 {
- emac: ethernet@01c0b000 {
- compatible = "allwinner,sun4i-a10-emac";
- reg = <0x01c0b000 0x1000>;
- interrupts = <55>;
- clocks = <&ccu CLK_AHB_EMAC>;
- allwinner,sram = <&emac_sram 1>;
- status = "disabled";
- };
-
- mdio: mdio@01c0b080 {
- compatible = "allwinner,sun4i-a10-mdio";
- reg = <0x01c0b080 0x14>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
pwm: pwm@01c20e00 {
compatible = "allwinner,sun5i-a10s-pwm";
reg = <0x01c20e00 0xc>;
@@ -116,26 +80,6 @@
#pwm-cells = <3>;
status = "disabled";
};
-
- uart0: serial@01c28000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28000 0x400>;
- interrupts = <1>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_APB1_UART0>;
- status = "disabled";
- };
-
- uart2: serial@01c28800 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28800 0x400>;
- interrupts = <3>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_APB1_UART2>;
- status = "disabled";
- };
};
};
@@ -165,15 +109,6 @@
function = "emac";
};
- emac_pins_a: emac0@0 {
- pins = "PD6", "PD7", "PD10",
- "PD11", "PD12", "PD13", "PD14",
- "PD15", "PD18", "PD19", "PD20",
- "PD21", "PD22", "PD23", "PD24",
- "PD25", "PD26", "PD27";
- function = "emac";
- };
-
mmc1_pins_a: mmc1@0 {
pins = "PG3", "PG4", "PG5",
"PG6", "PG7", "PG8";
@@ -193,9 +128,4 @@
};
&sram_a {
- emac_sram: sram-section@8000 {
- compatible = "allwinner,sun4i-a10-sram-a3-a4";
- reg = <0x8000 0x4000>;
- status = "disabled";
- };
};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index f27ca0be5835..9ba0c0302183 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -77,6 +77,16 @@
<&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
status = "disabled";
};
+
+ framebuffer@1 {
+ compatible = "allwinner,simple-framebuffer",
+ "simple-framebuffer";
+ allwinner,pipeline = "de_be0-lcd0-tve0";
+ clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
+ <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
+ <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
+ status = "disabled";
+ };
};
clocks {
@@ -120,6 +130,12 @@
ranges = <0 0x00000000 0xc000>;
};
+ emac_sram: sram-section@8000 {
+ compatible = "allwinner,sun4i-a10-sram-a3-a4";
+ reg = <0x8000 0x4000>;
+ status = "disabled";
+ };
+
sram_d: sram@00010000 {
compatible = "mmio-sram";
reg = <0x00010000 0x1000>;
@@ -171,6 +187,23 @@
#size-cells = <0>;
};
+ emac: ethernet@01c0b000 {
+ compatible = "allwinner,sun4i-a10-emac";
+ reg = <0x01c0b000 0x1000>;
+ interrupts = <55>;
+ clocks = <&ccu CLK_AHB_EMAC>;
+ allwinner,sram = <&emac_sram 1>;
+ status = "disabled";
+ };
+
+ mdio: mdio@01c0b080 {
+ compatible = "allwinner,sun4i-a10-mdio";
+ reg = <0x01c0b080 0x14>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
tcon0: lcd-controller@01c0c000 {
compatible = "allwinner,sun5i-a13-tcon";
reg = <0x01c0c000 0x1000>;
@@ -326,6 +359,15 @@
#interrupt-cells = <3>;
#gpio-cells = <3>;
+ emac_pins_a: emac0@0 {
+ pins = "PD6", "PD7", "PD10",
+ "PD11", "PD12", "PD13", "PD14",
+ "PD15", "PD18", "PD19", "PD20",
+ "PD21", "PD22", "PD23", "PD24",
+ "PD25", "PD26", "PD27";
+ function = "emac";
+ };
+
i2c0_pins_a: i2c0@0 {
pins = "PB0", "PB1";
function = "i2c0";
@@ -472,6 +514,16 @@
#thermal-sensor-cells = <0>;
};
+ uart0: serial@01c28000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28000 0x400>;
+ interrupts = <1>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_APB1_UART0>;
+ status = "disabled";
+ };
+
uart1: serial@01c28400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>;
@@ -482,6 +534,16 @@
status = "disabled";
};
+ uart2: serial@01c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <3>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_APB1_UART2>;
+ status = "disabled";
+ };
+
uart3: serial@01c28c00 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28c00 0x400>;
--
git-series 0.8.11
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 7/9] ARM: sun5i: a10s: Merge common controllers into the common DTSI
@ 2017-02-05 18:49 ` Maxime Ripard
0 siblings, 0 replies; 44+ messages in thread
From: Maxime Ripard @ 2017-02-05 18:49 UTC (permalink / raw)
To: linux-arm-kernel
Some controllers found in the A10s DTSI actually apply to all of the sun5i
family. Move those into the common DTSI so that all SoCs can benefit from
it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 70 +--------------------------------
arch/arm/boot/dts/sun5i.dtsi | 62 ++++++++++++++++++++++++++++-
2 files changed, 62 insertions(+), 70 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 5122d1179e59..074485782a4a 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -70,45 +70,9 @@
<&ccu CLK_DE_BE>, <&ccu CLK_HDMI>;
status = "disabled";
};
-
- framebuffer at 0 {
- compatible = "allwinner,simple-framebuffer",
- "simple-framebuffer";
- allwinner,pipeline = "de_be0-lcd0";
- clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
- <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
- status = "disabled";
- };
-
- framebuffer at 1 {
- compatible = "allwinner,simple-framebuffer",
- "simple-framebuffer";
- allwinner,pipeline = "de_be0-lcd0-tve0";
- clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
- <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
- <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
- status = "disabled";
- };
};
soc at 01c00000 {
- emac: ethernet at 01c0b000 {
- compatible = "allwinner,sun4i-a10-emac";
- reg = <0x01c0b000 0x1000>;
- interrupts = <55>;
- clocks = <&ccu CLK_AHB_EMAC>;
- allwinner,sram = <&emac_sram 1>;
- status = "disabled";
- };
-
- mdio: mdio at 01c0b080 {
- compatible = "allwinner,sun4i-a10-mdio";
- reg = <0x01c0b080 0x14>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
pwm: pwm at 01c20e00 {
compatible = "allwinner,sun5i-a10s-pwm";
reg = <0x01c20e00 0xc>;
@@ -116,26 +80,6 @@
#pwm-cells = <3>;
status = "disabled";
};
-
- uart0: serial at 01c28000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28000 0x400>;
- interrupts = <1>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_APB1_UART0>;
- status = "disabled";
- };
-
- uart2: serial at 01c28800 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28800 0x400>;
- interrupts = <3>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_APB1_UART2>;
- status = "disabled";
- };
};
};
@@ -165,15 +109,6 @@
function = "emac";
};
- emac_pins_a: emac0 at 0 {
- pins = "PD6", "PD7", "PD10",
- "PD11", "PD12", "PD13", "PD14",
- "PD15", "PD18", "PD19", "PD20",
- "PD21", "PD22", "PD23", "PD24",
- "PD25", "PD26", "PD27";
- function = "emac";
- };
-
mmc1_pins_a: mmc1 at 0 {
pins = "PG3", "PG4", "PG5",
"PG6", "PG7", "PG8";
@@ -193,9 +128,4 @@
};
&sram_a {
- emac_sram: sram-section at 8000 {
- compatible = "allwinner,sun4i-a10-sram-a3-a4";
- reg = <0x8000 0x4000>;
- status = "disabled";
- };
};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index f27ca0be5835..9ba0c0302183 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -77,6 +77,16 @@
<&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
status = "disabled";
};
+
+ framebuffer at 1 {
+ compatible = "allwinner,simple-framebuffer",
+ "simple-framebuffer";
+ allwinner,pipeline = "de_be0-lcd0-tve0";
+ clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
+ <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
+ <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
+ status = "disabled";
+ };
};
clocks {
@@ -120,6 +130,12 @@
ranges = <0 0x00000000 0xc000>;
};
+ emac_sram: sram-section at 8000 {
+ compatible = "allwinner,sun4i-a10-sram-a3-a4";
+ reg = <0x8000 0x4000>;
+ status = "disabled";
+ };
+
sram_d: sram at 00010000 {
compatible = "mmio-sram";
reg = <0x00010000 0x1000>;
@@ -171,6 +187,23 @@
#size-cells = <0>;
};
+ emac: ethernet at 01c0b000 {
+ compatible = "allwinner,sun4i-a10-emac";
+ reg = <0x01c0b000 0x1000>;
+ interrupts = <55>;
+ clocks = <&ccu CLK_AHB_EMAC>;
+ allwinner,sram = <&emac_sram 1>;
+ status = "disabled";
+ };
+
+ mdio: mdio at 01c0b080 {
+ compatible = "allwinner,sun4i-a10-mdio";
+ reg = <0x01c0b080 0x14>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
tcon0: lcd-controller at 01c0c000 {
compatible = "allwinner,sun5i-a13-tcon";
reg = <0x01c0c000 0x1000>;
@@ -326,6 +359,15 @@
#interrupt-cells = <3>;
#gpio-cells = <3>;
+ emac_pins_a: emac0 at 0 {
+ pins = "PD6", "PD7", "PD10",
+ "PD11", "PD12", "PD13", "PD14",
+ "PD15", "PD18", "PD19", "PD20",
+ "PD21", "PD22", "PD23", "PD24",
+ "PD25", "PD26", "PD27";
+ function = "emac";
+ };
+
i2c0_pins_a: i2c0 at 0 {
pins = "PB0", "PB1";
function = "i2c0";
@@ -472,6 +514,16 @@
#thermal-sensor-cells = <0>;
};
+ uart0: serial at 01c28000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28000 0x400>;
+ interrupts = <1>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_APB1_UART0>;
+ status = "disabled";
+ };
+
uart1: serial at 01c28400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>;
@@ -482,6 +534,16 @@
status = "disabled";
};
+ uart2: serial at 01c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <3>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_APB1_UART2>;
+ status = "disabled";
+ };
+
uart3: serial at 01c28c00 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28c00 0x400>;
--
git-series 0.8.11
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 8/9] ARM: sun5i: r8: Merge common controllers into the common DTSI
2017-02-05 18:49 ` Maxime Ripard
@ 2017-02-05 18:49 ` Maxime Ripard
-1 siblings, 0 replies; 44+ messages in thread
From: Maxime Ripard @ 2017-02-05 18:49 UTC (permalink / raw)
To: Chen-Yu Tsai, Maxime Ripard; +Cc: linux-arm-kernel, linux-kernel
Some controllers found in the R8 DTSI actually apply to all of the sun5i
family. Move those into the common DTSI so that all SoCs can benefit from
it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-r8.dtsi | 40 +----------------------------------
arch/arm/boot/dts/sun5i.dtsi | 23 ++++++++++++++++++++-
2 files changed, 23 insertions(+), 40 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi
index 4c1141396c99..de35dbcd1191 100644
--- a/arch/arm/boot/dts/sun5i-r8.dtsi
+++ b/arch/arm/boot/dts/sun5i-r8.dtsi
@@ -45,43 +45,3 @@
#include "sun5i-a13.dtsi"
-/ {
- chosen {
- framebuffer@1 {
- compatible = "allwinner,simple-framebuffer",
- "simple-framebuffer";
- allwinner,pipeline = "de_be0-lcd0-tve0";
- clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
- <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
- <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
- status = "disabled";
- };
- };
-
- soc@01c00000 {
- tve0: tv-encoder@01c0a000 {
- compatible = "allwinner,sun4i-a10-tv-encoder";
- reg = <0x01c0a000 0x1000>;
- clocks = <&ccu CLK_AHB_TVE>;
- resets = <&ccu RST_TVE>;
- status = "disabled";
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- tve0_in_tcon0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&tcon0_out_tve0>;
- };
- };
- };
- };
-};
-
-&tcon0_out {
- tcon0_out_tve0: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&tve0_in_tcon0>;
- };
-};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 9ba0c0302183..c8e2253cac1d 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -187,6 +187,24 @@
#size-cells = <0>;
};
+ tve0: tv-encoder@01c0a000 {
+ compatible = "allwinner,sun4i-a10-tv-encoder";
+ reg = <0x01c0a000 0x1000>;
+ clocks = <&ccu CLK_AHB_TVE>;
+ resets = <&ccu RST_TVE>;
+ status = "disabled";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tve0_in_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_out_tve0>;
+ };
+ };
+ };
+
emac: ethernet@01c0b000 {
compatible = "allwinner,sun4i-a10-emac";
reg = <0x01c0b000 0x1000>;
@@ -238,6 +256,11 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
+
+ tcon0_out_tve0: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tve0_in_tcon0>;
+ };
};
};
};
--
git-series 0.8.11
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 8/9] ARM: sun5i: r8: Merge common controllers into the common DTSI
@ 2017-02-05 18:49 ` Maxime Ripard
0 siblings, 0 replies; 44+ messages in thread
From: Maxime Ripard @ 2017-02-05 18:49 UTC (permalink / raw)
To: linux-arm-kernel
Some controllers found in the R8 DTSI actually apply to all of the sun5i
family. Move those into the common DTSI so that all SoCs can benefit from
it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-r8.dtsi | 40 +----------------------------------
arch/arm/boot/dts/sun5i.dtsi | 23 ++++++++++++++++++++-
2 files changed, 23 insertions(+), 40 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi
index 4c1141396c99..de35dbcd1191 100644
--- a/arch/arm/boot/dts/sun5i-r8.dtsi
+++ b/arch/arm/boot/dts/sun5i-r8.dtsi
@@ -45,43 +45,3 @@
#include "sun5i-a13.dtsi"
-/ {
- chosen {
- framebuffer at 1 {
- compatible = "allwinner,simple-framebuffer",
- "simple-framebuffer";
- allwinner,pipeline = "de_be0-lcd0-tve0";
- clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
- <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
- <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
- status = "disabled";
- };
- };
-
- soc at 01c00000 {
- tve0: tv-encoder at 01c0a000 {
- compatible = "allwinner,sun4i-a10-tv-encoder";
- reg = <0x01c0a000 0x1000>;
- clocks = <&ccu CLK_AHB_TVE>;
- resets = <&ccu RST_TVE>;
- status = "disabled";
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- tve0_in_tcon0: endpoint at 0 {
- reg = <0>;
- remote-endpoint = <&tcon0_out_tve0>;
- };
- };
- };
- };
-};
-
-&tcon0_out {
- tcon0_out_tve0: endpoint at 1 {
- reg = <1>;
- remote-endpoint = <&tve0_in_tcon0>;
- };
-};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 9ba0c0302183..c8e2253cac1d 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -187,6 +187,24 @@
#size-cells = <0>;
};
+ tve0: tv-encoder at 01c0a000 {
+ compatible = "allwinner,sun4i-a10-tv-encoder";
+ reg = <0x01c0a000 0x1000>;
+ clocks = <&ccu CLK_AHB_TVE>;
+ resets = <&ccu RST_TVE>;
+ status = "disabled";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tve0_in_tcon0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_out_tve0>;
+ };
+ };
+ };
+
emac: ethernet at 01c0b000 {
compatible = "allwinner,sun4i-a10-emac";
reg = <0x01c0b000 0x1000>;
@@ -238,6 +256,11 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
+
+ tcon0_out_tve0: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&tve0_in_tcon0>;
+ };
};
};
};
--
git-series 0.8.11
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 9/9] ARM: sun5i: gr8: Use common sun5i DTSI
2017-02-05 18:49 ` Maxime Ripard
@ 2017-02-05 18:49 ` Maxime Ripard
-1 siblings, 0 replies; 44+ messages in thread
From: Maxime Ripard @ 2017-02-05 18:49 UTC (permalink / raw)
To: Chen-Yu Tsai, Maxime Ripard; +Cc: linux-arm-kernel, linux-kernel
Most of the GR8 DTSI is duplicated with the common sun5i DTSI, and some of
the extra nodes defined there actually apply to all of the sun5i family.
Move those into the common DTSI so that all SoCs can benefit from it, and
include the sun5i DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-gr8-chip-pro.dts | 2 +-
arch/arm/boot/dts/sun5i-gr8-evb.dts | 2 +-
arch/arm/boot/dts/sun5i-gr8.dtsi | 617 +-----------------------
arch/arm/boot/dts/sun5i.dtsi | 45 ++-
4 files changed, 76 insertions(+), 590 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
index 0cf0813d363a..e5eb46b500ae 100644
--- a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
+++ b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
@@ -220,7 +220,7 @@
&uart1 {
pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins_a>, <&uart1_cts_rts_pins_a>;
+ pinctrl-0 = <&uart1_pins_b>, <&uart1_cts_rts_pins_a>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun5i-gr8-evb.dts b/arch/arm/boot/dts/sun5i-gr8-evb.dts
index 1a845af4d4db..ebd8388e2ba1 100644
--- a/arch/arm/boot/dts/sun5i-gr8-evb.dts
+++ b/arch/arm/boot/dts/sun5i-gr8-evb.dts
@@ -332,7 +332,7 @@
&uart1 {
pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins_a>, <&uart1_cts_rts_pins_a>;
+ pinctrl-0 = <&uart1_pins_b>, <&uart1_cts_rts_pins_a>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun5i-gr8.dtsi b/arch/arm/boot/dts/sun5i-gr8.dtsi
index cb9b2aaf7297..8921af3bf1ef 100644
--- a/arch/arm/boot/dts/sun5i-gr8.dtsi
+++ b/arch/arm/boot/dts/sun5i-gr8.dtsi
@@ -42,429 +42,20 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#include "sun5i.dtsi"
+
#include <dt-bindings/clock/sun5i-ccu.h>
#include <dt-bindings/dma/sun4i-a10.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
#include <dt-bindings/reset/sun5i-ccu.h>
/ {
- interrupt-parent = <&intc>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a8";
- reg = <0x0>;
- clocks = <&ccu CLK_CPU>;
- };
- };
-
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- osc24M: clk@01c20050 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "osc24M";
- };
-
- osc32k: clk@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "osc32k";
- };
- };
-
display-engine {
compatible = "allwinner,sun5i-a13-display-engine";
allwinner,pipelines = <&fe0>;
};
soc@01c00000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- sram-controller@01c00000 {
- compatible = "allwinner,sun4i-a10-sram-controller";
- reg = <0x01c00000 0x30>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- sram_a: sram@00000000 {
- compatible = "mmio-sram";
- reg = <0x00000000 0xc000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x00000000 0xc000>;
- };
-
- sram_d: sram@00010000 {
- compatible = "mmio-sram";
- reg = <0x00010000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x00010000 0x1000>;
-
- otg_sram: sram-section@0000 {
- compatible = "allwinner,sun4i-a10-sram-d";
- reg = <0x0000 0x1000>;
- status = "disabled";
- };
- };
- };
-
- dma: dma-controller@01c02000 {
- compatible = "allwinner,sun4i-a10-dma";
- reg = <0x01c02000 0x1000>;
- interrupts = <27>;
- clocks = <&ccu CLK_AHB_DMA>;
- #dma-cells = <2>;
- };
-
- nfc: nand@01c03000 {
- compatible = "allwinner,sun4i-a10-nand";
- reg = <0x01c03000 0x1000>;
- interrupts = <37>;
- clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
- clock-names = "ahb", "mod";
- dmas = <&dma SUN4I_DMA_DEDICATED 3>;
- dma-names = "rxtx";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- spi0: spi@01c05000 {
- compatible = "allwinner,sun4i-a10-spi";
- reg = <0x01c05000 0x1000>;
- interrupts = <10>;
- clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
- clock-names = "ahb", "mod";
- dmas = <&dma SUN4I_DMA_DEDICATED 27>,
- <&dma SUN4I_DMA_DEDICATED 26>;
- dma-names = "rx", "tx";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- spi1: spi@01c06000 {
- compatible = "allwinner,sun4i-a10-spi";
- reg = <0x01c06000 0x1000>;
- interrupts = <11>;
- clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
- clock-names = "ahb", "mod";
- dmas = <&dma SUN4I_DMA_DEDICATED 9>,
- <&dma SUN4I_DMA_DEDICATED 8>;
- dma-names = "rx", "tx";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- tve0: tv-encoder@01c0a000 {
- compatible = "allwinner,sun4i-a10-tv-encoder";
- reg = <0x01c0a000 0x1000>;
- clocks = <&ccu CLK_AHB_TVE>;
- resets = <&ccu RST_TVE>;
- status = "disabled";
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- tve0_in_tcon0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&tcon0_out_tve0>;
- };
- };
- };
-
- tcon0: lcd-controller@01c0c000 {
- compatible = "allwinner,sun5i-a13-tcon";
- reg = <0x01c0c000 0x1000>;
- interrupts = <44>;
- resets = <&ccu RST_LCD>;
- reset-names = "lcd";
- clocks = <&ccu CLK_AHB_LCD>,
- <&ccu CLK_TCON_CH0>,
- <&ccu CLK_TCON_CH1>;
- clock-names = "ahb",
- "tcon-ch0",
- "tcon-ch1";
- clock-output-names = "tcon-pixel-clock";
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- tcon0_in: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- tcon0_in_be0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&be0_out_tcon0>;
- };
- };
-
- tcon0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- tcon0_out_tve0: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&tve0_in_tcon0>;
- };
- };
- };
- };
-
- mmc0: mmc@01c0f000 {
- compatible = "allwinner,sun5i-a13-mmc";
- reg = <0x01c0f000 0x1000>;
- clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
- clock-names = "ahb", "mmc";
- interrupts = <32>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- mmc1: mmc@01c10000 {
- compatible = "allwinner,sun5i-a13-mmc";
- reg = <0x01c10000 0x1000>;
- clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
- clock-names = "ahb", "mmc";
- interrupts = <33>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- mmc2: mmc@01c11000 {
- compatible = "allwinner,sun5i-a13-mmc";
- reg = <0x01c11000 0x1000>;
- clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
- clock-names = "ahb", "mmc";
- interrupts = <34>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- usb_otg: usb@01c13000 {
- compatible = "allwinner,sun4i-a10-musb";
- reg = <0x01c13000 0x0400>;
- clocks = <&ccu CLK_AHB_OTG>;
- interrupts = <38>;
- interrupt-names = "mc";
- phys = <&usbphy 0>;
- phy-names = "usb";
- extcon = <&usbphy 0>;
- allwinner,sram = <&otg_sram 1>;
- status = "disabled";
-
- dr_mode = "otg";
- };
-
- usbphy: phy@01c13400 {
- #phy-cells = <1>;
- compatible = "allwinner,sun5i-a13-usb-phy";
- reg = <0x01c13400 0x10 0x01c14800 0x4>;
- reg-names = "phy_ctrl", "pmu1";
- clocks = <&ccu CLK_USB_PHY0>;
- clock-names = "usb_phy";
- resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
- reset-names = "usb0_reset", "usb1_reset";
- status = "disabled";
- };
-
- ehci0: usb@01c14000 {
- compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
- reg = <0x01c14000 0x100>;
- interrupts = <39>;
- clocks = <&ccu CLK_AHB_EHCI>;
- phys = <&usbphy 1>;
- phy-names = "usb";
- status = "disabled";
- };
-
- ohci0: usb@01c14400 {
- compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
- reg = <0x01c14400 0x100>;
- interrupts = <40>;
- clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
- phys = <&usbphy 1>;
- phy-names = "usb";
- status = "disabled";
- };
-
- spi2: spi@01c17000 {
- compatible = "allwinner,sun4i-a10-spi";
- reg = <0x01c17000 0x1000>;
- interrupts = <12>;
- clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
- clock-names = "ahb", "mod";
- dmas = <&dma SUN4I_DMA_DEDICATED 29>,
- <&dma SUN4I_DMA_DEDICATED 28>;
- dma-names = "rx", "tx";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- ccu: clock@01c20000 {
- compatible = "nextthing,gr8-ccu";
- reg = <0x01c20000 0x400>;
- clocks = <&osc24M>, <&osc32k>;
- clock-names = "hosc", "losc";
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- intc: interrupt-controller@01c20400 {
- compatible = "allwinner,sun4i-a10-ic";
- reg = <0x01c20400 0x400>;
- interrupt-controller;
- #interrupt-cells = <1>;
- };
-
- pio: pinctrl@01c20800 {
- compatible = "nextthing,gr8-pinctrl";
- reg = <0x01c20800 0x400>;
- interrupts = <28>;
- clocks = <&ccu CLK_APB0_PIO>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <3>;
- #gpio-cells = <3>;
-
- i2c0_pins_a: i2c0@0 {
- pins = "PB0", "PB1";
- function = "i2c0";
- };
-
- i2c1_pins_a: i2c1@0 {
- pins = "PB15", "PB16";
- function = "i2c1";
- };
-
- i2c2_pins_a: i2c2@0 {
- pins = "PB17", "PB18";
- function = "i2c2";
- };
-
- i2s0_data_pins_a: i2s0-data@0 {
- pins = "PB6", "PB7", "PB8", "PB9";
- function = "i2s0";
- };
-
- i2s0_mclk_pins_a: i2s0-mclk@0 {
- pins = "PB5";
- function = "i2s0";
- };
-
- ir0_rx_pins_a: ir0@0 {
- pins = "PB4";
- function = "ir0";
- };
-
- lcd_rgb666_pins: lcd-rgb666@0 {
- pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
- "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
- "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
- "PD24", "PD25", "PD26", "PD27";
- function = "lcd0";
- };
-
- mmc0_pins_a: mmc0@0 {
- pins = "PF0", "PF1", "PF2", "PF3",
- "PF4", "PF5";
- function = "mmc0";
- drive-strength = <30>;
- };
-
- nand_pins_a: nand-base0@0 {
- pins = "PC0", "PC1", "PC2",
- "PC5", "PC8", "PC9", "PC10",
- "PC11", "PC12", "PC13", "PC14",
- "PC15";
- function = "nand0";
- };
-
- nand_cs0_pins_a: nand-cs@0 {
- pins = "PC4";
- function = "nand0";
- };
-
- nand_rb0_pins_a: nand-rb@0 {
- pins = "PC6";
- function = "nand0";
- };
-
- pwm0_pins_a: pwm0@0 {
- pins = "PB2";
- function = "pwm0";
- };
-
- pwm1_pins: pwm1 {
- pins = "PG13";
- function = "pwm1";
- };
-
- spdif_tx_pins_a: spdif@0 {
- pins = "PB10";
- function = "spdif";
- bias-pull-up;
- };
-
- uart1_pins_a: uart1@1 {
- pins = "PG3", "PG4";
- function = "uart1";
- };
-
- uart1_cts_rts_pins_a: uart1-cts-rts@0 {
- pins = "PG5", "PG6";
- function = "uart1";
- };
-
- uart2_pins_a: uart2@1 {
- pins = "PD2", "PD3";
- function = "uart2";
- };
-
- uart2_cts_rts_pins_a: uart2-cts-rts@0 {
- pins = "PD4", "PD5";
- function = "uart2";
- };
-
- uart3_pins_a: uart3@1 {
- pins = "PG9", "PG10";
- function = "uart3";
- };
-
- uart3_cts_rts_pins_a: uart3-cts-rts@0 {
- pins = "PG11", "PG12";
- function = "uart3";
- };
- };
-
pwm: pwm@01c20e00 {
compatible = "allwinner,sun5i-a10s-pwm";
reg = <0x01c20e00 0xc>;
@@ -473,18 +64,6 @@
status = "disabled";
};
- timer@01c20c00 {
- compatible = "allwinner,sun4i-a10-timer";
- reg = <0x01c20c00 0x90>;
- interrupts = <22>;
- clocks = <&ccu CLK_HOSC>;
- };
-
- wdt: watchdog@01c20c90 {
- compatible = "allwinner,sun4i-a10-wdt";
- reg = <0x01c20c90 0x10>;
- };
-
spdif: spdif@01c21000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun4i-a10-spdif";
@@ -498,15 +77,6 @@
status = "disabled";
};
- ir0: ir@01c21800 {
- compatible = "allwinner,sun4i-a10-ir";
- clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;
- clock-names = "apb", "ir";
- interrupts = <5>;
- reg = <0x01c21800 0x40>;
- status = "disabled";
- };
-
i2s0: i2s@01c22400 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun4i-a10-i2s";
@@ -519,168 +89,39 @@
dma-names = "rx", "tx";
status = "disabled";
};
+ };
+};
- lradc: lradc@01c22800 {
- compatible = "allwinner,sun4i-a10-lradc-keys";
- reg = <0x01c22800 0x100>;
- interrupts = <31>;
- status = "disabled";
- };
-
- codec: codec@01c22c00 {
- #sound-dai-cells = <0>;
- compatible = "allwinner,sun4i-a10-codec";
- reg = <0x01c22c00 0x40>;
- interrupts = <30>;
- clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
- clock-names = "apb", "codec";
- dmas = <&dma SUN4I_DMA_NORMAL 19>,
- <&dma SUN4I_DMA_NORMAL 19>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- rtp: rtp@01c25000 {
- compatible = "allwinner,sun5i-a13-ts";
- reg = <0x01c25000 0x100>;
- interrupts = <29>;
- #thermal-sensor-cells = <0>;
- };
-
- uart1: serial@01c28400 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28400 0x400>;
- interrupts = <2>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_APB1_UART1>;
- status = "disabled";
- };
-
- uart2: serial@01c28800 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28800 0x400>;
- interrupts = <3>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_APB1_UART2>;
- status = "disabled";
- };
-
- uart3: serial@01c28c00 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28c00 0x400>;
- interrupts = <4>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_APB1_UART3>;
- status = "disabled";
- };
-
- i2c0: i2c@01c2ac00 {
- compatible = "allwinner,sun4i-a10-i2c";
- reg = <0x01c2ac00 0x400>;
- interrupts = <7>;
- clocks = <&ccu CLK_APB1_I2C0>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c1: i2c@01c2b000 {
- compatible = "allwinner,sun4i-a10-i2c";
- reg = <0x01c2b000 0x400>;
- interrupts = <8>;
- clocks = <&ccu CLK_APB1_I2C1>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c2: i2c@01c2b400 {
- compatible = "allwinner,sun4i-a10-i2c";
- reg = <0x01c2b400 0x400>;
- interrupts = <9>;
- clocks = <&ccu CLK_APB1_I2C2>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- timer@01c60000 {
- compatible = "allwinner,sun5i-a13-hstimer";
- reg = <0x01c60000 0x1000>;
- interrupts = <82>, <83>;
- clocks = <&ccu CLK_AHB_HSTIMER>;
- };
-
- fe0: display-frontend@01e00000 {
- compatible = "allwinner,sun5i-a13-display-frontend";
- reg = <0x01e00000 0x20000>;
- interrupts = <47>;
- clocks = <&ccu CLK_AHB_DE_FE>, <&ccu CLK_DE_FE>,
- <&ccu CLK_DRAM_DE_FE>;
- clock-names = "ahb", "mod",
- "ram";
- resets = <&ccu RST_DE_FE>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- fe0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- fe0_out_be0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&be0_in_fe0>;
- };
- };
- };
- };
-
- be0: display-backend@01e60000 {
- compatible = "allwinner,sun5i-a13-display-backend";
- reg = <0x01e60000 0x10000>;
- clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
- <&ccu CLK_DRAM_DE_BE>;
- clock-names = "ahb", "mod",
- "ram";
- resets = <&ccu RST_DE_BE>;
- status = "disabled";
+&ccu {
+ compatible = "nextthing,gr8-ccu";
+};
- assigned-clocks = <&ccu CLK_DE_BE>;
- assigned-clock-rates = <300000000>;
+&pio {
+ compatible = "nextthing,gr8-pinctrl";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
+ i2s0_data_pins_a: i2s0-data@0 {
+ pins = "PB6", "PB7", "PB8", "PB9";
+ function = "i2s0";
+ };
- be0_in: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
+ i2s0_mclk_pins_a: i2s0-mclk@0 {
+ pins = "PB5";
+ function = "i2s0";
+ };
- be0_in_fe0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&fe0_out_be0>;
- };
- };
+ pwm1_pins: pwm1 {
+ pins = "PG13";
+ function = "pwm1";
+ };
- be0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
+ spdif_tx_pins_a: spdif@0 {
+ pins = "PB10";
+ function = "spdif";
+ bias-pull-up;
+ };
- be0_out_tcon0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&tcon0_in_be0>;
- };
- };
- };
- };
+ uart1_cts_rts_pins_a: uart1-cts-rts@0 {
+ pins = "PG5", "PG6";
+ function = "uart1";
};
};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index c8e2253cac1d..14bd50169cbe 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -159,6 +159,19 @@
#dma-cells = <2>;
};
+ nfc: nand@01c03000 {
+ compatible = "allwinner,sun4i-a10-nand";
+ reg = <0x01c03000 0x1000>;
+ interrupts = <37>;
+ clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma SUN4I_DMA_DEDICATED 3>;
+ dma-names = "rxtx";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
spi0: spi@01c05000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c05000 0x1000>;
@@ -406,6 +419,11 @@
function = "i2c2";
};
+ ir0_rx_pins_a: ir0@0 {
+ pins = "PB4";
+ function = "ir0";
+ };
+
lcd_rgb565_pins: lcd_rgb565@0 {
pins = "PD3", "PD4", "PD5", "PD6", "PD7",
"PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
@@ -447,6 +465,24 @@
bias-pull-up;
};
+ nand_pins_a: nand-base0@0 {
+ pins = "PC0", "PC1", "PC2",
+ "PC5", "PC8", "PC9", "PC10",
+ "PC11", "PC12", "PC13", "PC14",
+ "PC15";
+ function = "nand0";
+ };
+
+ nand_cs0_pins_a: nand-cs@0 {
+ pins = "PC4";
+ function = "nand0";
+ };
+
+ nand_rb0_pins_a: nand-rb@0 {
+ pins = "PC6";
+ function = "nand0";
+ };
+
pwm0_pins_a: pwm0@0 {
pins = "PB2";
function = "pwm0";
@@ -505,6 +541,15 @@
reg = <0x01c20c90 0x10>;
};
+ ir0: ir@01c21800 {
+ compatible = "allwinner,sun4i-a10-ir";
+ clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;
+ clock-names = "apb", "ir";
+ interrupts = <5>;
+ reg = <0x01c21800 0x40>;
+ status = "disabled";
+ };
+
lradc: lradc@01c22800 {
compatible = "allwinner,sun4i-a10-lradc-keys";
reg = <0x01c22800 0x100>;
--
git-series 0.8.11
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 9/9] ARM: sun5i: gr8: Use common sun5i DTSI
@ 2017-02-05 18:49 ` Maxime Ripard
0 siblings, 0 replies; 44+ messages in thread
From: Maxime Ripard @ 2017-02-05 18:49 UTC (permalink / raw)
To: linux-arm-kernel
Most of the GR8 DTSI is duplicated with the common sun5i DTSI, and some of
the extra nodes defined there actually apply to all of the sun5i family.
Move those into the common DTSI so that all SoCs can benefit from it, and
include the sun5i DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-gr8-chip-pro.dts | 2 +-
arch/arm/boot/dts/sun5i-gr8-evb.dts | 2 +-
arch/arm/boot/dts/sun5i-gr8.dtsi | 617 +-----------------------
arch/arm/boot/dts/sun5i.dtsi | 45 ++-
4 files changed, 76 insertions(+), 590 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
index 0cf0813d363a..e5eb46b500ae 100644
--- a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
+++ b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
@@ -220,7 +220,7 @@
&uart1 {
pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins_a>, <&uart1_cts_rts_pins_a>;
+ pinctrl-0 = <&uart1_pins_b>, <&uart1_cts_rts_pins_a>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun5i-gr8-evb.dts b/arch/arm/boot/dts/sun5i-gr8-evb.dts
index 1a845af4d4db..ebd8388e2ba1 100644
--- a/arch/arm/boot/dts/sun5i-gr8-evb.dts
+++ b/arch/arm/boot/dts/sun5i-gr8-evb.dts
@@ -332,7 +332,7 @@
&uart1 {
pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins_a>, <&uart1_cts_rts_pins_a>;
+ pinctrl-0 = <&uart1_pins_b>, <&uart1_cts_rts_pins_a>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun5i-gr8.dtsi b/arch/arm/boot/dts/sun5i-gr8.dtsi
index cb9b2aaf7297..8921af3bf1ef 100644
--- a/arch/arm/boot/dts/sun5i-gr8.dtsi
+++ b/arch/arm/boot/dts/sun5i-gr8.dtsi
@@ -42,429 +42,20 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#include "sun5i.dtsi"
+
#include <dt-bindings/clock/sun5i-ccu.h>
#include <dt-bindings/dma/sun4i-a10.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
#include <dt-bindings/reset/sun5i-ccu.h>
/ {
- interrupt-parent = <&intc>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu at 0 {
- device_type = "cpu";
- compatible = "arm,cortex-a8";
- reg = <0x0>;
- clocks = <&ccu CLK_CPU>;
- };
- };
-
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- osc24M: clk at 01c20050 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "osc24M";
- };
-
- osc32k: clk at 0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "osc32k";
- };
- };
-
display-engine {
compatible = "allwinner,sun5i-a13-display-engine";
allwinner,pipelines = <&fe0>;
};
soc at 01c00000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- sram-controller at 01c00000 {
- compatible = "allwinner,sun4i-a10-sram-controller";
- reg = <0x01c00000 0x30>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- sram_a: sram at 00000000 {
- compatible = "mmio-sram";
- reg = <0x00000000 0xc000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x00000000 0xc000>;
- };
-
- sram_d: sram at 00010000 {
- compatible = "mmio-sram";
- reg = <0x00010000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x00010000 0x1000>;
-
- otg_sram: sram-section at 0000 {
- compatible = "allwinner,sun4i-a10-sram-d";
- reg = <0x0000 0x1000>;
- status = "disabled";
- };
- };
- };
-
- dma: dma-controller at 01c02000 {
- compatible = "allwinner,sun4i-a10-dma";
- reg = <0x01c02000 0x1000>;
- interrupts = <27>;
- clocks = <&ccu CLK_AHB_DMA>;
- #dma-cells = <2>;
- };
-
- nfc: nand at 01c03000 {
- compatible = "allwinner,sun4i-a10-nand";
- reg = <0x01c03000 0x1000>;
- interrupts = <37>;
- clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
- clock-names = "ahb", "mod";
- dmas = <&dma SUN4I_DMA_DEDICATED 3>;
- dma-names = "rxtx";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- spi0: spi at 01c05000 {
- compatible = "allwinner,sun4i-a10-spi";
- reg = <0x01c05000 0x1000>;
- interrupts = <10>;
- clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
- clock-names = "ahb", "mod";
- dmas = <&dma SUN4I_DMA_DEDICATED 27>,
- <&dma SUN4I_DMA_DEDICATED 26>;
- dma-names = "rx", "tx";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- spi1: spi at 01c06000 {
- compatible = "allwinner,sun4i-a10-spi";
- reg = <0x01c06000 0x1000>;
- interrupts = <11>;
- clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
- clock-names = "ahb", "mod";
- dmas = <&dma SUN4I_DMA_DEDICATED 9>,
- <&dma SUN4I_DMA_DEDICATED 8>;
- dma-names = "rx", "tx";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- tve0: tv-encoder at 01c0a000 {
- compatible = "allwinner,sun4i-a10-tv-encoder";
- reg = <0x01c0a000 0x1000>;
- clocks = <&ccu CLK_AHB_TVE>;
- resets = <&ccu RST_TVE>;
- status = "disabled";
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- tve0_in_tcon0: endpoint at 0 {
- reg = <0>;
- remote-endpoint = <&tcon0_out_tve0>;
- };
- };
- };
-
- tcon0: lcd-controller at 01c0c000 {
- compatible = "allwinner,sun5i-a13-tcon";
- reg = <0x01c0c000 0x1000>;
- interrupts = <44>;
- resets = <&ccu RST_LCD>;
- reset-names = "lcd";
- clocks = <&ccu CLK_AHB_LCD>,
- <&ccu CLK_TCON_CH0>,
- <&ccu CLK_TCON_CH1>;
- clock-names = "ahb",
- "tcon-ch0",
- "tcon-ch1";
- clock-output-names = "tcon-pixel-clock";
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- tcon0_in: port at 0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- tcon0_in_be0: endpoint at 0 {
- reg = <0>;
- remote-endpoint = <&be0_out_tcon0>;
- };
- };
-
- tcon0_out: port at 1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- tcon0_out_tve0: endpoint at 1 {
- reg = <1>;
- remote-endpoint = <&tve0_in_tcon0>;
- };
- };
- };
- };
-
- mmc0: mmc at 01c0f000 {
- compatible = "allwinner,sun5i-a13-mmc";
- reg = <0x01c0f000 0x1000>;
- clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
- clock-names = "ahb", "mmc";
- interrupts = <32>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- mmc1: mmc at 01c10000 {
- compatible = "allwinner,sun5i-a13-mmc";
- reg = <0x01c10000 0x1000>;
- clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
- clock-names = "ahb", "mmc";
- interrupts = <33>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- mmc2: mmc at 01c11000 {
- compatible = "allwinner,sun5i-a13-mmc";
- reg = <0x01c11000 0x1000>;
- clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
- clock-names = "ahb", "mmc";
- interrupts = <34>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- usb_otg: usb at 01c13000 {
- compatible = "allwinner,sun4i-a10-musb";
- reg = <0x01c13000 0x0400>;
- clocks = <&ccu CLK_AHB_OTG>;
- interrupts = <38>;
- interrupt-names = "mc";
- phys = <&usbphy 0>;
- phy-names = "usb";
- extcon = <&usbphy 0>;
- allwinner,sram = <&otg_sram 1>;
- status = "disabled";
-
- dr_mode = "otg";
- };
-
- usbphy: phy at 01c13400 {
- #phy-cells = <1>;
- compatible = "allwinner,sun5i-a13-usb-phy";
- reg = <0x01c13400 0x10 0x01c14800 0x4>;
- reg-names = "phy_ctrl", "pmu1";
- clocks = <&ccu CLK_USB_PHY0>;
- clock-names = "usb_phy";
- resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
- reset-names = "usb0_reset", "usb1_reset";
- status = "disabled";
- };
-
- ehci0: usb at 01c14000 {
- compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
- reg = <0x01c14000 0x100>;
- interrupts = <39>;
- clocks = <&ccu CLK_AHB_EHCI>;
- phys = <&usbphy 1>;
- phy-names = "usb";
- status = "disabled";
- };
-
- ohci0: usb at 01c14400 {
- compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
- reg = <0x01c14400 0x100>;
- interrupts = <40>;
- clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
- phys = <&usbphy 1>;
- phy-names = "usb";
- status = "disabled";
- };
-
- spi2: spi at 01c17000 {
- compatible = "allwinner,sun4i-a10-spi";
- reg = <0x01c17000 0x1000>;
- interrupts = <12>;
- clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
- clock-names = "ahb", "mod";
- dmas = <&dma SUN4I_DMA_DEDICATED 29>,
- <&dma SUN4I_DMA_DEDICATED 28>;
- dma-names = "rx", "tx";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- ccu: clock at 01c20000 {
- compatible = "nextthing,gr8-ccu";
- reg = <0x01c20000 0x400>;
- clocks = <&osc24M>, <&osc32k>;
- clock-names = "hosc", "losc";
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- intc: interrupt-controller at 01c20400 {
- compatible = "allwinner,sun4i-a10-ic";
- reg = <0x01c20400 0x400>;
- interrupt-controller;
- #interrupt-cells = <1>;
- };
-
- pio: pinctrl at 01c20800 {
- compatible = "nextthing,gr8-pinctrl";
- reg = <0x01c20800 0x400>;
- interrupts = <28>;
- clocks = <&ccu CLK_APB0_PIO>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <3>;
- #gpio-cells = <3>;
-
- i2c0_pins_a: i2c0 at 0 {
- pins = "PB0", "PB1";
- function = "i2c0";
- };
-
- i2c1_pins_a: i2c1 at 0 {
- pins = "PB15", "PB16";
- function = "i2c1";
- };
-
- i2c2_pins_a: i2c2 at 0 {
- pins = "PB17", "PB18";
- function = "i2c2";
- };
-
- i2s0_data_pins_a: i2s0-data at 0 {
- pins = "PB6", "PB7", "PB8", "PB9";
- function = "i2s0";
- };
-
- i2s0_mclk_pins_a: i2s0-mclk at 0 {
- pins = "PB5";
- function = "i2s0";
- };
-
- ir0_rx_pins_a: ir0 at 0 {
- pins = "PB4";
- function = "ir0";
- };
-
- lcd_rgb666_pins: lcd-rgb666 at 0 {
- pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
- "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
- "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
- "PD24", "PD25", "PD26", "PD27";
- function = "lcd0";
- };
-
- mmc0_pins_a: mmc0 at 0 {
- pins = "PF0", "PF1", "PF2", "PF3",
- "PF4", "PF5";
- function = "mmc0";
- drive-strength = <30>;
- };
-
- nand_pins_a: nand-base0 at 0 {
- pins = "PC0", "PC1", "PC2",
- "PC5", "PC8", "PC9", "PC10",
- "PC11", "PC12", "PC13", "PC14",
- "PC15";
- function = "nand0";
- };
-
- nand_cs0_pins_a: nand-cs at 0 {
- pins = "PC4";
- function = "nand0";
- };
-
- nand_rb0_pins_a: nand-rb at 0 {
- pins = "PC6";
- function = "nand0";
- };
-
- pwm0_pins_a: pwm0 at 0 {
- pins = "PB2";
- function = "pwm0";
- };
-
- pwm1_pins: pwm1 {
- pins = "PG13";
- function = "pwm1";
- };
-
- spdif_tx_pins_a: spdif at 0 {
- pins = "PB10";
- function = "spdif";
- bias-pull-up;
- };
-
- uart1_pins_a: uart1 at 1 {
- pins = "PG3", "PG4";
- function = "uart1";
- };
-
- uart1_cts_rts_pins_a: uart1-cts-rts at 0 {
- pins = "PG5", "PG6";
- function = "uart1";
- };
-
- uart2_pins_a: uart2 at 1 {
- pins = "PD2", "PD3";
- function = "uart2";
- };
-
- uart2_cts_rts_pins_a: uart2-cts-rts at 0 {
- pins = "PD4", "PD5";
- function = "uart2";
- };
-
- uart3_pins_a: uart3 at 1 {
- pins = "PG9", "PG10";
- function = "uart3";
- };
-
- uart3_cts_rts_pins_a: uart3-cts-rts at 0 {
- pins = "PG11", "PG12";
- function = "uart3";
- };
- };
-
pwm: pwm at 01c20e00 {
compatible = "allwinner,sun5i-a10s-pwm";
reg = <0x01c20e00 0xc>;
@@ -473,18 +64,6 @@
status = "disabled";
};
- timer at 01c20c00 {
- compatible = "allwinner,sun4i-a10-timer";
- reg = <0x01c20c00 0x90>;
- interrupts = <22>;
- clocks = <&ccu CLK_HOSC>;
- };
-
- wdt: watchdog at 01c20c90 {
- compatible = "allwinner,sun4i-a10-wdt";
- reg = <0x01c20c90 0x10>;
- };
-
spdif: spdif at 01c21000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun4i-a10-spdif";
@@ -498,15 +77,6 @@
status = "disabled";
};
- ir0: ir at 01c21800 {
- compatible = "allwinner,sun4i-a10-ir";
- clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;
- clock-names = "apb", "ir";
- interrupts = <5>;
- reg = <0x01c21800 0x40>;
- status = "disabled";
- };
-
i2s0: i2s at 01c22400 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun4i-a10-i2s";
@@ -519,168 +89,39 @@
dma-names = "rx", "tx";
status = "disabled";
};
+ };
+};
- lradc: lradc at 01c22800 {
- compatible = "allwinner,sun4i-a10-lradc-keys";
- reg = <0x01c22800 0x100>;
- interrupts = <31>;
- status = "disabled";
- };
-
- codec: codec at 01c22c00 {
- #sound-dai-cells = <0>;
- compatible = "allwinner,sun4i-a10-codec";
- reg = <0x01c22c00 0x40>;
- interrupts = <30>;
- clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
- clock-names = "apb", "codec";
- dmas = <&dma SUN4I_DMA_NORMAL 19>,
- <&dma SUN4I_DMA_NORMAL 19>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- rtp: rtp at 01c25000 {
- compatible = "allwinner,sun5i-a13-ts";
- reg = <0x01c25000 0x100>;
- interrupts = <29>;
- #thermal-sensor-cells = <0>;
- };
-
- uart1: serial at 01c28400 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28400 0x400>;
- interrupts = <2>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_APB1_UART1>;
- status = "disabled";
- };
-
- uart2: serial at 01c28800 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28800 0x400>;
- interrupts = <3>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_APB1_UART2>;
- status = "disabled";
- };
-
- uart3: serial at 01c28c00 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28c00 0x400>;
- interrupts = <4>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_APB1_UART3>;
- status = "disabled";
- };
-
- i2c0: i2c at 01c2ac00 {
- compatible = "allwinner,sun4i-a10-i2c";
- reg = <0x01c2ac00 0x400>;
- interrupts = <7>;
- clocks = <&ccu CLK_APB1_I2C0>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c1: i2c at 01c2b000 {
- compatible = "allwinner,sun4i-a10-i2c";
- reg = <0x01c2b000 0x400>;
- interrupts = <8>;
- clocks = <&ccu CLK_APB1_I2C1>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c2: i2c at 01c2b400 {
- compatible = "allwinner,sun4i-a10-i2c";
- reg = <0x01c2b400 0x400>;
- interrupts = <9>;
- clocks = <&ccu CLK_APB1_I2C2>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- timer at 01c60000 {
- compatible = "allwinner,sun5i-a13-hstimer";
- reg = <0x01c60000 0x1000>;
- interrupts = <82>, <83>;
- clocks = <&ccu CLK_AHB_HSTIMER>;
- };
-
- fe0: display-frontend at 01e00000 {
- compatible = "allwinner,sun5i-a13-display-frontend";
- reg = <0x01e00000 0x20000>;
- interrupts = <47>;
- clocks = <&ccu CLK_AHB_DE_FE>, <&ccu CLK_DE_FE>,
- <&ccu CLK_DRAM_DE_FE>;
- clock-names = "ahb", "mod",
- "ram";
- resets = <&ccu RST_DE_FE>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- fe0_out: port at 1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- fe0_out_be0: endpoint at 0 {
- reg = <0>;
- remote-endpoint = <&be0_in_fe0>;
- };
- };
- };
- };
-
- be0: display-backend at 01e60000 {
- compatible = "allwinner,sun5i-a13-display-backend";
- reg = <0x01e60000 0x10000>;
- clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
- <&ccu CLK_DRAM_DE_BE>;
- clock-names = "ahb", "mod",
- "ram";
- resets = <&ccu RST_DE_BE>;
- status = "disabled";
+&ccu {
+ compatible = "nextthing,gr8-ccu";
+};
- assigned-clocks = <&ccu CLK_DE_BE>;
- assigned-clock-rates = <300000000>;
+&pio {
+ compatible = "nextthing,gr8-pinctrl";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
+ i2s0_data_pins_a: i2s0-data at 0 {
+ pins = "PB6", "PB7", "PB8", "PB9";
+ function = "i2s0";
+ };
- be0_in: port at 0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
+ i2s0_mclk_pins_a: i2s0-mclk at 0 {
+ pins = "PB5";
+ function = "i2s0";
+ };
- be0_in_fe0: endpoint at 0 {
- reg = <0>;
- remote-endpoint = <&fe0_out_be0>;
- };
- };
+ pwm1_pins: pwm1 {
+ pins = "PG13";
+ function = "pwm1";
+ };
- be0_out: port at 1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
+ spdif_tx_pins_a: spdif at 0 {
+ pins = "PB10";
+ function = "spdif";
+ bias-pull-up;
+ };
- be0_out_tcon0: endpoint at 0 {
- reg = <0>;
- remote-endpoint = <&tcon0_in_be0>;
- };
- };
- };
- };
+ uart1_cts_rts_pins_a: uart1-cts-rts at 0 {
+ pins = "PG5", "PG6";
+ function = "uart1";
};
};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index c8e2253cac1d..14bd50169cbe 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -159,6 +159,19 @@
#dma-cells = <2>;
};
+ nfc: nand at 01c03000 {
+ compatible = "allwinner,sun4i-a10-nand";
+ reg = <0x01c03000 0x1000>;
+ interrupts = <37>;
+ clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma SUN4I_DMA_DEDICATED 3>;
+ dma-names = "rxtx";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
spi0: spi at 01c05000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c05000 0x1000>;
@@ -406,6 +419,11 @@
function = "i2c2";
};
+ ir0_rx_pins_a: ir0 at 0 {
+ pins = "PB4";
+ function = "ir0";
+ };
+
lcd_rgb565_pins: lcd_rgb565 at 0 {
pins = "PD3", "PD4", "PD5", "PD6", "PD7",
"PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
@@ -447,6 +465,24 @@
bias-pull-up;
};
+ nand_pins_a: nand-base0 at 0 {
+ pins = "PC0", "PC1", "PC2",
+ "PC5", "PC8", "PC9", "PC10",
+ "PC11", "PC12", "PC13", "PC14",
+ "PC15";
+ function = "nand0";
+ };
+
+ nand_cs0_pins_a: nand-cs at 0 {
+ pins = "PC4";
+ function = "nand0";
+ };
+
+ nand_rb0_pins_a: nand-rb at 0 {
+ pins = "PC6";
+ function = "nand0";
+ };
+
pwm0_pins_a: pwm0 at 0 {
pins = "PB2";
function = "pwm0";
@@ -505,6 +541,15 @@
reg = <0x01c20c90 0x10>;
};
+ ir0: ir at 01c21800 {
+ compatible = "allwinner,sun4i-a10-ir";
+ clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;
+ clock-names = "apb", "ir";
+ interrupts = <5>;
+ reg = <0x01c21800 0x40>;
+ status = "disabled";
+ };
+
lradc: lradc at 01c22800 {
compatible = "allwinner,sun4i-a10-lradc-keys";
reg = <0x01c22800 0x100>;
--
git-series 0.8.11
^ permalink raw reply related [flat|nested] 44+ messages in thread
* Re: [PATCH 1/9] ARM: sun5i: A10s: Switch the EMAC pins indices
2017-02-05 18:49 ` Maxime Ripard
@ 2017-02-06 7:10 ` Chen-Yu Tsai
-1 siblings, 0 replies; 44+ messages in thread
From: Chen-Yu Tsai @ 2017-02-06 7:10 UTC (permalink / raw)
To: Maxime Ripard; +Cc: Chen-Yu Tsai, linux-arm-kernel, linux-kernel
On Mon, Feb 6, 2017 at 2:49 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> One of the pins group for the EMAC can be used by all the SoCs of the sun5i
> family, and as such can be moved to the common DTSI.
>
> Unfortunately, this group is the second one we declare in our DT for now.
> Make it the first one so that it's more logical and consistent with the
> rest of our DTs before moving it.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 1/9] ARM: sun5i: A10s: Switch the EMAC pins indices
@ 2017-02-06 7:10 ` Chen-Yu Tsai
0 siblings, 0 replies; 44+ messages in thread
From: Chen-Yu Tsai @ 2017-02-06 7:10 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Feb 6, 2017 at 2:49 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> One of the pins group for the EMAC can be used by all the SoCs of the sun5i
> family, and as such can be moved to the common DTSI.
>
> Unfortunately, this group is the second one we declare in our DT for now.
> Make it the first one so that it's more logical and consistent with the
> rest of our DTs before moving it.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 2/9] ARM: sun5i: a10s: switch simple framebuffer indices
2017-02-05 18:49 ` Maxime Ripard
@ 2017-02-06 7:11 ` Chen-Yu Tsai
-1 siblings, 0 replies; 44+ messages in thread
From: Chen-Yu Tsai @ 2017-02-06 7:11 UTC (permalink / raw)
To: Maxime Ripard; +Cc: Chen-Yu Tsai, linux-arm-kernel, linux-kernel
On Mon, Feb 6, 2017 at 2:49 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Of the three simple framebuffer setups we have in the A10s, two of them can
> be shared with the other SoCs from the sun5i family (LCD panel and
> composite output).
>
> However, the only one we cannot share is the HDMI, which is the first
> listed in the A10s DTSI. In order to make it more logical and so that we
> can share the framebuffer nodes in the common DTSI, reorder those nodes.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 2/9] ARM: sun5i: a10s: switch simple framebuffer indices
@ 2017-02-06 7:11 ` Chen-Yu Tsai
0 siblings, 0 replies; 44+ messages in thread
From: Chen-Yu Tsai @ 2017-02-06 7:11 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Feb 6, 2017 at 2:49 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Of the three simple framebuffer setups we have in the A10s, two of them can
> be shared with the other SoCs from the sun5i family (LCD panel and
> composite output).
>
> However, the only one we cannot share is the HDMI, which is the first
> listed in the A10s DTSI. In order to make it more logical and so that we
> can share the framebuffer nodes in the common DTSI, reorder those nodes.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 3/9] ARM: sunxi: Rename pwm0_pins to match our usual pattern
2017-02-05 18:49 ` Maxime Ripard
@ 2017-02-06 7:15 ` Chen-Yu Tsai
-1 siblings, 0 replies; 44+ messages in thread
From: Chen-Yu Tsai @ 2017-02-06 7:15 UTC (permalink / raw)
To: Maxime Ripard; +Cc: Chen-Yu Tsai, linux-arm-kernel, linux-kernel
On Mon, Feb 6, 2017 at 2:49 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The pwm0_pins group name is suggesting that this is the only option usable
> for the PWM0 on the SoCs it's declared on. However, this is not the case
> and defining a second pwm0 group would be quite weird given the name of the
> first group.
Can you elaborate on the second pwm0 option? I'm not seeing it in my datasheets.
ChenYu
>
> Rename it so that it matches our usual pattern.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts | 2 +-
> arch/arm/boot/dts/sun5i.dtsi | 10 +++++-----
> arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
> arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi | 2 +-
> 4 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
> index 42435454acef..1bc87523b37c 100644
> --- a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
> +++ b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
> @@ -157,7 +157,7 @@
>
> &pwm {
> pinctrl-names = "default";
> - pinctrl-0 = <&pwm0_pins>;
> + pinctrl-0 = <&pwm0_pins_a>;
> status = "okay";
> };
>
> diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
> index a9574a6cd95c..fce3ec693531 100644
> --- a/arch/arm/boot/dts/sun5i.dtsi
> +++ b/arch/arm/boot/dts/sun5i.dtsi
> @@ -321,6 +321,11 @@
> bias-pull-up;
> };
>
> + pwm0_pins_a: pwm0@0 {
> + pins = "PB2";
> + function = "pwm0";
> + };
> +
> spi2_pins_a: spi2@0 {
> pins = "PE1", "PE2", "PE3";
> function = "spi2";
> @@ -340,11 +345,6 @@
> pins = "PG11", "PG12";
> function = "uart3";
> };
> -
> - pwm0_pins: pwm0 {
> - pins = "PB2";
> - function = "pwm";
> - };
> };
>
> timer@01c20c00 {
> diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> index 35008b78d899..b558d318a72e 100644
> --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> @@ -316,7 +316,7 @@
> bias-pull-up;
> };
>
> - pwm0_pins: pwm0 {
> + pwm0_pins_a: pwm0 {
> pins = "PH0";
> function = "pwm0";
> };
> diff --git a/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi b/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi
> index b8241462fcea..5cd891942fe3 100644
> --- a/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi
> +++ b/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi
> @@ -78,6 +78,6 @@
>
> &pwm {
> pinctrl-names = "default";
> - pinctrl-0 = <&pwm0_pins>;
> + pinctrl-0 = <&pwm0_pins_a>;
> status = "okay";
> };
> --
> git-series 0.8.11
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 3/9] ARM: sunxi: Rename pwm0_pins to match our usual pattern
@ 2017-02-06 7:15 ` Chen-Yu Tsai
0 siblings, 0 replies; 44+ messages in thread
From: Chen-Yu Tsai @ 2017-02-06 7:15 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Feb 6, 2017 at 2:49 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The pwm0_pins group name is suggesting that this is the only option usable
> for the PWM0 on the SoCs it's declared on. However, this is not the case
> and defining a second pwm0 group would be quite weird given the name of the
> first group.
Can you elaborate on the second pwm0 option? I'm not seeing it in my datasheets.
ChenYu
>
> Rename it so that it matches our usual pattern.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts | 2 +-
> arch/arm/boot/dts/sun5i.dtsi | 10 +++++-----
> arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
> arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi | 2 +-
> 4 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
> index 42435454acef..1bc87523b37c 100644
> --- a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
> +++ b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
> @@ -157,7 +157,7 @@
>
> &pwm {
> pinctrl-names = "default";
> - pinctrl-0 = <&pwm0_pins>;
> + pinctrl-0 = <&pwm0_pins_a>;
> status = "okay";
> };
>
> diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
> index a9574a6cd95c..fce3ec693531 100644
> --- a/arch/arm/boot/dts/sun5i.dtsi
> +++ b/arch/arm/boot/dts/sun5i.dtsi
> @@ -321,6 +321,11 @@
> bias-pull-up;
> };
>
> + pwm0_pins_a: pwm0 at 0 {
> + pins = "PB2";
> + function = "pwm0";
> + };
> +
> spi2_pins_a: spi2 at 0 {
> pins = "PE1", "PE2", "PE3";
> function = "spi2";
> @@ -340,11 +345,6 @@
> pins = "PG11", "PG12";
> function = "uart3";
> };
> -
> - pwm0_pins: pwm0 {
> - pins = "PB2";
> - function = "pwm";
> - };
> };
>
> timer at 01c20c00 {
> diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> index 35008b78d899..b558d318a72e 100644
> --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> @@ -316,7 +316,7 @@
> bias-pull-up;
> };
>
> - pwm0_pins: pwm0 {
> + pwm0_pins_a: pwm0 {
> pins = "PH0";
> function = "pwm0";
> };
> diff --git a/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi b/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi
> index b8241462fcea..5cd891942fe3 100644
> --- a/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi
> +++ b/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi
> @@ -78,6 +78,6 @@
>
> &pwm {
> pinctrl-names = "default";
> - pinctrl-0 = <&pwm0_pins>;
> + pinctrl-0 = <&pwm0_pins_a>;
> status = "okay";
> };
> --
> git-series 0.8.11
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 4/9] ARM: sun5i: Add UART2 pin group
2017-02-05 18:49 ` Maxime Ripard
@ 2017-02-06 7:17 ` Chen-Yu Tsai
-1 siblings, 0 replies; 44+ messages in thread
From: Chen-Yu Tsai @ 2017-02-06 7:17 UTC (permalink / raw)
To: Maxime Ripard; +Cc: Chen-Yu Tsai, linux-arm-kernel, linux-kernel
On Mon, Feb 6, 2017 at 2:49 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> There's one UART2 pin group that can be used across all sun5i SoCs.
> However, the A10s already has one pin group for that controller.
>
> Change the index of the one in the A10s DTSI, and add the common one to
> sun5i.dtsi
Kind of goes against the tradition of not adding stuff no one uses?
Perhaps add a comment instead? I'm OK either way though.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 4/9] ARM: sun5i: Add UART2 pin group
@ 2017-02-06 7:17 ` Chen-Yu Tsai
0 siblings, 0 replies; 44+ messages in thread
From: Chen-Yu Tsai @ 2017-02-06 7:17 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Feb 6, 2017 at 2:49 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> There's one UART2 pin group that can be used across all sun5i SoCs.
> However, the A10s already has one pin group for that controller.
>
> Change the index of the one in the A10s DTSI, and add the common one to
> sun5i.dtsi
Kind of goes against the tradition of not adding stuff no one uses?
Perhaps add a comment instead? I'm OK either way though.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 5/9] ARM: sun5i: Rename UART3 flow control pins
2017-02-05 18:49 ` Maxime Ripard
@ 2017-02-06 7:18 ` Chen-Yu Tsai
-1 siblings, 0 replies; 44+ messages in thread
From: Chen-Yu Tsai @ 2017-02-06 7:18 UTC (permalink / raw)
To: Maxime Ripard; +Cc: Chen-Yu Tsai, linux-arm-kernel, linux-kernel
On Mon, Feb 6, 2017 at 2:49 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The UART3 pin group for the CTS and RTS signals doesn't follow our usual
> pattern. Rename it so that it matches.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 5/9] ARM: sun5i: Rename UART3 flow control pins
@ 2017-02-06 7:18 ` Chen-Yu Tsai
0 siblings, 0 replies; 44+ messages in thread
From: Chen-Yu Tsai @ 2017-02-06 7:18 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Feb 6, 2017 at 2:49 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The UART3 pin group for the CTS and RTS signals doesn't follow our usual
> pattern. Rename it so that it matches.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 6/9] ARM: sun5i: a13: Merge common controllers into the common DTSI
2017-02-05 18:49 ` Maxime Ripard
@ 2017-02-06 7:18 ` Chen-Yu Tsai
-1 siblings, 0 replies; 44+ messages in thread
From: Chen-Yu Tsai @ 2017-02-06 7:18 UTC (permalink / raw)
To: Maxime Ripard; +Cc: Chen-Yu Tsai, linux-arm-kernel, linux-kernel
On Mon, Feb 6, 2017 at 2:49 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Some controllers found in the A13 DTSI actually apply to all of the sun5i
> family. Move those into the common DTSI so that all SoCs can benefit from
> it.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 6/9] ARM: sun5i: a13: Merge common controllers into the common DTSI
@ 2017-02-06 7:18 ` Chen-Yu Tsai
0 siblings, 0 replies; 44+ messages in thread
From: Chen-Yu Tsai @ 2017-02-06 7:18 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Feb 6, 2017 at 2:49 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Some controllers found in the A13 DTSI actually apply to all of the sun5i
> family. Move those into the common DTSI so that all SoCs can benefit from
> it.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 7/9] ARM: sun5i: a10s: Merge common controllers into the common DTSI
2017-02-05 18:49 ` Maxime Ripard
@ 2017-02-06 7:21 ` Chen-Yu Tsai
-1 siblings, 0 replies; 44+ messages in thread
From: Chen-Yu Tsai @ 2017-02-06 7:21 UTC (permalink / raw)
To: Maxime Ripard; +Cc: Chen-Yu Tsai, linux-arm-kernel, linux-kernel
On Mon, Feb 6, 2017 at 2:49 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Some controllers found in the A10s DTSI actually apply to all of the sun5i
> family. Move those into the common DTSI so that all SoCs can benefit from
> it.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 7/9] ARM: sun5i: a10s: Merge common controllers into the common DTSI
@ 2017-02-06 7:21 ` Chen-Yu Tsai
0 siblings, 0 replies; 44+ messages in thread
From: Chen-Yu Tsai @ 2017-02-06 7:21 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Feb 6, 2017 at 2:49 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Some controllers found in the A10s DTSI actually apply to all of the sun5i
> family. Move those into the common DTSI so that all SoCs can benefit from
> it.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 8/9] ARM: sun5i: r8: Merge common controllers into the common DTSI
2017-02-05 18:49 ` Maxime Ripard
@ 2017-02-06 7:22 ` Chen-Yu Tsai
-1 siblings, 0 replies; 44+ messages in thread
From: Chen-Yu Tsai @ 2017-02-06 7:22 UTC (permalink / raw)
To: Maxime Ripard; +Cc: Chen-Yu Tsai, linux-arm-kernel, linux-kernel
On Mon, Feb 6, 2017 at 2:49 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Some controllers found in the R8 DTSI actually apply to all of the sun5i
> family. Move those into the common DTSI so that all SoCs can benefit from
> it.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 8/9] ARM: sun5i: r8: Merge common controllers into the common DTSI
@ 2017-02-06 7:22 ` Chen-Yu Tsai
0 siblings, 0 replies; 44+ messages in thread
From: Chen-Yu Tsai @ 2017-02-06 7:22 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Feb 6, 2017 at 2:49 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Some controllers found in the R8 DTSI actually apply to all of the sun5i
> family. Move those into the common DTSI so that all SoCs can benefit from
> it.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 9/9] ARM: sun5i: gr8: Use common sun5i DTSI
2017-02-05 18:49 ` Maxime Ripard
@ 2017-02-06 7:30 ` Chen-Yu Tsai
-1 siblings, 0 replies; 44+ messages in thread
From: Chen-Yu Tsai @ 2017-02-06 7:30 UTC (permalink / raw)
To: Maxime Ripard; +Cc: Chen-Yu Tsai, linux-arm-kernel, linux-kernel
On Mon, Feb 6, 2017 at 2:49 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Most of the GR8 DTSI is duplicated with the common sun5i DTSI, and some of
> the extra nodes defined there actually apply to all of the sun5i family.
>
> Move those into the common DTSI so that all SoCs can benefit from it, and
> include the sun5i DTSI.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
I think it's possible to move the display-engine node over as well?
Acked-by: Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 9/9] ARM: sun5i: gr8: Use common sun5i DTSI
@ 2017-02-06 7:30 ` Chen-Yu Tsai
0 siblings, 0 replies; 44+ messages in thread
From: Chen-Yu Tsai @ 2017-02-06 7:30 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Feb 6, 2017 at 2:49 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Most of the GR8 DTSI is duplicated with the common sun5i DTSI, and some of
> the extra nodes defined there actually apply to all of the sun5i family.
>
> Move those into the common DTSI so that all SoCs can benefit from it, and
> include the sun5i DTSI.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
I think it's possible to move the display-engine node over as well?
Acked-by: Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 4/9] ARM: sun5i: Add UART2 pin group
2017-02-06 7:17 ` Chen-Yu Tsai
@ 2017-02-06 17:37 ` Maxime Ripard
-1 siblings, 0 replies; 44+ messages in thread
From: Maxime Ripard @ 2017-02-06 17:37 UTC (permalink / raw)
To: Chen-Yu Tsai; +Cc: linux-arm-kernel, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 699 bytes --]
Hi,
On Mon, Feb 06, 2017 at 03:17:40PM +0800, Chen-Yu Tsai wrote:
> On Mon, Feb 6, 2017 at 2:49 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > There's one UART2 pin group that can be used across all sun5i SoCs.
> > However, the A10s already has one pin group for that controller.
> >
> > Change the index of the one in the A10s DTSI, and add the common one to
> > sun5i.dtsi
>
> Kind of goes against the tradition of not adding stuff no one uses?
> Perhaps add a comment instead? I'm OK either way though.
Not really, this is used by the CHIP Pro.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 801 bytes --]
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 4/9] ARM: sun5i: Add UART2 pin group
@ 2017-02-06 17:37 ` Maxime Ripard
0 siblings, 0 replies; 44+ messages in thread
From: Maxime Ripard @ 2017-02-06 17:37 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Mon, Feb 06, 2017 at 03:17:40PM +0800, Chen-Yu Tsai wrote:
> On Mon, Feb 6, 2017 at 2:49 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > There's one UART2 pin group that can be used across all sun5i SoCs.
> > However, the A10s already has one pin group for that controller.
> >
> > Change the index of the one in the A10s DTSI, and add the common one to
> > sun5i.dtsi
>
> Kind of goes against the tradition of not adding stuff no one uses?
> Perhaps add a comment instead? I'm OK either way though.
Not really, this is used by the CHIP Pro.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 9/9] ARM: sun5i: gr8: Use common sun5i DTSI
2017-02-06 7:30 ` Chen-Yu Tsai
@ 2017-02-06 17:39 ` Maxime Ripard
-1 siblings, 0 replies; 44+ messages in thread
From: Maxime Ripard @ 2017-02-06 17:39 UTC (permalink / raw)
To: Chen-Yu Tsai; +Cc: linux-arm-kernel, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 845 bytes --]
Hi,
On Mon, Feb 06, 2017 at 03:30:11PM +0800, Chen-Yu Tsai wrote:
> On Mon, Feb 6, 2017 at 2:49 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Most of the GR8 DTSI is duplicated with the common sun5i DTSI, and some of
> > the extra nodes defined there actually apply to all of the sun5i family.
> >
> > Move those into the common DTSI so that all SoCs can benefit from it, and
> > include the sun5i DTSI.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>
> I think it's possible to move the display-engine node over as well?
I left it out for now, because if we follow our current rule, we will
have a different display engine for the A10s that has the HDMI
encoder.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 9/9] ARM: sun5i: gr8: Use common sun5i DTSI
@ 2017-02-06 17:39 ` Maxime Ripard
0 siblings, 0 replies; 44+ messages in thread
From: Maxime Ripard @ 2017-02-06 17:39 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Mon, Feb 06, 2017 at 03:30:11PM +0800, Chen-Yu Tsai wrote:
> On Mon, Feb 6, 2017 at 2:49 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Most of the GR8 DTSI is duplicated with the common sun5i DTSI, and some of
> > the extra nodes defined there actually apply to all of the sun5i family.
> >
> > Move those into the common DTSI so that all SoCs can benefit from it, and
> > include the sun5i DTSI.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>
> I think it's possible to move the display-engine node over as well?
I left it out for now, because if we follow our current rule, we will
have a different display engine for the A10s that has the HDMI
encoder.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
-------------- next part --------------
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^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 3/9] ARM: sunxi: Rename pwm0_pins to match our usual pattern
2017-02-06 7:15 ` Chen-Yu Tsai
@ 2017-02-06 17:46 ` Maxime Ripard
-1 siblings, 0 replies; 44+ messages in thread
From: Maxime Ripard @ 2017-02-06 17:46 UTC (permalink / raw)
To: Chen-Yu Tsai; +Cc: linux-arm-kernel, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 753 bytes --]
On Mon, Feb 06, 2017 at 03:15:15PM +0800, Chen-Yu Tsai wrote:
> On Mon, Feb 6, 2017 at 2:49 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > The pwm0_pins group name is suggesting that this is the only option usable
> > for the PWM0 on the SoCs it's declared on. However, this is not the case
> > and defining a second pwm0 group would be quite weird given the name of the
> > first group.
>
> Can you elaborate on the second pwm0 option? I'm not seeing it in my datasheets.
Hmmmm, I'm not sure why I did that anymore, looks like you're right...
I'll drop this one, and queue the others for 4.12.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 3/9] ARM: sunxi: Rename pwm0_pins to match our usual pattern
@ 2017-02-06 17:46 ` Maxime Ripard
0 siblings, 0 replies; 44+ messages in thread
From: Maxime Ripard @ 2017-02-06 17:46 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Feb 06, 2017 at 03:15:15PM +0800, Chen-Yu Tsai wrote:
> On Mon, Feb 6, 2017 at 2:49 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > The pwm0_pins group name is suggesting that this is the only option usable
> > for the PWM0 on the SoCs it's declared on. However, this is not the case
> > and defining a second pwm0 group would be quite weird given the name of the
> > first group.
>
> Can you elaborate on the second pwm0 option? I'm not seeing it in my datasheets.
Hmmmm, I'm not sure why I did that anymore, looks like you're right...
I'll drop this one, and queue the others for 4.12.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 44+ messages in thread
end of thread, other threads:[~2017-02-06 20:17 UTC | newest]
Thread overview: 44+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-02-05 18:49 [PATCH 0/9] ARM: sun5i: Cleanup and reorganisation of the DTSI Maxime Ripard
2017-02-05 18:49 ` Maxime Ripard
2017-02-05 18:49 ` [PATCH 1/9] ARM: sun5i: A10s: Switch the EMAC pins indices Maxime Ripard
2017-02-05 18:49 ` Maxime Ripard
2017-02-06 7:10 ` Chen-Yu Tsai
2017-02-06 7:10 ` Chen-Yu Tsai
2017-02-05 18:49 ` [PATCH 2/9] ARM: sun5i: a10s: switch simple framebuffer indices Maxime Ripard
2017-02-05 18:49 ` Maxime Ripard
2017-02-06 7:11 ` Chen-Yu Tsai
2017-02-06 7:11 ` Chen-Yu Tsai
2017-02-05 18:49 ` [PATCH 3/9] ARM: sunxi: Rename pwm0_pins to match our usual pattern Maxime Ripard
2017-02-05 18:49 ` Maxime Ripard
2017-02-06 7:15 ` Chen-Yu Tsai
2017-02-06 7:15 ` Chen-Yu Tsai
2017-02-06 17:46 ` Maxime Ripard
2017-02-06 17:46 ` Maxime Ripard
2017-02-05 18:49 ` [PATCH 4/9] ARM: sun5i: Add UART2 pin group Maxime Ripard
2017-02-05 18:49 ` Maxime Ripard
2017-02-06 7:17 ` Chen-Yu Tsai
2017-02-06 7:17 ` Chen-Yu Tsai
2017-02-06 17:37 ` Maxime Ripard
2017-02-06 17:37 ` Maxime Ripard
2017-02-05 18:49 ` [PATCH 5/9] ARM: sun5i: Rename UART3 flow control pins Maxime Ripard
2017-02-05 18:49 ` Maxime Ripard
2017-02-06 7:18 ` Chen-Yu Tsai
2017-02-06 7:18 ` Chen-Yu Tsai
2017-02-05 18:49 ` [PATCH 6/9] ARM: sun5i: a13: Merge common controllers into the common DTSI Maxime Ripard
2017-02-05 18:49 ` Maxime Ripard
2017-02-06 7:18 ` Chen-Yu Tsai
2017-02-06 7:18 ` Chen-Yu Tsai
2017-02-05 18:49 ` [PATCH 7/9] ARM: sun5i: a10s: " Maxime Ripard
2017-02-05 18:49 ` Maxime Ripard
2017-02-06 7:21 ` Chen-Yu Tsai
2017-02-06 7:21 ` Chen-Yu Tsai
2017-02-05 18:49 ` [PATCH 8/9] ARM: sun5i: r8: " Maxime Ripard
2017-02-05 18:49 ` Maxime Ripard
2017-02-06 7:22 ` Chen-Yu Tsai
2017-02-06 7:22 ` Chen-Yu Tsai
2017-02-05 18:49 ` [PATCH 9/9] ARM: sun5i: gr8: Use common sun5i DTSI Maxime Ripard
2017-02-05 18:49 ` Maxime Ripard
2017-02-06 7:30 ` Chen-Yu Tsai
2017-02-06 7:30 ` Chen-Yu Tsai
2017-02-06 17:39 ` Maxime Ripard
2017-02-06 17:39 ` Maxime Ripard
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