* [PATCH v3 0/3] ARM: l2c: add l2c support for RZ/A1 @ 2017-02-16 15:37 ` Chris Brandt 0 siblings, 0 replies; 12+ messages in thread From: Chris Brandt @ 2017-02-16 15:37 UTC (permalink / raw) To: Simon Horman, Magnus Damm, Geert Uytterhoeven, Rob Herring, Mark Rutland, Russell King, Brad Mouring, Andrey Smirnov, Arnd Bergmann, Richard Cochran Cc: devicetree, linux-renesas-soc, linux-arm-kernel, Chris Brandt The PL310 in the Renesas RZ/A1 SoC (R7S72100) does not have the sideband signals connected between the CPU and L2C. According the PL310 TRM, sideband signals are optional. If a PL310 is added to a system, but the sideband signals are not connected, some Cortex A9 optimizations cannot be used. In particular, enabling Full Line Zeros in the CA9 without sidebands connected will crash the system since the CA9 will expect the L2C to perform operations, yet the L2C never gets the commands. This series adds the option to not enable anything in the PL310 that uses sidebands, and then adds L2C support to the RZ/A1 DT. v3: * split "arm,pl310-no-sideband" into "arm,early-bresp-disable" and "arm,full-line-zero-disable" v2: * Added "arm,pl310-no-sideband" to cache-l2x0.c instead of hacking in a dummy l2c_write_sec function to keep FLZ from being enabled. Chris Brandt (3): ARM: l2c: allow CA9 optimizations to be disabled ARM: shmobile: r7s72100: Enable L2 cache ARM: dts: r7s72100: add l2 cache Documentation/devicetree/bindings/arm/l2c2x0.txt | 3 +++ arch/arm/boot/dts/r7s72100.dtsi | 11 +++++++++++ arch/arm/mach-shmobile/setup-r7s72100.c | 2 ++ arch/arm/mm/cache-l2x0.c | 13 +++++++++++-- 4 files changed, 27 insertions(+), 2 deletions(-) -- 2.10.1 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 0/3] ARM: l2c: add l2c support for RZ/A1 @ 2017-02-16 15:37 ` Chris Brandt 0 siblings, 0 replies; 12+ messages in thread From: Chris Brandt @ 2017-02-16 15:37 UTC (permalink / raw) To: linux-arm-kernel The PL310 in the Renesas RZ/A1 SoC (R7S72100) does not have the sideband signals connected between the CPU and L2C. According the PL310 TRM, sideband signals are optional. If a PL310 is added to a system, but the sideband signals are not connected, some Cortex A9 optimizations cannot be used. In particular, enabling Full Line Zeros in the CA9 without sidebands connected will crash the system since the CA9 will expect the L2C to perform operations, yet the L2C never gets the commands. This series adds the option to not enable anything in the PL310 that uses sidebands, and then adds L2C support to the RZ/A1 DT. v3: * split "arm,pl310-no-sideband" into "arm,early-bresp-disable" and "arm,full-line-zero-disable" v2: * Added "arm,pl310-no-sideband" to cache-l2x0.c instead of hacking in a dummy l2c_write_sec function to keep FLZ from being enabled. Chris Brandt (3): ARM: l2c: allow CA9 optimizations to be disabled ARM: shmobile: r7s72100: Enable L2 cache ARM: dts: r7s72100: add l2 cache Documentation/devicetree/bindings/arm/l2c2x0.txt | 3 +++ arch/arm/boot/dts/r7s72100.dtsi | 11 +++++++++++ arch/arm/mach-shmobile/setup-r7s72100.c | 2 ++ arch/arm/mm/cache-l2x0.c | 13 +++++++++++-- 4 files changed, 27 insertions(+), 2 deletions(-) -- 2.10.1 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 1/3] ARM: l2c: allow CA9 optimizations to be disabled 2017-02-16 15:37 ` Chris Brandt @ 2017-02-16 15:37 ` Chris Brandt -1 siblings, 0 replies; 12+ messages in thread From: Chris Brandt @ 2017-02-16 15:37 UTC (permalink / raw) To: Simon Horman, Magnus Damm, Geert Uytterhoeven, Rob Herring, Mark Rutland, Russell King, Brad Mouring, Andrey Smirnov, Arnd Bergmann, Richard Cochran Cc: devicetree, linux-renesas-soc, linux-arm-kernel, Chris Brandt If a PL310 is added to a system, but the sideband signals are not connected, some Cortex A9 optimizations cannot be used. In particular, enabling Full Line of Zeros in the CA9 without sidebands connected will crash the system since the CA9 will expect the L2C to perform operations, yet the L2C never gets the commands. Early BRESP also does not work without sideband signals. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> --- v2: * split "arm,pl310-no-sideband" into "arm,early-bresp-disable" and "arm,full-line-zero-disable" --- Documentation/devicetree/bindings/arm/l2c2x0.txt | 3 +++ arch/arm/mm/cache-l2x0.c | 13 +++++++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt index 917199f..d9650c1 100644 --- a/Documentation/devicetree/bindings/arm/l2c2x0.txt +++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt @@ -90,6 +90,9 @@ Optional properties: - arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable), <1> (forcibly enable), property absent (OS specific behavior, preferably retain firmware settings) +- arm,early-bresp-disable : Disable the CA9 optimization Early BRESP (PL310) +- arm,full-line-zero-disable : Disable the CA9 optimization Full line of zero + write (PL310) Example: diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 2290be3..486cc6d 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -57,6 +57,9 @@ static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; struct l2x0_regs l2x0_saved_regs; +static bool l2x0_bresp_dis; +static bool l2x0_flz_dis; + /* * Common code for all cache controllers. */ @@ -620,7 +623,7 @@ static void __init l2c310_enable(void __iomem *base, unsigned num_lock) u32 aux = l2x0_saved_regs.aux_ctrl; if (rev >= L310_CACHE_ID_RTL_R2P0) { - if (cortex_a9) { + if (cortex_a9 && !l2x0_bresp_dis) { aux |= L310_AUX_CTRL_EARLY_BRESP; pr_info("L2C-310 enabling early BRESP for Cortex-A9\n"); } else if (aux & L310_AUX_CTRL_EARLY_BRESP) { @@ -629,7 +632,7 @@ static void __init l2c310_enable(void __iomem *base, unsigned num_lock) } } - if (cortex_a9) { + if (cortex_a9 && !l2x0_flz_dis) { u32 aux_cur = readl_relaxed(base + L2X0_AUX_CTRL); u32 acr = get_auxcr(); @@ -1200,6 +1203,12 @@ static void __init l2c310_of_parse(const struct device_node *np, *aux_mask &= ~L2C_AUX_CTRL_PARITY_ENABLE; } + if (of_property_read_bool(np, "arm,early-bresp-disable")) + l2x0_bresp_dis = true; + + if (of_property_read_bool(np, "arm,full-line-zero-disable")) + l2x0_flz_dis = true; + prefetch = l2x0_saved_regs.prefetch_ctrl; ret = of_property_read_u32(np, "arm,double-linefill", &val); -- 2.10.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 1/3] ARM: l2c: allow CA9 optimizations to be disabled @ 2017-02-16 15:37 ` Chris Brandt 0 siblings, 0 replies; 12+ messages in thread From: Chris Brandt @ 2017-02-16 15:37 UTC (permalink / raw) To: linux-arm-kernel If a PL310 is added to a system, but the sideband signals are not connected, some Cortex A9 optimizations cannot be used. In particular, enabling Full Line of Zeros in the CA9 without sidebands connected will crash the system since the CA9 will expect the L2C to perform operations, yet the L2C never gets the commands. Early BRESP also does not work without sideband signals. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> --- v2: * split "arm,pl310-no-sideband" into "arm,early-bresp-disable" and "arm,full-line-zero-disable" --- Documentation/devicetree/bindings/arm/l2c2x0.txt | 3 +++ arch/arm/mm/cache-l2x0.c | 13 +++++++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt index 917199f..d9650c1 100644 --- a/Documentation/devicetree/bindings/arm/l2c2x0.txt +++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt @@ -90,6 +90,9 @@ Optional properties: - arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable), <1> (forcibly enable), property absent (OS specific behavior, preferably retain firmware settings) +- arm,early-bresp-disable : Disable the CA9 optimization Early BRESP (PL310) +- arm,full-line-zero-disable : Disable the CA9 optimization Full line of zero + write (PL310) Example: diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 2290be3..486cc6d 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -57,6 +57,9 @@ static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; struct l2x0_regs l2x0_saved_regs; +static bool l2x0_bresp_dis; +static bool l2x0_flz_dis; + /* * Common code for all cache controllers. */ @@ -620,7 +623,7 @@ static void __init l2c310_enable(void __iomem *base, unsigned num_lock) u32 aux = l2x0_saved_regs.aux_ctrl; if (rev >= L310_CACHE_ID_RTL_R2P0) { - if (cortex_a9) { + if (cortex_a9 && !l2x0_bresp_dis) { aux |= L310_AUX_CTRL_EARLY_BRESP; pr_info("L2C-310 enabling early BRESP for Cortex-A9\n"); } else if (aux & L310_AUX_CTRL_EARLY_BRESP) { @@ -629,7 +632,7 @@ static void __init l2c310_enable(void __iomem *base, unsigned num_lock) } } - if (cortex_a9) { + if (cortex_a9 && !l2x0_flz_dis) { u32 aux_cur = readl_relaxed(base + L2X0_AUX_CTRL); u32 acr = get_auxcr(); @@ -1200,6 +1203,12 @@ static void __init l2c310_of_parse(const struct device_node *np, *aux_mask &= ~L2C_AUX_CTRL_PARITY_ENABLE; } + if (of_property_read_bool(np, "arm,early-bresp-disable")) + l2x0_bresp_dis = true; + + if (of_property_read_bool(np, "arm,full-line-zero-disable")) + l2x0_flz_dis = true; + prefetch = l2x0_saved_regs.prefetch_ctrl; ret = of_property_read_u32(np, "arm,double-linefill", &val); -- 2.10.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
[parent not found: <20170216153726.22919-2-chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>]
* Re: [PATCH v3 1/3] ARM: l2c: allow CA9 optimizations to be disabled 2017-02-16 15:37 ` Chris Brandt (?) @ 2017-02-16 16:06 ` Russell King - ARM Linux -1 siblings, 0 replies; 12+ messages in thread From: Russell King - ARM Linux @ 2017-02-16 16:06 UTC (permalink / raw) To: Chris Brandt Cc: Simon Horman, Magnus Damm, Geert Uytterhoeven, Rob Herring, Mark Rutland, Brad Mouring, Andrey Smirnov, Arnd Bergmann, Richard Cochran, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r On Thu, Feb 16, 2017 at 10:37:24AM -0500, Chris Brandt wrote: > diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c > index 2290be3..486cc6d 100644 > --- a/arch/arm/mm/cache-l2x0.c > +++ b/arch/arm/mm/cache-l2x0.c > @@ -57,6 +57,9 @@ static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; > > struct l2x0_regs l2x0_saved_regs; > > +static bool l2x0_bresp_dis; > +static bool l2x0_flz_dis; Please use full "disable" here. Thanks. -- RMK's Patch system: http://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up according to speedtest.net. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 1/3] ARM: l2c: allow CA9 optimizations to be disabled @ 2017-02-16 16:06 ` Russell King - ARM Linux 0 siblings, 0 replies; 12+ messages in thread From: Russell King - ARM Linux @ 2017-02-16 16:06 UTC (permalink / raw) To: linux-arm-kernel On Thu, Feb 16, 2017 at 10:37:24AM -0500, Chris Brandt wrote: > diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c > index 2290be3..486cc6d 100644 > --- a/arch/arm/mm/cache-l2x0.c > +++ b/arch/arm/mm/cache-l2x0.c > @@ -57,6 +57,9 @@ static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; > > struct l2x0_regs l2x0_saved_regs; > > +static bool l2x0_bresp_dis; > +static bool l2x0_flz_dis; Please use full "disable" here. Thanks. -- RMK's Patch system: http://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up according to speedtest.net. ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/3] ARM: l2c: allow CA9 optimizations to be disabled @ 2017-02-16 16:06 ` Russell King - ARM Linux 0 siblings, 0 replies; 12+ messages in thread From: Russell King - ARM Linux @ 2017-02-16 16:06 UTC (permalink / raw) To: Chris Brandt Cc: Simon Horman, Magnus Damm, Geert Uytterhoeven, Rob Herring, Mark Rutland, Brad Mouring, Andrey Smirnov, Arnd Bergmann, Richard Cochran, devicetree, linux-renesas-soc, linux-arm-kernel On Thu, Feb 16, 2017 at 10:37:24AM -0500, Chris Brandt wrote: > diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c > index 2290be3..486cc6d 100644 > --- a/arch/arm/mm/cache-l2x0.c > +++ b/arch/arm/mm/cache-l2x0.c > @@ -57,6 +57,9 @@ static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; > > struct l2x0_regs l2x0_saved_regs; > > +static bool l2x0_bresp_dis; > +static bool l2x0_flz_dis; Please use full "disable" here. Thanks. -- RMK's Patch system: http://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up according to speedtest.net. ^ permalink raw reply [flat|nested] 12+ messages in thread
[parent not found: <20170216153726.22919-1-chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>]
* [PATCH v3 2/3] ARM: shmobile: r7s72100: Enable L2 cache 2017-02-16 15:37 ` Chris Brandt (?) @ 2017-02-16 15:37 ` Chris Brandt -1 siblings, 0 replies; 12+ messages in thread From: Chris Brandt @ 2017-02-16 15:37 UTC (permalink / raw) To: Simon Horman, Magnus Damm, Geert Uytterhoeven, Rob Herring, Mark Rutland, Russell King, Brad Mouring, Andrey Smirnov, Arnd Bergmann, Richard Cochran Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Chris Brandt Even though L2C is specified in the DT, you still need to add the aux settings in the machine_desc. Signed-off-by: Chris Brandt <chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org> Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org> --- v2: * removed dummy l2c_write_sec function --- arch/arm/mach-shmobile/setup-r7s72100.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c index d46639f..319ca95 100644 --- a/arch/arm/mach-shmobile/setup-r7s72100.c +++ b/arch/arm/mach-shmobile/setup-r7s72100.c @@ -26,6 +26,8 @@ static const char *const r7s72100_boards_compat_dt[] __initconst = { }; DT_MACHINE_START(R7S72100_DT, "Generic R7S72100 (Flattened Device Tree)") + .l2c_aux_val = 0, + .l2c_aux_mask = ~0, .init_early = shmobile_init_delay, .init_late = shmobile_init_late, .dt_compat = r7s72100_boards_compat_dt, -- 2.10.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 2/3] ARM: shmobile: r7s72100: Enable L2 cache @ 2017-02-16 15:37 ` Chris Brandt 0 siblings, 0 replies; 12+ messages in thread From: Chris Brandt @ 2017-02-16 15:37 UTC (permalink / raw) To: linux-arm-kernel Even though L2C is specified in the DT, you still need to add the aux settings in the machine_desc. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> --- v2: * removed dummy l2c_write_sec function --- arch/arm/mach-shmobile/setup-r7s72100.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c index d46639f..319ca95 100644 --- a/arch/arm/mach-shmobile/setup-r7s72100.c +++ b/arch/arm/mach-shmobile/setup-r7s72100.c @@ -26,6 +26,8 @@ static const char *const r7s72100_boards_compat_dt[] __initconst = { }; DT_MACHINE_START(R7S72100_DT, "Generic R7S72100 (Flattened Device Tree)") + .l2c_aux_val = 0, + .l2c_aux_mask = ~0, .init_early = shmobile_init_delay, .init_late = shmobile_init_late, .dt_compat = r7s72100_boards_compat_dt, -- 2.10.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 2/3] ARM: shmobile: r7s72100: Enable L2 cache @ 2017-02-16 15:37 ` Chris Brandt 0 siblings, 0 replies; 12+ messages in thread From: Chris Brandt @ 2017-02-16 15:37 UTC (permalink / raw) To: Simon Horman, Magnus Damm, Geert Uytterhoeven, Rob Herring, Mark Rutland, Russell King, Brad Mouring, Andrey Smirnov, Arnd Bergmann, Richard Cochran Cc: devicetree, linux-renesas-soc, linux-arm-kernel, Chris Brandt Even though L2C is specified in the DT, you still need to add the aux settings in the machine_desc. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> --- v2: * removed dummy l2c_write_sec function --- arch/arm/mach-shmobile/setup-r7s72100.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c index d46639f..319ca95 100644 --- a/arch/arm/mach-shmobile/setup-r7s72100.c +++ b/arch/arm/mach-shmobile/setup-r7s72100.c @@ -26,6 +26,8 @@ static const char *const r7s72100_boards_compat_dt[] __initconst = { }; DT_MACHINE_START(R7S72100_DT, "Generic R7S72100 (Flattened Device Tree)") + .l2c_aux_val = 0, + .l2c_aux_mask = ~0, .init_early = shmobile_init_delay, .init_late = shmobile_init_late, .dt_compat = r7s72100_boards_compat_dt, -- 2.10.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 3/3] ARM: dts: r7s72100: add l2 cache 2017-02-16 15:37 ` Chris Brandt @ 2017-02-16 15:37 ` Chris Brandt -1 siblings, 0 replies; 12+ messages in thread From: Chris Brandt @ 2017-02-16 15:37 UTC (permalink / raw) To: Simon Horman, Magnus Damm, Geert Uytterhoeven, Rob Herring, Mark Rutland, Russell King, Brad Mouring, Andrey Smirnov, Arnd Bergmann, Richard Cochran Cc: devicetree, linux-renesas-soc, linux-arm-kernel, Chris Brandt Note that early-bresp-disable and full-line-zero-disable are required because the sideband signals between the CPU and L2C were not connected in this SoC. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> --- v3: * split "arm,pl310-no-sideband" into "arm,early-bresp-disable" and "arm,full-line-zero-disable" v2: * added "arm,pl310-no-sideband" --- arch/arm/boot/dts/r7s72100.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 614ba79..ed62e19 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -180,6 +180,7 @@ compatible = "arm,cortex-a9"; reg = <0>; clock-frequency = <400000000>; + next-level-cache = <&L2>; }; }; @@ -371,6 +372,16 @@ <0xe8202000 0x1000>; }; + L2: cache-controller@3ffff000 { + compatible = "arm,pl310-cache"; + reg = <0x3ffff000 0x1000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + arm,early-bresp-disable; + arm,full-line-zero-disable; + cache-unified; + cache-level = <2>; + }; + i2c0: i2c@fcfee000 { #address-cells = <1>; #size-cells = <0>; -- 2.10.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 3/3] ARM: dts: r7s72100: add l2 cache @ 2017-02-16 15:37 ` Chris Brandt 0 siblings, 0 replies; 12+ messages in thread From: Chris Brandt @ 2017-02-16 15:37 UTC (permalink / raw) To: linux-arm-kernel Note that early-bresp-disable and full-line-zero-disable are required because the sideband signals between the CPU and L2C were not connected in this SoC. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> --- v3: * split "arm,pl310-no-sideband" into "arm,early-bresp-disable" and "arm,full-line-zero-disable" v2: * added "arm,pl310-no-sideband" --- arch/arm/boot/dts/r7s72100.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 614ba79..ed62e19 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -180,6 +180,7 @@ compatible = "arm,cortex-a9"; reg = <0>; clock-frequency = <400000000>; + next-level-cache = <&L2>; }; }; @@ -371,6 +372,16 @@ <0xe8202000 0x1000>; }; + L2: cache-controller at 3ffff000 { + compatible = "arm,pl310-cache"; + reg = <0x3ffff000 0x1000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + arm,early-bresp-disable; + arm,full-line-zero-disable; + cache-unified; + cache-level = <2>; + }; + i2c0: i2c at fcfee000 { #address-cells = <1>; #size-cells = <0>; -- 2.10.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
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2017-02-16 15:37 [PATCH v3 0/3] ARM: l2c: add l2c support for RZ/A1 Chris Brandt
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2017-02-16 15:37 ` [PATCH v3 1/3] ARM: l2c: allow CA9 optimizations to be disabled Chris Brandt
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2017-02-16 16:06 ` Russell King - ARM Linux
2017-02-16 16:06 ` Russell King - ARM Linux
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2017-02-16 15:37 ` [PATCH v3 2/3] ARM: shmobile: r7s72100: Enable L2 cache Chris Brandt
2017-02-16 15:37 ` Chris Brandt
2017-02-16 15:37 ` Chris Brandt
2017-02-16 15:37 ` [PATCH v3 3/3] ARM: dts: r7s72100: add l2 cache Chris Brandt
2017-02-16 15:37 ` Chris Brandt
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