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From: Maxime Ripard <maxime.ripard@free-electrons.com>
To: Icenowy Zheng <icenowy@aosc.xyz>
Cc: Rob Herring <robh+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com
Subject: Re: [PATCH v2 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs
Date: Tue, 21 Mar 2017 08:41:17 +0100	[thread overview]
Message-ID: <20170321074117.vdfjynauuuv6fivp@lukather> (raw)
In-Reply-To: <20170315172808.64011-2-icenowy@aosc.xyz>

[-- Attachment #1: Type: text/plain, Size: 2146 bytes --]

On Thu, Mar 16, 2017 at 01:28:04AM +0800, Icenowy Zheng wrote:
> Many Allwinner SoCs after A31 have a CCU in PRCM block.
> 
> Give the ones on H3 and A64 compatible strings.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> Changes in v2:
> - Add iosc for R_CCU's on H3/A64. (A31, A23 and A33 seem to have different
>   clock for mux 3 of ar100 clk. Investgations are needed for them.)
> 
>  Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 18 +++++++++++++++++-
>  1 file changed, 17 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> index 68512aa398a9..4a4addff595d 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> @@ -7,9 +7,11 @@ Required properties :
>  		- "allwinner,sun8i-a23-ccu"
>  		- "allwinner,sun8i-a33-ccu"
>  		- "allwinner,sun8i-h3-ccu"
> +		- "allwinner,sun8i-h3-r-ccu"
>  		- "allwinner,sun8i-v3s-ccu"
>  		- "allwinner,sun9i-a80-ccu"
>  		- "allwinner,sun50i-a64-ccu"
> +		- "allwinner,sun50i-a64-r-ccu"
>  		- "allwinner,sun50i-h5-ccu"
>  
>  - reg: Must contain the registers base address and length
> @@ -20,7 +22,11 @@ Required properties :
>  - #clock-cells : must contain 1
>  - #reset-cells : must contain 1
>  
> -Example:
> +For the PRCM CCUs on H3/A64, one more clock is needed:
> +- "iosc": another frequency oscillator used for CPUS (usually at 32000Hz,
> +          not the same with losc)

This is called the internal oscillator in the datasheet, it would
probably make more sense to call it that way in the documentation too.

This oscillator seems to be clocked at 16MHz, so we should represent
it as such.

And I'm wondering, are you *sure* that it's fed directly from the
internal oscillator, or goes through the registers in the RTC, with
the 32 divider and 16 prescaler by default that makes it at roughly
the same rate (31.25kHz).

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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WARNING: multiple messages have this Message-ID (diff)
From: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
To: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org
Subject: Re: [PATCH v2 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs
Date: Tue, 21 Mar 2017 08:41:17 +0100	[thread overview]
Message-ID: <20170321074117.vdfjynauuuv6fivp@lukather> (raw)
In-Reply-To: <20170315172808.64011-2-icenowy-ymACFijhrKM@public.gmane.org>

[-- Attachment #1: Type: text/plain, Size: 2109 bytes --]

On Thu, Mar 16, 2017 at 01:28:04AM +0800, Icenowy Zheng wrote:
> Many Allwinner SoCs after A31 have a CCU in PRCM block.
> 
> Give the ones on H3 and A64 compatible strings.
> 
> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
> ---
> Changes in v2:
> - Add iosc for R_CCU's on H3/A64. (A31, A23 and A33 seem to have different
>   clock for mux 3 of ar100 clk. Investgations are needed for them.)
> 
>  Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 18 +++++++++++++++++-
>  1 file changed, 17 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> index 68512aa398a9..4a4addff595d 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> @@ -7,9 +7,11 @@ Required properties :
>  		- "allwinner,sun8i-a23-ccu"
>  		- "allwinner,sun8i-a33-ccu"
>  		- "allwinner,sun8i-h3-ccu"
> +		- "allwinner,sun8i-h3-r-ccu"
>  		- "allwinner,sun8i-v3s-ccu"
>  		- "allwinner,sun9i-a80-ccu"
>  		- "allwinner,sun50i-a64-ccu"
> +		- "allwinner,sun50i-a64-r-ccu"
>  		- "allwinner,sun50i-h5-ccu"
>  
>  - reg: Must contain the registers base address and length
> @@ -20,7 +22,11 @@ Required properties :
>  - #clock-cells : must contain 1
>  - #reset-cells : must contain 1
>  
> -Example:
> +For the PRCM CCUs on H3/A64, one more clock is needed:
> +- "iosc": another frequency oscillator used for CPUS (usually at 32000Hz,
> +          not the same with losc)

This is called the internal oscillator in the datasheet, it would
probably make more sense to call it that way in the documentation too.

This oscillator seems to be clocked at 16MHz, so we should represent
it as such.

And I'm wondering, are you *sure* that it's fed directly from the
internal oscillator, or goes through the registers in the RTC, with
the 32 divider and 16 prescaler by default that makes it at roughly
the same rate (31.25kHz).

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

WARNING: multiple messages have this Message-ID (diff)
From: maxime.ripard@free-electrons.com (Maxime Ripard)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs
Date: Tue, 21 Mar 2017 08:41:17 +0100	[thread overview]
Message-ID: <20170321074117.vdfjynauuuv6fivp@lukather> (raw)
In-Reply-To: <20170315172808.64011-2-icenowy@aosc.xyz>

On Thu, Mar 16, 2017 at 01:28:04AM +0800, Icenowy Zheng wrote:
> Many Allwinner SoCs after A31 have a CCU in PRCM block.
> 
> Give the ones on H3 and A64 compatible strings.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> Changes in v2:
> - Add iosc for R_CCU's on H3/A64. (A31, A23 and A33 seem to have different
>   clock for mux 3 of ar100 clk. Investgations are needed for them.)
> 
>  Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 18 +++++++++++++++++-
>  1 file changed, 17 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> index 68512aa398a9..4a4addff595d 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> @@ -7,9 +7,11 @@ Required properties :
>  		- "allwinner,sun8i-a23-ccu"
>  		- "allwinner,sun8i-a33-ccu"
>  		- "allwinner,sun8i-h3-ccu"
> +		- "allwinner,sun8i-h3-r-ccu"
>  		- "allwinner,sun8i-v3s-ccu"
>  		- "allwinner,sun9i-a80-ccu"
>  		- "allwinner,sun50i-a64-ccu"
> +		- "allwinner,sun50i-a64-r-ccu"
>  		- "allwinner,sun50i-h5-ccu"
>  
>  - reg: Must contain the registers base address and length
> @@ -20,7 +22,11 @@ Required properties :
>  - #clock-cells : must contain 1
>  - #reset-cells : must contain 1
>  
> -Example:
> +For the PRCM CCUs on H3/A64, one more clock is needed:
> +- "iosc": another frequency oscillator used for CPUS (usually at 32000Hz,
> +          not the same with losc)

This is called the internal oscillator in the datasheet, it would
probably make more sense to call it that way in the documentation too.

This oscillator seems to be clocked at 16MHz, so we should represent
it as such.

And I'm wondering, are you *sure* that it's fed directly from the
internal oscillator, or goes through the registers in the RTC, with
the 32 divider and 16 prescaler by default that makes it at roughly
the same rate (31.25kHz).

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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  reply	other threads:[~2017-03-21  7:41 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-15 17:28 [PATCH v2 0/5] Add support for the R_CCU on Allwinner H3/A64 SoCs Icenowy Zheng
2017-03-15 17:28 ` Icenowy Zheng
     [not found] ` <20170315172808.64011-1-icenowy-ymACFijhrKM@public.gmane.org>
2017-03-15 17:28   ` [PATCH v2 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs Icenowy Zheng
2017-03-15 17:28     ` Icenowy Zheng
2017-03-21  7:41     ` Maxime Ripard [this message]
2017-03-21  7:41       ` Maxime Ripard
2017-03-21  7:41       ` Maxime Ripard
2017-03-21 18:22       ` Icenowy Zheng
2017-03-21 18:22         ` Icenowy Zheng
2017-03-22 20:09         ` Maxime Ripard
2017-03-22 20:09           ` Maxime Ripard
2017-03-22 20:09           ` Maxime Ripard
2017-03-22 23:17           ` Icenowy Zheng
2017-03-22 23:17             ` Icenowy Zheng
2017-03-26 13:10             ` Maxime Ripard
2017-03-26 13:10               ` Maxime Ripard
2017-03-26 13:10               ` Maxime Ripard
2017-03-15 17:28   ` [PATCH v2 2/5] clk: sunxi-ng: add support for " Icenowy Zheng
2017-03-15 17:28     ` Icenowy Zheng
2017-03-15 17:28   ` [PATCH v2 3/5] arm64: allwinner: a64: add r_ccu node Icenowy Zheng
2017-03-15 17:28     ` Icenowy Zheng
2017-03-15 17:28   ` [PATCH v2 4/5] ARM: sun8i: h3: switch apb0-related clocks to r_ccu Icenowy Zheng
2017-03-15 17:28     ` Icenowy Zheng
2017-03-15 17:28   ` [PATCH v2 5/5] arm64: allwinner: a64: add R_PIO pinctrl node Icenowy Zheng
2017-03-15 17:28     ` Icenowy Zheng
2017-03-27  9:11 [PATCH v2 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs Icenowy Zheng
2017-03-27  9:11 Icenowy Zheng
2017-03-27 13:47 ` Maxime Ripard
2017-03-27 13:47   ` Maxime Ripard
2017-03-27 13:47   ` Maxime Ripard
2017-03-27 19:13   ` icenowy
2017-03-27 19:13     ` icenowy at aosc.io
2017-03-27 19:13     ` icenowy-h8G6r0blFSE

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