From: "Andreas Färber" <afaerber@suse.de> To: linux-arm-kernel@lists.infradead.org Cc: mp-cs@actions-semi.com, "Thomas Liau" <thomas.liau@actions-semi.com>, 张东风 <zhangdf@actions-semi.com>, 刘炜 <liuwei@actions-semi.com>, 张天益 <tyzhang@actions-semi.com>, 96boards@ucrobotics.com, support@lemaker.org, linux-kernel@vger.kernel.org, "Andreas Färber" <afaerber@suse.de>, "Russell King" <linux@armlinux.org.uk> Subject: [PATCH v4 20/28] ARM: owl: Implement CPU enable-method for S500 Date: Tue, 6 Jun 2017 02:54:18 +0200 [thread overview] Message-ID: <20170606005426.26446-21-afaerber@suse.de> (raw) In-Reply-To: <20170606005426.26446-1-afaerber@suse.de> Allow to bring up CPU1. Based on LeMaker linux-actions tree. Signed-off-by: Andreas Färber <afaerber@suse.de> --- v3 -> v4: Unchanged v3: new arch/arm/mach-actions/Makefile | 3 + arch/arm/mach-actions/headsmp.S | 68 ++++++++++++++++ arch/arm/mach-actions/platsmp.c | 166 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 237 insertions(+) create mode 100644 arch/arm/mach-actions/headsmp.S create mode 100644 arch/arm/mach-actions/platsmp.c diff --git a/arch/arm/mach-actions/Makefile b/arch/arm/mach-actions/Makefile index 524c3817bcb3..217e95d04b43 100644 --- a/arch/arm/mach-actions/Makefile +++ b/arch/arm/mach-actions/Makefile @@ -1 +1,4 @@ obj-$(CONFIG_ARCH_ACTIONS) += owl.o +obj-${CONFIG_ARCH_ACTIONS} += platsmp.o headsmp.o + +AFLAGS_headsmp.o := -Wa,-march=armv7-a diff --git a/arch/arm/mach-actions/headsmp.S b/arch/arm/mach-actions/headsmp.S new file mode 100644 index 000000000000..dc4832fc101a --- /dev/null +++ b/arch/arm/mach-actions/headsmp.S @@ -0,0 +1,68 @@ +/* + * Copyright 2012 Actions Semi Inc. + * Author: Actions Semi, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <linux/linkage.h> +#include <linux/init.h> + +ENTRY(owl_v7_invalidate_l1) + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache + mcr p15, 2, r0, c0, c0, 0 + mrc p15, 1, r0, c0, c0, 0 + + ldr r1, =0x7fff + and r2, r1, r0, lsr #13 + + ldr r1, =0x3ff + + and r3, r1, r0, lsr #3 @ NumWays - 1 + add r2, r2, #1 @ NumSets + + and r0, r0, #0x7 + add r0, r0, #4 @ SetShift + + clz r1, r3 @ WayShift + add r4, r3, #1 @ NumWays +1: sub r2, r2, #1 @ NumSets-- + mov r3, r4 @ Temp = NumWays +2: subs r3, r3, #1 @ Temp-- + mov r5, r3, lsl r1 + mov r6, r2, lsl r0 + orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) + mcr p15, 0, r5, c7, c6, 2 + bgt 2b + cmp r2, #0 + bgt 1b + dsb + isb + mov pc, lr +ENDPROC(owl_v7_invalidate_l1) + +ENTRY(owl_secondary_startup) + mrc p15, 0, r0, c0, c0, 5 + and r0, r0, #0xf + adr r4, 1f + ldmia r4, {r5, r6} + sub r4, r4, r5 + add r6, r6, r4 +pen: + ldr r7, [r6] + cmp r7, r0 + bne pen + + /* + * we've been released from the holding pen: secondary_stack + * should now contain the SVC stack for this core + */ + bl owl_v7_invalidate_l1 + b secondary_startup + +1: .long . + .long pen_release diff --git a/arch/arm/mach-actions/platsmp.c b/arch/arm/mach-actions/platsmp.c new file mode 100644 index 000000000000..9d3601ebe535 --- /dev/null +++ b/arch/arm/mach-actions/platsmp.c @@ -0,0 +1,166 @@ +/* + * Actions Semi Leopard + * + * This file is based on arm realview smp platform. + * + * Copyright 2012 Actions Semi Inc. + * Author: Actions Semi, Inc. + * + * Copyright (c) 2017 Andreas Färber + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/smp.h> +#include <asm/cacheflush.h> +#include <asm/smp_plat.h> +#include <asm/smp_scu.h> + +#define OWL_CPU1_ADDR 0x50 +#define OWL_CPU1_FLAG 0x5c + +#define OWL_CPUx_FLAG_BOOT 0x55aa + +static void __iomem *scu_base_addr; +static void __iomem *timer_base_addr; +static int ncores; + +static DEFINE_SPINLOCK(boot_lock); + +static void write_pen_release(int val) +{ + pen_release = val; + smp_wmb(); + __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); + outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); +} + +static void s500_smp_secondary_init(unsigned int cpu) +{ + /* + * let the primary processor know we're out of the + * pen, then head off into the C entry point + */ + write_pen_release(-1); + + spin_lock(&boot_lock); + spin_unlock(&boot_lock); +} + +void owl_secondary_startup(void); + +static int s500_wakeup_secondary(unsigned int cpu) +{ + if (cpu > 3) + return -EINVAL; + + switch (cpu) { + case 2: + case 3: + /* CPU2/3 are power-gated */ + return -EINVAL; + } + + /* wait for CPUx to run to WFE instruction */ + udelay(200); + + writel(virt_to_phys(owl_secondary_startup), + timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4); + writel(OWL_CPUx_FLAG_BOOT, + timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4); + + dsb_sev(); + mb(); + + return 0; +} + +static int s500_smp_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + unsigned long timeout; + int ret; + + ret = s500_wakeup_secondary(cpu); + if (ret) + return ret; + + udelay(10); + + spin_lock(&boot_lock); + + /* + * The secondary processor is waiting to be released from + * the holding pen - release it, then wait for it to flag + * that it has been released by resetting pen_release. + */ + write_pen_release(cpu_logical_map(cpu)); + smp_send_reschedule(cpu); + + timeout = jiffies + (1 * HZ); + while (time_before(jiffies, timeout)) { + if (pen_release == -1) + break; + } + + writel(0, timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4); + writel(0, timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4); + + spin_unlock(&boot_lock); + + return pen_release != -1 ? -ENOSYS : 0; +} + +static void __init s500_smp_prepare_cpus(unsigned int max_cpus) +{ + struct device_node *node; + + node = of_find_compatible_node(NULL, NULL, "actions,s500-timer"); + if (!node) { + pr_err("%s: missing timer\n", __func__); + return; + } + + timer_base_addr = of_iomap(node, 0); + if (!timer_base_addr) { + pr_err("%s: could not map timer registers\n", __func__); + return; + } + + if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) { + node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); + if (!node) { + pr_err("%s: missing scu\n", __func__); + return; + } + + scu_base_addr = of_iomap(node, 0); + if (!scu_base_addr) { + pr_err("%s: could not map scu registers\n", __func__); + return; + } + + /* + * While the number of cpus is gathered from dt, also get the + * number of cores from the scu to verify this value when + * booting the cores. + */ + ncores = scu_get_core_count(scu_base_addr); + pr_debug("%s: ncores %d\n", __func__, ncores); + + scu_enable(scu_base_addr); + } +} + +static const struct smp_operations s500_smp_ops __initconst = { + .smp_prepare_cpus = s500_smp_prepare_cpus, + .smp_secondary_init = s500_smp_secondary_init, + .smp_boot_secondary = s500_smp_boot_secondary, +}; +CPU_METHOD_OF_DECLARE(s500_smp, "actions,s500-smp", &s500_smp_ops); -- 2.12.3
WARNING: multiple messages have this Message-ID (diff)
From: afaerber@suse.de (Andreas Färber) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 20/28] ARM: owl: Implement CPU enable-method for S500 Date: Tue, 6 Jun 2017 02:54:18 +0200 [thread overview] Message-ID: <20170606005426.26446-21-afaerber@suse.de> (raw) In-Reply-To: <20170606005426.26446-1-afaerber@suse.de> Allow to bring up CPU1. Based on LeMaker linux-actions tree. Signed-off-by: Andreas F?rber <afaerber@suse.de> --- v3 -> v4: Unchanged v3: new arch/arm/mach-actions/Makefile | 3 + arch/arm/mach-actions/headsmp.S | 68 ++++++++++++++++ arch/arm/mach-actions/platsmp.c | 166 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 237 insertions(+) create mode 100644 arch/arm/mach-actions/headsmp.S create mode 100644 arch/arm/mach-actions/platsmp.c diff --git a/arch/arm/mach-actions/Makefile b/arch/arm/mach-actions/Makefile index 524c3817bcb3..217e95d04b43 100644 --- a/arch/arm/mach-actions/Makefile +++ b/arch/arm/mach-actions/Makefile @@ -1 +1,4 @@ obj-$(CONFIG_ARCH_ACTIONS) += owl.o +obj-${CONFIG_ARCH_ACTIONS} += platsmp.o headsmp.o + +AFLAGS_headsmp.o := -Wa,-march=armv7-a diff --git a/arch/arm/mach-actions/headsmp.S b/arch/arm/mach-actions/headsmp.S new file mode 100644 index 000000000000..dc4832fc101a --- /dev/null +++ b/arch/arm/mach-actions/headsmp.S @@ -0,0 +1,68 @@ +/* + * Copyright 2012 Actions Semi Inc. + * Author: Actions Semi, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <linux/linkage.h> +#include <linux/init.h> + +ENTRY(owl_v7_invalidate_l1) + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache + mcr p15, 2, r0, c0, c0, 0 + mrc p15, 1, r0, c0, c0, 0 + + ldr r1, =0x7fff + and r2, r1, r0, lsr #13 + + ldr r1, =0x3ff + + and r3, r1, r0, lsr #3 @ NumWays - 1 + add r2, r2, #1 @ NumSets + + and r0, r0, #0x7 + add r0, r0, #4 @ SetShift + + clz r1, r3 @ WayShift + add r4, r3, #1 @ NumWays +1: sub r2, r2, #1 @ NumSets-- + mov r3, r4 @ Temp = NumWays +2: subs r3, r3, #1 @ Temp-- + mov r5, r3, lsl r1 + mov r6, r2, lsl r0 + orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) + mcr p15, 0, r5, c7, c6, 2 + bgt 2b + cmp r2, #0 + bgt 1b + dsb + isb + mov pc, lr +ENDPROC(owl_v7_invalidate_l1) + +ENTRY(owl_secondary_startup) + mrc p15, 0, r0, c0, c0, 5 + and r0, r0, #0xf + adr r4, 1f + ldmia r4, {r5, r6} + sub r4, r4, r5 + add r6, r6, r4 +pen: + ldr r7, [r6] + cmp r7, r0 + bne pen + + /* + * we've been released from the holding pen: secondary_stack + * should now contain the SVC stack for this core + */ + bl owl_v7_invalidate_l1 + b secondary_startup + +1: .long . + .long pen_release diff --git a/arch/arm/mach-actions/platsmp.c b/arch/arm/mach-actions/platsmp.c new file mode 100644 index 000000000000..9d3601ebe535 --- /dev/null +++ b/arch/arm/mach-actions/platsmp.c @@ -0,0 +1,166 @@ +/* + * Actions Semi Leopard + * + * This file is based on arm realview smp platform. + * + * Copyright 2012 Actions Semi Inc. + * Author: Actions Semi, Inc. + * + * Copyright (c) 2017 Andreas F?rber + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/smp.h> +#include <asm/cacheflush.h> +#include <asm/smp_plat.h> +#include <asm/smp_scu.h> + +#define OWL_CPU1_ADDR 0x50 +#define OWL_CPU1_FLAG 0x5c + +#define OWL_CPUx_FLAG_BOOT 0x55aa + +static void __iomem *scu_base_addr; +static void __iomem *timer_base_addr; +static int ncores; + +static DEFINE_SPINLOCK(boot_lock); + +static void write_pen_release(int val) +{ + pen_release = val; + smp_wmb(); + __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); + outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); +} + +static void s500_smp_secondary_init(unsigned int cpu) +{ + /* + * let the primary processor know we're out of the + * pen, then head off into the C entry point + */ + write_pen_release(-1); + + spin_lock(&boot_lock); + spin_unlock(&boot_lock); +} + +void owl_secondary_startup(void); + +static int s500_wakeup_secondary(unsigned int cpu) +{ + if (cpu > 3) + return -EINVAL; + + switch (cpu) { + case 2: + case 3: + /* CPU2/3 are power-gated */ + return -EINVAL; + } + + /* wait for CPUx to run to WFE instruction */ + udelay(200); + + writel(virt_to_phys(owl_secondary_startup), + timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4); + writel(OWL_CPUx_FLAG_BOOT, + timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4); + + dsb_sev(); + mb(); + + return 0; +} + +static int s500_smp_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + unsigned long timeout; + int ret; + + ret = s500_wakeup_secondary(cpu); + if (ret) + return ret; + + udelay(10); + + spin_lock(&boot_lock); + + /* + * The secondary processor is waiting to be released from + * the holding pen - release it, then wait for it to flag + * that it has been released by resetting pen_release. + */ + write_pen_release(cpu_logical_map(cpu)); + smp_send_reschedule(cpu); + + timeout = jiffies + (1 * HZ); + while (time_before(jiffies, timeout)) { + if (pen_release == -1) + break; + } + + writel(0, timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4); + writel(0, timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4); + + spin_unlock(&boot_lock); + + return pen_release != -1 ? -ENOSYS : 0; +} + +static void __init s500_smp_prepare_cpus(unsigned int max_cpus) +{ + struct device_node *node; + + node = of_find_compatible_node(NULL, NULL, "actions,s500-timer"); + if (!node) { + pr_err("%s: missing timer\n", __func__); + return; + } + + timer_base_addr = of_iomap(node, 0); + if (!timer_base_addr) { + pr_err("%s: could not map timer registers\n", __func__); + return; + } + + if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) { + node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); + if (!node) { + pr_err("%s: missing scu\n", __func__); + return; + } + + scu_base_addr = of_iomap(node, 0); + if (!scu_base_addr) { + pr_err("%s: could not map scu registers\n", __func__); + return; + } + + /* + * While the number of cpus is gathered from dt, also get the + * number of cores from the scu to verify this value when + * booting the cores. + */ + ncores = scu_get_core_count(scu_base_addr); + pr_debug("%s: ncores %d\n", __func__, ncores); + + scu_enable(scu_base_addr); + } +} + +static const struct smp_operations s500_smp_ops __initconst = { + .smp_prepare_cpus = s500_smp_prepare_cpus, + .smp_secondary_init = s500_smp_secondary_init, + .smp_boot_secondary = s500_smp_boot_secondary, +}; +CPU_METHOD_OF_DECLARE(s500_smp, "actions,s500-smp", &s500_smp_ops); -- 2.12.3
next prev parent reply other threads:[~2017-06-06 0:58 UTC|newest] Thread overview: 222+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-06-06 0:53 [PATCH v4 00/28] ARM: Initial Actions Semi S500 and S900 enablement Andreas Färber 2017-06-06 0:53 ` Andreas Färber 2017-06-06 0:53 ` Andreas Färber 2017-06-06 0:53 ` [PATCH v4 01/28] dt-bindings: Add vendor prefix for Actions Semi Andreas Färber 2017-06-06 0:53 ` Andreas Färber 2017-06-06 0:53 ` Andreas Färber 2017-06-18 18:46 ` Andreas Färber 2017-06-18 18:46 ` Andreas Färber 2017-06-06 0:54 ` [PATCH v4 02/28] dt-bindings: arm: Document Actions Semi S500 Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-06-18 18:48 ` Andreas Färber 2017-06-18 18:48 ` Andreas Färber 2017-06-18 18:48 ` Andreas Färber 2017-06-06 0:54 ` [PATCH v4 03/28] dt-bindings: timer: Document Owl timer Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-06-18 20:18 ` Andreas Färber 2017-06-18 20:18 ` Andreas Färber 2017-06-18 20:18 ` Andreas Färber 2017-06-06 0:54 ` [PATCH v4 04/28] clocksource: Add " Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-06-06 16:33 ` Daniel Lezcano 2017-06-06 16:33 ` Daniel Lezcano 2017-06-18 20:43 ` Andreas Färber 2017-06-18 20:43 ` Andreas Färber 2017-06-19 13:53 ` Daniel Lezcano 2017-06-19 13:53 ` Daniel Lezcano 2017-06-19 14:31 ` Andreas Färber 2017-06-19 14:31 ` Andreas Färber 2017-06-21 11:57 ` Daniel Lezcano 2017-06-21 11:57 ` Daniel Lezcano 2017-06-06 0:54 ` [PATCH v4 05/28] clocksource: owl: Add S900 support Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-06-06 16:34 ` Daniel Lezcano 2017-06-06 16:34 ` Daniel Lezcano 2017-06-18 20:50 ` Andreas Färber 2017-06-18 20:50 ` Andreas Färber 2017-06-06 0:54 ` [PATCH v4 06/28] ARM: Prepare Actions Semi S500 Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-06-18 21:21 ` Andreas Färber 2017-06-18 21:21 ` Andreas Färber 2017-07-01 21:41 ` [PATCH] ARM: owl: Drop custom machine Andreas Färber 2017-07-01 21:41 ` Andreas Färber 2017-06-06 0:54 ` [PATCH v4 07/28] ARM64: Prepare Actions Semi S900 Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-06-11 13:04 ` Andreas Färber 2017-06-11 13:04 ` Andreas Färber 2017-06-06 0:54 ` [PATCH v4 08/28] dt-bindings: serial: Document Actions Semi Owl UARTs Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-06-06 0:54 ` [PATCH v4 09/28] tty: serial: Add Actions Semi Owl UART earlycon Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-06-18 21:45 ` Andreas Färber 2017-06-18 21:45 ` Andreas Färber 2017-06-19 1:16 ` Greg Kroah-Hartman 2017-06-19 1:16 ` Greg Kroah-Hartman 2017-06-19 1:24 ` Andreas Färber 2017-06-19 1:24 ` Andreas Färber 2017-06-19 1:46 ` [PATCH v5 07/26] dt-bindings: serial: Document Actions Semi Owl UARTs Andreas Färber 2017-06-19 1:46 ` Andreas Färber 2017-06-19 1:46 ` Andreas Färber 2017-06-19 1:46 ` [PATCH v5 08/26] tty: serial: Add Actions Semi Owl UART earlycon Andreas Färber 2017-06-19 1:46 ` Andreas Färber 2017-06-19 2:12 ` [PATCH v4 09/28] " Greg Kroah-Hartman 2017-06-19 2:12 ` Greg Kroah-Hartman 2017-06-19 2:26 ` Andreas Färber 2017-06-19 2:26 ` Andreas Färber 2017-06-06 0:54 ` [PATCH v4 10/28] Documentation: kernel-parameters: Document owl earlycon Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-06-06 0:54 ` [PATCH v4 11/28] ARM: dts: Add Actions Semi S500 and LeMaker Guitar Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-06-18 22:10 ` Andreas Färber 2017-06-18 22:10 ` Andreas Färber 2017-06-18 22:10 ` Andreas Färber 2017-06-19 1:08 ` [PATCH v5 10/27] " Andreas Färber 2017-06-19 1:08 ` Andreas Färber 2017-06-19 1:08 ` Andreas Färber 2017-06-19 2:01 ` Andreas Färber 2017-06-19 2:01 ` Andreas Färber 2017-06-19 2:01 ` Andreas Färber 2017-06-06 0:54 ` [PATCH v4 12/28] dt-bindings: Add vendor prefix for uCRobotics Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-06-18 22:19 ` Andreas Färber 2017-06-18 22:19 ` Andreas Färber 2017-06-18 22:19 ` Andreas Färber 2017-06-06 0:54 ` [PATCH v4 13/28] dt-bindings: arm: Document Actions Semi S900 Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-06-18 22:29 ` Andreas Färber 2017-06-18 22:29 ` Andreas Färber 2017-06-18 22:29 ` Andreas Färber 2017-06-06 0:54 ` [PATCH v4 14/28] ARM64: dts: Add Actions Semi S900 and Bubblegum-96 Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-06-18 22:40 ` Andreas Färber 2017-06-18 22:40 ` Andreas Färber 2017-06-18 22:40 ` Andreas Färber 2017-06-06 0:54 ` [PATCH v4 15/28] MAINTAINERS: Add Actions Semi Owl section Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-06-18 22:49 ` Andreas Färber 2017-06-18 22:49 ` Andreas Färber 2017-06-19 2:44 ` [PATCH v5 13/26] " Andreas Färber 2017-06-19 2:44 ` Andreas Färber 2017-06-26 6:56 ` 答复: " 张天益 2017-06-26 6:56 ` 张天益 2017-06-06 0:54 ` [PATCH v4 16/28] tty: serial: owl: Implement console driver Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-06-06 13:34 ` Alan Cox 2017-06-06 13:34 ` Alan Cox 2017-06-06 13:34 ` Alan Cox 2017-07-02 20:27 ` Andreas Färber 2017-07-02 20:27 ` Andreas Färber 2017-06-07 14:37 ` Andy Shevchenko 2017-06-07 14:37 ` Andy Shevchenko 2017-06-07 14:37 ` Andy Shevchenko 2017-07-02 22:36 ` Andreas Färber 2017-07-02 22:36 ` Andreas Färber 2017-06-06 0:54 ` [PATCH v4 17/28] ARM64: dts: actions: s900-bubblegum-96: Add fake uart5 clock Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-09-05 21:29 ` Andreas Färber 2017-09-05 21:29 ` Andreas Färber 2017-09-05 21:29 ` Andreas Färber 2017-06-06 0:54 ` [PATCH v4 18/28] ARM: dts: s500-guitar-bb-rev-b: Add fake uart3 clock Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-09-05 21:37 ` Andreas Färber 2017-09-05 21:37 ` Andreas Färber 2017-06-06 0:54 ` [PATCH v4 19/28] dt-bindings: arm: cpus: Add S500 enable-method Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-06-19 2:09 ` Andreas Färber 2017-06-19 2:09 ` Andreas Färber 2017-06-19 2:09 ` Andreas Färber 2017-06-06 0:54 ` Andreas Färber [this message] 2017-06-06 0:54 ` [PATCH v4 20/28] ARM: owl: Implement CPU enable-method for S500 Andreas Färber 2017-06-19 2:11 ` Andreas Färber 2017-06-19 2:11 ` Andreas Färber 2017-06-21 8:16 ` Arnd Bergmann 2017-06-21 8:16 ` Arnd Bergmann 2017-06-21 10:25 ` Arnd Bergmann 2017-06-21 10:25 ` Arnd Bergmann 2017-06-21 16:48 ` Andreas Färber 2017-06-21 16:48 ` Andreas Färber 2017-06-21 18:02 ` Arnd Bergmann 2017-06-21 18:02 ` Arnd Bergmann 2017-06-29 15:07 ` Arnd Bergmann 2017-06-29 15:07 ` Arnd Bergmann 2017-06-29 15:22 ` Andreas Färber 2017-06-29 15:22 ` Andreas Färber 2017-06-29 15:50 ` Arnd Bergmann 2017-06-29 15:50 ` Arnd Bergmann 2017-07-01 21:29 ` [PATCH] ARM: owl: smp: Drop bogus holding pen Andreas Färber 2017-07-01 21:29 ` Andreas Färber 2017-07-03 12:35 ` Arnd Bergmann 2017-07-03 12:35 ` Arnd Bergmann 2017-07-01 4:42 ` 答复: [PATCH v4 20/28] ARM: owl: Implement CPU enable-method for S500 刘炜 2017-07-01 4:42 ` 刘炜 2017-07-01 19:56 ` Andreas Färber 2017-07-01 19:56 ` Andreas Färber 2017-07-03 8:13 ` 刘炜 2017-07-03 8:13 ` 刘炜 2017-07-04 23:32 ` [PATCH] ARM: owl: smp: Drop owl_secondary_boot() Andreas Färber 2017-07-04 23:32 ` Andreas Färber 2017-07-05 2:36 ` Florian Fainelli 2017-07-05 2:36 ` Florian Fainelli 2017-07-06 17:17 ` Andreas Färber 2017-07-06 17:17 ` Andreas Färber 2017-07-06 17:38 ` Alexandre Belloni 2017-07-06 17:38 ` Alexandre Belloni 2017-07-06 19:47 ` Florian Fainelli 2017-07-06 19:47 ` Florian Fainelli 2017-07-07 7:34 ` Gregory CLEMENT 2017-07-07 7:34 ` Gregory CLEMENT 2017-07-07 17:32 ` Florian Fainelli 2017-07-07 17:32 ` Florian Fainelli 2017-07-06 17:39 ` Mark Rutland 2017-07-06 17:39 ` Mark Rutland 2017-07-06 21:16 ` Florian Fainelli 2017-07-06 21:16 ` Florian Fainelli 2017-07-09 21:55 ` Andreas Färber 2017-07-09 21:55 ` Andreas Färber 2017-07-10 4:27 ` Florian Fainelli 2017-07-10 4:27 ` Florian Fainelli 2017-06-06 0:54 ` [PATCH v4 21/28] ARM: dts: s500: Set CPU enable-method Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-06-19 2:09 ` Andreas Färber 2017-06-19 2:09 ` Andreas Färber 2017-06-19 2:09 ` Andreas Färber 2017-06-06 0:54 ` [PATCH v4 22/28] dt-bindings: power: Add Owl SPS power domains Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-06-19 3:36 ` [PATCH v5 20/26] " Andreas Färber 2017-06-19 3:36 ` Andreas Färber 2017-06-19 3:36 ` Andreas Färber 2017-06-19 3:57 ` Andreas Färber 2017-06-19 3:57 ` Andreas Färber 2017-06-19 3:57 ` Andreas Färber 2017-06-06 0:54 ` [PATCH v4 23/28] soc: actions: Add Owl SPS Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-06-19 3:40 ` [PATCH v5 21/26] " Andreas Färber 2017-06-19 3:40 ` Andreas Färber 2017-06-19 3:59 ` Andreas Färber 2017-06-19 3:59 ` Andreas Färber 2017-06-06 0:54 ` [PATCH v4 24/28] MAINTAINERS: Update Actions Semi section with SPS Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-06-19 3:44 ` [PATCH v5 22/26] " Andreas Färber 2017-06-19 3:44 ` Andreas Färber 2017-06-19 4:00 ` Andreas Färber 2017-06-19 4:00 ` Andreas Färber 2017-06-06 0:54 ` [PATCH v4 25/28] ARM: dts: s500: Add SPS node Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-06-19 4:01 ` Andreas Färber 2017-06-19 4:01 ` Andreas Färber 2017-06-19 4:01 ` Andreas Färber 2017-06-06 0:54 ` [PATCH v4 26/28] ARM: dts: s500: Set power domains for CPU2 and CPU3 Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-07-27 20:58 ` Andreas Färber 2017-07-27 20:58 ` Andreas Färber 2017-06-06 0:54 ` [PATCH v4 27/28] soc: actions: owl-sps: Factor out owl_sps_set_pg() for power-gating Andreas Färber 2017-06-06 0:54 ` Andreas Färber 2017-06-19 4:12 ` Andreas Färber 2017-06-19 4:12 ` Andreas Färber 2017-06-06 0:54 ` [PATCH v4 28/28] ARM: owl: smp: Implement SPS power-gating for CPU2 and CPU3 Andreas Färber 2017-06-06 0:54 ` Andreas Färber
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