[U-Boot] [PATCH v2 1/7] db820c: set clk node to be probed before relocation

[U-Boot] [PATCH v2 1/7] db820c: set clk node to be probed before relocation

[Ramon Fried]

The clock and serial nodes are needed before relocation.
This patch ensures that the msm-serial driver will probe
and provide uart output before relocation.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
---
v2: fixed alignment
 arch/arm/dts/dragonboard820c-uboot.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/dts/dragonboard820c-uboot.dtsi b/arch/arm/dts/dragonboard820c-uboot.dtsi
index 88312b3fa1..97394cc5b0 100644
--- a/arch/arm/dts/dragonboard820c-uboot.dtsi
+++ b/arch/arm/dts/dragonboard820c-uboot.dtsi
@@ -5,6 +5,20 @@
  * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
  */
 
+/ {
+	soc {
+		u-boot,dm-pre-reloc;
+
+		clock-controller at 300000 {
+			u-boot,dm-pre-reloc;
+		};
+
+		serial at 75b0000 {
+			u-boot,dm-pre-reloc;
+			};
+		};
+};
+
 &pm8994_pon {
 	key_vol_down {
 		gpios = <&pm8994_pon 1 0>;
-- 
2.17.0

[U-Boot] [PATCH v2 2/7] serial: serial_msm: fail probe if settings clocks fails

[Ramon Fried]

Failure to set the clocks will causes data abort exception when
trying to write to AHB uart registers.
This patch ensures that we don't touch these registers if clock
setting failed.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
---
v2: on failure, return actual return code from msm_uart_clk_init

 drivers/serial/serial_msm.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index 119e6b9846..8b585deeeb 100644
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -181,10 +181,12 @@ static int msm_uart_clk_init(struct udevice *dev)
 
 static int msm_serial_probe(struct udevice *dev)
 {
+	int ret;
 	struct msm_serial_data *priv = dev_get_priv(dev);
 
-	msm_uart_clk_init(dev); /* Ignore return value and hope clock was
-				  properly initialized by earlier loaders */
+	ret = msm_uart_clk_init(dev);
+	if (ret)
+		return ret;
 
 	if (readl(priv->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN)
 		writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR);
-- 
2.17.0

[U-Boot] [PATCH v2 3/7] serial: serial_msm: initialize uart only before relocation

[Ramon Fried]

The uart is already initialized prior to relocation,
reinitialization after relocation is unnecessary.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
---
v2: removed extra parenthesis

 drivers/serial/serial_msm.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index 8b585deeeb..a4279accb4 100644
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -184,6 +184,10 @@ static int msm_serial_probe(struct udevice *dev)
 	int ret;
 	struct msm_serial_data *priv = dev_get_priv(dev);
 
+	/* No need to reinitialize the UART after relocation */
+	if (gd->flags & GD_FLG_RELOC)
+		return 0;
+
 	ret = msm_uart_clk_init(dev);
 	if (ret)
 		return ret;
-- 
2.17.0

[U-Boot] [PATCH v2 4/7] mach-snapdragon: Fix UART clock flow

[Ramon Fried]

UART clock enabling flow was wrong.
Changed the flow according to downstream implementation in LK.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
---
 arch/arm/mach-snapdragon/clock-apq8016.c      | 23 +++++++++++++------
 arch/arm/mach-snapdragon/clock-apq8096.c      |  4 ++--
 arch/arm/mach-snapdragon/clock-snapdragon.c   | 17 +++++++++++++-
 arch/arm/mach-snapdragon/clock-snapdragon.h   |  9 ++++++--
 .../include/mach/sysmap-apq8016.h             |  1 +
 5 files changed, 42 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-snapdragon/clock-apq8016.c b/arch/arm/mach-snapdragon/clock-apq8016.c
index 9c0cc1c22c..6e4a0ccb90 100644
--- a/arch/arm/mach-snapdragon/clock-apq8016.c
+++ b/arch/arm/mach-snapdragon/clock-apq8016.c
@@ -17,7 +17,6 @@
 
 /* GPLL0 clock control registers */
 #define GPLL0_STATUS_ACTIVE BIT(17)
-#define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0)
 
 static const struct bcr_regs sdc_regs[] = {
 	{
@@ -36,11 +35,17 @@ static const struct bcr_regs sdc_regs[] = {
 	}
 };
 
-static struct gpll0_ctrl gpll0_ctrl = {
+static struct pll_vote_clk gpll0_vote_clk = {
 	.status = GPLL0_STATUS,
 	.status_bit = GPLL0_STATUS_ACTIVE,
 	.ena_vote = APCS_GPLL_ENA_VOTE,
-	.vote_bit = APCS_GPLL_ENA_VOTE_GPLL0,
+	.vote_bit = BIT(0),
+};
+
+static struct vote_clk gcc_blsp1_ahb_clk = {
+	.cbcr_reg = BLSP1_AHB_CBCR,
+	.ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
+	.vote_bit = BIT(10),
 };
 
 /* SDHCI */
@@ -55,7 +60,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)
 	/* 800Mhz/div, gpll0 */
 	clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0,
 			     CFG_CLK_SRC_GPLL0);
-	clk_enable_gpll0(priv->base, &gpll0_ctrl);
+	clk_enable_gpll0(priv->base, &gpll0_vote_clk);
 	clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot));
 
 	return rate;
@@ -72,12 +77,16 @@ static const struct bcr_regs uart2_regs = {
 /* UART: 115200 */
 static int clk_init_uart(struct msm_clk_priv *priv)
 {
-	/* Enable iface clk */
-	clk_enable_cbc(priv->base + BLSP1_AHB_CBCR);
+	/* Enable AHB clock */
+	clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
+
 	/* 7372800 uart block clock @ GPLL0 */
 	clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625,
 			     CFG_CLK_SRC_GPLL0);
-	clk_enable_gpll0(priv->base, &gpll0_ctrl);
+
+	/* Vote for gpll0 clock */
+	clk_enable_gpll0(priv->base, &gpll0_vote_clk);
+
 	/* Enable core clk */
 	clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
 
diff --git a/arch/arm/mach-snapdragon/clock-apq8096.c b/arch/arm/mach-snapdragon/clock-apq8096.c
index 008649a4c6..628c38785b 100644
--- a/arch/arm/mach-snapdragon/clock-apq8096.c
+++ b/arch/arm/mach-snapdragon/clock-apq8096.c
@@ -27,7 +27,7 @@ static const struct bcr_regs sdc_regs = {
 	.D = SDCC2_D,
 };
 
-static const struct gpll0_ctrl gpll0_ctrl = {
+static const struct pll_vote_clk gpll0_vote_clk = {
 	.status = GPLL0_STATUS,
 	.status_bit = GPLL0_STATUS_ACTIVE,
 	.ena_vote = APCS_GPLL_ENA_VOTE,
@@ -41,7 +41,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, uint rate)
 	clk_enable_cbc(priv->base + SDCC2_AHB_CBCR);
 	clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0,
 			     CFG_CLK_SRC_GPLL0);
-	clk_enable_gpll0(priv->base, &gpll0_ctrl);
+	clk_enable_gpll0(priv->base, &gpll0_vote_clk);
 	clk_enable_cbc(priv->base + SDCC2_APPS_CBCR);
 
 	return rate;
diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c
index f738f57043..85526186c6 100644
--- a/arch/arm/mach-snapdragon/clock-snapdragon.c
+++ b/arch/arm/mach-snapdragon/clock-snapdragon.c
@@ -30,7 +30,7 @@ void clk_enable_cbc(phys_addr_t cbcr)
 		;
 }
 
-void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *gpll0)
+void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0)
 {
 	if (readl(base + gpll0->status) & gpll0->status_bit)
 		return; /* clock already enabled */
@@ -41,6 +41,21 @@ void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *gpll0)
 		;
 }
 
+#define BRANCH_ON_VAL (0)
+#define BRANCH_NOC_FSM_ON_VAL BIT(29)
+#define BRANCH_CHECK_MASK GENMASK(31, 28)
+
+void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk)
+{
+	u32 val;
+
+	setbits_le32(base + vclk->ena_vote, vclk->vote_bit);
+	do {
+		val = readl(base + vclk->cbcr_reg);
+		val &= BRANCH_CHECK_MASK;
+	} while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL));
+}
+
 #define APPS_CMD_RGCR_UPDATE BIT(0)
 
 /* Update clock command via CMD_RGCR */
diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.h b/arch/arm/mach-snapdragon/clock-snapdragon.h
index 2cff4f8a06..3ae21099c2 100644
--- a/arch/arm/mach-snapdragon/clock-snapdragon.h
+++ b/arch/arm/mach-snapdragon/clock-snapdragon.h
@@ -11,13 +11,18 @@
 #define CFG_CLK_SRC_GPLL0 (1 << 8)
 #define CFG_CLK_SRC_MASK  (7 << 8)
 
-struct gpll0_ctrl {
+struct pll_vote_clk {
 	uintptr_t status;
 	int status_bit;
 	uintptr_t ena_vote;
 	int vote_bit;
 };
 
+struct vote_clk {
+	uintptr_t cbcr_reg;
+	uintptr_t ena_vote;
+	int vote_bit;
+};
 struct bcr_regs {
 	uintptr_t cfg_rcgr;
 	uintptr_t cmd_rcgr;
@@ -30,7 +35,7 @@ struct msm_clk_priv {
 	phys_addr_t base;
 };
 
-void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *pll0);
+void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0);
 void clk_bcr_update(phys_addr_t apps_cmd_rgcr);
 void clk_enable_cbc(phys_addr_t cbcr);
 void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h
index ae784387fa..520e2e6bd7 100644
--- a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h
+++ b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h
@@ -13,6 +13,7 @@
 /* Clocks: (from CLK_CTL_BASE)  */
 #define GPLL0_STATUS			(0x2101C)
 #define APCS_GPLL_ENA_VOTE		(0x45000)
+#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004)
 
 #define SDCC_BCR(n)			((n * 0x1000) + 0x41000)
 #define SDCC_CMD_RCGR(n)		((n * 0x1000) + 0x41004)
-- 
2.17.0

[U-Boot] [PATCH v2 5/7] mach-snapdragon: Introduce pinctrl driver

[Ramon Fried]

This patch adds pinmux and pinctrl driver for TLMM
subsystem in snapdragon chipsets.
Currently, supporting only 8016, but implementation is
generic and 8096 can be added easily.

Driver is using the generic dt-bindings and doesn't
introduce any new bindings (yet).

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
---
v2: * restructred the code to be more generic
	* Reduced pin table size by snprintf on runtime as 
	  suggested by Simon.

 arch/arm/mach-snapdragon/Makefile             |   2 +
 arch/arm/mach-snapdragon/pinctrl-apq8016.c    |  62 +++++++++
 arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 128 ++++++++++++++++++
 arch/arm/mach-snapdragon/pinctrl-snapdragon.h |  29 ++++
 configs/dragonboard410c_defconfig             |   5 +
 .../dt-bindings/pinctrl/pinctrl-snapdragon.h  |  22 +++
 6 files changed, 248 insertions(+)
 create mode 100644 arch/arm/mach-snapdragon/pinctrl-apq8016.c
 create mode 100644 arch/arm/mach-snapdragon/pinctrl-snapdragon.c
 create mode 100644 arch/arm/mach-snapdragon/pinctrl-snapdragon.h
 create mode 100644 include/dt-bindings/pinctrl/pinctrl-snapdragon.h

diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile
index 1c23dc52cf..1d35fea912 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -6,4 +6,6 @@ obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o
 obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o
 obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o
 obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o
+obj-$(CONFIG_TARGET_DRAGONBOARD410C) += pinctrl-apq8016.o
+obj-$(CONFIG_TARGET_DRAGONBOARD410C) += pinctrl-snapdragon.o
 obj-y += clock-snapdragon.o
diff --git a/arch/arm/mach-snapdragon/pinctrl-apq8016.c b/arch/arm/mach-snapdragon/pinctrl-apq8016.c
new file mode 100644
index 0000000000..602af1b1d3
--- /dev/null
+++ b/arch/arm/mach-snapdragon/pinctrl-apq8016.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm APQ8016 pinctrl
+ *
+ * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
+ *
+ */
+
+#include "pinctrl-snapdragon.h"
+#include <common.h>
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN];
+static const char * const msm_pinctrl_pins[] = {
+	"SDC1_CLK",
+	"SDC1_CMD",
+	"SDC1_DATA",
+	"SDC2_CLK",
+	"SDC2_CMD",
+	"SDC2_DATA",
+	"QDSD_CLK",
+	"QDSD_CMD",
+	"QDSD_DATA0",
+	"QDSD_DATA1",
+	"QDSD_DATA2",
+	"QDSD_DATA3",
+};
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+	{"blsp1_uart", 2},
+};
+
+static const char *apq8016_get_function_name(struct udevice *dev,
+					     unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].name;
+}
+
+static const char *apq8016_get_pin_name(struct udevice *dev,
+					unsigned int selector)
+{
+	if (selector < 130) {
+		snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+		return pin_name;
+	} else {
+		return msm_pinctrl_pins[selector - 130];
+	}
+}
+
+static unsigned int apq8016_get_function_mux(unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].val;
+}
+
+struct msm_pinctrl_data apq8016_data = {
+	.pin_count = 140,
+	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+	.get_function_name = apq8016_get_function_name,
+	.get_function_mux = apq8016_get_function_mux,
+	.get_pin_name = apq8016_get_pin_name,
+};
+
diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
new file mode 100644
index 0000000000..9b7cf59a67
--- /dev/null
+++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TLMM driver for Qualcomm APQ8016, APQ8096
+ *
+ * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <dm/pinctrl.h>
+#include "pinctrl-snapdragon.h"
+
+struct msm_pinctrl_priv {
+	phys_addr_t base;
+	struct msm_pinctrl_data *data;
+};
+
+#define GPIO_CONFIG_OFFSET(x)         ((x) * 0x1000)
+#define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
+#define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
+#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
+#define TLMM_GPIO_ENABLE BIT(9)
+
+static const struct pinconf_param msm_conf_params[] = {
+	{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 3 },
+	{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
+};
+
+static int msm_get_functions_count(struct udevice *dev)
+{
+	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+
+	return priv->data->functions_count;
+}
+
+static int msm_get_pins_count(struct udevice *dev)
+{
+	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+
+	return priv->data->pin_count;
+}
+
+static const char *msm_get_function_name(struct udevice *dev,
+					 unsigned int selector)
+{
+	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+
+	return priv->data->get_function_name(dev, selector);
+}
+
+static int msm_pinctrl_probe(struct udevice *dev)
+{
+	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+
+	priv->base = devfdt_get_addr(dev);
+	priv->data = (struct msm_pinctrl_data *)dev->driver_data;
+
+	return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
+}
+
+static const char *msm_get_pin_name(struct udevice *dev, unsigned int selector)
+{
+	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+
+	return priv->data->get_pin_name(dev, selector);
+}
+
+static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
+			  unsigned int func_selector)
+{
+	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+
+	clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
+			TLMM_FUNC_SEL_MASK | TLMM_GPIO_ENABLE,
+			priv->data->get_function_mux(func_selector) << 2);
+	return 0;
+}
+
+static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
+			   unsigned int param, unsigned int argument)
+{
+	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+
+	switch (param) {
+	case PIN_CONFIG_DRIVE_STRENGTH:
+		clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
+				TLMM_DRV_STRENGTH_MASK, argument << 6);
+		break;
+	case PIN_CONFIG_BIAS_DISABLE:
+		clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
+			     TLMM_GPIO_PULL_MASK);
+		break;
+	default:
+		return 0;
+	}
+
+	return 0;
+}
+
+static struct pinctrl_ops msm_pinctrl_ops = {
+	.get_pins_count = msm_get_pins_count,
+	.get_pin_name = msm_get_pin_name,
+	.set_state = pinctrl_generic_set_state,
+	.pinmux_set = msm_pinmux_set,
+	.pinconf_num_params = ARRAY_SIZE(msm_conf_params),
+	.pinconf_params = msm_conf_params,
+	.pinconf_set = msm_pinconf_set,
+	.get_functions_count = msm_get_functions_count,
+	.get_function_name = msm_get_function_name,
+};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+	{ .compatible = "qcom,tlmm-msm8916", .data = (ulong)&apq8016_data },
+	{ .compatible = "qcom,tlmm-apq8016", .data = (ulong)&apq8016_data },
+	{ }
+};
+
+U_BOOT_DRIVER(pinctrl_snapdraon) = {
+	.name		= "pinctrl_msm",
+	.id		= UCLASS_PINCTRL,
+	.of_match	= msm_pinctrl_ids,
+	.priv_auto_alloc_size = sizeof(struct msm_pinctrl_priv),
+	.ops		= &msm_pinctrl_ops,
+	.probe		= msm_pinctrl_probe,
+};
diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
new file mode 100644
index 0000000000..6fd9971f17
--- /dev/null
+++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Qualcomm Pin control
+ *
+ * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
+ *
+ */
+#ifndef _PINCTRL_SNAPDRAGON_H
+#define _PINCTRL_SNAPDRAGON_H
+
+#include <common.h>
+
+struct msm_pinctrl_data {
+	int pin_count;
+	int functions_count;
+	const char *(*get_function_name)(struct udevice *dev,
+					 unsigned int selector);
+	unsigned int (*get_function_mux)(unsigned int selector);
+	const char *(*get_pin_name)(struct udevice *dev,
+				    unsigned int selector);
+};
+
+struct pinctrl_function {
+	const char *name;
+	int val;
+};
+
+extern struct msm_pinctrl_data apq8016_data;
+
+#endif
diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig
index e6114db2ce..4b3de64dd5 100644
--- a/configs/dragonboard410c_defconfig
+++ b/configs/dragonboard410c_defconfig
@@ -45,3 +45,8 @@ CONFIG_USB_ETHER_ASIX88179=y
 CONFIG_USB_ETHER_MCS7830=y
 CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_FULL=y
+CONFIG_PINCTRL_GENERIC=y
+CONFIG_PINMUX=y
+CONFIG_PINCONF=y
diff --git a/include/dt-bindings/pinctrl/pinctrl-snapdragon.h b/include/dt-bindings/pinctrl/pinctrl-snapdragon.h
new file mode 100644
index 0000000000..615affb6f2
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-snapdragon.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This header provides constants for Qualcomm Snapdragon pinctrl bindings.
+ *
+ * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
+ *
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_SNAPDRAGON_H
+#define _DT_BINDINGS_PINCTRL_SNAPDRAGON_H
+
+/* GPIO Drive Strength */
+#define DRIVE_STRENGTH_2MA        0
+#define DRIVE_STRENGTH_4MA        1
+#define DRIVE_STRENGTH_6MA        2
+#define DRIVE_STRENGTH_8MA        3
+#define DRIVE_STRENGTH_10MA       4
+#define DRIVE_STRENGTH_12MA       5
+#define DRIVE_STRENGTH_14MA       6
+#define DRIVE_STRENGTH_16MA       7
+
+#endif
-- 
2.17.0

[U-Boot] [PATCH v2 6/7] db410: added pinctrl node and serial bindings

[Ramon Fried]

Added TLMM pinctrl node for pin muxing & config.
Additionally, added a serial node for uart.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
---
 arch/arm/dts/dragonboard410c.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
index d9d5831f4f..182a865b0a 100644
--- a/arch/arm/dts/dragonboard410c.dts
+++ b/arch/arm/dts/dragonboard410c.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 
 #include "skeleton64.dtsi"
+#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
 
 / {
 	model = "Qualcomm Technologies, Inc. Dragonboard 410c";
@@ -38,6 +39,17 @@
 		ranges = <0x0 0x0 0x0 0xffffffff>;
 		compatible = "simple-bus";
 
+		pinctrl: qcom,tlmm at 1000000 {
+			compatible = "qcom,tlmm-apq8016";
+			reg = <0x1000000 0x400000>;
+
+			blsp1_uart: uart {
+				function = "blsp1_uart";
+				pins = "GPIO_4", "GPIO_5";
+				drive-strength = <DRIVE_STRENGTH_8MA>;
+				bias-disable;
+			};
+		};
 		clkc: qcom,gcc at 1800000 {
 			compatible = "qcom,gcc-apq8016";
 			reg = <0x1800000 0x80000>;
@@ -49,6 +61,8 @@
 			compatible = "qcom,msm-uartdm-v1.4";
 			reg = <0x78b0000 0x200>;
 			clock = <&clkc 4>;
+			pinctrl-names = "uart";
+			pinctrl-0 = <&blsp1_uart>;
 		};
 
 		soc_gpios: pinctrl at 1000000 {
-- 
2.17.0

[U-Boot] [PATCH v2 7/7] serial: serial_msm: added pinmux & config

[Ramon Fried]

Serial port configuration was missing from previous implementation.
It only worked because it was preconfigured by LK.
This patch configures the uart for 115200 8N1.
It also configures the pin mux for uart pins using DT bindings.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
---
 drivers/serial/serial_msm.c | 24 ++++++++++++++++++------
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index a4279accb4..c462394dbd 100644
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -16,6 +16,7 @@
 #include <watchdog.h>
 #include <asm/io.h>
 #include <linux/compiler.h>
+#include <dm/pinctrl.h>
 
 /* Serial registers - this driver works in uartdm mode*/
 
@@ -25,6 +26,9 @@
 #define UARTDM_RXFS             0x50 /* RX channel status register */
 #define UARTDM_RXFS_BUF_SHIFT   0x7  /* Number of bytes in the packing buffer */
 #define UARTDM_RXFS_BUF_MASK    0x7
+#define UARTDM_MR1				 0x00
+#define UARTDM_MR2				 0x04
+#define UARTDM_CSR				 0xA0
 
 #define UARTDM_SR                0xA4 /* Status register */
 #define UARTDM_SR_RX_READY       (1 << 0) /* Word is the receiver FIFO */
@@ -45,6 +49,10 @@
 #define UARTDM_TF               0x100 /* UART Transmit FIFO register */
 #define UARTDM_RF               0x140 /* UART Receive FIFO register */
 
+#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
+#define MSM_BOOT_UART_DM_8_N_1_MODE 0x34
+#define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10
+#define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -179,6 +187,14 @@ static int msm_uart_clk_init(struct udevice *dev)
 	return 0;
 }
 
+static void uart_dm_init(struct msm_serial_data *priv)
+{
+	writel(UART_DM_CLK_RX_TX_BIT_RATE, priv->base + UARTDM_CSR);
+	writel(0x0, priv->base + UARTDM_MR1);
+	writel(MSM_BOOT_UART_DM_8_N_1_MODE, priv->base + UARTDM_MR2);
+	writel(MSM_BOOT_UART_DM_CMD_RESET_RX, priv->base + UARTDM_CR);
+	writel(MSM_BOOT_UART_DM_CMD_RESET_TX, priv->base + UARTDM_CR);
+}
 static int msm_serial_probe(struct udevice *dev)
 {
 	int ret;
@@ -192,12 +208,8 @@ static int msm_serial_probe(struct udevice *dev)
 	if (ret)
 		return ret;
 
-	if (readl(priv->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN)
-		writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR);
-
-	writel(0, priv->base + UARTDM_IMR);
-	writel(UARTDM_CR_CMD_STALE_EVENT_DISABLE, priv->base + UARTDM_CR);
-	msm_serial_fetch(dev);
+	pinctrl_select_state(dev, "uart");
+	uart_dm_init(priv);
 
 	return 0;
 }
-- 
2.17.0

[U-Boot] [PATCH v2 5/7] mach-snapdragon: Introduce pinctrl driver

[Simon Glass]

On 16 May 2018 at 03:13, Ramon Fried <ramon.fried@gmail.com> wrote:
> This patch adds pinmux and pinctrl driver for TLMM
> subsystem in snapdragon chipsets.
> Currently, supporting only 8016, but implementation is
> generic and 8096 can be added easily.
>
> Driver is using the generic dt-bindings and doesn't
> introduce any new bindings (yet).
>
> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
> ---
> v2: * restructred the code to be more generic
>         * Reduced pin table size by snprintf on runtime as
>           suggested by Simon.
>
>  arch/arm/mach-snapdragon/Makefile             |   2 +
>  arch/arm/mach-snapdragon/pinctrl-apq8016.c    |  62 +++++++++
>  arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 128 ++++++++++++++++++
>  arch/arm/mach-snapdragon/pinctrl-snapdragon.h |  29 ++++
>  configs/dragonboard410c_defconfig             |   5 +
>  .../dt-bindings/pinctrl/pinctrl-snapdragon.h  |  22 +++
>  6 files changed, 248 insertions(+)
>  create mode 100644 arch/arm/mach-snapdragon/pinctrl-apq8016.c
>  create mode 100644 arch/arm/mach-snapdragon/pinctrl-snapdragon.c
>  create mode 100644 arch/arm/mach-snapdragon/pinctrl-snapdragon.h
>  create mode 100644 include/dt-bindings/pinctrl/pinctrl-snapdragon.h

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 2/7] serial: serial_msm: fail probe if settings clocks fails

[Simon Glass]

On 16 May 2018 at 03:13, Ramon Fried <ramon.fried@gmail.com> wrote:
> Failure to set the clocks will causes data abort exception when
> trying to write to AHB uart registers.
> This patch ensures that we don't touch these registers if clock
> setting failed.
>
> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
> ---
> v2: on failure, return actual return code from msm_uart_clk_init
>
>  drivers/serial/serial_msm.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 1/7] db820c: set clk node to be probed before relocation

[Simon Glass]

On 16 May 2018 at 03:13, Ramon Fried <ramon.fried@gmail.com> wrote:
> The clock and serial nodes are needed before relocation.
> This patch ensures that the msm-serial driver will probe
> and provide uart output before relocation.
>
> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
> ---
> v2: fixed alignment
>  arch/arm/dts/dragonboard820c-uboot.dtsi | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 3/7] serial: serial_msm: initialize uart only before relocation

[Simon Glass]

On 16 May 2018 at 03:13, Ramon Fried <ramon.fried@gmail.com> wrote:
> The uart is already initialized prior to relocation,
> reinitialization after relocation is unnecessary.
>
> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
> ---
> v2: removed extra parenthesis
>
>  drivers/serial/serial_msm.c | 4 ++++
>  1 file changed, 4 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [U-Boot, v2, 1/7] db820c: set clk node to be probed before relocation

[Tom Rini]

On Wed, May 16, 2018 at 12:13:36PM +0300, Ramon Fried wrote:

> The clock and serial nodes are needed before relocation.
> This patch ensures that the msm-serial driver will probe
> and provide uart output before relocation.
> 
> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, v2, 2/7] serial: serial_msm: fail probe if settings clocks fails

[Tom Rini]

On Wed, May 16, 2018 at 12:13:37PM +0300, Ramon Fried wrote:

> Failure to set the clocks will causes data abort exception when
> trying to write to AHB uart registers.
> This patch ensures that we don't touch these registers if clock
> setting failed.
> 
> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, v2, 3/7] serial: serial_msm: initialize uart only before relocation

[Tom Rini]

On Wed, May 16, 2018 at 12:13:38PM +0300, Ramon Fried wrote:

> The uart is already initialized prior to relocation,
> reinitialization after relocation is unnecessary.
> 
> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot,v2,4/7] mach-snapdragon: Fix UART clock flow

[Tom Rini]

On Wed, May 16, 2018 at 12:13:39PM +0300, Ramon Fried wrote:

> UART clock enabling flow was wrong.
> Changed the flow according to downstream implementation in LK.
> 
> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, v2, 5/7] mach-snapdragon: Introduce pinctrl driver

[Tom Rini]

On Wed, May 16, 2018 at 12:13:40PM +0300, Ramon Fried wrote:

> This patch adds pinmux and pinctrl driver for TLMM
> subsystem in snapdragon chipsets.
> Currently, supporting only 8016, but implementation is
> generic and 8096 can be added easily.
> 
> Driver is using the generic dt-bindings and doesn't
> introduce any new bindings (yet).
> 
> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, v2, 6/7] db410: added pinctrl node and serial bindings

[Tom Rini]

On Wed, May 16, 2018 at 12:13:41PM +0300, Ramon Fried wrote:

> Added TLMM pinctrl node for pin muxing & config.
> Additionally, added a serial node for uart.
> 
> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, v2, 7/7] serial: serial_msm: added pinmux & config

[Tom Rini]

On Wed, May 16, 2018 at 12:13:42PM +0300, Ramon Fried wrote:

> Serial port configuration was missing from previous implementation.
> It only worked because it was preconfigured by LK.
> This patch configures the uart for 115200 8N1.
> It also configures the pin mux for uart pins using DT bindings.
> 
> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot,v2,4/7] mach-snapdragon: Fix UART clock flow

[Jorge Ramirez-Ortiz]

On 05/28/2018 09:12 PM, Tom Rini wrote:
> On Wed, May 16, 2018 at 12:13:39PM +0300, Ramon Fried wrote:
>
>> UART clock enabling flow was wrong.
>> Changed the flow according to downstream implementation in LK.
>>
>> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
> Applied to u-boot/master, thanks!
>

Ramon, did you re-test this one on the 820 as we discussed?
Sorry Tom, when I tested this on Friday it broke my 820 (I should have 
reported it to the ML).

I think it introduces a regression but I'll let Ramon to confirm.

[U-Boot] [U-Boot,v2,4/7] mach-snapdragon: Fix UART clock flow

[Ramon Fried]

On Mon, May 28, 2018 at 10:19 PM, Jorge Ramirez-Ortiz
<jramirez@baylibre.com> wrote:
> On 05/28/2018 09:12 PM, Tom Rini wrote:
>>
>> On Wed, May 16, 2018 at 12:13:39PM +0300, Ramon Fried wrote:
>>
>>> UART clock enabling flow was wrong.
>>> Changed the flow according to downstream implementation in LK.
>>>
>>> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
>>
>> Applied to u-boot/master, thanks!
>>
>
> Ramon, did you re-test this one on the 820 as we discussed?
> Sorry Tom, when I tested this on Friday it broke my 820 (I should have
> reported it to the ML).
>
> I think it introduces a regression but I'll let Ramon to confirm.
Hi.
It's funny, I'm debugging it now. don't have any conclusions yet but I
was under the assumption that it won't get merged as it was
missing Reviewed-by.
Let me get back to you on these one in couple of hours.
Thanks,
Ramon.
>

[U-Boot] [U-Boot,v2,4/7] mach-snapdragon: Fix UART clock flow

[Tom Rini]

On Mon, May 28, 2018 at 10:24:36PM +0300, Ramon Fried wrote:
> On Mon, May 28, 2018 at 10:19 PM, Jorge Ramirez-Ortiz
> <jramirez@baylibre.com> wrote:
> > On 05/28/2018 09:12 PM, Tom Rini wrote:
> >>
> >> On Wed, May 16, 2018 at 12:13:39PM +0300, Ramon Fried wrote:
> >>
> >>> UART clock enabling flow was wrong.
> >>> Changed the flow according to downstream implementation in LK.
> >>>
> >>> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
> >>
> >> Applied to u-boot/master, thanks!
> >>
> >
> > Ramon, did you re-test this one on the 820 as we discussed?
> > Sorry Tom, when I tested this on Friday it broke my 820 (I should have
> > reported it to the ML).
> >
> > I think it introduces a regression but I'll let Ramon to confirm.
> Hi.
> It's funny, I'm debugging it now. don't have any conclusions yet but I
> was under the assumption that it won't get merged as it was
> missing Reviewed-by.
> Let me get back to you on these one in couple of hours.

Yeah, sorry guys, I didn't see anything in public about problems so I
fixed up the one new warning.  Please let me know if you need me to
revert these or if it's an "easy" fix, thanks!

-- 
Tom
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[U-Boot] [U-Boot,v2,4/7] mach-snapdragon: Fix UART clock flow

[Ramon Fried]

On Mon, May 28, 2018 at 10:26 PM, Tom Rini <trini@konsulko.com> wrote:
> On Mon, May 28, 2018 at 10:24:36PM +0300, Ramon Fried wrote:
>> On Mon, May 28, 2018 at 10:19 PM, Jorge Ramirez-Ortiz
>> <jramirez@baylibre.com> wrote:
>> > On 05/28/2018 09:12 PM, Tom Rini wrote:
>> >>
>> >> On Wed, May 16, 2018 at 12:13:39PM +0300, Ramon Fried wrote:
>> >>
>> >>> UART clock enabling flow was wrong.
>> >>> Changed the flow according to downstream implementation in LK.
>> >>>
>> >>> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
>> >>
>> >> Applied to u-boot/master, thanks!
>> >>
>> >
>> > Ramon, did you re-test this one on the 820 as we discussed?
>> > Sorry Tom, when I tested this on Friday it broke my 820 (I should have
>> > reported it to the ML).
>> >
>> > I think it introduces a regression but I'll let Ramon to confirm.
>> Hi.
>> It's funny, I'm debugging it now. don't have any conclusions yet but I
>> was under the assumption that it won't get merged as it was
>> missing Reviewed-by.
>> Let me get back to you on these one in couple of hours.
>
> Yeah, sorry guys, I didn't see anything in public about problems so I
> fixed up the one new warning.  Please let me know if you need me to
> revert these or if it's an "easy" fix, thanks!
Sure.
I'll keep you posted. but without any doubt, the following patch is
necessary to make it work:
https://patchwork.ozlabs.org/patch/921407/
Can you please merge it as well ?
>
> --
> Tom

[U-Boot] [U-Boot,v2,4/7] mach-snapdragon: Fix UART clock flow

[Tom Rini]

On Mon, May 28, 2018 at 10:28:51PM +0300, Ramon Fried wrote:
> On Mon, May 28, 2018 at 10:26 PM, Tom Rini <trini@konsulko.com> wrote:
> > On Mon, May 28, 2018 at 10:24:36PM +0300, Ramon Fried wrote:
> >> On Mon, May 28, 2018 at 10:19 PM, Jorge Ramirez-Ortiz
> >> <jramirez@baylibre.com> wrote:
> >> > On 05/28/2018 09:12 PM, Tom Rini wrote:
> >> >>
> >> >> On Wed, May 16, 2018 at 12:13:39PM +0300, Ramon Fried wrote:
> >> >>
> >> >>> UART clock enabling flow was wrong.
> >> >>> Changed the flow according to downstream implementation in LK.
> >> >>>
> >> >>> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
> >> >>
> >> >> Applied to u-boot/master, thanks!
> >> >>
> >> >
> >> > Ramon, did you re-test this one on the 820 as we discussed?
> >> > Sorry Tom, when I tested this on Friday it broke my 820 (I should have
> >> > reported it to the ML).
> >> >
> >> > I think it introduces a regression but I'll let Ramon to confirm.
> >> Hi.
> >> It's funny, I'm debugging it now. don't have any conclusions yet but I
> >> was under the assumption that it won't get merged as it was
> >> missing Reviewed-by.
> >> Let me get back to you on these one in couple of hours.
> >
> > Yeah, sorry guys, I didn't see anything in public about problems so I
> > fixed up the one new warning.  Please let me know if you need me to
> > revert these or if it's an "easy" fix, thanks!
> Sure.
> I'll keep you posted. but without any doubt, the following patch is
> necessary to make it work:
> https://patchwork.ozlabs.org/patch/921407/
> Can you please merge it as well ?

0x0800 is still pretty small.  We're talking about (and oops, I think I
need to for v2018.07..) bump it to 0x2000 for all TI platforms.  Can you
v2 doing that size if it works for you (it ought...) and as a default
VAL if ARCH_SNAPDRAGON ?  Thanks!

-- 
Tom
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[U-Boot] [U-Boot,v2,4/7] mach-snapdragon: Fix UART clock flow

[Ramon Fried]

On Mon, May 28, 2018 at 10:35 PM, Tom Rini <trini@konsulko.com> wrote:
> On Mon, May 28, 2018 at 10:28:51PM +0300, Ramon Fried wrote:
>> On Mon, May 28, 2018 at 10:26 PM, Tom Rini <trini@konsulko.com> wrote:
>> > On Mon, May 28, 2018 at 10:24:36PM +0300, Ramon Fried wrote:
>> >> On Mon, May 28, 2018 at 10:19 PM, Jorge Ramirez-Ortiz
>> >> <jramirez@baylibre.com> wrote:
>> >> > On 05/28/2018 09:12 PM, Tom Rini wrote:
>> >> >>
>> >> >> On Wed, May 16, 2018 at 12:13:39PM +0300, Ramon Fried wrote:
>> >> >>
>> >> >>> UART clock enabling flow was wrong.
>> >> >>> Changed the flow according to downstream implementation in LK.
>> >> >>>
>> >> >>> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
>> >> >>
>> >> >> Applied to u-boot/master, thanks!
>> >> >>
>> >> >
>> >> > Ramon, did you re-test this one on the 820 as we discussed?
>> >> > Sorry Tom, when I tested this on Friday it broke my 820 (I should have
>> >> > reported it to the ML).
>> >> >
>> >> > I think it introduces a regression but I'll let Ramon to confirm.
>> >> Hi.
>> >> It's funny, I'm debugging it now. don't have any conclusions yet but I
>> >> was under the assumption that it won't get merged as it was
>> >> missing Reviewed-by.
>> >> Let me get back to you on these one in couple of hours.
>> >
>> > Yeah, sorry guys, I didn't see anything in public about problems so I
>> > fixed up the one new warning.  Please let me know if you need me to
>> > revert these or if it's an "easy" fix, thanks!
>> Sure.
>> I'll keep you posted. but without any doubt, the following patch is
>> necessary to make it work:
>> https://patchwork.ozlabs.org/patch/921407/
>> Can you please merge it as well ?
>
> 0x0800 is still pretty small.  We're talking about (and oops, I think I
> need to for v2018.07..) bump it to 0x2000 for all TI platforms.  Can you
> v2 doing that size if it works for you (it ought...) and as a default
> VAL if ARCH_SNAPDRAGON ?  Thanks!
Sure. I'll test and resend.
>
> --
> Tom

[U-Boot] [U-Boot,v2,4/7] mach-snapdragon: Fix UART clock flow

[Ramon Fried]

On Mon, May 28, 2018 at 10:24 PM, Ramon Fried <ramon.fried@gmail.com> wrote:
> On Mon, May 28, 2018 at 10:19 PM, Jorge Ramirez-Ortiz
> <jramirez@baylibre.com> wrote:
>> On 05/28/2018 09:12 PM, Tom Rini wrote:
>>>
>>> On Wed, May 16, 2018 at 12:13:39PM +0300, Ramon Fried wrote:
>>>
>>>> UART clock enabling flow was wrong.
>>>> Changed the flow according to downstream implementation in LK.
>>>>
>>>> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
>>>
>>> Applied to u-boot/master, thanks!
>>>
>>
>> Ramon, did you re-test this one on the 820 as we discussed?
>> Sorry Tom, when I tested this on Friday it broke my 820 (I should have
>> reported it to the ML).
>>
>> I think it introduces a regression but I'll let Ramon to confirm.
> Hi.
> It's funny, I'm debugging it now. don't have any conclusions yet but I
> was under the assumption that it won't get merged as it was
> missing Reviewed-by.
> Let me get back to you on these one in couple of hours.
> Thanks,
> Ramon.
>>
I just toasted my 820 board...:(
I can only get a replacement by Thursday.
I can't find any explanation why the 820 should be affected, as the
clock configuration for it is empty.
and it's pre-initalized by the uart.
Jorge, you previously tested from my branch, care to test from master
to see if it's working ?
Thanks.
Ramon.

[U-Boot] [U-Boot,v2,4/7] mach-snapdragon: Fix UART clock flow

[Jorge Ramirez-Ortiz]

On 05/28/2018 09:48 PM, Ramon Fried wrote:
> On Mon, May 28, 2018 at 10:24 PM, Ramon Fried <ramon.fried@gmail.com> wrote:
>> On Mon, May 28, 2018 at 10:19 PM, Jorge Ramirez-Ortiz
>> <jramirez@baylibre.com> wrote:
>>> On 05/28/2018 09:12 PM, Tom Rini wrote:
>>>> On Wed, May 16, 2018 at 12:13:39PM +0300, Ramon Fried wrote:
>>>>
>>>>> UART clock enabling flow was wrong.
>>>>> Changed the flow according to downstream implementation in LK.
>>>>>
>>>>> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
>>>> Applied to u-boot/master, thanks!
>>>>
>>> Ramon, did you re-test this one on the 820 as we discussed?
>>> Sorry Tom, when I tested this on Friday it broke my 820 (I should have
>>> reported it to the ML).
>>>
>>> I think it introduces a regression but I'll let Ramon to confirm.
>> Hi.
>> It's funny, I'm debugging it now. don't have any conclusions yet but I
>> was under the assumption that it won't get merged as it was
>> missing Reviewed-by.
>> Let me get back to you on these one in couple of hours.
>> Thanks,
>> Ramon.
> I just toasted my 820 board...:(
> I can only get a replacement by Thursday.
> I can't find any explanation why the 820 should be affected, as the
> clock configuration for it is empty.
> and it's pre-initalized by the uart.
> Jorge, you previously tested from my branch, care to test from master
> to see if it's working ?

so just pull your master branch again and retest?


> Thanks.
> Ramon.

[U-Boot] [U-Boot,v2,4/7] mach-snapdragon: Fix UART clock flow

[Ramon Fried]

On Mon, May 28, 2018 at 10:59 PM, Jorge Ramirez-Ortiz
<jramirez@baylibre.com> wrote:
> On 05/28/2018 09:48 PM, Ramon Fried wrote:
>>
>> On Mon, May 28, 2018 at 10:24 PM, Ramon Fried <ramon.fried@gmail.com>
>> wrote:
>>>
>>> On Mon, May 28, 2018 at 10:19 PM, Jorge Ramirez-Ortiz
>>> <jramirez@baylibre.com> wrote:
>>>>
>>>> On 05/28/2018 09:12 PM, Tom Rini wrote:
>>>>>
>>>>> On Wed, May 16, 2018 at 12:13:39PM +0300, Ramon Fried wrote:
>>>>>
>>>>>> UART clock enabling flow was wrong.
>>>>>> Changed the flow according to downstream implementation in LK.
>>>>>>
>>>>>> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
>>>>>
>>>>> Applied to u-boot/master, thanks!
>>>>>
>>>> Ramon, did you re-test this one on the 820 as we discussed?
>>>> Sorry Tom, when I tested this on Friday it broke my 820 (I should have
>>>> reported it to the ML).
>>>>
>>>> I think it introduces a regression but I'll let Ramon to confirm.
>>>
>>> Hi.
>>> It's funny, I'm debugging it now. don't have any conclusions yet but I
>>> was under the assumption that it won't get merged as it was
>>> missing Reviewed-by.
>>> Let me get back to you on these one in couple of hours.
>>> Thanks,
>>> Ramon.
>>
>> I just toasted my 820 board...:(
>> I can only get a replacement by Thursday.
>> I can't find any explanation why the 820 should be affected, as the
>> clock configuration for it is empty.
>> and it's pre-initalized by the uart.
>> Jorge, you previously tested from my branch, care to test from master
>> to see if it's working ?
>
>
> so just pull your master branch again and retest?
not mine. upstream master.
>
>
>> Thanks.
>> Ramon.
>
>

[U-Boot] [U-Boot,v2,4/7] mach-snapdragon: Fix UART clock flow

[Jorge Ramirez-Ortiz]

On 05/28/2018 10:01 PM, Ramon Fried wrote:
> On Mon, May 28, 2018 at 10:59 PM, Jorge Ramirez-Ortiz
> <jramirez@baylibre.com> wrote:
>> On 05/28/2018 09:48 PM, Ramon Fried wrote:
>>> On Mon, May 28, 2018 at 10:24 PM, Ramon Fried <ramon.fried@gmail.com>
>>> wrote:
>>>> On Mon, May 28, 2018 at 10:19 PM, Jorge Ramirez-Ortiz
>>>> <jramirez@baylibre.com> wrote:
>>>>> On 05/28/2018 09:12 PM, Tom Rini wrote:
>>>>>> On Wed, May 16, 2018 at 12:13:39PM +0300, Ramon Fried wrote:
>>>>>>
>>>>>>> UART clock enabling flow was wrong.
>>>>>>> Changed the flow according to downstream implementation in LK.
>>>>>>>
>>>>>>> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
>>>>>> Applied to u-boot/master, thanks!
>>>>>>
>>>>> Ramon, did you re-test this one on the 820 as we discussed?
>>>>> Sorry Tom, when I tested this on Friday it broke my 820 (I should have
>>>>> reported it to the ML).
>>>>>
>>>>> I think it introduces a regression but I'll let Ramon to confirm.
>>>> Hi.
>>>> It's funny, I'm debugging it now. don't have any conclusions yet but I
>>>> was under the assumption that it won't get merged as it was
>>>> missing Reviewed-by.
>>>> Let me get back to you on these one in couple of hours.
>>>> Thanks,
>>>> Ramon.
>>> I just toasted my 820 board...:(
>>> I can only get a replacement by Thursday.
>>> I can't find any explanation why the 820 should be affected, as the
>>> clock configuration for it is empty.
>>> and it's pre-initalized by the uart.
>>> Jorge, you previously tested from my branch, care to test from master
>>> to see if it's working ?
>>
>> so just pull your master branch again and retest?
> not mine. upstream master.

2 days ago ffada23 db820c: set clk node to be probed before 
relocation          Ramon Fr..[Tom Rini]
2 days ago 0ed34aa Remove CONFIG_MVGBE from 
config_whitelist.txt                Chris Pa..[Tom Rini]
2 days ago 5ce9aca PCI: Document 
pciauto_region_allocate()                      Tuomas T..[Tom Rini]
2 days ago d71975a PCI: autoconfig: Don't allocate 64-bit addresses to 
32-bit.. Tuomas T..[Tom Rini]
2 days ago ed12a89 PCI: Add newlines to debug prints in 
pci_auto_common.c       Tuomas T..[Tom Rini]

the one on top is the last commit that works on the 820 from the current 
uboot master branch.

>>
>>> Thanks.
>>> Ramon.
>>

[U-Boot] [U-Boot,v2,4/7] mach-snapdragon: Fix UART clock flow

[Ramon Fried]

On Mon, May 28, 2018 at 11:07 PM, Jorge Ramirez-Ortiz
<jramirez@baylibre.com> wrote:
> On 05/28/2018 10:01 PM, Ramon Fried wrote:
>>
>> On Mon, May 28, 2018 at 10:59 PM, Jorge Ramirez-Ortiz
>> <jramirez@baylibre.com> wrote:
>>>
>>> On 05/28/2018 09:48 PM, Ramon Fried wrote:
>>>>
>>>> On Mon, May 28, 2018 at 10:24 PM, Ramon Fried <ramon.fried@gmail.com>
>>>> wrote:
>>>>>
>>>>> On Mon, May 28, 2018 at 10:19 PM, Jorge Ramirez-Ortiz
>>>>> <jramirez@baylibre.com> wrote:
>>>>>>
>>>>>> On 05/28/2018 09:12 PM, Tom Rini wrote:
>>>>>>>
>>>>>>> On Wed, May 16, 2018 at 12:13:39PM +0300, Ramon Fried wrote:
>>>>>>>
>>>>>>>> UART clock enabling flow was wrong.
>>>>>>>> Changed the flow according to downstream implementation in LK.
>>>>>>>>
>>>>>>>> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
>>>>>>>
>>>>>>> Applied to u-boot/master, thanks!
>>>>>>>
>>>>>> Ramon, did you re-test this one on the 820 as we discussed?
>>>>>> Sorry Tom, when I tested this on Friday it broke my 820 (I should have
>>>>>> reported it to the ML).
>>>>>>
>>>>>> I think it introduces a regression but I'll let Ramon to confirm.
>>>>>
>>>>> Hi.
>>>>> It's funny, I'm debugging it now. don't have any conclusions yet but I
>>>>> was under the assumption that it won't get merged as it was
>>>>> missing Reviewed-by.
>>>>> Let me get back to you on these one in couple of hours.
>>>>> Thanks,
>>>>> Ramon.
>>>>
>>>> I just toasted my 820 board...:(
>>>> I can only get a replacement by Thursday.
>>>> I can't find any explanation why the 820 should be affected, as the
>>>> clock configuration for it is empty.
>>>> and it's pre-initalized by the uart.
>>>> Jorge, you previously tested from my branch, care to test from master
>>>> to see if it's working ?
>>>
>>>
>>> so just pull your master branch again and retest?
>>
>> not mine. upstream master.
>
>
> 2 days ago ffada23 db820c: set clk node to be probed before relocation
> Ramon Fr..[Tom Rini]
> 2 days ago 0ed34aa Remove CONFIG_MVGBE from config_whitelist.txt
> Chris Pa..[Tom Rini]
> 2 days ago 5ce9aca PCI: Document pciauto_region_allocate()
> Tuomas T..[Tom Rini]
> 2 days ago d71975a PCI: autoconfig: Don't allocate 64-bit addresses to
> 32-bit.. Tuomas T..[Tom Rini]
> 2 days ago ed12a89 PCI: Add newlines to debug prints in pci_auto_common.c
> Tuomas T..[Tom Rini]
>
> the one on top is the last commit that works on the 820 from the current
> uboot master branch.
Thanks Jorge.
I see where the problem is. there's no clock defintions in 820 device tree,
so msm_uart_clk_init() fails. I'll add dummy definitions meanwhile and
after I'll finish
with 410, I'll work on the correct clock values for 820. nevertheless
the UART will work as
LK already initalizes it with the right values.
expect a fix patch shortly.

Thanks,
Ramon.
>
>>>
>>>> Thanks.
>>>> Ramon.
>>>
>>>
>

[U-Boot] [U-Boot,v2,4/7] mach-snapdragon: Fix UART clock flow

[Ramon Fried]

On Mon, May 28, 2018 at 11:14 PM, Ramon Fried <ramon.fried@gmail.com> wrote:
> On Mon, May 28, 2018 at 11:07 PM, Jorge Ramirez-Ortiz
> <jramirez@baylibre.com> wrote:
>> On 05/28/2018 10:01 PM, Ramon Fried wrote:
>>>
>>> On Mon, May 28, 2018 at 10:59 PM, Jorge Ramirez-Ortiz
>>> <jramirez@baylibre.com> wrote:
>>>>
>>>> On 05/28/2018 09:48 PM, Ramon Fried wrote:
>>>>>
>>>>> On Mon, May 28, 2018 at 10:24 PM, Ramon Fried <ramon.fried@gmail.com>
>>>>> wrote:
>>>>>>
>>>>>> On Mon, May 28, 2018 at 10:19 PM, Jorge Ramirez-Ortiz
>>>>>> <jramirez@baylibre.com> wrote:
>>>>>>>
>>>>>>> On 05/28/2018 09:12 PM, Tom Rini wrote:
>>>>>>>>
>>>>>>>> On Wed, May 16, 2018 at 12:13:39PM +0300, Ramon Fried wrote:
>>>>>>>>
>>>>>>>>> UART clock enabling flow was wrong.
>>>>>>>>> Changed the flow according to downstream implementation in LK.
>>>>>>>>>
>>>>>>>>> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
>>>>>>>>
>>>>>>>> Applied to u-boot/master, thanks!
>>>>>>>>
>>>>>>> Ramon, did you re-test this one on the 820 as we discussed?
>>>>>>> Sorry Tom, when I tested this on Friday it broke my 820 (I should have
>>>>>>> reported it to the ML).
>>>>>>>
>>>>>>> I think it introduces a regression but I'll let Ramon to confirm.
>>>>>>
>>>>>> Hi.
>>>>>> It's funny, I'm debugging it now. don't have any conclusions yet but I
>>>>>> was under the assumption that it won't get merged as it was
>>>>>> missing Reviewed-by.
>>>>>> Let me get back to you on these one in couple of hours.
>>>>>> Thanks,
>>>>>> Ramon.
>>>>>
>>>>> I just toasted my 820 board...:(
>>>>> I can only get a replacement by Thursday.
>>>>> I can't find any explanation why the 820 should be affected, as the
>>>>> clock configuration for it is empty.
>>>>> and it's pre-initalized by the uart.
>>>>> Jorge, you previously tested from my branch, care to test from master
>>>>> to see if it's working ?
>>>>
>>>>
>>>> so just pull your master branch again and retest?
>>>
>>> not mine. upstream master.
>>
>>
>> 2 days ago ffada23 db820c: set clk node to be probed before relocation
>> Ramon Fr..[Tom Rini]
>> 2 days ago 0ed34aa Remove CONFIG_MVGBE from config_whitelist.txt
>> Chris Pa..[Tom Rini]
>> 2 days ago 5ce9aca PCI: Document pciauto_region_allocate()
>> Tuomas T..[Tom Rini]
>> 2 days ago d71975a PCI: autoconfig: Don't allocate 64-bit addresses to
>> 32-bit.. Tuomas T..[Tom Rini]
>> 2 days ago ed12a89 PCI: Add newlines to debug prints in pci_auto_common.c
>> Tuomas T..[Tom Rini]
>>
>> the one on top is the last commit that works on the 820 from the current
>> uboot master branch.
> Thanks Jorge.
> I see where the problem is. there's no clock defintions in 820 device tree,
> so msm_uart_clk_init() fails. I'll add dummy definitions meanwhile and
> after I'll finish
> with 410, I'll work on the correct clock values for 820. nevertheless
> the UART will work as
> LK already initalizes it with the right values.
> expect a fix patch shortly.
>
> Thanks,
> Ramon.
Jorge, I just sent you a fix. can you test it and if it works I'll
push it upstream.
Thanks ! and sorry for the trouble...
>>
>>>>
>>>>> Thanks.
>>>>> Ramon.
>>>>
>>>>
>>

[U-Boot] [U-Boot,v2,4/7] mach-snapdragon: Fix UART clock flow

[Jorge Ramirez-Ortiz]

On 05/28/2018 10:25 PM, Ramon Fried wrote:
> On Mon, May 28, 2018 at 11:14 PM, Ramon Fried <ramon.fried@gmail.com> wrote:
>> On Mon, May 28, 2018 at 11:07 PM, Jorge Ramirez-Ortiz
>> <jramirez@baylibre.com> wrote:
>>> On 05/28/2018 10:01 PM, Ramon Fried wrote:
>>>> On Mon, May 28, 2018 at 10:59 PM, Jorge Ramirez-Ortiz
>>>> <jramirez@baylibre.com> wrote:
>>>>> On 05/28/2018 09:48 PM, Ramon Fried wrote:
>>>>>> On Mon, May 28, 2018 at 10:24 PM, Ramon Fried <ramon.fried@gmail.com>
>>>>>> wrote:
>>>>>>> On Mon, May 28, 2018 at 10:19 PM, Jorge Ramirez-Ortiz
>>>>>>> <jramirez@baylibre.com> wrote:
>>>>>>>> On 05/28/2018 09:12 PM, Tom Rini wrote:
>>>>>>>>> On Wed, May 16, 2018 at 12:13:39PM +0300, Ramon Fried wrote:
>>>>>>>>>
>>>>>>>>>> UART clock enabling flow was wrong.
>>>>>>>>>> Changed the flow according to downstream implementation in LK.
>>>>>>>>>>
>>>>>>>>>> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
>>>>>>>>> Applied to u-boot/master, thanks!
>>>>>>>>>
>>>>>>>> Ramon, did you re-test this one on the 820 as we discussed?
>>>>>>>> Sorry Tom, when I tested this on Friday it broke my 820 (I should have
>>>>>>>> reported it to the ML).
>>>>>>>>
>>>>>>>> I think it introduces a regression but I'll let Ramon to confirm.
>>>>>>> Hi.
>>>>>>> It's funny, I'm debugging it now. don't have any conclusions yet but I
>>>>>>> was under the assumption that it won't get merged as it was
>>>>>>> missing Reviewed-by.
>>>>>>> Let me get back to you on these one in couple of hours.
>>>>>>> Thanks,
>>>>>>> Ramon.
>>>>>> I just toasted my 820 board...:(
>>>>>> I can only get a replacement by Thursday.
>>>>>> I can't find any explanation why the 820 should be affected, as the
>>>>>> clock configuration for it is empty.
>>>>>> and it's pre-initalized by the uart.
>>>>>> Jorge, you previously tested from my branch, care to test from master
>>>>>> to see if it's working ?
>>>>>
>>>>> so just pull your master branch again and retest?
>>>> not mine. upstream master.
>>>
>>> 2 days ago ffada23 db820c: set clk node to be probed before relocation
>>> Ramon Fr..[Tom Rini]
>>> 2 days ago 0ed34aa Remove CONFIG_MVGBE from config_whitelist.txt
>>> Chris Pa..[Tom Rini]
>>> 2 days ago 5ce9aca PCI: Document pciauto_region_allocate()
>>> Tuomas T..[Tom Rini]
>>> 2 days ago d71975a PCI: autoconfig: Don't allocate 64-bit addresses to
>>> 32-bit.. Tuomas T..[Tom Rini]
>>> 2 days ago ed12a89 PCI: Add newlines to debug prints in pci_auto_common.c
>>> Tuomas T..[Tom Rini]
>>>
>>> the one on top is the last commit that works on the 820 from the current
>>> uboot master branch.
>> Thanks Jorge.
>> I see where the problem is. there's no clock defintions in 820 device tree,
>> so msm_uart_clk_init() fails. I'll add dummy definitions meanwhile and
>> after I'll finish
>> with 410, I'll work on the correct clock values for 820. nevertheless
>> the UART will work as
>> LK already initalizes it with the right values.
>> expect a fix patch shortly.
>>
>> Thanks,
>> Ramon.
> Jorge, I just sent you a fix. can you test it and if it works I'll
> push it upstream.

yes I can see the console now so that fix is good.

however there must be some other regression lurking because the system 
wont boot a kernel from the SD card

[U-Boot] [U-Boot,v2,4/7] mach-snapdragon: Fix UART clock flow

[Jorge Ramirez-Ortiz]

On 05/28/2018 11:07 PM, Jorge Ramirez-Ortiz wrote:
>> Jorge, I just sent you a fix. can you test it and if it works I'll
>> push it upstream.
>
> yes I can see the console now so that fix is good.
>
> however there must be some other regression lurking because the system 
> wont boot a kernel from the SD card 

sorry forgot the trace.
I think you might have fixed this one as well Ramon (I remember you 
mentioning it in some other thread?)

U-Boot 2018.05-00430-g5ce9aca (May 28 2018 - 23:09:02) [15/592]
Qualcomm-DragonBoard 820C

DRAM:  3 GiB
PSCI:  v1.0
MMC:   sdhci at 74a4900: 0
In:    serial at 75b0000
Out:   serial at 75b0000
Err:   serial at 75b0000
Net:   Net Initialization Skipped
No ethernet found.
Hit any key to stop autoboot:  0
Card did not respond to voltage select! <---------------

[U-Boot] [U-Boot,v2,4/7] mach-snapdragon: Fix UART clock flow

[Ramon Fried]

On Tue, May 29, 2018, 12:11 AM Jorge Ramirez-Ortiz
<jramirez@baylibre.com> wrote:
>
> On 05/28/2018 11:07 PM, Jorge Ramirez-Ortiz wrote:
>
> Jorge, I just sent you a fix. can you test it and if it works I'll
> push it upstream.
>
>
> yes I can see the console now so that fix is good.
>
> however there must be some other regression lurking because the system wont boot a kernel from the SD card
>
Sorry, I don't recall seeing this ever, perhaps the regression is
caused by another patch ?
are you sure it's from the latest uart fixes ? can you bisect ?
Thanks,
Ramon.
>
> sorry forgot the trace.
> I think you might have fixed this one as well Ramon (I remember you mentioning it in some other thread?)
>
> U-Boot 2018.05-00430-g5ce9aca (May 28 2018 - 23:09:02)                                                                                                                                       [15/592]
> Qualcomm-DragonBoard 820C
>
> DRAM:  3 GiB
> PSCI:  v1.0
> MMC:   sdhci at 74a4900: 0
> In:    serial at 75b0000
> Out:   serial at 75b0000
> Err:   serial at 75b0000
> Net:   Net Initialization Skipped
> No ethernet found.
> Hit any key to stop autoboot:  0
> Card did not respond to voltage select! <---------------
>