* [U-Boot] [PATCH 01/25] ARM: dts: sun4i: Sync A10 MMC nodes from Linux
2018-07-16 8:19 [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Jagan Teki
@ 2018-07-16 8:19 ` Jagan Teki
2018-07-16 9:30 ` Maxime Ripard
2018-07-16 8:19 ` [U-Boot] [PATCH 02/25] ARM: dts: sun4i: Sync A10 board dts mmc0 node " Jagan Teki
` (24 subsequent siblings)
25 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 8:19 UTC (permalink / raw)
To: u-boot
DM_MMC need MMC nodes in dtsi need to update and
follow Linux notation to support dm driven mmc driver.
So sync mmc nodes for sun4i-a10 from Linux. This will
also useful for CLK driver handling in future.
Last linux commit for sun4i-a10.dtsi:
commit 590b0c0cfc6162aeebbf43eaafb9753b56df1532
Author: Pascal Roeleven <dev@pascalroeleven.nl>
Date: Fri Apr 20 12:21:12 2018 +0200
ARM: dts: sun4i: Fix incorrect clocks for displays
Last linux commit for sun4i-a10-ccu.h:
commit 4328a2186e5120cfd34c4f04c6e4b7e74fb8b7b4
Author: Jonathan Liu <net147@gmail.com>
Date: Tue Oct 17 20:18:03 2017 +0800
clk: sunxi-ng: sun4i: Export video PLLs
Cc: Adam Sampson <ats@offog.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/dts/sun4i-a10.dtsi | 112 ++++--------
include/dt-bindings/clock/sun4i-a10-ccu.h | 202 ++++++++++++++++++++++
2 files changed, 232 insertions(+), 82 deletions(-)
create mode 100644 include/dt-bindings/clock/sun4i-a10-ccu.h
diff --git a/arch/arm/dts/sun4i-a10.dtsi b/arch/arm/dts/sun4i-a10.dtsi
index 7e7dfc2b43..b58252934b 100644
--- a/arch/arm/dts/sun4i-a10.dtsi
+++ b/arch/arm/dts/sun4i-a10.dtsi
@@ -47,6 +47,7 @@
#include <dt-bindings/clock/sun4i-a10-pll2.h>
#include <dt-bindings/dma/sun4i-a10.h>
+#include <dt-bindings/clock/sun4i-a10-ccu.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
@@ -420,46 +421,6 @@
clock-output-names = "ms";
};
- mmc0_clk: clk at 01c20088 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c20088 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc0",
- "mmc0_output",
- "mmc0_sample";
- };
-
- mmc1_clk: clk at 01c2008c {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c2008c 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc1",
- "mmc1_output",
- "mmc1_sample";
- };
-
- mmc2_clk: clk at 01c20090 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c20090 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc2",
- "mmc2_output",
- "mmc2_sample";
- };
-
- mmc3_clk: clk at 01c20094 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c20094 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc3",
- "mmc3_output",
- "mmc3_sample";
- };
-
ts_clk: clk at 01c20098 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
@@ -779,68 +740,46 @@
#size-cells = <0>;
};
- mmc0: mmc at 01c0f000 {
+ mmc0: mmc at 1c0f000 {
compatible = "allwinner,sun4i-a10-mmc";
reg = <0x01c0f000 0x1000>;
- clocks = <&ahb_gates 8>,
- <&mmc0_clk 0>,
- <&mmc0_clk 1>,
- <&mmc0_clk 2>;
- clock-names = "ahb",
- "mmc",
- "output",
- "sample";
+ clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
+ clock-names = "ahb", "mmc";
interrupts = <32>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- mmc1: mmc at 01c10000 {
+ mmc1: mmc at 1c10000 {
compatible = "allwinner,sun4i-a10-mmc";
reg = <0x01c10000 0x1000>;
- clocks = <&ahb_gates 9>,
- <&mmc1_clk 0>,
- <&mmc1_clk 1>,
- <&mmc1_clk 2>;
- clock-names = "ahb",
- "mmc",
- "output",
- "sample";
+ clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
+ clock-names = "ahb", "mmc";
interrupts = <33>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- mmc2: mmc at 01c11000 {
+ mmc2: mmc at 1c11000 {
compatible = "allwinner,sun4i-a10-mmc";
reg = <0x01c11000 0x1000>;
- clocks = <&ahb_gates 10>,
- <&mmc2_clk 0>,
- <&mmc2_clk 1>,
- <&mmc2_clk 2>;
- clock-names = "ahb",
- "mmc",
- "output",
- "sample";
+ clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
+ clock-names = "ahb", "mmc";
interrupts = <34>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- mmc3: mmc at 01c12000 {
+ mmc3: mmc at 1c12000 {
compatible = "allwinner,sun4i-a10-mmc";
reg = <0x01c12000 0x1000>;
- clocks = <&ahb_gates 11>,
- <&mmc3_clk 0>,
- <&mmc3_clk 1>,
- <&mmc3_clk 2>;
- clock-names = "ahb",
- "mmc",
- "output",
- "sample";
+ clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>;
+ clock-names = "ahb", "mmc";
interrupts = <35>;
status = "disabled";
#address-cells = <1>;
@@ -956,6 +895,15 @@
#size-cells = <0>;
};
+ ccu: clock at 1c20000 {
+ compatible = "allwinner,sun4i-a10-ccu";
+ reg = <0x01c20000 0x400>;
+ clocks = <&osc24M>, <&osc32k>;
+ clock-names = "hosc", "losc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
intc: interrupt-controller at 01c20400 {
compatible = "allwinner,sun4i-a10-ic";
reg = <0x01c20400 0x400>;
@@ -1033,12 +981,12 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
- mmc0_pins_a: mmc0 at 0 {
- allwinner,pins = "PF0", "PF1", "PF2",
- "PF3", "PF4", "PF5";
- allwinner,function = "mmc0";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ mmc0_pins: mmc0-pins {
+ pins = "PF0", "PF1", "PF2",
+ "PF3", "PF4", "PF5";
+ function = "mmc0";
+ drive-strength = <30>;
+ bias-pull-up;
};
mmc0_cd_pin_reference_design: mmc0_cd_pin at 0 {
diff --git a/include/dt-bindings/clock/sun4i-a10-ccu.h b/include/dt-bindings/clock/sun4i-a10-ccu.h
new file mode 100644
index 0000000000..e4fa61be5c
--- /dev/null
+++ b/include/dt-bindings/clock/sun4i-a10-ccu.h
@@ -0,0 +1,202 @@
+/*
+ * Copyright (C) 2017 Priit Laes <plaes@plaes.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN4I_A10_H_
+#define _DT_BINDINGS_CLK_SUN4I_A10_H_
+
+#define CLK_HOSC 1
+#define CLK_PLL_VIDEO0_2X 9
+#define CLK_PLL_VIDEO1_2X 18
+#define CLK_CPU 20
+
+/* AHB Gates */
+#define CLK_AHB_OTG 26
+#define CLK_AHB_EHCI0 27
+#define CLK_AHB_OHCI0 28
+#define CLK_AHB_EHCI1 29
+#define CLK_AHB_OHCI1 30
+#define CLK_AHB_SS 31
+#define CLK_AHB_DMA 32
+#define CLK_AHB_BIST 33
+#define CLK_AHB_MMC0 34
+#define CLK_AHB_MMC1 35
+#define CLK_AHB_MMC2 36
+#define CLK_AHB_MMC3 37
+#define CLK_AHB_MS 38
+#define CLK_AHB_NAND 39
+#define CLK_AHB_SDRAM 40
+#define CLK_AHB_ACE 41
+#define CLK_AHB_EMAC 42
+#define CLK_AHB_TS 43
+#define CLK_AHB_SPI0 44
+#define CLK_AHB_SPI1 45
+#define CLK_AHB_SPI2 46
+#define CLK_AHB_SPI3 47
+#define CLK_AHB_PATA 48
+#define CLK_AHB_SATA 49
+#define CLK_AHB_GPS 50
+#define CLK_AHB_HSTIMER 51
+#define CLK_AHB_VE 52
+#define CLK_AHB_TVD 53
+#define CLK_AHB_TVE0 54
+#define CLK_AHB_TVE1 55
+#define CLK_AHB_LCD0 56
+#define CLK_AHB_LCD1 57
+#define CLK_AHB_CSI0 58
+#define CLK_AHB_CSI1 59
+#define CLK_AHB_HDMI0 60
+#define CLK_AHB_HDMI1 61
+#define CLK_AHB_DE_BE0 62
+#define CLK_AHB_DE_BE1 63
+#define CLK_AHB_DE_FE0 64
+#define CLK_AHB_DE_FE1 65
+#define CLK_AHB_GMAC 66
+#define CLK_AHB_MP 67
+#define CLK_AHB_GPU 68
+
+/* APB0 Gates */
+#define CLK_APB0_CODEC 69
+#define CLK_APB0_SPDIF 70
+#define CLK_APB0_I2S0 71
+#define CLK_APB0_AC97 72
+#define CLK_APB0_I2S1 73
+#define CLK_APB0_PIO 74
+#define CLK_APB0_IR0 75
+#define CLK_APB0_IR1 76
+#define CLK_APB0_I2S2 77
+#define CLK_APB0_KEYPAD 78
+
+/* APB1 Gates */
+#define CLK_APB1_I2C0 79
+#define CLK_APB1_I2C1 80
+#define CLK_APB1_I2C2 81
+#define CLK_APB1_I2C3 82
+#define CLK_APB1_CAN 83
+#define CLK_APB1_SCR 84
+#define CLK_APB1_PS20 85
+#define CLK_APB1_PS21 86
+#define CLK_APB1_I2C4 87
+#define CLK_APB1_UART0 88
+#define CLK_APB1_UART1 89
+#define CLK_APB1_UART2 90
+#define CLK_APB1_UART3 91
+#define CLK_APB1_UART4 92
+#define CLK_APB1_UART5 93
+#define CLK_APB1_UART6 94
+#define CLK_APB1_UART7 95
+
+/* IP clocks */
+#define CLK_NAND 96
+#define CLK_MS 97
+#define CLK_MMC0 98
+#define CLK_MMC0_OUTPUT 99
+#define CLK_MMC0_SAMPLE 100
+#define CLK_MMC1 101
+#define CLK_MMC1_OUTPUT 102
+#define CLK_MMC1_SAMPLE 103
+#define CLK_MMC2 104
+#define CLK_MMC2_OUTPUT 105
+#define CLK_MMC2_SAMPLE 106
+#define CLK_MMC3 107
+#define CLK_MMC3_OUTPUT 108
+#define CLK_MMC3_SAMPLE 109
+#define CLK_TS 110
+#define CLK_SS 111
+#define CLK_SPI0 112
+#define CLK_SPI1 113
+#define CLK_SPI2 114
+#define CLK_PATA 115
+#define CLK_IR0 116
+#define CLK_IR1 117
+#define CLK_I2S0 118
+#define CLK_AC97 119
+#define CLK_SPDIF 120
+#define CLK_KEYPAD 121
+#define CLK_SATA 122
+#define CLK_USB_OHCI0 123
+#define CLK_USB_OHCI1 124
+#define CLK_USB_PHY 125
+#define CLK_GPS 126
+#define CLK_SPI3 127
+#define CLK_I2S1 128
+#define CLK_I2S2 129
+
+/* DRAM Gates */
+#define CLK_DRAM_VE 130
+#define CLK_DRAM_CSI0 131
+#define CLK_DRAM_CSI1 132
+#define CLK_DRAM_TS 133
+#define CLK_DRAM_TVD 134
+#define CLK_DRAM_TVE0 135
+#define CLK_DRAM_TVE1 136
+#define CLK_DRAM_OUT 137
+#define CLK_DRAM_DE_FE1 138
+#define CLK_DRAM_DE_FE0 139
+#define CLK_DRAM_DE_BE0 140
+#define CLK_DRAM_DE_BE1 141
+#define CLK_DRAM_MP 142
+#define CLK_DRAM_ACE 143
+
+/* Display Engine Clocks */
+#define CLK_DE_BE0 144
+#define CLK_DE_BE1 145
+#define CLK_DE_FE0 146
+#define CLK_DE_FE1 147
+#define CLK_DE_MP 148
+#define CLK_TCON0_CH0 149
+#define CLK_TCON1_CH0 150
+#define CLK_CSI_SCLK 151
+#define CLK_TVD_SCLK2 152
+#define CLK_TVD 153
+#define CLK_TCON0_CH1_SCLK2 154
+#define CLK_TCON0_CH1 155
+#define CLK_TCON1_CH1_SCLK2 156
+#define CLK_TCON1_CH1 157
+#define CLK_CSI0 158
+#define CLK_CSI1 159
+#define CLK_CODEC 160
+#define CLK_VE 161
+#define CLK_AVS 162
+#define CLK_ACE 163
+#define CLK_HDMI 164
+#define CLK_GPU 165
+
+#endif /* _DT_BINDINGS_CLK_SUN4I_A10_H_ */
--
2.17.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 01/25] ARM: dts: sun4i: Sync A10 MMC nodes from Linux
2018-07-16 8:19 ` [U-Boot] [PATCH 01/25] ARM: dts: sun4i: Sync A10 MMC nodes from Linux Jagan Teki
@ 2018-07-16 9:30 ` Maxime Ripard
2018-07-16 10:28 ` Jagan Teki
0 siblings, 1 reply; 59+ messages in thread
From: Maxime Ripard @ 2018-07-16 9:30 UTC (permalink / raw)
To: u-boot
On Mon, Jul 16, 2018 at 01:49:32PM +0530, Jagan Teki wrote:
> DM_MMC need MMC nodes in dtsi need to update and
> follow Linux notation to support dm driven mmc driver.
> So sync mmc nodes for sun4i-a10 from Linux. This will
> also useful for CLK driver handling in future.
>
> Last linux commit for sun4i-a10.dtsi:
> commit 590b0c0cfc6162aeebbf43eaafb9753b56df1532
> Author: Pascal Roeleven <dev@pascalroeleven.nl>
> Date: Fri Apr 20 12:21:12 2018 +0200
>
> ARM: dts: sun4i: Fix incorrect clocks for displays
>
> Last linux commit for sun4i-a10-ccu.h:
> commit 4328a2186e5120cfd34c4f04c6e4b7e74fb8b7b4
> Author: Jonathan Liu <net147@gmail.com>
> Date: Tue Oct 17 20:18:03 2017 +0800
>
> clk: sunxi-ng: sun4i: Export video PLLs
Can't we just sync all the A10 DTs in one go to the latest kernel
release, instead of half doing the work with a random commit?
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [U-Boot] [PATCH 01/25] ARM: dts: sun4i: Sync A10 MMC nodes from Linux
2018-07-16 9:30 ` Maxime Ripard
@ 2018-07-16 10:28 ` Jagan Teki
2018-07-16 13:37 ` Maxime Ripard
0 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 10:28 UTC (permalink / raw)
To: u-boot
On Mon, Jul 16, 2018 at 3:00 PM, Maxime Ripard
<maxime.ripard@bootlin.com> wrote:
> On Mon, Jul 16, 2018 at 01:49:32PM +0530, Jagan Teki wrote:
>> DM_MMC need MMC nodes in dtsi need to update and
>> follow Linux notation to support dm driven mmc driver.
>> So sync mmc nodes for sun4i-a10 from Linux. This will
>> also useful for CLK driver handling in future.
>>
>> Last linux commit for sun4i-a10.dtsi:
>> commit 590b0c0cfc6162aeebbf43eaafb9753b56df1532
>> Author: Pascal Roeleven <dev@pascalroeleven.nl>
>> Date: Fri Apr 20 12:21:12 2018 +0200
>>
>> ARM: dts: sun4i: Fix incorrect clocks for displays
>>
>> Last linux commit for sun4i-a10-ccu.h:
>> commit 4328a2186e5120cfd34c4f04c6e4b7e74fb8b7b4
>> Author: Jonathan Liu <net147@gmail.com>
>> Date: Tue Oct 17 20:18:03 2017 +0800
>>
>> clk: sunxi-ng: sun4i: Export video PLLs
>
> Can't we just sync all the A10 DTs in one go to the latest kernel
> release, instead of half doing the work with a random commit?
Now we need only minimal changes in dtsi, no need for board dts files
to update for sun4i. All DT sync from Linux not require here at this
point of time. even the subsequent patches will add only mmc0 node in
dts files which are not available in Linux.
^ permalink raw reply [flat|nested] 59+ messages in thread
* [U-Boot] [PATCH 01/25] ARM: dts: sun4i: Sync A10 MMC nodes from Linux
2018-07-16 10:28 ` Jagan Teki
@ 2018-07-16 13:37 ` Maxime Ripard
0 siblings, 0 replies; 59+ messages in thread
From: Maxime Ripard @ 2018-07-16 13:37 UTC (permalink / raw)
To: u-boot
On Mon, Jul 16, 2018 at 03:58:51PM +0530, Jagan Teki wrote:
> On Mon, Jul 16, 2018 at 3:00 PM, Maxime Ripard
> <maxime.ripard@bootlin.com> wrote:
> > On Mon, Jul 16, 2018 at 01:49:32PM +0530, Jagan Teki wrote:
> >> DM_MMC need MMC nodes in dtsi need to update and
> >> follow Linux notation to support dm driven mmc driver.
> >> So sync mmc nodes for sun4i-a10 from Linux. This will
> >> also useful for CLK driver handling in future.
> >>
> >> Last linux commit for sun4i-a10.dtsi:
> >> commit 590b0c0cfc6162aeebbf43eaafb9753b56df1532
> >> Author: Pascal Roeleven <dev@pascalroeleven.nl>
> >> Date: Fri Apr 20 12:21:12 2018 +0200
> >>
> >> ARM: dts: sun4i: Fix incorrect clocks for displays
> >>
> >> Last linux commit for sun4i-a10-ccu.h:
> >> commit 4328a2186e5120cfd34c4f04c6e4b7e74fb8b7b4
> >> Author: Jonathan Liu <net147@gmail.com>
> >> Date: Tue Oct 17 20:18:03 2017 +0800
> >>
> >> clk: sunxi-ng: sun4i: Export video PLLs
> >
> > Can't we just sync all the A10 DTs in one go to the latest kernel
> > release, instead of half doing the work with a random commit?
>
> Now we need only minimal changes in dtsi, no need for board dts files
> to update for sun4i. All DT sync from Linux not require here at this
> point of time.
Why? A DT is an hardware description, the hardware doesn't change
between U-Boot and Linux.
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [U-Boot] [PATCH 02/25] ARM: dts: sun4i: Sync A10 board dts mmc0 node from Linux
2018-07-16 8:19 [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Jagan Teki
2018-07-16 8:19 ` [U-Boot] [PATCH 01/25] ARM: dts: sun4i: Sync A10 MMC nodes from Linux Jagan Teki
@ 2018-07-16 8:19 ` Jagan Teki
2018-07-16 8:19 ` [U-Boot] [PATCH 03/25] ARM: dts: sun4i: Add mmc0 node for iNet 3F Jagan Teki
` (23 subsequent siblings)
25 siblings, 0 replies; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 8:19 UTC (permalink / raw)
To: u-boot
Since sun4i-a10.dtsi synced from Linux, for compatibility
sync sun4i-a10 board mmc0 nodes from Linux.
Last linux commit for sun4i-a10*.dts
commit 190e3138f9577885691540dca59c2f07540bde04
Merge: cafc87023b0d a7affb13b271
Author: Arnd Bergmann <arnd@arndb.de>
Date: Tue Mar 27 14:58:00 2018 +0200
Merge tag 'sunxi-h3-h5-for-4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt
Cc: Adam Sampson <ats@offog.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/dts/sun4i-a10-a1000.dts | 5 +----
arch/arm/dts/sun4i-a10-ba10-tvbox.dts | 5 +----
arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts | 5 +----
arch/arm/dts/sun4i-a10-cubieboard.dts | 5 +----
arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts | 5 +----
arch/arm/dts/sun4i-a10-gemei-g9.dts | 5 +----
arch/arm/dts/sun4i-a10-hackberry.dts | 5 +----
arch/arm/dts/sun4i-a10-hyundai-a7hd.dts | 5 +----
arch/arm/dts/sun4i-a10-inet1.dts | 5 +----
arch/arm/dts/sun4i-a10-inet97fv2.dts | 5 +----
arch/arm/dts/sun4i-a10-inet9f-rev03.dts | 5 +----
arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts | 5 +----
arch/arm/dts/sun4i-a10-jesurun-q5.dts | 5 +----
arch/arm/dts/sun4i-a10-marsboard.dts | 5 +----
arch/arm/dts/sun4i-a10-mini-xplus.dts | 5 +----
arch/arm/dts/sun4i-a10-mk802.dts | 5 +----
arch/arm/dts/sun4i-a10-mk802ii.dts | 5 +----
arch/arm/dts/sun4i-a10-olinuxino-lime.dts | 5 +----
arch/arm/dts/sun4i-a10-pcduino.dts | 5 +----
arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts | 5 +----
20 files changed, 20 insertions(+), 80 deletions(-)
diff --git a/arch/arm/dts/sun4i-a10-a1000.dts b/arch/arm/dts/sun4i-a10-a1000.dts
index 39e368ec34..52ce35508f 100644
--- a/arch/arm/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/dts/sun4i-a10-a1000.dts
@@ -167,12 +167,9 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/dts/sun4i-a10-ba10-tvbox.dts b/arch/arm/dts/sun4i-a10-ba10-tvbox.dts
index f3cb297fd1..414db62310 100644
--- a/arch/arm/dts/sun4i-a10-ba10-tvbox.dts
+++ b/arch/arm/dts/sun4i-a10-ba10-tvbox.dts
@@ -108,12 +108,9 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts b/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts
index 023b03efa5..14ad14bfbe 100644
--- a/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts
+++ b/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts
@@ -127,12 +127,9 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/dts/sun4i-a10-cubieboard.dts b/arch/arm/dts/sun4i-a10-cubieboard.dts
index 710e2ef516..713157d967 100644
--- a/arch/arm/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/dts/sun4i-a10-cubieboard.dts
@@ -142,12 +142,9 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts b/arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts
index 893497e397..f5334056ca 100644
--- a/arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts
+++ b/arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts
@@ -163,12 +163,9 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/dts/sun4i-a10-gemei-g9.dts b/arch/arm/dts/sun4i-a10-gemei-g9.dts
index ac64781a0a..a4e2d45249 100644
--- a/arch/arm/dts/sun4i-a10-gemei-g9.dts
+++ b/arch/arm/dts/sun4i-a10-gemei-g9.dts
@@ -145,12 +145,9 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH01 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH01 */
status = "okay";
};
diff --git a/arch/arm/dts/sun4i-a10-hackberry.dts b/arch/arm/dts/sun4i-a10-hackberry.dts
index 6de83a6187..ac8939f985 100644
--- a/arch/arm/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/dts/sun4i-a10-hackberry.dts
@@ -107,12 +107,9 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/dts/sun4i-a10-hyundai-a7hd.dts b/arch/arm/dts/sun4i-a10-hyundai-a7hd.dts
index 9103864fef..6904c55e74 100644
--- a/arch/arm/dts/sun4i-a10-hyundai-a7hd.dts
+++ b/arch/arm/dts/sun4i-a10-hyundai-a7hd.dts
@@ -78,12 +78,9 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/dts/sun4i-a10-inet1.dts b/arch/arm/dts/sun4i-a10-inet1.dts
index e09053bf5e..542816a8dc 100644
--- a/arch/arm/dts/sun4i-a10-inet1.dts
+++ b/arch/arm/dts/sun4i-a10-inet1.dts
@@ -161,12 +161,9 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/dts/sun4i-a10-inet97fv2.dts b/arch/arm/dts/sun4i-a10-inet97fv2.dts
index 04b0d2d1ae..8624fe1fa3 100644
--- a/arch/arm/dts/sun4i-a10-inet97fv2.dts
+++ b/arch/arm/dts/sun4i-a10-inet97fv2.dts
@@ -146,12 +146,9 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/dts/sun4i-a10-inet9f-rev03.dts
index bba4f9cf9b..3d36c0e060 100644
--- a/arch/arm/dts/sun4i-a10-inet9f-rev03.dts
+++ b/arch/arm/dts/sun4i-a10-inet9f-rev03.dts
@@ -305,12 +305,9 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts b/arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts
index 4e798f014c..0336333908 100644
--- a/arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts
+++ b/arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts
@@ -99,12 +99,9 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/dts/sun4i-a10-jesurun-q5.dts b/arch/arm/dts/sun4i-a10-jesurun-q5.dts
index e28f080b1f..3218a45e81 100644
--- a/arch/arm/dts/sun4i-a10-jesurun-q5.dts
+++ b/arch/arm/dts/sun4i-a10-jesurun-q5.dts
@@ -140,12 +140,9 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/dts/sun4i-a10-marsboard.dts b/arch/arm/dts/sun4i-a10-marsboard.dts
index 8e50723dbe..5c82b639c3 100644
--- a/arch/arm/dts/sun4i-a10-marsboard.dts
+++ b/arch/arm/dts/sun4i-a10-marsboard.dts
@@ -141,12 +141,9 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/dts/sun4i-a10-mini-xplus.dts b/arch/arm/dts/sun4i-a10-mini-xplus.dts
index a7dd86d30f..958b6b984e 100644
--- a/arch/arm/dts/sun4i-a10-mini-xplus.dts
+++ b/arch/arm/dts/sun4i-a10-mini-xplus.dts
@@ -97,12 +97,9 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/dts/sun4i-a10-mk802.dts b/arch/arm/dts/sun4i-a10-mk802.dts
index ee46ea8548..beac451356 100644
--- a/arch/arm/dts/sun4i-a10-mk802.dts
+++ b/arch/arm/dts/sun4i-a10-mk802.dts
@@ -72,12 +72,9 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/dts/sun4i-a10-mk802ii.dts b/arch/arm/dts/sun4i-a10-mk802ii.dts
index c861fa7e35..857384ad78 100644
--- a/arch/arm/dts/sun4i-a10-mk802ii.dts
+++ b/arch/arm/dts/sun4i-a10-mk802ii.dts
@@ -82,12 +82,9 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/dts/sun4i-a10-olinuxino-lime.dts
index b350448c72..3e93ebc93e 100644
--- a/arch/arm/dts/sun4i-a10-olinuxino-lime.dts
+++ b/arch/arm/dts/sun4i-a10-olinuxino-lime.dts
@@ -145,12 +145,9 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/dts/sun4i-a10-pcduino.dts b/arch/arm/dts/sun4i-a10-pcduino.dts
index 39034aa8e1..aa3ffb2b2b 100644
--- a/arch/arm/dts/sun4i-a10-pcduino.dts
+++ b/arch/arm/dts/sun4i-a10-pcduino.dts
@@ -147,12 +147,9 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts
index ea90634e48..6bd3bc0863 100644
--- a/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts
+++ b/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts
@@ -156,12 +156,9 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
--
2.17.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 03/25] ARM: dts: sun4i: Add mmc0 node for iNet 3F
2018-07-16 8:19 [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Jagan Teki
2018-07-16 8:19 ` [U-Boot] [PATCH 01/25] ARM: dts: sun4i: Sync A10 MMC nodes from Linux Jagan Teki
2018-07-16 8:19 ` [U-Boot] [PATCH 02/25] ARM: dts: sun4i: Sync A10 board dts mmc0 node " Jagan Teki
@ 2018-07-16 8:19 ` Jagan Teki
2018-07-16 8:19 ` [U-Boot] [PATCH 04/25] ARM: dts: sun4i: Add mmc0 node for iNet 3W Jagan Teki
` (22 subsequent siblings)
25 siblings, 0 replies; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 8:19 UTC (permalink / raw)
To: u-boot
Since SUN4I moved to DM_MMC, we need to have mmc node
in iNet 3F DT otherwise it will not probe.
Cc: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/dts/sun4i-a10-inet-3f.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/dts/sun4i-a10-inet-3f.dts b/arch/arm/dts/sun4i-a10-inet-3f.dts
index f815b83157..4ebf206c4a 100644
--- a/arch/arm/dts/sun4i-a10-inet-3f.dts
+++ b/arch/arm/dts/sun4i-a10-inet-3f.dts
@@ -7,6 +7,8 @@
/dts-v1/;
#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "iNet 3F";
@@ -21,6 +23,13 @@
};
};
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
--
2.17.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 04/25] ARM: dts: sun4i: Add mmc0 node for iNet 3W
2018-07-16 8:19 [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Jagan Teki
` (2 preceding siblings ...)
2018-07-16 8:19 ` [U-Boot] [PATCH 03/25] ARM: dts: sun4i: Add mmc0 node for iNet 3F Jagan Teki
@ 2018-07-16 8:19 ` Jagan Teki
2018-07-16 8:19 ` [U-Boot] [PATCH 05/25] dm: mmc: sunxi: Refactor ahb gate and clock setup Jagan Teki
` (21 subsequent siblings)
25 siblings, 0 replies; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 8:19 UTC (permalink / raw)
To: u-boot
Since SUN4I moved to DM_MMC, we need to have mmc node
in iNet 3W DT otherwise it will not probe.
Cc: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/dts/sun4i-a10-inet-3w.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/dts/sun4i-a10-inet-3w.dts b/arch/arm/dts/sun4i-a10-inet-3w.dts
index d0267ceee9..4168e2c0d0 100644
--- a/arch/arm/dts/sun4i-a10-inet-3w.dts
+++ b/arch/arm/dts/sun4i-a10-inet-3w.dts
@@ -7,6 +7,8 @@
/dts-v1/;
#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "iNet 3W";
@@ -21,6 +23,13 @@
};
};
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 20 GPIO_ACTIVE_LOW>; /* PH20 */
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
--
2.17.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 05/25] dm: mmc: sunxi: Refactor ahb gate and clock setup
2018-07-16 8:19 [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Jagan Teki
` (3 preceding siblings ...)
2018-07-16 8:19 ` [U-Boot] [PATCH 04/25] ARM: dts: sun4i: Add mmc0 node for iNet 3W Jagan Teki
@ 2018-07-16 8:19 ` Jagan Teki
2018-07-16 8:19 ` [U-Boot] [PATCH 06/25] dm: mmc: sunxi: Add ahb reset0 register write Jagan Teki
` (20 subsequent siblings)
25 siblings, 0 replies; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 8:19 UTC (permalink / raw)
To: u-boot
Existing dm code for ahb gate clock will be suitable to handle
sun4i,5i,6i and 7i U-Boot specific mmc dt nodes, which are different
from Linux in terms of clocks phandle notation.
U-Boot DT clocks phandle follow direct ahb and clock address on
node definition with specific bit position, but Linux clocks phandle
follow macros to define AHB and MMC clocks so-that the ccu driver
will set the bits accordingly.
Clocks phandle notations in U-Boot for higher Allwinner SoC start
from sun8i, sun50i are following Linux notation to sync with common
node definition along with proper clock driver handling.
So refactor the ahb gate, clock setup to handle all type of Allwinner SoCs.
Since we don't have proper CLK driver yet, this code using driver data
to differentiate require SoC specific data.
This require existing U-Boot mmc DT nodes need to sync with Linux
and the subsequent patches are doing the same.
Cc: Simon Glass <sjg@chromium.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/mmc/sunxi_mmc.c | 39 ++++++++++++++++++++++++++++-----------
1 file changed, 28 insertions(+), 11 deletions(-)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 7fa1ae8b16..38171b81f3 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -569,8 +569,8 @@ static int sunxi_mmc_probe(struct udevice *dev)
struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
struct sunxi_mmc_priv *priv = dev_get_priv(dev);
struct mmc_config *cfg = &plat->cfg;
+ struct sunxi_ccm_reg *ccm;
struct ofnode_phandle_args args;
- u32 *gate_reg;
int bus_width, ret;
cfg->name = dev->name;
@@ -589,21 +589,38 @@ static int sunxi_mmc_probe(struct udevice *dev)
cfg->f_max = 52000000;
priv->reg = (void *)dev_read_addr(dev);
+ priv->mmc_no = (((uintptr_t)priv->reg / 0x1000) - 0x1C0F);
- /* We don't have a sunxi clock driver so find the clock address here */
ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
- 1, &args);
+ 0, &args);
if (ret)
return ret;
- priv->mclkreg = (u32 *)ofnode_get_addr(args.node);
- ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
- 0, &args);
- if (ret)
- return ret;
- gate_reg = (u32 *)ofnode_get_addr(args.node);
- setbits_le32(gate_reg, 1 << args.args[0]);
- priv->mmc_no = args.args[0] - 8;
+ ccm = (struct sunxi_ccm_reg *)ofnode_get_addr(args.node);
+ if (IS_ERR(ccm))
+ return PTR_ERR(ccm);
+
+ /* enable ahb gate */
+ setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no)));
+
+ /* find clock reg */
+ switch (priv->mmc_no) {
+ case 0:
+ priv->mclkreg = &ccm->sd0_clk_cfg;
+ break;
+ case 1:
+ priv->mclkreg = &ccm->sd1_clk_cfg;
+ break;
+ case 2:
+ priv->mclkreg = &ccm->sd2_clk_cfg;
+ break;
+ case 3:
+ priv->mclkreg = &ccm->sd3_clk_cfg;
+ break;
+ default:
+ printf("Wrong mmc number %d\n", priv->mmc_no);
+ return -EINVAL;
+ }
ret = mmc_set_mod_clk(priv, 24000000);
if (ret)
--
2.17.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 06/25] dm: mmc: sunxi: Add ahb reset0 register write
2018-07-16 8:19 [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Jagan Teki
` (4 preceding siblings ...)
2018-07-16 8:19 ` [U-Boot] [PATCH 05/25] dm: mmc: sunxi: Refactor ahb gate and clock setup Jagan Teki
@ 2018-07-16 8:19 ` Jagan Teki
2018-07-16 9:39 ` Maxime Ripard
2018-07-16 8:19 ` [U-Boot] [PATCH 07/25] ARM: dts: sun7i: Sync A20 MMC nodes from Linux Jagan Teki
` (19 subsequent siblings)
25 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 8:19 UTC (permalink / raw)
To: u-boot
AHB reset0 is needed for Allwinner start from sun6i, so
add driver data configuration for ahb reset0 and update
the register bits during probe.
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/mmc/sunxi_mmc.c | 36 +++++++++++++++++++++++++++++++++---
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 38171b81f3..beeded50af 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -30,6 +30,7 @@ struct sunxi_mmc_priv {
unsigned fatal_err;
struct gpio_desc cd_gpio; /* Change Detect GPIO */
int cd_inverted; /* Inverted Card Detect */
+ u32 *reg_reset0;
struct sunxi_mmc *reg;
struct mmc_config cfg;
};
@@ -528,6 +529,14 @@ struct mmc *sunxi_mmc_init(int sdc_no)
}
#else
+#define OFF_SUN6I_AHB_RESET0 0x2c0
+
+struct sunxi_mmc_config {
+ bool has_reset0;
+ u8 pos_reset0;
+ u32 off_reset0;
+};
+
static int sunxi_mmc_set_ios(struct udevice *dev)
{
struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
@@ -569,6 +578,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
struct sunxi_mmc_priv *priv = dev_get_priv(dev);
struct mmc_config *cfg = &plat->cfg;
+ const struct sunxi_mmc_config *data;
struct sunxi_ccm_reg *ccm;
struct ofnode_phandle_args args;
int bus_width, ret;
@@ -588,6 +598,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
cfg->f_min = 400000;
cfg->f_max = 52000000;
+ data = (struct sunxi_mmc_config *)dev_get_driver_data(dev);
priv->reg = (void *)dev_read_addr(dev);
priv->mmc_no = (((uintptr_t)priv->reg / 0x1000) - 0x1C0F);
@@ -600,9 +611,15 @@ static int sunxi_mmc_probe(struct udevice *dev)
if (IS_ERR(ccm))
return PTR_ERR(ccm);
+ priv->reg_reset0 = (void *)ccm + data->off_reset0;
+
/* enable ahb gate */
setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no)));
+ /* unassert reset */
+ if (data->has_reset0)
+ setbits_le32(priv->reg_reset0, BIT(data->pos_reset0 + priv->mmc_no));
+
/* find clock reg */
switch (priv->mmc_no) {
case 0:
@@ -653,10 +670,23 @@ static int sunxi_mmc_bind(struct udevice *dev)
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
+static const struct sunxi_mmc_config sun4i_a10_cfg = {
+ .has_reset0 = false,
+};
+
+static const struct sunxi_mmc_config sun7i_a20_cfg = {
+ .has_reset0 = true,
+ .pos_reset0 = 8,
+ .off_reset0 = OFF_SUN6I_AHB_RESET0,
+};
+
static const struct udevice_id sunxi_mmc_ids[] = {
- { .compatible = "allwinner,sun4i-a10-mmc" },
- { .compatible = "allwinner,sun5i-a13-mmc" },
- { .compatible = "allwinner,sun7i-a20-mmc" },
+ { .compatible = "allwinner,sun4i-a10-mmc",
+ .data = (ulong)&sun4i_a10_cfg },
+ { .compatible = "allwinner,sun5i-a13-mmc",
+ .data = (ulong)&sun4i_a10_cfg },
+ { .compatible = "allwinner,sun7i-a20-mmc",
+ .data = (ulong)&sun7i_a20_cfg },
{ }
};
--
2.17.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 06/25] dm: mmc: sunxi: Add ahb reset0 register write
2018-07-16 8:19 ` [U-Boot] [PATCH 06/25] dm: mmc: sunxi: Add ahb reset0 register write Jagan Teki
@ 2018-07-16 9:39 ` Maxime Ripard
2018-07-16 9:55 ` Jagan Teki
0 siblings, 1 reply; 59+ messages in thread
From: Maxime Ripard @ 2018-07-16 9:39 UTC (permalink / raw)
To: u-boot
On Mon, Jul 16, 2018 at 01:49:37PM +0530, Jagan Teki wrote:
> AHB reset0 is needed for Allwinner start from sun6i, so
> add driver data configuration for ahb reset0 and update
> the register bits during probe.
>
> Cc: Jaehoon Chung <jh80.chung@samsung.com>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
> drivers/mmc/sunxi_mmc.c | 36 +++++++++++++++++++++++++++++++++---
> 1 file changed, 33 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
> index 38171b81f3..beeded50af 100644
> --- a/drivers/mmc/sunxi_mmc.c
> +++ b/drivers/mmc/sunxi_mmc.c
> @@ -30,6 +30,7 @@ struct sunxi_mmc_priv {
> unsigned fatal_err;
> struct gpio_desc cd_gpio; /* Change Detect GPIO */
> int cd_inverted; /* Inverted Card Detect */
> + u32 *reg_reset0;
> struct sunxi_mmc *reg;
> struct mmc_config cfg;
> };
> @@ -528,6 +529,14 @@ struct mmc *sunxi_mmc_init(int sdc_no)
> }
> #else
>
> +#define OFF_SUN6I_AHB_RESET0 0x2c0
> +
> +struct sunxi_mmc_config {
> + bool has_reset0;
> + u8 pos_reset0;
> + u32 off_reset0;
> +};
> +
> static int sunxi_mmc_set_ios(struct udevice *dev)
> {
> struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
> @@ -569,6 +578,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
> struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
> struct sunxi_mmc_priv *priv = dev_get_priv(dev);
> struct mmc_config *cfg = &plat->cfg;
> + const struct sunxi_mmc_config *data;
> struct sunxi_ccm_reg *ccm;
> struct ofnode_phandle_args args;
> int bus_width, ret;
> @@ -588,6 +598,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
> cfg->f_min = 400000;
> cfg->f_max = 52000000;
>
> + data = (struct sunxi_mmc_config *)dev_get_driver_data(dev);
> priv->reg = (void *)dev_read_addr(dev);
> priv->mmc_no = (((uintptr_t)priv->reg / 0x1000) - 0x1C0F);
>
> @@ -600,9 +611,15 @@ static int sunxi_mmc_probe(struct udevice *dev)
> if (IS_ERR(ccm))
> return PTR_ERR(ccm);
>
> + priv->reg_reset0 = (void *)ccm + data->off_reset0;
> +
> /* enable ahb gate */
> setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no)));
>
> + /* unassert reset */
> + if (data->has_reset0)
> + setbits_le32(priv->reg_reset0, BIT(data->pos_reset0 + priv->mmc_no));
> +
> /* find clock reg */
> switch (priv->mmc_no) {
> case 0:
> @@ -653,10 +670,23 @@ static int sunxi_mmc_bind(struct udevice *dev)
> return mmc_bind(dev, &plat->mmc, &plat->cfg);
> }
>
> +static const struct sunxi_mmc_config sun4i_a10_cfg = {
> + .has_reset0 = false,
> +};
> +
> +static const struct sunxi_mmc_config sun7i_a20_cfg = {
> + .has_reset0 = true,
> + .pos_reset0 = 8,
> + .off_reset0 = OFF_SUN6I_AHB_RESET0,
> +};
Nope. The A20 doesn't have any reset line.
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 06/25] dm: mmc: sunxi: Add ahb reset0 register write
2018-07-16 9:39 ` Maxime Ripard
@ 2018-07-16 9:55 ` Jagan Teki
2018-07-16 10:02 ` Maxime Ripard
0 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 9:55 UTC (permalink / raw)
To: u-boot
On Mon, Jul 16, 2018 at 3:09 PM, Maxime Ripard
<maxime.ripard@bootlin.com> wrote:
> On Mon, Jul 16, 2018 at 01:49:37PM +0530, Jagan Teki wrote:
>> AHB reset0 is needed for Allwinner start from sun6i, so
>> add driver data configuration for ahb reset0 and update
>> the register bits during probe.
>>
>> Cc: Jaehoon Chung <jh80.chung@samsung.com>
>> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>> ---
>> drivers/mmc/sunxi_mmc.c | 36 +++++++++++++++++++++++++++++++++---
>> 1 file changed, 33 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
>> index 38171b81f3..beeded50af 100644
>> --- a/drivers/mmc/sunxi_mmc.c
>> +++ b/drivers/mmc/sunxi_mmc.c
>> @@ -30,6 +30,7 @@ struct sunxi_mmc_priv {
>> unsigned fatal_err;
>> struct gpio_desc cd_gpio; /* Change Detect GPIO */
>> int cd_inverted; /* Inverted Card Detect */
>> + u32 *reg_reset0;
>> struct sunxi_mmc *reg;
>> struct mmc_config cfg;
>> };
>> @@ -528,6 +529,14 @@ struct mmc *sunxi_mmc_init(int sdc_no)
>> }
>> #else
>>
>> +#define OFF_SUN6I_AHB_RESET0 0x2c0
>> +
>> +struct sunxi_mmc_config {
>> + bool has_reset0;
>> + u8 pos_reset0;
>> + u32 off_reset0;
>> +};
>> +
>> static int sunxi_mmc_set_ios(struct udevice *dev)
>> {
>> struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
>> @@ -569,6 +578,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
>> struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
>> struct sunxi_mmc_priv *priv = dev_get_priv(dev);
>> struct mmc_config *cfg = &plat->cfg;
>> + const struct sunxi_mmc_config *data;
>> struct sunxi_ccm_reg *ccm;
>> struct ofnode_phandle_args args;
>> int bus_width, ret;
>> @@ -588,6 +598,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
>> cfg->f_min = 400000;
>> cfg->f_max = 52000000;
>>
>> + data = (struct sunxi_mmc_config *)dev_get_driver_data(dev);
>> priv->reg = (void *)dev_read_addr(dev);
>> priv->mmc_no = (((uintptr_t)priv->reg / 0x1000) - 0x1C0F);
>>
>> @@ -600,9 +611,15 @@ static int sunxi_mmc_probe(struct udevice *dev)
>> if (IS_ERR(ccm))
>> return PTR_ERR(ccm);
>>
>> + priv->reg_reset0 = (void *)ccm + data->off_reset0;
>> +
>> /* enable ahb gate */
>> setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no)));
>>
>> + /* unassert reset */
>> + if (data->has_reset0)
>> + setbits_le32(priv->reg_reset0, BIT(data->pos_reset0 + priv->mmc_no));
>> +
>> /* find clock reg */
>> switch (priv->mmc_no) {
>> case 0:
>> @@ -653,10 +670,23 @@ static int sunxi_mmc_bind(struct udevice *dev)
>> return mmc_bind(dev, &plat->mmc, &plat->cfg);
>> }
>>
>> +static const struct sunxi_mmc_config sun4i_a10_cfg = {
>> + .has_reset0 = false,
>> +};
>> +
>> +static const struct sunxi_mmc_config sun7i_a20_cfg = {
>> + .has_reset0 = true,
>> + .pos_reset0 = 8,
>> + .off_reset0 = OFF_SUN6I_AHB_RESET0,
>> +};
>
> Nope. The A20 doesn't have any reset line.
Yes, I know. but sun6i-a31 has it and share same compatible
allwinner,sun7i-a20-mmc ie reason I've attached driver data.
^ permalink raw reply [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 06/25] dm: mmc: sunxi: Add ahb reset0 register write
2018-07-16 9:55 ` Jagan Teki
@ 2018-07-16 10:02 ` Maxime Ripard
2018-07-16 10:39 ` Jagan Teki
0 siblings, 1 reply; 59+ messages in thread
From: Maxime Ripard @ 2018-07-16 10:02 UTC (permalink / raw)
To: u-boot
On Mon, Jul 16, 2018 at 03:25:08PM +0530, Jagan Teki wrote:
> On Mon, Jul 16, 2018 at 3:09 PM, Maxime Ripard
> <maxime.ripard@bootlin.com> wrote:
> > On Mon, Jul 16, 2018 at 01:49:37PM +0530, Jagan Teki wrote:
> >> AHB reset0 is needed for Allwinner start from sun6i, so
> >> add driver data configuration for ahb reset0 and update
> >> the register bits during probe.
> >>
> >> Cc: Jaehoon Chung <jh80.chung@samsung.com>
> >> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> >> ---
> >> drivers/mmc/sunxi_mmc.c | 36 +++++++++++++++++++++++++++++++++---
> >> 1 file changed, 33 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
> >> index 38171b81f3..beeded50af 100644
> >> --- a/drivers/mmc/sunxi_mmc.c
> >> +++ b/drivers/mmc/sunxi_mmc.c
> >> @@ -30,6 +30,7 @@ struct sunxi_mmc_priv {
> >> unsigned fatal_err;
> >> struct gpio_desc cd_gpio; /* Change Detect GPIO */
> >> int cd_inverted; /* Inverted Card Detect */
> >> + u32 *reg_reset0;
> >> struct sunxi_mmc *reg;
> >> struct mmc_config cfg;
> >> };
> >> @@ -528,6 +529,14 @@ struct mmc *sunxi_mmc_init(int sdc_no)
> >> }
> >> #else
> >>
> >> +#define OFF_SUN6I_AHB_RESET0 0x2c0
> >> +
> >> +struct sunxi_mmc_config {
> >> + bool has_reset0;
> >> + u8 pos_reset0;
> >> + u32 off_reset0;
> >> +};
> >> +
> >> static int sunxi_mmc_set_ios(struct udevice *dev)
> >> {
> >> struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
> >> @@ -569,6 +578,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
> >> struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
> >> struct sunxi_mmc_priv *priv = dev_get_priv(dev);
> >> struct mmc_config *cfg = &plat->cfg;
> >> + const struct sunxi_mmc_config *data;
> >> struct sunxi_ccm_reg *ccm;
> >> struct ofnode_phandle_args args;
> >> int bus_width, ret;
> >> @@ -588,6 +598,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
> >> cfg->f_min = 400000;
> >> cfg->f_max = 52000000;
> >>
> >> + data = (struct sunxi_mmc_config *)dev_get_driver_data(dev);
> >> priv->reg = (void *)dev_read_addr(dev);
> >> priv->mmc_no = (((uintptr_t)priv->reg / 0x1000) - 0x1C0F);
> >>
> >> @@ -600,9 +611,15 @@ static int sunxi_mmc_probe(struct udevice *dev)
> >> if (IS_ERR(ccm))
> >> return PTR_ERR(ccm);
> >>
> >> + priv->reg_reset0 = (void *)ccm + data->off_reset0;
> >> +
> >> /* enable ahb gate */
> >> setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no)));
> >>
> >> + /* unassert reset */
> >> + if (data->has_reset0)
> >> + setbits_le32(priv->reg_reset0, BIT(data->pos_reset0 + priv->mmc_no));
> >> +
> >> /* find clock reg */
> >> switch (priv->mmc_no) {
> >> case 0:
> >> @@ -653,10 +670,23 @@ static int sunxi_mmc_bind(struct udevice *dev)
> >> return mmc_bind(dev, &plat->mmc, &plat->cfg);
> >> }
> >>
> >> +static const struct sunxi_mmc_config sun4i_a10_cfg = {
> >> + .has_reset0 = false,
> >> +};
> >> +
> >> +static const struct sunxi_mmc_config sun7i_a20_cfg = {
> >> + .has_reset0 = true,
> >> + .pos_reset0 = 8,
> >> + .off_reset0 = OFF_SUN6I_AHB_RESET0,
> >> +};
> >
> > Nope. The A20 doesn't have any reset line.
>
> Yes, I know. but sun6i-a31 has it and share same compatible
> allwinner,sun7i-a20-mmc ie reason I've attached driver data.
That doesn't make it more correct. The A20 doesn't have a reset line,
I don't see any good reason to imply this.
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 06/25] dm: mmc: sunxi: Add ahb reset0 register write
2018-07-16 10:02 ` Maxime Ripard
@ 2018-07-16 10:39 ` Jagan Teki
2018-07-16 13:36 ` Maxime Ripard
0 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 10:39 UTC (permalink / raw)
To: u-boot
On Mon, Jul 16, 2018 at 3:32 PM, Maxime Ripard
<maxime.ripard@bootlin.com> wrote:
> On Mon, Jul 16, 2018 at 03:25:08PM +0530, Jagan Teki wrote:
>> On Mon, Jul 16, 2018 at 3:09 PM, Maxime Ripard
>> <maxime.ripard@bootlin.com> wrote:
>> > On Mon, Jul 16, 2018 at 01:49:37PM +0530, Jagan Teki wrote:
>> >> AHB reset0 is needed for Allwinner start from sun6i, so
>> >> add driver data configuration for ahb reset0 and update
>> >> the register bits during probe.
>> >>
>> >> Cc: Jaehoon Chung <jh80.chung@samsung.com>
>> >> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>> >> ---
>> >> drivers/mmc/sunxi_mmc.c | 36 +++++++++++++++++++++++++++++++++---
>> >> 1 file changed, 33 insertions(+), 3 deletions(-)
>> >>
>> >> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
>> >> index 38171b81f3..beeded50af 100644
>> >> --- a/drivers/mmc/sunxi_mmc.c
>> >> +++ b/drivers/mmc/sunxi_mmc.c
>> >> @@ -30,6 +30,7 @@ struct sunxi_mmc_priv {
>> >> unsigned fatal_err;
>> >> struct gpio_desc cd_gpio; /* Change Detect GPIO */
>> >> int cd_inverted; /* Inverted Card Detect */
>> >> + u32 *reg_reset0;
>> >> struct sunxi_mmc *reg;
>> >> struct mmc_config cfg;
>> >> };
>> >> @@ -528,6 +529,14 @@ struct mmc *sunxi_mmc_init(int sdc_no)
>> >> }
>> >> #else
>> >>
>> >> +#define OFF_SUN6I_AHB_RESET0 0x2c0
>> >> +
>> >> +struct sunxi_mmc_config {
>> >> + bool has_reset0;
>> >> + u8 pos_reset0;
>> >> + u32 off_reset0;
>> >> +};
>> >> +
>> >> static int sunxi_mmc_set_ios(struct udevice *dev)
>> >> {
>> >> struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
>> >> @@ -569,6 +578,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
>> >> struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
>> >> struct sunxi_mmc_priv *priv = dev_get_priv(dev);
>> >> struct mmc_config *cfg = &plat->cfg;
>> >> + const struct sunxi_mmc_config *data;
>> >> struct sunxi_ccm_reg *ccm;
>> >> struct ofnode_phandle_args args;
>> >> int bus_width, ret;
>> >> @@ -588,6 +598,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
>> >> cfg->f_min = 400000;
>> >> cfg->f_max = 52000000;
>> >>
>> >> + data = (struct sunxi_mmc_config *)dev_get_driver_data(dev);
>> >> priv->reg = (void *)dev_read_addr(dev);
>> >> priv->mmc_no = (((uintptr_t)priv->reg / 0x1000) - 0x1C0F);
>> >>
>> >> @@ -600,9 +611,15 @@ static int sunxi_mmc_probe(struct udevice *dev)
>> >> if (IS_ERR(ccm))
>> >> return PTR_ERR(ccm);
>> >>
>> >> + priv->reg_reset0 = (void *)ccm + data->off_reset0;
>> >> +
>> >> /* enable ahb gate */
>> >> setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no)));
>> >>
>> >> + /* unassert reset */
>> >> + if (data->has_reset0)
>> >> + setbits_le32(priv->reg_reset0, BIT(data->pos_reset0 + priv->mmc_no));
>> >> +
>> >> /* find clock reg */
>> >> switch (priv->mmc_no) {
>> >> case 0:
>> >> @@ -653,10 +670,23 @@ static int sunxi_mmc_bind(struct udevice *dev)
>> >> return mmc_bind(dev, &plat->mmc, &plat->cfg);
>> >> }
>> >>
>> >> +static const struct sunxi_mmc_config sun4i_a10_cfg = {
>> >> + .has_reset0 = false,
>> >> +};
>> >> +
>> >> +static const struct sunxi_mmc_config sun7i_a20_cfg = {
>> >> + .has_reset0 = true,
>> >> + .pos_reset0 = 8,
>> >> + .off_reset0 = OFF_SUN6I_AHB_RESET0,
>> >> +};
>> >
>> > Nope. The A20 doesn't have any reset line.
>>
>> Yes, I know. but sun6i-a31 has it and share same compatible
>> allwinner,sun7i-a20-mmc ie reason I've attached driver data.
>
> That doesn't make it more correct. The A20 doesn't have a reset line,
> I don't see any good reason to imply this.
OK, let me know if you have any suggestion on this I will remove this for A20.
^ permalink raw reply [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 06/25] dm: mmc: sunxi: Add ahb reset0 register write
2018-07-16 10:39 ` Jagan Teki
@ 2018-07-16 13:36 ` Maxime Ripard
0 siblings, 0 replies; 59+ messages in thread
From: Maxime Ripard @ 2018-07-16 13:36 UTC (permalink / raw)
To: u-boot
On Mon, Jul 16, 2018 at 04:09:35PM +0530, Jagan Teki wrote:
> On Mon, Jul 16, 2018 at 3:32 PM, Maxime Ripard
> <maxime.ripard@bootlin.com> wrote:
> > On Mon, Jul 16, 2018 at 03:25:08PM +0530, Jagan Teki wrote:
> >> On Mon, Jul 16, 2018 at 3:09 PM, Maxime Ripard
> >> <maxime.ripard@bootlin.com> wrote:
> >> > On Mon, Jul 16, 2018 at 01:49:37PM +0530, Jagan Teki wrote:
> >> >> AHB reset0 is needed for Allwinner start from sun6i, so
> >> >> add driver data configuration for ahb reset0 and update
> >> >> the register bits during probe.
> >> >>
> >> >> Cc: Jaehoon Chung <jh80.chung@samsung.com>
> >> >> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> >> >> ---
> >> >> drivers/mmc/sunxi_mmc.c | 36 +++++++++++++++++++++++++++++++++---
> >> >> 1 file changed, 33 insertions(+), 3 deletions(-)
> >> >>
> >> >> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
> >> >> index 38171b81f3..beeded50af 100644
> >> >> --- a/drivers/mmc/sunxi_mmc.c
> >> >> +++ b/drivers/mmc/sunxi_mmc.c
> >> >> @@ -30,6 +30,7 @@ struct sunxi_mmc_priv {
> >> >> unsigned fatal_err;
> >> >> struct gpio_desc cd_gpio; /* Change Detect GPIO */
> >> >> int cd_inverted; /* Inverted Card Detect */
> >> >> + u32 *reg_reset0;
> >> >> struct sunxi_mmc *reg;
> >> >> struct mmc_config cfg;
> >> >> };
> >> >> @@ -528,6 +529,14 @@ struct mmc *sunxi_mmc_init(int sdc_no)
> >> >> }
> >> >> #else
> >> >>
> >> >> +#define OFF_SUN6I_AHB_RESET0 0x2c0
> >> >> +
> >> >> +struct sunxi_mmc_config {
> >> >> + bool has_reset0;
> >> >> + u8 pos_reset0;
> >> >> + u32 off_reset0;
> >> >> +};
> >> >> +
> >> >> static int sunxi_mmc_set_ios(struct udevice *dev)
> >> >> {
> >> >> struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
> >> >> @@ -569,6 +578,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
> >> >> struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
> >> >> struct sunxi_mmc_priv *priv = dev_get_priv(dev);
> >> >> struct mmc_config *cfg = &plat->cfg;
> >> >> + const struct sunxi_mmc_config *data;
> >> >> struct sunxi_ccm_reg *ccm;
> >> >> struct ofnode_phandle_args args;
> >> >> int bus_width, ret;
> >> >> @@ -588,6 +598,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
> >> >> cfg->f_min = 400000;
> >> >> cfg->f_max = 52000000;
> >> >>
> >> >> + data = (struct sunxi_mmc_config *)dev_get_driver_data(dev);
> >> >> priv->reg = (void *)dev_read_addr(dev);
> >> >> priv->mmc_no = (((uintptr_t)priv->reg / 0x1000) - 0x1C0F);
> >> >>
> >> >> @@ -600,9 +611,15 @@ static int sunxi_mmc_probe(struct udevice *dev)
> >> >> if (IS_ERR(ccm))
> >> >> return PTR_ERR(ccm);
> >> >>
> >> >> + priv->reg_reset0 = (void *)ccm + data->off_reset0;
> >> >> +
> >> >> /* enable ahb gate */
> >> >> setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no)));
> >> >>
> >> >> + /* unassert reset */
> >> >> + if (data->has_reset0)
> >> >> + setbits_le32(priv->reg_reset0, BIT(data->pos_reset0 + priv->mmc_no));
> >> >> +
> >> >> /* find clock reg */
> >> >> switch (priv->mmc_no) {
> >> >> case 0:
> >> >> @@ -653,10 +670,23 @@ static int sunxi_mmc_bind(struct udevice *dev)
> >> >> return mmc_bind(dev, &plat->mmc, &plat->cfg);
> >> >> }
> >> >>
> >> >> +static const struct sunxi_mmc_config sun4i_a10_cfg = {
> >> >> + .has_reset0 = false,
> >> >> +};
> >> >> +
> >> >> +static const struct sunxi_mmc_config sun7i_a20_cfg = {
> >> >> + .has_reset0 = true,
> >> >> + .pos_reset0 = 8,
> >> >> + .off_reset0 = OFF_SUN6I_AHB_RESET0,
> >> >> +};
> >> >
> >> > Nope. The A20 doesn't have any reset line.
> >>
> >> Yes, I know. but sun6i-a31 has it and share same compatible
> >> allwinner,sun7i-a20-mmc ie reason I've attached driver data.
> >
> > That doesn't make it more correct. The A20 doesn't have a reset line,
> > I don't see any good reason to imply this.
>
> OK, let me know if you have any suggestion on this I will remove
> this for A20.
Use the A31 name and tie it to the matching compatible instead?
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [U-Boot] [PATCH 07/25] ARM: dts: sun7i: Sync A20 MMC nodes from Linux
2018-07-16 8:19 [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Jagan Teki
` (5 preceding siblings ...)
2018-07-16 8:19 ` [U-Boot] [PATCH 06/25] dm: mmc: sunxi: Add ahb reset0 register write Jagan Teki
@ 2018-07-16 8:19 ` Jagan Teki
2018-07-16 8:19 ` [U-Boot] [PATCH 08/25] ARM: dts: sun7i: Add mmc0 node for Primo73 tablet Jagan Teki
` (18 subsequent siblings)
25 siblings, 0 replies; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 8:19 UTC (permalink / raw)
To: u-boot
DM_MMC need MMC nodes in dtsi need to update and
follow Linux notation to support dm driven mmc driver.
So sync mmc nodes for sun7i-a20 from Linux. This will
also useful for CLK driver handling in future.
Last linux commit for sun7i-a20.dtsi:
commit e3b742026b92a141b43560858b089921953a63de
Author: Viresh Kumar <viresh.kumar@linaro.org>
Date: Tue Jun 5 10:17:49 2018 +0530
ARM: dts: sunxi: Add missing cooling device properties for CPUs
Last linux commit for sun7i-a20-ccu.h:
commit c84f5683f6e9fee78e054431d89121225ccb7464
Author: Priit Laes <plaes@plaes.org>
Date: Wed Aug 23 20:23:29 2017 +0300
clk: sunxi-ng: Add sun4i/sun7i CCU driver
Cc: Stefan Mavrodiev <stefan@olimex.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/dts/sun7i-a20.dtsi | 102 ++++++++--------------
include/dt-bindings/clock/sun7i-a20-ccu.h | 53 +++++++++++
2 files changed, 87 insertions(+), 68 deletions(-)
create mode 100644 include/dt-bindings/clock/sun7i-a20-ccu.h
diff --git a/arch/arm/dts/sun7i-a20.dtsi b/arch/arm/dts/sun7i-a20.dtsi
index 4394711e5a..620e4d5a21 100644
--- a/arch/arm/dts/sun7i-a20.dtsi
+++ b/arch/arm/dts/sun7i-a20.dtsi
@@ -49,6 +49,7 @@
#include <dt-bindings/clock/sun4i-a10-pll2.h>
#include <dt-bindings/dma/sun4i-a10.h>
+#include <dt-bindings/clock/sun7i-a20-ccu.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
@@ -419,46 +420,6 @@
clock-output-names = "ms";
};
- mmc0_clk: clk at 01c20088 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c20088 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc0",
- "mmc0_output",
- "mmc0_sample";
- };
-
- mmc1_clk: clk at 01c2008c {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c2008c 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc1",
- "mmc1_output",
- "mmc1_sample";
- };
-
- mmc2_clk: clk at 01c20090 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c20090 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc2",
- "mmc2_output",
- "mmc2_sample";
- };
-
- mmc3_clk: clk at 01c20094 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c20094 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc3",
- "mmc3_output",
- "mmc3_sample";
- };
-
ts_clk: clk at 01c20098 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
@@ -904,14 +865,13 @@
#size-cells = <0>;
};
- mmc0: mmc at 01c0f000 {
- compatible = "allwinner,sun7i-a20-mmc",
- "allwinner,sun5i-a13-mmc";
+ mmc0: mmc at 1c0f000 {
+ compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
- clocks = <&ahb_gates 8>,
- <&mmc0_clk 0>,
- <&mmc0_clk 1>,
- <&mmc0_clk 2>;
+ clocks = <&ccu CLK_AHB_MMC0>,
+ <&ccu CLK_MMC0>,
+ <&ccu CLK_MMC0_OUTPUT>,
+ <&ccu CLK_MMC0_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
@@ -922,14 +882,13 @@
#size-cells = <0>;
};
- mmc1: mmc at 01c10000 {
- compatible = "allwinner,sun7i-a20-mmc",
- "allwinner,sun5i-a13-mmc";
+ mmc1: mmc at 1c10000 {
+ compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c10000 0x1000>;
- clocks = <&ahb_gates 9>,
- <&mmc1_clk 0>,
- <&mmc1_clk 1>,
- <&mmc1_clk 2>;
+ clocks = <&ccu CLK_AHB_MMC1>,
+ <&ccu CLK_MMC1>,
+ <&ccu CLK_MMC1_OUTPUT>,
+ <&ccu CLK_MMC1_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
@@ -940,14 +899,13 @@
#size-cells = <0>;
};
- mmc2: mmc at 01c11000 {
- compatible = "allwinner,sun7i-a20-mmc",
- "allwinner,sun5i-a13-mmc";
+ mmc2: mmc at 1c11000 {
+ compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c11000 0x1000>;
- clocks = <&ahb_gates 10>,
- <&mmc2_clk 0>,
- <&mmc2_clk 1>,
- <&mmc2_clk 2>;
+ clocks = <&ccu CLK_AHB_MMC2>,
+ <&ccu CLK_MMC2>,
+ <&ccu CLK_MMC2_OUTPUT>,
+ <&ccu CLK_MMC2_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
@@ -958,14 +916,13 @@
#size-cells = <0>;
};
- mmc3: mmc at 01c12000 {
- compatible = "allwinner,sun7i-a20-mmc",
- "allwinner,sun5i-a13-mmc";
+ mmc3: mmc at 1c12000 {
+ compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c12000 0x1000>;
- clocks = <&ahb_gates 11>,
- <&mmc3_clk 0>,
- <&mmc3_clk 1>,
- <&mmc3_clk 2>;
+ clocks = <&ccu CLK_AHB_MMC3>,
+ <&ccu CLK_MMC3>,
+ <&ccu CLK_MMC3_OUTPUT>,
+ <&ccu CLK_MMC3_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
@@ -1085,6 +1042,15 @@
#size-cells = <0>;
};
+ ccu: clock at 1c20000 {
+ compatible = "allwinner,sun7i-a20-ccu";
+ reg = <0x01c20000 0x400>;
+ clocks = <&osc24M>, <&osc32k>;
+ clock-names = "hosc", "losc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
pio: pinctrl at 01c20800 {
compatible = "allwinner,sun7i-a20-pinctrl";
reg = <0x01c20800 0x400>;
diff --git a/include/dt-bindings/clock/sun7i-a20-ccu.h b/include/dt-bindings/clock/sun7i-a20-ccu.h
new file mode 100644
index 0000000000..045a5178da
--- /dev/null
+++ b/include/dt-bindings/clock/sun7i-a20-ccu.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2017 Priit Laes <plaes@plaes.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN7I_A20_H_
+#define _DT_BINDINGS_CLK_SUN7I_A20_H_
+
+#include <dt-bindings/clock/sun4i-a10-ccu.h>
+
+#define CLK_MBUS 166
+#define CLK_HDMI1_SLOW 167
+#define CLK_HDMI1 168
+#define CLK_OUT_A 169
+#define CLK_OUT_B 170
+
+#endif /* _DT_BINDINGS_CLK_SUN7I_A20_H_ */
--
2.17.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 08/25] ARM: dts: sun7i: Add mmc0 node for Primo73 tablet
2018-07-16 8:19 [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Jagan Teki
` (6 preceding siblings ...)
2018-07-16 8:19 ` [U-Boot] [PATCH 07/25] ARM: dts: sun7i: Sync A20 MMC nodes from Linux Jagan Teki
@ 2018-07-16 8:19 ` Jagan Teki
2018-07-16 9:40 ` Maxime Ripard
2018-07-16 8:19 ` [U-Boot] [PATCH 09/25] ARM: dts: sun7i: Add mmc0 node for Ainol AW1 Jagan Teki
` (17 subsequent siblings)
25 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 8:19 UTC (permalink / raw)
To: u-boot
Reuse mmc0 node from sun7i-a20.dtsi like other board
dts files for Primo73 tablet dts file, and drop in dts
mmc0 definition.
Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/dts/sun7i-a20-primo73.dts | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/dts/sun7i-a20-primo73.dts b/arch/arm/dts/sun7i-a20-primo73.dts
index 0658f82675..942a955309 100644
--- a/arch/arm/dts/sun7i-a20-primo73.dts
+++ b/arch/arm/dts/sun7i-a20-primo73.dts
@@ -62,16 +62,6 @@
};
soc at 01c00000 {
- mmc0: mmc at 01c0f000 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
- vmmc-supply = <®_vcc3v3>;
- bus-width = <4>;
- cd-gpios = <&pio 7 1 0>; /* PH1 */
- cd-inverted;
- status = "okay";
- };
-
usbphy: phy at 01c13400 {
usb2_vbus-supply = <®_usb2_vbus>;
status = "okay";
@@ -100,3 +90,13 @@
status = "okay";
};
};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 08/25] ARM: dts: sun7i: Add mmc0 node for Primo73 tablet
2018-07-16 8:19 ` [U-Boot] [PATCH 08/25] ARM: dts: sun7i: Add mmc0 node for Primo73 tablet Jagan Teki
@ 2018-07-16 9:40 ` Maxime Ripard
2018-07-16 10:03 ` Jagan Teki
0 siblings, 1 reply; 59+ messages in thread
From: Maxime Ripard @ 2018-07-16 9:40 UTC (permalink / raw)
To: u-boot
On Mon, Jul 16, 2018 at 01:49:39PM +0530, Jagan Teki wrote:
> Reuse mmc0 node from sun7i-a20.dtsi like other board
> dts files for Primo73 tablet dts file, and drop in dts
> mmc0 definition.
>
> Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
> arch/arm/dts/sun7i-a20-primo73.dts | 20 ++++++++++----------
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/dts/sun7i-a20-primo73.dts b/arch/arm/dts/sun7i-a20-primo73.dts
> index 0658f82675..942a955309 100644
> --- a/arch/arm/dts/sun7i-a20-primo73.dts
> +++ b/arch/arm/dts/sun7i-a20-primo73.dts
> @@ -62,16 +62,6 @@
> };
>
> soc at 01c00000 {
> - mmc0: mmc at 01c0f000 {
> - pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> - vmmc-supply = <®_vcc3v3>;
> - bus-width = <4>;
> - cd-gpios = <&pio 7 1 0>; /* PH1 */
> - cd-inverted;
> - status = "okay";
> - };
> -
> usbphy: phy at 01c13400 {
> usb2_vbus-supply = <®_usb2_vbus>;
> status = "okay";
> @@ -100,3 +90,13 @@
> status = "okay";
> };
> };
> +
> +&mmc0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + vmmc-supply = <®_vcc3v3>;
> + bus-width = <4>;
> + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> + cd-inverted;
> + status = "okay";
> +};
You're not adding the node, you're just moving it around.
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 08/25] ARM: dts: sun7i: Add mmc0 node for Primo73 tablet
2018-07-16 9:40 ` Maxime Ripard
@ 2018-07-16 10:03 ` Jagan Teki
2018-07-16 10:09 ` Chen-Yu Tsai
0 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 10:03 UTC (permalink / raw)
To: u-boot
On Mon, Jul 16, 2018 at 3:10 PM, Maxime Ripard
<maxime.ripard@bootlin.com> wrote:
> On Mon, Jul 16, 2018 at 01:49:39PM +0530, Jagan Teki wrote:
>> Reuse mmc0 node from sun7i-a20.dtsi like other board
>> dts files for Primo73 tablet dts file, and drop in dts
>> mmc0 definition.
>>
>> Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com>
>> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>> ---
>> arch/arm/dts/sun7i-a20-primo73.dts | 20 ++++++++++----------
>> 1 file changed, 10 insertions(+), 10 deletions(-)
>>
>> diff --git a/arch/arm/dts/sun7i-a20-primo73.dts b/arch/arm/dts/sun7i-a20-primo73.dts
>> index 0658f82675..942a955309 100644
>> --- a/arch/arm/dts/sun7i-a20-primo73.dts
>> +++ b/arch/arm/dts/sun7i-a20-primo73.dts
>> @@ -62,16 +62,6 @@
>> };
>>
>> soc at 01c00000 {
>> - mmc0: mmc at 01c0f000 {
>> - pinctrl-names = "default";
>> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
>> - vmmc-supply = <®_vcc3v3>;
>> - bus-width = <4>;
>> - cd-gpios = <&pio 7 1 0>; /* PH1 */
>> - cd-inverted;
>> - status = "okay";
>> - };
>> -
>> usbphy: phy at 01c13400 {
>> usb2_vbus-supply = <®_usb2_vbus>;
>> status = "okay";
>> @@ -100,3 +90,13 @@
>> status = "okay";
>> };
>> };
>> +
>> +&mmc0 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
>> + vmmc-supply = <®_vcc3v3>;
>> + bus-width = <4>;
>> + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
>> + cd-inverted;
>> + status = "okay";
>> +};
>
> You're not adding the node, you're just moving it around.
ie what I mentioned on the commit message. adding mmc0 node like other
board dts files and removing in dts mmc0 node definition.
^ permalink raw reply [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 08/25] ARM: dts: sun7i: Add mmc0 node for Primo73 tablet
2018-07-16 10:03 ` Jagan Teki
@ 2018-07-16 10:09 ` Chen-Yu Tsai
0 siblings, 0 replies; 59+ messages in thread
From: Chen-Yu Tsai @ 2018-07-16 10:09 UTC (permalink / raw)
To: u-boot
On Mon, Jul 16, 2018 at 6:03 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote:
> On Mon, Jul 16, 2018 at 3:10 PM, Maxime Ripard
> <maxime.ripard@bootlin.com> wrote:
>> On Mon, Jul 16, 2018 at 01:49:39PM +0530, Jagan Teki wrote:
>>> Reuse mmc0 node from sun7i-a20.dtsi like other board
>>> dts files for Primo73 tablet dts file, and drop in dts
>>> mmc0 definition.
>>>
>>> Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com>
>>> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>>> ---
>>> arch/arm/dts/sun7i-a20-primo73.dts | 20 ++++++++++----------
>>> 1 file changed, 10 insertions(+), 10 deletions(-)
>>>
>>> diff --git a/arch/arm/dts/sun7i-a20-primo73.dts b/arch/arm/dts/sun7i-a20-primo73.dts
>>> index 0658f82675..942a955309 100644
>>> --- a/arch/arm/dts/sun7i-a20-primo73.dts
>>> +++ b/arch/arm/dts/sun7i-a20-primo73.dts
>>> @@ -62,16 +62,6 @@
>>> };
>>>
>>> soc at 01c00000 {
>>> - mmc0: mmc at 01c0f000 {
>>> - pinctrl-names = "default";
>>> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
>>> - vmmc-supply = <®_vcc3v3>;
>>> - bus-width = <4>;
>>> - cd-gpios = <&pio 7 1 0>; /* PH1 */
>>> - cd-inverted;
>>> - status = "okay";
>>> - };
>>> -
>>> usbphy: phy at 01c13400 {
>>> usb2_vbus-supply = <®_usb2_vbus>;
>>> status = "okay";
>>> @@ -100,3 +90,13 @@
>>> status = "okay";
>>> };
>>> };
>>> +
>>> +&mmc0 {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
>>> + vmmc-supply = <®_vcc3v3>;
>>> + bus-width = <4>;
>>> + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
>>> + cd-inverted;
>>> + status = "okay";
>>> +};
>>
>> You're not adding the node, you're just moving it around.
>
> ie what I mentioned on the commit message. adding mmc0 node like other
> board dts files and removing in dts mmc0 node definition.
If you understand the device tree, you'll know that they are one and
the same. They compile down to the same node. Otherwise the original
pattern wouldn't work.
The commit message should read something more like:
xxx: Convert to DT label based syntax
In order to lessen the amount of duplication of the DT tree, ease the
new and follow the trend that prefers to use label based references
when overriding DTSI nodes, convert the board to this syntax
This was the commit message in a whole slew of patches that Maxime
did to convert all the sunxi device tree files in the kernel.
Better yet, just drop all these conversion patches and just sync up
to Linux 4.18-rc1.
ChenYu
^ permalink raw reply [flat|nested] 59+ messages in thread
* [U-Boot] [PATCH 09/25] ARM: dts: sun7i: Add mmc0 node for Ainol AW1
2018-07-16 8:19 [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Jagan Teki
` (7 preceding siblings ...)
2018-07-16 8:19 ` [U-Boot] [PATCH 08/25] ARM: dts: sun7i: Add mmc0 node for Primo73 tablet Jagan Teki
@ 2018-07-16 8:19 ` Jagan Teki
2018-07-16 8:19 ` [U-Boot] [PATCH 10/25] ARM: dts: sun7i: Add mmc0 node for Mele M5 Jagan Teki
` (16 subsequent siblings)
25 siblings, 0 replies; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 8:19 UTC (permalink / raw)
To: u-boot
Since SUN7I moved to DM_MMC, we need to have mmc node
in Ainol AW1 DT otherwise it will not probe.
Cc: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/dts/sun7i-a20-ainol-aw1.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/dts/sun7i-a20-ainol-aw1.dts b/arch/arm/dts/sun7i-a20-ainol-aw1.dts
index 57fe0066cb..3831adc88d 100644
--- a/arch/arm/dts/sun7i-a20-ainol-aw1.dts
+++ b/arch/arm/dts/sun7i-a20-ainol-aw1.dts
@@ -7,6 +7,9 @@
/dts-v1/;
#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "Ainol AW1";
@@ -21,6 +24,16 @@
};
};
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
--
2.17.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 10/25] ARM: dts: sun7i: Add mmc0 node for Mele M5
2018-07-16 8:19 [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Jagan Teki
` (8 preceding siblings ...)
2018-07-16 8:19 ` [U-Boot] [PATCH 09/25] ARM: dts: sun7i: Add mmc0 node for Ainol AW1 Jagan Teki
@ 2018-07-16 8:19 ` Jagan Teki
2018-07-16 8:19 ` [U-Boot] [PATCH 11/25] ARM: dts: sun7i: Add mmc0 node for Toptech BD1078 Jagan Teki
` (15 subsequent siblings)
25 siblings, 0 replies; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 8:19 UTC (permalink / raw)
To: u-boot
Since SUN7I moved to DM_MMC, we need to have mmc node
in Mele M5 DT otherwise it will not probe.
Cc: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/dts/sun7i-a20-m5.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/dts/sun7i-a20-m5.dts b/arch/arm/dts/sun7i-a20-m5.dts
index 00c3ffd323..8014ebc310 100644
--- a/arch/arm/dts/sun7i-a20-m5.dts
+++ b/arch/arm/dts/sun7i-a20-m5.dts
@@ -7,6 +7,8 @@
/dts-v1/;
#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "Mele M5";
@@ -41,6 +43,16 @@
};
};
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
&ohci0 {
status = "okay";
};
--
2.17.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 11/25] ARM: dts: sun7i: Add mmc0 node for Toptech BD1078
2018-07-16 8:19 [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Jagan Teki
` (9 preceding siblings ...)
2018-07-16 8:19 ` [U-Boot] [PATCH 10/25] ARM: dts: sun7i: Add mmc0 node for Mele M5 Jagan Teki
@ 2018-07-16 8:19 ` Jagan Teki
2018-07-16 8:19 ` [U-Boot] [PATCH 12/25] sunxi: A20: Enable DM_MMC Jagan Teki
` (14 subsequent siblings)
25 siblings, 0 replies; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 8:19 UTC (permalink / raw)
To: u-boot
Since SUN7I moved to DM_MMC, we need to have mmc node
in Toptech BD1078 DT otherwise it will not probe.
Cc: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/dts/sun7i-a20-yones-toptech-bd1078.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/dts/sun7i-a20-yones-toptech-bd1078.dts b/arch/arm/dts/sun7i-a20-yones-toptech-bd1078.dts
index f1fb97d3fb..89c8cf60b1 100644
--- a/arch/arm/dts/sun7i-a20-yones-toptech-bd1078.dts
+++ b/arch/arm/dts/sun7i-a20-yones-toptech-bd1078.dts
@@ -7,6 +7,9 @@
/dts-v1/;
#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Yones Toptech BD1078";
@@ -21,6 +24,16 @@
};
};
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
--
2.17.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 12/25] sunxi: A20: Enable DM_MMC
2018-07-16 8:19 [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Jagan Teki
` (10 preceding siblings ...)
2018-07-16 8:19 ` [U-Boot] [PATCH 11/25] ARM: dts: sun7i: Add mmc0 node for Toptech BD1078 Jagan Teki
@ 2018-07-16 8:19 ` Jagan Teki
2018-07-16 8:19 ` [U-Boot] [PATCH 13/25] mmc: sunxi: Add mmc, emmc H5/A64 compatible Jagan Teki
` (13 subsequent siblings)
25 siblings, 0 replies; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 8:19 UTC (permalink / raw)
To: u-boot
Enable DM_MMC for Allwinner A20 SoC.
Tested on A20-OLinuXino-LIME2.
Cc: Stefan Mavrodiev <stefan@olimex.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/mach-sunxi/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 678e33dd40..7d1184306f 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -180,6 +180,7 @@ config MACH_SUN7I
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
select DRAM_SUN4I
+ select DM_MMC if MMC
select PHY_SUN4I_USB
select SUNXI_GEN_SUN4I
select SUPPORT_SPL
--
2.17.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 13/25] mmc: sunxi: Add mmc, emmc H5/A64 compatible
2018-07-16 8:19 [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Jagan Teki
` (11 preceding siblings ...)
2018-07-16 8:19 ` [U-Boot] [PATCH 12/25] sunxi: A20: Enable DM_MMC Jagan Teki
@ 2018-07-16 8:19 ` Jagan Teki
2018-07-16 8:19 ` [U-Boot] [PATCH 14/25] sunxi: H3_H5: Enable DM_MMC Jagan Teki
` (12 subsequent siblings)
25 siblings, 0 replies; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 8:19 UTC (permalink / raw)
To: u-boot
Added H5, A64 compatible for mmc and emmc.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/mmc/sunxi_mmc.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index beeded50af..16e94cf4b7 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -687,6 +687,10 @@ static const struct udevice_id sunxi_mmc_ids[] = {
.data = (ulong)&sun4i_a10_cfg },
{ .compatible = "allwinner,sun7i-a20-mmc",
.data = (ulong)&sun7i_a20_cfg },
+ { .compatible = "allwinner,sun50i-a64-mmc",
+ .data = (ulong)&sun7i_a20_cfg },
+ { .compatible = "allwinner,sun50i-a64-emmc",
+ .data = (ulong)&sun7i_a20_cfg },
{ }
};
--
2.17.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 14/25] sunxi: H3_H5: Enable DM_MMC
2018-07-16 8:19 [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Jagan Teki
` (12 preceding siblings ...)
2018-07-16 8:19 ` [U-Boot] [PATCH 13/25] mmc: sunxi: Add mmc, emmc H5/A64 compatible Jagan Teki
@ 2018-07-16 8:19 ` Jagan Teki
2018-07-16 8:19 ` [U-Boot] [PATCH 15/25] sunxi: A64: " Jagan Teki
` (11 subsequent siblings)
25 siblings, 0 replies; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 8:19 UTC (permalink / raw)
To: u-boot
Enable DM_MMC for Allwinner H3/H5 SoCs.
Tested on
H3: BPI-M2+
H5: Orangepi pc2, prime, zero+2
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/mach-sunxi/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 7d1184306f..a1ee431700 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -127,6 +127,7 @@ endif
config MACH_SUNXI_H3_H5
bool
select DM_I2C
+ select DM_MMC if MMC
select PHY_SUN4I_USB
select SUNXI_DE2
select SUNXI_DRAM_DW
--
2.17.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 15/25] sunxi: A64: Enable DM_MMC
2018-07-16 8:19 [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Jagan Teki
` (13 preceding siblings ...)
2018-07-16 8:19 ` [U-Boot] [PATCH 14/25] sunxi: H3_H5: Enable DM_MMC Jagan Teki
@ 2018-07-16 8:19 ` Jagan Teki
2018-07-16 8:19 ` [U-Boot] [PATCH 16/25] ARM: dts: sun8i: Update A83T dts(i) files from Linux Jagan Teki
` (10 subsequent siblings)
25 siblings, 0 replies; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 8:19 UTC (permalink / raw)
To: u-boot
Enable DM_MMC for Allwinner A64 SoCs.
Tested on BPI-M64, Amarula A64-Relic
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/mach-sunxi/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index a1ee431700..3b790e39dd 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -268,6 +268,7 @@ config MACH_SUN50I
bool "sun50i (Allwinner A64)"
select ARM64
select DM_I2C
+ select DM_MMC if MMC
select PHY_SUN4I_USB
select SUNXI_DE2
select SUNXI_GEN_SUN6I
--
2.17.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 16/25] ARM: dts: sun8i: Update A83T dts(i) files from Linux
2018-07-16 8:19 [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Jagan Teki
` (14 preceding siblings ...)
2018-07-16 8:19 ` [U-Boot] [PATCH 15/25] sunxi: A64: " Jagan Teki
@ 2018-07-16 8:19 ` Jagan Teki
2018-07-16 8:19 ` [U-Boot] [PATCH 17/25] mmc: sunxi: Add A83T emmc compatible Jagan Teki
` (9 subsequent siblings)
25 siblings, 0 replies; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 8:19 UTC (permalink / raw)
To: u-boot
Update all A83T devicetree dtsi and dtsi files from Linux
with below commit:
commit 221cb9fd2ee3042689fe0e6613d0f34eb46a5af6
Author: Mylène Josserand <mylene.josserand@bootlin.com>
Date: Fri May 4 21:05:44 2018 +0200
ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC
Note: bananapi-m3 and cubietruck-plus board dts files has
usb_otg enabled in U-Boot which were not present in Linux.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/dts/axp81x.dtsi | 169 ++++
.../dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 195 +++-
arch/arm/dts/sun8i-a83t-bananapi-m3.dts | 298 +++++-
arch/arm/dts/sun8i-a83t-cubietruck-plus.dts | 322 ++++++-
arch/arm/dts/sun8i-a83t-tbs-a711.dts | 355 ++++++-
arch/arm/dts/sun8i-a83t.dtsi | 885 ++++++++++++++++--
include/dt-bindings/clock/sun8i-a83t-ccu.h | 140 +++
include/dt-bindings/reset/sun8i-a83t-ccu.h | 98 ++
8 files changed, 2382 insertions(+), 80 deletions(-)
create mode 100644 arch/arm/dts/axp81x.dtsi
create mode 100644 include/dt-bindings/clock/sun8i-a83t-ccu.h
create mode 100644 include/dt-bindings/reset/sun8i-a83t-ccu.h
diff --git a/arch/arm/dts/axp81x.dtsi b/arch/arm/dts/axp81x.dtsi
new file mode 100644
index 0000000000..043c717dce
--- /dev/null
+++ b/arch/arm/dts/axp81x.dtsi
@@ -0,0 +1,169 @@
+/*
+ * Copyright 2017 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/* AXP813/818 Integrated Power Management Chip */
+
+&axp81x {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ axp_adc: adc {
+ compatible = "x-powers,axp813-adc";
+ #io-channel-cells = <1>;
+ };
+
+ axp_gpio: gpio {
+ compatible = "x-powers,axp813-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio0_ldo: gpio0-ldo {
+ pins = "GPIO0";
+ function = "ldo";
+ };
+
+ gpio1_ldo: gpio1-ldo {
+ pins = "GPIO1";
+ function = "ldo";
+ };
+ };
+
+ battery_power_supply: battery-power-supply {
+ compatible = "x-powers,axp813-battery-power-supply";
+ status = "disabled";
+ };
+
+ regulators {
+ /* Default work frequency for buck regulators */
+ x-powers,dcdc-freq = <3000>;
+
+ reg_dcdc1: dcdc1 {
+ };
+
+ reg_dcdc2: dcdc2 {
+ };
+
+ reg_dcdc3: dcdc3 {
+ };
+
+ reg_dcdc4: dcdc4 {
+ };
+
+ reg_dcdc5: dcdc5 {
+ };
+
+ reg_dcdc6: dcdc6 {
+ };
+
+ reg_dcdc7: dcdc7 {
+ };
+
+ reg_aldo1: aldo1 {
+ };
+
+ reg_aldo2: aldo2 {
+ };
+
+ reg_aldo3: aldo3 {
+ };
+
+ reg_dldo1: dldo1 {
+ };
+
+ reg_dldo2: dldo2 {
+ };
+
+ reg_dldo3: dldo3 {
+ };
+
+ reg_dldo4: dldo4 {
+ };
+
+ reg_eldo1: eldo1 {
+ };
+
+ reg_eldo2: eldo2 {
+ };
+
+ reg_eldo3: eldo3 {
+ };
+
+ reg_fldo1: fldo1 {
+ };
+
+ reg_fldo2: fldo2 {
+ };
+
+ reg_fldo3: fldo3 {
+ };
+
+ reg_ldo_io0: ldo-io0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio0_ldo>;
+ /* Disable by default to avoid conflicts with GPIO */
+ status = "disabled";
+ };
+
+ reg_ldo_io1: ldo-io1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio1_ldo>;
+ /* Disable by default to avoid conflicts with GPIO */
+ status = "disabled";
+ };
+
+ reg_rtc_ldo: rtc-ldo {
+ /* RTC_LDO is a fixed, always-on regulator */
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ reg_sw: sw {
+ };
+
+ reg_drivevbus: drivevbus {
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
index c8495d7624..36ecebaff3 100644
--- a/arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
+++ b/arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
@@ -44,6 +44,8 @@
/dts-v1/;
#include "sun8i-a83t.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
/ {
model = "Allwinner A83T H8Homlet Proto Dev Board v2.0";
compatible = "allwinner,h8homlet-v2", "allwinner,sun8i-a83t";
@@ -55,22 +57,213 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ reg_usb0_vbus: reg-usb0-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
+ };
+
+ reg_usb1_vbus: reg-usb1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
+ };
};
&ehci0 {
status = "okay";
};
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <®_dcdc1>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ bus-width = <4>;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_emmc_pins>;
+ vmmc-supply = <®_dcdc1>;
+ vqmmc-supply = <®_dcdc1>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
&ohci0 {
status = "okay";
};
+&r_rsb {
+ status = "okay";
+
+ axp81x: pmic at 3a3 {
+ compatible = "x-powers,axp818", "x-powers,axp813";
+ reg = <0x3a3>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ eldoin-supply = <®_dcdc1>;
+ swin-supply = <®_dcdc1>;
+ };
+
+ ac100: codec at e89 {
+ compatible = "x-powers,ac100";
+ reg = <0xe89>;
+
+ ac100_codec: codec {
+ compatible = "x-powers,ac100-codec";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */
+ #clock-cells = <0>;
+ clock-output-names = "4M_adda";
+ };
+
+ ac100_rtc: rtc {
+ compatible = "x-powers,ac100-rtc";
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&ac100_codec>;
+ #clock-cells = <1>;
+ clock-output-names = "cko1_rtc",
+ "cko2_rtc",
+ "cko3_rtc";
+ };
+ };
+};
+
+#include "axp81x.dtsi"
+
+®_aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-1v8";
+};
+
+®_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "dram-pll";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpua";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpub";
+};
+
+®_dcdc4 {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-gpu";
+};
+
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dcdc6 {
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vdd-sys";
+};
+
+®_dldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-mipi";
+};
+
+®_dldo4 {
+ /*
+ * The PHY requires 20ms after all voltages are applied until core
+ * logic is ready and 30ms after the reset pin is de-asserted.
+ * Set a 100ms delay to account for PMIC ramp time and board traces.
+ */
+ regulator-enable-ramp-delay = <100000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-ephy";
+};
+
+®_fldo1 {
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd12-hsic";
+};
+
+®_fldo2 {
+ /*
+ * Despite the embedded CPUs core not being used in any way,
+ * this must remain on or the system will hang.
+ */
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpus";
+};
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+®_sw {
+ regulator-name = "vcc-wifi";
+};
+
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_b>;
+ pinctrl-0 = <&uart0_pb_pins>;
+ status = "okay";
+};
+
+&usbphy {
+ usb0_vbus-supply = <®_usb0_vbus>;
+ usb1_vbus-supply = <®_usb1_vbus>;
status = "okay";
};
&usb_otg {
+ dr_mode = "host";
status = "okay";
};
diff --git a/arch/arm/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/dts/sun8i-a83t-bananapi-m3.dts
index dfc16a0272..eaff6fa401 100644
--- a/arch/arm/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/dts/sun8i-a83t-bananapi-m3.dts
@@ -1,6 +1,7 @@
/*
- * Copyright 2015 Vishnu Patekar
- * Vishnu Patekar <vishnupatekar0510@gmail.com>
+ * Copyright 2017 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <wens@csie.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@@ -44,29 +45,316 @@
/dts-v1/;
#include "sun8i-a83t.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
/ {
- model = "Allwinner A83T BananaPi M3 Board v1.2";
- compatible = "bananapi,m3v1.2", "allwinner,sun8i-a83t";
+ model = "Banana Pi BPI-M3";
+ compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ blue {
+ label = "bananapi-m3:blue:usr";
+ gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ green {
+ label = "bananapi-m3:green:usr";
+ gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ reg_usb1_vbus: reg-usb1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&ac100_rtc 1>;
+ clock-names = "ext_clock";
+ /* The WiFi low power clock must be 32768 Hz */
+ assigned-clocks = <&ac100_rtc 1>;
+ assigned-clock-rates = <32768>;
+ /* enables internal regulator and de-asserts reset */
+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
+ };
+};
+
+&de {
+ status = "okay";
};
&ehci0 {
+ /* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */
status = "okay";
+
+ /* TODO GL830 USB-to-SATA bridge downstream w/ GPIO power controls */
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <®_sw>;
+ phy-handle = <&rgmii_phy>;
+ phy-mode = "rgmii";
+ allwinner,rx-delay-ps = <700>;
+ allwinner,tx-delay-ps = <700>;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&mdio {
+ rgmii_phy: ethernet-phy at 1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <®_dcdc1>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_dldo1>;
+ vqmmc-supply = <®_dldo1>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: wifi at 1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "host-wake";
+ };
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_emmc_pins>;
+ vmmc-supply = <®_dcdc1>;
+ vqmmc-supply = <®_dcdc1>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&r_rsb {
+ status = "okay";
+
+ axp81x: pmic at 3a3 {
+ compatible = "x-powers,axp813";
+ reg = <0x3a3>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ eldoin-supply = <®_dcdc1>;
+ fldoin-supply = <®_dcdc5>;
+ swin-supply = <®_dcdc1>;
+ x-powers,drive-vbus-en;
+ };
+
+ ac100: codec at e89 {
+ compatible = "x-powers,ac100";
+ reg = <0xe89>;
+
+ ac100_codec: codec {
+ compatible = "x-powers,ac100-codec";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */
+ #clock-cells = <0>;
+ clock-output-names = "4M_adda";
+ };
+
+ ac100_rtc: rtc {
+ compatible = "x-powers,ac100-rtc";
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&ac100_codec>;
+ #clock-cells = <1>;
+ clock-output-names = "cko1_rtc",
+ "cko2_rtc",
+ "cko3_rtc";
+ };
+ };
+};
+
+#include "axp81x.dtsi"
+
+®_aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-1v8";
+};
+
+®_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "dram-pll";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_dcdc1 {
+ /* schematics says 3.1V but FEX file says 3.3V */
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpua";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpub";
+};
+
+®_dcdc4 {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-gpu";
+};
+
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dcdc6 {
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vdd-sys";
+};
+
+®_dldo1 {
+ /*
+ * This powers both the WiFi/BT module's main power, I/O supply,
+ * and external pull-ups on all the data lines. It should be set
+ * to the same voltage as the I/O supply (DCDC1 in this case) to
+ * avoid any leakage or mismatch.
+ */
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+®_dldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-name = "vcc-pd";
+};
+
+®_drivevbus {
+ regulator-name = "usb0-vbus";
+ status = "okay";
+};
+
+®_fldo1 {
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd12-hsic";
+};
+
+®_fldo2 {
+ /*
+ * Despite the embedded CPUs core not being used in any way,
+ * this must remain on or the system will hang.
+ */
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpus";
+};
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+®_sw {
+ /*
+ * The PHY requires 20ms after all voltages
+ * are applied until core logic is ready and
+ * 30ms after the reset pin is de-asserted.
+ * Set a 100ms delay to account for PMIC
+ * ramp time and board traces.
+ */
+ regulator-enable-ramp-delay = <100000>;
+ regulator-name = "vcc-ephy";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_b>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&usb_otg {
status = "okay";
};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts
index 8437c8f59e..5dba4fc310 100644
--- a/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts
+++ b/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts
@@ -45,33 +45,353 @@
/dts-v1/;
#include "sun8i-a83t.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
/ {
model = "Cubietech Cubietruck Plus";
compatible = "cubietech,cubietruck-plus", "allwinner,sun8i-a83t";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
+
+ leds {
+ compatible = "gpio-leds";
+
+ blue {
+ label = "cubietruck-plus:blue:usr";
+ gpios = <&pio 3 25 GPIO_ACTIVE_HIGH>; /* PD25 */
+ };
+
+ orange {
+ label = "cubietruck-plus:orange:usr";
+ gpios = <&pio 3 26 GPIO_ACTIVE_HIGH>; /* PD26 */
+ };
+
+ white {
+ label = "cubietruck-plus:white:usr";
+ gpios = <&pio 3 27 GPIO_ACTIVE_HIGH>; /* PD27 */
+ };
+
+ green {
+ label = "cubietruck-plus:green:usr";
+ gpios = <&pio 4 4 GPIO_ACTIVE_HIGH>; /* PE4 */
+ };
+ };
+
+ usb-hub {
+ /* I2C is not connected */
+ compatible = "smsc,usb3503";
+ initial-mode = <1>; /* initialize in HUB mode */
+ disabled-ports = <1>;
+ intn-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ reset-gpios = <&pio 4 16 GPIO_ACTIVE_HIGH>; /* PE16 */
+ connect-gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */
+ refclk-frequency = <19200000>;
+ };
+
+ reg_usb1_vbus: reg-usb1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pio 3 29 GPIO_ACTIVE_HIGH>; /* PD29 */
+ };
+
+ reg_usb2_vbus: reg-usb2-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb2-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "On-board SPDIF";
+
+ simple-audio-card,cpu {
+ sound-dai = <&spdif>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&spdif_out>;
+ };
+ };
+
+ spdif_out: spdif-out {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&ac100_rtc 1>;
+ clock-names = "ext_clock";
+ /* The WiFi low power clock must be 32768 Hz */
+ assigned-clocks = <&ac100_rtc 1>;
+ assigned-clock-rates = <32768>;
+ /* enables internal regulator and de-asserts reset */
+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
+ };
};
&ehci0 {
+ /* GL830 USB-to-SATA bridge here */
status = "okay";
};
&ehci1 {
+ /* USB3503 HSIC USB 2.0 hub here */
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <®_dldo4>;
+ phy-handle = <&rgmii_phy>;
+ phy-mode = "rgmii";
+ status = "okay";
+};
+
+&mdio {
+ rgmii_phy: ethernet-phy at 1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <®_dcdc1>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_dcdc1>;
+ vqmmc-supply = <®_sw>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_emmc_pins>;
+ vmmc-supply = <®_dcdc1>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&r_rsb {
+ status = "okay";
+
+ axp81x: pmic at 3a3 {
+ compatible = "x-powers,axp818", "x-powers,axp813";
+ reg = <0x3a3>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ eldoin-supply = <®_dcdc1>;
+ swin-supply = <®_dcdc1>;
+ x-powers,drive-vbus-en;
+ };
+
+ ac100: codec at e89 {
+ compatible = "x-powers,ac100";
+ reg = <0xe89>;
+
+ ac100_codec: codec {
+ compatible = "x-powers,ac100-codec";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */
+ #clock-cells = <0>;
+ clock-output-names = "4M_adda";
+ };
+
+ ac100_rtc: rtc {
+ compatible = "x-powers,ac100-rtc";
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&ac100_codec>;
+ #clock-cells = <1>;
+ clock-output-names = "cko1_rtc",
+ "cko2_rtc",
+ "cko3_rtc";
+ };
+ };
+};
+
+#include "axp81x.dtsi"
+
+®_aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-1v8";
+};
+
+®_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "dram-pll";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_dcdc1 {
+ /*
+ * The schematics say this should be 3.3V, but the FEX file says
+ * it should be 3V. The latter makes sense, as the WiFi module's
+ * I/O is indirectly powered from DCDC1, through SW. It is rated
+ * at 2.98V maximum.
+ */
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-3v";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpua";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpub";
+};
+
+®_dcdc4 {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-gpu";
+};
+
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dcdc6 {
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vdd-sys";
+};
+
+®_dldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "dp-pwr";
+};
+
+®_dldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-name = "ephy-io";
+};
+
+®_dldo4 {
+ /*
+ * The PHY requires 20ms after all voltages are applied until core
+ * logic is ready and 30ms after the reset pin is de-asserted.
+ * Set a 100ms delay to account for PMIC ramp time and board traces.
+ */
+ regulator-enable-ramp-delay = <100000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "ephy";
+};
+
+®_drivevbus {
+ regulator-name = "usb0-vbus";
+ status = "okay";
+};
+
+®_eldo1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "dp-bridge-1";
+};
+
+®_eldo2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "dp-bridge-2";
+};
+
+®_fldo1 {
+ /* TODO should be handled by USB PHY */
+ regulator-always-on;
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd12-hsic";
+};
+
+®_fldo2 {
+ /*
+ * Despite the embedded CPUs core not being used in any way,
+ * this must remain on or the system will hang.
+ */
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpus";
+};
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+®_sw {
+ regulator-name = "vcc-wifi-io";
+};
+
+&spdif {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_b>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&usb_otg {
status = "okay";
};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/dts/sun8i-a83t-tbs-a711.dts
index 80e8b1cc90..1537ce148c 100644
--- a/arch/arm/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/dts/sun8i-a83t-tbs-a711.dts
@@ -1,6 +1,6 @@
/*
- * Copyright 2017 Ondřej Jirman
- * Ondřej Jirman <megous@megous.com>
+ * Copyright (C) 2017 Touchless Biometric Systems AG
+ * Tomas Novotny <tomas@novotny.cz>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@@ -44,33 +44,380 @@
/dts-v1/;
#include "sun8i-a83t.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+
/ {
model = "TBS A711 Tablet";
compatible = "tbs-biometrics,a711", "allwinner,sun8i-a83t";
aliases {
serial0 = &uart0;
+ serial1 = &uart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+ enable-gpios = <&pio 3 29 GPIO_ACTIVE_HIGH>;
+
+ brightness-levels = <0 1 2 4 8 16 32 64 128 255>;
+ default-brightness-level = <9>;
+ };
+
+ panel {
+ compatible = "tbs,a711-panel", "panel-lvds";
+ backlight = <&backlight>;
+ power-supply = <®_sw>;
+
+ width-mm = <153>;
+ height-mm = <90>;
+ data-mapping = "vesa-24";
+
+ panel-timing {
+ /* 1024x600 @60Hz */
+ clock-frequency = <52000000>;
+ hactive = <1024>;
+ vactive = <600>;
+ hsync-len = <20>;
+ hfront-porch = <180>;
+ hback-porch = <160>;
+ vfront-porch = <12>;
+ vback-porch = <23>;
+ vsync-len = <5>;
+ };
+
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <&tcon0_out_lcd>;
+ };
+ };
+ };
+
+ reg_vbat: reg-vbat {
+ compatible = "regulator-fixed";
+ regulator-name = "vbat";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ };
+
+ reg_vmain: reg-vmain {
+ compatible = "regulator-fixed";
+ regulator-name = "vmain";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <®_vbat>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
+
+ /*
+ * This is actually Bluetooth's clock, but we have to
+ * hook it up somewheere
+ */
+ clocks = <&ac100_rtc 1>;
+ clock-names = "ext_clock";
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu100 {
+ cpu-supply = <®_dcdc3>;
+};
+
+&de {
+ status = "okay";
};
+/*
+ * An USB-2 hub is connected here, which also means we don't need to
+ * enable the OHCI controller.
+ */
&ehci0 {
status = "okay";
};
-&ohci0 {
+/*
+ * There's a modem connected here that needs to be initialised before
+ * being able to be enumerated.
+ */
+&ehci1 {
+ status = "okay";
+};
+
+&mmc0 {
+ vmmc-supply = <®_dcdc1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&mmc1 {
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ vmmc-supply = <®_dldo1>;
+ vqmmc-supply = <®_dldo1>;
+ non-removable;
+ wakeup-source;
+ status = "okay";
+
+ brcmf: wifi at 1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 WL_WAKE_UP */
+ interrupt-names = "host-wake";
+ };
+};
+
+&mmc2 {
+ pinctrl-0 = <&mmc2_8bit_emmc_pins>;
+ pinctrl-names = "default";
+ vmmc-supply = <®_dcdc1>;
+ vqmmc-supply = <®_dcdc1>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pin>;
+ status = "okay";
+};
+
+&r_rsb {
+ status = "okay";
+
+ axp81x: pmic at 3a3 {
+ compatible = "x-powers,axp813";
+ reg = <0x3a3>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ swin-supply = <®_dcdc1>;
+ x-powers,drive-vbus-en;
+ };
+
+ ac100: codec at e89 {
+ compatible = "x-powers,ac100";
+ reg = <0xe89>;
+
+ ac100_codec: codec {
+ compatible = "x-powers,ac100-codec";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 12 IRQ_TYPE_LEVEL_LOW>; /* PL12 */
+ #clock-cells = <0>;
+ clock-output-names = "4M_adda";
+ };
+
+ ac100_rtc: rtc {
+ compatible = "x-powers,ac100-rtc";
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&ac100_codec>;
+ #clock-cells = <1>;
+ clock-output-names = "cko1_rtc",
+ "cko2_rtc",
+ "cko3_rtc";
+ };
+ };
+
+};
+
+#include "axp81x.dtsi"
+
+&battery_power_supply {
+ status = "okay";
+};
+
+®_aldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-1.8";
+};
+
+®_aldo2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-name = "vdd-drampll";
+};
+
+®_aldo3 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ regulator-name = "avcc";
+};
+
+®_dcdc1 {
+ regulator-min-microvolt = <3100000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-always-on;
+ regulator-name = "vcc-io";
+};
+
+®_dcdc2 {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-name = "vdd-cpu-A";
+};
+
+®_dcdc3 {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-name = "vdd-cpu-B";
+};
+
+®_dcdc4 {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-gpu";
+};
+
+®_dcdc5 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-name = "vcc-dram";
+};
+
+®_dcdc6 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-always-on;
+ regulator-name = "vdd-sys";
+};
+
+®_dldo1 {
+ regulator-min-microvolt = <3100000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-name = "vcc-wifi-io";
+};
+
+®_dldo2 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <4200000>;
+ regulator-name = "vcc-mipi";
+};
+
+®_dldo3 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "vdd-csi";
+};
+
+®_dldo4 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "avdd-csi";
+};
+
+®_drivevbus {
+ regulator-name = "usb0-vbus";
status = "okay";
};
+®_eldo1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "dvdd-csi-r";
+};
+
+®_eldo2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-dsi";
+};
+
+®_eldo3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "dvdd-csi-f";
+};
+
+®_fldo1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-hsic";
+};
+
+®_fldo2 {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-name = "vdd-cpus";
+};
+
+®_ldo_io0 {
+ regulator-min-microvolt = <3100000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-name = "vcc-ctp";
+ status = "okay";
+};
+
+®_ldo_io1 {
+ regulator-min-microvolt = <3100000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-name = "vcc-vb";
+ status = "okay";
+};
+
+®_sw {
+ regulator-min-microvolt = <3100000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-name = "vcc-lcd";
+};
+
+&tcon0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_lvds_pins>;
+};
+
+&tcon0_out {
+ tcon0_out_lcd: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&panel_input>;
+ };
+};
+
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_b>;
+ pinctrl-0 = <&uart0_pb_pins>;
+ status = "okay";
+};
+
+/* There's the BT part of the AP6210 connected to that UART */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
status = "okay";
};
&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
+ usb0_vbus-supply = <®_drivevbus>;
+ usb1_vbus_supply = <®_vmain>;
+ usb2_vbus_supply = <®_vmain>;
status = "okay";
};
diff --git a/arch/arm/dts/sun8i-a83t.dtsi b/arch/arm/dts/sun8i-a83t.dtsi
index 2953e0fdac..2be23d6009 100644
--- a/arch/arm/dts/sun8i-a83t.dtsi
+++ b/arch/arm/dts/sun8i-a83t.dtsi
@@ -40,67 +40,99 @@
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
-
*/
-#include "skeleton.dtsi"
-
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/clock/sun8i-a83t-ccu.h>
+#include <dt-bindings/clock/sun8i-de2.h>
+#include <dt-bindings/clock/sun8i-r-ccu.h>
+#include <dt-bindings/reset/sun8i-a83t-ccu.h>
+#include <dt-bindings/reset/sun8i-de2.h>
+#include <dt-bindings/reset/sun8i-r-ccu.h>
/ {
interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
- cpu at 0 {
+ cpu0: cpu at 0 {
+ clocks = <&ccu CLK_C0CPUX>;
+ clock-names = "cpu";
compatible = "arm,cortex-a7";
device_type = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
+ cci-control-port = <&cci_control0>;
+ enable-method = "allwinner,sun8i-a83t-smp";
reg = <0>;
};
cpu at 1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
+ cci-control-port = <&cci_control0>;
+ enable-method = "allwinner,sun8i-a83t-smp";
reg = <1>;
};
cpu at 2 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
+ cci-control-port = <&cci_control0>;
+ enable-method = "allwinner,sun8i-a83t-smp";
reg = <2>;
};
cpu at 3 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
+ cci-control-port = <&cci_control0>;
+ enable-method = "allwinner,sun8i-a83t-smp";
reg = <3>;
};
- cpu at 100 {
+ cpu100: cpu at 100 {
+ clocks = <&ccu CLK_C1CPUX>;
+ clock-names = "cpu";
compatible = "arm,cortex-a7";
device_type = "cpu";
+ operating-points-v2 = <&cpu1_opp_table>;
+ cci-control-port = <&cci_control1>;
+ enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x100>;
};
cpu at 101 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ operating-points-v2 = <&cpu1_opp_table>;
+ cci-control-port = <&cci_control1>;
+ enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x101>;
};
cpu at 102 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ operating-points-v2 = <&cpu1_opp_table>;
+ cci-control-port = <&cci_control1>;
+ enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x102>;
};
cpu at 103 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ operating-points-v2 = <&cpu1_opp_table>;
+ cci-control-port = <&cci_control1>;
+ enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x103>;
};
};
@@ -123,6 +155,7 @@
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
+ clock-accuracy = <50000>;
clock-output-names = "osc24M";
};
@@ -148,48 +181,575 @@
};
};
+ de: display-engine {
+ compatible = "allwinner,sun8i-a83t-display-engine";
+ allwinner,pipelines = <&mixer0>, <&mixer1>;
+ status = "disabled";
+ };
+
+ memory {
+ reg = <0x40000000 0x80000000>;
+ device_type = "memory";
+ };
+
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-720000000 {
+ opp-hz = /bits/ 64 <720000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-864000000 {
+ opp-hz = /bits/ 64 <864000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-912000000 {
+ opp-hz = /bits/ 64 <912000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1128000000 {
+ opp-hz = /bits/ 64 <1128000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+ };
+
+ cpu1_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-720000000 {
+ opp-hz = /bits/ 64 <720000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-864000000 {
+ opp-hz = /bits/ 64 <864000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-912000000 {
+ opp-hz = /bits/ 64 <912000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1128000000 {
+ opp-hz = /bits/ 64 <1128000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
- pio: pinctrl at 01c20800 {
+ display_clocks: clock at 1000000 {
+ compatible = "allwinner,sun8i-a83t-de2-clk";
+ reg = <0x01000000 0x100000>;
+ clocks = <&ccu CLK_PLL_DE>,
+ <&ccu CLK_BUS_DE>;
+ clock-names = "mod",
+ "bus";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mixer0: mixer at 1100000 {
+ compatible = "allwinner,sun8i-a83t-de2-mixer-0";
+ reg = <0x01100000 0x100000>;
+ clocks = <&display_clocks CLK_BUS_MIXER0>,
+ <&display_clocks CLK_MIXER0>;
+ clock-names = "bus",
+ "mod";
+ resets = <&display_clocks RST_MIXER0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer0_out: port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mixer0_out_tcon0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_in_mixer0>;
+ };
+ };
+ };
+ };
+
+ mixer1: mixer at 1200000 {
+ compatible = "allwinner,sun8i-a83t-de2-mixer-1";
+ reg = <0x01200000 0x100000>;
+ clocks = <&display_clocks CLK_BUS_MIXER1>,
+ <&display_clocks CLK_MIXER1>;
+ clock-names = "bus",
+ "mod";
+ resets = <&display_clocks RST_WB>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer1_out: port at 1 {
+ reg = <1>;
+
+ mixer1_out_tcon1: endpoint {
+ remote-endpoint = <&tcon1_in_mixer1>;
+ };
+ };
+ };
+ };
+
+ cpucfg at 1700000 {
+ compatible = "allwinner,sun8i-a83t-cpucfg";
+ reg = <0x01700000 0x400>;
+ };
+
+ cci at 1790000 {
+ compatible = "arm,cci-400";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x01790000 0x10000>;
+ ranges = <0x0 0x01790000 0x10000>;
+
+ cci_control0: slave-if at 4000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x4000 0x1000>;
+ };
+
+ cci_control1: slave-if at 5000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x5000 0x1000>;
+ };
+
+ pmu at 9000 {
+ compatible = "arm,cci-400-pmu,r1";
+ reg = <0x9000 0x5000>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ syscon: syscon at 1c00000 {
+ compatible = "allwinner,sun8i-a83t-system-controller",
+ "syscon";
+ reg = <0x01c00000 0x1000>;
+ };
+
+ dma: dma-controller at 1c02000 {
+ compatible = "allwinner,sun8i-a83t-dma";
+ reg = <0x01c02000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_DMA>;
+ resets = <&ccu RST_BUS_DMA>;
+ #dma-cells = <1>;
+ };
+
+ tcon0: lcd-controller at 1c0c000 {
+ compatible = "allwinner,sun8i-a83t-tcon-lcd";
+ reg = <0x01c0c000 0x1000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
+ clock-names = "ahb", "tcon-ch0";
+ clock-output-names = "tcon-pixel-clock";
+ resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
+ reset-names = "lcd", "lvds";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon0_in_mixer0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&mixer0_out_tcon0>;
+ };
+ };
+
+ tcon0_out: port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+
+ tcon1: lcd-controller at 1c0d000 {
+ compatible = "allwinner,sun8i-a83t-tcon-tv";
+ reg = <0x01c0d000 0x1000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
+ clock-names = "ahb", "tcon-ch1";
+ resets = <&ccu RST_BUS_TCON1>;
+ reset-names = "lcd";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon1_in: port at 0 {
+ reg = <0>;
+
+ tcon1_in_mixer1: endpoint {
+ remote-endpoint = <&mixer1_out_tcon1>;
+ };
+ };
+
+ tcon1_out: port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon1_out_hdmi: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&hdmi_in_tcon1>;
+ };
+ };
+ };
+ };
+
+ mmc0: mmc at 1c0f000 {
+ compatible = "allwinner,sun8i-a83t-mmc",
+ "allwinner,sun7i-a20-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC0>,
+ <&ccu CLK_MMC0>,
+ <&ccu CLK_MMC0_OUTPUT>,
+ <&ccu CLK_MMC0_SAMPLE>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ccu RST_BUS_MMC0>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc at 1c10000 {
+ compatible = "allwinner,sun8i-a83t-mmc",
+ "allwinner,sun7i-a20-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC1>,
+ <&ccu CLK_MMC1>,
+ <&ccu CLK_MMC1_OUTPUT>,
+ <&ccu CLK_MMC1_SAMPLE>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ccu RST_BUS_MMC1>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc at 1c11000 {
+ compatible = "allwinner,sun8i-a83t-emmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC2>,
+ <&ccu CLK_MMC2>,
+ <&ccu CLK_MMC2_OUTPUT>,
+ <&ccu CLK_MMC2_SAMPLE>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ccu RST_BUS_MMC2>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sid: eeprom at 1c14000 {
+ compatible = "allwinner,sun8i-a83t-sid";
+ reg = <0x1c14000 0x400>;
+ };
+
+ usb_otg: usb at 1c19000 {
+ compatible = "allwinner,sun8i-a83t-musb",
+ "allwinner,sun8i-a33-musb";
+ reg = <0x01c19000 0x0400>;
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mc";
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ extcon = <&usbphy 0>;
+ status = "disabled";
+ };
+
+ usbphy: phy at 1c19400 {
+ compatible = "allwinner,sun8i-a83t-usb-phy";
+ reg = <0x01c19400 0x10>,
+ <0x01c1a800 0x14>,
+ <0x01c1b800 0x14>;
+ reg-names = "phy_ctrl",
+ "pmu1",
+ "pmu2";
+ clocks = <&ccu CLK_USB_PHY0>,
+ <&ccu CLK_USB_PHY1>,
+ <&ccu CLK_USB_HSIC>,
+ <&ccu CLK_USB_HSIC_12M>;
+ clock-names = "usb0_phy",
+ "usb1_phy",
+ "usb2_phy",
+ "usb2_hsic_12M";
+ resets = <&ccu RST_USB_PHY0>,
+ <&ccu RST_USB_PHY1>,
+ <&ccu RST_USB_HSIC>;
+ reset-names = "usb0_reset",
+ "usb1_reset",
+ "usb2_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ehci0: usb at 1c1a000 {
+ compatible = "allwinner,sun8i-a83t-ehci",
+ "generic-ehci";
+ reg = <0x01c1a000 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI0>;
+ resets = <&ccu RST_BUS_EHCI0>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci0: usb at 1c1a400 {
+ compatible = "allwinner,sun8i-a83t-ohci",
+ "generic-ohci";
+ reg = <0x01c1a400 0x100>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci1: usb at 1c1b000 {
+ compatible = "allwinner,sun8i-a83t-ehci",
+ "generic-ehci";
+ reg = <0x01c1b000 0x100>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI1>;
+ resets = <&ccu RST_BUS_EHCI1>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ccu: clock at 1c20000 {
+ compatible = "allwinner,sun8i-a83t-ccu";
+ reg = <0x01c20000 0x400>;
+ clocks = <&osc24M>, <&osc16Md512>;
+ clock-names = "hosc", "losc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pio: pinctrl at 1c20800 {
compatible = "allwinner,sun8i-a83t-pinctrl";
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x01c20800 0x400>;
- clocks = <&osc24M>;
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
+ clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
#gpio-cells = <3>;
- mmc0_pins_a: mmc0 at 0 {
- allwinner,pins = "PF0", "PF1", "PF2",
- "PF3", "PF4", "PF5";
- allwinner,function = "mmc0";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ emac_rgmii_pins: emac-rgmii-pins {
+ pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
+ "PD11", "PD12", "PD13", "PD14", "PD18",
+ "PD19", "PD21", "PD22", "PD23";
+ function = "gmac";
+ /*
+ * data lines in RGMII mode use DDR mode
+ * and need a higher signal drive strength
+ */
+ drive-strength = <40>;
+ };
+
+ hdmi_pins: hdmi-pins {
+ pins = "PH6", "PH7", "PH8";
+ function = "hdmi";
+ };
+
+ i2c0_pins: i2c0-pins {
+ pins = "PH0", "PH1";
+ function = "i2c0";
+ };
+
+ i2c1_pins: i2c1-pins {
+ pins = "PH2", "PH3";
+ function = "i2c1";
+ };
+
+ i2c2_ph_pins: i2c2-ph-pins {
+ pins = "PH4", "PH5";
+ function = "i2c2";
+ };
+
+ i2s1_pins: i2s1-pins {
+ /* I2S1 does not have external MCLK pin */
+ pins = "PG10", "PG11", "PG12", "PG13";
+ function = "i2s1";
+ };
+
+ lcd_lvds_pins: lcd-lvds-pins {
+ pins = "PD18", "PD19", "PD20", "PD21", "PD22",
+ "PD23", "PD24", "PD25", "PD26", "PD27";
+ function = "lvds0";
+ };
+
+ mmc0_pins: mmc0-pins {
+ pins = "PF0", "PF1", "PF2",
+ "PF3", "PF4", "PF5";
+ function = "mmc0";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ mmc1_pins: mmc1-pins {
+ pins = "PG0", "PG1", "PG2",
+ "PG3", "PG4", "PG5";
+ function = "mmc1";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
+ pins = "PC5", "PC6", "PC8", "PC9",
+ "PC10", "PC11", "PC12", "PC13",
+ "PC14", "PC15", "PC16";
+ function = "mmc2";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ pwm_pin: pwm-pin {
+ pins = "PD28";
+ function = "pwm";
+ };
+
+ spdif_tx_pin: spdif-tx-pin {
+ pins = "PE18";
+ function = "spdif";
+ };
+
+ uart0_pb_pins: uart0-pb-pins {
+ pins = "PB9", "PB10";
+ function = "uart0";
+ };
+
+ uart0_pf_pins: uart0-pf-pins {
+ pins = "PF2", "PF4";
+ function = "uart0";
};
- uart0_pins_a: uart0 at 0 {
- allwinner,pins = "PF2", "PF4";
- allwinner,function = "uart0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ uart1_pins: uart1-pins {
+ pins = "PG6", "PG7";
+ function = "uart1";
};
- uart0_pins_b: uart0 at 1 {
- allwinner,pins = "PB9", "PB10";
- allwinner,function = "uart0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ uart1_rts_cts_pins: uart1-rts-cts-pins {
+ pins = "PG8", "PG9";
+ function = "uart1";
};
};
- timer at 01c20c00 {
+ timer at 1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0xa0>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
@@ -197,27 +757,166 @@
clocks = <&osc24M>;
};
- watchdog at 01c20ca0 {
+ watchdog at 1c20ca0 {
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
- uart0: serial at 01c28000 {
+ spdif: spdif at 1c21000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-a83t-spdif",
+ "allwinner,sun8i-h3-spdif";
+ reg = <0x01c21000 0x400>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
+ resets = <&ccu RST_BUS_SPDIF>;
+ clock-names = "apb", "spdif";
+ dmas = <&dma 2>;
+ dma-names = "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif_tx_pin>;
+ status = "disabled";
+ };
+
+ i2s0: i2s at 1c22000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-a83t-i2s";
+ reg = <0x01c22000 0x400>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
+ clock-names = "apb", "mod";
+ dmas = <&dma 3>, <&dma 3>;
+ resets = <&ccu RST_BUS_I2S0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2s1: i2s at 1c22400 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-a83t-i2s";
+ reg = <0x01c22400 0x400>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
+ clock-names = "apb", "mod";
+ dmas = <&dma 4>, <&dma 4>;
+ resets = <&ccu RST_BUS_I2S1>;
+ dma-names = "rx", "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1_pins>;
+ status = "disabled";
+ };
+
+ i2s2: i2s at 1c22800 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-a83t-i2s";
+ reg = <0x01c22800 0x400>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
+ clock-names = "apb", "mod";
+ dmas = <&dma 27>;
+ resets = <&ccu RST_BUS_I2S2>;
+ dma-names = "tx";
+ status = "disabled";
+ };
+
+ pwm: pwm at 1c21400 {
+ compatible = "allwinner,sun8i-a83t-pwm",
+ "allwinner,sun8i-h3-pwm";
+ reg = <0x01c21400 0x400>;
+ clocks = <&osc24M>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ uart0: serial at 1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc24M>;
+ clocks = <&ccu CLK_BUS_UART0>;
+ resets = <&ccu RST_BUS_UART0>;
status = "disabled";
};
- gic: interrupt-controller at 01c81000 {
+ uart1: serial at 1c28400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28400 0x400>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART1>;
+ resets = <&ccu RST_BUS_UART1>;
+ status = "disabled";
+ };
+
+ i2c0: i2c at 1c2ac00 {
+ compatible = "allwinner,sun8i-a83t-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2ac00 0x400>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C0>;
+ resets = <&ccu RST_BUS_I2C0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c at 1c2b000 {
+ compatible = "allwinner,sun8i-a83t-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b000 0x400>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C1>;
+ resets = <&ccu RST_BUS_I2C1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c at 1c2b400 {
+ compatible = "allwinner,sun8i-a83t-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b400 0x400>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C2>;
+ resets = <&ccu RST_BUS_I2C2>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ emac: ethernet at 1c30000 {
+ compatible = "allwinner,sun8i-a83t-emac";
+ syscon = <&syscon>;
+ reg = <0x01c30000 0x104>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ resets = <&ccu 13>;
+ reset-names = "stmmaceth";
+ clocks = <&ccu 27>;
+ clock-names = "stmmaceth";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ mdio: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ gic: interrupt-controller at 1c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
- <0x01c82000 0x1000>,
+ <0x01c82000 0x2000>,
<0x01c84000 0x2000>,
<0x01c86000 0x2000>;
interrupt-controller;
@@ -225,59 +924,107 @@
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
};
- usb_otg: usb at 01c19000 {
- compatible = "allwinner,sun8i-a33-musb";
- reg = <0x01c19000 0x400>;
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "mc";
- phys = <&usbphy 0>;
- phy-names = "usb";
+ hdmi: hdmi at 1ee0000 {
+ compatible = "allwinner,sun8i-a83t-dw-hdmi";
+ reg = <0x01ee0000 0x10000>;
+ reg-io-width = <1>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
+ <&ccu CLK_HDMI>;
+ clock-names = "iahb", "isfr", "tmds";
+ resets = <&ccu RST_BUS_HDMI1>;
+ reset-names = "ctrl";
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi-phy";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pins>;
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port at 0 {
+ reg = <0>;
+
+ hdmi_in_tcon1: endpoint {
+ remote-endpoint = <&tcon1_out_hdmi>;
+ };
+ };
+
+ hdmi_out: port at 1 {
+ reg = <1>;
+ };
+ };
};
- usbphy: phy at 1c19400 {
- compatible = "allwinner,sun8i-a83t-usb-phy";
- reg = <0x01c19400 0x10>,
- <0x01c1a800 0x14>,
- <0x01c1b800 0x14>;
- reg-names = "phy_ctrl",
- "pmu1",
- "pmu2";
- status = "disabled";
- #phy-cells = <1>;
+ hdmi_phy: hdmi-phy at 1ef0000 {
+ compatible = "allwinner,sun8i-a83t-hdmi-phy";
+ reg = <0x01ef0000 0x10000>;
+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_HDMI0>;
+ reset-names = "phy";
+ #phy-cells = <0>;
};
- ehci0: usb at 01c1a000 {
- compatible = "allwinner,sun8i-a83t-ehci", "generic-ehci";
- reg = <0x01c1a000 0x100>;
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usbphy 1>;
- phy-names = "usb";
- status = "disabled";
+ r_intc: interrupt-controller at 1f00c00 {
+ compatible = "allwinner,sun8i-a83t-r-intc",
+ "allwinner,sun6i-a31-r-intc";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x01f00c00 0x400>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
- ohci0: usb at 01c1a400 {
- compatible = "allwinner,sun8i-a83t-ohci", "generic-ohci";
- reg = <0x01c1a400 0x100>;
- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usbphy 1>;
- phy-names = "usb";
- status = "disabled";
+ r_ccu: clock at 1f01400 {
+ compatible = "allwinner,sun8i-a83t-r-ccu";
+ reg = <0x01f01400 0x400>;
+ clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
+ <&ccu 6>;
+ clock-names = "hosc", "losc", "iosc", "pll-periph";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
};
- ehci1: usb at 01c1b000 {
- compatible = "allwinner,sun8i-a83t-ehci", "generic-ehci";
- reg = <0x01c1b000 0x100>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usbphy 2>;
- phy-names = "usb";
- status = "disabled";
+ r_cpucfg at 1f01c00 {
+ compatible = "allwinner,sun8i-a83t-r-cpucfg";
+ reg = <0x1f01c00 0x400>;
};
- r_pio: pinctrl at 01f02c00 {
+ r_pio: pinctrl at 1f02c00 {
compatible = "allwinner,sun8i-a83t-r-pinctrl";
reg = <0x01f02c00 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
+ <&osc16Md512>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ r_rsb_pins: r-rsb-pins {
+ pins = "PL0", "PL1";
+ function = "s_rsb";
+ drive-strength = <20>;
+ bias-pull-up;
+ };
+ };
+
+ r_rsb: rsb at 1f03400 {
+ compatible = "allwinner,sun8i-a83t-rsb",
+ "allwinner,sun8i-a23-rsb";
+ reg = <0x01f03400 0x400>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_APB0_RSB>;
+ clock-frequency = <3000000>;
+ resets = <&r_ccu RST_APB0_RSB>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_rsb_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
};
};
diff --git a/include/dt-bindings/clock/sun8i-a83t-ccu.h b/include/dt-bindings/clock/sun8i-a83t-ccu.h
new file mode 100644
index 0000000000..78af5085f6
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-a83t-ccu.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_
+#define _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_
+
+#define CLK_PLL_PERIPH 6
+
+#define CLK_PLL_DE 9
+
+#define CLK_C0CPUX 11
+#define CLK_C1CPUX 12
+
+#define CLK_BUS_MIPI_DSI 19
+#define CLK_BUS_SS 20
+#define CLK_BUS_DMA 21
+#define CLK_BUS_MMC0 22
+#define CLK_BUS_MMC1 23
+#define CLK_BUS_MMC2 24
+#define CLK_BUS_NAND 25
+#define CLK_BUS_DRAM 26
+#define CLK_BUS_EMAC 27
+#define CLK_BUS_HSTIMER 28
+#define CLK_BUS_SPI0 29
+#define CLK_BUS_SPI1 30
+#define CLK_BUS_OTG 31
+#define CLK_BUS_EHCI0 32
+#define CLK_BUS_EHCI1 33
+#define CLK_BUS_OHCI0 34
+
+#define CLK_BUS_VE 35
+#define CLK_BUS_TCON0 36
+#define CLK_BUS_TCON1 37
+#define CLK_BUS_CSI 38
+#define CLK_BUS_HDMI 39
+#define CLK_BUS_DE 40
+#define CLK_BUS_GPU 41
+#define CLK_BUS_MSGBOX 42
+#define CLK_BUS_SPINLOCK 43
+
+#define CLK_BUS_SPDIF 44
+#define CLK_BUS_PIO 45
+#define CLK_BUS_I2S0 46
+#define CLK_BUS_I2S1 47
+#define CLK_BUS_I2S2 48
+#define CLK_BUS_TDM 49
+
+#define CLK_BUS_I2C0 50
+#define CLK_BUS_I2C1 51
+#define CLK_BUS_I2C2 52
+#define CLK_BUS_UART0 53
+#define CLK_BUS_UART1 54
+#define CLK_BUS_UART2 55
+#define CLK_BUS_UART3 56
+#define CLK_BUS_UART4 57
+
+#define CLK_NAND 59
+#define CLK_MMC0 60
+#define CLK_MMC0_SAMPLE 61
+#define CLK_MMC0_OUTPUT 62
+#define CLK_MMC1 63
+#define CLK_MMC1_SAMPLE 64
+#define CLK_MMC1_OUTPUT 65
+#define CLK_MMC2 66
+#define CLK_MMC2_SAMPLE 67
+#define CLK_MMC2_OUTPUT 68
+#define CLK_SS 69
+#define CLK_SPI0 70
+#define CLK_SPI1 71
+#define CLK_I2S0 72
+#define CLK_I2S1 73
+#define CLK_I2S2 74
+#define CLK_TDM 75
+#define CLK_SPDIF 76
+#define CLK_USB_PHY0 77
+#define CLK_USB_PHY1 78
+#define CLK_USB_HSIC 79
+#define CLK_USB_HSIC_12M 80
+#define CLK_USB_OHCI0 81
+
+#define CLK_DRAM_VE 83
+#define CLK_DRAM_CSI 84
+
+#define CLK_TCON0 85
+#define CLK_TCON1 86
+#define CLK_CSI_MISC 87
+#define CLK_MIPI_CSI 88
+#define CLK_CSI_MCLK 89
+#define CLK_CSI_SCLK 90
+#define CLK_VE 91
+#define CLK_AVS 92
+#define CLK_HDMI 93
+#define CLK_HDMI_SLOW 94
+
+#define CLK_MIPI_DSI0 96
+#define CLK_MIPI_DSI1 97
+#define CLK_GPU_CORE 98
+#define CLK_GPU_MEMORY 99
+#define CLK_GPU_HYD 100
+
+#endif /* _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ */
diff --git a/include/dt-bindings/reset/sun8i-a83t-ccu.h b/include/dt-bindings/reset/sun8i-a83t-ccu.h
new file mode 100644
index 0000000000..784f6e1166
--- /dev/null
+++ b/include/dt-bindings/reset/sun8i-a83t-ccu.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_
+#define _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_
+
+#define RST_USB_PHY0 0
+#define RST_USB_PHY1 1
+#define RST_USB_HSIC 2
+
+#define RST_DRAM 3
+#define RST_MBUS 4
+
+#define RST_BUS_MIPI_DSI 5
+#define RST_BUS_SS 6
+#define RST_BUS_DMA 7
+#define RST_BUS_MMC0 8
+#define RST_BUS_MMC1 9
+#define RST_BUS_MMC2 10
+#define RST_BUS_NAND 11
+#define RST_BUS_DRAM 12
+#define RST_BUS_EMAC 13
+#define RST_BUS_HSTIMER 14
+#define RST_BUS_SPI0 15
+#define RST_BUS_SPI1 16
+#define RST_BUS_OTG 17
+#define RST_BUS_EHCI0 18
+#define RST_BUS_EHCI1 19
+#define RST_BUS_OHCI0 20
+
+#define RST_BUS_VE 21
+#define RST_BUS_TCON0 22
+#define RST_BUS_TCON1 23
+#define RST_BUS_CSI 24
+#define RST_BUS_HDMI0 25
+#define RST_BUS_HDMI1 26
+#define RST_BUS_DE 27
+#define RST_BUS_GPU 28
+#define RST_BUS_MSGBOX 29
+#define RST_BUS_SPINLOCK 30
+
+#define RST_BUS_LVDS 31
+
+#define RST_BUS_SPDIF 32
+#define RST_BUS_I2S0 33
+#define RST_BUS_I2S1 34
+#define RST_BUS_I2S2 35
+#define RST_BUS_TDM 36
+
+#define RST_BUS_I2C0 37
+#define RST_BUS_I2C1 38
+#define RST_BUS_I2C2 39
+#define RST_BUS_UART0 40
+#define RST_BUS_UART1 41
+#define RST_BUS_UART2 42
+#define RST_BUS_UART3 43
+#define RST_BUS_UART4 44
+
+#endif /* _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_ */
--
2.17.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 17/25] mmc: sunxi: Add A83T emmc compatible
2018-07-16 8:19 [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Jagan Teki
` (15 preceding siblings ...)
2018-07-16 8:19 ` [U-Boot] [PATCH 16/25] ARM: dts: sun8i: Update A83T dts(i) files from Linux Jagan Teki
@ 2018-07-16 8:19 ` Jagan Teki
2018-07-16 8:19 ` [U-Boot] [PATCH 18/25] sunxi: A83T: Enable DM_MMC Jagan Teki
` (8 subsequent siblings)
25 siblings, 0 replies; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 8:19 UTC (permalink / raw)
To: u-boot
Add emmc compatible for A83T SoC.
Cc: VishnuPatekar <vishnupatekar0510@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/mmc/sunxi_mmc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 16e94cf4b7..1e7bea4d5a 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -687,6 +687,8 @@ static const struct udevice_id sunxi_mmc_ids[] = {
.data = (ulong)&sun4i_a10_cfg },
{ .compatible = "allwinner,sun7i-a20-mmc",
.data = (ulong)&sun7i_a20_cfg },
+ { .compatible = "allwinner,sun8i-a83t-emmc",
+ .data = (ulong)&sun7i_a20_cfg },
{ .compatible = "allwinner,sun50i-a64-mmc",
.data = (ulong)&sun7i_a20_cfg },
{ .compatible = "allwinner,sun50i-a64-emmc",
--
2.17.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 18/25] sunxi: A83T: Enable DM_MMC
2018-07-16 8:19 [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Jagan Teki
` (16 preceding siblings ...)
2018-07-16 8:19 ` [U-Boot] [PATCH 17/25] mmc: sunxi: Add A83T emmc compatible Jagan Teki
@ 2018-07-16 8:19 ` Jagan Teki
2018-07-16 8:19 ` [U-Boot] [PATCH 19/25] ARM: dts: sun8i: Update R40 dts(i) files from Linux Jagan Teki
` (7 subsequent siblings)
25 siblings, 0 replies; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 8:19 UTC (permalink / raw)
To: u-boot
Enable DM_MMC for Allwinner A83T SoC.
Tested on BPI-M3.
Cc: VishnuPatekar <vishnupatekar0510@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/mach-sunxi/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 3b790e39dd..d5b0700e13 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -216,6 +216,7 @@ config MACH_SUN8I_A33
config MACH_SUN8I_A83T
bool "sun8i (Allwinner A83T)"
select CPU_V7A
+ select DM_MMC if MMC
select DRAM_SUN8I_A83T
select PHY_SUN4I_USB
select SUNXI_GEN_SUN6I
--
2.17.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 19/25] ARM: dts: sun8i: Update R40 dts(i) files from Linux
2018-07-16 8:19 [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Jagan Teki
` (17 preceding siblings ...)
2018-07-16 8:19 ` [U-Boot] [PATCH 18/25] sunxi: A83T: Enable DM_MMC Jagan Teki
@ 2018-07-16 8:19 ` Jagan Teki
2018-07-16 8:19 ` [U-Boot] [PATCH 20/25] sunxi: V40: Enable DM_MMC Jagan Teki
` (6 subsequent siblings)
25 siblings, 0 replies; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 8:19 UTC (permalink / raw)
To: u-boot
Update all R40 devicetree dtsi and dtsi files from Linux
with below commit:
commit 6a7556f604f94461ca802ab69a6dad317c014d30
Author: Jernej Skrabec <jernej.skrabec@siol.net>
Date: Tue Jul 10 22:35:09 2018 +0200
ARM: dts: sun8i: r40: Disable TCONs by default.
and BPI-M2 berry
commit c5f0bb472795170ab5c33be12e29ce7465fb31ed
Author: Icenowy Zheng <icenowy@aosc.io>
Date: Fri Apr 6 22:03:44 2018 +0800
ARM: sun8i: v40: enable USB host ports for Banana Pi M2 Berry
Cc: Lothar Felten <lothar.felten@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts | 197 +++++-
arch/arm/dts/sun8i-r40.dtsi | 616 ++++++++++++++++++-
arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts | 50 ++
3 files changed, 830 insertions(+), 33 deletions(-)
diff --git a/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
index 28c9158302..c39b9169ea 100644
--- a/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
+++ b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -1,5 +1,6 @@
/*
- * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
+ * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@@ -43,6 +44,8 @@
/dts-v1/;
#include "sun8i-r40.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
/ {
model = "Banana Pi BPI-M2-Ultra";
compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40";
@@ -55,17 +58,62 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pwr-led {
+ label = "bananapi:red:pwr";
+ gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ user-led-green {
+ label = "bananapi:green:user";
+ gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>;
+ };
+
+ user-led-blue {
+ label = "bananapi:blue:user";
+ gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ reg_vcc5v0: vcc5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
+ enable-active-high;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
+ };
};
-&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
+&de {
status = "okay";
};
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pb_pins>;
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
status = "okay";
};
@@ -74,6 +122,7 @@
pinctrl-0 = <&gmac_rgmii_pins>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
+ phy-supply = <®_dc1sw>;
status = "okay";
};
@@ -83,3 +132,137 @@
reg = <1>;
};
};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ axp22x: pmic at 34 {
+ compatible = "x-powers,axp221";
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "axp22x.dtsi"
+
+&mmc0 {
+ vmmc-supply = <®_dcdc1>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pg_pins>;
+ vmmc-supply = <®_dldo2>;
+ vqmmc-supply = <®_dldo1>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+&mmc2 {
+ vmmc-supply = <®_dcdc1>;
+ vqmmc-supply = <®_dcdc1>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+®_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-name = "vcc-pa";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "avcc";
+};
+
+®_dc1sw {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-gmac-phy";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-3v0";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-sys";
+};
+
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-io";
+};
+
+®_dldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+&tcon_tv0 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pb_pins>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_vcc5v0>;
+ usb2_vbus-supply = <®_vcc5v0>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi
index 2cdfb54282..e2cbd4f645 100644
--- a/arch/arm/dts/sun8i-r40.dtsi
+++ b/arch/arm/dts/sun8i-r40.dtsi
@@ -1,7 +1,6 @@
/*
- * Copyright 2016 Chen-Yu Tsai
- *
- * Chen-Yu Tsai <wens@csie.org>
+ * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
+ * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@@ -43,32 +42,29 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/sun8i-de2.h>
#include <dt-bindings/clock/sun8i-r40-ccu.h>
#include <dt-bindings/reset/sun8i-r40-ccu.h>
+#include <dt-bindings/reset/sun8i-de2.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
- aliases {
- };
-
- chosen {
- };
-
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
- osc24M: osc24M_clk {
+ osc24M: osc24M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
};
- osc32k: osc32k_clk {
+ osc32k: osc32k {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
@@ -80,7 +76,7 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu0: cpu at 0 {
+ cpu at 0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
@@ -105,9 +101,10 @@
};
};
- memory at 40000000 {
- device_type = "memory";
- reg = <0x40000000 0x80000000>;
+ de: display-engine {
+ compatible = "allwinner,sun8i-r40-display-engine";
+ allwinner,pipelines = <&mixer0>, <&mixer1>;
+ status = "disabled";
};
soc {
@@ -116,6 +113,63 @@
#size-cells = <1>;
ranges;
+ display_clocks: clock at 1000000 {
+ compatible = "allwinner,sun8i-r40-de2-clk",
+ "allwinner,sun8i-h3-de2-clk";
+ reg = <0x01000000 0x100000>;
+ clocks = <&ccu CLK_DE>,
+ <&ccu CLK_BUS_DE>;
+ clock-names = "mod",
+ "bus";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mixer0: mixer at 1100000 {
+ compatible = "allwinner,sun8i-r40-de2-mixer-0";
+ reg = <0x01100000 0x100000>;
+ clocks = <&display_clocks CLK_BUS_MIXER0>,
+ <&display_clocks CLK_MIXER0>;
+ clock-names = "bus",
+ "mod";
+ resets = <&display_clocks RST_MIXER0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer0_out: port at 1 {
+ reg = <1>;
+ mixer0_out_tcon_top: endpoint {
+ remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
+ };
+ };
+ };
+ };
+
+ mixer1: mixer at 1200000 {
+ compatible = "allwinner,sun8i-r40-de2-mixer-1";
+ reg = <0x01200000 0x100000>;
+ clocks = <&display_clocks CLK_BUS_MIXER1>,
+ <&display_clocks CLK_MIXER1>;
+ clock-names = "bus",
+ "mod";
+ resets = <&display_clocks RST_WB>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer1_out: port at 1 {
+ reg = <1>;
+ mixer1_out_tcon_top: endpoint {
+ remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
+ };
+ };
+ };
+ };
+
nmi_intc: interrupt-controller at 1c00030 {
compatible = "allwinner,sun7i-a20-sc-nmi";
interrupt-controller;
@@ -140,6 +194,122 @@
#size-cells = <0>;
};
+ mmc1: mmc at 1c10000 {
+ compatible = "allwinner,sun8i-r40-mmc",
+ "allwinner,sun50i-a64-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC1>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc at 1c11000 {
+ compatible = "allwinner,sun8i-r40-emmc",
+ "allwinner,sun50i-a64-emmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC2>;
+ reset-names = "ahb";
+ pinctrl-0 = <&mmc2_pins>;
+ pinctrl-names = "default";
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc3: mmc at 1c12000 {
+ compatible = "allwinner,sun8i-r40-mmc",
+ "allwinner,sun50i-a64-mmc";
+ reg = <0x01c12000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC3>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ usbphy: phy at 1c13400 {
+ compatible = "allwinner,sun8i-r40-usb-phy";
+ reg = <0x01c13400 0x14>,
+ <0x01c14800 0x4>,
+ <0x01c19800 0x4>,
+ <0x01c1c800 0x4>;
+ reg-names = "phy_ctrl",
+ "pmu0",
+ "pmu1",
+ "pmu2";
+ clocks = <&ccu CLK_USB_PHY0>,
+ <&ccu CLK_USB_PHY1>,
+ <&ccu CLK_USB_PHY2>;
+ clock-names = "usb0_phy",
+ "usb1_phy",
+ "usb2_phy";
+ resets = <&ccu RST_USB_PHY0>,
+ <&ccu RST_USB_PHY1>,
+ <&ccu RST_USB_PHY2>;
+ reset-names = "usb0_reset",
+ "usb1_reset",
+ "usb2_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ehci1: usb at 1c19000 {
+ compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
+ reg = <0x01c19000 0x100>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI1>;
+ resets = <&ccu RST_BUS_EHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci1: usb at 1c19400 {
+ compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
+ reg = <0x01c19400 0x100>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI1>,
+ <&ccu CLK_USB_OHCI1>;
+ resets = <&ccu RST_BUS_OHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci2: usb at 1c1c000 {
+ compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
+ reg = <0x01c1c000 0x100>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI2>;
+ resets = <&ccu RST_BUS_EHCI2>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci2: usb at 1c1c400 {
+ compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
+ reg = <0x01c1c400 0x100>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI2>,
+ <&ccu CLK_USB_OHCI2>;
+ resets = <&ccu RST_BUS_OHCI2>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
ccu: clock at 1c20000 {
compatible = "allwinner,sun8i-r40-ccu";
reg = <0x01c20000 0x400>;
@@ -153,8 +323,7 @@
compatible = "allwinner,sun8i-r40-pinctrl";
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- /* apb should be replaced once CCU is implemented */
- clocks = <&osc24M>, <&osc24M>, <&osc32k>;
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
@@ -174,10 +343,9 @@
drive-strength = <40>;
};
- i2c0_pins: i2c0_pins {
+ i2c0_pins: i2c0-pins {
pins = "PB0", "PB1";
function = "i2c0";
- bias-pull-up;
};
mmc0_pins: mmc0-pins {
@@ -188,20 +356,119 @@
bias-pull-up;
};
- uart0_pb_pins: uart0_pb_pins {
+ mmc1_pg_pins: mmc1-pg-pins {
+ pins = "PG0", "PG1", "PG2",
+ "PG3", "PG4", "PG5";
+ function = "mmc1";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ mmc2_pins: mmc2-pins {
+ pins = "PC5", "PC6", "PC7", "PC8", "PC9",
+ "PC10", "PC11", "PC12", "PC13", "PC14",
+ "PC15", "PC24";
+ function = "mmc2";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ uart0_pb_pins: uart0-pb-pins {
pins = "PB22", "PB23";
function = "uart0";
- bias-pull-up;
};
};
+ wdt: watchdog at 1c20c90 {
+ compatible = "allwinner,sun4i-a10-wdt";
+ reg = <0x01c20c90 0x10>;
+ };
+
uart0: serial at 1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc24M>;
+ clocks = <&ccu CLK_BUS_UART0>;
+ resets = <&ccu RST_BUS_UART0>;
+ status = "disabled";
+ };
+
+ uart1: serial at 1c28400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28400 0x400>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART1>;
+ resets = <&ccu RST_BUS_UART1>;
+ status = "disabled";
+ };
+
+ uart2: serial at 1c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART2>;
+ resets = <&ccu RST_BUS_UART2>;
+ status = "disabled";
+ };
+
+ uart3: serial at 1c28c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28c00 0x400>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART3>;
+ resets = <&ccu RST_BUS_UART3>;
+ status = "disabled";
+ };
+
+ uart4: serial at 1c29000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29000 0x400>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART4>;
+ resets = <&ccu RST_BUS_UART4>;
+ status = "disabled";
+ };
+
+ uart5: serial at 1c29400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29400 0x400>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART5>;
+ resets = <&ccu RST_BUS_UART5>;
+ status = "disabled";
+ };
+
+ uart6: serial at 1c29800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29800 0x400>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART6>;
+ resets = <&ccu RST_BUS_UART6>;
+ status = "disabled";
+ };
+
+ uart7: serial at 1c29c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29c00 0x400>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART7>;
+ resets = <&ccu RST_BUS_UART7>;
status = "disabled";
};
@@ -209,7 +476,54 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc24M>;
+ clocks = <&ccu CLK_BUS_I2C0>;
+ resets = <&ccu RST_BUS_I2C0>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c at 1c2b000 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b000 0x400>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C1>;
+ resets = <&ccu RST_BUS_I2C1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c at 1c2b400 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b400 0x400>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C2>;
+ resets = <&ccu RST_BUS_I2C2>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c3: i2c at 1c2b800 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b800 0x400>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C3>;
+ resets = <&ccu RST_BUS_I2C3>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c4: i2c at 1c2c000 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2c000 0x400>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C4>;
+ resets = <&ccu RST_BUS_I2C4>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -236,8 +550,215 @@
};
};
+ tcon_top: tcon-top at 1c70000 {
+ compatible = "allwinner,sun8i-r40-tcon-top";
+ reg = <0x01c70000 0x1000>;
+ clocks = <&ccu CLK_BUS_TCON_TOP>,
+ <&ccu CLK_TCON_TV0>,
+ <&ccu CLK_TVE0>,
+ <&ccu CLK_TCON_TV1>,
+ <&ccu CLK_TVE1>,
+ <&ccu CLK_DSI_DPHY>;
+ clock-names = "bus",
+ "tcon-tv0",
+ "tve0",
+ "tcon-tv1",
+ "tve1",
+ "dsi";
+ clock-output-names = "tcon-top-tv0",
+ "tcon-top-tv1",
+ "tcon-top-dsi";
+ resets = <&ccu RST_BUS_TCON_TOP>;
+ #clock-cells = <1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_top_mixer0_in: port at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon_top_mixer0_in_mixer0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&mixer0_out_tcon_top>;
+ };
+ };
+
+ tcon_top_mixer0_out: port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon_top_mixer0_out_tcon_lcd0: endpoint at 0 {
+ reg = <0>;
+ };
+
+ tcon_top_mixer0_out_tcon_lcd1: endpoint at 1 {
+ reg = <1>;
+ };
+
+ tcon_top_mixer0_out_tcon_tv0: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
+ };
+
+ tcon_top_mixer0_out_tcon_tv1: endpoint at 3 {
+ reg = <3>;
+ remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
+ };
+ };
+
+ tcon_top_mixer1_in: port at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ tcon_top_mixer1_in_mixer1: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&mixer1_out_tcon_top>;
+ };
+ };
+
+ tcon_top_mixer1_out: port at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ tcon_top_mixer1_out_tcon_lcd0: endpoint at 0 {
+ reg = <0>;
+ };
+
+ tcon_top_mixer1_out_tcon_lcd1: endpoint at 1 {
+ reg = <1>;
+ };
+
+ tcon_top_mixer1_out_tcon_tv0: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
+ };
+
+ tcon_top_mixer1_out_tcon_tv1: endpoint at 3 {
+ reg = <3>;
+ remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
+ };
+ };
+
+ tcon_top_hdmi_in: port at 4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+
+ tcon_top_hdmi_in_tcon_tv0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&tcon_tv0_out_tcon_top>;
+ };
+
+ tcon_top_hdmi_in_tcon_tv1: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&tcon_tv1_out_tcon_top>;
+ };
+ };
+
+ tcon_top_hdmi_out: port at 5 {
+ reg = <5>;
+
+ tcon_top_hdmi_out_hdmi: endpoint {
+ remote-endpoint = <&hdmi_in_tcon_top>;
+ };
+ };
+ };
+ };
+
+ tcon_tv0: lcd-controller at 1c73000 {
+ compatible = "allwinner,sun8i-r40-tcon-tv";
+ reg = <0x01c73000 0x1000>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>;
+ clock-names = "ahb", "tcon-ch1";
+ resets = <&ccu RST_BUS_TCON_TV0>;
+ reset-names = "lcd";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_tv0_in: port at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon_tv0_in_tcon_top_mixer0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
+ };
+
+ tcon_tv0_in_tcon_top_mixer1: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
+ };
+ };
+
+ tcon_tv0_out: port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon_tv0_out_tcon_top: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
+ };
+ };
+ };
+ };
+
+ tcon_tv1: lcd-controller at 1c74000 {
+ compatible = "allwinner,sun8i-r40-tcon-tv";
+ reg = <0x01c74000 0x1000>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>;
+ clock-names = "ahb", "tcon-ch1";
+ resets = <&ccu RST_BUS_TCON_TV1>;
+ reset-names = "lcd";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_tv1_in: port at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon_tv1_in_tcon_top_mixer0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>;
+ };
+
+ tcon_tv1_in_tcon_top_mixer1: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>;
+ };
+ };
+
+ tcon_tv1_out: port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon_tv1_out_tcon_top: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>;
+ };
+ };
+ };
+ };
+
gic: interrupt-controller at 1c81000 {
- compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,
<0x01c82000 0x1000>,
<0x01c84000 0x2000>,
@@ -246,6 +767,51 @@
#interrupt-cells = <3>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+
+ hdmi: hdmi at 1ee0000 {
+ compatible = "allwinner,sun8i-r40-dw-hdmi",
+ "allwinner,sun8i-a83t-dw-hdmi";
+ reg = <0x01ee0000 0x10000>;
+ reg-io-width = <1>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
+ <&ccu CLK_HDMI>;
+ clock-names = "iahb", "isfr", "tmds";
+ resets = <&ccu RST_BUS_HDMI1>;
+ reset-names = "ctrl";
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi-phy";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port at 0 {
+ reg = <0>;
+
+ hdmi_in_tcon_top: endpoint {
+ remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
+ };
+ };
+
+ hdmi_out: port at 1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ hdmi_phy: hdmi-phy at 1ef0000 {
+ compatible = "allwinner,sun8i-r40-hdmi-phy",
+ "allwinner,sun50i-a64-hdmi-phy";
+ reg = <0x01ef0000 0x10000>;
+ clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
+ <&ccu 7>, <&ccu 16>;
+ clock-names = "bus", "mod", "pll-0", "pll-1";
+ resets = <&ccu RST_BUS_HDMI0>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ };
};
timer {
@@ -254,7 +820,5 @@
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- clock-frequency = <24000000>;
- arm,cpu-registers-not-fw-configured;
};
};
diff --git a/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts
index 193d9b29ec..35859d8f32 100644
--- a/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts
+++ b/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts
@@ -56,6 +56,40 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ leds {
+ compatible = "gpio-leds";
+
+ pwr-led {
+ label = "bananapi:red:pwr";
+ gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ user-led {
+ label = "bananapi:green:user";
+ gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ reg_vcc5v0: vcc5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
+ enable-active-high;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
+ };
+};
+
+&ehci1 {
+ /* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */
+ status = "okay";
};
&i2c0 {
@@ -125,8 +159,24 @@
status = "okay";
};
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pg_pins>;
+ vmmc-supply = <®_dldo2>;
+ vqmmc-supply = <®_dldo1>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
+
+&usbphy {
+ usb1_vbus-supply = <®_vcc5v0>;
+ status = "okay";
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 20/25] sunxi: V40: Enable DM_MMC
2018-07-16 8:19 [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Jagan Teki
` (18 preceding siblings ...)
2018-07-16 8:19 ` [U-Boot] [PATCH 19/25] ARM: dts: sun8i: Update R40 dts(i) files from Linux Jagan Teki
@ 2018-07-16 8:19 ` Jagan Teki
2018-07-16 8:19 ` [U-Boot] [PATCH 21/25] fastboot: sunxi: Update fastboot mmc default device Jagan Teki
` (5 subsequent siblings)
25 siblings, 0 replies; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 8:19 UTC (permalink / raw)
To: u-boot
Enable DM_MMC for Allwinner V40 SoC.
Tested on BPI-M2 Ultra, BPI-M2 Berry.
Cc: Lothar Felten <lothar.felten@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/mach-sunxi/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index d5b0700e13..f3d7c8b67d 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -238,6 +238,7 @@ config MACH_SUN8I_R40
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
+ select DM_MMC if MMC
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
select SUNXI_DRAM_DW
--
2.17.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 21/25] fastboot: sunxi: Update fastboot mmc default device
2018-07-16 8:19 [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Jagan Teki
` (19 preceding siblings ...)
2018-07-16 8:19 ` [U-Boot] [PATCH 20/25] sunxi: V40: Enable DM_MMC Jagan Teki
@ 2018-07-16 8:19 ` Jagan Teki
2018-07-16 9:46 ` Maxime Ripard
2018-07-16 8:19 ` [U-Boot] [PATCH 22/25] env: sunxi: Update default env fat device Jagan Teki
` (4 subsequent siblings)
25 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 8:19 UTC (permalink / raw)
To: u-boot
Usually eMMC is default env fat device for environment,
if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc
device as 1. but with DM_MMC it can be more possible to
probe eMMC as device 2 since for most of the sunxi platforms
eMMC is configured mmc2.
So update the fastboot mmc default device as 2 if DM_MMC and
MMC_SUNXI_SLOT_EXTRA != 1 slot is 2 defined but some boards
may not use all possible mmc devices or partly disabled in DT,
for those update the device in board specific defconfig.
Cc: Olliver Schinagl <oliver@schinagl.nl>
Cc: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
configs/Sinlinx_SinA33_defconfig | 1 +
configs/amarula_a64_relic_defconfig | 1 +
drivers/fastboot/Kconfig | 3 ++-
4 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
index 5657fc2594..20ea254191 100644
--- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
+++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
@@ -29,4 +29,5 @@ CONFIG_AXP_ALDO4_VOLT=2800
CONFIG_SCSI=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
index 394534b8b5..7841219a65 100644
--- a/configs/Sinlinx_SinA33_defconfig
+++ b/configs/Sinlinx_SinA33_defconfig
@@ -21,5 +21,6 @@ CONFIG_DFU_RAM=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
CONFIG_USB_FUNCTION_MASS_STORAGE=y
diff --git a/configs/amarula_a64_relic_defconfig b/configs/amarula_a64_relic_defconfig
index b72cbfabc6..caeb3f6008 100644
--- a/configs/amarula_a64_relic_defconfig
+++ b/configs/amarula_a64_relic_defconfig
@@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic"
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
index bc25ea1d9c..4a1bfd119c 100644
--- a/drivers/fastboot/Kconfig
+++ b/drivers/fastboot/Kconfig
@@ -88,7 +88,8 @@ config FASTBOOT_FLASH_MMC_DEV
int "Define FASTBOOT MMC FLASH default device"
depends on FASTBOOT_FLASH_MMC
default 0 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
- default 1 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
+ default 1 if ARCH_SUNXI && !DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
+ default 2 if ARCH_SUNXI && DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
help
The fastboot "flash" command requires additional information
regarding the non-volatile storage device. Define this to
--
2.17.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 21/25] fastboot: sunxi: Update fastboot mmc default device
2018-07-16 8:19 ` [U-Boot] [PATCH 21/25] fastboot: sunxi: Update fastboot mmc default device Jagan Teki
@ 2018-07-16 9:46 ` Maxime Ripard
2018-07-16 10:12 ` Jagan Teki
0 siblings, 1 reply; 59+ messages in thread
From: Maxime Ripard @ 2018-07-16 9:46 UTC (permalink / raw)
To: u-boot
On Mon, Jul 16, 2018 at 01:49:52PM +0530, Jagan Teki wrote:
> Usually eMMC is default env fat device for environment,
> if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc
> device as 1. but with DM_MMC it can be more possible to
> probe eMMC as device 2 since for most of the sunxi platforms
> eMMC is configured mmc2.
>
> So update the fastboot mmc default device as 2 if DM_MMC and
> MMC_SUNXI_SLOT_EXTRA != 1 slot is 2 defined but some boards
> may not use all possible mmc devices or partly disabled in DT,
> for those update the device in board specific defconfig.
>
> Cc: Olliver Schinagl <oliver@schinagl.nl>
> Cc: Chen-Yu Tsai <wens@csie.org>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
> configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
> configs/Sinlinx_SinA33_defconfig | 1 +
> configs/amarula_a64_relic_defconfig | 1 +
> drivers/fastboot/Kconfig | 3 ++-
> 4 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> index 5657fc2594..20ea254191 100644
> --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> @@ -29,4 +29,5 @@ CONFIG_AXP_ALDO4_VOLT=2800
> CONFIG_SCSI=y
> CONFIG_USB_EHCI_HCD=y
> CONFIG_USB_MUSB_GADGET=y
> +CONFIG_FASTBOOT_FLASH_MMC_DEV=1
> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
> diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
> index 394534b8b5..7841219a65 100644
> --- a/configs/Sinlinx_SinA33_defconfig
> +++ b/configs/Sinlinx_SinA33_defconfig
> @@ -21,5 +21,6 @@ CONFIG_DFU_RAM=y
> CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
> CONFIG_USB_EHCI_HCD=y
> CONFIG_USB_MUSB_GADGET=y
> +CONFIG_FASTBOOT_FLASH_MMC_DEV=1
Your commit doesn't make any sense: the SinaA33 and the Lime2 both
have the eMMC on MMC2, and you claim you want to update the default to
point to MMC2, but you're changing both these boards to point to MMC1
instead?
> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
> CONFIG_USB_FUNCTION_MASS_STORAGE=y
> diff --git a/configs/amarula_a64_relic_defconfig b/configs/amarula_a64_relic_defconfig
> index b72cbfabc6..caeb3f6008 100644
> --- a/configs/amarula_a64_relic_defconfig
> +++ b/configs/amarula_a64_relic_defconfig
> @@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic"
> # CONFIG_SPL_DOS_PARTITION is not set
> # CONFIG_SPL_EFI_PARTITION is not set
> CONFIG_USB_MUSB_GADGET=y
> +CONFIG_FASTBOOT_FLASH_MMC_DEV=0
> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
> diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
> index bc25ea1d9c..4a1bfd119c 100644
> --- a/drivers/fastboot/Kconfig
> +++ b/drivers/fastboot/Kconfig
> @@ -88,7 +88,8 @@ config FASTBOOT_FLASH_MMC_DEV
> int "Define FASTBOOT MMC FLASH default device"
> depends on FASTBOOT_FLASH_MMC
> default 0 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
> - default 1 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
> + default 1 if ARCH_SUNXI && !DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
> + default 2 if ARCH_SUNXI && DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
It'd be better to be fixed properly, instead of just relying on a
broken index.
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [U-Boot] [PATCH 21/25] fastboot: sunxi: Update fastboot mmc default device
2018-07-16 9:46 ` Maxime Ripard
@ 2018-07-16 10:12 ` Jagan Teki
2018-07-16 11:11 ` Alex Kiernan
2018-07-17 11:56 ` Maxime Ripard
0 siblings, 2 replies; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 10:12 UTC (permalink / raw)
To: u-boot
On Mon, Jul 16, 2018 at 3:16 PM, Maxime Ripard
<maxime.ripard@bootlin.com> wrote:
> On Mon, Jul 16, 2018 at 01:49:52PM +0530, Jagan Teki wrote:
>> Usually eMMC is default env fat device for environment,
>> if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc
>> device as 1. but with DM_MMC it can be more possible to
>> probe eMMC as device 2 since for most of the sunxi platforms
>> eMMC is configured mmc2.
>>
>> So update the fastboot mmc default device as 2 if DM_MMC and
>> MMC_SUNXI_SLOT_EXTRA != 1 slot is 2 defined but some boards
>> may not use all possible mmc devices or partly disabled in DT,
>> for those update the device in board specific defconfig.
>>
>> Cc: Olliver Schinagl <oliver@schinagl.nl>
>> Cc: Chen-Yu Tsai <wens@csie.org>
>> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>> ---
>> configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
>> configs/Sinlinx_SinA33_defconfig | 1 +
>> configs/amarula_a64_relic_defconfig | 1 +
>> drivers/fastboot/Kconfig | 3 ++-
>> 4 files changed, 5 insertions(+), 1 deletion(-)
>>
>> diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
>> index 5657fc2594..20ea254191 100644
>> --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
>> +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
>> @@ -29,4 +29,5 @@ CONFIG_AXP_ALDO4_VOLT=2800
>> CONFIG_SCSI=y
>> CONFIG_USB_EHCI_HCD=y
>> CONFIG_USB_MUSB_GADGET=y
>> +CONFIG_FASTBOOT_FLASH_MMC_DEV=1
>> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
>> diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
>> index 394534b8b5..7841219a65 100644
>> --- a/configs/Sinlinx_SinA33_defconfig
>> +++ b/configs/Sinlinx_SinA33_defconfig
>> @@ -21,5 +21,6 @@ CONFIG_DFU_RAM=y
>> CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
>> CONFIG_USB_EHCI_HCD=y
>> CONFIG_USB_MUSB_GADGET=y
>> +CONFIG_FASTBOOT_FLASH_MMC_DEV=1
>
> Your commit doesn't make any sense: the SinaA33 and the Lime2 both
> have the eMMC on MMC2, and you claim you want to update the default to
> point to MMC2, but you're changing both these boards to point to MMC1
> instead?
If DM_MMC and SLOT != 1 => default device 2 which is updated by
kconfig, this is with all relevant mmc nodes are enabled
but these two boards mmc1 is not enabled so emmc will detected in device 1
>
>> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
>> CONFIG_USB_FUNCTION_MASS_STORAGE=y
>> diff --git a/configs/amarula_a64_relic_defconfig b/configs/amarula_a64_relic_defconfig
>> index b72cbfabc6..caeb3f6008 100644
>> --- a/configs/amarula_a64_relic_defconfig
>> +++ b/configs/amarula_a64_relic_defconfig
>> @@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic"
>> # CONFIG_SPL_DOS_PARTITION is not set
>> # CONFIG_SPL_EFI_PARTITION is not set
>> CONFIG_USB_MUSB_GADGET=y
>> +CONFIG_FASTBOOT_FLASH_MMC_DEV=0
>> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
>> diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
>> index bc25ea1d9c..4a1bfd119c 100644
>> --- a/drivers/fastboot/Kconfig
>> +++ b/drivers/fastboot/Kconfig
>> @@ -88,7 +88,8 @@ config FASTBOOT_FLASH_MMC_DEV
>> int "Define FASTBOOT MMC FLASH default device"
>> depends on FASTBOOT_FLASH_MMC
>> default 0 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
>> - default 1 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
>> + default 1 if ARCH_SUNXI && !DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
>> + default 2 if ARCH_SUNXI && DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
>
> It'd be better to be fixed properly, instead of just relying on a
> broken index.
I don't think we can't do anything with this now, since this INDEX
more rely on SPL for pinctrl enablement. if you have any suggestion
please share.
^ permalink raw reply [flat|nested] 59+ messages in thread
* [U-Boot] [PATCH 21/25] fastboot: sunxi: Update fastboot mmc default device
2018-07-16 10:12 ` Jagan Teki
@ 2018-07-16 11:11 ` Alex Kiernan
2018-07-17 11:57 ` Maxime Ripard
2018-07-17 11:56 ` Maxime Ripard
1 sibling, 1 reply; 59+ messages in thread
From: Alex Kiernan @ 2018-07-16 11:11 UTC (permalink / raw)
To: u-boot
On Mon, Jul 16, 2018 at 11:13 AM Jagan Teki <jagannadh.teki@gmail.com> wrote:
>
> On Mon, Jul 16, 2018 at 3:16 PM, Maxime Ripard
> <maxime.ripard@bootlin.com> wrote:
> > On Mon, Jul 16, 2018 at 01:49:52PM +0530, Jagan Teki wrote:
> >> Usually eMMC is default env fat device for environment,
> >> if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc
> >> device as 1. but with DM_MMC it can be more possible to
> >> probe eMMC as device 2 since for most of the sunxi platforms
> >> eMMC is configured mmc2.
> >>
> >> So update the fastboot mmc default device as 2 if DM_MMC and
> >> MMC_SUNXI_SLOT_EXTRA != 1 slot is 2 defined but some boards
> >> may not use all possible mmc devices or partly disabled in DT,
> >> for those update the device in board specific defconfig.
> >>
> >> Cc: Olliver Schinagl <oliver@schinagl.nl>
> >> Cc: Chen-Yu Tsai <wens@csie.org>
> >> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> >> ---
> >> configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
> >> configs/Sinlinx_SinA33_defconfig | 1 +
> >> configs/amarula_a64_relic_defconfig | 1 +
> >> drivers/fastboot/Kconfig | 3 ++-
> >> 4 files changed, 5 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> >> index 5657fc2594..20ea254191 100644
> >> --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> >> +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> >> @@ -29,4 +29,5 @@ CONFIG_AXP_ALDO4_VOLT=2800
> >> CONFIG_SCSI=y
> >> CONFIG_USB_EHCI_HCD=y
> >> CONFIG_USB_MUSB_GADGET=y
> >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=1
> >> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
> >> diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
> >> index 394534b8b5..7841219a65 100644
> >> --- a/configs/Sinlinx_SinA33_defconfig
> >> +++ b/configs/Sinlinx_SinA33_defconfig
> >> @@ -21,5 +21,6 @@ CONFIG_DFU_RAM=y
> >> CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
> >> CONFIG_USB_EHCI_HCD=y
> >> CONFIG_USB_MUSB_GADGET=y
> >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=1
> >
> > Your commit doesn't make any sense: the SinaA33 and the Lime2 both
> > have the eMMC on MMC2, and you claim you want to update the default to
> > point to MMC2, but you're changing both these boards to point to MMC1
> > instead?
>
> If DM_MMC and SLOT != 1 => default device 2 which is updated by
> kconfig, this is with all relevant mmc nodes are enabled
> but these two boards mmc1 is not enabled so emmc will detected in device 1
>
> >
> >> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
> >> CONFIG_USB_FUNCTION_MASS_STORAGE=y
> >> diff --git a/configs/amarula_a64_relic_defconfig b/configs/amarula_a64_relic_defconfig
> >> index b72cbfabc6..caeb3f6008 100644
> >> --- a/configs/amarula_a64_relic_defconfig
> >> +++ b/configs/amarula_a64_relic_defconfig
> >> @@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic"
> >> # CONFIG_SPL_DOS_PARTITION is not set
> >> # CONFIG_SPL_EFI_PARTITION is not set
> >> CONFIG_USB_MUSB_GADGET=y
> >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=0
> >> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
> >> diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
> >> index bc25ea1d9c..4a1bfd119c 100644
> >> --- a/drivers/fastboot/Kconfig
> >> +++ b/drivers/fastboot/Kconfig
> >> @@ -88,7 +88,8 @@ config FASTBOOT_FLASH_MMC_DEV
> >> int "Define FASTBOOT MMC FLASH default device"
> >> depends on FASTBOOT_FLASH_MMC
> >> default 0 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
> >> - default 1 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
> >> + default 1 if ARCH_SUNXI && !DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
> >> + default 2 if ARCH_SUNXI && DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
> >
> > It'd be better to be fixed properly, instead of just relying on a
> > broken index.
>
> I don't think we can't do anything with this now, since this INDEX
> more rely on SPL for pinctrl enablement. if you have any suggestion
> please share.
Would another answer (at least for this specific case) to change the
fastboot code so it doesn't need the device number in advance? Given
we get device names along the lines of 'mmcsda1', we could parse out
the 'a' to figure out the device number (and then use the alias code
so your board can expose a portable name).
--
Alex Kiernan
^ permalink raw reply [flat|nested] 59+ messages in thread
* [U-Boot] [PATCH 21/25] fastboot: sunxi: Update fastboot mmc default device
2018-07-16 11:11 ` Alex Kiernan
@ 2018-07-17 11:57 ` Maxime Ripard
2018-07-18 19:15 ` Alex Kiernan
0 siblings, 1 reply; 59+ messages in thread
From: Maxime Ripard @ 2018-07-17 11:57 UTC (permalink / raw)
To: u-boot
On Mon, Jul 16, 2018 at 12:11:59PM +0100, Alex Kiernan wrote:
> On Mon, Jul 16, 2018 at 11:13 AM Jagan Teki <jagannadh.teki@gmail.com> wrote:
> >
> > On Mon, Jul 16, 2018 at 3:16 PM, Maxime Ripard
> > <maxime.ripard@bootlin.com> wrote:
> > > On Mon, Jul 16, 2018 at 01:49:52PM +0530, Jagan Teki wrote:
> > >> Usually eMMC is default env fat device for environment,
> > >> if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc
> > >> device as 1. but with DM_MMC it can be more possible to
> > >> probe eMMC as device 2 since for most of the sunxi platforms
> > >> eMMC is configured mmc2.
> > >>
> > >> So update the fastboot mmc default device as 2 if DM_MMC and
> > >> MMC_SUNXI_SLOT_EXTRA != 1 slot is 2 defined but some boards
> > >> may not use all possible mmc devices or partly disabled in DT,
> > >> for those update the device in board specific defconfig.
> > >>
> > >> Cc: Olliver Schinagl <oliver@schinagl.nl>
> > >> Cc: Chen-Yu Tsai <wens@csie.org>
> > >> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> > >> ---
> > >> configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
> > >> configs/Sinlinx_SinA33_defconfig | 1 +
> > >> configs/amarula_a64_relic_defconfig | 1 +
> > >> drivers/fastboot/Kconfig | 3 ++-
> > >> 4 files changed, 5 insertions(+), 1 deletion(-)
> > >>
> > >> diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> > >> index 5657fc2594..20ea254191 100644
> > >> --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> > >> +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> > >> @@ -29,4 +29,5 @@ CONFIG_AXP_ALDO4_VOLT=2800
> > >> CONFIG_SCSI=y
> > >> CONFIG_USB_EHCI_HCD=y
> > >> CONFIG_USB_MUSB_GADGET=y
> > >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=1
> > >> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
> > >> diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
> > >> index 394534b8b5..7841219a65 100644
> > >> --- a/configs/Sinlinx_SinA33_defconfig
> > >> +++ b/configs/Sinlinx_SinA33_defconfig
> > >> @@ -21,5 +21,6 @@ CONFIG_DFU_RAM=y
> > >> CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
> > >> CONFIG_USB_EHCI_HCD=y
> > >> CONFIG_USB_MUSB_GADGET=y
> > >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=1
> > >
> > > Your commit doesn't make any sense: the SinaA33 and the Lime2 both
> > > have the eMMC on MMC2, and you claim you want to update the default to
> > > point to MMC2, but you're changing both these boards to point to MMC1
> > > instead?
> >
> > If DM_MMC and SLOT != 1 => default device 2 which is updated by
> > kconfig, this is with all relevant mmc nodes are enabled
> > but these two boards mmc1 is not enabled so emmc will detected in device 1
> >
> > >
> > >> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
> > >> CONFIG_USB_FUNCTION_MASS_STORAGE=y
> > >> diff --git a/configs/amarula_a64_relic_defconfig b/configs/amarula_a64_relic_defconfig
> > >> index b72cbfabc6..caeb3f6008 100644
> > >> --- a/configs/amarula_a64_relic_defconfig
> > >> +++ b/configs/amarula_a64_relic_defconfig
> > >> @@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic"
> > >> # CONFIG_SPL_DOS_PARTITION is not set
> > >> # CONFIG_SPL_EFI_PARTITION is not set
> > >> CONFIG_USB_MUSB_GADGET=y
> > >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=0
> > >> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
> > >> diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
> > >> index bc25ea1d9c..4a1bfd119c 100644
> > >> --- a/drivers/fastboot/Kconfig
> > >> +++ b/drivers/fastboot/Kconfig
> > >> @@ -88,7 +88,8 @@ config FASTBOOT_FLASH_MMC_DEV
> > >> int "Define FASTBOOT MMC FLASH default device"
> > >> depends on FASTBOOT_FLASH_MMC
> > >> default 0 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
> > >> - default 1 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
> > >> + default 1 if ARCH_SUNXI && !DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
> > >> + default 2 if ARCH_SUNXI && DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
> > >
> > > It'd be better to be fixed properly, instead of just relying on a
> > > broken index.
> >
> > I don't think we can't do anything with this now, since this INDEX
> > more rely on SPL for pinctrl enablement. if you have any suggestion
> > please share.
>
> Would another answer (at least for this specific case) to change the
> fastboot code so it doesn't need the device number in advance? Given
> we get device names along the lines of 'mmcsda1', we could parse out
> the 'a' to figure out the device number (and then use the alias code
> so your board can expose a portable name).
That sounds like a pretty good solution. I guess we would have some
corner cases when we have a NAND and an MMC card for example that can
be flashed using fastboot, but I'm not sure we have boards in that
setup at the moment (for Allwinner SoCs at least).
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [U-Boot] [PATCH 21/25] fastboot: sunxi: Update fastboot mmc default device
2018-07-17 11:57 ` Maxime Ripard
@ 2018-07-18 19:15 ` Alex Kiernan
2018-07-19 13:26 ` Maxime Ripard
0 siblings, 1 reply; 59+ messages in thread
From: Alex Kiernan @ 2018-07-18 19:15 UTC (permalink / raw)
To: u-boot
On Tue, Jul 17, 2018 at 12:57 PM Maxime Ripard
<maxime.ripard@bootlin.com> wrote:
>
> On Mon, Jul 16, 2018 at 12:11:59PM +0100, Alex Kiernan wrote:
> > On Mon, Jul 16, 2018 at 11:13 AM Jagan Teki <jagannadh.teki@gmail.com> wrote:
> > >
> > > On Mon, Jul 16, 2018 at 3:16 PM, Maxime Ripard
> > > <maxime.ripard@bootlin.com> wrote:
> > > > On Mon, Jul 16, 2018 at 01:49:52PM +0530, Jagan Teki wrote:
> > > >> Usually eMMC is default env fat device for environment,
> > > >> if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc
> > > >> device as 1. but with DM_MMC it can be more possible to
> > > >> probe eMMC as device 2 since for most of the sunxi platforms
> > > >> eMMC is configured mmc2.
> > > >>
> > > >> So update the fastboot mmc default device as 2 if DM_MMC and
> > > >> MMC_SUNXI_SLOT_EXTRA != 1 slot is 2 defined but some boards
> > > >> may not use all possible mmc devices or partly disabled in DT,
> > > >> for those update the device in board specific defconfig.
> > > >>
> > > >> Cc: Olliver Schinagl <oliver@schinagl.nl>
> > > >> Cc: Chen-Yu Tsai <wens@csie.org>
> > > >> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> > > >> ---
> > > >> configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
> > > >> configs/Sinlinx_SinA33_defconfig | 1 +
> > > >> configs/amarula_a64_relic_defconfig | 1 +
> > > >> drivers/fastboot/Kconfig | 3 ++-
> > > >> 4 files changed, 5 insertions(+), 1 deletion(-)
> > > >>
> > > >> diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> > > >> index 5657fc2594..20ea254191 100644
> > > >> --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> > > >> +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> > > >> @@ -29,4 +29,5 @@ CONFIG_AXP_ALDO4_VOLT=2800
> > > >> CONFIG_SCSI=y
> > > >> CONFIG_USB_EHCI_HCD=y
> > > >> CONFIG_USB_MUSB_GADGET=y
> > > >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=1
> > > >> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
> > > >> diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
> > > >> index 394534b8b5..7841219a65 100644
> > > >> --- a/configs/Sinlinx_SinA33_defconfig
> > > >> +++ b/configs/Sinlinx_SinA33_defconfig
> > > >> @@ -21,5 +21,6 @@ CONFIG_DFU_RAM=y
> > > >> CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
> > > >> CONFIG_USB_EHCI_HCD=y
> > > >> CONFIG_USB_MUSB_GADGET=y
> > > >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=1
> > > >
> > > > Your commit doesn't make any sense: the SinaA33 and the Lime2 both
> > > > have the eMMC on MMC2, and you claim you want to update the default to
> > > > point to MMC2, but you're changing both these boards to point to MMC1
> > > > instead?
> > >
> > > If DM_MMC and SLOT != 1 => default device 2 which is updated by
> > > kconfig, this is with all relevant mmc nodes are enabled
> > > but these two boards mmc1 is not enabled so emmc will detected in device 1
> > >
> > > >
> > > >> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
> > > >> CONFIG_USB_FUNCTION_MASS_STORAGE=y
> > > >> diff --git a/configs/amarula_a64_relic_defconfig b/configs/amarula_a64_relic_defconfig
> > > >> index b72cbfabc6..caeb3f6008 100644
> > > >> --- a/configs/amarula_a64_relic_defconfig
> > > >> +++ b/configs/amarula_a64_relic_defconfig
> > > >> @@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic"
> > > >> # CONFIG_SPL_DOS_PARTITION is not set
> > > >> # CONFIG_SPL_EFI_PARTITION is not set
> > > >> CONFIG_USB_MUSB_GADGET=y
> > > >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=0
> > > >> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
> > > >> diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
> > > >> index bc25ea1d9c..4a1bfd119c 100644
> > > >> --- a/drivers/fastboot/Kconfig
> > > >> +++ b/drivers/fastboot/Kconfig
> > > >> @@ -88,7 +88,8 @@ config FASTBOOT_FLASH_MMC_DEV
> > > >> int "Define FASTBOOT MMC FLASH default device"
> > > >> depends on FASTBOOT_FLASH_MMC
> > > >> default 0 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
> > > >> - default 1 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
> > > >> + default 1 if ARCH_SUNXI && !DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
> > > >> + default 2 if ARCH_SUNXI && DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
> > > >
> > > > It'd be better to be fixed properly, instead of just relying on a
> > > > broken index.
> > >
> > > I don't think we can't do anything with this now, since this INDEX
> > > more rely on SPL for pinctrl enablement. if you have any suggestion
> > > please share.
> >
> > Would another answer (at least for this specific case) to change the
> > fastboot code so it doesn't need the device number in advance? Given
> > we get device names along the lines of 'mmcsda1', we could parse out
> > the 'a' to figure out the device number (and then use the alias code
> > so your board can expose a portable name).
>
> That sounds like a pretty good solution. I guess we would have some
> corner cases when we have a NAND and an MMC card for example that can
> be flashed using fastboot, but I'm not sure we have boards in that
> setup at the moment (for Allwinner SoCs at least).
>
It's not something I need right now, but having spent so much time
refactoring the fastboot code I'd like to get to this! Support for
`getvar all` is also on my todo list.
The NAND stuff is a good call, I'm not sure how that fits in (not
least not having a board which has a NAND part).
--
Alex Kiernan
^ permalink raw reply [flat|nested] 59+ messages in thread
* [U-Boot] [PATCH 21/25] fastboot: sunxi: Update fastboot mmc default device
2018-07-18 19:15 ` Alex Kiernan
@ 2018-07-19 13:26 ` Maxime Ripard
2018-07-19 18:11 ` Jagan Teki
2018-07-19 18:43 ` Alex Kiernan
0 siblings, 2 replies; 59+ messages in thread
From: Maxime Ripard @ 2018-07-19 13:26 UTC (permalink / raw)
To: u-boot
On Wed, Jul 18, 2018 at 08:15:23PM +0100, Alex Kiernan wrote:
> On Tue, Jul 17, 2018 at 12:57 PM Maxime Ripard
> <maxime.ripard@bootlin.com> wrote:
> >
> > On Mon, Jul 16, 2018 at 12:11:59PM +0100, Alex Kiernan wrote:
> > > On Mon, Jul 16, 2018 at 11:13 AM Jagan Teki <jagannadh.teki@gmail.com> wrote:
> > > >
> > > > On Mon, Jul 16, 2018 at 3:16 PM, Maxime Ripard
> > > > <maxime.ripard@bootlin.com> wrote:
> > > > > On Mon, Jul 16, 2018 at 01:49:52PM +0530, Jagan Teki wrote:
> > > > >> Usually eMMC is default env fat device for environment,
> > > > >> if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc
> > > > >> device as 1. but with DM_MMC it can be more possible to
> > > > >> probe eMMC as device 2 since for most of the sunxi platforms
> > > > >> eMMC is configured mmc2.
> > > > >>
> > > > >> So update the fastboot mmc default device as 2 if DM_MMC and
> > > > >> MMC_SUNXI_SLOT_EXTRA != 1 slot is 2 defined but some boards
> > > > >> may not use all possible mmc devices or partly disabled in DT,
> > > > >> for those update the device in board specific defconfig.
> > > > >>
> > > > >> Cc: Olliver Schinagl <oliver@schinagl.nl>
> > > > >> Cc: Chen-Yu Tsai <wens@csie.org>
> > > > >> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> > > > >> ---
> > > > >> configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
> > > > >> configs/Sinlinx_SinA33_defconfig | 1 +
> > > > >> configs/amarula_a64_relic_defconfig | 1 +
> > > > >> drivers/fastboot/Kconfig | 3 ++-
> > > > >> 4 files changed, 5 insertions(+), 1 deletion(-)
> > > > >>
> > > > >> diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> > > > >> index 5657fc2594..20ea254191 100644
> > > > >> --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> > > > >> +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> > > > >> @@ -29,4 +29,5 @@ CONFIG_AXP_ALDO4_VOLT=2800
> > > > >> CONFIG_SCSI=y
> > > > >> CONFIG_USB_EHCI_HCD=y
> > > > >> CONFIG_USB_MUSB_GADGET=y
> > > > >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=1
> > > > >> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
> > > > >> diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
> > > > >> index 394534b8b5..7841219a65 100644
> > > > >> --- a/configs/Sinlinx_SinA33_defconfig
> > > > >> +++ b/configs/Sinlinx_SinA33_defconfig
> > > > >> @@ -21,5 +21,6 @@ CONFIG_DFU_RAM=y
> > > > >> CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
> > > > >> CONFIG_USB_EHCI_HCD=y
> > > > >> CONFIG_USB_MUSB_GADGET=y
> > > > >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=1
> > > > >
> > > > > Your commit doesn't make any sense: the SinaA33 and the Lime2 both
> > > > > have the eMMC on MMC2, and you claim you want to update the default to
> > > > > point to MMC2, but you're changing both these boards to point to MMC1
> > > > > instead?
> > > >
> > > > If DM_MMC and SLOT != 1 => default device 2 which is updated by
> > > > kconfig, this is with all relevant mmc nodes are enabled
> > > > but these two boards mmc1 is not enabled so emmc will detected in device 1
> > > >
> > > > >
> > > > >> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
> > > > >> CONFIG_USB_FUNCTION_MASS_STORAGE=y
> > > > >> diff --git a/configs/amarula_a64_relic_defconfig b/configs/amarula_a64_relic_defconfig
> > > > >> index b72cbfabc6..caeb3f6008 100644
> > > > >> --- a/configs/amarula_a64_relic_defconfig
> > > > >> +++ b/configs/amarula_a64_relic_defconfig
> > > > >> @@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic"
> > > > >> # CONFIG_SPL_DOS_PARTITION is not set
> > > > >> # CONFIG_SPL_EFI_PARTITION is not set
> > > > >> CONFIG_USB_MUSB_GADGET=y
> > > > >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=0
> > > > >> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
> > > > >> diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
> > > > >> index bc25ea1d9c..4a1bfd119c 100644
> > > > >> --- a/drivers/fastboot/Kconfig
> > > > >> +++ b/drivers/fastboot/Kconfig
> > > > >> @@ -88,7 +88,8 @@ config FASTBOOT_FLASH_MMC_DEV
> > > > >> int "Define FASTBOOT MMC FLASH default device"
> > > > >> depends on FASTBOOT_FLASH_MMC
> > > > >> default 0 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
> > > > >> - default 1 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
> > > > >> + default 1 if ARCH_SUNXI && !DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
> > > > >> + default 2 if ARCH_SUNXI && DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
> > > > >
> > > > > It'd be better to be fixed properly, instead of just relying on a
> > > > > broken index.
> > > >
> > > > I don't think we can't do anything with this now, since this INDEX
> > > > more rely on SPL for pinctrl enablement. if you have any suggestion
> > > > please share.
> > >
> > > Would another answer (at least for this specific case) to change the
> > > fastboot code so it doesn't need the device number in advance? Given
> > > we get device names along the lines of 'mmcsda1', we could parse out
> > > the 'a' to figure out the device number (and then use the alias code
> > > so your board can expose a portable name).
> >
> > That sounds like a pretty good solution. I guess we would have some
> > corner cases when we have a NAND and an MMC card for example that can
> > be flashed using fastboot, but I'm not sure we have boards in that
> > setup at the moment (for Allwinner SoCs at least).
> >
>
> It's not something I need right now, but having spent so much time
> refactoring the fastboot code I'd like to get to this! Support for
> `getvar all` is also on my todo list.
>
> The NAND stuff is a good call, I'm not sure how that fits in (not
> least not having a board which has a NAND part).
Maybe we can hack something at the partition level though: instead of
having the partition name itself, what about prefixing it by the
device name? ie having something like mmc1:rootfs and nand0:rootfs, as
partition name.
maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [U-Boot] [PATCH 21/25] fastboot: sunxi: Update fastboot mmc default device
2018-07-19 13:26 ` Maxime Ripard
@ 2018-07-19 18:11 ` Jagan Teki
2018-07-20 7:39 ` Maxime Ripard
2018-07-19 18:43 ` Alex Kiernan
1 sibling, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2018-07-19 18:11 UTC (permalink / raw)
To: u-boot
On Thu, Jul 19, 2018 at 6:56 PM, Maxime Ripard
<maxime.ripard@bootlin.com> wrote:
> On Wed, Jul 18, 2018 at 08:15:23PM +0100, Alex Kiernan wrote:
>> On Tue, Jul 17, 2018 at 12:57 PM Maxime Ripard
>> <maxime.ripard@bootlin.com> wrote:
>> >
>> > On Mon, Jul 16, 2018 at 12:11:59PM +0100, Alex Kiernan wrote:
>> > > On Mon, Jul 16, 2018 at 11:13 AM Jagan Teki <jagannadh.teki@gmail.com> wrote:
>> > > >
>> > > > On Mon, Jul 16, 2018 at 3:16 PM, Maxime Ripard
>> > > > <maxime.ripard@bootlin.com> wrote:
>> > > > > On Mon, Jul 16, 2018 at 01:49:52PM +0530, Jagan Teki wrote:
>> > > > >> Usually eMMC is default env fat device for environment,
>> > > > >> if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc
>> > > > >> device as 1. but with DM_MMC it can be more possible to
>> > > > >> probe eMMC as device 2 since for most of the sunxi platforms
>> > > > >> eMMC is configured mmc2.
>> > > > >>
>> > > > >> So update the fastboot mmc default device as 2 if DM_MMC and
>> > > > >> MMC_SUNXI_SLOT_EXTRA != 1 slot is 2 defined but some boards
>> > > > >> may not use all possible mmc devices or partly disabled in DT,
>> > > > >> for those update the device in board specific defconfig.
>> > > > >>
>> > > > >> Cc: Olliver Schinagl <oliver@schinagl.nl>
>> > > > >> Cc: Chen-Yu Tsai <wens@csie.org>
>> > > > >> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>> > > > >> ---
>> > > > >> configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
>> > > > >> configs/Sinlinx_SinA33_defconfig | 1 +
>> > > > >> configs/amarula_a64_relic_defconfig | 1 +
>> > > > >> drivers/fastboot/Kconfig | 3 ++-
>> > > > >> 4 files changed, 5 insertions(+), 1 deletion(-)
>> > > > >>
>> > > > >> diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
>> > > > >> index 5657fc2594..20ea254191 100644
>> > > > >> --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
>> > > > >> +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
>> > > > >> @@ -29,4 +29,5 @@ CONFIG_AXP_ALDO4_VOLT=2800
>> > > > >> CONFIG_SCSI=y
>> > > > >> CONFIG_USB_EHCI_HCD=y
>> > > > >> CONFIG_USB_MUSB_GADGET=y
>> > > > >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=1
>> > > > >> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
>> > > > >> diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
>> > > > >> index 394534b8b5..7841219a65 100644
>> > > > >> --- a/configs/Sinlinx_SinA33_defconfig
>> > > > >> +++ b/configs/Sinlinx_SinA33_defconfig
>> > > > >> @@ -21,5 +21,6 @@ CONFIG_DFU_RAM=y
>> > > > >> CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
>> > > > >> CONFIG_USB_EHCI_HCD=y
>> > > > >> CONFIG_USB_MUSB_GADGET=y
>> > > > >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=1
>> > > > >
>> > > > > Your commit doesn't make any sense: the SinaA33 and the Lime2 both
>> > > > > have the eMMC on MMC2, and you claim you want to update the default to
>> > > > > point to MMC2, but you're changing both these boards to point to MMC1
>> > > > > instead?
>> > > >
>> > > > If DM_MMC and SLOT != 1 => default device 2 which is updated by
>> > > > kconfig, this is with all relevant mmc nodes are enabled
>> > > > but these two boards mmc1 is not enabled so emmc will detected in device 1
>> > > >
>> > > > >
>> > > > >> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
>> > > > >> CONFIG_USB_FUNCTION_MASS_STORAGE=y
>> > > > >> diff --git a/configs/amarula_a64_relic_defconfig b/configs/amarula_a64_relic_defconfig
>> > > > >> index b72cbfabc6..caeb3f6008 100644
>> > > > >> --- a/configs/amarula_a64_relic_defconfig
>> > > > >> +++ b/configs/amarula_a64_relic_defconfig
>> > > > >> @@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic"
>> > > > >> # CONFIG_SPL_DOS_PARTITION is not set
>> > > > >> # CONFIG_SPL_EFI_PARTITION is not set
>> > > > >> CONFIG_USB_MUSB_GADGET=y
>> > > > >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=0
>> > > > >> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
>> > > > >> diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
>> > > > >> index bc25ea1d9c..4a1bfd119c 100644
>> > > > >> --- a/drivers/fastboot/Kconfig
>> > > > >> +++ b/drivers/fastboot/Kconfig
>> > > > >> @@ -88,7 +88,8 @@ config FASTBOOT_FLASH_MMC_DEV
>> > > > >> int "Define FASTBOOT MMC FLASH default device"
>> > > > >> depends on FASTBOOT_FLASH_MMC
>> > > > >> default 0 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
>> > > > >> - default 1 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
>> > > > >> + default 1 if ARCH_SUNXI && !DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
>> > > > >> + default 2 if ARCH_SUNXI && DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
>> > > > >
>> > > > > It'd be better to be fixed properly, instead of just relying on a
>> > > > > broken index.
>> > > >
>> > > > I don't think we can't do anything with this now, since this INDEX
>> > > > more rely on SPL for pinctrl enablement. if you have any suggestion
>> > > > please share.
>> > >
>> > > Would another answer (at least for this specific case) to change the
>> > > fastboot code so it doesn't need the device number in advance? Given
>> > > we get device names along the lines of 'mmcsda1', we could parse out
>> > > the 'a' to figure out the device number (and then use the alias code
>> > > so your board can expose a portable name).
>> >
>> > That sounds like a pretty good solution. I guess we would have some
>> > corner cases when we have a NAND and an MMC card for example that can
>> > be flashed using fastboot, but I'm not sure we have boards in that
>> > setup at the moment (for Allwinner SoCs at least).
>> >
>>
>> It's not something I need right now, but having spent so much time
>> refactoring the fastboot code I'd like to get to this! Support for
>> `getvar all` is also on my todo list.
>>
>> The NAND stuff is a good call, I'm not sure how that fits in (not
>> least not having a board which has a NAND part).
>
> Maybe we can hack something at the partition level though: instead of
> having the partition name itself, what about prefixing it by the
> device name? ie having something like mmc1:rootfs and nand0:rootfs, as
> partition name.
How about giving an input during command 'fastboot <controller>
[dev_type] <dev[:part]>' it can be fastboot 0 mmc 1 similar like ums
did 'ums 0 mmc 1'
^ permalink raw reply [flat|nested] 59+ messages in thread
* [U-Boot] [PATCH 21/25] fastboot: sunxi: Update fastboot mmc default device
2018-07-19 18:11 ` Jagan Teki
@ 2018-07-20 7:39 ` Maxime Ripard
0 siblings, 0 replies; 59+ messages in thread
From: Maxime Ripard @ 2018-07-20 7:39 UTC (permalink / raw)
To: u-boot
On Thu, Jul 19, 2018 at 11:41:10PM +0530, Jagan Teki wrote:
> On Thu, Jul 19, 2018 at 6:56 PM, Maxime Ripard
> <maxime.ripard@bootlin.com> wrote:
> > On Wed, Jul 18, 2018 at 08:15:23PM +0100, Alex Kiernan wrote:
> >> On Tue, Jul 17, 2018 at 12:57 PM Maxime Ripard
> >> <maxime.ripard@bootlin.com> wrote:
> >> >
> >> > On Mon, Jul 16, 2018 at 12:11:59PM +0100, Alex Kiernan wrote:
> >> > > On Mon, Jul 16, 2018 at 11:13 AM Jagan Teki <jagannadh.teki@gmail.com> wrote:
> >> > > >
> >> > > > On Mon, Jul 16, 2018 at 3:16 PM, Maxime Ripard
> >> > > > <maxime.ripard@bootlin.com> wrote:
> >> > > > > On Mon, Jul 16, 2018 at 01:49:52PM +0530, Jagan Teki wrote:
> >> > > > >> Usually eMMC is default env fat device for environment,
> >> > > > >> if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc
> >> > > > >> device as 1. but with DM_MMC it can be more possible to
> >> > > > >> probe eMMC as device 2 since for most of the sunxi platforms
> >> > > > >> eMMC is configured mmc2.
> >> > > > >>
> >> > > > >> So update the fastboot mmc default device as 2 if DM_MMC and
> >> > > > >> MMC_SUNXI_SLOT_EXTRA != 1 slot is 2 defined but some boards
> >> > > > >> may not use all possible mmc devices or partly disabled in DT,
> >> > > > >> for those update the device in board specific defconfig.
> >> > > > >>
> >> > > > >> Cc: Olliver Schinagl <oliver@schinagl.nl>
> >> > > > >> Cc: Chen-Yu Tsai <wens@csie.org>
> >> > > > >> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> >> > > > >> ---
> >> > > > >> configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
> >> > > > >> configs/Sinlinx_SinA33_defconfig | 1 +
> >> > > > >> configs/amarula_a64_relic_defconfig | 1 +
> >> > > > >> drivers/fastboot/Kconfig | 3 ++-
> >> > > > >> 4 files changed, 5 insertions(+), 1 deletion(-)
> >> > > > >>
> >> > > > >> diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> >> > > > >> index 5657fc2594..20ea254191 100644
> >> > > > >> --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> >> > > > >> +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> >> > > > >> @@ -29,4 +29,5 @@ CONFIG_AXP_ALDO4_VOLT=2800
> >> > > > >> CONFIG_SCSI=y
> >> > > > >> CONFIG_USB_EHCI_HCD=y
> >> > > > >> CONFIG_USB_MUSB_GADGET=y
> >> > > > >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=1
> >> > > > >> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
> >> > > > >> diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
> >> > > > >> index 394534b8b5..7841219a65 100644
> >> > > > >> --- a/configs/Sinlinx_SinA33_defconfig
> >> > > > >> +++ b/configs/Sinlinx_SinA33_defconfig
> >> > > > >> @@ -21,5 +21,6 @@ CONFIG_DFU_RAM=y
> >> > > > >> CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
> >> > > > >> CONFIG_USB_EHCI_HCD=y
> >> > > > >> CONFIG_USB_MUSB_GADGET=y
> >> > > > >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=1
> >> > > > >
> >> > > > > Your commit doesn't make any sense: the SinaA33 and the Lime2 both
> >> > > > > have the eMMC on MMC2, and you claim you want to update the default to
> >> > > > > point to MMC2, but you're changing both these boards to point to MMC1
> >> > > > > instead?
> >> > > >
> >> > > > If DM_MMC and SLOT != 1 => default device 2 which is updated by
> >> > > > kconfig, this is with all relevant mmc nodes are enabled
> >> > > > but these two boards mmc1 is not enabled so emmc will detected in device 1
> >> > > >
> >> > > > >
> >> > > > >> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
> >> > > > >> CONFIG_USB_FUNCTION_MASS_STORAGE=y
> >> > > > >> diff --git a/configs/amarula_a64_relic_defconfig b/configs/amarula_a64_relic_defconfig
> >> > > > >> index b72cbfabc6..caeb3f6008 100644
> >> > > > >> --- a/configs/amarula_a64_relic_defconfig
> >> > > > >> +++ b/configs/amarula_a64_relic_defconfig
> >> > > > >> @@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic"
> >> > > > >> # CONFIG_SPL_DOS_PARTITION is not set
> >> > > > >> # CONFIG_SPL_EFI_PARTITION is not set
> >> > > > >> CONFIG_USB_MUSB_GADGET=y
> >> > > > >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=0
> >> > > > >> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
> >> > > > >> diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
> >> > > > >> index bc25ea1d9c..4a1bfd119c 100644
> >> > > > >> --- a/drivers/fastboot/Kconfig
> >> > > > >> +++ b/drivers/fastboot/Kconfig
> >> > > > >> @@ -88,7 +88,8 @@ config FASTBOOT_FLASH_MMC_DEV
> >> > > > >> int "Define FASTBOOT MMC FLASH default device"
> >> > > > >> depends on FASTBOOT_FLASH_MMC
> >> > > > >> default 0 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
> >> > > > >> - default 1 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
> >> > > > >> + default 1 if ARCH_SUNXI && !DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
> >> > > > >> + default 2 if ARCH_SUNXI && DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
> >> > > > >
> >> > > > > It'd be better to be fixed properly, instead of just relying on a
> >> > > > > broken index.
> >> > > >
> >> > > > I don't think we can't do anything with this now, since this INDEX
> >> > > > more rely on SPL for pinctrl enablement. if you have any suggestion
> >> > > > please share.
> >> > >
> >> > > Would another answer (at least for this specific case) to change the
> >> > > fastboot code so it doesn't need the device number in advance? Given
> >> > > we get device names along the lines of 'mmcsda1', we could parse out
> >> > > the 'a' to figure out the device number (and then use the alias code
> >> > > so your board can expose a portable name).
> >> >
> >> > That sounds like a pretty good solution. I guess we would have some
> >> > corner cases when we have a NAND and an MMC card for example that can
> >> > be flashed using fastboot, but I'm not sure we have boards in that
> >> > setup at the moment (for Allwinner SoCs at least).
> >> >
> >>
> >> It's not something I need right now, but having spent so much time
> >> refactoring the fastboot code I'd like to get to this! Support for
> >> `getvar all` is also on my todo list.
> >>
> >> The NAND stuff is a good call, I'm not sure how that fits in (not
> >> least not having a board which has a NAND part).
> >
> > Maybe we can hack something at the partition level though: instead of
> > having the partition name itself, what about prefixing it by the
> > device name? ie having something like mmc1:rootfs and nand0:rootfs, as
> > partition name.
>
> How about giving an input during command 'fastboot <controller>
> [dev_type] <dev[:part]>' it can be fastboot 0 mmc 1 similar like ums
> did 'ums 0 mmc 1'
The dev ID doesn't have much sense with the DM either though.
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [U-Boot] [PATCH 21/25] fastboot: sunxi: Update fastboot mmc default device
2018-07-19 13:26 ` Maxime Ripard
2018-07-19 18:11 ` Jagan Teki
@ 2018-07-19 18:43 ` Alex Kiernan
2018-07-20 7:34 ` Maxime Ripard
1 sibling, 1 reply; 59+ messages in thread
From: Alex Kiernan @ 2018-07-19 18:43 UTC (permalink / raw)
To: u-boot
On Thu, Jul 19, 2018 at 2:26 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> On Wed, Jul 18, 2018 at 08:15:23PM +0100, Alex Kiernan wrote:
> > On Tue, Jul 17, 2018 at 12:57 PM Maxime Ripard
> > <maxime.ripard@bootlin.com> wrote:
> > >
> > > On Mon, Jul 16, 2018 at 12:11:59PM +0100, Alex Kiernan wrote:
> > > > On Mon, Jul 16, 2018 at 11:13 AM Jagan Teki <jagannadh.teki@gmail.com> wrote:
> > > > >
> > > > > On Mon, Jul 16, 2018 at 3:16 PM, Maxime Ripard
> > > > > <maxime.ripard@bootlin.com> wrote:
> > > > > > On Mon, Jul 16, 2018 at 01:49:52PM +0530, Jagan Teki wrote:
> > > > > >> Usually eMMC is default env fat device for environment,
> > > > > >> if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc
> > > > > >> device as 1. but with DM_MMC it can be more possible to
> > > > > >> probe eMMC as device 2 since for most of the sunxi platforms
> > > > > >> eMMC is configured mmc2.
> > > > > >>
> > > > > >> So update the fastboot mmc default device as 2 if DM_MMC and
> > > > > >> MMC_SUNXI_SLOT_EXTRA != 1 slot is 2 defined but some boards
> > > > > >> may not use all possible mmc devices or partly disabled in DT,
> > > > > >> for those update the device in board specific defconfig.
> > > > > >>
> > > > > >> Cc: Olliver Schinagl <oliver@schinagl.nl>
> > > > > >> Cc: Chen-Yu Tsai <wens@csie.org>
> > > > > >> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> > > > > >> ---
> > > > > >> configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
> > > > > >> configs/Sinlinx_SinA33_defconfig | 1 +
> > > > > >> configs/amarula_a64_relic_defconfig | 1 +
> > > > > >> drivers/fastboot/Kconfig | 3 ++-
> > > > > >> 4 files changed, 5 insertions(+), 1 deletion(-)
> > > > > >>
> > > > > >> diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> > > > > >> index 5657fc2594..20ea254191 100644
> > > > > >> --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> > > > > >> +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> > > > > >> @@ -29,4 +29,5 @@ CONFIG_AXP_ALDO4_VOLT=2800
> > > > > >> CONFIG_SCSI=y
> > > > > >> CONFIG_USB_EHCI_HCD=y
> > > > > >> CONFIG_USB_MUSB_GADGET=y
> > > > > >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=1
> > > > > >> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
> > > > > >> diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
> > > > > >> index 394534b8b5..7841219a65 100644
> > > > > >> --- a/configs/Sinlinx_SinA33_defconfig
> > > > > >> +++ b/configs/Sinlinx_SinA33_defconfig
> > > > > >> @@ -21,5 +21,6 @@ CONFIG_DFU_RAM=y
> > > > > >> CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
> > > > > >> CONFIG_USB_EHCI_HCD=y
> > > > > >> CONFIG_USB_MUSB_GADGET=y
> > > > > >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=1
> > > > > >
> > > > > > Your commit doesn't make any sense: the SinaA33 and the Lime2 both
> > > > > > have the eMMC on MMC2, and you claim you want to update the default to
> > > > > > point to MMC2, but you're changing both these boards to point to MMC1
> > > > > > instead?
> > > > >
> > > > > If DM_MMC and SLOT != 1 => default device 2 which is updated by
> > > > > kconfig, this is with all relevant mmc nodes are enabled
> > > > > but these two boards mmc1 is not enabled so emmc will detected in device 1
> > > > >
> > > > > >
> > > > > >> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
> > > > > >> CONFIG_USB_FUNCTION_MASS_STORAGE=y
> > > > > >> diff --git a/configs/amarula_a64_relic_defconfig b/configs/amarula_a64_relic_defconfig
> > > > > >> index b72cbfabc6..caeb3f6008 100644
> > > > > >> --- a/configs/amarula_a64_relic_defconfig
> > > > > >> +++ b/configs/amarula_a64_relic_defconfig
> > > > > >> @@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic"
> > > > > >> # CONFIG_SPL_DOS_PARTITION is not set
> > > > > >> # CONFIG_SPL_EFI_PARTITION is not set
> > > > > >> CONFIG_USB_MUSB_GADGET=y
> > > > > >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=0
> > > > > >> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
> > > > > >> diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
> > > > > >> index bc25ea1d9c..4a1bfd119c 100644
> > > > > >> --- a/drivers/fastboot/Kconfig
> > > > > >> +++ b/drivers/fastboot/Kconfig
> > > > > >> @@ -88,7 +88,8 @@ config FASTBOOT_FLASH_MMC_DEV
> > > > > >> int "Define FASTBOOT MMC FLASH default device"
> > > > > >> depends on FASTBOOT_FLASH_MMC
> > > > > >> default 0 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
> > > > > >> - default 1 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
> > > > > >> + default 1 if ARCH_SUNXI && !DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
> > > > > >> + default 2 if ARCH_SUNXI && DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
> > > > > >
> > > > > > It'd be better to be fixed properly, instead of just relying on a
> > > > > > broken index.
> > > > >
> > > > > I don't think we can't do anything with this now, since this INDEX
> > > > > more rely on SPL for pinctrl enablement. if you have any suggestion
> > > > > please share.
> > > >
> > > > Would another answer (at least for this specific case) to change the
> > > > fastboot code so it doesn't need the device number in advance? Given
> > > > we get device names along the lines of 'mmcsda1', we could parse out
> > > > the 'a' to figure out the device number (and then use the alias code
> > > > so your board can expose a portable name).
> > >
> > > That sounds like a pretty good solution. I guess we would have some
> > > corner cases when we have a NAND and an MMC card for example that can
> > > be flashed using fastboot, but I'm not sure we have boards in that
> > > setup at the moment (for Allwinner SoCs at least).
> > >
> >
> > It's not something I need right now, but having spent so much time
> > refactoring the fastboot code I'd like to get to this! Support for
> > `getvar all` is also on my todo list.
> >
> > The NAND stuff is a good call, I'm not sure how that fits in (not
> > least not having a board which has a NAND part).
>
> Maybe we can hack something at the partition level though: instead of
> having the partition name itself, what about prefixing it by the
> device name? ie having something like mmc1:rootfs and nand0:rootfs, as
> partition name.
>
Just looking at the code, I suspect NAND already works, just use the
name that mtd knows. And mmc looks trivial to implement.
I guess one question is if you want to be able to filter out which
devices you can address from the fastboot client.
--
Alex Kiernan
^ permalink raw reply [flat|nested] 59+ messages in thread
* [U-Boot] [PATCH 21/25] fastboot: sunxi: Update fastboot mmc default device
2018-07-19 18:43 ` Alex Kiernan
@ 2018-07-20 7:34 ` Maxime Ripard
0 siblings, 0 replies; 59+ messages in thread
From: Maxime Ripard @ 2018-07-20 7:34 UTC (permalink / raw)
To: u-boot
On Thu, Jul 19, 2018 at 07:43:24PM +0100, Alex Kiernan wrote:
> On Thu, Jul 19, 2018 at 2:26 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> >
> > On Wed, Jul 18, 2018 at 08:15:23PM +0100, Alex Kiernan wrote:
> > > On Tue, Jul 17, 2018 at 12:57 PM Maxime Ripard
> > > <maxime.ripard@bootlin.com> wrote:
> > > >
> > > > On Mon, Jul 16, 2018 at 12:11:59PM +0100, Alex Kiernan wrote:
> > > > > On Mon, Jul 16, 2018 at 11:13 AM Jagan Teki <jagannadh.teki@gmail.com> wrote:
> > > > > >
> > > > > > On Mon, Jul 16, 2018 at 3:16 PM, Maxime Ripard
> > > > > > <maxime.ripard@bootlin.com> wrote:
> > > > > > > On Mon, Jul 16, 2018 at 01:49:52PM +0530, Jagan Teki wrote:
> > > > > > >> Usually eMMC is default env fat device for environment,
> > > > > > >> if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc
> > > > > > >> device as 1. but with DM_MMC it can be more possible to
> > > > > > >> probe eMMC as device 2 since for most of the sunxi platforms
> > > > > > >> eMMC is configured mmc2.
> > > > > > >>
> > > > > > >> So update the fastboot mmc default device as 2 if DM_MMC and
> > > > > > >> MMC_SUNXI_SLOT_EXTRA != 1 slot is 2 defined but some boards
> > > > > > >> may not use all possible mmc devices or partly disabled in DT,
> > > > > > >> for those update the device in board specific defconfig.
> > > > > > >>
> > > > > > >> Cc: Olliver Schinagl <oliver@schinagl.nl>
> > > > > > >> Cc: Chen-Yu Tsai <wens@csie.org>
> > > > > > >> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> > > > > > >> ---
> > > > > > >> configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
> > > > > > >> configs/Sinlinx_SinA33_defconfig | 1 +
> > > > > > >> configs/amarula_a64_relic_defconfig | 1 +
> > > > > > >> drivers/fastboot/Kconfig | 3 ++-
> > > > > > >> 4 files changed, 5 insertions(+), 1 deletion(-)
> > > > > > >>
> > > > > > >> diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> > > > > > >> index 5657fc2594..20ea254191 100644
> > > > > > >> --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> > > > > > >> +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> > > > > > >> @@ -29,4 +29,5 @@ CONFIG_AXP_ALDO4_VOLT=2800
> > > > > > >> CONFIG_SCSI=y
> > > > > > >> CONFIG_USB_EHCI_HCD=y
> > > > > > >> CONFIG_USB_MUSB_GADGET=y
> > > > > > >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=1
> > > > > > >> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
> > > > > > >> diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
> > > > > > >> index 394534b8b5..7841219a65 100644
> > > > > > >> --- a/configs/Sinlinx_SinA33_defconfig
> > > > > > >> +++ b/configs/Sinlinx_SinA33_defconfig
> > > > > > >> @@ -21,5 +21,6 @@ CONFIG_DFU_RAM=y
> > > > > > >> CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
> > > > > > >> CONFIG_USB_EHCI_HCD=y
> > > > > > >> CONFIG_USB_MUSB_GADGET=y
> > > > > > >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=1
> > > > > > >
> > > > > > > Your commit doesn't make any sense: the SinaA33 and the Lime2 both
> > > > > > > have the eMMC on MMC2, and you claim you want to update the default to
> > > > > > > point to MMC2, but you're changing both these boards to point to MMC1
> > > > > > > instead?
> > > > > >
> > > > > > If DM_MMC and SLOT != 1 => default device 2 which is updated by
> > > > > > kconfig, this is with all relevant mmc nodes are enabled
> > > > > > but these two boards mmc1 is not enabled so emmc will detected in device 1
> > > > > >
> > > > > > >
> > > > > > >> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
> > > > > > >> CONFIG_USB_FUNCTION_MASS_STORAGE=y
> > > > > > >> diff --git a/configs/amarula_a64_relic_defconfig b/configs/amarula_a64_relic_defconfig
> > > > > > >> index b72cbfabc6..caeb3f6008 100644
> > > > > > >> --- a/configs/amarula_a64_relic_defconfig
> > > > > > >> +++ b/configs/amarula_a64_relic_defconfig
> > > > > > >> @@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic"
> > > > > > >> # CONFIG_SPL_DOS_PARTITION is not set
> > > > > > >> # CONFIG_SPL_EFI_PARTITION is not set
> > > > > > >> CONFIG_USB_MUSB_GADGET=y
> > > > > > >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=0
> > > > > > >> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
> > > > > > >> diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
> > > > > > >> index bc25ea1d9c..4a1bfd119c 100644
> > > > > > >> --- a/drivers/fastboot/Kconfig
> > > > > > >> +++ b/drivers/fastboot/Kconfig
> > > > > > >> @@ -88,7 +88,8 @@ config FASTBOOT_FLASH_MMC_DEV
> > > > > > >> int "Define FASTBOOT MMC FLASH default device"
> > > > > > >> depends on FASTBOOT_FLASH_MMC
> > > > > > >> default 0 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
> > > > > > >> - default 1 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
> > > > > > >> + default 1 if ARCH_SUNXI && !DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
> > > > > > >> + default 2 if ARCH_SUNXI && DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
> > > > > > >
> > > > > > > It'd be better to be fixed properly, instead of just relying on a
> > > > > > > broken index.
> > > > > >
> > > > > > I don't think we can't do anything with this now, since this INDEX
> > > > > > more rely on SPL for pinctrl enablement. if you have any suggestion
> > > > > > please share.
> > > > >
> > > > > Would another answer (at least for this specific case) to change the
> > > > > fastboot code so it doesn't need the device number in advance? Given
> > > > > we get device names along the lines of 'mmcsda1', we could parse out
> > > > > the 'a' to figure out the device number (and then use the alias code
> > > > > so your board can expose a portable name).
> > > >
> > > > That sounds like a pretty good solution. I guess we would have some
> > > > corner cases when we have a NAND and an MMC card for example that can
> > > > be flashed using fastboot, but I'm not sure we have boards in that
> > > > setup at the moment (for Allwinner SoCs at least).
> > > >
> > >
> > > It's not something I need right now, but having spent so much time
> > > refactoring the fastboot code I'd like to get to this! Support for
> > > `getvar all` is also on my todo list.
> > >
> > > The NAND stuff is a good call, I'm not sure how that fits in (not
> > > least not having a board which has a NAND part).
> >
> > Maybe we can hack something at the partition level though: instead of
> > having the partition name itself, what about prefixing it by the
> > device name? ie having something like mmc1:rootfs and nand0:rootfs, as
> > partition name.
> >
>
> Just looking at the code, I suspect NAND already works, just use the
> name that mtd knows. And mmc looks trivial to implement.
>
> I guess one question is if you want to be able to filter out which
> devices you can address from the fastboot client.
Yeah, that's what I meant. NAND definitely works as long as you stick
to partitions defined in mtdparts
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [U-Boot] [PATCH 21/25] fastboot: sunxi: Update fastboot mmc default device
2018-07-16 10:12 ` Jagan Teki
2018-07-16 11:11 ` Alex Kiernan
@ 2018-07-17 11:56 ` Maxime Ripard
1 sibling, 0 replies; 59+ messages in thread
From: Maxime Ripard @ 2018-07-17 11:56 UTC (permalink / raw)
To: u-boot
On Mon, Jul 16, 2018 at 03:42:47PM +0530, Jagan Teki wrote:
> On Mon, Jul 16, 2018 at 3:16 PM, Maxime Ripard
> <maxime.ripard@bootlin.com> wrote:
> > On Mon, Jul 16, 2018 at 01:49:52PM +0530, Jagan Teki wrote:
> >> Usually eMMC is default env fat device for environment,
> >> if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc
> >> device as 1. but with DM_MMC it can be more possible to
> >> probe eMMC as device 2 since for most of the sunxi platforms
> >> eMMC is configured mmc2.
> >>
> >> So update the fastboot mmc default device as 2 if DM_MMC and
> >> MMC_SUNXI_SLOT_EXTRA != 1 slot is 2 defined but some boards
> >> may not use all possible mmc devices or partly disabled in DT,
> >> for those update the device in board specific defconfig.
> >>
> >> Cc: Olliver Schinagl <oliver@schinagl.nl>
> >> Cc: Chen-Yu Tsai <wens@csie.org>
> >> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> >> ---
> >> configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
> >> configs/Sinlinx_SinA33_defconfig | 1 +
> >> configs/amarula_a64_relic_defconfig | 1 +
> >> drivers/fastboot/Kconfig | 3 ++-
> >> 4 files changed, 5 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> >> index 5657fc2594..20ea254191 100644
> >> --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> >> +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> >> @@ -29,4 +29,5 @@ CONFIG_AXP_ALDO4_VOLT=2800
> >> CONFIG_SCSI=y
> >> CONFIG_USB_EHCI_HCD=y
> >> CONFIG_USB_MUSB_GADGET=y
> >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=1
> >> CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
> >> diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
> >> index 394534b8b5..7841219a65 100644
> >> --- a/configs/Sinlinx_SinA33_defconfig
> >> +++ b/configs/Sinlinx_SinA33_defconfig
> >> @@ -21,5 +21,6 @@ CONFIG_DFU_RAM=y
> >> CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
> >> CONFIG_USB_EHCI_HCD=y
> >> CONFIG_USB_MUSB_GADGET=y
> >> +CONFIG_FASTBOOT_FLASH_MMC_DEV=1
> >
> > Your commit doesn't make any sense: the SinaA33 and the Lime2 both
> > have the eMMC on MMC2, and you claim you want to update the default to
> > point to MMC2, but you're changing both these boards to point to MMC1
> > instead?
>
> If DM_MMC and SLOT != 1 => default device 2 which is updated by
> kconfig, this is with all relevant mmc nodes are enabled but these
> two boards mmc1 is not enabled so emmc will detected in device 1
So it purely relies on luck and the fact that we don't have a wifi
device enabled yet? It seems pretty fragile, doesn't it?
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [U-Boot] [PATCH 22/25] env: sunxi: Update default env fat device
2018-07-16 8:19 [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Jagan Teki
` (20 preceding siblings ...)
2018-07-16 8:19 ` [U-Boot] [PATCH 21/25] fastboot: sunxi: Update fastboot mmc default device Jagan Teki
@ 2018-07-16 8:19 ` Jagan Teki
2018-07-16 9:47 ` Maxime Ripard
2018-07-16 8:19 ` [U-Boot] [PATCH 23/25] sunxi: Use mmc_bootdev=2 for MMC2 boot Jagan Teki
` (3 subsequent siblings)
25 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 8:19 UTC (permalink / raw)
To: u-boot
Usually eMMC is default env fat device for environment,
if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc
device as 1. but with DM_MMC it can be more possible to
probe eMMC as device 2 since for most of the sunxi platforms
eMMC is configured mmc2.
So update the env default device as 2 if DM_MMC and
MMC_SUNXI_SLOT_EXTRA != 1 but some boards may not use all
possible mmc devices or partly disabled in DT, for those update
the device in board specific defconfig.
Cc: Olliver Schinagl <oliver@schinagl.nl>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Marcus Cooper <codekipper@gmail.com>
Cc: Stefan Mavrodiev <stefan@olimex.com>
Cc: Paul Kocialkowski <contact@paulk.fr>
Cc: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
configs/A20-OLinuXino_MICRO-eMMC_defconfig | 1 +
configs/A20-OLinuXino_MICRO_defconfig | 1 +
configs/A20-Olimex-SOM-EVB_defconfig | 1 +
configs/A20-Olimex-SOM204-EVB-eMMC_defconfig | 1 +
configs/Mele_M3_defconfig | 1 +
configs/Orangepi_mini_defconfig | 1 +
configs/Sinlinx_SinA33_defconfig | 1 +
configs/Yones_Toptech_BD1078_defconfig | 1 +
configs/amarula_a64_relic_defconfig | 1 +
env/Kconfig | 3 ++-
11 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
index 20ea254191..98a8ceb178 100644
--- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
+++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
CONFIG_USB0_VBUS_PIN="PC17"
CONFIG_USB0_VBUS_DET="PH5"
CONFIG_I2C1_ENABLE=y
diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
index f7e7cbab0a..1552960d88 100644
--- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig
+++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
CONFIG_I2C1_ENABLE=y
CONFIG_VIDEO_VGA=y
CONFIG_SATAPWR="PB8"
diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
index 8dcbdc08f9..b5f1b7efe2 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -6,6 +6,7 @@ CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_MMC3_CD_PIN="PH11"
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
CONFIG_I2C1_ENABLE=y
CONFIG_VIDEO_VGA=y
CONFIG_SATAPWR="PB8"
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
index a06499e2d0..58f6fbad91 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -7,6 +7,7 @@ CONFIG_MMC0_CD_PIN="PH1"
CONFIG_MMC3_CD_PIN="PH0"
CONFIG_MMC3_PINS="PH"
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_USB0_VBUS_DET="PH5"
CONFIG_SATAPWR="PC3"
diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
index 3bb8c4c7e6..ac4f841c4e 100644
--- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
+++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
CONFIG_USB0_VBUS_PIN="PC17"
CONFIG_USB0_VBUS_DET="PH5"
CONFIG_I2C1_ENABLE=y
diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig
index 9f48bd91e0..93a2395aee 100644
--- a/configs/Mele_M3_defconfig
+++ b/configs/Mele_M3_defconfig
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
CONFIG_VIDEO_VGA=y
CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3"
diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig
index 46f27be254..d562273bef 100644
--- a/configs/Orangepi_mini_defconfig
+++ b/configs/Orangepi_mini_defconfig
@@ -7,6 +7,7 @@ CONFIG_MACPWR="PH23"
CONFIG_MMC0_CD_PIN="PH10"
CONFIG_MMC3_CD_PIN="PH11"
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
CONFIG_USB1_VBUS_PIN="PH26"
CONFIG_USB2_VBUS_PIN="PH22"
CONFIG_VIDEO_COMPOSITE=y
diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
index 7841219a65..061f27c9db 100644
--- a/configs/Sinlinx_SinA33_defconfig
+++ b/configs/Sinlinx_SinA33_defconfig
@@ -6,6 +6,7 @@ CONFIG_DRAM_CLK=552
CONFIG_DRAM_ZQ=15291
CONFIG_MMC0_CD_PIN="PB4"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
CONFIG_USB0_ID_DET="PH8"
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig
index c49cbcbc3c..cad5618d54 100644
--- a/configs/Yones_Toptech_BD1078_defconfig
+++ b/configs/Yones_Toptech_BD1078_defconfig
@@ -7,6 +7,7 @@ CONFIG_MMC0_CD_PIN="PH1"
CONFIG_MMC1_CD_PIN="PH2"
CONFIG_MMC1_PINS="PH"
CONFIG_MMC_SUNXI_SLOT_EXTRA=1
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
CONFIG_AXP_GPIO=y
diff --git a/configs/amarula_a64_relic_defconfig b/configs/amarula_a64_relic_defconfig
index caeb3f6008..bb5c0ff7b2 100644
--- a/configs/amarula_a64_relic_defconfig
+++ b/configs/amarula_a64_relic_defconfig
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN50I=y
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_DRAM_ODT_EN=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:auto"
# CONFIG_VIDEO_DE2 is not set
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/env/Kconfig b/env/Kconfig
index 8618376f25..2be16893b6 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -374,7 +374,8 @@ config ENV_FAT_DEVICE_AND_PART
default "0:1" if TI_COMMON_CMD_OPTIONS
default "0:auto" if ARCH_ZYNQMP
default "0:auto" if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
- default "1:auto" if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
+ default "1:auto" if ARCH_SUNXI && !DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
+ default "2:auto" if ARCH_SUNXI && DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
default "0" if ARCH_AT91
help
Define this to a string to specify the partition of the device. It can
--
2.17.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 22/25] env: sunxi: Update default env fat device
2018-07-16 8:19 ` [U-Boot] [PATCH 22/25] env: sunxi: Update default env fat device Jagan Teki
@ 2018-07-16 9:47 ` Maxime Ripard
2018-07-16 10:16 ` Jagan Teki
0 siblings, 1 reply; 59+ messages in thread
From: Maxime Ripard @ 2018-07-16 9:47 UTC (permalink / raw)
To: u-boot
On Mon, Jul 16, 2018 at 01:49:53PM +0530, Jagan Teki wrote:
> Usually eMMC is default env fat device for environment,
> if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc
> device as 1. but with DM_MMC it can be more possible to
> probe eMMC as device 2 since for most of the sunxi platforms
> eMMC is configured mmc2.
>
> So update the env default device as 2 if DM_MMC and
> MMC_SUNXI_SLOT_EXTRA != 1 but some boards may not use all
> possible mmc devices or partly disabled in DT, for those update
> the device in board specific defconfig.
>
> Cc: Olliver Schinagl <oliver@schinagl.nl>
> Cc: Hans de Goede <hdegoede@redhat.com>
> Cc: Marcus Cooper <codekipper@gmail.com>
> Cc: Stefan Mavrodiev <stefan@olimex.com>
> Cc: Paul Kocialkowski <contact@paulk.fr>
> Cc: Chen-Yu Tsai <wens@csie.org>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
> configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
> configs/A20-OLinuXino_MICRO-eMMC_defconfig | 1 +
> configs/A20-OLinuXino_MICRO_defconfig | 1 +
> configs/A20-Olimex-SOM-EVB_defconfig | 1 +
> configs/A20-Olimex-SOM204-EVB-eMMC_defconfig | 1 +
> configs/Mele_M3_defconfig | 1 +
> configs/Orangepi_mini_defconfig | 1 +
> configs/Sinlinx_SinA33_defconfig | 1 +
> configs/Yones_Toptech_BD1078_defconfig | 1 +
> configs/amarula_a64_relic_defconfig | 1 +
> env/Kconfig | 3 ++-
> 11 files changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> index 20ea254191..98a8ceb178 100644
> --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> @@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
> CONFIG_DRAM_CLK=384
> CONFIG_MMC0_CD_PIN="PH1"
> CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
> CONFIG_USB0_VBUS_PIN="PC17"
> CONFIG_USB0_VBUS_DET="PH5"
> CONFIG_I2C1_ENABLE=y
> diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
> index f7e7cbab0a..1552960d88 100644
> --- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig
> +++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
> @@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
> CONFIG_DRAM_CLK=384
> CONFIG_MMC0_CD_PIN="PH1"
> CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
> CONFIG_I2C1_ENABLE=y
> CONFIG_VIDEO_VGA=y
> CONFIG_SATAPWR="PB8"
> diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
> index 8dcbdc08f9..b5f1b7efe2 100644
> --- a/configs/A20-OLinuXino_MICRO_defconfig
> +++ b/configs/A20-OLinuXino_MICRO_defconfig
> @@ -6,6 +6,7 @@ CONFIG_DRAM_CLK=384
> CONFIG_MMC0_CD_PIN="PH1"
> CONFIG_MMC3_CD_PIN="PH11"
> CONFIG_MMC_SUNXI_SLOT_EXTRA=3
> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
> CONFIG_I2C1_ENABLE=y
> CONFIG_VIDEO_VGA=y
> CONFIG_SATAPWR="PB8"
> diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
> index a06499e2d0..58f6fbad91 100644
> --- a/configs/A20-Olimex-SOM-EVB_defconfig
> +++ b/configs/A20-Olimex-SOM-EVB_defconfig
> @@ -7,6 +7,7 @@ CONFIG_MMC0_CD_PIN="PH1"
> CONFIG_MMC3_CD_PIN="PH0"
> CONFIG_MMC3_PINS="PH"
> CONFIG_MMC_SUNXI_SLOT_EXTRA=3
> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
> CONFIG_USB0_VBUS_PIN="PB9"
> CONFIG_USB0_VBUS_DET="PH5"
> CONFIG_SATAPWR="PC3"
> diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
> index 3bb8c4c7e6..ac4f841c4e 100644
> --- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
> +++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
> @@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
> CONFIG_DRAM_CLK=384
> CONFIG_MMC0_CD_PIN="PH1"
> CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
> CONFIG_USB0_VBUS_PIN="PC17"
> CONFIG_USB0_VBUS_DET="PH5"
> CONFIG_I2C1_ENABLE=y
> diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig
> index 9f48bd91e0..93a2395aee 100644
> --- a/configs/Mele_M3_defconfig
> +++ b/configs/Mele_M3_defconfig
> @@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
> CONFIG_DRAM_CLK=384
> CONFIG_MMC0_CD_PIN="PH1"
> CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
> CONFIG_VIDEO_VGA=y
> CONFIG_VIDEO_COMPOSITE=y
> CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3"
> diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig
> index 46f27be254..d562273bef 100644
> --- a/configs/Orangepi_mini_defconfig
> +++ b/configs/Orangepi_mini_defconfig
> @@ -7,6 +7,7 @@ CONFIG_MACPWR="PH23"
> CONFIG_MMC0_CD_PIN="PH10"
> CONFIG_MMC3_CD_PIN="PH11"
> CONFIG_MMC_SUNXI_SLOT_EXTRA=3
> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
> CONFIG_USB1_VBUS_PIN="PH26"
> CONFIG_USB2_VBUS_PIN="PH22"
> CONFIG_VIDEO_COMPOSITE=y
> diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
> index 7841219a65..061f27c9db 100644
> --- a/configs/Sinlinx_SinA33_defconfig
> +++ b/configs/Sinlinx_SinA33_defconfig
> @@ -6,6 +6,7 @@ CONFIG_DRAM_CLK=552
> CONFIG_DRAM_ZQ=15291
> CONFIG_MMC0_CD_PIN="PB4"
> CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
> CONFIG_USB0_ID_DET="PH8"
> CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:3,vmode:0"
> CONFIG_VIDEO_LCD_DCLK_PHASE=0
> diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig
> index c49cbcbc3c..cad5618d54 100644
> --- a/configs/Yones_Toptech_BD1078_defconfig
> +++ b/configs/Yones_Toptech_BD1078_defconfig
> @@ -7,6 +7,7 @@ CONFIG_MMC0_CD_PIN="PH1"
> CONFIG_MMC1_CD_PIN="PH2"
> CONFIG_MMC1_PINS="PH"
> CONFIG_MMC_SUNXI_SLOT_EXTRA=1
> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
Again, you're breaking all these boards while saying you want to fix
them.
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [U-Boot] [PATCH 22/25] env: sunxi: Update default env fat device
2018-07-16 9:47 ` Maxime Ripard
@ 2018-07-16 10:16 ` Jagan Teki
2018-07-17 11:54 ` Maxime Ripard
0 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 10:16 UTC (permalink / raw)
To: u-boot
On Mon, Jul 16, 2018 at 3:17 PM, Maxime Ripard
<maxime.ripard@bootlin.com> wrote:
> On Mon, Jul 16, 2018 at 01:49:53PM +0530, Jagan Teki wrote:
>> Usually eMMC is default env fat device for environment,
>> if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc
>> device as 1. but with DM_MMC it can be more possible to
>> probe eMMC as device 2 since for most of the sunxi platforms
>> eMMC is configured mmc2.
>>
>> So update the env default device as 2 if DM_MMC and
>> MMC_SUNXI_SLOT_EXTRA != 1 but some boards may not use all
>> possible mmc devices or partly disabled in DT, for those update
>> the device in board specific defconfig.
>>
>> Cc: Olliver Schinagl <oliver@schinagl.nl>
>> Cc: Hans de Goede <hdegoede@redhat.com>
>> Cc: Marcus Cooper <codekipper@gmail.com>
>> Cc: Stefan Mavrodiev <stefan@olimex.com>
>> Cc: Paul Kocialkowski <contact@paulk.fr>
>> Cc: Chen-Yu Tsai <wens@csie.org>
>> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>> ---
>> configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
>> configs/A20-OLinuXino_MICRO-eMMC_defconfig | 1 +
>> configs/A20-OLinuXino_MICRO_defconfig | 1 +
>> configs/A20-Olimex-SOM-EVB_defconfig | 1 +
>> configs/A20-Olimex-SOM204-EVB-eMMC_defconfig | 1 +
>> configs/Mele_M3_defconfig | 1 +
>> configs/Orangepi_mini_defconfig | 1 +
>> configs/Sinlinx_SinA33_defconfig | 1 +
>> configs/Yones_Toptech_BD1078_defconfig | 1 +
>> configs/amarula_a64_relic_defconfig | 1 +
>> env/Kconfig | 3 ++-
>> 11 files changed, 12 insertions(+), 1 deletion(-)
>>
>> diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
>> index 20ea254191..98a8ceb178 100644
>> --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
>> +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
>> @@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
>> CONFIG_DRAM_CLK=384
>> CONFIG_MMC0_CD_PIN="PH1"
>> CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
>> CONFIG_USB0_VBUS_PIN="PC17"
>> CONFIG_USB0_VBUS_DET="PH5"
>> CONFIG_I2C1_ENABLE=y
>> diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
>> index f7e7cbab0a..1552960d88 100644
>> --- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig
>> +++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
>> @@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
>> CONFIG_DRAM_CLK=384
>> CONFIG_MMC0_CD_PIN="PH1"
>> CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
>> CONFIG_I2C1_ENABLE=y
>> CONFIG_VIDEO_VGA=y
>> CONFIG_SATAPWR="PB8"
>> diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
>> index 8dcbdc08f9..b5f1b7efe2 100644
>> --- a/configs/A20-OLinuXino_MICRO_defconfig
>> +++ b/configs/A20-OLinuXino_MICRO_defconfig
>> @@ -6,6 +6,7 @@ CONFIG_DRAM_CLK=384
>> CONFIG_MMC0_CD_PIN="PH1"
>> CONFIG_MMC3_CD_PIN="PH11"
>> CONFIG_MMC_SUNXI_SLOT_EXTRA=3
>> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
>> CONFIG_I2C1_ENABLE=y
>> CONFIG_VIDEO_VGA=y
>> CONFIG_SATAPWR="PB8"
>> diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
>> index a06499e2d0..58f6fbad91 100644
>> --- a/configs/A20-Olimex-SOM-EVB_defconfig
>> +++ b/configs/A20-Olimex-SOM-EVB_defconfig
>> @@ -7,6 +7,7 @@ CONFIG_MMC0_CD_PIN="PH1"
>> CONFIG_MMC3_CD_PIN="PH0"
>> CONFIG_MMC3_PINS="PH"
>> CONFIG_MMC_SUNXI_SLOT_EXTRA=3
>> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
>> CONFIG_USB0_VBUS_PIN="PB9"
>> CONFIG_USB0_VBUS_DET="PH5"
>> CONFIG_SATAPWR="PC3"
>> diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
>> index 3bb8c4c7e6..ac4f841c4e 100644
>> --- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
>> +++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
>> @@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
>> CONFIG_DRAM_CLK=384
>> CONFIG_MMC0_CD_PIN="PH1"
>> CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
>> CONFIG_USB0_VBUS_PIN="PC17"
>> CONFIG_USB0_VBUS_DET="PH5"
>> CONFIG_I2C1_ENABLE=y
>> diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig
>> index 9f48bd91e0..93a2395aee 100644
>> --- a/configs/Mele_M3_defconfig
>> +++ b/configs/Mele_M3_defconfig
>> @@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
>> CONFIG_DRAM_CLK=384
>> CONFIG_MMC0_CD_PIN="PH1"
>> CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
>> CONFIG_VIDEO_VGA=y
>> CONFIG_VIDEO_COMPOSITE=y
>> CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3"
>> diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig
>> index 46f27be254..d562273bef 100644
>> --- a/configs/Orangepi_mini_defconfig
>> +++ b/configs/Orangepi_mini_defconfig
>> @@ -7,6 +7,7 @@ CONFIG_MACPWR="PH23"
>> CONFIG_MMC0_CD_PIN="PH10"
>> CONFIG_MMC3_CD_PIN="PH11"
>> CONFIG_MMC_SUNXI_SLOT_EXTRA=3
>> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
>> CONFIG_USB1_VBUS_PIN="PH26"
>> CONFIG_USB2_VBUS_PIN="PH22"
>> CONFIG_VIDEO_COMPOSITE=y
>> diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
>> index 7841219a65..061f27c9db 100644
>> --- a/configs/Sinlinx_SinA33_defconfig
>> +++ b/configs/Sinlinx_SinA33_defconfig
>> @@ -6,6 +6,7 @@ CONFIG_DRAM_CLK=552
>> CONFIG_DRAM_ZQ=15291
>> CONFIG_MMC0_CD_PIN="PB4"
>> CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
>> CONFIG_USB0_ID_DET="PH8"
>> CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:3,vmode:0"
>> CONFIG_VIDEO_LCD_DCLK_PHASE=0
>> diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig
>> index c49cbcbc3c..cad5618d54 100644
>> --- a/configs/Yones_Toptech_BD1078_defconfig
>> +++ b/configs/Yones_Toptech_BD1078_defconfig
>> @@ -7,6 +7,7 @@ CONFIG_MMC0_CD_PIN="PH1"
>> CONFIG_MMC1_CD_PIN="PH2"
>> CONFIG_MMC1_PINS="PH"
>> CONFIG_MMC_SUNXI_SLOT_EXTRA=1
>> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
>
> Again, you're breaking all these boards while saying you want to fix
> them.
Let me know what is breaking here, I'm trying to update the env device
like before even if the order or detection follow as per DT.
^ permalink raw reply [flat|nested] 59+ messages in thread
* [U-Boot] [PATCH 22/25] env: sunxi: Update default env fat device
2018-07-16 10:16 ` Jagan Teki
@ 2018-07-17 11:54 ` Maxime Ripard
2018-07-19 18:21 ` Jagan Teki
0 siblings, 1 reply; 59+ messages in thread
From: Maxime Ripard @ 2018-07-17 11:54 UTC (permalink / raw)
To: u-boot
On Mon, Jul 16, 2018 at 03:46:10PM +0530, Jagan Teki wrote:
> On Mon, Jul 16, 2018 at 3:17 PM, Maxime Ripard
> <maxime.ripard@bootlin.com> wrote:
> > On Mon, Jul 16, 2018 at 01:49:53PM +0530, Jagan Teki wrote:
> >> Usually eMMC is default env fat device for environment,
> >> if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc
> >> device as 1. but with DM_MMC it can be more possible to
> >> probe eMMC as device 2 since for most of the sunxi platforms
> >> eMMC is configured mmc2.
> >>
> >> So update the env default device as 2 if DM_MMC and
> >> MMC_SUNXI_SLOT_EXTRA != 1 but some boards may not use all
> >> possible mmc devices or partly disabled in DT, for those update
> >> the device in board specific defconfig.
> >>
> >> Cc: Olliver Schinagl <oliver@schinagl.nl>
> >> Cc: Hans de Goede <hdegoede@redhat.com>
> >> Cc: Marcus Cooper <codekipper@gmail.com>
> >> Cc: Stefan Mavrodiev <stefan@olimex.com>
> >> Cc: Paul Kocialkowski <contact@paulk.fr>
> >> Cc: Chen-Yu Tsai <wens@csie.org>
> >> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> >> ---
> >> configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
> >> configs/A20-OLinuXino_MICRO-eMMC_defconfig | 1 +
> >> configs/A20-OLinuXino_MICRO_defconfig | 1 +
> >> configs/A20-Olimex-SOM-EVB_defconfig | 1 +
> >> configs/A20-Olimex-SOM204-EVB-eMMC_defconfig | 1 +
> >> configs/Mele_M3_defconfig | 1 +
> >> configs/Orangepi_mini_defconfig | 1 +
> >> configs/Sinlinx_SinA33_defconfig | 1 +
> >> configs/Yones_Toptech_BD1078_defconfig | 1 +
> >> configs/amarula_a64_relic_defconfig | 1 +
> >> env/Kconfig | 3 ++-
> >> 11 files changed, 12 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> >> index 20ea254191..98a8ceb178 100644
> >> --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> >> +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> >> @@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
> >> CONFIG_DRAM_CLK=384
> >> CONFIG_MMC0_CD_PIN="PH1"
> >> CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> >> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
> >> CONFIG_USB0_VBUS_PIN="PC17"
> >> CONFIG_USB0_VBUS_DET="PH5"
> >> CONFIG_I2C1_ENABLE=y
> >> diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
> >> index f7e7cbab0a..1552960d88 100644
> >> --- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig
> >> +++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
> >> @@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
> >> CONFIG_DRAM_CLK=384
> >> CONFIG_MMC0_CD_PIN="PH1"
> >> CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> >> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
> >> CONFIG_I2C1_ENABLE=y
> >> CONFIG_VIDEO_VGA=y
> >> CONFIG_SATAPWR="PB8"
> >> diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
> >> index 8dcbdc08f9..b5f1b7efe2 100644
> >> --- a/configs/A20-OLinuXino_MICRO_defconfig
> >> +++ b/configs/A20-OLinuXino_MICRO_defconfig
> >> @@ -6,6 +6,7 @@ CONFIG_DRAM_CLK=384
> >> CONFIG_MMC0_CD_PIN="PH1"
> >> CONFIG_MMC3_CD_PIN="PH11"
> >> CONFIG_MMC_SUNXI_SLOT_EXTRA=3
> >> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
> >> CONFIG_I2C1_ENABLE=y
> >> CONFIG_VIDEO_VGA=y
> >> CONFIG_SATAPWR="PB8"
> >> diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
> >> index a06499e2d0..58f6fbad91 100644
> >> --- a/configs/A20-Olimex-SOM-EVB_defconfig
> >> +++ b/configs/A20-Olimex-SOM-EVB_defconfig
> >> @@ -7,6 +7,7 @@ CONFIG_MMC0_CD_PIN="PH1"
> >> CONFIG_MMC3_CD_PIN="PH0"
> >> CONFIG_MMC3_PINS="PH"
> >> CONFIG_MMC_SUNXI_SLOT_EXTRA=3
> >> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
> >> CONFIG_USB0_VBUS_PIN="PB9"
> >> CONFIG_USB0_VBUS_DET="PH5"
> >> CONFIG_SATAPWR="PC3"
> >> diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
> >> index 3bb8c4c7e6..ac4f841c4e 100644
> >> --- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
> >> +++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
> >> @@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
> >> CONFIG_DRAM_CLK=384
> >> CONFIG_MMC0_CD_PIN="PH1"
> >> CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> >> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
> >> CONFIG_USB0_VBUS_PIN="PC17"
> >> CONFIG_USB0_VBUS_DET="PH5"
> >> CONFIG_I2C1_ENABLE=y
> >> diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig
> >> index 9f48bd91e0..93a2395aee 100644
> >> --- a/configs/Mele_M3_defconfig
> >> +++ b/configs/Mele_M3_defconfig
> >> @@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
> >> CONFIG_DRAM_CLK=384
> >> CONFIG_MMC0_CD_PIN="PH1"
> >> CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> >> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
> >> CONFIG_VIDEO_VGA=y
> >> CONFIG_VIDEO_COMPOSITE=y
> >> CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3"
> >> diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig
> >> index 46f27be254..d562273bef 100644
> >> --- a/configs/Orangepi_mini_defconfig
> >> +++ b/configs/Orangepi_mini_defconfig
> >> @@ -7,6 +7,7 @@ CONFIG_MACPWR="PH23"
> >> CONFIG_MMC0_CD_PIN="PH10"
> >> CONFIG_MMC3_CD_PIN="PH11"
> >> CONFIG_MMC_SUNXI_SLOT_EXTRA=3
> >> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
> >> CONFIG_USB1_VBUS_PIN="PH26"
> >> CONFIG_USB2_VBUS_PIN="PH22"
> >> CONFIG_VIDEO_COMPOSITE=y
> >> diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
> >> index 7841219a65..061f27c9db 100644
> >> --- a/configs/Sinlinx_SinA33_defconfig
> >> +++ b/configs/Sinlinx_SinA33_defconfig
> >> @@ -6,6 +6,7 @@ CONFIG_DRAM_CLK=552
> >> CONFIG_DRAM_ZQ=15291
> >> CONFIG_MMC0_CD_PIN="PB4"
> >> CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> >> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
> >> CONFIG_USB0_ID_DET="PH8"
> >> CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:3,vmode:0"
> >> CONFIG_VIDEO_LCD_DCLK_PHASE=0
> >> diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig
> >> index c49cbcbc3c..cad5618d54 100644
> >> --- a/configs/Yones_Toptech_BD1078_defconfig
> >> +++ b/configs/Yones_Toptech_BD1078_defconfig
> >> @@ -7,6 +7,7 @@ CONFIG_MMC0_CD_PIN="PH1"
> >> CONFIG_MMC1_CD_PIN="PH2"
> >> CONFIG_MMC1_PINS="PH"
> >> CONFIG_MMC_SUNXI_SLOT_EXTRA=1
> >> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
> >
> > Again, you're breaking all these boards while saying you want to fix
> > them.
>
> Let me know what is breaking here, I'm trying to update the env
> device like before even if the order or detection follow as per DT.
If the number is the one coming from the DT, then with DM_MMC, the ID
will change for them as well and they will have the FAT device become
2 if they have an eMMC. Which is why you're changing the default.
However, you're also changing the defconfig so that the number remain
the same, so you'll end up with the previous id being used, 1, which
is not the eMMC one.
A proper fix would be to simply changing the default.
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [U-Boot] [PATCH 22/25] env: sunxi: Update default env fat device
2018-07-17 11:54 ` Maxime Ripard
@ 2018-07-19 18:21 ` Jagan Teki
0 siblings, 0 replies; 59+ messages in thread
From: Jagan Teki @ 2018-07-19 18:21 UTC (permalink / raw)
To: u-boot
On Tue, Jul 17, 2018 at 5:24 PM, Maxime Ripard
<maxime.ripard@bootlin.com> wrote:
> On Mon, Jul 16, 2018 at 03:46:10PM +0530, Jagan Teki wrote:
>> On Mon, Jul 16, 2018 at 3:17 PM, Maxime Ripard
>> <maxime.ripard@bootlin.com> wrote:
>> > On Mon, Jul 16, 2018 at 01:49:53PM +0530, Jagan Teki wrote:
>> >> Usually eMMC is default env fat device for environment,
>> >> if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc
>> >> device as 1. but with DM_MMC it can be more possible to
>> >> probe eMMC as device 2 since for most of the sunxi platforms
>> >> eMMC is configured mmc2.
>> >>
>> >> So update the env default device as 2 if DM_MMC and
>> >> MMC_SUNXI_SLOT_EXTRA != 1 but some boards may not use all
>> >> possible mmc devices or partly disabled in DT, for those update
>> >> the device in board specific defconfig.
>> >>
>> >> Cc: Olliver Schinagl <oliver@schinagl.nl>
>> >> Cc: Hans de Goede <hdegoede@redhat.com>
>> >> Cc: Marcus Cooper <codekipper@gmail.com>
>> >> Cc: Stefan Mavrodiev <stefan@olimex.com>
>> >> Cc: Paul Kocialkowski <contact@paulk.fr>
>> >> Cc: Chen-Yu Tsai <wens@csie.org>
>> >> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>> >> ---
>> >> configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
>> >> configs/A20-OLinuXino_MICRO-eMMC_defconfig | 1 +
>> >> configs/A20-OLinuXino_MICRO_defconfig | 1 +
>> >> configs/A20-Olimex-SOM-EVB_defconfig | 1 +
>> >> configs/A20-Olimex-SOM204-EVB-eMMC_defconfig | 1 +
>> >> configs/Mele_M3_defconfig | 1 +
>> >> configs/Orangepi_mini_defconfig | 1 +
>> >> configs/Sinlinx_SinA33_defconfig | 1 +
>> >> configs/Yones_Toptech_BD1078_defconfig | 1 +
>> >> configs/amarula_a64_relic_defconfig | 1 +
>> >> env/Kconfig | 3 ++-
>> >> 11 files changed, 12 insertions(+), 1 deletion(-)
>> >>
>> >> diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
>> >> index 20ea254191..98a8ceb178 100644
>> >> --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
>> >> +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
>> >> @@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
>> >> CONFIG_DRAM_CLK=384
>> >> CONFIG_MMC0_CD_PIN="PH1"
>> >> CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>> >> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
>> >> CONFIG_USB0_VBUS_PIN="PC17"
>> >> CONFIG_USB0_VBUS_DET="PH5"
>> >> CONFIG_I2C1_ENABLE=y
>> >> diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
>> >> index f7e7cbab0a..1552960d88 100644
>> >> --- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig
>> >> +++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
>> >> @@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
>> >> CONFIG_DRAM_CLK=384
>> >> CONFIG_MMC0_CD_PIN="PH1"
>> >> CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>> >> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
>> >> CONFIG_I2C1_ENABLE=y
>> >> CONFIG_VIDEO_VGA=y
>> >> CONFIG_SATAPWR="PB8"
>> >> diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
>> >> index 8dcbdc08f9..b5f1b7efe2 100644
>> >> --- a/configs/A20-OLinuXino_MICRO_defconfig
>> >> +++ b/configs/A20-OLinuXino_MICRO_defconfig
>> >> @@ -6,6 +6,7 @@ CONFIG_DRAM_CLK=384
>> >> CONFIG_MMC0_CD_PIN="PH1"
>> >> CONFIG_MMC3_CD_PIN="PH11"
>> >> CONFIG_MMC_SUNXI_SLOT_EXTRA=3
>> >> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
>> >> CONFIG_I2C1_ENABLE=y
>> >> CONFIG_VIDEO_VGA=y
>> >> CONFIG_SATAPWR="PB8"
>> >> diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
>> >> index a06499e2d0..58f6fbad91 100644
>> >> --- a/configs/A20-Olimex-SOM-EVB_defconfig
>> >> +++ b/configs/A20-Olimex-SOM-EVB_defconfig
>> >> @@ -7,6 +7,7 @@ CONFIG_MMC0_CD_PIN="PH1"
>> >> CONFIG_MMC3_CD_PIN="PH0"
>> >> CONFIG_MMC3_PINS="PH"
>> >> CONFIG_MMC_SUNXI_SLOT_EXTRA=3
>> >> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
>> >> CONFIG_USB0_VBUS_PIN="PB9"
>> >> CONFIG_USB0_VBUS_DET="PH5"
>> >> CONFIG_SATAPWR="PC3"
>> >> diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
>> >> index 3bb8c4c7e6..ac4f841c4e 100644
>> >> --- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
>> >> +++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
>> >> @@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
>> >> CONFIG_DRAM_CLK=384
>> >> CONFIG_MMC0_CD_PIN="PH1"
>> >> CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>> >> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
>> >> CONFIG_USB0_VBUS_PIN="PC17"
>> >> CONFIG_USB0_VBUS_DET="PH5"
>> >> CONFIG_I2C1_ENABLE=y
>> >> diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig
>> >> index 9f48bd91e0..93a2395aee 100644
>> >> --- a/configs/Mele_M3_defconfig
>> >> +++ b/configs/Mele_M3_defconfig
>> >> @@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
>> >> CONFIG_DRAM_CLK=384
>> >> CONFIG_MMC0_CD_PIN="PH1"
>> >> CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>> >> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
>> >> CONFIG_VIDEO_VGA=y
>> >> CONFIG_VIDEO_COMPOSITE=y
>> >> CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3"
>> >> diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig
>> >> index 46f27be254..d562273bef 100644
>> >> --- a/configs/Orangepi_mini_defconfig
>> >> +++ b/configs/Orangepi_mini_defconfig
>> >> @@ -7,6 +7,7 @@ CONFIG_MACPWR="PH23"
>> >> CONFIG_MMC0_CD_PIN="PH10"
>> >> CONFIG_MMC3_CD_PIN="PH11"
>> >> CONFIG_MMC_SUNXI_SLOT_EXTRA=3
>> >> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
>> >> CONFIG_USB1_VBUS_PIN="PH26"
>> >> CONFIG_USB2_VBUS_PIN="PH22"
>> >> CONFIG_VIDEO_COMPOSITE=y
>> >> diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
>> >> index 7841219a65..061f27c9db 100644
>> >> --- a/configs/Sinlinx_SinA33_defconfig
>> >> +++ b/configs/Sinlinx_SinA33_defconfig
>> >> @@ -6,6 +6,7 @@ CONFIG_DRAM_CLK=552
>> >> CONFIG_DRAM_ZQ=15291
>> >> CONFIG_MMC0_CD_PIN="PB4"
>> >> CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>> >> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
>> >> CONFIG_USB0_ID_DET="PH8"
>> >> CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:3,vmode:0"
>> >> CONFIG_VIDEO_LCD_DCLK_PHASE=0
>> >> diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig
>> >> index c49cbcbc3c..cad5618d54 100644
>> >> --- a/configs/Yones_Toptech_BD1078_defconfig
>> >> +++ b/configs/Yones_Toptech_BD1078_defconfig
>> >> @@ -7,6 +7,7 @@ CONFIG_MMC0_CD_PIN="PH1"
>> >> CONFIG_MMC1_CD_PIN="PH2"
>> >> CONFIG_MMC1_PINS="PH"
>> >> CONFIG_MMC_SUNXI_SLOT_EXTRA=1
>> >> +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
>> >
>> > Again, you're breaking all these boards while saying you want to fix
>> > them.
>>
>> Let me know what is breaking here, I'm trying to update the env
>> device like before even if the order or detection follow as per DT.
>
> If the number is the one coming from the DT, then with DM_MMC, the ID
> will change for them as well and they will have the FAT device become
> 2 if they have an eMMC. Which is why you're changing the default.
>
> However, you're also changing the defconfig so that the number remain
> the same, so you'll end up with the previous id being used, 1, which
> is not the eMMC one.
ie what I'm trying here. Say for example A20-OLinuXino-LIME2-eMMC
board based on the kconfig with 2 SLOTS and DM_MMC defined the default
fat device is 2 but since the sun7i-a20-olinuxino-lime2-emmc.dts has
only mmc0 and mmc2 (which is eMMC) due to missing mmc1 the eMMC will
probed on device 1 ie what I'm trying to update in defconfig.
> A proper fix would be to simply changing the default.
No idea how can we support this, how about give device input to saveenv command.
^ permalink raw reply [flat|nested] 59+ messages in thread
* [U-Boot] [PATCH 23/25] sunxi: Use mmc_bootdev=2 for MMC2 boot
2018-07-16 8:19 [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Jagan Teki
` (21 preceding siblings ...)
2018-07-16 8:19 ` [U-Boot] [PATCH 22/25] env: sunxi: Update default env fat device Jagan Teki
@ 2018-07-16 8:19 ` Jagan Teki
2018-07-16 9:48 ` Maxime Ripard
2018-07-16 8:19 ` [U-Boot] [DO NOT MERGE PATCH 24/25] sunxi: A13/A31: Enable DM_MMC Jagan Teki
` (2 subsequent siblings)
25 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 8:19 UTC (permalink / raw)
To: u-boot
With DM_MMC the mmc devices are probed as per dt status
and eMMC can probed maximum device of 2, if all nodes like
mmc0, mmc1 and mmc2 status are 'okay'.
So update mmc_bootdev to 2 and add boot order as 2, 1, 0
devices. so-that it can to boot any identified device even
if the respective device status disabled or unsupported.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
board/sunxi/board.c | 2 +-
include/configs/sunxi-common.h | 4 +++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 5ed1b8bae1..7edc468185 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -768,7 +768,7 @@ int misc_init_r(void)
} else if (boot == BOOT_DEVICE_MMC1) {
env_set("mmc_bootdev", "0");
} else if (boot == BOOT_DEVICE_MMC2) {
- env_set("mmc_bootdev", "1");
+ env_set("mmc_bootdev", "2");
}
setup_environment(gd->fdt_blob);
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 21371f4919..abf10f6dcf 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -373,8 +373,10 @@ extern int soft_i2c_gpio_scl;
#define BOOTENV_DEV_MMC_AUTO(devtypeu, devtypel, instance) \
BOOTENV_DEV_MMC(MMC, mmc, 0) \
BOOTENV_DEV_MMC(MMC, mmc, 1) \
+ BOOTENV_DEV_MMC(MMC, mmc, 2) \
"bootcmd_mmc_auto=" \
- "if test ${mmc_bootdev} -eq 1; then " \
+ "if test ${mmc_bootdev} -eq 2; then " \
+ "run bootcmd_mmc2; " \
"run bootcmd_mmc1; " \
"run bootcmd_mmc0; " \
"elif test ${mmc_bootdev} -eq 0; then " \
--
2.17.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 23/25] sunxi: Use mmc_bootdev=2 for MMC2 boot
2018-07-16 8:19 ` [U-Boot] [PATCH 23/25] sunxi: Use mmc_bootdev=2 for MMC2 boot Jagan Teki
@ 2018-07-16 9:48 ` Maxime Ripard
2018-07-16 10:21 ` Jagan Teki
0 siblings, 1 reply; 59+ messages in thread
From: Maxime Ripard @ 2018-07-16 9:48 UTC (permalink / raw)
To: u-boot
On Mon, Jul 16, 2018 at 01:49:54PM +0530, Jagan Teki wrote:
> With DM_MMC the mmc devices are probed as per dt status
> and eMMC can probed maximum device of 2, if all nodes like
> mmc0, mmc1 and mmc2 status are 'okay'.
>
> So update mmc_bootdev to 2 and add boot order as 2, 1, 0
> devices. so-that it can to boot any identified device even
> if the respective device status disabled or unsupported.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
> board/sunxi/board.c | 2 +-
> include/configs/sunxi-common.h | 4 +++-
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> index 5ed1b8bae1..7edc468185 100644
> --- a/board/sunxi/board.c
> +++ b/board/sunxi/board.c
> @@ -768,7 +768,7 @@ int misc_init_r(void)
> } else if (boot == BOOT_DEVICE_MMC1) {
> env_set("mmc_bootdev", "0");
> } else if (boot == BOOT_DEVICE_MMC2) {
> - env_set("mmc_bootdev", "1");
> + env_set("mmc_bootdev", "2");
Isn't that broken too? I guess we should return MMC3 in that case.
Also, what about bisectability?
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 23/25] sunxi: Use mmc_bootdev=2 for MMC2 boot
2018-07-16 9:48 ` Maxime Ripard
@ 2018-07-16 10:21 ` Jagan Teki
2018-07-17 11:55 ` Maxime Ripard
0 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 10:21 UTC (permalink / raw)
To: u-boot
On Mon, Jul 16, 2018 at 3:18 PM, Maxime Ripard
<maxime.ripard@bootlin.com> wrote:
> On Mon, Jul 16, 2018 at 01:49:54PM +0530, Jagan Teki wrote:
>> With DM_MMC the mmc devices are probed as per dt status
>> and eMMC can probed maximum device of 2, if all nodes like
>> mmc0, mmc1 and mmc2 status are 'okay'.
>>
>> So update mmc_bootdev to 2 and add boot order as 2, 1, 0
>> devices. so-that it can to boot any identified device even
>> if the respective device status disabled or unsupported.
>>
>> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>> ---
>> board/sunxi/board.c | 2 +-
>> include/configs/sunxi-common.h | 4 +++-
>> 2 files changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/board/sunxi/board.c b/board/sunxi/board.c
>> index 5ed1b8bae1..7edc468185 100644
>> --- a/board/sunxi/board.c
>> +++ b/board/sunxi/board.c
>> @@ -768,7 +768,7 @@ int misc_init_r(void)
>> } else if (boot == BOOT_DEVICE_MMC1) {
>> env_set("mmc_bootdev", "0");
>> } else if (boot == BOOT_DEVICE_MMC2) {
>> - env_set("mmc_bootdev", "1");
>> + env_set("mmc_bootdev", "2");
>
> Isn't that broken too? I guess we should return MMC3 in that case.
Yes, A10 has maximum of mmc3 will fix.
>
> Also, what about bisectability?
are you referring order check while booting, ie reason I've update the
ordering with device 2, 1, 0
^ permalink raw reply [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 23/25] sunxi: Use mmc_bootdev=2 for MMC2 boot
2018-07-16 10:21 ` Jagan Teki
@ 2018-07-17 11:55 ` Maxime Ripard
0 siblings, 0 replies; 59+ messages in thread
From: Maxime Ripard @ 2018-07-17 11:55 UTC (permalink / raw)
To: u-boot
On Mon, Jul 16, 2018 at 03:51:33PM +0530, Jagan Teki wrote:
> On Mon, Jul 16, 2018 at 3:18 PM, Maxime Ripard
> <maxime.ripard@bootlin.com> wrote:
> > On Mon, Jul 16, 2018 at 01:49:54PM +0530, Jagan Teki wrote:
> >> With DM_MMC the mmc devices are probed as per dt status
> >> and eMMC can probed maximum device of 2, if all nodes like
> >> mmc0, mmc1 and mmc2 status are 'okay'.
> >>
> >> So update mmc_bootdev to 2 and add boot order as 2, 1, 0
> >> devices. so-that it can to boot any identified device even
> >> if the respective device status disabled or unsupported.
> >>
> >> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> >> ---
> >> board/sunxi/board.c | 2 +-
> >> include/configs/sunxi-common.h | 4 +++-
> >> 2 files changed, 4 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> >> index 5ed1b8bae1..7edc468185 100644
> >> --- a/board/sunxi/board.c
> >> +++ b/board/sunxi/board.c
> >> @@ -768,7 +768,7 @@ int misc_init_r(void)
> >> } else if (boot == BOOT_DEVICE_MMC1) {
> >> env_set("mmc_bootdev", "0");
> >> } else if (boot == BOOT_DEVICE_MMC2) {
> >> - env_set("mmc_bootdev", "1");
> >> + env_set("mmc_bootdev", "2");
> >
> > Isn't that broken too? I guess we should return MMC3 in that case.
>
> Yes, A10 has maximum of mmc3 will fix.
>
> >
> > Also, what about bisectability?
>
> are you referring order check while booting, ie reason I've update the
> ordering with device 2, 1, 0
No, I'm referring to the fact that each and every commit of your serie
should be bootable and fully working without any regression. Selecting
DM_MMC and then fixing the IDs in that case breaks that assumption.
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [U-Boot] [DO NOT MERGE PATCH 24/25] sunxi: A13/A31: Enable DM_MMC
2018-07-16 8:19 [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Jagan Teki
` (22 preceding siblings ...)
2018-07-16 8:19 ` [U-Boot] [PATCH 23/25] sunxi: Use mmc_bootdev=2 for MMC2 boot Jagan Teki
@ 2018-07-16 8:19 ` Jagan Teki
2018-07-16 8:19 ` [U-Boot] [DO NOT MERGE PATCH 25/25] sunxi: A23/A33/V3S: " Jagan Teki
2018-07-16 8:35 ` [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Chen-Yu Tsai
25 siblings, 0 replies; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 8:19 UTC (permalink / raw)
To: u-boot
Enable DM_MMC for Allwinner A13/A31 SoC.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/mach-sunxi/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index f3d7c8b67d..0d277f9e2b 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -155,6 +155,7 @@ config MACH_SUN5I
select CPU_V7A
select ARM_CORTEX_CPU_IS_UP
select DRAM_SUN4I
+ select DM_MMC if MMC
select PHY_SUN4I_USB
select SUNXI_GEN_SUN4I
select SUPPORT_SPL
@@ -167,6 +168,7 @@ config MACH_SUN6I
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
select DRAM_SUN6I
+ select DM_MMC if MMC
select PHY_SUN4I_USB
select SUN6I_P2WI
select SUN6I_PRCM
--
2.17.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [U-Boot] [DO NOT MERGE PATCH 25/25] sunxi: A23/A33/V3S: Enable DM_MMC
2018-07-16 8:19 [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Jagan Teki
` (23 preceding siblings ...)
2018-07-16 8:19 ` [U-Boot] [DO NOT MERGE PATCH 24/25] sunxi: A13/A31: Enable DM_MMC Jagan Teki
@ 2018-07-16 8:19 ` Jagan Teki
2018-07-16 8:35 ` [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Chen-Yu Tsai
25 siblings, 0 replies; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 8:19 UTC (permalink / raw)
To: u-boot
Enable DM_MMC for Allwinner A23/A33/V3S SoC.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/mach-sunxi/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 0d277f9e2b..be1ff10212 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -196,6 +196,7 @@ config MACH_SUN8I_A23
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
select DRAM_SUN8I_A23
+ select DM_MMC if MMC
select PHY_SUN4I_USB
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
@@ -209,6 +210,7 @@ config MACH_SUN8I_A33
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
select DRAM_SUN8I_A33
+ select DM_MMC if MMC
select PHY_SUN4I_USB
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
@@ -252,6 +254,7 @@ config MACH_SUN8I_V3S
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
+ select DM_MMC if MMC
select SUNXI_GEN_SUN6I
select SUNXI_DRAM_DW
select SUNXI_DRAM_DW_16BIT
--
2.17.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper
2018-07-16 8:19 [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Jagan Teki
` (24 preceding siblings ...)
2018-07-16 8:19 ` [U-Boot] [DO NOT MERGE PATCH 25/25] sunxi: A23/A33/V3S: " Jagan Teki
@ 2018-07-16 8:35 ` Chen-Yu Tsai
2018-07-16 9:52 ` Maxime Ripard
25 siblings, 1 reply; 59+ messages in thread
From: Chen-Yu Tsai @ 2018-07-16 8:35 UTC (permalink / raw)
To: u-boot
On Mon, Jul 16, 2018 at 4:19 PM, Jagan Teki <jagan@amarulasolutions.com> wrote:
> Enabling DM_MMC is not straight forward for Allwinner SoC's to
> make proper compatibility in mmc driver vs DT nodes.
>
> Existing dm code for ahb gate clock will be suitable to handle
> sun4i,5i,6i and 7i U-Boot specific mmc dt nodes, which are different
> from Linux in terms of clocks phandle notation.
>
> U-Boot DT clocks phandle follow direct ahb and clock address on
> node definition with specific bit position, but Linux clocks phandle
> follow macros to define AHB and MMC clocks so-that the ccu driver
> will set the bits accordingly.
And that has been deprecated upstream.
> Clocks phandle notations in U-Boot for higher Allwinner SoC start
> from sun8i, sun50i are following Linux notation so-that both Linux
> and U-Boot can have common node definition.
So basically you're saying the additional code for clock/reset
handling through the device tree only works for half of the SoCs,
based on a deprecated device tree binding. Which means we're
going to throw it out some time in the future. Is it worth the
churn of driver and device tree changes?
IMHO the new clock handling code is no better than the old. The only
thing that has changed is how the clock register address is derived.
Not even the index numbers, which BTW are actual bit offsets, for
the AHB gates from the device tree are used. Neither is the device
tree used for the AHB resets.
If we remove that portion from the series, and also sync up all
device tree files to Linux 4.17 (or a later -rc or -next), instead
of manually adding device nodes based on the old device tree binding,
it probably would still work.
Regards
ChenYu
> This series will address the ahb gate, clock setup to handle all
> type of Allwinner SoCs. and sync mmc node definitions from Linux
> for sun4i and sun5i.
>
> Note:
> - sun6i, A23, A33, V3S were untested these need to have a closer look
> on dt nodes along with default ENV_FAT device.
>
> All these changes available at u-boot-sunxi/next
>
> Let me know if any questions or missings,
> Jagan.
>
> Jagan Teki (25):
> ARM: dts: sun4i: Sync A10 MMC nodes from Linux
> ARM: dts: sun4i: Sync A10 board dts mmc0 node from Linux
> ARM: dts: sun4i: Add mmc0 node for iNet 3F
> ARM: dts: sun4i: Add mmc0 node for iNet 3W
> dm: mmc: sunxi: Refactor ahb gate and clock setup
> dm: mmc: sunxi: Add ahb reset0 register write
> ARM: dts: sun7i: Sync A20 MMC nodes from Linux
> ARM: dts: sun7i: Add mmc0 node for Primo73 tablet
> ARM: dts: sun7i: Add mmc0 node for Ainol AW1
> ARM: dts: sun7i: Add mmc0 node for Mele M5
> ARM: dts: sun7i: Add mmc0 node for Toptech BD1078
> sunxi: A20: Enable DM_MMC
> mmc: sunxi: Add mmc, emmc H5/A64 compatible
> sunxi: H3_H5: Enable DM_MMC
> sunxi: A64: Enable DM_MMC
> ARM: dts: sun8i: Update A83T dts(i) files from Linux
> mmc: sunxi: Add A83T emmc compatible
> sunxi: A83T: Enable DM_MMC
> ARM: dts: sun8i: Update R40 dts(i) files from Linux
> sunxi: V40: Enable DM_MMC
> fastboot: sunxi: Update fastboot mmc default device
> env: sunxi: Update default env fat device
> sunxi: Use mmc_bootdev=2 for MMC2 boot
> [DO NOT MERGE] sunxi: A13/A31: Enable DM_MMC
> [DO NOT MERGE] sunxi: A23/A33/V3S: Enable DM_MMC
>
> arch/arm/dts/axp81x.dtsi | 169 ++++
> arch/arm/dts/sun4i-a10-a1000.dts | 5 +-
> arch/arm/dts/sun4i-a10-ba10-tvbox.dts | 5 +-
> arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts | 5 +-
> arch/arm/dts/sun4i-a10-cubieboard.dts | 5 +-
> arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts | 5 +-
> arch/arm/dts/sun4i-a10-gemei-g9.dts | 5 +-
> arch/arm/dts/sun4i-a10-hackberry.dts | 5 +-
> arch/arm/dts/sun4i-a10-hyundai-a7hd.dts | 5 +-
> arch/arm/dts/sun4i-a10-inet-3f.dts | 9 +
> arch/arm/dts/sun4i-a10-inet-3w.dts | 9 +
> arch/arm/dts/sun4i-a10-inet1.dts | 5 +-
> arch/arm/dts/sun4i-a10-inet97fv2.dts | 5 +-
> arch/arm/dts/sun4i-a10-inet9f-rev03.dts | 5 +-
> .../dts/sun4i-a10-itead-iteaduino-plus.dts | 5 +-
> arch/arm/dts/sun4i-a10-jesurun-q5.dts | 5 +-
> arch/arm/dts/sun4i-a10-marsboard.dts | 5 +-
> arch/arm/dts/sun4i-a10-mini-xplus.dts | 5 +-
> arch/arm/dts/sun4i-a10-mk802.dts | 5 +-
> arch/arm/dts/sun4i-a10-mk802ii.dts | 5 +-
> arch/arm/dts/sun4i-a10-olinuxino-lime.dts | 5 +-
> arch/arm/dts/sun4i-a10-pcduino.dts | 5 +-
> arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts | 5 +-
> arch/arm/dts/sun4i-a10.dtsi | 112 +--
> arch/arm/dts/sun7i-a20-ainol-aw1.dts | 13 +
> arch/arm/dts/sun7i-a20-m5.dts | 12 +
> arch/arm/dts/sun7i-a20-primo73.dts | 20 +-
> .../dts/sun7i-a20-yones-toptech-bd1078.dts | 13 +
> arch/arm/dts/sun7i-a20.dtsi | 102 +-
> .../dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 195 +++-
> arch/arm/dts/sun8i-a83t-bananapi-m3.dts | 298 +++++-
> arch/arm/dts/sun8i-a83t-cubietruck-plus.dts | 322 ++++++-
> arch/arm/dts/sun8i-a83t-tbs-a711.dts | 355 ++++++-
> arch/arm/dts/sun8i-a83t.dtsi | 885 ++++++++++++++++--
> arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts | 197 +++-
> arch/arm/dts/sun8i-r40.dtsi | 616 +++++++++++-
> arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts | 50 +
> arch/arm/mach-sunxi/Kconfig | 10 +
> board/sunxi/board.c | 2 +-
> configs/A20-OLinuXino-Lime2-eMMC_defconfig | 2 +
> configs/A20-OLinuXino_MICRO-eMMC_defconfig | 1 +
> configs/A20-OLinuXino_MICRO_defconfig | 1 +
> configs/A20-Olimex-SOM-EVB_defconfig | 1 +
> configs/A20-Olimex-SOM204-EVB-eMMC_defconfig | 1 +
> configs/Mele_M3_defconfig | 1 +
> configs/Orangepi_mini_defconfig | 1 +
> configs/Sinlinx_SinA33_defconfig | 2 +
> configs/Yones_Toptech_BD1078_defconfig | 1 +
> configs/amarula_a64_relic_defconfig | 2 +
> drivers/fastboot/Kconfig | 3 +-
> drivers/mmc/sunxi_mmc.c | 81 +-
> env/Kconfig | 3 +-
> include/configs/sunxi-common.h | 4 +-
> include/dt-bindings/clock/sun4i-a10-ccu.h | 202 ++++
> include/dt-bindings/clock/sun7i-a20-ccu.h | 53 ++
> include/dt-bindings/clock/sun8i-a83t-ccu.h | 140 +++
> include/dt-bindings/reset/sun8i-a83t-ccu.h | 98 ++
> 57 files changed, 3715 insertions(+), 371 deletions(-)
> create mode 100644 arch/arm/dts/axp81x.dtsi
> create mode 100644 include/dt-bindings/clock/sun4i-a10-ccu.h
> create mode 100644 include/dt-bindings/clock/sun7i-a20-ccu.h
> create mode 100644 include/dt-bindings/clock/sun8i-a83t-ccu.h
> create mode 100644 include/dt-bindings/reset/sun8i-a83t-ccu.h
>
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 59+ messages in thread* [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper
2018-07-16 8:35 ` [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper Chen-Yu Tsai
@ 2018-07-16 9:52 ` Maxime Ripard
2018-07-16 11:08 ` Andre Przywara
0 siblings, 1 reply; 59+ messages in thread
From: Maxime Ripard @ 2018-07-16 9:52 UTC (permalink / raw)
To: u-boot
On Mon, Jul 16, 2018 at 04:35:09PM +0800, Chen-Yu Tsai wrote:
> On Mon, Jul 16, 2018 at 4:19 PM, Jagan Teki <jagan@amarulasolutions.com> wrote:
> > Enabling DM_MMC is not straight forward for Allwinner SoC's to
> > make proper compatibility in mmc driver vs DT nodes.
> >
> > Existing dm code for ahb gate clock will be suitable to handle
> > sun4i,5i,6i and 7i U-Boot specific mmc dt nodes, which are different
> > from Linux in terms of clocks phandle notation.
> >
> > U-Boot DT clocks phandle follow direct ahb and clock address on
> > node definition with specific bit position, but Linux clocks phandle
> > follow macros to define AHB and MMC clocks so-that the ccu driver
> > will set the bits accordingly.
>
> And that has been deprecated upstream.
>
> > Clocks phandle notations in U-Boot for higher Allwinner SoC start
> > from sun8i, sun50i are following Linux notation so-that both Linux
> > and U-Boot can have common node definition.
>
> So basically you're saying the additional code for clock/reset
> handling through the device tree only works for half of the SoCs,
> based on a deprecated device tree binding. Which means we're
> going to throw it out some time in the future. Is it worth the
> churn of driver and device tree changes?
>
> IMHO the new clock handling code is no better than the old. The only
> thing that has changed is how the clock register address is derived.
> Not even the index numbers, which BTW are actual bit offsets, for
> the AHB gates from the device tree are used. Neither is the device
> tree used for the AHB resets.
I'd say that it's even worse. We want an actual, common, clock
driver. Not a quick hack that doesn't solve any of the issues we're
facing.
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper
2018-07-16 9:52 ` Maxime Ripard
@ 2018-07-16 11:08 ` Andre Przywara
2018-07-16 11:42 ` Jagan Teki
0 siblings, 1 reply; 59+ messages in thread
From: Andre Przywara @ 2018-07-16 11:08 UTC (permalink / raw)
To: u-boot
Hi,
On 16/07/18 10:52, Maxime Ripard wrote:
> On Mon, Jul 16, 2018 at 04:35:09PM +0800, Chen-Yu Tsai wrote:
>> On Mon, Jul 16, 2018 at 4:19 PM, Jagan Teki <jagan@amarulasolutions.com> wrote:
>>> Enabling DM_MMC is not straight forward for Allwinner SoC's to
>>> make proper compatibility in mmc driver vs DT nodes.
>>>
>>> Existing dm code for ahb gate clock will be suitable to handle
>>> sun4i,5i,6i and 7i U-Boot specific mmc dt nodes, which are different
>>> from Linux in terms of clocks phandle notation.
>>>
>>> U-Boot DT clocks phandle follow direct ahb and clock address on
>>> node definition with specific bit position, but Linux clocks phandle
>>> follow macros to define AHB and MMC clocks so-that the ccu driver
>>> will set the bits accordingly.
>>
>> And that has been deprecated upstream.
>>
>>> Clocks phandle notations in U-Boot for higher Allwinner SoC start
>>> from sun8i, sun50i are following Linux notation so-that both Linux
>>> and U-Boot can have common node definition.
>>
>> So basically you're saying the additional code for clock/reset
>> handling through the device tree only works for half of the SoCs,
>> based on a deprecated device tree binding. Which means we're
>> going to throw it out some time in the future. Is it worth the
>> churn of driver and device tree changes?
>>
>> IMHO the new clock handling code is no better than the old. The only
>> thing that has changed is how the clock register address is derived.
>> Not even the index numbers, which BTW are actual bit offsets, for
>> the AHB gates from the device tree are used. Neither is the device
>> tree used for the AHB resets.
>
> I'd say that it's even worse. We want an actual, common, clock
> driver. Not a quick hack that doesn't solve any of the issues we're
> facing.
So is the purpose of this whole series to just comply with the
deprecation of non-DM_MMC configurations?
As mentioned before I am wondering how useful this is, and if we could
ever get rid of those hardcoded hacks for the SPL anyway (so the driver
would technically be DM_MMC compliant, but still had non-DM_MMC code in).
So I would suggest we push the clock DM driver forward first [1],
implementing the new CCU binding, then possibly convert over the pre-H3
boards.
And meanwhile we try to appease the maintainers to not remove any boards
which don't support DM_MMC, because the purpose of U-Boot should be to
get boards booting and not to have some fancy driver model just for the
sake of it.
Cheers,
Andre.
[1] https://github.com/apritzel/u-boot/commits/sunxi-dm-WIP
^ permalink raw reply [flat|nested] 59+ messages in thread
* [U-Boot] [PATCH 00/25] sunxi: Enable DM_MMC for U-Boot proper
2018-07-16 11:08 ` Andre Przywara
@ 2018-07-16 11:42 ` Jagan Teki
0 siblings, 0 replies; 59+ messages in thread
From: Jagan Teki @ 2018-07-16 11:42 UTC (permalink / raw)
To: u-boot
On Mon, Jul 16, 2018 at 4:38 PM, Andre Przywara <andre.przywara@arm.com> wrote:
> Hi,
>
> On 16/07/18 10:52, Maxime Ripard wrote:
>> On Mon, Jul 16, 2018 at 04:35:09PM +0800, Chen-Yu Tsai wrote:
>>> On Mon, Jul 16, 2018 at 4:19 PM, Jagan Teki <jagan@amarulasolutions.com> wrote:
>>>> Enabling DM_MMC is not straight forward for Allwinner SoC's to
>>>> make proper compatibility in mmc driver vs DT nodes.
>>>>
>>>> Existing dm code for ahb gate clock will be suitable to handle
>>>> sun4i,5i,6i and 7i U-Boot specific mmc dt nodes, which are different
>>>> from Linux in terms of clocks phandle notation.
>>>>
>>>> U-Boot DT clocks phandle follow direct ahb and clock address on
>>>> node definition with specific bit position, but Linux clocks phandle
>>>> follow macros to define AHB and MMC clocks so-that the ccu driver
>>>> will set the bits accordingly.
>>>
>>> And that has been deprecated upstream.
>>>
>>>> Clocks phandle notations in U-Boot for higher Allwinner SoC start
>>>> from sun8i, sun50i are following Linux notation so-that both Linux
>>>> and U-Boot can have common node definition.
>>>
>>> So basically you're saying the additional code for clock/reset
>>> handling through the device tree only works for half of the SoCs,
>>> based on a deprecated device tree binding. Which means we're
>>> going to throw it out some time in the future. Is it worth the
>>> churn of driver and device tree changes?
>>>
>>> IMHO the new clock handling code is no better than the old. The only
>>> thing that has changed is how the clock register address is derived.
>>> Not even the index numbers, which BTW are actual bit offsets, for
>>> the AHB gates from the device tree are used. Neither is the device
>>> tree used for the AHB resets.
>>
>> I'd say that it's even worse. We want an actual, common, clock
>> driver. Not a quick hack that doesn't solve any of the issues we're
>> facing.
>
> So is the purpose of this whole series to just comply with the
> deprecation of non-DM_MMC configurations?
> As mentioned before I am wondering how useful this is, and if we could
> ever get rid of those hardcoded hacks for the SPL anyway (so the driver
> would technically be DM_MMC compliant, but still had non-DM_MMC code in).
The migration idea about DM_MMC would be for U-Boot proper[2] (not for
SPL as of now). Even if we put the migration aside, we have a problem
with SPL size for DM_MMC for arm64 SoCs. indeed we need to wait for
this to fix for having full DM_MMC code.
[2] https://patchwork.ozlabs.org/patch/933761/
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