From: Christoph Hellwig <hch@lst.de> To: Atish Patra <atish.patra@wdc.com> Cc: Christoph Hellwig <hch@lst.de>, "tglx@linutronix.de" <tglx@linutronix.de>, "palmer@sifive.com" <palmer@sifive.com>, "jason@lakedaemon.net" <jason@lakedaemon.net>, "marc.zyngier@arm.com" <marc.zyngier@arm.com>, "robh+dt@kernel.org" <robh+dt@kernel.org>, "mark.rutland@arm.com" <mark.rutland@arm.com>, "anup@brainfault.org" <anup@brainfault.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>, "shorne@gmail.com" <shorne@gmail.com> Subject: Re: [PATCH 10/11] irqchip: add a SiFive PLIC driver Date: Fri, 3 Aug 2018 14:29:58 +0200 [thread overview] Message-ID: <20180803122958.GA18301@lst.de> (raw) In-Reply-To: <2416469e-c39e-6481-f5e0-ad191b858d06@wdc.com> On Thu, Aug 02, 2018 at 04:13:26PM -0700, Atish Patra wrote: >> + * which device 0 is defined as non-existant by the RISC-V Priviledged Spec. > /s/existant/existent > > /s/Priviledged/Privileged >> + * Each hart context has a vector of interupt enable bits associated with it. > /s/interupt/interrupt All fixed. >> + WARN_ON_ONCE(!handler->present); >> + >> + csr_clear(sie, SIE_STIE); > > We should clear the SIE_SEIE not SIE_STIE. Correct ? Yes, fixed. >> + if (plic_regs) { >> + pr_warning("PLIC already present.\n"); > > Got a check-patch warning. > > WARNING: Prefer pr_warn(... to pr_warning(... > #257: FILE: drivers/irqchip/irq-sifive-plic.c:191: > + pr_warning("PLIC already present.\n"); Fixed. >> + >> + if (of_irq_parse_one(node, i, &parent)) { >> + pr_err("failed to parse parent for contxt %d.\n", i); > /s/contxt/context Fixed. >> + continue; >> + } >> + >> + /* skip context holes */ >> + if (parent.args[0] == -1) >> + continue; >> + >> + cpu = plic_find_hart_id(parent.np->parent); > > Since plic_find_hart_id() is going to walk up the DT, we can pass only > parent.np instead of parent.np->parent. It does not increase any efficiency > either way. So not very necessary. Just thought of taking the advantage of > plic_find_hart_id. Yeah, I'll update this. Thanks for the review!
WARNING: multiple messages have this Message-ID (diff)
From: hch@lst.de (Christoph Hellwig) To: linux-riscv@lists.infradead.org Subject: [PATCH 10/11] irqchip: add a SiFive PLIC driver Date: Fri, 3 Aug 2018 14:29:58 +0200 [thread overview] Message-ID: <20180803122958.GA18301@lst.de> (raw) In-Reply-To: <2416469e-c39e-6481-f5e0-ad191b858d06@wdc.com> On Thu, Aug 02, 2018 at 04:13:26PM -0700, Atish Patra wrote: >> + * which device 0 is defined as non-existant by the RISC-V Priviledged Spec. > /s/existant/existent > > /s/Priviledged/Privileged >> + * Each hart context has a vector of interupt enable bits associated with it. > /s/interupt/interrupt All fixed. >> + WARN_ON_ONCE(!handler->present); >> + >> + csr_clear(sie, SIE_STIE); > > We should clear the SIE_SEIE not SIE_STIE. Correct ? Yes, fixed. >> + if (plic_regs) { >> + pr_warning("PLIC already present.\n"); > > Got a check-patch warning. > > WARNING: Prefer pr_warn(... to pr_warning(... > #257: FILE: drivers/irqchip/irq-sifive-plic.c:191: > + pr_warning("PLIC already present.\n"); Fixed. >> + >> + if (of_irq_parse_one(node, i, &parent)) { >> + pr_err("failed to parse parent for contxt %d.\n", i); > /s/contxt/context Fixed. >> + continue; >> + } >> + >> + /* skip context holes */ >> + if (parent.args[0] == -1) >> + continue; >> + >> + cpu = plic_find_hart_id(parent.np->parent); > > Since plic_find_hart_id() is going to walk up the DT, we can pass only > parent.np instead of parent.np->parent. It does not increase any efficiency > either way. So not very necessary. Just thought of taking the advantage of > plic_find_hart_id. Yeah, I'll update this. Thanks for the review!
next prev parent reply other threads:[~2018-08-03 12:25 UTC|newest] Thread overview: 99+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-08-02 11:49 simplified RISC-V interrupt and clocksource handling v2 Christoph Hellwig 2018-08-02 11:49 ` Christoph Hellwig 2018-08-02 11:49 ` Christoph Hellwig 2018-08-02 11:49 ` [PATCH 01/11] dt-bindings: Correct RISC-V's timebase-frequency Christoph Hellwig 2018-08-02 11:49 ` Christoph Hellwig 2018-08-02 11:49 ` Christoph Hellwig 2018-08-08 14:44 ` Rob Herring 2018-08-08 14:44 ` Rob Herring 2018-08-02 11:49 ` [PATCH 02/11] dt-bindings: Add an enable method to RISC-V Christoph Hellwig 2018-08-02 11:49 ` Christoph Hellwig 2018-08-02 11:49 ` Christoph Hellwig 2018-08-08 14:43 ` Rob Herring 2018-08-08 14:43 ` Rob Herring 2018-08-02 11:50 ` [PATCH 03/11] dt-bindings: interrupt-controller: RISC-V PLIC documentation Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 22:08 ` Atish Patra 2018-08-02 22:08 ` Atish Patra 2018-08-03 13:30 ` Christoph Hellwig 2018-08-03 13:30 ` Christoph Hellwig 2018-08-06 20:59 ` Rob Herring 2018-08-06 20:59 ` Rob Herring 2018-08-07 7:20 ` Christoph Hellwig 2018-08-07 7:20 ` Christoph Hellwig 2018-08-08 2:17 ` Palmer Dabbelt 2018-08-08 2:17 ` Palmer Dabbelt 2018-08-08 6:42 ` Atish Patra 2018-08-08 6:42 ` Atish Patra 2018-08-08 14:16 ` Rob Herring 2018-08-08 14:16 ` Rob Herring 2018-08-08 15:09 ` Christoph Hellwig 2018-08-08 15:09 ` Christoph Hellwig 2018-08-08 16:47 ` Marc Zyngier 2018-08-08 16:47 ` Marc Zyngier 2018-08-08 16:57 ` Christoph Hellwig 2018-08-08 16:57 ` Christoph Hellwig 2018-08-09 10:19 ` Marc Zyngier 2018-08-09 10:19 ` Marc Zyngier 2018-08-08 19:38 ` Palmer Dabbelt 2018-08-08 19:38 ` Palmer Dabbelt 2018-08-08 23:32 ` Rob Herring 2018-08-08 23:32 ` Rob Herring 2018-08-09 6:29 ` Palmer Dabbelt 2018-08-09 6:29 ` Palmer Dabbelt 2018-08-09 6:43 ` Christoph Hellwig 2018-08-09 6:43 ` Christoph Hellwig 2018-08-10 16:57 ` Rob Herring 2018-08-10 16:57 ` Rob Herring 2018-08-10 20:09 ` Palmer Dabbelt 2018-08-10 20:09 ` Palmer Dabbelt 2018-08-13 14:09 ` Rob Herring 2018-08-13 14:09 ` Rob Herring 2018-08-02 11:50 ` [PATCH 04/11] RISC-V: remove timer leftovers Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` [PATCH 05/11] RISC-V: simplify software interrupt / IPI code Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` [PATCH 06/11] RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` [PATCH 07/11] RISC-V: add a definition for the SIE SEIE bit Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` [PATCH 08/11] RISC-V: implement low-level interrupt handling Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` [PATCH 09/11] RISC-V: Support per-hart timebase-frequency Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 22:19 ` Atish Patra 2018-08-02 22:19 ` Atish Patra 2018-08-03 12:33 ` Christoph Hellwig 2018-08-03 12:33 ` Christoph Hellwig 2018-08-04 9:58 ` Christoph Hellwig 2018-08-04 9:58 ` Christoph Hellwig 2018-08-06 20:34 ` Palmer Dabbelt 2018-08-06 20:34 ` Palmer Dabbelt 2018-08-06 20:34 ` Palmer Dabbelt 2018-08-08 6:47 ` Atish Patra 2018-08-08 6:47 ` Atish Patra 2018-08-02 11:50 ` [PATCH 10/11] irqchip: add a SiFive PLIC driver Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 23:13 ` Atish Patra 2018-08-02 23:13 ` Atish Patra 2018-08-03 12:29 ` Christoph Hellwig [this message] 2018-08-03 12:29 ` Christoph Hellwig 2018-08-02 11:50 ` [PATCH 11/11] clocksource: new RISC-V SBI timer driver Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 23:21 ` Atish Patra 2018-08-02 23:21 ` Atish Patra 2018-08-03 12:31 ` Christoph Hellwig 2018-08-03 12:31 ` Christoph Hellwig 2018-08-02 17:24 ` simplified RISC-V interrupt and clocksource handling v2 Palmer Dabbelt 2018-08-02 17:24 ` Palmer Dabbelt 2018-08-03 7:49 ` Thomas Gleixner 2018-08-03 7:49 ` Thomas Gleixner
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20180803122958.GA18301@lst.de \ --to=hch@lst.de \ --cc=anup@brainfault.org \ --cc=aou@eecs.berkeley.edu \ --cc=atish.patra@wdc.com \ --cc=devicetree@vger.kernel.org \ --cc=jason@lakedaemon.net \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-riscv@lists.infradead.org \ --cc=marc.zyngier@arm.com \ --cc=mark.rutland@arm.com \ --cc=palmer@sifive.com \ --cc=robh+dt@kernel.org \ --cc=shorne@gmail.com \ --cc=tglx@linutronix.de \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.