From: Rob Herring <robh+dt@kernel.org> To: atish.patra@wdc.com Cc: Christoph Hellwig <hch@lst.de>, Thomas Gleixner <tglx@linutronix.de>, Palmer Dabbelt <palmer@sifive.com>, Jason Cooper <jason@lakedaemon.net>, Marc Zyngier <marc.zyngier@arm.com>, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, devicetree@vger.kernel.org, Albert Ou <aou@eecs.berkeley.edu>, Anup Patel <anup@brainfault.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, linux-riscv@lists.infradead.org, Stafford Horne <shorne@gmail.com> Subject: Re: [PATCH 03/11] dt-bindings: interrupt-controller: RISC-V PLIC documentation Date: Mon, 6 Aug 2018 14:59:48 -0600 [thread overview] Message-ID: <CAL_Jsq+pVzqKUbhErRr15JX2mPUOSTp_ddGvu9KAuf=TtXfduQ@mail.gmail.com> (raw) In-Reply-To: <0093fadc-a150-3745-e73d-e579bfdfabfb@wdc.com> On Thu, Aug 2, 2018 at 4:08 PM Atish Patra <atish.patra@wdc.com> wrote: > > On 8/2/18 4:50 AM, Christoph Hellwig wrote: > > From: Palmer Dabbelt <palmer@dabbelt.com> > > > > This patch adds documentation for the platform-level interrupt > > controller (PLIC) found in all RISC-V systems. This interrupt > > controller routes interrupts from all the devices in the system to each > > hart-local interrupt controller. > > > > Note: the DTS bindings for the PLIC aren't set in stone yet, as we might > > want to change how we're specifying holes in the hart list. > > > > Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> > > [hch: various fixes and updates] > > Signed-off-by: Christoph Hellwig <hch@lst.de> > > --- > > .../interrupt-controller/sifive,plic0.txt | 57 +++++++++++++++++++ > > 1 file changed, 57 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sifive,plic0.txt > > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic0.txt b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic0.txt > > new file mode 100644 > > index 000000000000..c756cd208a93 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic0.txt > > @@ -0,0 +1,57 @@ > > +SiFive Platform-Level Interrupt Controller (PLIC) > > +------------------------------------------------- > > + > > +SiFive SOCs include an implementation of the Platform-Level Interrupt Controller > > +(PLIC) high-level specification in the RISC-V Privileged Architecture > > +specification. The PLIC connects all external interrupts in the system to all > > +hart contexts in the system, via the external interrupt source in each hart. > > + > > +A hart context is a privilege mode in a hardware execution thread. For example, > > +in an 4 core system with 2-way SMT, you have 8 harts and probably at least two > > +privilege modes per hart; machine mode and supervisor mode. > > + > > +Each interrupt can be enabled on per-context basis. Any context can claim > > +a pending enabled interrupt and then release it once it has been handled. > > + > > +Each interrupt has a configurable priority. Higher priority interrupts are > > +serviced first. Each context can specify a priority threshold. Interrupts > > +with priority below this threshold will not cause the PLIC to raise its > > +interrupt line leading to the context. > > + > > +While the PLIC supports both edge-triggered and level-triggered interrupts, > > +interrupt handlers are oblivious to this distinction and therefore it is not > > +specified in the PLIC device-tree binding. > > + > > +While the RISC-V ISA doesn't specify a memory layout for the PLIC, the > > +"sifive,plic0" device is a concrete implementation of the PLIC that contains a > > +specific memory layout, which is documented in chapter 8 of the SiFive U5 > > +Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>. > > + > > +Required properties: > > +- compatible : "sifive,plic0" > > +- #address-cells : should be <0> > > +- #interrupt-cells : should be <1> > > +- interrupt-controller : Identifies the node as an interrupt controller > > +- reg : Should contain 1 register range (address and length) > > The one in the real device tree has two entries. > reg = <0x00000000 0x0c000000 0x00000000 0x04000000>; > > Is it intentional or just incorrect entry left over from earlier days? > > + reg = <0xc000000 0x4000000>; Looks to me like one has #size-cells and #address-cells set to 2 and the example is using 1. Rob
WARNING: multiple messages have this Message-ID (diff)
From: robh+dt@kernel.org (Rob Herring) To: linux-riscv@lists.infradead.org Subject: [PATCH 03/11] dt-bindings: interrupt-controller: RISC-V PLIC documentation Date: Mon, 6 Aug 2018 14:59:48 -0600 [thread overview] Message-ID: <CAL_Jsq+pVzqKUbhErRr15JX2mPUOSTp_ddGvu9KAuf=TtXfduQ@mail.gmail.com> (raw) In-Reply-To: <0093fadc-a150-3745-e73d-e579bfdfabfb@wdc.com> On Thu, Aug 2, 2018 at 4:08 PM Atish Patra <atish.patra@wdc.com> wrote: > > On 8/2/18 4:50 AM, Christoph Hellwig wrote: > > From: Palmer Dabbelt <palmer@dabbelt.com> > > > > This patch adds documentation for the platform-level interrupt > > controller (PLIC) found in all RISC-V systems. This interrupt > > controller routes interrupts from all the devices in the system to each > > hart-local interrupt controller. > > > > Note: the DTS bindings for the PLIC aren't set in stone yet, as we might > > want to change how we're specifying holes in the hart list. > > > > Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> > > [hch: various fixes and updates] > > Signed-off-by: Christoph Hellwig <hch@lst.de> > > --- > > .../interrupt-controller/sifive,plic0.txt | 57 +++++++++++++++++++ > > 1 file changed, 57 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sifive,plic0.txt > > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic0.txt b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic0.txt > > new file mode 100644 > > index 000000000000..c756cd208a93 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic0.txt > > @@ -0,0 +1,57 @@ > > +SiFive Platform-Level Interrupt Controller (PLIC) > > +------------------------------------------------- > > + > > +SiFive SOCs include an implementation of the Platform-Level Interrupt Controller > > +(PLIC) high-level specification in the RISC-V Privileged Architecture > > +specification. The PLIC connects all external interrupts in the system to all > > +hart contexts in the system, via the external interrupt source in each hart. > > + > > +A hart context is a privilege mode in a hardware execution thread. For example, > > +in an 4 core system with 2-way SMT, you have 8 harts and probably at least two > > +privilege modes per hart; machine mode and supervisor mode. > > + > > +Each interrupt can be enabled on per-context basis. Any context can claim > > +a pending enabled interrupt and then release it once it has been handled. > > + > > +Each interrupt has a configurable priority. Higher priority interrupts are > > +serviced first. Each context can specify a priority threshold. Interrupts > > +with priority below this threshold will not cause the PLIC to raise its > > +interrupt line leading to the context. > > + > > +While the PLIC supports both edge-triggered and level-triggered interrupts, > > +interrupt handlers are oblivious to this distinction and therefore it is not > > +specified in the PLIC device-tree binding. > > + > > +While the RISC-V ISA doesn't specify a memory layout for the PLIC, the > > +"sifive,plic0" device is a concrete implementation of the PLIC that contains a > > +specific memory layout, which is documented in chapter 8 of the SiFive U5 > > +Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>. > > + > > +Required properties: > > +- compatible : "sifive,plic0" > > +- #address-cells : should be <0> > > +- #interrupt-cells : should be <1> > > +- interrupt-controller : Identifies the node as an interrupt controller > > +- reg : Should contain 1 register range (address and length) > > The one in the real device tree has two entries. > reg = <0x00000000 0x0c000000 0x00000000 0x04000000>; > > Is it intentional or just incorrect entry left over from earlier days? > > + reg = <0xc000000 0x4000000>; Looks to me like one has #size-cells and #address-cells set to 2 and the example is using 1. Rob
next prev parent reply other threads:[~2018-08-06 21:00 UTC|newest] Thread overview: 99+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-08-02 11:49 simplified RISC-V interrupt and clocksource handling v2 Christoph Hellwig 2018-08-02 11:49 ` Christoph Hellwig 2018-08-02 11:49 ` Christoph Hellwig 2018-08-02 11:49 ` [PATCH 01/11] dt-bindings: Correct RISC-V's timebase-frequency Christoph Hellwig 2018-08-02 11:49 ` Christoph Hellwig 2018-08-02 11:49 ` Christoph Hellwig 2018-08-08 14:44 ` Rob Herring 2018-08-08 14:44 ` Rob Herring 2018-08-02 11:49 ` [PATCH 02/11] dt-bindings: Add an enable method to RISC-V Christoph Hellwig 2018-08-02 11:49 ` Christoph Hellwig 2018-08-02 11:49 ` Christoph Hellwig 2018-08-08 14:43 ` Rob Herring 2018-08-08 14:43 ` Rob Herring 2018-08-02 11:50 ` [PATCH 03/11] dt-bindings: interrupt-controller: RISC-V PLIC documentation Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 22:08 ` Atish Patra 2018-08-02 22:08 ` Atish Patra 2018-08-03 13:30 ` Christoph Hellwig 2018-08-03 13:30 ` Christoph Hellwig 2018-08-06 20:59 ` Rob Herring [this message] 2018-08-06 20:59 ` Rob Herring 2018-08-07 7:20 ` Christoph Hellwig 2018-08-07 7:20 ` Christoph Hellwig 2018-08-08 2:17 ` Palmer Dabbelt 2018-08-08 2:17 ` Palmer Dabbelt 2018-08-08 6:42 ` Atish Patra 2018-08-08 6:42 ` Atish Patra 2018-08-08 14:16 ` Rob Herring 2018-08-08 14:16 ` Rob Herring 2018-08-08 15:09 ` Christoph Hellwig 2018-08-08 15:09 ` Christoph Hellwig 2018-08-08 16:47 ` Marc Zyngier 2018-08-08 16:47 ` Marc Zyngier 2018-08-08 16:57 ` Christoph Hellwig 2018-08-08 16:57 ` Christoph Hellwig 2018-08-09 10:19 ` Marc Zyngier 2018-08-09 10:19 ` Marc Zyngier 2018-08-08 19:38 ` Palmer Dabbelt 2018-08-08 19:38 ` Palmer Dabbelt 2018-08-08 23:32 ` Rob Herring 2018-08-08 23:32 ` Rob Herring 2018-08-09 6:29 ` Palmer Dabbelt 2018-08-09 6:29 ` Palmer Dabbelt 2018-08-09 6:43 ` Christoph Hellwig 2018-08-09 6:43 ` Christoph Hellwig 2018-08-10 16:57 ` Rob Herring 2018-08-10 16:57 ` Rob Herring 2018-08-10 20:09 ` Palmer Dabbelt 2018-08-10 20:09 ` Palmer Dabbelt 2018-08-13 14:09 ` Rob Herring 2018-08-13 14:09 ` Rob Herring 2018-08-02 11:50 ` [PATCH 04/11] RISC-V: remove timer leftovers Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` [PATCH 05/11] RISC-V: simplify software interrupt / IPI code Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` [PATCH 06/11] RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` [PATCH 07/11] RISC-V: add a definition for the SIE SEIE bit Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` [PATCH 08/11] RISC-V: implement low-level interrupt handling Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` [PATCH 09/11] RISC-V: Support per-hart timebase-frequency Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 22:19 ` Atish Patra 2018-08-02 22:19 ` Atish Patra 2018-08-03 12:33 ` Christoph Hellwig 2018-08-03 12:33 ` Christoph Hellwig 2018-08-04 9:58 ` Christoph Hellwig 2018-08-04 9:58 ` Christoph Hellwig 2018-08-06 20:34 ` Palmer Dabbelt 2018-08-06 20:34 ` Palmer Dabbelt 2018-08-06 20:34 ` Palmer Dabbelt 2018-08-08 6:47 ` Atish Patra 2018-08-08 6:47 ` Atish Patra 2018-08-02 11:50 ` [PATCH 10/11] irqchip: add a SiFive PLIC driver Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 23:13 ` Atish Patra 2018-08-02 23:13 ` Atish Patra 2018-08-03 12:29 ` Christoph Hellwig 2018-08-03 12:29 ` Christoph Hellwig 2018-08-02 11:50 ` [PATCH 11/11] clocksource: new RISC-V SBI timer driver Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 11:50 ` Christoph Hellwig 2018-08-02 23:21 ` Atish Patra 2018-08-02 23:21 ` Atish Patra 2018-08-03 12:31 ` Christoph Hellwig 2018-08-03 12:31 ` Christoph Hellwig 2018-08-02 17:24 ` simplified RISC-V interrupt and clocksource handling v2 Palmer Dabbelt 2018-08-02 17:24 ` Palmer Dabbelt 2018-08-03 7:49 ` Thomas Gleixner 2018-08-03 7:49 ` Thomas Gleixner
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