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From: Christoph Hellwig <hch@lst.de>
To: Palmer Dabbelt <palmer@dabbelt.com>
Cc: robh+dt@kernel.org, atish.patra@wdc.com,
	Christoph Hellwig <hch@lst.de>,
	tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com,
	mark.rutland@arm.com, devicetree@vger.kernel.org,
	aou@eecs.berkeley.edu, anup@brainfault.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	shorne@gmail.com
Subject: Re: [PATCH 03/11] dt-bindings: interrupt-controller: RISC-V PLIC documentation
Date: Thu, 9 Aug 2018 08:43:53 +0200	[thread overview]
Message-ID: <20180809064353.GA19566@lst.de> (raw)
In-Reply-To: <mhng-cfa17eb2-3548-48ee-9216-74a3607a3091@palmer-si-x1c4>

On Wed, Aug 08, 2018 at 11:29:17PM -0700, Palmer Dabbelt wrote:
>> So I guess to answer my question, you are just making up version
>> numbers. Unless you are doing the IP verilog too, don't do that.
>
> Well, in this case my proposal would be that we change the hardware team's 
> versioning scheme to match whatever we decide on the versioning scheme 
> should be as a part of this discussion.  I proposed accepting whatever 
> versioning scheme is decided upon hereto the hardware team before 
> discussing changing the naming scheme and they agreed to do so.
>
> So we're really in the drivers' seat here.
>
>> If you want to use just 'sifive,plic' then I'm fine with that. I've
>> given you the potential problems with that and they will be your
>> problems to deal with. Maybe you'll get lucky. Plus it won't be a
>> problem for the 1st implementation.
>
> I'd prefer to have some versioning scheme, that's why I'm talking so much 
> about this :).  I really just want to learn how to get the right one, as 
> I'm quite new to all this and we'll have many of these.

Based on the discussion so far I think we should settle for sifive,plic +
an actual implementation string suggested by Palmer and Andrew.

This is what I have right now:

http://git.infradead.org/users/hch/riscv.git/commitdiff/1972707029f8f1216dbe14bd7791295e4b37f560

and which I'd like to send out before it is too late.

WARNING: multiple messages have this Message-ID (diff)
From: hch@lst.de (Christoph Hellwig)
To: linux-riscv@lists.infradead.org
Subject: [PATCH 03/11] dt-bindings: interrupt-controller: RISC-V PLIC documentation
Date: Thu, 9 Aug 2018 08:43:53 +0200	[thread overview]
Message-ID: <20180809064353.GA19566@lst.de> (raw)
In-Reply-To: <mhng-cfa17eb2-3548-48ee-9216-74a3607a3091@palmer-si-x1c4>

On Wed, Aug 08, 2018 at 11:29:17PM -0700, Palmer Dabbelt wrote:
>> So I guess to answer my question, you are just making up version
>> numbers. Unless you are doing the IP verilog too, don't do that.
>
> Well, in this case my proposal would be that we change the hardware team's 
> versioning scheme to match whatever we decide on the versioning scheme 
> should be as a part of this discussion.  I proposed accepting whatever 
> versioning scheme is decided upon hereto the hardware team before 
> discussing changing the naming scheme and they agreed to do so.
>
> So we're really in the drivers' seat here.
>
>> If you want to use just 'sifive,plic' then I'm fine with that. I've
>> given you the potential problems with that and they will be your
>> problems to deal with. Maybe you'll get lucky. Plus it won't be a
>> problem for the 1st implementation.
>
> I'd prefer to have some versioning scheme, that's why I'm talking so much 
> about this :).  I really just want to learn how to get the right one, as 
> I'm quite new to all this and we'll have many of these.

Based on the discussion so far I think we should settle for sifive,plic +
an actual implementation string suggested by Palmer and Andrew.

This is what I have right now:

http://git.infradead.org/users/hch/riscv.git/commitdiff/1972707029f8f1216dbe14bd7791295e4b37f560

and which I'd like to send out before it is too late.

  reply	other threads:[~2018-08-09  6:38 UTC|newest]

Thread overview: 99+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-02 11:49 simplified RISC-V interrupt and clocksource handling v2 Christoph Hellwig
2018-08-02 11:49 ` Christoph Hellwig
2018-08-02 11:49 ` Christoph Hellwig
2018-08-02 11:49 ` [PATCH 01/11] dt-bindings: Correct RISC-V's timebase-frequency Christoph Hellwig
2018-08-02 11:49   ` Christoph Hellwig
2018-08-02 11:49   ` Christoph Hellwig
2018-08-08 14:44   ` Rob Herring
2018-08-08 14:44     ` Rob Herring
2018-08-02 11:49 ` [PATCH 02/11] dt-bindings: Add an enable method to RISC-V Christoph Hellwig
2018-08-02 11:49   ` Christoph Hellwig
2018-08-02 11:49   ` Christoph Hellwig
2018-08-08 14:43   ` Rob Herring
2018-08-08 14:43     ` Rob Herring
2018-08-02 11:50 ` [PATCH 03/11] dt-bindings: interrupt-controller: RISC-V PLIC documentation Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 22:08   ` Atish Patra
2018-08-02 22:08     ` Atish Patra
2018-08-03 13:30     ` Christoph Hellwig
2018-08-03 13:30       ` Christoph Hellwig
2018-08-06 20:59     ` Rob Herring
2018-08-06 20:59       ` Rob Herring
2018-08-07  7:20       ` Christoph Hellwig
2018-08-07  7:20         ` Christoph Hellwig
2018-08-08  2:17       ` Palmer Dabbelt
2018-08-08  2:17         ` Palmer Dabbelt
2018-08-08  6:42         ` Atish Patra
2018-08-08  6:42           ` Atish Patra
2018-08-08 14:16         ` Rob Herring
2018-08-08 14:16           ` Rob Herring
2018-08-08 15:09           ` Christoph Hellwig
2018-08-08 15:09             ` Christoph Hellwig
2018-08-08 16:47             ` Marc Zyngier
2018-08-08 16:47               ` Marc Zyngier
2018-08-08 16:57               ` Christoph Hellwig
2018-08-08 16:57                 ` Christoph Hellwig
2018-08-09 10:19                 ` Marc Zyngier
2018-08-09 10:19                   ` Marc Zyngier
2018-08-08 19:38           ` Palmer Dabbelt
2018-08-08 19:38             ` Palmer Dabbelt
2018-08-08 23:32             ` Rob Herring
2018-08-08 23:32               ` Rob Herring
2018-08-09  6:29               ` Palmer Dabbelt
2018-08-09  6:29                 ` Palmer Dabbelt
2018-08-09  6:43                 ` Christoph Hellwig [this message]
2018-08-09  6:43                   ` Christoph Hellwig
2018-08-10 16:57                 ` Rob Herring
2018-08-10 16:57                   ` Rob Herring
2018-08-10 20:09                   ` Palmer Dabbelt
2018-08-10 20:09                     ` Palmer Dabbelt
2018-08-13 14:09                     ` Rob Herring
2018-08-13 14:09                       ` Rob Herring
2018-08-02 11:50 ` [PATCH 04/11] RISC-V: remove timer leftovers Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50 ` [PATCH 05/11] RISC-V: simplify software interrupt / IPI code Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50 ` [PATCH 06/11] RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50 ` [PATCH 07/11] RISC-V: add a definition for the SIE SEIE bit Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50 ` [PATCH 08/11] RISC-V: implement low-level interrupt handling Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50 ` [PATCH 09/11] RISC-V: Support per-hart timebase-frequency Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 22:19   ` Atish Patra
2018-08-02 22:19     ` Atish Patra
2018-08-03 12:33     ` Christoph Hellwig
2018-08-03 12:33       ` Christoph Hellwig
2018-08-04  9:58       ` Christoph Hellwig
2018-08-04  9:58         ` Christoph Hellwig
2018-08-06 20:34       ` Palmer Dabbelt
2018-08-06 20:34         ` Palmer Dabbelt
2018-08-06 20:34         ` Palmer Dabbelt
2018-08-08  6:47         ` Atish Patra
2018-08-08  6:47           ` Atish Patra
2018-08-02 11:50 ` [PATCH 10/11] irqchip: add a SiFive PLIC driver Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 23:13   ` Atish Patra
2018-08-02 23:13     ` Atish Patra
2018-08-03 12:29     ` Christoph Hellwig
2018-08-03 12:29       ` Christoph Hellwig
2018-08-02 11:50 ` [PATCH 11/11] clocksource: new RISC-V SBI timer driver Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 23:21   ` Atish Patra
2018-08-02 23:21     ` Atish Patra
2018-08-03 12:31     ` Christoph Hellwig
2018-08-03 12:31       ` Christoph Hellwig
2018-08-02 17:24 ` simplified RISC-V interrupt and clocksource handling v2 Palmer Dabbelt
2018-08-02 17:24   ` Palmer Dabbelt
2018-08-03  7:49   ` Thomas Gleixner
2018-08-03  7:49     ` Thomas Gleixner

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