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From: Atish Patra <atish.patra@wdc.com>
To: Palmer Dabbelt <palmer@dabbelt.com>, Christoph Hellwig <hch@lst.de>
Cc: "tglx@linutronix.de" <tglx@linutronix.de>,
	"jason@lakedaemon.net" <jason@lakedaemon.net>,
	"marc.zyngier@arm.com" <marc.zyngier@arm.com>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
	"anup@brainfault.org" <anup@brainfault.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	"shorne@gmail.com" <shorne@gmail.com>
Subject: Re: [PATCH 09/11] RISC-V: Support per-hart timebase-frequency
Date: Tue, 7 Aug 2018 23:47:13 -0700	[thread overview]
Message-ID: <b4ddcb20-6109-22ac-4691-c2c012ea112a@wdc.com> (raw)
In-Reply-To: <mhng-d315d8a6-c4db-4ec8-927b-fc9f1d8e7872@palmer-si-x1c4>

On 8/6/18 1:34 PM, Palmer Dabbelt wrote:
> On Fri, 03 Aug 2018 05:33:57 PDT (-0700), Christoph Hellwig wrote:
>> On Thu, Aug 02, 2018 at 03:19:49PM -0700, Atish Patra wrote:
>>> On 8/2/18 4:50 AM, Christoph Hellwig wrote:
>>>> From: Palmer Dabbelt <palmer@sifive.com>
>>>>
>>>> Follow the updated DT specs and read the timebase-frequency from the
>>>> CPU 0 node.
>>>>
>>>
>>> However, the DT in the HighFive Unleashed has the entry at the wrong place.
>>>
>>> Even the example in github also at wrong place.
>>> https://github.com/riscv/riscv-device-tree-doc/pull/8/commits/2461d481329c55005fcbe684f0d6bdb3b7f0a432
>>>
>>> DT should be consistent between Documentation and the one in the hardware.
>>> I can fix them in bbl & submit a bbl patch. But I am not sure if that's an
>>> acceptable way to do it.
>>
>> I'll need to have comments from Palmer and/or someone else at SiFive
>> here.  Personally I really don't care where we document the timebase,
>> as this patch supports both locations anywhere.  For now I'll just update
>> the commit log to state that more explicitly.
> 
> You're welcome to submit a BBL patch to make this all match, but from my
> understanding of the device tree spec putting timebase-frequency in either
> place should be legal so it's not a critical fix.  That said, it's better to
> have them match than not match.
> 

ok. I will add it my TODO list as a low priority task. Following DT 
entries can be fixed for now.

1. timebase-frequency
2. next-level-cache

Regards,
Atish

WARNING: multiple messages have this Message-ID (diff)
From: atish.patra@wdc.com (Atish Patra)
To: linux-riscv@lists.infradead.org
Subject: [PATCH 09/11] RISC-V: Support per-hart timebase-frequency
Date: Tue, 7 Aug 2018 23:47:13 -0700	[thread overview]
Message-ID: <b4ddcb20-6109-22ac-4691-c2c012ea112a@wdc.com> (raw)
In-Reply-To: <mhng-d315d8a6-c4db-4ec8-927b-fc9f1d8e7872@palmer-si-x1c4>

On 8/6/18 1:34 PM, Palmer Dabbelt wrote:
> On Fri, 03 Aug 2018 05:33:57 PDT (-0700), Christoph Hellwig wrote:
>> On Thu, Aug 02, 2018 at 03:19:49PM -0700, Atish Patra wrote:
>>> On 8/2/18 4:50 AM, Christoph Hellwig wrote:
>>>> From: Palmer Dabbelt <palmer@sifive.com>
>>>>
>>>> Follow the updated DT specs and read the timebase-frequency from the
>>>> CPU 0 node.
>>>>
>>>
>>> However, the DT in the HighFive Unleashed has the entry at the wrong place.
>>>
>>> Even the example in github also at wrong place.
>>> https://github.com/riscv/riscv-device-tree-doc/pull/8/commits/2461d481329c55005fcbe684f0d6bdb3b7f0a432
>>>
>>> DT should be consistent between Documentation and the one in the hardware.
>>> I can fix them in bbl & submit a bbl patch. But I am not sure if that's an
>>> acceptable way to do it.
>>
>> I'll need to have comments from Palmer and/or someone else at SiFive
>> here.  Personally I really don't care where we document the timebase,
>> as this patch supports both locations anywhere.  For now I'll just update
>> the commit log to state that more explicitly.
> 
> You're welcome to submit a BBL patch to make this all match, but from my
> understanding of the device tree spec putting timebase-frequency in either
> place should be legal so it's not a critical fix.  That said, it's better to
> have them match than not match.
> 

ok. I will add it my TODO list as a low priority task. Following DT 
entries can be fixed for now.

1. timebase-frequency
2. next-level-cache

Regards,
Atish

  reply	other threads:[~2018-08-08  6:47 UTC|newest]

Thread overview: 99+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-02 11:49 simplified RISC-V interrupt and clocksource handling v2 Christoph Hellwig
2018-08-02 11:49 ` Christoph Hellwig
2018-08-02 11:49 ` Christoph Hellwig
2018-08-02 11:49 ` [PATCH 01/11] dt-bindings: Correct RISC-V's timebase-frequency Christoph Hellwig
2018-08-02 11:49   ` Christoph Hellwig
2018-08-02 11:49   ` Christoph Hellwig
2018-08-08 14:44   ` Rob Herring
2018-08-08 14:44     ` Rob Herring
2018-08-02 11:49 ` [PATCH 02/11] dt-bindings: Add an enable method to RISC-V Christoph Hellwig
2018-08-02 11:49   ` Christoph Hellwig
2018-08-02 11:49   ` Christoph Hellwig
2018-08-08 14:43   ` Rob Herring
2018-08-08 14:43     ` Rob Herring
2018-08-02 11:50 ` [PATCH 03/11] dt-bindings: interrupt-controller: RISC-V PLIC documentation Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 22:08   ` Atish Patra
2018-08-02 22:08     ` Atish Patra
2018-08-03 13:30     ` Christoph Hellwig
2018-08-03 13:30       ` Christoph Hellwig
2018-08-06 20:59     ` Rob Herring
2018-08-06 20:59       ` Rob Herring
2018-08-07  7:20       ` Christoph Hellwig
2018-08-07  7:20         ` Christoph Hellwig
2018-08-08  2:17       ` Palmer Dabbelt
2018-08-08  2:17         ` Palmer Dabbelt
2018-08-08  6:42         ` Atish Patra
2018-08-08  6:42           ` Atish Patra
2018-08-08 14:16         ` Rob Herring
2018-08-08 14:16           ` Rob Herring
2018-08-08 15:09           ` Christoph Hellwig
2018-08-08 15:09             ` Christoph Hellwig
2018-08-08 16:47             ` Marc Zyngier
2018-08-08 16:47               ` Marc Zyngier
2018-08-08 16:57               ` Christoph Hellwig
2018-08-08 16:57                 ` Christoph Hellwig
2018-08-09 10:19                 ` Marc Zyngier
2018-08-09 10:19                   ` Marc Zyngier
2018-08-08 19:38           ` Palmer Dabbelt
2018-08-08 19:38             ` Palmer Dabbelt
2018-08-08 23:32             ` Rob Herring
2018-08-08 23:32               ` Rob Herring
2018-08-09  6:29               ` Palmer Dabbelt
2018-08-09  6:29                 ` Palmer Dabbelt
2018-08-09  6:43                 ` Christoph Hellwig
2018-08-09  6:43                   ` Christoph Hellwig
2018-08-10 16:57                 ` Rob Herring
2018-08-10 16:57                   ` Rob Herring
2018-08-10 20:09                   ` Palmer Dabbelt
2018-08-10 20:09                     ` Palmer Dabbelt
2018-08-13 14:09                     ` Rob Herring
2018-08-13 14:09                       ` Rob Herring
2018-08-02 11:50 ` [PATCH 04/11] RISC-V: remove timer leftovers Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50 ` [PATCH 05/11] RISC-V: simplify software interrupt / IPI code Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50 ` [PATCH 06/11] RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50 ` [PATCH 07/11] RISC-V: add a definition for the SIE SEIE bit Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50 ` [PATCH 08/11] RISC-V: implement low-level interrupt handling Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50 ` [PATCH 09/11] RISC-V: Support per-hart timebase-frequency Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 22:19   ` Atish Patra
2018-08-02 22:19     ` Atish Patra
2018-08-03 12:33     ` Christoph Hellwig
2018-08-03 12:33       ` Christoph Hellwig
2018-08-04  9:58       ` Christoph Hellwig
2018-08-04  9:58         ` Christoph Hellwig
2018-08-06 20:34       ` Palmer Dabbelt
2018-08-06 20:34         ` Palmer Dabbelt
2018-08-06 20:34         ` Palmer Dabbelt
2018-08-08  6:47         ` Atish Patra [this message]
2018-08-08  6:47           ` Atish Patra
2018-08-02 11:50 ` [PATCH 10/11] irqchip: add a SiFive PLIC driver Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 23:13   ` Atish Patra
2018-08-02 23:13     ` Atish Patra
2018-08-03 12:29     ` Christoph Hellwig
2018-08-03 12:29       ` Christoph Hellwig
2018-08-02 11:50 ` [PATCH 11/11] clocksource: new RISC-V SBI timer driver Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 11:50   ` Christoph Hellwig
2018-08-02 23:21   ` Atish Patra
2018-08-02 23:21     ` Atish Patra
2018-08-03 12:31     ` Christoph Hellwig
2018-08-03 12:31       ` Christoph Hellwig
2018-08-02 17:24 ` simplified RISC-V interrupt and clocksource handling v2 Palmer Dabbelt
2018-08-02 17:24   ` Palmer Dabbelt
2018-08-03  7:49   ` Thomas Gleixner
2018-08-03  7:49     ` Thomas Gleixner

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