* [U-Boot] [PATCH 2/9] ARM: rmobile: Remove console parameter from bootargs on Gen3
2018-10-18 18:37 [U-Boot] [PATCH 1/9] ARM: rmobile: Fix CPGWPR Address define and Settings on Gen3 Marek Vasut
@ 2018-10-18 18:37 ` Marek Vasut
2018-10-18 18:37 ` [U-Boot] [PATCH 3/9] ARM: rmobile: Remove TMU0/TMU1 settings " Marek Vasut
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Marek Vasut @ 2018-10-18 18:37 UTC (permalink / raw)
To: u-boot
From: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
This patch removes 'console=' argument, because kernel uses
stdout-path as parameter.
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
---
configs/r8a7795_salvator-x_defconfig | 2 +-
configs/r8a7795_ulcb_defconfig | 2 +-
configs/r8a77965_salvator-x_defconfig | 2 +-
configs/r8a7796_salvator-x_defconfig | 2 +-
configs/r8a7796_ulcb_defconfig | 2 +-
configs/r8a77970_eagle_defconfig | 2 +-
configs/r8a77990_ebisu_defconfig | 2 +-
configs/r8a77995_draak_defconfig | 2 +-
8 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/configs/r8a7795_salvator-x_defconfig b/configs/r8a7795_salvator-x_defconfig
index aae38e84a0..40712a44c3 100644
--- a/configs/r8a7795_salvator-x_defconfig
+++ b/configs/r8a7795_salvator-x_defconfig
@@ -8,7 +8,7 @@ CONFIG_SMBIOS_PRODUCT_NAME=""
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
+CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a7795-salvator-x.dtb"
CONFIG_VERSION_VARIABLE=y
diff --git a/configs/r8a7795_ulcb_defconfig b/configs/r8a7795_ulcb_defconfig
index c341e1aaac..f1d150b5a0 100644
--- a/configs/r8a7795_ulcb_defconfig
+++ b/configs/r8a7795_ulcb_defconfig
@@ -8,7 +8,7 @@ CONFIG_SMBIOS_PRODUCT_NAME=""
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
+CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a7795-h3ulcb.dtb"
CONFIG_VERSION_VARIABLE=y
diff --git a/configs/r8a77965_salvator-x_defconfig b/configs/r8a77965_salvator-x_defconfig
index 567f63977e..72549e2836 100644
--- a/configs/r8a77965_salvator-x_defconfig
+++ b/configs/r8a77965_salvator-x_defconfig
@@ -9,7 +9,7 @@ CONFIG_SMBIOS_PRODUCT_NAME=""
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
+CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a77965-salvator-x.dtb"
CONFIG_VERSION_VARIABLE=y
diff --git a/configs/r8a7796_salvator-x_defconfig b/configs/r8a7796_salvator-x_defconfig
index e3551a8007..7c39268a43 100644
--- a/configs/r8a7796_salvator-x_defconfig
+++ b/configs/r8a7796_salvator-x_defconfig
@@ -9,7 +9,7 @@ CONFIG_SMBIOS_PRODUCT_NAME=""
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
+CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a7796-salvator-x.dtb"
CONFIG_VERSION_VARIABLE=y
diff --git a/configs/r8a7796_ulcb_defconfig b/configs/r8a7796_ulcb_defconfig
index 8086261637..ef5c9443f9 100644
--- a/configs/r8a7796_ulcb_defconfig
+++ b/configs/r8a7796_ulcb_defconfig
@@ -9,7 +9,7 @@ CONFIG_SMBIOS_PRODUCT_NAME=""
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
+CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a7796-m3ulcb.dtb"
CONFIG_VERSION_VARIABLE=y
diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig
index 0cd47c1203..67ef2632a9 100644
--- a/configs/r8a77970_eagle_defconfig
+++ b/configs/r8a77970_eagle_defconfig
@@ -9,7 +9,7 @@ CONFIG_SMBIOS_PRODUCT_NAME=""
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
+CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a77970-eagle.dtb"
CONFIG_VERSION_VARIABLE=y
diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig
index 4f9ebad23d..7363310d52 100644
--- a/configs/r8a77990_ebisu_defconfig
+++ b/configs/r8a77990_ebisu_defconfig
@@ -9,7 +9,7 @@ CONFIG_SMBIOS_PRODUCT_NAME=""
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC0,115200"
+CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a77990-ebisu.dtb"
CONFIG_VERSION_VARIABLE=y
diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig
index ca89a12b7b..0f1189b671 100644
--- a/configs/r8a77995_draak_defconfig
+++ b/configs/r8a77995_draak_defconfig
@@ -9,7 +9,7 @@ CONFIG_SMBIOS_PRODUCT_NAME=""
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
+CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a77995-draak.dtb"
CONFIG_VERSION_VARIABLE=y
--
2.18.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [U-Boot] [PATCH 3/9] ARM: rmobile: Remove TMU0/TMU1 settings on Gen3
2018-10-18 18:37 [U-Boot] [PATCH 1/9] ARM: rmobile: Fix CPGWPR Address define and Settings on Gen3 Marek Vasut
2018-10-18 18:37 ` [U-Boot] [PATCH 2/9] ARM: rmobile: Remove console parameter from bootargs " Marek Vasut
@ 2018-10-18 18:37 ` Marek Vasut
2018-10-18 18:37 ` [U-Boot] [PATCH 4/9] ARM: rmobile: Remove Watchdog and CPG " Marek Vasut
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Marek Vasut @ 2018-10-18 18:37 UTC (permalink / raw)
To: u-boot
From: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
U-Boot uses ARM generic timer, TMU0 and TMU1 are not used, remove them.
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
---
board/renesas/draak/draak.c | 5 -----
board/renesas/eagle/eagle.c | 5 -----
board/renesas/ebisu/ebisu.c | 5 -----
board/renesas/salvator-x/salvator-x.c | 5 -----
board/renesas/ulcb/ulcb.c | 5 -----
5 files changed, 25 deletions(-)
diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c
index e7f0bd7b65..f9ae74a39d 100644
--- a/board/renesas/draak/draak.c
+++ b/board/renesas/draak/draak.c
@@ -44,17 +44,12 @@ void s_init(void)
}
#define GSX_MSTP112 BIT(12) /* 3DG */
-#define TMU0_MSTP125 BIT(25) /* secure */
-#define TMU1_MSTP124 BIT(24) /* non-secure */
#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
#define DVFS_MSTP926 BIT(26)
#define HSUSB_MSTP704 BIT(4) /* HSUSB */
int board_early_init_f(void)
{
- /* TMU0,1 */ /* which use ? */
- mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
-
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
diff --git a/board/renesas/eagle/eagle.c b/board/renesas/eagle/eagle.c
index 9317410071..0e5efea19d 100644
--- a/board/renesas/eagle/eagle.c
+++ b/board/renesas/eagle/eagle.c
@@ -50,17 +50,12 @@ void s_init(void)
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
}
-#define TMU0_MSTP125 BIT(25) /* secure */
-
int board_early_init_f(void)
{
/* Unlock CPG access */
writel(0xA5A5FFFF, CPGWPR);
writel(0x5A5A0000, CPGWPCR);
- /* TMU0 */
- mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
-
return 0;
}
diff --git a/board/renesas/ebisu/ebisu.c b/board/renesas/ebisu/ebisu.c
index 248223b444..5d8b79eee3 100644
--- a/board/renesas/ebisu/ebisu.c
+++ b/board/renesas/ebisu/ebisu.c
@@ -30,13 +30,8 @@ void s_init(void)
{
}
-#define TMU0_MSTP125 BIT(25) /* secure */
-
int board_early_init_f(void)
{
- /* TMU0 */
- mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
-
return 0;
}
diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c
index 746403a5c5..cb5228a0bd 100644
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -45,17 +45,12 @@ void s_init(void)
}
#define GSX_MSTP112 BIT(12) /* 3DG */
-#define TMU0_MSTP125 BIT(25) /* secure */
-#define TMU1_MSTP124 BIT(24) /* non-secure */
#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
#define DVFS_MSTP926 BIT(26)
#define HSUSB_MSTP704 BIT(4) /* HSUSB */
int board_early_init_f(void)
{
- /* TMU0,1 */ /* which use ? */
- mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
-
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c
index dfe8efd3ac..fca6eae1fb 100644
--- a/board/renesas/ulcb/ulcb.c
+++ b/board/renesas/ulcb/ulcb.c
@@ -44,17 +44,12 @@ void s_init(void)
}
#define GSX_MSTP112 BIT(12) /* 3DG */
-#define TMU0_MSTP125 BIT(25) /* secure */
-#define TMU1_MSTP124 BIT(24) /* non-secure */
#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
#define DVFS_MSTP926 BIT(26)
#define HSUSB_MSTP704 BIT(4) /* HSUSB */
int board_early_init_f(void)
{
- /* TMU0,1 */ /* which use ? */
- mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
-
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
--
2.18.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [U-Boot] [PATCH 4/9] ARM: rmobile: Remove Watchdog and CPG settings on Gen3
2018-10-18 18:37 [U-Boot] [PATCH 1/9] ARM: rmobile: Fix CPGWPR Address define and Settings on Gen3 Marek Vasut
2018-10-18 18:37 ` [U-Boot] [PATCH 2/9] ARM: rmobile: Remove console parameter from bootargs " Marek Vasut
2018-10-18 18:37 ` [U-Boot] [PATCH 3/9] ARM: rmobile: Remove TMU0/TMU1 settings " Marek Vasut
@ 2018-10-18 18:37 ` Marek Vasut
2018-10-18 18:37 ` [U-Boot] [PATCH 5/9] ARM: rmobile: salvator-x: Remove GSX clock force supply Marek Vasut
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Marek Vasut @ 2018-10-18 18:37 UTC (permalink / raw)
To: u-boot
From: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
This code is unnecessary, because these registers are set by the
initial program loader (IPL).
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
---
board/renesas/draak/draak.c | 13 -------------
board/renesas/salvator-x/salvator-x.c | 13 -------------
board/renesas/ulcb/ulcb.c | 13 -------------
3 files changed, 39 deletions(-)
diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c
index f9ae74a39d..71fd5001c4 100644
--- a/board/renesas/draak/draak.c
+++ b/board/renesas/draak/draak.c
@@ -26,21 +26,8 @@
DECLARE_GLOBAL_DATA_PTR;
-#define CPGWPCR 0xE6150904
-#define CPGWPR 0xE6150900
-
-#define CLK2MHZ(clk) (clk / 1000 / 1000)
void s_init(void)
{
- struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
- struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
-
- /* Watchdog init */
- writel(0xA5A5A500, &rwdt->rwtcsra);
- writel(0xA5A5A500, &swdt->swtcsra);
-
- writel(0x5A5AFFFF, CPGWPR);
- writel(0xA5A50000, CPGWPCR);
}
#define GSX_MSTP112 BIT(12) /* 3DG */
diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c
index cb5228a0bd..296aa90a12 100644
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -27,21 +27,8 @@
DECLARE_GLOBAL_DATA_PTR;
-#define CPGWPCR 0xE6150904
-#define CPGWPR 0xE6150900
-
-#define CLK2MHZ(clk) (clk / 1000 / 1000)
void s_init(void)
{
- struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
- struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
-
- /* Watchdog init */
- writel(0xA5A5A500, &rwdt->rwtcsra);
- writel(0xA5A5A500, &swdt->swtcsra);
-
- writel(0x5A5AFFFF, CPGWPR);
- writel(0xA5A50000, CPGWPCR);
}
#define GSX_MSTP112 BIT(12) /* 3DG */
diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c
index fca6eae1fb..a7ca274f34 100644
--- a/board/renesas/ulcb/ulcb.c
+++ b/board/renesas/ulcb/ulcb.c
@@ -26,21 +26,8 @@
DECLARE_GLOBAL_DATA_PTR;
-#define CPGWPCR 0xE6150904
-#define CPGWPR 0xE6150900
-
-#define CLK2MHZ(clk) (clk / 1000 / 1000)
void s_init(void)
{
- struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
- struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
-
- /* Watchdog init */
- writel(0xA5A5A500, &rwdt->rwtcsra);
- writel(0xA5A5A500, &swdt->swtcsra);
-
- writel(0x5A5AFFFF, CPGWPR);
- writel(0xA5A50000, CPGWPCR);
}
#define GSX_MSTP112 BIT(12) /* 3DG */
--
2.18.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [U-Boot] [PATCH 5/9] ARM: rmobile: salvator-x: Remove GSX clock force supply
2018-10-18 18:37 [U-Boot] [PATCH 1/9] ARM: rmobile: Fix CPGWPR Address define and Settings on Gen3 Marek Vasut
` (2 preceding siblings ...)
2018-10-18 18:37 ` [U-Boot] [PATCH 4/9] ARM: rmobile: Remove Watchdog and CPG " Marek Vasut
@ 2018-10-18 18:37 ` Marek Vasut
2018-10-18 18:37 ` [U-Boot] [PATCH 6/9] ARM: rmobile: Tidy up SYSC_PWRx define of 3DG on Gen3 Marek Vasut
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Marek Vasut @ 2018-10-18 18:37 UTC (permalink / raw)
To: u-boot
From: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
GSX clock force supply code is unnecessary at U-Boot,
because GSX clock control is supported at the kernel driver.
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
---
board/renesas/salvator-x/salvator-x.c | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c
index 296aa90a12..726a236af3 100644
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -31,7 +31,6 @@ void s_init(void)
{
}
-#define GSX_MSTP112 BIT(12) /* 3DG */
#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
#define DVFS_MSTP926 BIT(26)
#define HSUSB_MSTP704 BIT(4) /* HSUSB */
@@ -60,20 +59,9 @@ int board_early_init_f(void)
int board_init(void)
{
- u32 cpu_type = rmobile_get_cpu_type();
-
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
- if (cpu_type == RMOBILE_CPU_TYPE_R8A7795) {
- /* GSX: force power and clock supply */
- writel(0x0000001F, SYSC_PWRONCR2);
- while (readl(SYSC_PWRSR2) != 0x000003E0)
- mdelay(20);
-
- mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
- }
-
/* USB1 pull-up */
setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
--
2.18.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [U-Boot] [PATCH 6/9] ARM: rmobile: Tidy up SYSC_PWRx define of 3DG on Gen3
2018-10-18 18:37 [U-Boot] [PATCH 1/9] ARM: rmobile: Fix CPGWPR Address define and Settings on Gen3 Marek Vasut
` (3 preceding siblings ...)
2018-10-18 18:37 ` [U-Boot] [PATCH 5/9] ARM: rmobile: salvator-x: Remove GSX clock force supply Marek Vasut
@ 2018-10-18 18:37 ` Marek Vasut
2018-10-18 18:37 ` [U-Boot] [PATCH 7/9] ARM: rmobile: Enable cache command " Marek Vasut
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Marek Vasut @ 2018-10-18 18:37 UTC (permalink / raw)
To: u-boot
From: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Tidy up unused definition related to power control of 3DG.
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
---
board/renesas/draak/draak.c | 6 ------
board/renesas/salvator-x/salvator-x.c | 6 ------
board/renesas/ulcb/ulcb.c | 6 ------
3 files changed, 18 deletions(-)
diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c
index 71fd5001c4..060343dfe4 100644
--- a/board/renesas/draak/draak.c
+++ b/board/renesas/draak/draak.c
@@ -44,12 +44,6 @@ int board_early_init_f(void)
return 0;
}
-/* SYSC */
-/* R/- 32 Power status register 2(3DG) */
-#define SYSC_PWRSR2 0xE6180100
-/* -/W 32 Power resume control register 2 (3DG) */
-#define SYSC_PWRONCR2 0xE618010C
-
/* HSUSB block registers */
#define HSUSB_REG_LPSTS 0xE6590102
#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c
index 726a236af3..a1a1531663 100644
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -44,12 +44,6 @@ int board_early_init_f(void)
return 0;
}
-/* SYSC */
-/* R/- 32 Power status register 2(3DG) */
-#define SYSC_PWRSR2 0xE6180100
-/* -/W 32 Power resume control register 2 (3DG) */
-#define SYSC_PWRONCR2 0xE618010C
-
/* HSUSB block registers */
#define HSUSB_REG_LPSTS 0xE6590102
#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c
index a7ca274f34..e549a2efac 100644
--- a/board/renesas/ulcb/ulcb.c
+++ b/board/renesas/ulcb/ulcb.c
@@ -44,12 +44,6 @@ int board_early_init_f(void)
return 0;
}
-/* SYSC */
-/* R/- 32 Power status register 2(3DG) */
-#define SYSC_PWRSR2 0xE6180100
-/* -/W 32 Power resume control register 2 (3DG) */
-#define SYSC_PWRONCR2 0xE618010C
-
/* HSUSB block registers */
#define HSUSB_REG_LPSTS 0xE6590102
#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
--
2.18.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [U-Boot] [PATCH 7/9] ARM: rmobile: Enable cache command on Gen3
2018-10-18 18:37 [U-Boot] [PATCH 1/9] ARM: rmobile: Fix CPGWPR Address define and Settings on Gen3 Marek Vasut
` (4 preceding siblings ...)
2018-10-18 18:37 ` [U-Boot] [PATCH 6/9] ARM: rmobile: Tidy up SYSC_PWRx define of 3DG on Gen3 Marek Vasut
@ 2018-10-18 18:37 ` Marek Vasut
2018-10-18 18:37 ` [U-Boot] [PATCH 8/9] ARM: rmobile: Fix module clock controls refer status " Marek Vasut
2018-10-18 18:37 ` [U-Boot] [PATCH 9/9] ARM: dts: rmobile: r8a77990: Add USB2.0(EHCI) DT nodes on Ebisu Marek Vasut
7 siblings, 0 replies; 9+ messages in thread
From: Marek Vasut @ 2018-10-18 18:37 UTC (permalink / raw)
To: u-boot
From: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
This patch enables the cache command, mostly for convenience of testing.
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
---
arch/arm/mach-rmobile/Kconfig | 1 +
configs/r8a7795_salvator-x_defconfig | 1 +
include/configs/draak.h | 1 -
3 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index ac08d6eb12..d82023acf3 100644
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -12,6 +12,7 @@ config RCAR_GEN3
bool "Renesas ARM SoCs R-Car Gen3 (64bit)"
select ARM64
select PHY
+ select CMD_CACHE
endchoice
diff --git a/configs/r8a7795_salvator-x_defconfig b/configs/r8a7795_salvator-x_defconfig
index 40712a44c3..87870fc595 100644
--- a/configs/r8a7795_salvator-x_defconfig
+++ b/configs/r8a7795_salvator-x_defconfig
@@ -21,6 +21,7 @@ CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
diff --git a/include/configs/draak.h b/include/configs/draak.h
index 5d1da21e99..70c4f166a5 100644
--- a/include/configs/draak.h
+++ b/include/configs/draak.h
@@ -33,6 +33,5 @@
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_WRITE_SWAPPED_DATA
-#define CONFIG_CMD_CACHE
#endif /* __DRAAK_H */
--
2.18.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [U-Boot] [PATCH 8/9] ARM: rmobile: Fix module clock controls refer status on Gen3
2018-10-18 18:37 [U-Boot] [PATCH 1/9] ARM: rmobile: Fix CPGWPR Address define and Settings on Gen3 Marek Vasut
` (5 preceding siblings ...)
2018-10-18 18:37 ` [U-Boot] [PATCH 7/9] ARM: rmobile: Enable cache command " Marek Vasut
@ 2018-10-18 18:37 ` Marek Vasut
2018-10-18 18:37 ` [U-Boot] [PATCH 9/9] ARM: dts: rmobile: r8a77990: Add USB2.0(EHCI) DT nodes on Ebisu Marek Vasut
7 siblings, 0 replies; 9+ messages in thread
From: Marek Vasut @ 2018-10-18 18:37 UTC (permalink / raw)
To: u-boot
From: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
When referring to the MSTPSR register, it contains the clock
status of SYS, RT, SECURE, and controlling SMSTPCR using this
value has the problem of being affected by the RT and SECURE
status.This patch changes the reference register to SMSTPCR.
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
---
board/renesas/draak/draak.c | 4 ++--
board/renesas/salvator-x/salvator-x.c | 4 ++--
board/renesas/ulcb/ulcb.c | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c
index 060343dfe4..8f3d3915f7 100644
--- a/board/renesas/draak/draak.c
+++ b/board/renesas/draak/draak.c
@@ -39,7 +39,7 @@ int board_early_init_f(void)
{
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
- mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
+ mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
#endif
return 0;
}
@@ -60,7 +60,7 @@ int board_init(void)
setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
/* Configure the HSUSB block */
- mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
+ mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
/* Choice USB0SEL */
clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c
index a1a1531663..8b15267d7b 100644
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -39,7 +39,7 @@ int board_early_init_f(void)
{
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
- mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
+ mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
#endif
return 0;
}
@@ -60,7 +60,7 @@ int board_init(void)
setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
/* Configure the HSUSB block */
- mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
+ mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
/* Choice USB0SEL */
clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c
index e549a2efac..63550af1f0 100644
--- a/board/renesas/ulcb/ulcb.c
+++ b/board/renesas/ulcb/ulcb.c
@@ -39,7 +39,7 @@ int board_early_init_f(void)
{
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
- mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
+ mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
#endif
return 0;
}
@@ -60,7 +60,7 @@ int board_init(void)
setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
/* Configure the HSUSB block */
- mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
+ mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
/* Choice USB0SEL */
clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
--
2.18.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [U-Boot] [PATCH 9/9] ARM: dts: rmobile: r8a77990: Add USB2.0(EHCI) DT nodes on Ebisu
2018-10-18 18:37 [U-Boot] [PATCH 1/9] ARM: rmobile: Fix CPGWPR Address define and Settings on Gen3 Marek Vasut
` (6 preceding siblings ...)
2018-10-18 18:37 ` [U-Boot] [PATCH 8/9] ARM: rmobile: Fix module clock controls refer status " Marek Vasut
@ 2018-10-18 18:37 ` Marek Vasut
7 siblings, 0 replies; 9+ messages in thread
From: Marek Vasut @ 2018-10-18 18:37 UTC (permalink / raw)
To: u-boot
From: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Add device tree nodes for USB2.0(EHCI) on R-Car E3 Ebisu board.
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
---
arch/arm/dts/r8a77990-ebisu.dts | 16 ++++++++++
arch/arm/dts/r8a77990.dtsi | 38 +++++++++++++++++++++++
include/dt-bindings/power/r8a77990-sysc.h | 20 ++++++++++++
3 files changed, 74 insertions(+)
create mode 100644 include/dt-bindings/power/r8a77990-sysc.h
diff --git a/arch/arm/dts/r8a77990-ebisu.dts b/arch/arm/dts/r8a77990-ebisu.dts
index 8b0d24bd29..5e3c195d4c 100644
--- a/arch/arm/dts/r8a77990-ebisu.dts
+++ b/arch/arm/dts/r8a77990-ebisu.dts
@@ -65,6 +65,10 @@
};
};
+&ehci0 {
+ status = "okay";
+};
+
&extal_clk {
clock-frequency = <48000000>;
};
@@ -101,6 +105,18 @@
function = "sdhi3";
power-source = <1800>;
};
+
+ usb0_pins: usb0 {
+ groups = "usb0";
+ function = "usb0";
+ };
+};
+
+&usb2_phy0 {
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-name = "default";
+
+ status = "okay";
};
&sdhi0 {
diff --git a/arch/arm/dts/r8a77990.dtsi b/arch/arm/dts/r8a77990.dtsi
index 6d2d5e1068..ad20ea14cd 100644
--- a/arch/arm/dts/r8a77990.dtsi
+++ b/arch/arm/dts/r8a77990.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/clock/renesas-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/r8a77990-sysc.h>
/ {
compatible = "renesas,r8a77990";
@@ -165,6 +166,43 @@
resets = <&cpg 906>;
};
+ ohci0: usb at ee080000 {
+ compatible = "generic-ohci";
+ reg = <0 0xee080000 0 0x100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ phys = <&usb2_phy0>;
+ phy-names = "usb";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+ };
+
+ ehci0: usb at ee080100 {
+ compatible = "generic-ehci";
+ reg = <0 0xee080100 0 0x100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ phys = <&usb2_phy0>;
+ phy-names = "usb";
+ companion = <&ohci0>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+ };
+
+ usb2_phy0: usb-phy at ee080200 {
+ compatible = "renesas,usb2-phy-r8a7790",
+ "renesas,rcar-gen3-usb2-phy";
+ reg = <0 0xee080200 0 0x700>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
pfc: pin-controller at e6060000 {
compatible = "renesas,pfc-r8a77990";
reg = <0 0xe6060000 0 0x508>;
diff --git a/include/dt-bindings/power/r8a77990-sysc.h b/include/dt-bindings/power/r8a77990-sysc.h
new file mode 100644
index 0000000000..1409c73a57
--- /dev/null
+++ b/include/dt-bindings/power/r8a77990-sysc.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A77990_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A77990_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A77990_PD_CA53_CPU0 5
+#define R8A77990_PD_CA53_SCU 21
+
+/* Always-on power area */
+#define R8A77990_PD_ALWAYS_ON 32
+
+#endif /* __DT_BINDINGS_POWER_R8A77990_SYSC_H__ */
--
2.18.0
^ permalink raw reply related [flat|nested] 9+ messages in thread