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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Manasi Navare <manasi.d.navare@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
	Harry Wentland <harry.wentland@amd.com>
Subject: Re: [PATCH v6 08/28] drm/dsc: Define Display Stream Compression PPS infoframe
Date: Thu, 1 Nov 2018 18:42:17 +0200	[thread overview]
Message-ID: <20181101164217.GF9144@intel.com> (raw)
In-Reply-To: <20181024222840.25683-9-manasi.d.navare@intel.com>

On Wed, Oct 24, 2018 at 03:28:20PM -0700, Manasi Navare wrote:
> This patch defines a new header file for all the DSC 1.2 structures
> and creates a structure for PPS infoframe which will be used to send
> picture parameter set secondary data packet for display stream compression.
> All the PPS infoframe syntax elements are taken from DSC 1.2 specification
> from VESA.
> 
> v3:
> * Add the SPDX shorthand (Chris Wilson)
> v2:
> * Do not use bitfields in the struct (Jani Nikula)
> 
> Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
> Cc: dri-devel@lists.freedesktop.org
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Harry Wentland <harry.wentland@amd.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Reviewed-by: Harry Wentland <harry.wentland@amd.com>
> ---
>  include/drm/drm_dsc.h | 347 ++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 347 insertions(+)
>  create mode 100644 include/drm/drm_dsc.h
> 
> diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
> new file mode 100644
> index 000000000000..1d8a03983b90
> --- /dev/null
> +++ b/include/drm/drm_dsc.h
> @@ -0,0 +1,347 @@
> +/* SPDX-License-Identifier: MIT
> + * Copyright (C) 2018 Intel Corp.
> + *
> + * Authors:
> + * Manasi Navare <manasi.d.navare@intel.com>
> + */
> +
> +#ifndef DRM_DSC_H_
> +#define DRM_DSC_H_
> +
> +#include <drm/drm_dp_helper.h>
> +
> +/* VESA Display Stream Compression DSC 1.2 constants */
> +#define DSC_NUM_BUF_RANGES	15

DRM_DSC_...  perhasp?

> +
> +/**
> + * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set
> + *
> + * The VESA DSC standard defines picture parameter set (PPS) which display
> + * stream compression encoders must communicate to decoders.
> + * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The fields in
> + * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2.
> + * The PPS fields that span over more than a byte should be stored in Big Endian
> + * format.
> + */
> +struct picture_parameter_set {

Needs a namespace too. Probably best make this struct packed. A
BUILD_BUG_ON() somewhere to verify the size might also be nice.

> +	/**
> +	 * @dsc_version:
> +	 * PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC
> +	 * PPS0[7:4] - dsc_version_major: Contains major version of DSC
> +	 */
> +	u8 dsc_version;
> +	/**
> +	 * @pps_identifier:
> +	 * PPS1[7:0] - Application specific identifier that can be
> +	 * used to differentiate between different PPS tables.
> +	 */
> +	u8 pps_identifier;
> +	/**
> +	 * @pps_reserved:
> +	 * PPS2[7:0]- RESERVED Byte
> +	 */
> +	u8 pps_reserved;
> +	/**
> +	 * @pps_3:
> +	 * PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to
> +	 * generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits,
> +	 * 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits,
> +	 * 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2.
> +	 * PPS3[7:4] - bits_per_component: Bits per component for the original
> +	 * pixels of the encoded picture.
> +	 * 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2)
> +	 * 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also
> +	 * allowed only when dsc_minor_version = 0x2)
> +	 */
> +	u8 pps_3;
> +	/**
> +	 * @pps_4:
> +	 * PPS4[1:0] -These are the most significant 2 bits of
> +	 * compressed BPP bits_per_pixel[9:0] syntax element.
> +	 * PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled
> +	 * PPS4[3] - simple_422: Indicates if decoder drops samples to
> +	 * reconstruct the 4:2:2 picture.
> +	 * PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is
> +	 * active.
> +	 * PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any
> +	 * groups in picture
> +	 * PPS4[7:6] - Reseved bits
> +	 */
> +	u8 pps_4;
> +	/**
> +	 * @bits_per_pixel_low:
> +	 * PPS5[7:0] - This indicates the lower significant 8 bits of
> +	 * the compressed BPP bits_per_pixel[9:0] element.
> +	 */
> +	u8 bits_per_pixel_low;
> +	/**
> +	 * @pic_height:
> +	 * PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows
> +	 * within the raster.
> +	 */
> +	__be16 pic_height;
> +	/**
> +	 * @pic_width:
> +	 * PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within
> +	 * the raster.
> +	 */
> +	__be16 pic_width;
> +	/**
> +	 * @slice_height:
> +	 * PPS10[7:0], PPS11[7:0] - Slice height in units of pixels.
> +	 */
> +	__be16 slice_height;
> +	/**
> +	 * @slice_width:
> +	 * PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels.
> +	 */
> +	__be16 slice_width;
> +	/**
> +	 * @chunk_size:
> +	 * PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks
> +	 * that are used for slice multiplexing.
> +	 */
> +	__be16 chunk_size;
> +	/**
> +	 * @initial_xmit_delay_high:
> +	 * PPS16[1:0] - Most Significant two bits of initial transmission delay.
> +	 * It specifies the number of pixel times that the encoder waits before
> +	 * transmitting data from its rate buffer.
> +	 * PPS16[7:2] - Reserved
> +	 */
> +	u8 initial_xmit_delay_high;
> +	/**
> +	 * @initial_xmit_delay_low:
> +	 * PPS17[7:0] - Least significant 8 bits of initial transmission delay.
> +	 */
> +	u8 initial_xmit_delay_low;
> +	/**
> +	 * @initial_dec_delay:
> +	 *
> +	 * PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number
> +	 * of pixel times that the decoder accumulates data in its rate buffer
> +	 * before starting to decode and output pixels.
> +	 */
> +	__be16 initial_dec_delay;
> +	/**
> +	 * @pps20_reserved:
> +	 *
> +	 * PPS20[7:0] - Reserved
> +	 */
> +	u8 pps20_reserved;
> +	/**
> +	 * @initial_scale_value:
> +	 * PPS21[5:0] - Initial rcXformScale factor used at beginning
> +	 * of a slice.
> +	 * PPS21[7:6] - Reserved
> +	 */
> +	u8 initial_scale_value;
> +	/**
> +	 * @scale_increment_interval:
> +	 * PPS22[7:0], PPS23[7:0] - Number of group times between incrementing
> +	 * the rcXformScale factor at end of a slice.
> +	 */
> +	__be16 scale_increment_interval;
> +	/**
> +	 * @scale_decrement_interval_high:
> +	 * PPS24[3:0] - Higher 4 bits indicating number of group times between
> +	 * decrementing the rcXformScale factor at beginning of a slice.
> +	 * PPS24[7:4] - Reserved
> +	 */
> +	u8 scale_decrement_interval_high;
> +	/**
> +	 * @scale_decrement_interval_low:
> +	 * PPS25[7:0] - Lower 8 bits of scale decrement interval
> +	 */
> +	u8 scale_decrement_interval_low;
> +	/**
> +	 * @pps26_reserved:
> +	 * PPS26[7:0]
> +	 */
> +	u8 pps26_reserved;
> +	/**
> +	 * @first_line_bpg_offset:
> +	 * PPS27[4:0] - Number of additional bits that are allocated
> +	 * for each group on first line of a slice.
> +	 * PPS27[7:5] - Reserved
> +	 */
> +	u8 first_line_bpg_offset;
> +	/**
> +	 * @nfl_bpg_offset:
> +	 * PPS28[7:0], PPS29[7:0] - Number of bits including frac bits
> +	 * deallocated for each group for groups after the first line of slice.
> +	 */
> +	__be16 nfl_bpg_offset;
> +	/**
> +	 * @slice_bpg_offset:
> +	 * PPS30, PPS31[7:0] - Number of bits that are deallocated for each
> +	 * group to enforce the slice constraint.
> +	 */
> +	__be16 slice_bpg_offset;
> +	/**
> +	 * @initial_offset:
> +	 * PPS32,33[7:0] - Initial value for rcXformOffset
> +	 */
> +	__be16 initial_offset;
> +	/**
> +	 * @final_offset:
> +	 * PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset
> +	 */
> +	__be16 final_offset;
> +	/**
> +	 * @flatness_min_qp:
> +	 * PPS36[4:0] - Minimum QP at which flatness is signaled and
> +	 * flatness QP adjustment is made.
> +	 * PPS36[7:5] - Reserved
> +	 */
> +	u8 flatness_min_qp;
> +	/**
> +	 * @flatness_max_qp:
> +	 * PPS37[4:0] - Max QP at which flatness is signalled and
> +	 * the flatness adjustment is made.
> +	 * PPS37[7:5] - Reserved
> +	 */
> +	u8 flatness_max_qp;
> +	/**
> +	 * @rc_model_size:
> +	 * PPS38,39[7:0] - Number of bits within RC Model.
> +	 */
> +	__be16 rc_model_size;
> +	/**
> +	 * @rc_edge_factor:
> +	 * PPS40[3:0] - Ratio of current activity vs, previous
> +	 * activity to determine presence of edge.
> +	 * PPS40[7:4] - Reserved
> +	 */
> +	u8 rc_edge_factor;
> +	/**
> +	 * @rc_quant_incr_limit0:
> +	 * PPS41[4:0] - QP threshold used in short term RC
> +	 * PPS41[7:5] - Reserved
> +	 */
> +	u8 rc_quant_incr_limit0;
> +	/**
> +	 * @rc_quant_incr_limit1:
> +	 * PPS42[4:0] - QP threshold used in short term RC
> +	 * PPS42[7:5] - Reserved
> +	 */
> +	u8 rc_quant_incr_limit1;
> +	/**
> +	 * @rc_tgt_offset:
> +	 * PPS43[3:0] - Lower end of the variability range around the target
> +	 * bits per group that is allowed by short term RC.
> +	 * PPS43[7:4]- Upper end of the variability range around the target
> +	 * bits per group that i allowed by short term rc.
> +	 */
> +	u8 rc_tgt_offset;
> +	/**
> +	 * @rc_buf_thresh:
> +	 * PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for
> +	 * the 15 ranges defined by 14 thresholds.
> +	 */
> +	u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
> +	/**
> +	 * @rc_range_parameters:
> +	 * PPS58[7:0] - PPS87[7:0]
> +	 * Parameters that correspond to each of the 15 ranges.
> +	 */
> +	__be16 rc_range_parameters[DSC_NUM_BUF_RANGES];
> +	/**
> +	 * @native_422_420:
> +	 * PPS88[0] - 0 = Native 4:2:2 not used
> +	 * 1 = Native 4:2:2 used
> +	 * PPS88[1] - 0 = Native 4:2:0 not use
> +	 * 1 = Native 4:2:0 used
> +	 * PPS88[7:2] - Reserved 6 bits
> +	 */
> +	u8 native_422_420;
> +	/**
> +	 * @second_line_bpg_offset:
> +	 * PPS89[4:0] - Additional bits/group budget for the
> +	 * second line of a slice in Native 4:2:0 mode.
> +	 * Set to 0 if DSC minor version is 1 or native420 is 0.
> +	 * PPS89[7:5] - Reserved
> +	 */
> +	u8 second_line_bpg_offset;
> +	/**
> +	 * @nsl_bpg_offset:
> +	 * PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated
> +	 * for each group that is not in the second line of a slice.
> +	 */
> +	__be16 nsl_bpg_offset;
> +	/**
> +	 * @second_line_offset_adj:
> +	 * PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second
> +	 * line in Native 4:2:0 mode.
> +	 */
> +	__be16 second_line_offset_adj;
> +	/**
> +	 * @pps_long_94_reserved:
> +	 * PPS 94, 95, 96, 97 - Reserved
> +	 */
> +	u32 pps_long_94_reserved;
> +	/**
> +	 * @pps_long_98_reserved:
> +	 * PPS 98, 99, 100, 101 - Reserved
> +	 */
> +	u32 pps_long_98_reserved;
> +	/**
> +	 * @pps_long_102_reserved:
> +	 * PPS 102, 103, 104, 105 - Reserved
> +	 */
> +	u32 pps_long_102_reserved;
> +	/**
> +	 * @pps_long_106_reserved:
> +	 * PPS 106, 107, 108, 109 - reserved
> +	 */
> +	u32 pps_long_106_reserved;
> +	/**
> +	 * @pps_long_110_reserved:
> +	 * PPS 110, 111, 112, 113 - reserved
> +	 */
> +	u32 pps_long_110_reserved;
> +	/**
> +	 * @pps_long_114_reserved:
> +	 * PPS 114 - 117 - reserved
> +	 */
> +	u32 pps_long_114_reserved;
> +	/**
> +	 * @pps_long_118_reserved:
> +	 * PPS 118 - 121 - reserved
> +	 */
> +	u32 pps_long_118_reserved;
> +	/**
> +	 * @pps_long_122_reserved:
> +	 * PPS 122- 125 - reserved
> +	 */
> +	u32 pps_long_122_reserved;
> +	/**
> +	 * @pps_short_126_reserved:
> +	 * PPS 126, 127 - reserved
> +	 */
> +	__be16 pps_short_126_reserved;
> +};
> +
> +/**
> + * struct drm_dsc_pps_infoframe - DSC infoframe carrying the Picture Parameter
> + * Set Metadata
> + *
> + * This structure represents the DSC PPS infoframe required to send the Picture
> + * Parameter Set metadata required before enabling VESA Display Stream
> + * Compression. This is based on the DP Secondary Data Packet structure and
> + * comprises of SDP Header as defined in drm_dp_helper.h and PPS payload.
> + *
> + * @pps_header:
> + *

What's with the newline and blank line here? Maybe put the member docs
next to the member itself?

> + * Header for PPS as per DP SDP header format
> + *
> + * @pps_payload:
> + *
> + * PPS payload fields as per DSC specification Table 4-1
> + */
> +struct drm_dsc_pps_infoframe {
> +	struct dp_sdp_header pps_header;
> +	struct picture_parameter_set pps_payload;
> +} __packed;
> +
> +#endif /* _DRM_DSC_H_ */
> -- 
> 2.18.0

-- 
Ville Syrjälä
Intel
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  reply	other threads:[~2018-11-01 16:42 UTC|newest]

Thread overview: 74+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-24 22:28 [PATCH v6 00/28] Display Stream Compression enabling on eDP/DP Manasi Navare
2018-10-24 22:28 ` [PATCH v6 01/28] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming Manasi Navare
2018-10-24 22:28 ` [PATCH v6 02/28] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Manasi Navare
2018-10-24 22:28 ` [PATCH v6 03/28] drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Manasi Navare
2018-10-24 22:28 ` [PATCH v6 04/28] drm/dp: DRM DP helper/macros to get DP sink DSC parameters Manasi Navare
2018-12-19 18:54   ` [Intel-gfx] " Daniel Vetter
2019-01-30 11:06     ` Daniel Vetter
2019-01-30 18:06       ` Sean Paul
2019-01-30 18:27         ` Manasi Navare
2019-01-30 18:26       ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 05/28] drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC Manasi Navare
2018-10-24 22:28 ` [PATCH v6 06/28] drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Manasi Navare
2018-10-24 22:28 ` [PATCH v6 07/28] drm/dp: Define payload size for DP SDP PPS packet Manasi Navare
2018-10-24 22:28 ` [PATCH v6 08/28] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
2018-11-01 16:42   ` Ville Syrjälä [this message]
2018-11-01 16:53     ` Ville Syrjälä
2018-11-01 21:48     ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 09/28] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
2018-10-24 22:28 ` [PATCH v6 10/28] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
2018-10-24 22:28 ` [PATCH v6 11/28] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
2018-11-01 16:46   ` Ville Syrjälä
2018-11-01 23:54     ` Manasi Navare
2018-11-02  0:23       ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 12/28] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-10-30 23:53   ` Manasi Navare
2018-10-31 13:10     ` Ville Syrjälä
2018-10-31 16:05       ` Manasi Navare
2018-10-31 16:13         ` Ville Syrjälä
2018-10-24 22:28 ` [PATCH v6 13/28] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-10-29 20:30   ` Ville Syrjälä
2018-10-29 20:34     ` Ville Syrjälä
2018-10-29 23:08       ` Manasi Navare
2018-10-30 11:46         ` Ville Syrjälä
2018-10-29 21:42     ` Manasi Navare
2018-10-29 22:12     ` Manasi Navare
2018-10-30 11:41       ` Ville Syrjälä
2018-10-24 22:28 ` [PATCH v6 14/28] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-10-24 22:28 ` [PATCH v6 15/28] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare
2018-10-24 22:28 ` [PATCH v6 16/28] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-10-24 22:28 ` [PATCH v6 17/28] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-10-24 22:28 ` [PATCH v6 18/28] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-10-25 14:03   ` Ville Syrjälä
2018-10-25 20:11     ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 19/28] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Manasi Navare
2018-10-24 22:28 ` [PATCH v6 20/28] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-10-24 22:28 ` [PATCH v6 21/28] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-10-25 14:08   ` Ville Syrjälä
2018-10-29 19:24     ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 22/28] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-10-25 14:09   ` Ville Syrjälä
2018-10-25 20:07     ` Manasi Navare
2018-10-30 23:45     ` Manasi Navare
2018-10-31 13:09       ` Ville Syrjälä
2018-10-24 22:28 ` [PATCH v6 23/28] drm/i915/icl: Add Display Stream Splitter control registers Manasi Navare
2018-10-24 22:28 ` [PATCH v6 24/28] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-10-25 14:15   ` Ville Syrjälä
2018-10-25 20:05     ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 25/28] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-10-25 14:16   ` Ville Syrjälä
2018-10-25 19:55     ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 26/28] drm/i915/dsc: Enable and disable appropriate power wells for VDSC Manasi Navare
2018-10-25 14:22   ` Ville Syrjälä
2018-10-25 19:41     ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 27/28] drm/i915/dsc: Add Per connector debugfs node for DSC support/enable Manasi Navare
2018-10-24 22:28   ` Lyude Paul
2018-10-25 20:12     ` Manasi Navare
2018-10-29 20:39   ` Ville Syrjälä
2018-10-29 21:35     ` Manasi Navare
2018-10-30 11:26       ` Ville Syrjälä
2018-10-24 22:28 ` [PATCH v6 28/28] drm/i915/dsc: Force DSC enable if requested by IGT/userspace Manasi Navare
2018-10-24 22:39 ` ✗ Fi.CI.CHECKPATCH: warning for Display Stream Compression enabling on eDP/DP (rev6) Patchwork
2018-10-24 22:50 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-10-24 23:02 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-10-31 23:36 ` [PATCH v6 00/28] Display Stream Compression enabling on eDP/DP Manasi Navare

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