From: Manasi Navare <manasi.d.navare@intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org,
Anusha Srivatsa <anusha.srivatsa@intel.com>,
dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v6 11/28] drm/dsc: Add helpers for DSC picture parameter set infoframes
Date: Thu, 1 Nov 2018 17:23:23 -0700 [thread overview]
Message-ID: <20181102002323.GK3481@intel.com> (raw)
In-Reply-To: <20181101235414.GJ3481@intel.com>
On Thu, Nov 01, 2018 at 04:54:14PM -0700, Manasi Navare wrote:
> Thanks for reviewing this patch. Find some comments inline
>
> On Thu, Nov 01, 2018 at 06:46:28PM +0200, Ville Syrjälä wrote:
> > On Wed, Oct 24, 2018 at 03:28:23PM -0700, Manasi Navare wrote:
> > > According to Display Stream compression spec 1.2, the picture
> > > parameter set metadata is sent from source to sink device
> > > using the DP Secondary data packet. An infoframe is formed
> > > for the PPS SDP header and PPS SDP payload bytes.
> > > This patch adds helpers to fill the PPS SDP header
> > > and PPS SDP payload according to the DSC 1.2 specification.
> > >
> > > v6:
> > > * Use proper sequence points for breaking down the
> > > assignments (Chris Wilson)
> > > * Use SPDX identifier
> > > v5:
> > > Do not use bitfields for DRM structs (Jani N)
> > > v4:
> > > * Use DSC constants for params that dont change across
> > > configurations
> > > v3:
> > > * Add reference to added kernel-docs in Documentation/gpu/drm-kms-helpers.rst
> > > (Daniel Vetter)
> > >
> > > v2:
> > > * Add EXPORT_SYMBOL for the drm functions (Manasi)
> > >
> > > Cc: dri-devel@lists.freedesktop.org
> > > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > Cc: Harry Wentland <harry.wentland@amd.com>
> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > Acked-by: Harry Wentland <harry.wentland@amd.com>
> > > ---
> > > Documentation/gpu/drm-kms-helpers.rst | 12 ++
> > > drivers/gpu/drm/Makefile | 2 +-
> > > drivers/gpu/drm/drm_dsc.c | 223 ++++++++++++++++++++++++++
> > > include/drm/drm_dsc.h | 22 +++
> > > 4 files changed, 258 insertions(+), 1 deletion(-)
> > > create mode 100644 drivers/gpu/drm/drm_dsc.c
> > >
> > > diff --git a/Documentation/gpu/drm-kms-helpers.rst b/Documentation/gpu/drm-kms-helpers.rst
> > > index 4b4dc236ef6f..b422eb8edf16 100644
> > > --- a/Documentation/gpu/drm-kms-helpers.rst
> > > +++ b/Documentation/gpu/drm-kms-helpers.rst
> > > @@ -232,6 +232,18 @@ MIPI DSI Helper Functions Reference
> > > .. kernel-doc:: drivers/gpu/drm/drm_mipi_dsi.c
> > > :export:
> > >
> > > +Display Stream Compression Helper Functions Reference
> > > +=====================================================
> > > +
> > > +.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
> > > + :doc: dsc helpers
> > > +
> > > +.. kernel-doc:: include/drm/drm_dsc.h
> > > + :internal:
> > > +
> > > +.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
> > > + :export:
> > > +
> > > Output Probing Helper Functions Reference
> > > =========================================
> > >
> > > diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
> > > index 576ba985e138..3a3e6fb6d476 100644
> > > --- a/drivers/gpu/drm/Makefile
> > > +++ b/drivers/gpu/drm/Makefile
> > > @@ -32,7 +32,7 @@ drm-$(CONFIG_AGP) += drm_agpsupport.o
> > > drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o
> > > drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
> > >
> > > -drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \
> > > +drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_dsc.o drm_probe_helper.o \
> > > drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \
> > > drm_kms_helper_common.o drm_dp_dual_mode_helper.o \
> > > drm_simple_kms_helper.o drm_modeset_helper.o \
> > > diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
> > > new file mode 100644
> > > index 000000000000..21ae8d015afd
> > > --- /dev/null
> > > +++ b/drivers/gpu/drm/drm_dsc.c
> > > @@ -0,0 +1,223 @@
> > > +// SPDX-License-Identifier: MIT
> > > +/*
> > > + * Copyright © 2018 Intel Corp
> > > + *
> > > + * Author:
> > > + * Manasi Navare <manasi.d.navare@intel.com>
> > > + */
> > > +
> > > +#include <linux/kernel.h>
> > > +#include <linux/module.h>
> > > +#include <linux/init.h>
> > > +#include <linux/errno.h>
> > > +#include <drm/drm_dp_helper.h>
> > > +#include <drm/drm_dsc.h>
> > > +
> > > +/**
> > > + * DOC: dsc helpers
> > > + *
> > > + * These functions contain some common logic and helpers to deal with VESA
> > > + * Display Stream Compression standard required for DSC on Display Port/eDP or
> > > + * MIPI display interfaces.
> > > + */
> > > +
> > > +/**
> > > + * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
> > > + * for DisplayPort as per the DP 1.4 spec.
> > > + * @pps_sdp: Secondary data packet for DSC Picture Parameter Set
> > > + */
> > > +void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp)
> > > +{
> > > + memset(&pps_sdp->pps_header, 0, sizeof(pps_sdp->pps_header));
> > > +
> > > + pps_sdp->pps_header.HB1 = DP_SDP_PPS;
> > > + pps_sdp->pps_header.HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;
> > > +}
> > > +EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
> > > +
> > > +/**
> > > + * drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe
> > > + * using the DSC configuration parameters in the order expected
> > > + * by the DSC Display Sink device. For the DSC, the sink device
> > > + * expects the PPS payload in the big endian format for the fields
> > > + * that span more than 1 byte.
> > > + *
> > > + * @pps_sdp:
> > > + * Secondary data packet for DSC Picture Parameter Set
> > > + * @dsc_cfg:
> > > + * DSC Configuration data filled by driver
> > > + */
> > > +void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
> > > + struct drm_dsc_config *dsc_cfg)
> > > +{
> > > + u8 i = 0;
> >
> > int i;
>
> Ok will do,
>
> >
> > > +
> > > + memset(&pps_sdp->pps_payload, 0, sizeof(pps_sdp->pps_payload));
> > > +
> > > + /* PPS 0 */
> > > + pps_sdp->pps_payload.dsc_version =
> > > + dsc_cfg->dsc_version_minor |
> > > + dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
> > > +
> > > + /* PPS 1, 2 is 0 */
> > > +
> > > + /* PPS 3 */
> > > + pps_sdp->pps_payload.pps_3 =
> > > + dsc_cfg->line_buf_depth |
> > > + dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT;
> > > +
> > > + /* PPS 4 */
> > > + pps_sdp->pps_payload.pps_4 =
> > > + (u8)((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >>
> > > + DSC_PPS_MSB_SHIFT) |
> > > + (u8)dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
> > > + (u8)dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT |
> > > + (u8)dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
> > > + (u8)dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
> >
> > What's with all the (u8) casts?
>
> Since we are assigning to u8 value we dont need type cast, will remove it.
>
> >
> > > +
> > > + /* PPS 5 */
> > > + pps_sdp->pps_payload.bits_per_pixel_low =
> > > + (u8)(dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK);
> > > +
> > > + /*
> > > + * The DSC panel expects the PPS packet to have big endian format
> > > + * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert
> > > + * to big endian format. If format is little endian, it will swap
> > > + * bytes to convert to Big endian else keep it unchanged.
> > > + */
> > > +
> > > + /* PPS 6, 7 */
> > > + pps_sdp->pps_payload.pic_height = cpu_to_be16(dsc_cfg->pic_height);
> > > +
> > > + /* PPS 8, 9 */
> > > + pps_sdp->pps_payload.pic_width = cpu_to_be16(dsc_cfg->pic_width);
> > > +
> > > + /* PPS 10, 11 */
> > > + pps_sdp->pps_payload.slice_height = cpu_to_be16(dsc_cfg->slice_height);
> > > +
> > > + /* PPS 12, 13 */
> > > + pps_sdp->pps_payload.slice_width = cpu_to_be16(dsc_cfg->slice_width);
> > > +
> > > + /* PPS 14, 15 */
> > > + pps_sdp->pps_payload.chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);
> > > +
> > > + /* PPS 16 */
> > > + pps_sdp->pps_payload.initial_xmit_delay_high =
> > > + (u8)((dsc_cfg->initial_xmit_delay &
> > > + DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >>
> > > + DSC_PPS_MSB_SHIFT);
> > > +
> > > + /* PPS 17 */
> > > + pps_sdp->pps_payload.initial_xmit_delay_low =
> > > + (u8)(dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK);
> > > +
> > > + /* PPS 18, 19 */
> > > + pps_sdp->pps_payload.initial_dec_delay =
> > > + cpu_to_be16(dsc_cfg->initial_dec_delay);
> > > +
> > > + /* PPS 20 is 0 */
> > > +
> > > + /* PPS 21 */
> > > + pps_sdp->pps_payload.initial_scale_value =
> > > + (u8)dsc_cfg->initial_scale_value;
> > > +
> > > + /* PPS 22, 23 */
> > > + pps_sdp->pps_payload.scale_increment_interval =
> > > + cpu_to_be16(dsc_cfg->scale_increment_interval);
> > > +
> > > + /* PPS 24 */
> > > + pps_sdp->pps_payload.scale_decrement_interval_high =
> > > + (u8)((dsc_cfg->scale_decrement_interval &
> > > + DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>
> > > + DSC_PPS_MSB_SHIFT);
> > > +
> > > + /* PPS 25 */
> > > + pps_sdp->pps_payload.scale_decrement_interval_low =
> > > + (u8)(dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK);
> > > +
> > > + /* PPS 26[7:0], PPS 27[7:5] RESERVED */
> > > +
> > > + /* PPS 27 */
> > > + pps_sdp->pps_payload.first_line_bpg_offset =
> > > + (u8)dsc_cfg->first_line_bpg_offset;
> > > +
> > > + /* PPS 28, 29 */
> > > + pps_sdp->pps_payload.nfl_bpg_offset =
> > > + cpu_to_be16(dsc_cfg->nfl_bpg_offset);
> > > +
> > > + /* PPS 30, 31 */
> > > + pps_sdp->pps_payload.slice_bpg_offset =
> > > + cpu_to_be16(dsc_cfg->slice_bpg_offset);
> > > +
> > > + /* PPS 32, 33 */
> > > + pps_sdp->pps_payload.initial_offset =
> > > + cpu_to_be16(dsc_cfg->initial_offset);
> > > +
> > > + /* PPS 34, 35 */
> > > + pps_sdp->pps_payload.final_offset = cpu_to_be16(dsc_cfg->final_offset);
> > > +
> > > + /* PPS 36 */
> > > + pps_sdp->pps_payload.flatness_min_qp = (u8)dsc_cfg->flatness_min_qp;
> > > +
> > > + /* PPS 37 */
> > > + pps_sdp->pps_payload.flatness_max_qp = (u8)dsc_cfg->flatness_max_qp;
> > > +
> > > + /* PPS 38, 39 */
> > > + pps_sdp->pps_payload.rc_model_size =
> > > + cpu_to_be16((u16)DSC_RC_MODEL_SIZE_CONST);
> > > +
> > > + /* PPS 40 */
> > > + pps_sdp->pps_payload.rc_edge_factor = (u8)DSC_RC_EDGE_FACTOR_CONST;
> > > +
> > > + /* PPS 41 */
> > > + pps_sdp->pps_payload.rc_quant_incr_limit0 =
> > > + (u8)dsc_cfg->rc_quant_incr_limit0;
> > > +
> > > + /* PPS 42 */
> > > + pps_sdp->pps_payload.rc_quant_incr_limit1 =
> > > + (u8)dsc_cfg->rc_quant_incr_limit1;
> > > +
> > > + /* PPS 43 */
> > > + pps_sdp->pps_payload.rc_tgt_offset = (u8)DSC_RC_TGT_OFFSET_LO_CONST |
> > > + (u8)DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT;
> > > +
> > > + /* PPS 44 - 57 */
> > > + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
> >
> > Is the -1 correct? The loop below doesn't have it.
Forgot to address this. So this -1 is correct since there are only 14 RC_Buf_thresh values
as per the DSC spec Table 4-2 so it is 0 - 13.
DSC_NUM_BUF_RANGES is defined as 15
while rc_range_parameters there are 15 values so there is no -1 in below loop.
Manasi
> >
> > > + pps_sdp->pps_payload.rc_buf_thresh[i] =
> > > + dsc_cfg->rc_buf_thresh[i];
> > > +
> > > + /* PPS 58 - 87 */
> > > + /*
> > > + * For DSC sink programming the RC Range parameter fields
> > > + * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0]
> > > + */
> > > + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
> > > + pps_sdp->pps_payload.rc_range_parameters[i] =
> > > + (u16)((dsc_cfg->rc_range_params[i].range_min_qp <<
> > > + DSC_PPS_RC_RANGE_MINQP_SHIFT) |
> > > + (dsc_cfg->rc_range_params[i].range_max_qp <<
> > > + DSC_PPS_RC_RANGE_MAXQP_SHIFT) |
> > > + (dsc_cfg->rc_range_params[i].range_bpg_offset));
> > > + pps_sdp->pps_payload.rc_range_parameters[i] =
> > > + cpu_to_be16(pps_sdp->pps_payload.rc_range_parameters[i]);
> > > + }
> > > +
> > > + /* PPS 88 */
> > > + pps_sdp->pps_payload.native_422_420 = (u8)dsc_cfg->native_422 |
> > > + (u8)dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT;
> > > +
> > > + /* PPS 89 */
> > > + pps_sdp->pps_payload.second_line_bpg_offset =
> > > + (u8)dsc_cfg->second_line_bpg_offset;
> > > +
> > > + /* PPS 90, 91 */
> > > + pps_sdp->pps_payload.nsl_bpg_offset =
> > > + cpu_to_be16(dsc_cfg->nsl_bpg_offset);
> > > +
> > > + /* PPS 92, 93 */
> > > + pps_sdp->pps_payload.second_line_offset_adj =
> > > + cpu_to_be16(dsc_cfg->second_line_offset_adj);
> > > +
> > > + /* PPS 94 - 127 are O */
> > > +}
> > > +EXPORT_SYMBOL(drm_dsc_pps_infoframe_pack);
> > > diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
> > > index 986f962f38d4..0e5e3368d645 100644
> > > --- a/include/drm/drm_dsc.h
> > > +++ b/include/drm/drm_dsc.h
> > > @@ -8,6 +8,7 @@
> > > #ifndef DRM_DSC_H_
> > > #define DRM_DSC_H_
> > >
> > > +#include <linux/byteorder/generic.h>
> >
> > This header doesn't need that AFAICS.
> >
>
> I will move that to drm_dsc.c
>
> Manasi
>
> > > #include <drm/drm_dp_helper.h>
> > >
> > > /* VESA Display Stream Compression DSC 1.2 constants */
> > > @@ -24,6 +25,23 @@
> > > #define DSC_RC_TGT_OFFSET_HI_CONST 3
> > > #define DSC_RC_TGT_OFFSET_LO_CONST 3
> > >
> > > +/* DSC PPS constants and macros */
> > > +#define DSC_PPS_VERSION_MAJOR_SHIFT 4
> > > +#define DSC_PPS_BPC_SHIFT 4
> > > +#define DSC_PPS_MSB_SHIFT 8
> > > +#define DSC_PPS_LSB_MASK (0xFF << 0)
> > > +#define DSC_PPS_BPP_HIGH_MASK (0x3 << 8)
> > > +#define DSC_PPS_VBR_EN_SHIFT 2
> > > +#define DSC_PPS_SIMPLE422_SHIFT 3
> > > +#define DSC_PPS_CONVERT_RGB_SHIFT 4
> > > +#define DSC_PPS_BLOCK_PRED_EN_SHIFT 5
> > > +#define DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK (0x3 << 8)
> > > +#define DSC_PPS_SCALE_DEC_INT_HIGH_MASK (0xF << 8)
> > > +#define DSC_PPS_RC_TGT_OFFSET_HI_SHIFT 4
> > > +#define DSC_PPS_RC_RANGE_MINQP_SHIFT 11
> > > +#define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6
> > > +#define DSC_PPS_NATIVE_420_SHIFT 1
> > > +
> > > /* Configuration for a single Rate Control model range */
> > > struct dsc_rc_range_parameters {
> > > /* Min Quantization Parameters allowed for this range */
> > > @@ -463,4 +481,8 @@ struct drm_dsc_pps_infoframe {
> > > struct picture_parameter_set pps_payload;
> > > } __packed;
> > >
> > > +void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp);
> > > +void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
> > > + struct drm_dsc_config *dsc_cfg);
> > > +
> > > #endif /* _DRM_DSC_H_ */
> > > --
> > > 2.18.0
> >
> > --
> > Ville Syrjälä
> > Intel
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
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next prev parent reply other threads:[~2018-11-02 0:23 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-24 22:28 [PATCH v6 00/28] Display Stream Compression enabling on eDP/DP Manasi Navare
2018-10-24 22:28 ` [PATCH v6 01/28] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming Manasi Navare
2018-10-24 22:28 ` [PATCH v6 02/28] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Manasi Navare
2018-10-24 22:28 ` [PATCH v6 03/28] drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Manasi Navare
2018-10-24 22:28 ` [PATCH v6 04/28] drm/dp: DRM DP helper/macros to get DP sink DSC parameters Manasi Navare
2018-12-19 18:54 ` [Intel-gfx] " Daniel Vetter
2019-01-30 11:06 ` Daniel Vetter
2019-01-30 18:06 ` Sean Paul
2019-01-30 18:27 ` Manasi Navare
2019-01-30 18:26 ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 05/28] drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC Manasi Navare
2018-10-24 22:28 ` [PATCH v6 06/28] drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Manasi Navare
2018-10-24 22:28 ` [PATCH v6 07/28] drm/dp: Define payload size for DP SDP PPS packet Manasi Navare
2018-10-24 22:28 ` [PATCH v6 08/28] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
2018-11-01 16:42 ` Ville Syrjälä
2018-11-01 16:53 ` Ville Syrjälä
2018-11-01 21:48 ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 09/28] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
2018-10-24 22:28 ` [PATCH v6 10/28] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
2018-10-24 22:28 ` [PATCH v6 11/28] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
2018-11-01 16:46 ` Ville Syrjälä
2018-11-01 23:54 ` Manasi Navare
2018-11-02 0:23 ` Manasi Navare [this message]
2018-10-24 22:28 ` [PATCH v6 12/28] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-10-30 23:53 ` Manasi Navare
2018-10-31 13:10 ` Ville Syrjälä
2018-10-31 16:05 ` Manasi Navare
2018-10-31 16:13 ` Ville Syrjälä
2018-10-24 22:28 ` [PATCH v6 13/28] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-10-29 20:30 ` Ville Syrjälä
2018-10-29 20:34 ` Ville Syrjälä
2018-10-29 23:08 ` Manasi Navare
2018-10-30 11:46 ` Ville Syrjälä
2018-10-29 21:42 ` Manasi Navare
2018-10-29 22:12 ` Manasi Navare
2018-10-30 11:41 ` Ville Syrjälä
2018-10-24 22:28 ` [PATCH v6 14/28] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-10-24 22:28 ` [PATCH v6 15/28] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare
2018-10-24 22:28 ` [PATCH v6 16/28] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-10-24 22:28 ` [PATCH v6 17/28] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-10-24 22:28 ` [PATCH v6 18/28] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-10-25 14:03 ` Ville Syrjälä
2018-10-25 20:11 ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 19/28] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Manasi Navare
2018-10-24 22:28 ` [PATCH v6 20/28] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-10-24 22:28 ` [PATCH v6 21/28] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-10-25 14:08 ` Ville Syrjälä
2018-10-29 19:24 ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 22/28] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-10-25 14:09 ` Ville Syrjälä
2018-10-25 20:07 ` Manasi Navare
2018-10-30 23:45 ` Manasi Navare
2018-10-31 13:09 ` Ville Syrjälä
2018-10-24 22:28 ` [PATCH v6 23/28] drm/i915/icl: Add Display Stream Splitter control registers Manasi Navare
2018-10-24 22:28 ` [PATCH v6 24/28] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-10-25 14:15 ` Ville Syrjälä
2018-10-25 20:05 ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 25/28] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-10-25 14:16 ` Ville Syrjälä
2018-10-25 19:55 ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 26/28] drm/i915/dsc: Enable and disable appropriate power wells for VDSC Manasi Navare
2018-10-25 14:22 ` Ville Syrjälä
2018-10-25 19:41 ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 27/28] drm/i915/dsc: Add Per connector debugfs node for DSC support/enable Manasi Navare
2018-10-24 22:28 ` Lyude Paul
2018-10-25 20:12 ` Manasi Navare
2018-10-29 20:39 ` Ville Syrjälä
2018-10-29 21:35 ` Manasi Navare
2018-10-30 11:26 ` Ville Syrjälä
2018-10-24 22:28 ` [PATCH v6 28/28] drm/i915/dsc: Force DSC enable if requested by IGT/userspace Manasi Navare
2018-10-24 22:39 ` ✗ Fi.CI.CHECKPATCH: warning for Display Stream Compression enabling on eDP/DP (rev6) Patchwork
2018-10-24 22:50 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-10-24 23:02 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-10-31 23:36 ` [PATCH v6 00/28] Display Stream Compression enabling on eDP/DP Manasi Navare
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