[PATCH v7 00/19] DSC enabling remaining patches

[PATCH v7 00/19] DSC enabling remaining patches

[Manasi Navare]

This patch series addresses review comments on previous DSC series:

https://patchwork.freedesktop.org/series/47514/

Gaurav K Singh (3):
  drm/i915/dsc: Define & Compute VESA DSC params
  drm/i915/dsc: Compute Rate Control parameters for DSC
  drm/i915/dp: Enable/Disable DSC in DP Sink

Manasi Navare (15):
  drm/dsc: Define Display Stream Compression PPS infoframe
  drm/dsc: Define VESA Display Stream Compression Capabilities
  drm/dsc: Add helpers for DSC picture parameter set infoframes
  drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
  drm/i915/dp: Compute DSC pipe config in atomic check
  drm/i915/dp: Do not enable PSR2 if DSC is enabled
  drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
  drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
  drm/i915/dp: Configure i915 Picture parameter Set registers during DSC
    enabling
  drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
  drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
  drm/i915/dp: Configure Display stream splitter registers during DSC
    enable
  drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
  drm/i915/dsc: Enable and disable appropriate power wells for VDSC
  drm/i915/dsc: Add Per connector debugfs node for DSC support/enable

Srivatsa, Anusha (1):
  drm/dsc: Define Rate Control values that do not change over
    configurations

 Documentation/gpu/drm-kms-helpers.rst   |   12 +
 drivers/gpu/drm/Makefile                |    2 +-
 drivers/gpu/drm/drm_dsc.c               |  228 +++++
 drivers/gpu/drm/i915/Makefile           |    3 +-
 drivers/gpu/drm/i915/i915_debugfs.c     |   71 +-
 drivers/gpu/drm/i915/i915_drv.h         |    4 +
 drivers/gpu/drm/i915/i915_reg.h         |    1 +
 drivers/gpu/drm/i915/intel_ddi.c        |    8 +-
 drivers/gpu/drm/i915/intel_display.c    |   28 +-
 drivers/gpu/drm/i915/intel_display.h    |    4 +-
 drivers/gpu/drm/i915/intel_dp.c         |  196 +++-
 drivers/gpu/drm/i915/intel_dp_mst.c     |    2 +-
 drivers/gpu/drm/i915/intel_drv.h        |   21 +
 drivers/gpu/drm/i915/intel_hdmi.c       |   21 +-
 drivers/gpu/drm/i915/intel_psr.c        |   16 +-
 drivers/gpu/drm/i915/intel_runtime_pm.c |    4 +-
 drivers/gpu/drm/i915/intel_vdsc.c       | 1100 +++++++++++++++++++++++
 include/drm/drm_dp_helper.h             |    3 +
 include/drm/drm_dsc.h                   |  485 ++++++++++
 19 files changed, 2169 insertions(+), 40 deletions(-)
 create mode 100644 drivers/gpu/drm/drm_dsc.c
 create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c
 create mode 100644 include/drm/drm_dsc.h

-- 
2.18.0

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[PATCH v7 01/19] drm/dsc: Define Display Stream Compression PPS infoframe

[Manasi Navare]

This patch defines a new header file for all the DSC 1.2 structures
and creates a structure for PPS infoframe which will be used to send
picture parameter set secondary data packet for display stream compression.
All the PPS infoframe syntax elements are taken from DSC 1.2 specification
from VESA.

v4:
* Remove redundant blankline in doc (Ville)
* use drm_dsc namespace for all structs (Ville)
* Use packed struct (Ville)
v3:
* Add the SPDX shorthand (Chris Wilson)
v2:
* Do not use bitfields in the struct (Jani Nikula)

Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
---
 include/drm/drm_dsc.h | 342 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 342 insertions(+)
 create mode 100644 include/drm/drm_dsc.h

diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
new file mode 100644
index 000000000000..78db4f61d01c
--- /dev/null
+++ b/include/drm/drm_dsc.h
@@ -0,0 +1,342 @@
+/* SPDX-License-Identifier: MIT
+ * Copyright (C) 2018 Intel Corp.
+ *
+ * Authors:
+ * Manasi Navare <manasi.d.navare@intel.com>
+ */
+
+#ifndef DRM_DSC_H_
+#define DRM_DSC_H_
+
+#include <drm/drm_dp_helper.h>
+
+/* VESA Display Stream Compression DSC 1.2 constants */
+#define DSC_NUM_BUF_RANGES	15
+
+/**
+ * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set
+ *
+ * The VESA DSC standard defines picture parameter set (PPS) which display
+ * stream compression encoders must communicate to decoders.
+ * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The fields in
+ * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2.
+ * The PPS fields that span over more than a byte should be stored in Big Endian
+ * format.
+ */
+struct drm_dsc_picture_parameter_set {
+	/**
+	 * @dsc_version:
+	 * PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC
+	 * PPS0[7:4] - dsc_version_major: Contains major version of DSC
+	 */
+	u8 dsc_version;
+	/**
+	 * @pps_identifier:
+	 * PPS1[7:0] - Application specific identifier that can be
+	 * used to differentiate between different PPS tables.
+	 */
+	u8 pps_identifier;
+	/**
+	 * @pps_reserved:
+	 * PPS2[7:0]- RESERVED Byte
+	 */
+	u8 pps_reserved;
+	/**
+	 * @pps_3:
+	 * PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to
+	 * generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits,
+	 * 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits,
+	 * 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2.
+	 * PPS3[7:4] - bits_per_component: Bits per component for the original
+	 * pixels of the encoded picture.
+	 * 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2)
+	 * 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also
+	 * allowed only when dsc_minor_version = 0x2)
+	 */
+	u8 pps_3;
+	/**
+	 * @pps_4:
+	 * PPS4[1:0] -These are the most significant 2 bits of
+	 * compressed BPP bits_per_pixel[9:0] syntax element.
+	 * PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled
+	 * PPS4[3] - simple_422: Indicates if decoder drops samples to
+	 * reconstruct the 4:2:2 picture.
+	 * PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is
+	 * active.
+	 * PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any
+	 * groups in picture
+	 * PPS4[7:6] - Reseved bits
+	 */
+	u8 pps_4;
+	/**
+	 * @bits_per_pixel_low:
+	 * PPS5[7:0] - This indicates the lower significant 8 bits of
+	 * the compressed BPP bits_per_pixel[9:0] element.
+	 */
+	u8 bits_per_pixel_low;
+	/**
+	 * @pic_height:
+	 * PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows
+	 * within the raster.
+	 */
+	__be16 pic_height;
+	/**
+	 * @pic_width:
+	 * PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within
+	 * the raster.
+	 */
+	__be16 pic_width;
+	/**
+	 * @slice_height:
+	 * PPS10[7:0], PPS11[7:0] - Slice height in units of pixels.
+	 */
+	__be16 slice_height;
+	/**
+	 * @slice_width:
+	 * PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels.
+	 */
+	__be16 slice_width;
+	/**
+	 * @chunk_size:
+	 * PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks
+	 * that are used for slice multiplexing.
+	 */
+	__be16 chunk_size;
+	/**
+	 * @initial_xmit_delay_high:
+	 * PPS16[1:0] - Most Significant two bits of initial transmission delay.
+	 * It specifies the number of pixel times that the encoder waits before
+	 * transmitting data from its rate buffer.
+	 * PPS16[7:2] - Reserved
+	 */
+	u8 initial_xmit_delay_high;
+	/**
+	 * @initial_xmit_delay_low:
+	 * PPS17[7:0] - Least significant 8 bits of initial transmission delay.
+	 */
+	u8 initial_xmit_delay_low;
+	/**
+	 * @initial_dec_delay:
+	 *
+	 * PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number
+	 * of pixel times that the decoder accumulates data in its rate buffer
+	 * before starting to decode and output pixels.
+	 */
+	__be16 initial_dec_delay;
+	/**
+	 * @pps20_reserved:
+	 *
+	 * PPS20[7:0] - Reserved
+	 */
+	u8 pps20_reserved;
+	/**
+	 * @initial_scale_value:
+	 * PPS21[5:0] - Initial rcXformScale factor used at beginning
+	 * of a slice.
+	 * PPS21[7:6] - Reserved
+	 */
+	u8 initial_scale_value;
+	/**
+	 * @scale_increment_interval:
+	 * PPS22[7:0], PPS23[7:0] - Number of group times between incrementing
+	 * the rcXformScale factor at end of a slice.
+	 */
+	__be16 scale_increment_interval;
+	/**
+	 * @scale_decrement_interval_high:
+	 * PPS24[3:0] - Higher 4 bits indicating number of group times between
+	 * decrementing the rcXformScale factor at beginning of a slice.
+	 * PPS24[7:4] - Reserved
+	 */
+	u8 scale_decrement_interval_high;
+	/**
+	 * @scale_decrement_interval_low:
+	 * PPS25[7:0] - Lower 8 bits of scale decrement interval
+	 */
+	u8 scale_decrement_interval_low;
+	/**
+	 * @pps26_reserved:
+	 * PPS26[7:0]
+	 */
+	u8 pps26_reserved;
+	/**
+	 * @first_line_bpg_offset:
+	 * PPS27[4:0] - Number of additional bits that are allocated
+	 * for each group on first line of a slice.
+	 * PPS27[7:5] - Reserved
+	 */
+	u8 first_line_bpg_offset;
+	/**
+	 * @nfl_bpg_offset:
+	 * PPS28[7:0], PPS29[7:0] - Number of bits including frac bits
+	 * deallocated for each group for groups after the first line of slice.
+	 */
+	__be16 nfl_bpg_offset;
+	/**
+	 * @slice_bpg_offset:
+	 * PPS30, PPS31[7:0] - Number of bits that are deallocated for each
+	 * group to enforce the slice constraint.
+	 */
+	__be16 slice_bpg_offset;
+	/**
+	 * @initial_offset:
+	 * PPS32,33[7:0] - Initial value for rcXformOffset
+	 */
+	__be16 initial_offset;
+	/**
+	 * @final_offset:
+	 * PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset
+	 */
+	__be16 final_offset;
+	/**
+	 * @flatness_min_qp:
+	 * PPS36[4:0] - Minimum QP at which flatness is signaled and
+	 * flatness QP adjustment is made.
+	 * PPS36[7:5] - Reserved
+	 */
+	u8 flatness_min_qp;
+	/**
+	 * @flatness_max_qp:
+	 * PPS37[4:0] - Max QP at which flatness is signalled and
+	 * the flatness adjustment is made.
+	 * PPS37[7:5] - Reserved
+	 */
+	u8 flatness_max_qp;
+	/**
+	 * @rc_model_size:
+	 * PPS38,39[7:0] - Number of bits within RC Model.
+	 */
+	__be16 rc_model_size;
+	/**
+	 * @rc_edge_factor:
+	 * PPS40[3:0] - Ratio of current activity vs, previous
+	 * activity to determine presence of edge.
+	 * PPS40[7:4] - Reserved
+	 */
+	u8 rc_edge_factor;
+	/**
+	 * @rc_quant_incr_limit0:
+	 * PPS41[4:0] - QP threshold used in short term RC
+	 * PPS41[7:5] - Reserved
+	 */
+	u8 rc_quant_incr_limit0;
+	/**
+	 * @rc_quant_incr_limit1:
+	 * PPS42[4:0] - QP threshold used in short term RC
+	 * PPS42[7:5] - Reserved
+	 */
+	u8 rc_quant_incr_limit1;
+	/**
+	 * @rc_tgt_offset:
+	 * PPS43[3:0] - Lower end of the variability range around the target
+	 * bits per group that is allowed by short term RC.
+	 * PPS43[7:4]- Upper end of the variability range around the target
+	 * bits per group that i allowed by short term rc.
+	 */
+	u8 rc_tgt_offset;
+	/**
+	 * @rc_buf_thresh:
+	 * PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for
+	 * the 15 ranges defined by 14 thresholds.
+	 */
+	u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
+	/**
+	 * @rc_range_parameters:
+	 * PPS58[7:0] - PPS87[7:0]
+	 * Parameters that correspond to each of the 15 ranges.
+	 */
+	__be16 rc_range_parameters[DSC_NUM_BUF_RANGES];
+	/**
+	 * @native_422_420:
+	 * PPS88[0] - 0 = Native 4:2:2 not used
+	 * 1 = Native 4:2:2 used
+	 * PPS88[1] - 0 = Native 4:2:0 not use
+	 * 1 = Native 4:2:0 used
+	 * PPS88[7:2] - Reserved 6 bits
+	 */
+	u8 native_422_420;
+	/**
+	 * @second_line_bpg_offset:
+	 * PPS89[4:0] - Additional bits/group budget for the
+	 * second line of a slice in Native 4:2:0 mode.
+	 * Set to 0 if DSC minor version is 1 or native420 is 0.
+	 * PPS89[7:5] - Reserved
+	 */
+	u8 second_line_bpg_offset;
+	/**
+	 * @nsl_bpg_offset:
+	 * PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated
+	 * for each group that is not in the second line of a slice.
+	 */
+	__be16 nsl_bpg_offset;
+	/**
+	 * @second_line_offset_adj:
+	 * PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second
+	 * line in Native 4:2:0 mode.
+	 */
+	__be16 second_line_offset_adj;
+	/**
+	 * @pps_long_94_reserved:
+	 * PPS 94, 95, 96, 97 - Reserved
+	 */
+	u32 pps_long_94_reserved;
+	/**
+	 * @pps_long_98_reserved:
+	 * PPS 98, 99, 100, 101 - Reserved
+	 */
+	u32 pps_long_98_reserved;
+	/**
+	 * @pps_long_102_reserved:
+	 * PPS 102, 103, 104, 105 - Reserved
+	 */
+	u32 pps_long_102_reserved;
+	/**
+	 * @pps_long_106_reserved:
+	 * PPS 106, 107, 108, 109 - reserved
+	 */
+	u32 pps_long_106_reserved;
+	/**
+	 * @pps_long_110_reserved:
+	 * PPS 110, 111, 112, 113 - reserved
+	 */
+	u32 pps_long_110_reserved;
+	/**
+	 * @pps_long_114_reserved:
+	 * PPS 114 - 117 - reserved
+	 */
+	u32 pps_long_114_reserved;
+	/**
+	 * @pps_long_118_reserved:
+	 * PPS 118 - 121 - reserved
+	 */
+	u32 pps_long_118_reserved;
+	/**
+	 * @pps_long_122_reserved:
+	 * PPS 122- 125 - reserved
+	 */
+	u32 pps_long_122_reserved;
+	/**
+	 * @pps_short_126_reserved:
+	 * PPS 126, 127 - reserved
+	 */
+	__be16 pps_short_126_reserved;
+} __packed;
+
+/**
+ * struct drm_dsc_pps_infoframe - DSC infoframe carrying the Picture Parameter
+ * Set Metadata
+ *
+ * This structure represents the DSC PPS infoframe required to send the Picture
+ * Parameter Set metadata required before enabling VESA Display Stream
+ * Compression. This is based on the DP Secondary Data Packet structure and
+ * comprises of SDP Header as defined in drm_dp_helper.h and PPS payload.
+ *
+ * @pps_header: Header for PPS as per DP SDP header format
+ * @pps_payload: PPS payload fields as per DSC specification Table 4-1
+ */
+struct drm_dsc_pps_infoframe {
+	struct dp_sdp_header pps_header;
+	struct drm_dsc_picture_parameter_set pps_payload;
+} __packed;
+
+#endif /* _DRM_DSC_H_ */
-- 
2.18.0

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[PATCH v7 02/19] drm/dsc: Define VESA Display Stream Compression Capabilities

[Manasi Navare]

This defines all the DSC parameters as per the VESA DSC spec
that will be required for DSC encoder/decoder

v6: (From Manasi)
* Add a bit mask for RANGE_BPG_OFFSET for 6 bits(Manasi)
v5 (From Manasi)
* Add the RC constants as per the spec
v4 (From Manasi)
* Add the DSC_MUX_WORD_SIZE constants (Manasi)

v3 (From Manasi)
* Remove the duplicate define (Suggested By:Harry Wentland)

v2: Define this struct in DRM (From Manasi)
* Changed the data types to u8/u16 instead of unsigned longs (Manasi)
* Remove driver specific fields (Manasi)
* Move this struct definition to DRM (Manasi)
* Define DSC 1.2 parameters (Manasi)
* Use DSC_NUM_BUF_RANGES (Manasi)
* Call it drm_dsc_config (Manasi)

Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Co-developed-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 include/drm/drm_dsc.h | 115 +++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 114 insertions(+), 1 deletion(-)

diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 78db4f61d01c..3292dfed9d0a 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -11,7 +11,120 @@
 #include <drm/drm_dp_helper.h>
 
 /* VESA Display Stream Compression DSC 1.2 constants */
-#define DSC_NUM_BUF_RANGES	15
+#define DSC_NUM_BUF_RANGES			15
+#define DSC_MUX_WORD_SIZE_8_10_BPC		48
+#define DSC_MUX_WORD_SIZE_12_BPC		64
+#define DSC_RC_PIXELS_PER_GROUP			3
+#define DSC_SCALE_DECREMENT_INTERVAL_MAX	4095
+#define DSC_RANGE_BPG_OFFSET_MASK		0x3f
+
+/* Configuration for a single Rate Control model range */
+struct drm_dsc_rc_range_parameters {
+	/* Min Quantization Parameters allowed for this range */
+	u8 range_min_qp;
+	/* Max Quantization Parameters allowed for this range */
+	u8 range_max_qp;
+	/* Bits/group offset to apply to target for this group */
+	u8 range_bpg_offset;
+};
+
+struct drm_dsc_config {
+	/* Bits / component for previous reconstructed line buffer */
+	u8 line_buf_depth;
+	/* Bits per component to code (must be 8, 10, or 12) */
+	u8 bits_per_component;
+	/*
+	 * Flag indicating to do RGB - YCoCg conversion
+	 * and back (should be 1 for RGB input)
+	 */
+	bool convert_rgb;
+	u8 slice_count;
+	/* Slice Width */
+	u16 slice_width;
+	/* Slice Height */
+	u16 slice_height;
+	/*
+	 * 4:2:2 enable mode (from PPS, 4:2:2 conversion happens
+	 * outside of DSC encode/decode algorithm)
+	 */
+	bool enable422;
+	/* Picture Width */
+	u16 pic_width;
+	/* Picture Height */
+	u16 pic_height;
+	/* Offset to bits/group used by RC to determine QP adjustment */
+	u8 rc_tgt_offset_high;
+	/* Offset to bits/group used by RC to determine QP adjustment */
+	u8 rc_tgt_offset_low;
+	/* Bits/pixel target << 4 (ie., 4 fractional bits) */
+	u16 bits_per_pixel;
+	/*
+	 * Factor to determine if an edge is present based
+	 * on the bits produced
+	 */
+	u8 rc_edge_factor;
+	/* Slow down incrementing once the range reaches this value */
+	u8 rc_quant_incr_limit1;
+	/* Slow down incrementing once the range reaches this value */
+	u8 rc_quant_incr_limit0;
+	/* Number of pixels to delay the initial transmission */
+	u16 initial_xmit_delay;
+	/* Number of pixels to delay the VLD on the decoder,not including SSM */
+	u16  initial_dec_delay;
+	/* Block prediction enable */
+	bool block_pred_enable;
+	/* Bits/group offset to use for first line of the slice */
+	u8 first_line_bpg_offset;
+	/* Value to use for RC model offset at slice start */
+	u16 initial_offset;
+	/* Thresholds defining each of the buffer ranges */
+	u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
+	/* Parameters for each of the RC ranges */
+	struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
+	/* Total size of RC model */
+	u16 rc_model_size;
+	/* Minimum QP where flatness information is sent */
+	u8 flatness_min_qp;
+	/* Maximum QP where flatness information is sent */
+	u8 flatness_max_qp;
+	/* Initial value for scale factor */
+	u8 initial_scale_value;
+	/* Decrement scale factor every scale_decrement_interval groups */
+	u16 scale_decrement_interval;
+	/* Increment scale factor every scale_increment_interval groups */
+	u16 scale_increment_interval;
+	/* Non-first line BPG offset to use */
+	u16 nfl_bpg_offset;
+	/* BPG offset used to enforce slice bit */
+	u16 slice_bpg_offset;
+	/* Final RC linear transformation offset value */
+	u16 final_offset;
+	/* Enable on-off VBR (ie., disable stuffing bits) */
+	bool vbr_enable;
+	/* Mux word size (in bits) for SSM mode */
+	u8 mux_word_size;
+	/*
+	 * The (max) size in bytes of the "chunks" that are
+	 * used in slice multiplexing
+	 */
+	u16 slice_chunk_size;
+	/* Rate Control buffer siz in bits */
+	u16 rc_bits;
+	/* DSC Minor Version */
+	u8 dsc_version_minor;
+	/* DSC Major version */
+	u8 dsc_version_major;
+	/* Native 4:2:2 support */
+	bool native_422;
+	/* Native 4:2:0 support */
+	bool native_420;
+	/* Additional bits/grp for seconnd line of slice for native 4:2:0 */
+	u8 second_line_bpg_offset;
+	/* Num of bits deallocated for each grp that is not in second line of slice */
+	u16 nsl_bpg_offset;
+	/* Offset adj fr second line in Native 4:2:0 mode */
+	u16 second_line_offset_adj;
+};
 
 /**
  * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set
-- 
2.18.0

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[PATCH v7 03/19] drm/dsc: Define Rate Control values that do not change over configurations

[Manasi Navare]

From: "Srivatsa, Anusha" <anusha.srivatsa@intel.com>

DSC has some Rate Control values that remain constant
across all configurations. These are as per the DSC
standard.

v3:
* Define them in drm_dsc.h as they are
DSC constants (Manasi)
v2:
* Add DP_DSC_ prefix (Jani Nikula)

Cc: dri-devel@lists.freedesktop.org
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
---
 include/drm/drm_dsc.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 3292dfed9d0a..b88e31bd9da7 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -18,6 +18,12 @@
 #define DSC_SCALE_DECREMENT_INTERVAL_MAX	4095
 #define DSC_RANGE_BPG_OFFSET_MASK		0x3f
 
+/* DSC Rate Control Constants */
+#define DSC_RC_MODEL_SIZE_CONST		    8192
+#define DSC_RC_EDGE_FACTOR_CONST	    6
+#define DSC_RC_TGT_OFFSET_HI_CONST	    3
+#define DSC_RC_TGT_OFFSET_LO_CONST	    3
+
 /* Configuration for a single Rate Control model range */
 struct drm_dsc_rc_range_parameters {
 	/* Min Quantization Parameters allowed for this range */
-- 
2.18.0

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[PATCH v7 04/19] drm/dsc: Add helpers for DSC picture parameter set infoframes

[Manasi Navare]

According to Display Stream compression spec 1.2, the picture
parameter set metadata is sent from source to sink device
using the DP Secondary data packet. An infoframe is formed
for the PPS SDP header and PPS SDP payload bytes.
This patch adds helpers to fill the PPS SDP header
and PPS SDP payload according to the DSC 1.2 specification.

v7:
* Use BUILD_BUG_ON() to protect changing struct size (Ville)
* Remove typecaseting (Ville)
* Include byteorder.h in drm_dsc.c (Ville)
v6:
* Use proper sequence points for breaking down the
assignments (Chris Wilson)
* Use SPDX identifier
v5:
Do not use bitfields for DRM structs (Jani N)
v4:
* Use DSC constants for params that dont change across
configurations
v3:
* Add reference to added kernel-docs in Documentation/gpu/drm-kms-helpers.rst
(Daniel Vetter)

v2:
* Add EXPORT_SYMBOL for the drm functions (Manasi)

Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 Documentation/gpu/drm-kms-helpers.rst |  12 ++
 drivers/gpu/drm/Makefile              |   2 +-
 drivers/gpu/drm/drm_dsc.c             | 228 ++++++++++++++++++++++++++
 include/drm/drm_dsc.h                 |  21 +++
 4 files changed, 262 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/drm_dsc.c

diff --git a/Documentation/gpu/drm-kms-helpers.rst b/Documentation/gpu/drm-kms-helpers.rst
index 4b4dc236ef6f..b422eb8edf16 100644
--- a/Documentation/gpu/drm-kms-helpers.rst
+++ b/Documentation/gpu/drm-kms-helpers.rst
@@ -232,6 +232,18 @@ MIPI DSI Helper Functions Reference
 .. kernel-doc:: drivers/gpu/drm/drm_mipi_dsi.c
    :export:
 
+Display Stream Compression Helper Functions Reference
+=====================================================
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+   :doc: dsc helpers
+
+.. kernel-doc:: include/drm/drm_dsc.h
+   :internal:
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+   :export:
+
 Output Probing Helper Functions Reference
 =========================================
 
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 576ba985e138..3a3e6fb6d476 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -32,7 +32,7 @@ drm-$(CONFIG_AGP) += drm_agpsupport.o
 drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o
 drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
 
-drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \
+drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_dsc.o drm_probe_helper.o \
 		drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \
 		drm_kms_helper_common.o drm_dp_dual_mode_helper.o \
 		drm_simple_kms_helper.o drm_modeset_helper.o \
diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
new file mode 100644
index 000000000000..3a4942c1ae3b
--- /dev/null
+++ b/drivers/gpu/drm/drm_dsc.c
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2018 Intel Corp
+ *
+ * Author:
+ * Manasi Navare <manasi.d.navare@intel.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/byteorder/generic.h>
+#include <drm/drm_dp_helper.h>
+#include <drm/drm_dsc.h>
+
+/**
+ * DOC: dsc helpers
+ *
+ * These functions contain some common logic and helpers to deal with VESA
+ * Display Stream Compression standard required for DSC on Display Port/eDP or
+ * MIPI display interfaces.
+ */
+
+/**
+ * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
+ * for DisplayPort as per the DP 1.4 spec.
+ * @pps_sdp: Secondary data packet for DSC Picture Parameter Set
+ */
+void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp)
+{
+	memset(&pps_sdp->pps_header, 0, sizeof(pps_sdp->pps_header));
+
+	pps_sdp->pps_header.HB1 = DP_SDP_PPS;
+	pps_sdp->pps_header.HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;
+}
+EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
+
+/**
+ * drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe
+ * using the DSC configuration parameters in the order expected
+ * by the DSC Display Sink device. For the DSC, the sink device
+ * expects the PPS payload in the big endian format for the fields
+ * that span more than 1 byte.
+ *
+ * @pps_sdp:
+ * Secondary data packet for DSC Picture Parameter Set
+ * @dsc_cfg:
+ * DSC Configuration data filled by driver
+ */
+void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
+				const struct drm_dsc_config *dsc_cfg)
+{
+	int i;
+
+	/*Protect against someone accidently changing struct size */
+	BUILD_BUG_ON(sizeof(pps_sdp->pps_payload) !=
+		     DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1);
+
+	memset(&pps_sdp->pps_payload, 0, sizeof(pps_sdp->pps_payload));
+
+	/* PPS 0 */
+	pps_sdp->pps_payload.dsc_version =
+		dsc_cfg->dsc_version_minor |
+		dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
+
+	/* PPS 1, 2 is 0 */
+
+	/* PPS 3 */
+	pps_sdp->pps_payload.pps_3 =
+		dsc_cfg->line_buf_depth |
+		dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT;
+
+	/* PPS 4 */
+	pps_sdp->pps_payload.pps_4 =
+		((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >>
+		 DSC_PPS_MSB_SHIFT) |
+		dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
+		dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT |
+		dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
+		dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
+
+	/* PPS 5 */
+	pps_sdp->pps_payload.bits_per_pixel_low =
+		(dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK);
+
+	/*
+	 * The DSC panel expects the PPS packet to have big endian format
+	 * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert
+	 * to big endian format. If format is little endian, it will swap
+	 * bytes to convert to Big endian else keep it unchanged.
+	 */
+
+	/* PPS 6, 7 */
+	pps_sdp->pps_payload.pic_height = cpu_to_be16(dsc_cfg->pic_height);
+
+	/* PPS 8, 9 */
+	pps_sdp->pps_payload.pic_width = cpu_to_be16(dsc_cfg->pic_width);
+
+	/* PPS 10, 11 */
+	pps_sdp->pps_payload.slice_height = cpu_to_be16(dsc_cfg->slice_height);
+
+	/* PPS 12, 13 */
+	pps_sdp->pps_payload.slice_width = cpu_to_be16(dsc_cfg->slice_width);
+
+	/* PPS 14, 15 */
+	pps_sdp->pps_payload.chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);
+
+	/* PPS 16 */
+	pps_sdp->pps_payload.initial_xmit_delay_high =
+		((dsc_cfg->initial_xmit_delay &
+		  DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >>
+		 DSC_PPS_MSB_SHIFT);
+
+	/* PPS 17 */
+	pps_sdp->pps_payload.initial_xmit_delay_low =
+		(dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK);
+
+	/* PPS 18, 19 */
+	pps_sdp->pps_payload.initial_dec_delay =
+		cpu_to_be16(dsc_cfg->initial_dec_delay);
+
+	/* PPS 20 is 0 */
+
+	/* PPS 21 */
+	pps_sdp->pps_payload.initial_scale_value =
+		dsc_cfg->initial_scale_value;
+
+	/* PPS 22, 23 */
+	pps_sdp->pps_payload.scale_increment_interval =
+		cpu_to_be16(dsc_cfg->scale_increment_interval);
+
+	/* PPS 24 */
+	pps_sdp->pps_payload.scale_decrement_interval_high =
+		((dsc_cfg->scale_decrement_interval &
+		  DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>
+		 DSC_PPS_MSB_SHIFT);
+
+	/* PPS 25 */
+	pps_sdp->pps_payload.scale_decrement_interval_low =
+		(dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK);
+
+	/* PPS 26[7:0], PPS 27[7:5] RESERVED */
+
+	/* PPS 27 */
+	pps_sdp->pps_payload.first_line_bpg_offset =
+		dsc_cfg->first_line_bpg_offset;
+
+	/* PPS 28, 29 */
+	pps_sdp->pps_payload.nfl_bpg_offset =
+		cpu_to_be16(dsc_cfg->nfl_bpg_offset);
+
+	/* PPS 30, 31 */
+	pps_sdp->pps_payload.slice_bpg_offset =
+		cpu_to_be16(dsc_cfg->slice_bpg_offset);
+
+	/* PPS 32, 33 */
+	pps_sdp->pps_payload.initial_offset =
+		cpu_to_be16(dsc_cfg->initial_offset);
+
+	/* PPS 34, 35 */
+	pps_sdp->pps_payload.final_offset = cpu_to_be16(dsc_cfg->final_offset);
+
+	/* PPS 36 */
+	pps_sdp->pps_payload.flatness_min_qp = dsc_cfg->flatness_min_qp;
+
+	/* PPS 37 */
+	pps_sdp->pps_payload.flatness_max_qp = dsc_cfg->flatness_max_qp;
+
+	/* PPS 38, 39 */
+	pps_sdp->pps_payload.rc_model_size =
+		cpu_to_be16(DSC_RC_MODEL_SIZE_CONST);
+
+	/* PPS 40 */
+	pps_sdp->pps_payload.rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
+
+	/* PPS 41 */
+	pps_sdp->pps_payload.rc_quant_incr_limit0 =
+		dsc_cfg->rc_quant_incr_limit0;
+
+	/* PPS 42 */
+	pps_sdp->pps_payload.rc_quant_incr_limit1 =
+		dsc_cfg->rc_quant_incr_limit1;
+
+	/* PPS 43 */
+	pps_sdp->pps_payload.rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST |
+		DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT;
+
+	/* PPS 44 - 57 */
+	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
+		pps_sdp->pps_payload.rc_buf_thresh[i] =
+			dsc_cfg->rc_buf_thresh[i];
+
+	/* PPS 58 - 87 */
+	/*
+	 * For DSC sink programming the RC Range parameter fields
+	 * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0]
+	 */
+	for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
+		pps_sdp->pps_payload.rc_range_parameters[i] =
+			((dsc_cfg->rc_range_params[i].range_min_qp <<
+			  DSC_PPS_RC_RANGE_MINQP_SHIFT) |
+			 (dsc_cfg->rc_range_params[i].range_max_qp <<
+			  DSC_PPS_RC_RANGE_MAXQP_SHIFT) |
+			 (dsc_cfg->rc_range_params[i].range_bpg_offset));
+		pps_sdp->pps_payload.rc_range_parameters[i] =
+			cpu_to_be16(pps_sdp->pps_payload.rc_range_parameters[i]);
+	}
+
+	/* PPS 88 */
+	pps_sdp->pps_payload.native_422_420 = dsc_cfg->native_422 |
+		dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT;
+
+	/* PPS 89 */
+	pps_sdp->pps_payload.second_line_bpg_offset =
+		dsc_cfg->second_line_bpg_offset;
+
+	/* PPS 90, 91 */
+	pps_sdp->pps_payload.nsl_bpg_offset =
+		cpu_to_be16(dsc_cfg->nsl_bpg_offset);
+
+	/* PPS 92, 93 */
+	pps_sdp->pps_payload.second_line_offset_adj =
+		cpu_to_be16(dsc_cfg->second_line_offset_adj);
+
+	/* PPS 94 - 127 are O */
+}
+EXPORT_SYMBOL(drm_dsc_pps_infoframe_pack);
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index b88e31bd9da7..52e57ceaff80 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -24,6 +24,23 @@
 #define DSC_RC_TGT_OFFSET_HI_CONST	    3
 #define DSC_RC_TGT_OFFSET_LO_CONST	    3
 
+/* DSC PPS constants and macros */
+#define DSC_PPS_VERSION_MAJOR_SHIFT		4
+#define DSC_PPS_BPC_SHIFT			4
+#define DSC_PPS_MSB_SHIFT			8
+#define DSC_PPS_LSB_MASK			(0xFF << 0)
+#define DSC_PPS_BPP_HIGH_MASK			(0x3 << 8)
+#define DSC_PPS_VBR_EN_SHIFT			2
+#define DSC_PPS_SIMPLE422_SHIFT			3
+#define DSC_PPS_CONVERT_RGB_SHIFT		4
+#define DSC_PPS_BLOCK_PRED_EN_SHIFT		5
+#define DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK	(0x3 << 8)
+#define DSC_PPS_SCALE_DEC_INT_HIGH_MASK		(0xF << 8)
+#define DSC_PPS_RC_TGT_OFFSET_HI_SHIFT		4
+#define DSC_PPS_RC_RANGE_MINQP_SHIFT		11
+#define DSC_PPS_RC_RANGE_MAXQP_SHIFT		6
+#define DSC_PPS_NATIVE_420_SHIFT		1
+
 /* Configuration for a single Rate Control model range */
 struct drm_dsc_rc_range_parameters {
 	/* Min Quantization Parameters allowed for this range */
@@ -458,4 +475,8 @@ struct drm_dsc_pps_infoframe {
 	struct drm_dsc_picture_parameter_set pps_payload;
 } __packed;
 
+void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp);
+void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
+				const struct drm_dsc_config *dsc_cfg);
+
 #endif /* _DRM_DSC_H_ */
-- 
2.18.0

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[PATCH v7 05/19] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state

[Manasi Navare]

Basic DSC parameters and DSC configuration data needs to be computed
for each of the requested mode during atomic check. This is
required since for certain modes, valid DSC parameters and config
data might not be computed in which case compression cannot be
enabled for that mode.
For that reason we need to add these params and config structure
to the intel_crtc_state so that if valid this state information
can directly be used while enabling DSC in atomic commit.

v2:
* Rebase on drm-tip (Manasi)

Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  | 1 +
 drivers/gpu/drm/i915/intel_drv.h | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6157f8128cc5..d7797a41c648 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -53,6 +53,7 @@
 #include <drm/drm_auth.h>
 #include <drm/drm_cache.h>
 #include <drm/drm_util.h>
+#include <drm/drm_dsc.h>
 
 #include "i915_params.h"
 #include "i915_reg.h"
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 191c26e17f2d..491872353cf0 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -936,6 +936,15 @@ struct intel_crtc_state {
 
 	/* Output down scaling is done in LSPCON device */
 	bool lspcon_downsampling;
+
+	/* Display Stream compression state */
+	struct {
+		bool compression_enable;
+		bool dsc_split;
+		u16 compressed_bpp;
+		u8 slice_count;
+	} dsc_params;
+	struct drm_dsc_config dp_dsc_cfg;
 };
 
 struct intel_crtc {
-- 
2.18.0

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[PATCH v7 06/19] drm/i915/dp: Compute DSC pipe config in atomic check

[Manasi Navare]

DSC params like the enable, compressed bpp, slice count and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the remaining DSC
and RC parameters before enbaling DSC in atomic commit.

v10:
* Add a helper for dp_dsc support (Ville)
* Set pipe_config to max bpp, link params for DSC for now (Ville)
* Compute bpp - use dp dsc support helper (Ville)
v9:
* Rebase on top of drm-tip that now uses fast_narrow config
for edp (Manasi)
v8:
* Check for DSC bpc not 0 (manasi)

v7:
* Fix indentation in compute_m_n (Manasi)

v6 (From Gaurav):
* Remove function call of intel_dp_compute_dsc_params() and
invoke intel_dp_compute_dsc_params() in the patch where
it is defined to fix compilation warning (Gaurav)

v5:
Add drm_dsc_cfg in intel_crtc_state (Manasi)

v4:
* Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
* Add a comment why we need to check PSR while enabling DSC (Gaurav)

v3:
* Check PPR > max_cdclock to use 2 VDSC instances (Ville)

v2:
* Add if-else for eDP/DP (Gaurav)

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Acked-by: Jani Nikula <jani.nikula@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |  20 +++-
 drivers/gpu/drm/i915/intel_display.h |   3 +-
 drivers/gpu/drm/i915/intel_dp.c      | 172 +++++++++++++++++++++++----
 drivers/gpu/drm/i915/intel_dp_mst.c  |   2 +-
 4 files changed, 167 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b219d5858160..477e53c37353 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6442,7 +6442,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
 
 	pipe_config->fdi_lanes = lane;
 
-	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
+	intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock,
 			       link_bw, &pipe_config->fdi_m_n, false);
 
 	ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
@@ -6679,17 +6679,25 @@ static void compute_m_n(unsigned int m, unsigned int n,
 }
 
 void
-intel_link_compute_m_n(int bits_per_pixel, int nlanes,
+intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
+		       int nlanes,
 		       int pixel_clock, int link_clock,
 		       struct intel_link_m_n *m_n,
 		       bool constant_n)
 {
 	m_n->tu = 64;
 
-	compute_m_n(bits_per_pixel * pixel_clock,
-		    link_clock * nlanes * 8,
-		    &m_n->gmch_m, &m_n->gmch_n,
-		    constant_n);
+	/* For DSC, Data M/N calculation uses compressed BPP */
+	if (compressed_bpp)
+		compute_m_n(compressed_bpp * pixel_clock,
+			    link_clock * nlanes * 8,
+			    &m_n->gmch_m, &m_n->gmch_n,
+			    constant_n);
+	else
+		compute_m_n(bits_per_pixel * pixel_clock,
+			    link_clock * nlanes * 8,
+			    &m_n->gmch_m, &m_n->gmch_n,
+			    constant_n);
 
 	compute_m_n(pixel_clock, link_clock,
 		    &m_n->link_m, &m_n->link_n,
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index 5d50decbcbb5..b0b23e1e9392 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -407,7 +407,8 @@ struct intel_link_m_n {
 	     (__i)++) \
 		for_each_if(plane)
 
-void intel_link_compute_m_n(int bpp, int nlanes,
+void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
+			    int nlanes,
 			    int pixel_clock, int link_clock,
 			    struct intel_link_m_n *m_n,
 			    bool constant_n);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b39b4bda8e40..1b10e27b3e2b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -47,6 +47,8 @@
 
 /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
 #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER	61440
+#define DP_DSC_MIN_SUPPORTED_BPC		8
+#define DP_DSC_MAX_SUPPORTED_BPC		10
 
 /* DP DSC throughput values used for slice count calculations KPixels/s */
 #define DP_DSC_PEAK_PIXEL_RATE			2720000
@@ -1840,6 +1842,29 @@ struct link_config_limits {
 	int min_bpp, max_bpp;
 };
 
+static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
+					 struct intel_crtc_state *pipe_config)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+	if (INTEL_GEN(dev_priv) < 10)
+		return false;
+	if (pipe_config->cpu_transcoder == TRANSCODER_A)
+		return false;
+
+	return true;
+}
+
+static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
+				  struct intel_crtc_state *pipe_config)
+{
+	if (!intel_dp_source_supports_dsc(intel_dp, pipe_config) ||
+	    !drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd))
+		return false;
+
+	return true;
+}
+
 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
 				struct intel_crtc_state *pipe_config)
 {
@@ -1863,6 +1888,15 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
 		}
 	}
 
+	/* If DSC is supported, use the max value reported by panel */
+	if (intel_dp_supports_dsc(intel_dp, pipe_config)) {
+		bpc = min_t(u8,
+			    drm_dp_dsc_sink_max_color_depth(intel_dp->dsc_dpcd),
+			    DP_DSC_MAX_SUPPORTED_BPC);
+		if (bpc)
+			bpp = min(bpp, 3*bpc);
+	}
+
 	return bpp;
 }
 
@@ -1923,12 +1957,10 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
 				link_clock = intel_dp->common_rates[clock];
 				link_avail = intel_dp_max_data_rate(link_clock,
 								    lane_count);
-
 				if (mode_rate <= link_avail) {
 					pipe_config->lane_count = lane_count;
 					pipe_config->pipe_bpp = bpp;
 					pipe_config->port_clock = link_clock;
-
 					return true;
 				}
 			}
@@ -1959,12 +1991,10 @@ intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
 				link_clock = intel_dp->common_rates[clock];
 				link_avail = intel_dp_max_data_rate(link_clock,
 								    lane_count);
-
 				if (mode_rate <= link_avail) {
 					pipe_config->lane_count = lane_count;
 					pipe_config->pipe_bpp = bpp;
 					pipe_config->port_clock = link_clock;
-
 					return true;
 				}
 			}
@@ -1974,6 +2004,81 @@ intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
 	return false;
 }
 
+static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
+					struct intel_crtc_state *pipe_config,
+					const struct link_config_limits *limits)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+	u16 dsc_max_output_bpp = 0;
+	u8 dsc_dp_slice_count = 0;
+
+	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
+		return false;
+
+	/* DSC not supported for DSC sink BPC < 8 */
+	if (limits->max_bpp < 3 * DP_DSC_MIN_SUPPORTED_BPC) {
+		DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
+		return false;
+	}
+
+	/*
+	 * For now enable DSC for max bpp, max link rate, max lane count.
+	 * Optimize this later for the minimum possible link rate/lane count
+	 * with DSC enabled for the requested mode.
+	 */
+	pipe_config->pipe_bpp = limits->max_bpp;
+	pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
+	pipe_config->lane_count = limits->max_lane_count;
+
+	if (intel_dp_is_edp(intel_dp)) {
+		pipe_config->dsc_params.compressed_bpp =
+			drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
+		pipe_config->dsc_params.slice_count =
+			drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
+							true);
+	} else {
+		dsc_max_output_bpp =
+			intel_dp_dsc_get_output_bpp(pipe_config->port_clock,
+						    pipe_config->lane_count,
+						    adjusted_mode->crtc_clock,
+						    adjusted_mode->crtc_hdisplay);
+		dsc_dp_slice_count =
+			intel_dp_dsc_get_slice_count(intel_dp,
+						     adjusted_mode->crtc_clock,
+						     adjusted_mode->crtc_hdisplay);
+		if (!(dsc_max_output_bpp && dsc_dp_slice_count)) {
+			DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
+			return false;
+		}
+		pipe_config->dsc_params.compressed_bpp = dsc_max_output_bpp >> 4;
+		pipe_config->dsc_params.slice_count = dsc_dp_slice_count;
+	}
+	/*
+	 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
+	 * is greater than the maximum Cdclock and if slice count is even
+	 * then we need to use 2 VDSC instances.
+	 */
+	pipe_config->dsc_params.dsc_split = false;
+	if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
+		if (pipe_config->dsc_params.slice_count > 1) {
+			pipe_config->dsc_params.dsc_split = true;
+		} else {
+			DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
+			return false;
+		}
+	}
+	pipe_config->dsc_params.compression_enable = true;
+	DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
+		      "Compressed Bpp = %d Slice Count = %d\n",
+		      pipe_config->pipe_bpp,
+		      pipe_config->dsc_params.compressed_bpp,
+		      pipe_config->dsc_params.slice_count);
+
+	return true;
+}
+
 static bool
 intel_dp_compute_link_config(struct intel_encoder *encoder,
 			     struct intel_crtc_state *pipe_config)
@@ -1982,6 +2087,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	struct link_config_limits limits;
 	int common_len;
+	bool ret = false;
 
 	common_len = intel_dp_common_len_rate_limit(intel_dp,
 						    intel_dp->max_link_rate);
@@ -1995,8 +2101,12 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 	limits.min_lane_count = 1;
 	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
 
-	limits.min_bpp = 6 * 3;
 	limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
+	if (intel_dp_supports_dsc(intel_dp, pipe_config) &&
+	    limits.max_bpp >= DP_DSC_MIN_SUPPORTED_BPC*3)
+		limits.min_bpp = DP_DSC_MIN_SUPPORTED_BPC * 3;
+	else
+		limits.min_bpp = 6 * 3;
 
 	if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) {
 		/*
@@ -2020,7 +2130,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 		      intel_dp->common_rates[limits.max_clock],
 		      limits.max_bpp, adjusted_mode->crtc_clock);
 
-	if (intel_dp_is_edp(intel_dp)) {
+	if (intel_dp_is_edp(intel_dp))
 		/*
 		 * Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4
 		 * section A.1: "It is recommended that the minimum number of
@@ -2030,26 +2140,42 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 		 * Note that we use the max clock and lane count for eDP 1.3 and
 		 * earlier, and fast vs. wide is irrelevant.
 		 */
-		if (!intel_dp_compute_link_config_fast(intel_dp, pipe_config,
-						       &limits))
-			return false;
-	} else {
+		ret = intel_dp_compute_link_config_fast(intel_dp, pipe_config,
+							&limits);
+	else
 		/* Optimize for slow and wide. */
-		if (!intel_dp_compute_link_config_wide(intel_dp, pipe_config,
-						       &limits))
+		ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
+							&limits);
+
+	/* enable compression if the mode doesn't fit available BW */
+	if (!ret) {
+		if (!intel_dp_dsc_compute_config(intel_dp, pipe_config,
+						 &limits))
 			return false;
 	}
 
-	DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
-		      pipe_config->lane_count, pipe_config->port_clock,
-		      pipe_config->pipe_bpp);
+	if (pipe_config->dsc_params.compression_enable) {
+		DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
+			      pipe_config->lane_count, pipe_config->port_clock,
+			      pipe_config->pipe_bpp,
+			      pipe_config->dsc_params.compressed_bpp);
 
-	DRM_DEBUG_KMS("DP link rate required %i available %i\n",
-		      intel_dp_link_required(adjusted_mode->crtc_clock,
-					     pipe_config->pipe_bpp),
-		      intel_dp_max_data_rate(pipe_config->port_clock,
-					     pipe_config->lane_count));
+		DRM_DEBUG_KMS("DP link rate required %i available %i\n",
+			      intel_dp_link_required(adjusted_mode->crtc_clock,
+						     pipe_config->dsc_params.compressed_bpp),
+			      intel_dp_max_data_rate(pipe_config->port_clock,
+						     pipe_config->lane_count));
+	} else {
+		DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
+			      pipe_config->lane_count, pipe_config->port_clock,
+			      pipe_config->pipe_bpp);
 
+		DRM_DEBUG_KMS("DP link rate required %i available %i\n",
+			      intel_dp_link_required(adjusted_mode->crtc_clock,
+						     pipe_config->pipe_bpp),
+			      intel_dp_max_data_rate(pipe_config->port_clock,
+						     pipe_config->lane_count));
+	}
 	return true;
 }
 
@@ -2133,7 +2259,9 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 			intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
 	}
 
-	intel_link_compute_m_n(pipe_config->pipe_bpp, pipe_config->lane_count,
+	intel_link_compute_m_n(pipe_config->pipe_bpp,
+			       pipe_config->dsc_params.compressed_bpp,
+			       pipe_config->lane_count,
 			       adjusted_mode->crtc_clock,
 			       pipe_config->port_clock,
 			       &pipe_config->dp_m_n,
@@ -2142,7 +2270,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	if (intel_connector->panel.downclock_mode != NULL &&
 		dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
 			pipe_config->has_drrs = true;
-			intel_link_compute_m_n(pipe_config->pipe_bpp,
+			intel_link_compute_m_n(pipe_config->pipe_bpp, 0,
 					       pipe_config->lane_count,
 					       intel_connector->panel.downclock_mode->clock,
 					       pipe_config->port_clock,
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 8b71d64ebd9d..e02caedd443c 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -90,7 +90,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
 		}
 	}
 
-	intel_link_compute_m_n(bpp, lane_count,
+	intel_link_compute_m_n(bpp, 0, lane_count,
 			       adjusted_mode->crtc_clock,
 			       pipe_config->port_clock,
 			       &pipe_config->dp_m_n,
-- 
2.18.0

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Re: [PATCH v7 06/19] drm/i915/dp: Compute DSC pipe config in atomic check

[Ville Syrjälä]

On Thu, Nov 01, 2018 at 11:46:46PM -0700, Manasi Navare wrote:
> DSC params like the enable, compressed bpp, slice count and
> dsc_split are added to the intel_crtc_state. These parameters
> are set based on the requested mode and available link parameters
> during the pipe configuration in atomic check phase.
> These values are then later used to populate the remaining DSC
> and RC parameters before enbaling DSC in atomic commit.
> 
> v10:
> * Add a helper for dp_dsc support (Ville)
> * Set pipe_config to max bpp, link params for DSC for now (Ville)
> * Compute bpp - use dp dsc support helper (Ville)
> v9:
> * Rebase on top of drm-tip that now uses fast_narrow config
> for edp (Manasi)
> v8:
> * Check for DSC bpc not 0 (manasi)
> 
> v7:
> * Fix indentation in compute_m_n (Manasi)
> 
> v6 (From Gaurav):
> * Remove function call of intel_dp_compute_dsc_params() and
> invoke intel_dp_compute_dsc_params() in the patch where
> it is defined to fix compilation warning (Gaurav)
> 
> v5:
> Add drm_dsc_cfg in intel_crtc_state (Manasi)
> 
> v4:
> * Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
> * Add a comment why we need to check PSR while enabling DSC (Gaurav)
> 
> v3:
> * Check PPR > max_cdclock to use 2 VDSC instances (Ville)
> 
> v2:
> * Add if-else for eDP/DP (Gaurav)
> 
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Acked-by: Jani Nikula <jani.nikula@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |  20 +++-
>  drivers/gpu/drm/i915/intel_display.h |   3 +-
>  drivers/gpu/drm/i915/intel_dp.c      | 172 +++++++++++++++++++++++----
>  drivers/gpu/drm/i915/intel_dp_mst.c  |   2 +-
>  4 files changed, 167 insertions(+), 30 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b219d5858160..477e53c37353 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6442,7 +6442,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
>  
>  	pipe_config->fdi_lanes = lane;
>  
> -	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
> +	intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock,
>  			       link_bw, &pipe_config->fdi_m_n, false);
>  
>  	ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
> @@ -6679,17 +6679,25 @@ static void compute_m_n(unsigned int m, unsigned int n,
>  }
>  
>  void
> -intel_link_compute_m_n(int bits_per_pixel, int nlanes,
> +intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
> +		       int nlanes,
>  		       int pixel_clock, int link_clock,
>  		       struct intel_link_m_n *m_n,
>  		       bool constant_n)
>  {
>  	m_n->tu = 64;
>  
> -	compute_m_n(bits_per_pixel * pixel_clock,
> -		    link_clock * nlanes * 8,
> -		    &m_n->gmch_m, &m_n->gmch_n,
> -		    constant_n);
> +	/* For DSC, Data M/N calculation uses compressed BPP */
> +	if (compressed_bpp)
> +		compute_m_n(compressed_bpp * pixel_clock,
> +			    link_clock * nlanes * 8,
> +			    &m_n->gmch_m, &m_n->gmch_n,
> +			    constant_n);
> +	else
> +		compute_m_n(bits_per_pixel * pixel_clock,
> +			    link_clock * nlanes * 8,
> +			    &m_n->gmch_m, &m_n->gmch_n,
> +			    constant_n);
>  
>  	compute_m_n(pixel_clock, link_clock,
>  		    &m_n->link_m, &m_n->link_n,
> diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
> index 5d50decbcbb5..b0b23e1e9392 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -407,7 +407,8 @@ struct intel_link_m_n {
>  	     (__i)++) \
>  		for_each_if(plane)
>  
> -void intel_link_compute_m_n(int bpp, int nlanes,
> +void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
> +			    int nlanes,
>  			    int pixel_clock, int link_clock,
>  			    struct intel_link_m_n *m_n,
>  			    bool constant_n);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index b39b4bda8e40..1b10e27b3e2b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -47,6 +47,8 @@
>  
>  /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
>  #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER	61440
> +#define DP_DSC_MIN_SUPPORTED_BPC		8
> +#define DP_DSC_MAX_SUPPORTED_BPC		10
>  
>  /* DP DSC throughput values used for slice count calculations KPixels/s */
>  #define DP_DSC_PEAK_PIXEL_RATE			2720000
> @@ -1840,6 +1842,29 @@ struct link_config_limits {
>  	int min_bpp, max_bpp;
>  };
>  
> +static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
> +					 struct intel_crtc_state *pipe_config)a

nit
const struct intel_crtc_state *crtc_state

same all over the series.

> +{
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> +	if (INTEL_GEN(dev_priv) < 10)
> +		return false;
> +	if (pipe_config->cpu_transcoder == TRANSCODER_A)
> +		return false;
> +
> +	return true;

return GEN >= 10 && transcoder != A;
would seem easier to parse.

And until we get FEC this seems like it needs to say
/* FIXME FEC needed */
if (!is_edp())
	return false;

otherwise I presume we'll try to enable DSC without FEC and that
won't end well.

> +}
> +
> +static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
> +				  struct intel_crtc_state *pipe_config)
> +{
> +	if (!intel_dp_source_supports_dsc(intel_dp, pipe_config) ||
> +	    !drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd))
> +		return false;
> +
> +	return true;
> +}
> +
>  static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
>  				struct intel_crtc_state *pipe_config)
>  {
> @@ -1863,6 +1888,15 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
>  		}
>  	}
>  
> +	/* If DSC is supported, use the max value reported by panel */
> +	if (intel_dp_supports_dsc(intel_dp, pipe_config)) {
> +		bpc = min_t(u8,
> +			    drm_dp_dsc_sink_max_color_depth(intel_dp->dsc_dpcd),
> +			    DP_DSC_MAX_SUPPORTED_BPC);
> +		if (bpc)
> +			bpp = min(bpp, 3*bpc);
> +	}
> +
>  	return bpp;
>  }
>  
> @@ -1923,12 +1957,10 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
>  				link_clock = intel_dp->common_rates[clock];
>  				link_avail = intel_dp_max_data_rate(link_clock,
>  								    lane_count);
> -
>  				if (mode_rate <= link_avail) {
>  					pipe_config->lane_count = lane_count;
>  					pipe_config->pipe_bpp = bpp;
>  					pipe_config->port_clock = link_clock;
> -
>  					return true;
>  				}
>  			}
> @@ -1959,12 +1991,10 @@ intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
>  				link_clock = intel_dp->common_rates[clock];
>  				link_avail = intel_dp_max_data_rate(link_clock,
>  								    lane_count);
> -
>  				if (mode_rate <= link_avail) {
>  					pipe_config->lane_count = lane_count;
>  					pipe_config->pipe_bpp = bpp;
>  					pipe_config->port_clock = link_clock;
> -

Leftover changes. Increases the chance of conflicts.

>  					return true;
>  				}
>  			}
> @@ -1974,6 +2004,81 @@ intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
>  	return false;
>  }
>  
> +static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> +					struct intel_crtc_state *pipe_config,
> +					const struct link_config_limits *limits)
> +{
> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> +	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> +	u16 dsc_max_output_bpp = 0;
> +	u8 dsc_dp_slice_count = 0;
> +
> +	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> +		return false;
> +
> +	/* DSC not supported for DSC sink BPC < 8 */
> +	if (limits->max_bpp < 3 * DP_DSC_MIN_SUPPORTED_BPC) {
> +		DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
> +		return false;
> +	}
> +
> +	/*
> +	 * For now enable DSC for max bpp, max link rate, max lane count.
> +	 * Optimize this later for the minimum possible link rate/lane count
> +	 * with DSC enabled for the requested mode.
> +	 */
> +	pipe_config->pipe_bpp = limits->max_bpp;
> +	pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
> +	pipe_config->lane_count = limits->max_lane_count;
> +
> +	if (intel_dp_is_edp(intel_dp)) {
> +		pipe_config->dsc_params.compressed_bpp =
> +			drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
> +		pipe_config->dsc_params.slice_count =
> +			drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
> +							true);
> +	} else {
> +		dsc_max_output_bpp =
> +			intel_dp_dsc_get_output_bpp(pipe_config->port_clock,
> +						    pipe_config->lane_count,
> +						    adjusted_mode->crtc_clock,
> +						    adjusted_mode->crtc_hdisplay);
> +		dsc_dp_slice_count =
> +			intel_dp_dsc_get_slice_count(intel_dp,
> +						     adjusted_mode->crtc_clock,
> +						     adjusted_mode->crtc_hdisplay);
> +		if (!(dsc_max_output_bpp && dsc_dp_slice_count)) {
> +			DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
> +			return false;
> +		}
> +		pipe_config->dsc_params.compressed_bpp = dsc_max_output_bpp >> 4;
> +		pipe_config->dsc_params.slice_count = dsc_dp_slice_count;
> +	}
> +	/*
> +	 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
> +	 * is greater than the maximum Cdclock and if slice count is even
> +	 * then we need to use 2 VDSC instances.
> +	 */
> +	pipe_config->dsc_params.dsc_split = false;

This will be false already, no need to set again.

> +	if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
> +		if (pipe_config->dsc_params.slice_count > 1) {
> +			pipe_config->dsc_params.dsc_split = true;
> +		} else {
> +			DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
> +			return false;
> +		}
> +	}
> +	pipe_config->dsc_params.compression_enable = true;
> +	DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
> +		      "Compressed Bpp = %d Slice Count = %d\n",
> +		      pipe_config->pipe_bpp,
> +		      pipe_config->dsc_params.compressed_bpp,
> +		      pipe_config->dsc_params.slice_count);
> +
> +	return true;
> +}
> +
>  static bool
>  intel_dp_compute_link_config(struct intel_encoder *encoder,
>  			     struct intel_crtc_state *pipe_config)
> @@ -1982,6 +2087,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
>  	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
>  	struct link_config_limits limits;
>  	int common_len;
> +	bool ret = false;
>  
>  	common_len = intel_dp_common_len_rate_limit(intel_dp,
>  						    intel_dp->max_link_rate);
> @@ -1995,8 +2101,12 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
>  	limits.min_lane_count = 1;
>  	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
>  
> -	limits.min_bpp = 6 * 3;
>  	limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
> +	if (intel_dp_supports_dsc(intel_dp, pipe_config) &&
> +	    limits.max_bpp >= DP_DSC_MIN_SUPPORTED_BPC*3)
> +		limits.min_bpp = DP_DSC_MIN_SUPPORTED_BPC * 3;
> +	else
> +		limits.min_bpp = 6 * 3;
>  
>  	if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) {
>  		/*
> @@ -2020,7 +2130,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
>  		      intel_dp->common_rates[limits.max_clock],
>  		      limits.max_bpp, adjusted_mode->crtc_clock);
>  
> -	if (intel_dp_is_edp(intel_dp)) {
> +	if (intel_dp_is_edp(intel_dp))
>  		/*
>  		 * Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4
>  		 * section A.1: "It is recommended that the minimum number of
> @@ -2030,26 +2140,42 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
>  		 * Note that we use the max clock and lane count for eDP 1.3 and
>  		 * earlier, and fast vs. wide is irrelevant.
>  		 */
> -		if (!intel_dp_compute_link_config_fast(intel_dp, pipe_config,
> -						       &limits))
> -			return false;
> -	} else {
> +		ret = intel_dp_compute_link_config_fast(intel_dp, pipe_config,
> +							&limits);
> +	else
>  		/* Optimize for slow and wide. */
> -		if (!intel_dp_compute_link_config_wide(intel_dp, pipe_config,
> -						       &limits))
> +		ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
> +							&limits);
> +
> +	/* enable compression if the mode doesn't fit available BW */
> +	if (!ret) {
> +		if (!intel_dp_dsc_compute_config(intel_dp, pipe_config,
> +						 &limits))
>  			return false;
>  	}
>  
> -	DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
> -		      pipe_config->lane_count, pipe_config->port_clock,
> -		      pipe_config->pipe_bpp);
> +	if (pipe_config->dsc_params.compression_enable) {
> +		DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
> +			      pipe_config->lane_count, pipe_config->port_clock,
> +			      pipe_config->pipe_bpp,
> +			      pipe_config->dsc_params.compressed_bpp);
>  
> -	DRM_DEBUG_KMS("DP link rate required %i available %i\n",
> -		      intel_dp_link_required(adjusted_mode->crtc_clock,
> -					     pipe_config->pipe_bpp),
> -		      intel_dp_max_data_rate(pipe_config->port_clock,
> -					     pipe_config->lane_count));
> +		DRM_DEBUG_KMS("DP link rate required %i available %i\n",
> +			      intel_dp_link_required(adjusted_mode->crtc_clock,
> +						     pipe_config->dsc_params.compressed_bpp),
> +			      intel_dp_max_data_rate(pipe_config->port_clock,
> +						     pipe_config->lane_count));
> +	} else {
> +		DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
> +			      pipe_config->lane_count, pipe_config->port_clock,
> +			      pipe_config->pipe_bpp);
>  
> +		DRM_DEBUG_KMS("DP link rate required %i available %i\n",
> +			      intel_dp_link_required(adjusted_mode->crtc_clock,
> +						     pipe_config->pipe_bpp),
> +			      intel_dp_max_data_rate(pipe_config->port_clock,
> +						     pipe_config->lane_count));
> +	}
>  	return true;
>  }
>  
> @@ -2133,7 +2259,9 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  			intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
>  	}
>  
> -	intel_link_compute_m_n(pipe_config->pipe_bpp, pipe_config->lane_count,
> +	intel_link_compute_m_n(pipe_config->pipe_bpp,
> +			       pipe_config->dsc_params.compressed_bpp,
> +			       pipe_config->lane_count,
>  			       adjusted_mode->crtc_clock,
>  			       pipe_config->port_clock,
>  			       &pipe_config->dp_m_n,
> @@ -2142,7 +2270,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  	if (intel_connector->panel.downclock_mode != NULL &&
>  		dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
>  			pipe_config->has_drrs = true;
> -			intel_link_compute_m_n(pipe_config->pipe_bpp,
> +			intel_link_compute_m_n(pipe_config->pipe_bpp, 0,
>  					       pipe_config->lane_count,
>  					       intel_connector->panel.downclock_mode->clock,
>  					       pipe_config->port_clock,
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
> index 8b71d64ebd9d..e02caedd443c 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -90,7 +90,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
>  		}
>  	}
>  
> -	intel_link_compute_m_n(bpp, lane_count,
> +	intel_link_compute_m_n(bpp, 0, lane_count,
>  			       adjusted_mode->crtc_clock,
>  			       pipe_config->port_clock,
>  			       &pipe_config->dp_m_n,
> -- 
> 2.18.0

-- 
Ville Syrjälä
Intel
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[PATCH v7 07/19] drm/i915/dp: Do not enable PSR2 if DSC is enabled

[Manasi Navare]

If a eDP panel supports both PSR2 and VDSC, our HW cannot
support both at a time. Give priority to PSR2 if a requested
resolution can be supported without compression else enable
VDSC and keep PSR2 disabled.

v3:
* Rebase
v2:
* Add warning for DSC and PSR2 enabled together (DK)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index bc2d88313ed0..8f063e1e2fb2 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -71,9 +71,9 @@ static bool psr_global_enabled(u32 debug)
 static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
 			       const struct intel_crtc_state *crtc_state)
 {
-	/* Disable PSR2 by default for all platforms */
-	if (i915_modparams.enable_psr == -1)
-		return false;
+	/* Cannot enable DSC and PSR2 simultaneously */
+	WARN_ON(crtc_state->dsc_params.compression_enable &&
+		crtc_state->has_psr2);
 
 	switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
 	case I915_PSR_DEBUG_FORCE_PSR1:
@@ -463,6 +463,16 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 	if (!dev_priv->psr.sink_psr2_support)
 		return false;
 
+	/*
+	 * DSC and PSR2 cannot be enabled simultaneously. If a requested
+	 * resolution requires DSC to be enabled, priority is given to DSC
+	 * over PSR2.
+	 */
+	if (crtc_state->dsc_params.compression_enable) {
+		DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n");
+		return false;
+	}
+
 	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
 		psr_max_h = 4096;
 		psr_max_v = 2304;
-- 
2.18.0

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Re: [PATCH v7 07/19] drm/i915/dp: Do not enable PSR2 if DSC is enabled

[Ville Syrjälä]

On Thu, Nov 01, 2018 at 11:46:47PM -0700, Manasi Navare wrote:
> If a eDP panel supports both PSR2 and VDSC, our HW cannot
> support both at a time. Give priority to PSR2 if a requested
> resolution can be supported without compression else enable
> VDSC and keep PSR2 disabled.
> 
> v3:
> * Rebase
> v2:
> * Add warning for DSC and PSR2 enabled together (DK)
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_psr.c | 16 +++++++++++++---
>  1 file changed, 13 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index bc2d88313ed0..8f063e1e2fb2 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -71,9 +71,9 @@ static bool psr_global_enabled(u32 debug)
>  static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
>  			       const struct intel_crtc_state *crtc_state)
>  {
> -	/* Disable PSR2 by default for all platforms */
> -	if (i915_modparams.enable_psr == -1)
> -		return false;

That seems unrelated to DSC?

> +	/* Cannot enable DSC and PSR2 simultaneously */
> +	WARN_ON(crtc_state->dsc_params.compression_enable &&
> +		crtc_state->has_psr2);
>  
>  	switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
>  	case I915_PSR_DEBUG_FORCE_PSR1:
> @@ -463,6 +463,16 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>  	if (!dev_priv->psr.sink_psr2_support)
>  		return false;
>  
> +	/*
> +	 * DSC and PSR2 cannot be enabled simultaneously. If a requested
> +	 * resolution requires DSC to be enabled, priority is given to DSC
> +	 * over PSR2.
> +	 */
> +	if (crtc_state->dsc_params.compression_enable) {
> +		DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n");
> +		return false;
> +	}
> +
>  	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
>  		psr_max_h = 4096;
>  		psr_max_v = 2304;
> -- 
> 2.18.0

-- 
Ville Syrjälä
Intel
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Re: [PATCH v7 07/19] drm/i915/dp: Do not enable PSR2 if DSC is enabled

[Manasi Navare]

On Fri, Nov 02, 2018 at 07:51:18PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 01, 2018 at 11:46:47PM -0700, Manasi Navare wrote:
> > If a eDP panel supports both PSR2 and VDSC, our HW cannot
> > support both at a time. Give priority to PSR2 if a requested
> > resolution can be supported without compression else enable
> > VDSC and keep PSR2 disabled.
> > 
> > v3:
> > * Rebase
> > v2:
> > * Add warning for DSC and PSR2 enabled together (DK)
> > 
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_psr.c | 16 +++++++++++++---
> >  1 file changed, 13 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> > index bc2d88313ed0..8f063e1e2fb2 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -71,9 +71,9 @@ static bool psr_global_enabled(u32 debug)
> >  static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
> >  			       const struct intel_crtc_state *crtc_state)
> >  {
> > -	/* Disable PSR2 by default for all platforms */
> > -	if (i915_modparams.enable_psr == -1)
> > -		return false;
> 
> That seems unrelated to DSC?

Thats a good catch, i think thsi got removed due to a rebase by mistake.
I will add it back there.

Manasi

> 
> > +	/* Cannot enable DSC and PSR2 simultaneously */
> > +	WARN_ON(crtc_state->dsc_params.compression_enable &&
> > +		crtc_state->has_psr2);
> >  
> >  	switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
> >  	case I915_PSR_DEBUG_FORCE_PSR1:
> > @@ -463,6 +463,16 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> >  	if (!dev_priv->psr.sink_psr2_support)
> >  		return false;
> >  
> > +	/*
> > +	 * DSC and PSR2 cannot be enabled simultaneously. If a requested
> > +	 * resolution requires DSC to be enabled, priority is given to DSC
> > +	 * over PSR2.
> > +	 */
> > +	if (crtc_state->dsc_params.compression_enable) {
> > +		DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n");
> > +		return false;
> > +	}
> > +
> >  	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
> >  		psr_max_h = 4096;
> >  		psr_max_v = 2304;
> > -- 
> > 2.18.0
> 
> -- 
> Ville Syrjälä
> Intel
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> https://lists.freedesktop.org/mailman/listinfo/dri-devel
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[PATCH v7 08/19] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants

[Manasi Navare]

DSC specification defines linebuf_depth which contains the
line buffer bit depth used to generate the bitstream.
These values are defined as per Table 4.1 in DSC 1.2 spec

v2 (From Manasi):
* Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2

Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 include/drm/drm_dsc.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 52e57ceaff80..d03f1b83421a 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -40,6 +40,9 @@
 #define DSC_PPS_RC_RANGE_MINQP_SHIFT		11
 #define DSC_PPS_RC_RANGE_MAXQP_SHIFT		6
 #define DSC_PPS_NATIVE_420_SHIFT		1
+#define DSC_1_2_MAX_LINEBUF_DEPTH_BITS		16
+#define DSC_1_2_MAX_LINEBUF_DEPTH_VAL		0
+#define DSC_1_1_MAX_LINEBUF_DEPTH_BITS		13
 
 /* Configuration for a single Rate Control model range */
 struct drm_dsc_rc_range_parameters {
-- 
2.18.0

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[PATCH v7 09/19] drm/i915/dsc: Define & Compute VESA DSC params

[Manasi Navare]

From: Gaurav K Singh <gaurav.k.singh@intel.com>

This patches does the following:

1. This patch defines all the DSC parameters as per the VESA
DSC specification. These are stored in the encoder and used
to compute the PPS parameters to be sent to the Sink.
2. Compute all the DSC parameters which are derived from DSC
state of intel_crtc_state.
3. Compute all parameters that are VESA DSC specific

This computation happens in the atomic check phase during
compute_config() to validate if display stream compression
can be enabled for the requested mode.

v7: (From Manasi)
* Dont use signed int for rc_range_params (Manasi)
* Mask the range_bpg_offset to use only 6 bits
* Add SPDX identifier (Chris Wilson)
v6 (From Manasi):
* Add a check for line_buf_depth return value (Anusha)
* Remove DRM DSC constants to different patch (Manasi)
v5 (From Manasi):
* Add logic to limit the max line buf depth for DSC 1.1 to 13
as per DSC 1.1 spec
* Fix dim checkpatch warnings/checks

v4 (From Gaurav):
* Rebase on latest drm tip
* rename variable name(Manasi)
* Populate linebuf_depth variable(Manasi)

v3 (From Gaurav):
* Rebase my previous patches on top of Manasi's latest patch
series
* Using >>n rather than /2^n (Manasi)
* Change the commit message to explain what the patch is doing(Gaurav)

Fixed review comments from Ville:
* Don't use macro TWOS_COMPLEMENT
* Mention in comment about the source of RC params
* Return directly from case statements
* Using single asssignment for assigning rc_range_params
* Using <<n rather than *2^n and removing the comments
about the fixed point numbers

v2 (From Manasi):
* Update logic for minor version to consider the dpcd value
and what supported by the HW platform
* Use DRM DSC config struct instead of intel_dp struct
* Move the DSC constants to DRM DSC header file
* Use u16, u8 where bigger data types not needed
* * Compute the DSC parameters as part of DSC compute config
since the computation can fail (Manasi)

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Co-developed-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/Makefile     |   3 +-
 drivers/gpu/drm/i915/intel_dp.c   |   7 +
 drivers/gpu/drm/i915/intel_drv.h  |   4 +
 drivers/gpu/drm/i915/intel_vdsc.c | 455 ++++++++++++++++++++++++++++++
 include/drm/drm_dp_helper.h       |   3 +
 5 files changed, 471 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 28c7d7884e88..a51a9ae0f496 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -156,7 +156,8 @@ i915-y += dvo_ch7017.o \
 	  intel_sdvo.o \
 	  intel_tv.o \
 	  vlv_dsi.o \
-	  vlv_dsi_pll.o
+	  vlv_dsi_pll.o \
+	  intel_vdsc.o
 
 # Post-mortem debug and GPU hang state capture
 i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1b10e27b3e2b..13891890d041 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2069,6 +2069,13 @@ static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 			return false;
 		}
 	}
+	if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) {
+		DRM_ERROR("Cannot compute valid DSC parameters for Input Bpp = %d"
+			  "Compressed BPP = %d\n",
+			  pipe_config->pipe_bpp,
+			  pipe_config->dsc_params.compressed_bpp);
+		return false;
+	}
 	pipe_config->dsc_params.compression_enable = true;
 	DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
 		      "Compressed Bpp = %d Slice Count = %d\n",
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 491872353cf0..3b57146766bb 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1853,6 +1853,10 @@ uint16_t intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count,
 uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
 				     int mode_hdisplay);
 
+/* intel_vdsc.c */
+int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
+				struct intel_crtc_state *pipe_config);
+
 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
 {
 	return ~((1 << lane_count) - 1) & 0xf;
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
new file mode 100644
index 000000000000..0a1918f2f643
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -0,0 +1,455 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Author: Gaurav K Singh <gaurav.k.singh@intel.com>
+ *         Manasi Navare <manasi.d.navare@intel.com>
+ */
+
+#include <drm/drmP.h>
+#include <drm/i915_drm.h>
+#include "i915_drv.h"
+#include "intel_drv.h"
+
+enum ROW_INDEX_BPP {
+	ROW_INDEX_6BPP = 0,
+	ROW_INDEX_8BPP,
+	ROW_INDEX_10BPP,
+	ROW_INDEX_12BPP,
+	ROW_INDEX_15BPP,
+	MAX_ROW_INDEX
+};
+
+enum COLUMN_INDEX_BPC {
+	COLUMN_INDEX_8BPC = 0,
+	COLUMN_INDEX_10BPC,
+	COLUMN_INDEX_12BPC,
+	COLUMN_INDEX_14BPC,
+	COLUMN_INDEX_16BPC,
+	MAX_COLUMN_INDEX
+};
+
+#define DSC_SUPPORTED_VERSION_MIN		1
+
+/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
+static u16 rc_buf_thresh[] = {
+	896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
+	7744, 7872, 8000, 8064
+};
+
+struct rc_parameters {
+	u16 initial_xmit_delay;
+	u8 first_line_bpg_offset;
+	u16 initial_offset;
+	u8 flatness_min_qp;
+	u8 flatness_max_qp;
+	u8 rc_quant_incr_limit0;
+	u8 rc_quant_incr_limit1;
+	struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
+};
+
+/*
+ * Selected Rate Control Related Parameter Recommended Values
+ * from DSC_v1.11 spec & C Model release: DSC_model_20161212
+ */
+static struct rc_parameters rc_params[][MAX_COLUMN_INDEX] = {
+{
+	/* 6BPP/8BPC */
+	{ 768, 15, 6144, 3, 13, 11, 11, {
+		{ 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
+		{ 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
+		{ 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
+		{ 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
+		}
+	},
+	/* 6BPP/10BPC */
+	{ 768, 15, 6144, 7, 17, 15, 15, {
+		{ 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
+		{ 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
+		{ 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
+		{ 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
+		{ 17, 18, -12 }
+		}
+	},
+	/* 6BPP/12BPC */
+	{ 768, 15, 6144, 11, 21, 19, 19, {
+		{ 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
+		{ 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
+		{ 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
+		{ 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
+		{ 21, 22, -12 }
+		}
+	},
+	/* 6BPP/14BPC */
+	{ 768, 15, 6144, 15, 25, 23, 27, {
+		{ 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
+		{ 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
+		{ 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
+		{ 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
+		{ 25, 26, -12 }
+		}
+	},
+	/* 6BPP/16BPC */
+	{ 768, 15, 6144, 19, 29, 27, 27, {
+		{ 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
+		{ 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
+		{ 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
+		{ 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
+		{ 29, 30, -12 }
+		}
+	},
+},
+{
+	/* 8BPP/8BPC */
+	{ 512, 12, 6144, 3, 12, 11, 11, {
+		{ 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+		{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+		{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
+		{ 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+		}
+	},
+	/* 8BPP/10BPC */
+	{ 512, 12, 6144, 7, 16, 15, 15, {
+		{ 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+		{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+		{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+		{ 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+		}
+	},
+	/* 8BPP/12BPC */
+	{ 512, 12, 6144, 11, 20, 19, 19, {
+		{ 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+		{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+		{ 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+		{ 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+		{ 21, 23, -12 }
+		}
+	},
+	/* 8BPP/14BPC */
+	{ 512, 12, 6144, 15, 24, 23, 23, {
+		{ 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
+		{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+		{ 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
+		{ 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
+		{ 24, 25, -12 }
+		}
+	},
+	/* 8BPP/16BPC */
+	{ 512, 12, 6144, 19, 28, 27, 27, {
+		{ 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
+		{ 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+		{ 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
+		{ 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
+		{ 28, 29, -12 }
+		}
+	},
+},
+{
+	/* 10BPP/8BPC */
+	{ 410, 15, 5632, 3, 12, 11, 11, {
+		{ 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+		{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+		{ 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
+		{ 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
+		}
+	},
+	/* 10BPP/10BPC */
+	{ 410, 15, 5632, 7, 16, 15, 15, {
+		{ 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+		{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+		{ 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
+		{ 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
+		}
+	},
+	/* 10BPP/12BPC */
+	{ 410, 15, 5632, 11, 20, 19, 19, {
+		{ 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
+		{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+		{ 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+		{ 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
+		{ 19, 20, -12 }
+		}
+	},
+	/* 10BPP/14BPC */
+	{ 410, 15, 5632, 15, 24, 23, 23, {
+		{ 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
+		{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+		{ 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
+		{ 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
+		{ 23, 24, -12 }
+		}
+	},
+	/* 10BPP/16BPC */
+	{ 410, 15, 5632, 19, 28, 27, 27, {
+		{ 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
+		{ 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+		{ 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
+		{ 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
+		{ 27, 28, -12 }
+		}
+	},
+},
+{
+	/* 12BPP/8BPC */
+	{ 341, 15, 2048, 3, 12, 11, 11, {
+		{ 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+		{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+		{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
+		{ 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+		}
+	},
+	/* 12BPP/10BPC */
+	{ 341, 15, 2048, 7, 16, 15, 15, {
+		{ 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+		{ 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+		{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+		{ 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+		}
+	},
+	/* 12BPP/12BPC */
+	{ 341, 15, 2048, 11, 20, 19, 19, {
+		{ 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+		{ 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+		{ 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+		{ 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+		{ 21, 23, -12 }
+		}
+	},
+	/* 12BPP/14BPC */
+	{ 341, 15, 2048, 15, 24, 23, 23, {
+		{ 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
+		{ 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+		{ 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
+		{ 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
+		{ 22, 23, -12 }
+		}
+	},
+	/* 12BPP/16BPC */
+	{ 341, 15, 2048, 19, 28, 27, 27, {
+		{ 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
+		{ 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+		{ 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
+		{ 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
+		{ 26, 27, -12 }
+		}
+	},
+},
+{
+	/* 15BPP/8BPC */
+	{ 273, 15, 2048, 3, 12, 11, 11, {
+		{ 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
+		{ 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
+		{ 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
+		{ 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
+		}
+	},
+	/* 15BPP/10BPC */
+	{ 273, 15, 2048, 7, 16, 15, 15, {
+		{ 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
+		{ 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
+		{ 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
+		{ 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
+		}
+	},
+	/* 15BPP/12BPC */
+	{ 273, 15, 2048, 11, 20, 19, 19, {
+		{ 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
+		{ 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
+		{ 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
+		{ 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
+		{ 16, 17, -12 }
+		}
+	},
+	/* 15BPP/14BPC */
+	{ 273, 15, 2048, 15, 24, 23, 23, {
+		{ 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
+		{ 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
+		{ 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
+		{ 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
+		{ 20, 21, -12 }
+		}
+	},
+	/* 15BPP/16BPC */
+	{ 273, 15, 2048, 19, 28, 27, 27, {
+		{ 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
+		{ 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
+		{ 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
+		{ 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
+		{ 24, 25, -12 }
+		}
+	}
+}
+};
+
+static int get_row_index_for_rc_params(u16 compressed_bpp)
+{
+	switch (compressed_bpp) {
+	case 6:
+		return ROW_INDEX_6BPP;
+	case 8:
+		return ROW_INDEX_8BPP;
+	case 10:
+		return ROW_INDEX_10BPP;
+	case 12:
+		return ROW_INDEX_12BPP;
+	case 15:
+		return ROW_INDEX_15BPP;
+	default:
+		return -EINVAL;
+	}
+}
+
+static int get_column_index_for_rc_params(u8 bits_per_component)
+{
+	switch (bits_per_component) {
+	case 8:
+		return COLUMN_INDEX_8BPC;
+	case 10:
+		return COLUMN_INDEX_10BPC;
+	case 12:
+		return COLUMN_INDEX_12BPC;
+	case 14:
+		return COLUMN_INDEX_14BPC;
+	case 16:
+		return COLUMN_INDEX_16BPC;
+	default:
+		return -EINVAL;
+	}
+}
+
+int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
+				struct intel_crtc_state *pipe_config)
+{
+	struct drm_dsc_config *vdsc_cfg = &pipe_config->dp_dsc_cfg;
+	u16 compressed_bpp = pipe_config->dsc_params.compressed_bpp;
+	u8 i = 0;
+	u8 row_index = 0;
+	u8 column_index = 0;
+	u8 line_buf_depth = 0;
+
+	vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay;
+	vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay;
+	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
+					     pipe_config->dsc_params.slice_count);
+	/*
+	 * Slice Height of 8 works for all currently available panels. So start
+	 * with that if pic_height is an integral multiple of 8.
+	 * Eventually add logic to try multiple slice heights.
+	 */
+	if (vdsc_cfg->pic_height % 8 == 0)
+		vdsc_cfg->slice_height = 8;
+	else if (vdsc_cfg->pic_height % 4 == 0)
+		vdsc_cfg->slice_height = 4;
+	else
+		vdsc_cfg->slice_height = 2;
+
+	/* Values filled from DSC Sink DPCD */
+	vdsc_cfg->dsc_version_major =
+		(intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
+		 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
+	vdsc_cfg->dsc_version_minor =
+		min(DSC_SUPPORTED_VERSION_MIN,
+		    (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
+		     DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
+
+	vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
+		DP_DSC_RGB;
+
+	line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
+	if (!line_buf_depth) {
+		DRM_DEBUG_KMS("DSC Sink Line Buffer Depth invalid\n");
+		return -EINVAL;
+	}
+	if (vdsc_cfg->dsc_version_minor == 2)
+		vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
+			DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
+	else
+		vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
+			DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
+
+	/* Gen 11 does not support YCbCr */
+	vdsc_cfg->enable422 = false;
+	/* Gen 11 does not support VBR */
+	vdsc_cfg->vbr_enable = false;
+	vdsc_cfg->block_pred_enable =
+			intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
+		DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
+
+	/* Gen 11 only supports integral values of bpp */
+	vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
+	vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
+
+	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
+		/*
+		 * six 0s are appended to the lsb of each threshold value
+		 * internally in h/w.
+		 * Only 8 bits are allowed for programming RcBufThreshold
+		 */
+		vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
+	}
+
+	/*
+	 * For 6bpp, RC Buffer threshold 12 and 13 need a different value
+	 * as per C Model
+	 */
+	if (compressed_bpp == 6) {
+		vdsc_cfg->rc_buf_thresh[12] = 0x7C;
+		vdsc_cfg->rc_buf_thresh[13] = 0x7D;
+	}
+
+	row_index = get_row_index_for_rc_params(compressed_bpp);
+	column_index =
+		get_column_index_for_rc_params(vdsc_cfg->bits_per_component);
+
+	if (row_index < 0 || column_index < 0)
+		return -EINVAL;
+
+	vdsc_cfg->first_line_bpg_offset =
+		rc_params[row_index][column_index].first_line_bpg_offset;
+	vdsc_cfg->initial_xmit_delay =
+		rc_params[row_index][column_index].initial_xmit_delay;
+	vdsc_cfg->initial_offset =
+		rc_params[row_index][column_index].initial_offset;
+	vdsc_cfg->flatness_min_qp =
+		rc_params[row_index][column_index].flatness_min_qp;
+	vdsc_cfg->flatness_max_qp =
+		rc_params[row_index][column_index].flatness_max_qp;
+	vdsc_cfg->rc_quant_incr_limit0 =
+		rc_params[row_index][column_index].rc_quant_incr_limit0;
+	vdsc_cfg->rc_quant_incr_limit1 =
+		rc_params[row_index][column_index].rc_quant_incr_limit1;
+
+	for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
+		vdsc_cfg->rc_range_params[i].range_min_qp =
+			rc_params[row_index][column_index].rc_range_params[i].range_min_qp;
+		vdsc_cfg->rc_range_params[i].range_max_qp =
+			rc_params[row_index][column_index].rc_range_params[i].range_max_qp;
+		/*
+		 * Range BPG Offset uses 2's complement and is only a 6 bits. So
+		 * mask it to get only 6 bits.
+		 */
+		vdsc_cfg->rc_range_params[i].range_bpg_offset =
+			rc_params[row_index][column_index].rc_range_params[i].range_bpg_offset &
+			DSC_RANGE_BPG_OFFSET_MASK;
+	}
+
+	/*
+	 * BitsPerComponent value determines mux_word_size:
+	 * When BitsPerComponent is 12bpc, muxWordSize will be equal to 64 bits
+	 * When BitsPerComponent is 8 or 10bpc, muxWordSize will be equal to
+	 * 48 bits
+	 */
+	if (vdsc_cfg->bits_per_component == 8 ||
+	    vdsc_cfg->bits_per_component == 10)
+		vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
+	else if (vdsc_cfg->bits_per_component == 12)
+		vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
+
+	/* RC_MODEL_SIZE is a constant across all configurations */
+	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
+	/* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */
+	vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
+		(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
+
+	return 0;
+}
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 0fba8d2198a4..dab994e2f04e 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -187,6 +187,9 @@
 
 #define DP_GUID				    0x030   /* 1.2 */
 
+#define DP_DSC_RC_PIXELS_PER_GROUP		3
+#define DP_DSC_SCALE_DECREMENT_INTERVAL_MAX	4095
+
 #define DP_DSC_SUPPORT                      0x060   /* DP 1.4 */
 # define DP_DSC_DECOMPRESSION_IS_SUPPORTED  (1 << 0)
 
-- 
2.18.0

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Re: [PATCH v7 09/19] drm/i915/dsc: Define & Compute VESA DSC params

[Ville Syrjälä]

On Thu, Nov 01, 2018 at 11:46:49PM -0700, Manasi Navare wrote:
> From: Gaurav K Singh <gaurav.k.singh@intel.com>
> 
> This patches does the following:
> 
> 1. This patch defines all the DSC parameters as per the VESA
> DSC specification. These are stored in the encoder and used
> to compute the PPS parameters to be sent to the Sink.
> 2. Compute all the DSC parameters which are derived from DSC
> state of intel_crtc_state.
> 3. Compute all parameters that are VESA DSC specific
> 
> This computation happens in the atomic check phase during
> compute_config() to validate if display stream compression
> can be enabled for the requested mode.
> 
> v7: (From Manasi)
> * Dont use signed int for rc_range_params (Manasi)
> * Mask the range_bpg_offset to use only 6 bits
> * Add SPDX identifier (Chris Wilson)
> v6 (From Manasi):
> * Add a check for line_buf_depth return value (Anusha)
> * Remove DRM DSC constants to different patch (Manasi)
> v5 (From Manasi):
> * Add logic to limit the max line buf depth for DSC 1.1 to 13
> as per DSC 1.1 spec
> * Fix dim checkpatch warnings/checks
> 
> v4 (From Gaurav):
> * Rebase on latest drm tip
> * rename variable name(Manasi)
> * Populate linebuf_depth variable(Manasi)
> 
> v3 (From Gaurav):
> * Rebase my previous patches on top of Manasi's latest patch
> series
> * Using >>n rather than /2^n (Manasi)
> * Change the commit message to explain what the patch is doing(Gaurav)
> 
> Fixed review comments from Ville:
> * Don't use macro TWOS_COMPLEMENT
> * Mention in comment about the source of RC params
> * Return directly from case statements
> * Using single asssignment for assigning rc_range_params
> * Using <<n rather than *2^n and removing the comments
> about the fixed point numbers
> 
> v2 (From Manasi):
> * Update logic for minor version to consider the dpcd value
> and what supported by the HW platform
> * Use DRM DSC config struct instead of intel_dp struct
> * Move the DSC constants to DRM DSC header file
> * Use u16, u8 where bigger data types not needed
> * * Compute the DSC parameters as part of DSC compute config
> since the computation can fail (Manasi)
> 
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Co-developed-by: Manasi Navare <manasi.d.navare@intel.com>
> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/Makefile     |   3 +-
>  drivers/gpu/drm/i915/intel_dp.c   |   7 +
>  drivers/gpu/drm/i915/intel_drv.h  |   4 +
>  drivers/gpu/drm/i915/intel_vdsc.c | 455 ++++++++++++++++++++++++++++++
>  include/drm/drm_dp_helper.h       |   3 +
>  5 files changed, 471 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c
> 
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 28c7d7884e88..a51a9ae0f496 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -156,7 +156,8 @@ i915-y += dvo_ch7017.o \
>  	  intel_sdvo.o \
>  	  intel_tv.o \
>  	  vlv_dsi.o \
> -	  vlv_dsi_pll.o
> +	  vlv_dsi_pll.o \
> +	  intel_vdsc.o
>  
>  # Post-mortem debug and GPU hang state capture
>  i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 1b10e27b3e2b..13891890d041 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2069,6 +2069,13 @@ static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  			return false;
>  		}
>  	}
> +	if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) {
> +		DRM_ERROR("Cannot compute valid DSC parameters for Input Bpp = %d"

Is this something that can't happen ever? If not this needs to be 
DRM_DEBUG_KMS().

> +			  "Compressed BPP = %d\n",
> +			  pipe_config->pipe_bpp,
> +			  pipe_config->dsc_params.compressed_bpp);
> +		return false;
> +	}
>  	pipe_config->dsc_params.compression_enable = true;
>  	DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
>  		      "Compressed Bpp = %d Slice Count = %d\n",
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 491872353cf0..3b57146766bb 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1853,6 +1853,10 @@ uint16_t intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count,
>  uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
>  				     int mode_hdisplay);
>  
> +/* intel_vdsc.c */
> +int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
> +				struct intel_crtc_state *pipe_config);
> +
>  static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
>  {
>  	return ~((1 << lane_count) - 1) & 0xf;
> diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
> new file mode 100644
> index 000000000000..0a1918f2f643
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_vdsc.c
> @@ -0,0 +1,455 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2018 Intel Corporation
> + *
> + * Author: Gaurav K Singh <gaurav.k.singh@intel.com>
> + *         Manasi Navare <manasi.d.navare@intel.com>
> + */
> +
> +#include <drm/drmP.h>
> +#include <drm/i915_drm.h>
> +#include "i915_drv.h"
> +#include "intel_drv.h"
> +
> +enum ROW_INDEX_BPP {
> +	ROW_INDEX_6BPP = 0,
> +	ROW_INDEX_8BPP,
> +	ROW_INDEX_10BPP,
> +	ROW_INDEX_12BPP,
> +	ROW_INDEX_15BPP,
> +	MAX_ROW_INDEX
> +};
> +
> +enum COLUMN_INDEX_BPC {
> +	COLUMN_INDEX_8BPC = 0,
> +	COLUMN_INDEX_10BPC,
> +	COLUMN_INDEX_12BPC,
> +	COLUMN_INDEX_14BPC,
> +	COLUMN_INDEX_16BPC,
> +	MAX_COLUMN_INDEX
> +};
> +
> +#define DSC_SUPPORTED_VERSION_MIN		1
> +
> +/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
> +static u16 rc_buf_thresh[] = {
> +	896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
> +	7744, 7872, 8000, 8064
> +};
> +
> +struct rc_parameters {
> +	u16 initial_xmit_delay;
> +	u8 first_line_bpg_offset;
> +	u16 initial_offset;
> +	u8 flatness_min_qp;
> +	u8 flatness_max_qp;
> +	u8 rc_quant_incr_limit0;
> +	u8 rc_quant_incr_limit1;
> +	struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
> +};
> +
> +/*
> + * Selected Rate Control Related Parameter Recommended Values
> + * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> + */
> +static struct rc_parameters rc_params[][MAX_COLUMN_INDEX] = {
> +{
> +	/* 6BPP/8BPC */
> +	{ 768, 15, 6144, 3, 13, 11, 11, {
> +		{ 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
> +		{ 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
> +		{ 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
> +		{ 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
> +		}
> +	},
> +	/* 6BPP/10BPC */
> +	{ 768, 15, 6144, 7, 17, 15, 15, {
> +		{ 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
> +		{ 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
> +		{ 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
> +		{ 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
> +		{ 17, 18, -12 }
> +		}
> +	},
> +	/* 6BPP/12BPC */
> +	{ 768, 15, 6144, 11, 21, 19, 19, {
> +		{ 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
> +		{ 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
> +		{ 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
> +		{ 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
> +		{ 21, 22, -12 }
> +		}
> +	},
> +	/* 6BPP/14BPC */
> +	{ 768, 15, 6144, 15, 25, 23, 27, {
> +		{ 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
> +		{ 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
> +		{ 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
> +		{ 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
> +		{ 25, 26, -12 }
> +		}
> +	},
> +	/* 6BPP/16BPC */
> +	{ 768, 15, 6144, 19, 29, 27, 27, {
> +		{ 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
> +		{ 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
> +		{ 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
> +		{ 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
> +		{ 29, 30, -12 }
> +		}
> +	},
> +},
> +{
> +	/* 8BPP/8BPC */
> +	{ 512, 12, 6144, 3, 12, 11, 11, {
> +		{ 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> +		{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> +		{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> +		{ 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> +		}
> +	},
> +	/* 8BPP/10BPC */
> +	{ 512, 12, 6144, 7, 16, 15, 15, {
> +		{ 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> +		{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> +		{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> +		{ 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> +		}
> +	},
> +	/* 8BPP/12BPC */
> +	{ 512, 12, 6144, 11, 20, 19, 19, {
> +		{ 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> +		{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> +		{ 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> +		{ 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> +		{ 21, 23, -12 }
> +		}
> +	},
> +	/* 8BPP/14BPC */
> +	{ 512, 12, 6144, 15, 24, 23, 23, {
> +		{ 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
> +		{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> +		{ 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
> +		{ 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
> +		{ 24, 25, -12 }
> +		}
> +	},
> +	/* 8BPP/16BPC */
> +	{ 512, 12, 6144, 19, 28, 27, 27, {
> +		{ 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
> +		{ 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> +		{ 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
> +		{ 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
> +		{ 28, 29, -12 }
> +		}
> +	},
> +},
> +{
> +	/* 10BPP/8BPC */
> +	{ 410, 15, 5632, 3, 12, 11, 11, {
> +		{ 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
> +		{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> +		{ 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
> +		{ 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
> +		}
> +	},
> +	/* 10BPP/10BPC */
> +	{ 410, 15, 5632, 7, 16, 15, 15, {
> +		{ 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
> +		{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> +		{ 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
> +		{ 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
> +		}
> +	},
> +	/* 10BPP/12BPC */
> +	{ 410, 15, 5632, 11, 20, 19, 19, {
> +		{ 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
> +		{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> +		{ 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
> +		{ 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
> +		{ 19, 20, -12 }
> +		}
> +	},
> +	/* 10BPP/14BPC */
> +	{ 410, 15, 5632, 15, 24, 23, 23, {
> +		{ 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
> +		{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> +		{ 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
> +		{ 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
> +		{ 23, 24, -12 }
> +		}
> +	},
> +	/* 10BPP/16BPC */
> +	{ 410, 15, 5632, 19, 28, 27, 27, {
> +		{ 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
> +		{ 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> +		{ 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
> +		{ 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
> +		{ 27, 28, -12 }
> +		}
> +	},
> +},
> +{
> +	/* 12BPP/8BPC */
> +	{ 341, 15, 2048, 3, 12, 11, 11, {
> +		{ 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> +		{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> +		{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> +		{ 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> +		}
> +	},
> +	/* 12BPP/10BPC */
> +	{ 341, 15, 2048, 7, 16, 15, 15, {
> +		{ 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> +		{ 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> +		{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> +		{ 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> +		}
> +	},
> +	/* 12BPP/12BPC */
> +	{ 341, 15, 2048, 11, 20, 19, 19, {
> +		{ 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> +		{ 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> +		{ 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> +		{ 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> +		{ 21, 23, -12 }
> +		}
> +	},
> +	/* 12BPP/14BPC */
> +	{ 341, 15, 2048, 15, 24, 23, 23, {
> +		{ 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
> +		{ 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> +		{ 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
> +		{ 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
> +		{ 22, 23, -12 }
> +		}
> +	},
> +	/* 12BPP/16BPC */
> +	{ 341, 15, 2048, 19, 28, 27, 27, {
> +		{ 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
> +		{ 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> +		{ 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
> +		{ 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
> +		{ 26, 27, -12 }
> +		}
> +	},
> +},
> +{
> +	/* 15BPP/8BPC */
> +	{ 273, 15, 2048, 3, 12, 11, 11, {
> +		{ 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
> +		{ 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
> +		{ 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
> +		{ 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
> +		}
> +	},
> +	/* 15BPP/10BPC */
> +	{ 273, 15, 2048, 7, 16, 15, 15, {
> +		{ 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
> +		{ 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
> +		{ 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
> +		{ 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
> +		}
> +	},
> +	/* 15BPP/12BPC */
> +	{ 273, 15, 2048, 11, 20, 19, 19, {
> +		{ 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
> +		{ 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
> +		{ 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
> +		{ 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
> +		{ 16, 17, -12 }
> +		}
> +	},
> +	/* 15BPP/14BPC */
> +	{ 273, 15, 2048, 15, 24, 23, 23, {
> +		{ 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
> +		{ 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
> +		{ 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
> +		{ 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
> +		{ 20, 21, -12 }
> +		}
> +	},
> +	/* 15BPP/16BPC */
> +	{ 273, 15, 2048, 19, 28, 27, 27, {
> +		{ 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
> +		{ 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
> +		{ 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
> +		{ 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
> +		{ 24, 25, -12 }
> +		}
> +	}
> +}
> +};
> +
> +static int get_row_index_for_rc_params(u16 compressed_bpp)
> +{
> +	switch (compressed_bpp) {
> +	case 6:
> +		return ROW_INDEX_6BPP;
> +	case 8:
> +		return ROW_INDEX_8BPP;
> +	case 10:
> +		return ROW_INDEX_10BPP;
> +	case 12:
> +		return ROW_INDEX_12BPP;
> +	case 15:
> +		return ROW_INDEX_15BPP;
> +	default:
> +		return -EINVAL;
> +	}
> +}
> +
> +static int get_column_index_for_rc_params(u8 bits_per_component)
> +{
> +	switch (bits_per_component) {
> +	case 8:
> +		return COLUMN_INDEX_8BPC;
> +	case 10:
> +		return COLUMN_INDEX_10BPC;
> +	case 12:
> +		return COLUMN_INDEX_12BPC;
> +	case 14:
> +		return COLUMN_INDEX_14BPC;
> +	case 16:
> +		return COLUMN_INDEX_16BPC;
> +	default:
> +		return -EINVAL;
> +	}
> +}
> +
> +int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
> +				struct intel_crtc_state *pipe_config)
> +{
> +	struct drm_dsc_config *vdsc_cfg = &pipe_config->dp_dsc_cfg;
> +	u16 compressed_bpp = pipe_config->dsc_params.compressed_bpp;
> +	u8 i = 0;
> +	u8 row_index = 0;
> +	u8 column_index = 0;
> +	u8 line_buf_depth = 0;
> +
> +	vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay;
> +	vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay;
> +	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
> +					     pipe_config->dsc_params.slice_count);
> +	/*
> +	 * Slice Height of 8 works for all currently available panels. So start
> +	 * with that if pic_height is an integral multiple of 8.
> +	 * Eventually add logic to try multiple slice heights.
> +	 */
> +	if (vdsc_cfg->pic_height % 8 == 0)
> +		vdsc_cfg->slice_height = 8;
> +	else if (vdsc_cfg->pic_height % 4 == 0)
> +		vdsc_cfg->slice_height = 4;
> +	else
> +		vdsc_cfg->slice_height = 2;
> +
> +	/* Values filled from DSC Sink DPCD */
> +	vdsc_cfg->dsc_version_major =
> +		(intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
> +		 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
> +	vdsc_cfg->dsc_version_minor =
> +		min(DSC_SUPPORTED_VERSION_MIN,
> +		    (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
> +		     DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
> +
> +	vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
> +		DP_DSC_RGB;
> +
> +	line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
> +	if (!line_buf_depth) {
> +		DRM_DEBUG_KMS("DSC Sink Line Buffer Depth invalid\n");
> +		return -EINVAL;
> +	}
> +	if (vdsc_cfg->dsc_version_minor == 2)
> +		vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
> +			DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
> +	else
> +		vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
> +			DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
> +
> +	/* Gen 11 does not support YCbCr */
> +	vdsc_cfg->enable422 = false;
> +	/* Gen 11 does not support VBR */
> +	vdsc_cfg->vbr_enable = false;
> +	vdsc_cfg->block_pred_enable =
> +			intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
> +		DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
> +
> +	/* Gen 11 only supports integral values of bpp */
> +	vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
> +	vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
> +
> +	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
> +		/*
> +		 * six 0s are appended to the lsb of each threshold value
> +		 * internally in h/w.
> +		 * Only 8 bits are allowed for programming RcBufThreshold
> +		 */
> +		vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
> +	}
> +
> +	/*
> +	 * For 6bpp, RC Buffer threshold 12 and 13 need a different value
> +	 * as per C Model
> +	 */
> +	if (compressed_bpp == 6) {
> +		vdsc_cfg->rc_buf_thresh[12] = 0x7C;
> +		vdsc_cfg->rc_buf_thresh[13] = 0x7D;
> +	}
> +
> +	row_index = get_row_index_for_rc_params(compressed_bpp);
> +	column_index =
> +		get_column_index_for_rc_params(vdsc_cfg->bits_per_component);
> +
> +	if (row_index < 0 || column_index < 0)
> +		return -EINVAL;
> +
> +	vdsc_cfg->first_line_bpg_offset =
> +		rc_params[row_index][column_index].first_line_bpg_offset;
> +	vdsc_cfg->initial_xmit_delay =
> +		rc_params[row_index][column_index].initial_xmit_delay;
> +	vdsc_cfg->initial_offset =
> +		rc_params[row_index][column_index].initial_offset;
> +	vdsc_cfg->flatness_min_qp =
> +		rc_params[row_index][column_index].flatness_min_qp;
> +	vdsc_cfg->flatness_max_qp =
> +		rc_params[row_index][column_index].flatness_max_qp;
> +	vdsc_cfg->rc_quant_incr_limit0 =
> +		rc_params[row_index][column_index].rc_quant_incr_limit0;
> +	vdsc_cfg->rc_quant_incr_limit1 =
> +		rc_params[row_index][column_index].rc_quant_incr_limit1;
> +
> +	for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
> +		vdsc_cfg->rc_range_params[i].range_min_qp =
> +			rc_params[row_index][column_index].rc_range_params[i].range_min_qp;
> +		vdsc_cfg->rc_range_params[i].range_max_qp =
> +			rc_params[row_index][column_index].rc_range_params[i].range_max_qp;
> +		/*
> +		 * Range BPG Offset uses 2's complement and is only a 6 bits. So
> +		 * mask it to get only 6 bits.
> +		 */
> +		vdsc_cfg->rc_range_params[i].range_bpg_offset =
> +			rc_params[row_index][column_index].rc_range_params[i].range_bpg_offset &
> +			DSC_RANGE_BPG_OFFSET_MASK;
> +	}
> +
> +	/*
> +	 * BitsPerComponent value determines mux_word_size:
> +	 * When BitsPerComponent is 12bpc, muxWordSize will be equal to 64 bits
> +	 * When BitsPerComponent is 8 or 10bpc, muxWordSize will be equal to
> +	 * 48 bits
> +	 */
> +	if (vdsc_cfg->bits_per_component == 8 ||
> +	    vdsc_cfg->bits_per_component == 10)
> +		vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
> +	else if (vdsc_cfg->bits_per_component == 12)
> +		vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
> +
> +	/* RC_MODEL_SIZE is a constant across all configurations */
> +	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
> +	/* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */
> +	vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
> +		(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
> +
> +	return 0;
> +}
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 0fba8d2198a4..dab994e2f04e 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -187,6 +187,9 @@
>  
>  #define DP_GUID				    0x030   /* 1.2 */
>  
> +#define DP_DSC_RC_PIXELS_PER_GROUP		3
> +#define DP_DSC_SCALE_DECREMENT_INTERVAL_MAX	4095
> +
>  #define DP_DSC_SUPPORT                      0x060   /* DP 1.4 */
>  # define DP_DSC_DECOMPRESSION_IS_SUPPORTED  (1 << 0)
>  
> -- 
> 2.18.0

-- 
Ville Syrjälä
Intel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH v7 10/19] drm/i915/dsc: Compute Rate Control parameters for DSC

[Manasi Navare]

From: Gaurav K Singh <gaurav.k.singh@intel.com>

This computation of RC params happens in the atomic commit phase
during compute_config() to validate if display stream compression
can be enabled for the requested mode.

v6 (From Manasi):
* Use 9 instead of 0x9 for consistency (Anusha)

v5 (From Manasi):
* Fix dim checkpatch warnings/checks
v4(From Gaurav):
* No change.Rebase on drm-tip

v3 (From Gaurav):
* Rebase on top of Manasi's latest series
* Return -ve value in case of failure scenarios (Manasi)

Fix review comments from Ville:
* Remove unnecessary comments
* Remove unnecessary paranthesis
* Add comments for few RC params calculations

v2 (From Manasi):
* Rebase Gaurav's patch from intel-gfx to gfx-internal
* Use struct drm_dsc_cfg instead of struct intel_dp
as a parameter

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/intel_vdsc.c | 127 ++++++++++++++++++++++++++++++
 1 file changed, 127 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
index 0a1918f2f643..b93cb32026fa 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -317,6 +317,130 @@ static int get_column_index_for_rc_params(u8 bits_per_component)
 	}
 }
 
+static int intel_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
+{
+	unsigned long groups_per_line = 0;
+	unsigned long groups_total = 0;
+	unsigned long num_extra_mux_bits = 0;
+	unsigned long slice_bits = 0;
+	unsigned long hrd_delay = 0;
+	unsigned long final_scale = 0;
+	unsigned long rbs_min = 0;
+
+	/* Number of groups used to code each line of a slice */
+	groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
+				       DSC_RC_PIXELS_PER_GROUP);
+
+	/* chunksize in Bytes */
+	vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
+						  vdsc_cfg->bits_per_pixel,
+						  (8 * 16));
+
+	if (vdsc_cfg->convert_rgb)
+		num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
+					  (4 * vdsc_cfg->bits_per_component + 4)
+					  - 2);
+	else
+		num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
+			(4 * vdsc_cfg->bits_per_component + 4) +
+			2 * (4 * vdsc_cfg->bits_per_component) - 2;
+	/* Number of bits in one Slice */
+	slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
+
+	while ((num_extra_mux_bits > 0) &&
+	       ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
+		num_extra_mux_bits--;
+
+	if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
+		vdsc_cfg->initial_scale_value = groups_per_line + 8;
+
+	/* scale_decrement_interval calculation according to DSC spec 1.11 */
+	if (vdsc_cfg->initial_scale_value > 8)
+		vdsc_cfg->scale_decrement_interval = groups_per_line /
+			(vdsc_cfg->initial_scale_value - 8);
+	else
+		vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX;
+
+	vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
+		(vdsc_cfg->initial_xmit_delay *
+		 vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
+
+	if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
+		DRM_ERROR("FinalOfs < RcModelSze for this InitialXmitDelay\n");
+		return -EINVAL;
+	}
+
+	final_scale = (vdsc_cfg->rc_model_size * 8) /
+		(vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
+	if (vdsc_cfg->slice_height > 1)
+		/*
+		 * NflBpgOffset is 16 bit value with 11 fractional bits
+		 * hence we multiply by 2^11 for preserving the
+		 * fractional part
+		 */
+		vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
+							(vdsc_cfg->slice_height - 1));
+	else
+		vdsc_cfg->nfl_bpg_offset = 0;
+
+	/* 2^16 - 1 */
+	if (vdsc_cfg->nfl_bpg_offset > 65535) {
+		DRM_ERROR("NflBpgOffset is too large for this slice height\n");
+		return -EINVAL;
+	}
+
+	/* Number of groups used to code the entire slice */
+	groups_total = groups_per_line * vdsc_cfg->slice_height;
+
+	/* slice_bpg_offset is 16 bit value with 11 fractional bits */
+	vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
+						    vdsc_cfg->initial_offset +
+						    num_extra_mux_bits) << 11),
+						  groups_total);
+
+	if (final_scale > 9) {
+		/*
+		 * ScaleIncrementInterval =
+		 * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125))
+		 * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value,
+		 * we need divide by 2^11 from pstDscCfg values
+		 */
+		vdsc_cfg->scale_increment_interval =
+				(vdsc_cfg->final_offset * (1 << 11)) /
+				((vdsc_cfg->nfl_bpg_offset +
+				vdsc_cfg->slice_bpg_offset)*
+				(final_scale - 9));
+	} else {
+		/*
+		 * If finalScaleValue is less than or equal to 9, a value of 0 should
+		 * be used to disable the scale increment at the end of the slice
+		 */
+		vdsc_cfg->scale_increment_interval = 0;
+	}
+
+	if (vdsc_cfg->scale_increment_interval > 65535) {
+		DRM_ERROR("ScaleIncrementInterval is large for slice height\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * DSC spec mentions that bits_per_pixel specifies the target
+	 * bits/pixel (bpp) rate that is used by the encoder,
+	 * in steps of 1/16 of a bit per pixel
+	 */
+	rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
+		DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
+			     vdsc_cfg->bits_per_pixel, 16) +
+		groups_per_line * vdsc_cfg->first_line_bpg_offset;
+
+	hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
+	vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
+	vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay;
+
+	return 0;
+}
+
+
 int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
 				struct intel_crtc_state *pipe_config)
 {
@@ -451,5 +575,8 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
 	vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
 		(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
 
+	if (intel_compute_rc_parameters(vdsc_cfg) < 0)
+		return -1;
+
 	return 0;
 }
-- 
2.18.0

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Re: [PATCH v7 10/19] drm/i915/dsc: Compute Rate Control parameters for DSC

[Ville Syrjälä]

On Thu, Nov 01, 2018 at 11:46:50PM -0700, Manasi Navare wrote:
> From: Gaurav K Singh <gaurav.k.singh@intel.com>
> 
> This computation of RC params happens in the atomic commit phase
> during compute_config() to validate if display stream compression
> can be enabled for the requested mode.
> 
> v6 (From Manasi):
> * Use 9 instead of 0x9 for consistency (Anusha)
> 
> v5 (From Manasi):
> * Fix dim checkpatch warnings/checks
> v4(From Gaurav):
> * No change.Rebase on drm-tip
> 
> v3 (From Gaurav):
> * Rebase on top of Manasi's latest series
> * Return -ve value in case of failure scenarios (Manasi)
> 
> Fix review comments from Ville:
> * Remove unnecessary comments
> * Remove unnecessary paranthesis
> * Add comments for few RC params calculations
> 
> v2 (From Manasi):
> * Rebase Gaurav's patch from intel-gfx to gfx-internal
> * Use struct drm_dsc_cfg instead of struct intel_dp
> as a parameter
> 
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_vdsc.c | 127 ++++++++++++++++++++++++++++++
>  1 file changed, 127 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
> index 0a1918f2f643..b93cb32026fa 100644
> --- a/drivers/gpu/drm/i915/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/intel_vdsc.c
> @@ -317,6 +317,130 @@ static int get_column_index_for_rc_params(u8 bits_per_component)
>  	}
>  }
>  
> +static int intel_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
> +{
> +	unsigned long groups_per_line = 0;
> +	unsigned long groups_total = 0;
> +	unsigned long num_extra_mux_bits = 0;
> +	unsigned long slice_bits = 0;
> +	unsigned long hrd_delay = 0;
> +	unsigned long final_scale = 0;
> +	unsigned long rbs_min = 0;
> +
> +	/* Number of groups used to code each line of a slice */
> +	groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
> +				       DSC_RC_PIXELS_PER_GROUP);
> +
> +	/* chunksize in Bytes */
> +	vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
> +						  vdsc_cfg->bits_per_pixel,
> +						  (8 * 16));
> +
> +	if (vdsc_cfg->convert_rgb)
> +		num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
> +					  (4 * vdsc_cfg->bits_per_component + 4)
> +					  - 2);
> +	else
> +		num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
> +			(4 * vdsc_cfg->bits_per_component + 4) +
> +			2 * (4 * vdsc_cfg->bits_per_component) - 2;
> +	/* Number of bits in one Slice */
> +	slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
> +
> +	while ((num_extra_mux_bits > 0) &&
> +	       ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
> +		num_extra_mux_bits--;
> +
> +	if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
> +		vdsc_cfg->initial_scale_value = groups_per_line + 8;
> +
> +	/* scale_decrement_interval calculation according to DSC spec 1.11 */
> +	if (vdsc_cfg->initial_scale_value > 8)
> +		vdsc_cfg->scale_decrement_interval = groups_per_line /
> +			(vdsc_cfg->initial_scale_value - 8);
> +	else
> +		vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX;
> +
> +	vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
> +		(vdsc_cfg->initial_xmit_delay *
> +		 vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
> +
> +	if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
> +		DRM_ERROR("FinalOfs < RcModelSze for this InitialXmitDelay\n");

More DRM_ERROR()s. Can the user trigger these?

> +		return -EINVAL;
> +	}
> +
> +	final_scale = (vdsc_cfg->rc_model_size * 8) /
> +		(vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
> +	if (vdsc_cfg->slice_height > 1)
> +		/*
> +		 * NflBpgOffset is 16 bit value with 11 fractional bits
> +		 * hence we multiply by 2^11 for preserving the
> +		 * fractional part
> +		 */
> +		vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
> +							(vdsc_cfg->slice_height - 1));
> +	else
> +		vdsc_cfg->nfl_bpg_offset = 0;
> +
> +	/* 2^16 - 1 */
> +	if (vdsc_cfg->nfl_bpg_offset > 65535) {
> +		DRM_ERROR("NflBpgOffset is too large for this slice height\n");
> +		return -EINVAL;
> +	}
> +
> +	/* Number of groups used to code the entire slice */
> +	groups_total = groups_per_line * vdsc_cfg->slice_height;
> +
> +	/* slice_bpg_offset is 16 bit value with 11 fractional bits */
> +	vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
> +						    vdsc_cfg->initial_offset +
> +						    num_extra_mux_bits) << 11),
> +						  groups_total);
> +
> +	if (final_scale > 9) {
> +		/*
> +		 * ScaleIncrementInterval =
> +		 * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125))
> +		 * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value,
> +		 * we need divide by 2^11 from pstDscCfg values
> +		 */
> +		vdsc_cfg->scale_increment_interval =
> +				(vdsc_cfg->final_offset * (1 << 11)) /
> +				((vdsc_cfg->nfl_bpg_offset +
> +				vdsc_cfg->slice_bpg_offset)*
> +				(final_scale - 9));
> +	} else {
> +		/*
> +		 * If finalScaleValue is less than or equal to 9, a value of 0 should
> +		 * be used to disable the scale increment at the end of the slice
> +		 */
> +		vdsc_cfg->scale_increment_interval = 0;
> +	}
> +
> +	if (vdsc_cfg->scale_increment_interval > 65535) {
> +		DRM_ERROR("ScaleIncrementInterval is large for slice height\n");
> +		return -EINVAL;
> +	}
> +
> +	/*
> +	 * DSC spec mentions that bits_per_pixel specifies the target
> +	 * bits/pixel (bpp) rate that is used by the encoder,
> +	 * in steps of 1/16 of a bit per pixel
> +	 */
> +	rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
> +		DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
> +			     vdsc_cfg->bits_per_pixel, 16) +
> +		groups_per_line * vdsc_cfg->first_line_bpg_offset;
> +
> +	hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
> +	vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
> +	vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay;
> +
> +	return 0;
> +}
> +
> +
>  int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
>  				struct intel_crtc_state *pipe_config)
>  {
> @@ -451,5 +575,8 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
>  	vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
>  		(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
>  
> +	if (intel_compute_rc_parameters(vdsc_cfg) < 0)
> +		return -1;

Just pass on the errno.

> +
>  	return 0;
>  }
> -- 
> 2.18.0

-- 
Ville Syrjälä
Intel
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[PATCH v7 11/19] drm/i915/dp: Enable/Disable DSC in DP Sink

[Manasi Navare]

From: Gaurav K Singh <gaurav.k.singh@intel.com>

This patch enables decompression support in sink device
before link training and disables the same during the
DDI disabling.

v3 (From manasi):
* Pass bool state to enable/disable (Ville)
v2:(From Manasi)
* Change the enable/disable function to take crtc_state
instead of intel_dp as an argument (Manasi)
* Use the compression_enable flag as part of crtc_state (Manasi)

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c |  5 +++++
 drivers/gpu/drm/i915/intel_dp.c  | 16 ++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h |  3 +++
 3 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 3eea987e909b..af12c15ed94f 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2952,6 +2952,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
 	intel_ddi_init_dp_buf_reg(encoder);
 	if (!is_mst)
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+	intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
+					      true);
 	intel_dp_start_link_train(intel_dp);
 	if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
 		intel_dp_stop_link_train(intel_dp);
@@ -3291,6 +3293,9 @@ static void intel_disable_ddi_dp(struct intel_encoder *encoder,
 	intel_edp_drrs_disable(intel_dp, old_crtc_state);
 	intel_psr_disable(intel_dp, old_crtc_state);
 	intel_edp_backlight_off(old_conn_state);
+	/* Disable the decompression in DP Sink */
+	intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
+					      false);
 }
 
 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 13891890d041..4cc730e9d245 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2969,6 +2969,22 @@ static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
 		intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
 }
 
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+					   const struct intel_crtc_state *crtc_state,
+					   bool enable)
+{
+	int ret;
+
+	if (!crtc_state->dsc_params.compression_enable)
+		return;
+
+	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
+				 enable ? DP_DECOMPRESSION_EN : 0);
+	if (ret < 0)
+		DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
+			      enable ? "enable" : "disable");
+}
+
 /* If the sink supports it, try to set the power state appropriately */
 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
 {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3b57146766bb..e537561b3d40 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1795,6 +1795,9 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp);
 int intel_dp_retrain_link(struct intel_encoder *encoder,
 			  struct drm_modeset_acquire_ctx *ctx);
 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+					   const struct intel_crtc_state *crtc_state,
+					   bool enable);
 void intel_dp_encoder_reset(struct drm_encoder *encoder);
 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
-- 
2.18.0

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[PATCH v7 12/19] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI

[Manasi Navare]

On Icelake, a separate power well PG2 is created for
VDSC engine used for eDP/MIPI DSI. This patch adds a new
display power domain for Power well 2.

v3:
* Call it POWER_DOMAIN_TRANSCODER_EDP_VDSC (Ville)
* Move it around TRANSCODER power domain defs (Ville)

v2:
* Fix the power well mismatch CI error (Ville)
* Rename as VDSC_PIPE_A (Imre)
* Fix a whitespace (Anusha)
* Fix Comments (Imre)

Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Ville Syrjala <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.h    | 1 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 4 +++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index b0b23e1e9392..4e6b824ccc8c 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -226,6 +226,7 @@ enum intel_display_power_domain {
 	POWER_DOMAIN_TRANSCODER_B,
 	POWER_DOMAIN_TRANSCODER_C,
 	POWER_DOMAIN_TRANSCODER_EDP,
+	POWER_DOMAIN_TRANSCODER_EDP_VDSC,
 	POWER_DOMAIN_TRANSCODER_DSI_A,
 	POWER_DOMAIN_TRANSCODER_DSI_C,
 	POWER_DOMAIN_PORT_DDI_A_LANES,
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 6c453366cd24..acbe52adbf16 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -76,6 +76,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
 		return "TRANSCODER_C";
 	case POWER_DOMAIN_TRANSCODER_EDP:
 		return "TRANSCODER_EDP";
+	case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
+		return "TRANSCODER_EDP_VDSC";
 	case POWER_DOMAIN_TRANSCODER_DSI_A:
 		return "TRANSCODER_DSI_A";
 	case POWER_DOMAIN_TRANSCODER_DSI_C:
@@ -2006,9 +2008,9 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 	 */
 #define ICL_PW_2_POWER_DOMAINS (			\
 	ICL_PW_3_POWER_DOMAINS |			\
+	BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) |		\
 	BIT_ULL(POWER_DOMAIN_INIT))
 	/*
-	 * - eDP/DSI VDSC
 	 * - KVMR (HW control)
 	 */
 #define ICL_DISPLAY_DC_OFF_POWER_DOMAINS (		\
-- 
2.18.0

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[PATCH v7 13/19] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling

[Manasi Navare]

After encoder->pre_enable() hook, after link training sequence is
completed, PPS registers for DSC encoder are configured using the
DSC state parameters in intel_crtc_state as part of DSC enabling
routine in the source. DSC enabling routine is called after
encoder->pre_enable() before enbaling the pipe and after
compression is enabled on the sink.

v5:
* make crtc_state const (Ville)
v4:
* Use cpu_transcoder instead of encoder->type for using EDP transcoder
DSC registers(Ville)
* Keep all PSS regs together (Anusha)

v3:
* Configure Pic_width/2 for each VDSC engine when two VDSC engines per pipe
are used (Manasi)
* Add DSC slice_row_per_frame in PPS16 (Manasi)

v2:
* Enable PG2 power well for VDSC on eDP

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |   2 +
 drivers/gpu/drm/i915/intel_display.c |   6 +
 drivers/gpu/drm/i915/intel_vdsc.c    | 419 +++++++++++++++++++++++++++
 3 files changed, 427 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d7797a41c648..f347d0d7b9eb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3485,6 +3485,8 @@ extern void intel_rps_mark_interactive(struct drm_i915_private *i915,
 				       bool interactive);
 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
 				  bool enable);
+extern void intel_dsc_enable(struct intel_encoder *encoder,
+			     const struct intel_crtc_state *crtc_state);
 
 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
 			struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 477e53c37353..2e96e2004831 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5417,6 +5417,12 @@ static void intel_encoders_pre_enable(struct drm_crtc *crtc,
 
 		if (encoder->pre_enable)
 			encoder->pre_enable(encoder, crtc_state, conn_state);
+
+		/*
+		 * Enable and Configure Display Stream Compression in the source
+		 * if enabled in intel_crtc_state.
+		 */
+		intel_dsc_enable(encoder, crtc_state);
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
index b93cb32026fa..9f80a86f95df 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -580,3 +580,422 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
 
 	return 0;
 }
+
+static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
+						const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg;
+	enum pipe pipe = crtc->pipe;
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 pps_val = 0;
+	u32 rc_buf_thresh_dword[4];
+	u32 rc_range_params_dword[8];
+	u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1;
+	int i = 0;
+
+	/* Populate PICTURE_PARAMETER_SET_0 registers */
+	pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
+		DSC_VER_MIN_SHIFT |
+		vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
+		vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
+	if (vdsc_cfg->block_pred_enable)
+		pps_val |= DSC_BLOCK_PREDICTION;
+	else
+		pps_val &= ~DSC_BLOCK_PREDICTION;
+	if (vdsc_cfg->convert_rgb)
+		pps_val |= DSC_COLOR_SPACE_CONVERSION;
+	else
+		pps_val &= ~DSC_COLOR_SPACE_CONVERSION;
+	if (vdsc_cfg->enable422)
+		pps_val |= DSC_422_ENABLE;
+	else
+		pps_val &= ~DSC_422_ENABLE;
+	if (vdsc_cfg->vbr_enable)
+		pps_val |= DSC_VBR_ENABLE;
+	else
+		pps_val &= ~DSC_VBR_ENABLE;
+
+	DRM_INFO("PPS0 = 0x%08x\n", pps_val);
+	 if (cpu_transcoder == TRANSCODER_EDP) {
+		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val);
+		/*
+		 * If 2 VDSC instances are needed, configure PPS for second
+		 * VDSC
+		 */
+		if (crtc_state->dsc_params.dsc_split)
+			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val);
+	} else {
+		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val);
+		if (crtc_state->dsc_params.dsc_split)
+			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
+				   pps_val);
+	}
+
+	/* Populate PICTURE_PARAMETER_SET_1 registers */
+	pps_val = 0;
+	pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
+	DRM_INFO("PPS1 = 0x%08x\n", pps_val);
+	if (cpu_transcoder == TRANSCODER_EDP) {
+		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val);
+		/*
+		 * If 2 VDSC instances are needed, configure PPS for second
+		 * VDSC
+		 */
+		if (crtc_state->dsc_params.dsc_split)
+			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_1, pps_val);
+	} else {
+		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), pps_val);
+		if (crtc_state->dsc_params.dsc_split)
+			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
+				   pps_val);
+	}
+
+	/* Populate PICTURE_PARAMETER_SET_2 registers */
+	pps_val = 0;
+	pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
+		DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
+	DRM_INFO("PPS2 = 0x%08x\n", pps_val);
+	if (encoder->type == INTEL_OUTPUT_EDP) {
+		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val);
+		/*
+		 * If 2 VDSC instances are needed, configure PPS for second
+		 * VDSC
+		 */
+		if (crtc_state->dsc_params.dsc_split)
+			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_2, pps_val);
+	} else {
+		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), pps_val);
+		if (crtc_state->dsc_params.dsc_split)
+			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),
+				   pps_val);
+	}
+
+	/* Populate PICTURE_PARAMETER_SET_3 registers */
+	pps_val = 0;
+	pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
+		DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
+	DRM_INFO("PPS3 = 0x%08x\n", pps_val);
+	if (cpu_transcoder == TRANSCODER_EDP) {
+		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_3, pps_val);
+		/*
+		 * If 2 VDSC instances are needed, configure PPS for second
+		 * VDSC
+		 */
+		if (crtc_state->dsc_params.dsc_split)
+			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_3, pps_val);
+	} else {
+		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), pps_val);
+		if (crtc_state->dsc_params.dsc_split)
+			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),
+				   pps_val);
+	}
+
+	/* Populate PICTURE_PARAMETER_SET_4 registers */
+	pps_val = 0;
+	pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
+		DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
+	DRM_INFO("PPS4 = 0x%08x\n", pps_val);
+	if (cpu_transcoder == TRANSCODER_EDP) {
+		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_4, pps_val);
+		/*
+		 * If 2 VDSC instances are needed, configure PPS for second
+		 * VDSC
+		 */
+		if (crtc_state->dsc_params.dsc_split)
+			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_4, pps_val);
+	} else {
+		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), pps_val);
+		if (crtc_state->dsc_params.dsc_split)
+			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),
+				   pps_val);
+	}
+
+	/* Populate PICTURE_PARAMETER_SET_5 registers */
+	pps_val = 0;
+	pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
+		DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
+	DRM_INFO("PPS5 = 0x%08x\n", pps_val);
+	if (cpu_transcoder == TRANSCODER_EDP) {
+		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_5, pps_val);
+		/*
+		 * If 2 VDSC instances are needed, configure PPS for second
+		 * VDSC
+		 */
+		if (crtc_state->dsc_params.dsc_split)
+			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_5, pps_val);
+	} else {
+		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), pps_val);
+		if (crtc_state->dsc_params.dsc_split)
+			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),
+				   pps_val);
+	}
+
+	/* Populate PICTURE_PARAMETER_SET_6 registers */
+	pps_val = 0;
+	pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
+		DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
+		DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
+		DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
+	DRM_INFO("PPS6 = 0x%08x\n", pps_val);
+	if (cpu_transcoder == TRANSCODER_EDP) {
+		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_6, pps_val);
+		/*
+		 * If 2 VDSC instances are needed, configure PPS for second
+		 * VDSC
+		 */
+		if (crtc_state->dsc_params.dsc_split)
+			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_6, pps_val);
+	} else {
+		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), pps_val);
+		if (crtc_state->dsc_params.dsc_split)
+			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),
+				   pps_val);
+	}
+
+	/* Populate PICTURE_PARAMETER_SET_7 registers */
+	pps_val = 0;
+	pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
+		DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
+	DRM_INFO("PPS7 = 0x%08x\n", pps_val);
+	if (cpu_transcoder == TRANSCODER_EDP) {
+		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_7, pps_val);
+		/*
+		 * If 2 VDSC instances are needed, configure PPS for second
+		 * VDSC
+		 */
+		if (crtc_state->dsc_params.dsc_split)
+			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_7, pps_val);
+	} else {
+		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), pps_val);
+		if (crtc_state->dsc_params.dsc_split)
+			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),
+				   pps_val);
+	}
+
+	/* Populate PICTURE_PARAMETER_SET_8 registers */
+	pps_val = 0;
+	pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
+		DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
+	DRM_INFO("PPS8 = 0x%08x\n", pps_val);
+	if (cpu_transcoder == TRANSCODER_EDP) {
+		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_8, pps_val);
+		/*
+		 * If 2 VDSC instances are needed, configure PPS for second
+		 * VDSC
+		 */
+		if (crtc_state->dsc_params.dsc_split)
+			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_8, pps_val);
+	} else {
+		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), pps_val);
+		if (crtc_state->dsc_params.dsc_split)
+			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),
+				   pps_val);
+	}
+
+	/* Populate PICTURE_PARAMETER_SET_9 registers */
+	pps_val = 0;
+	pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) |
+		DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
+	DRM_INFO("PPS9 = 0x%08x\n", pps_val);
+	if (cpu_transcoder == TRANSCODER_EDP) {
+		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_9, pps_val);
+		/*
+		 * If 2 VDSC instances are needed, configure PPS for second
+		 * VDSC
+		 */
+		if (crtc_state->dsc_params.dsc_split)
+			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_9, pps_val);
+	} else {
+		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), pps_val);
+		if (crtc_state->dsc_params.dsc_split)
+			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),
+				   pps_val);
+	}
+
+	/* Populate PICTURE_PARAMETER_SET_10 registers */
+	pps_val = 0;
+	pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
+		DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
+		DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
+		DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
+	DRM_INFO("PPS10 = 0x%08x\n", pps_val);
+	if (cpu_transcoder == TRANSCODER_EDP) {
+		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_10, pps_val);
+		/*
+		 * If 2 VDSC instances are needed, configure PPS for second
+		 * VDSC
+		 */
+		if (crtc_state->dsc_params.dsc_split)
+			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_10, pps_val);
+	} else {
+		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), pps_val);
+		if (crtc_state->dsc_params.dsc_split)
+			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),
+				   pps_val);
+	}
+
+	/* Populate Picture parameter set 16 */
+	pps_val = 0;
+	pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
+		DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
+				   vdsc_cfg->slice_width) |
+		DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
+					vdsc_cfg->slice_height);
+	DRM_INFO("PPS16 = 0x%08x\n", pps_val);
+	if (cpu_transcoder == TRANSCODER_EDP) {
+		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_16, pps_val);
+		/*
+		 * If 2 VDSC instances are needed, configure PPS for second
+		 * VDSC
+		 */
+		if (crtc_state->dsc_params.dsc_split)
+			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_16, pps_val);
+	} else {
+		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), pps_val);
+		if (crtc_state->dsc_params.dsc_split)
+			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),
+				   pps_val);
+	}
+
+	/* Populate the RC_BUF_THRESH registers */
+	memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
+	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
+		rc_buf_thresh_dword[i/4] |= (u32)(vdsc_cfg->rc_buf_thresh[i] <<
+						  BITS_PER_BYTE * (i % 4));
+		DRM_INFO(" RC_BUF_THRESH%d = 0x%08x\n", i,
+			 rc_buf_thresh_dword[i/4]);
+	}
+	if (cpu_transcoder == TRANSCODER_EDP) {
+		I915_WRITE(DSCA_RC_BUF_THRESH_0, rc_buf_thresh_dword[0]);
+		I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]);
+		I915_WRITE(DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]);
+		I915_WRITE(DSCA_RC_BUF_THRESH_1_UDW, rc_buf_thresh_dword[3]);
+		if (crtc_state->dsc_params.dsc_split) {
+			I915_WRITE(DSCC_RC_BUF_THRESH_0,
+				   rc_buf_thresh_dword[0]);
+			I915_WRITE(DSCC_RC_BUF_THRESH_0_UDW,
+				   rc_buf_thresh_dword[1]);
+			I915_WRITE(DSCC_RC_BUF_THRESH_1,
+				   rc_buf_thresh_dword[2]);
+			I915_WRITE(DSCC_RC_BUF_THRESH_1_UDW,
+				   rc_buf_thresh_dword[3]);
+		}
+	} else {
+		I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0(pipe),
+			   rc_buf_thresh_dword[0]);
+		I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
+			   rc_buf_thresh_dword[1]);
+		I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1(pipe),
+			   rc_buf_thresh_dword[2]);
+		I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
+			   rc_buf_thresh_dword[3]);
+		if (crtc_state->dsc_params.dsc_split) {
+			I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0(pipe),
+				   rc_buf_thresh_dword[0]);
+			I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
+				   rc_buf_thresh_dword[1]);
+			I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1(pipe),
+				   rc_buf_thresh_dword[2]);
+			I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),
+				   rc_buf_thresh_dword[3]);
+		}
+	}
+
+	/* Populate the RC_RANGE_PARAMETERS registers */
+	memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword));
+	for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
+		rc_range_params_dword[i/2] |= (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
+						      RC_BPG_OFFSET_SHIFT) |
+						     (vdsc_cfg->rc_range_params[i].range_max_qp <<
+						      RC_MAX_QP_SHIFT) |
+						     (vdsc_cfg->rc_range_params[i].range_min_qp <<
+						      RC_MIN_QP_SHIFT)) << 16 * (i % 2));
+		DRM_INFO(" RC_RANGE_PARAM_%d = 0x%08x\n", i,
+			 rc_range_params_dword[i/2]);
+	}
+	if (cpu_transcoder == TRANSCODER_EDP) {
+		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0,
+			   rc_range_params_dword[0]);
+		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0_UDW,
+			   rc_range_params_dword[1]);
+		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1,
+			   rc_range_params_dword[2]);
+		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1_UDW,
+			   rc_range_params_dword[3]);
+		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2,
+			   rc_range_params_dword[4]);
+		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2_UDW,
+			   rc_range_params_dword[5]);
+		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3,
+			   rc_range_params_dword[6]);
+		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3_UDW,
+			   rc_range_params_dword[7]);
+		if (crtc_state->dsc_params.dsc_split) {
+			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0,
+				   rc_range_params_dword[0]);
+			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0_UDW,
+				   rc_range_params_dword[1]);
+			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1,
+				   rc_range_params_dword[2]);
+			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1_UDW,
+				   rc_range_params_dword[3]);
+			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2,
+				   rc_range_params_dword[4]);
+			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2_UDW,
+				   rc_range_params_dword[5]);
+			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3,
+				   rc_range_params_dword[6]);
+			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3_UDW,
+				   rc_range_params_dword[7]);
+		}
+	} else {
+		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
+			   rc_range_params_dword[0]);
+		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),
+			   rc_range_params_dword[1]);
+		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
+			   rc_range_params_dword[2]);
+		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),
+			   rc_range_params_dword[3]);
+		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
+			   rc_range_params_dword[4]);
+		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),
+			   rc_range_params_dword[5]);
+		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
+			   rc_range_params_dword[6]);
+		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
+			   rc_range_params_dword[7]);
+		if (crtc_state->dsc_params.dsc_split) {
+			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
+				   rc_range_params_dword[0]);
+			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
+				   rc_range_params_dword[1]);
+			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),
+				   rc_range_params_dword[2]);
+			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),
+				   rc_range_params_dword[3]);
+			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),
+				   rc_range_params_dword[4]);
+			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),
+				   rc_range_params_dword[5]);
+			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),
+				   rc_range_params_dword[6]);
+			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),
+				   rc_range_params_dword[7]);
+		}
+	}
+}
+
+void intel_dsc_enable(struct intel_encoder *encoder,
+		      const struct intel_crtc_state *crtc_state)
+{
+
+	if (!crtc_state->dsc_params.compression_enable)
+		return;
+
+	intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
+
+	return;
+}
-- 
2.18.0

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Re: [PATCH v7 13/19] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling

[Ville Syrjälä]

On Thu, Nov 01, 2018 at 11:46:53PM -0700, Manasi Navare wrote:
> After encoder->pre_enable() hook, after link training sequence is
> completed, PPS registers for DSC encoder are configured using the
> DSC state parameters in intel_crtc_state as part of DSC enabling
> routine in the source. DSC enabling routine is called after
> encoder->pre_enable() before enbaling the pipe and after
> compression is enabled on the sink.
> 
> v5:
> * make crtc_state const (Ville)
> v4:
> * Use cpu_transcoder instead of encoder->type for using EDP transcoder
> DSC registers(Ville)
> * Keep all PSS regs together (Anusha)
> 
> v3:
> * Configure Pic_width/2 for each VDSC engine when two VDSC engines per pipe
> are used (Manasi)
> * Add DSC slice_row_per_frame in PPS16 (Manasi)
> 
> v2:
> * Enable PG2 power well for VDSC on eDP
> 
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h      |   2 +
>  drivers/gpu/drm/i915/intel_display.c |   6 +
>  drivers/gpu/drm/i915/intel_vdsc.c    | 419 +++++++++++++++++++++++++++
>  3 files changed, 427 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d7797a41c648..f347d0d7b9eb 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3485,6 +3485,8 @@ extern void intel_rps_mark_interactive(struct drm_i915_private *i915,
>  				       bool interactive);
>  extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
>  				  bool enable);
> +extern void intel_dsc_enable(struct intel_encoder *encoder,
> +			     const struct intel_crtc_state *crtc_state);
>  
>  int i915_reg_read_ioctl(struct drm_device *dev, void *data,
>  			struct drm_file *file);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 477e53c37353..2e96e2004831 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5417,6 +5417,12 @@ static void intel_encoders_pre_enable(struct drm_crtc *crtc,
>  
>  		if (encoder->pre_enable)
>  			encoder->pre_enable(encoder, crtc_state, conn_state);
> +
> +		/*
> +		 * Enable and Configure Display Stream Compression in the source
> +		 * if enabled in intel_crtc_state.
> +		 */
> +		intel_dsc_enable(encoder, crtc_state);

Didn't I ask for this to be moved into the pre_enable hook?
We definitely don't want it here as it would be a very suprising place
for stuff like this.

>  	}
>  }
>  
> diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
> index b93cb32026fa..9f80a86f95df 100644
> --- a/drivers/gpu/drm/i915/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/intel_vdsc.c
> @@ -580,3 +580,422 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
>  
>  	return 0;
>  }
> +
> +static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
> +						const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg;
> +	enum pipe pipe = crtc->pipe;
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 pps_val = 0;
> +	u32 rc_buf_thresh_dword[4];
> +	u32 rc_range_params_dword[8];
> +	u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1;
> +	int i = 0;
> +
> +	/* Populate PICTURE_PARAMETER_SET_0 registers */
> +	pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
> +		DSC_VER_MIN_SHIFT |
> +		vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
> +		vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
> +	if (vdsc_cfg->block_pred_enable)
> +		pps_val |= DSC_BLOCK_PREDICTION;
> +	else
> +		pps_val &= ~DSC_BLOCK_PREDICTION;
> +	if (vdsc_cfg->convert_rgb)
> +		pps_val |= DSC_COLOR_SPACE_CONVERSION;
> +	else
> +		pps_val &= ~DSC_COLOR_SPACE_CONVERSION;
> +	if (vdsc_cfg->enable422)
> +		pps_val |= DSC_422_ENABLE;
> +	else
> +		pps_val &= ~DSC_422_ENABLE;
> +	if (vdsc_cfg->vbr_enable)
> +		pps_val |= DSC_VBR_ENABLE;
> +	else
> +		pps_val &= ~DSC_VBR_ENABLE;
> +
> +	DRM_INFO("PPS0 = 0x%08x\n", pps_val);
> +	 if (cpu_transcoder == TRANSCODER_EDP) {
> +		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val);
> +		/*
> +		 * If 2 VDSC instances are needed, configure PPS for second
> +		 * VDSC
> +		 */
> +		if (crtc_state->dsc_params.dsc_split)
> +			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val);
> +	} else {
> +		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val);
> +		if (crtc_state->dsc_params.dsc_split)
> +			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
> +				   pps_val);
> +	}
> +
> +	/* Populate PICTURE_PARAMETER_SET_1 registers */
> +	pps_val = 0;
> +	pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
> +	DRM_INFO("PPS1 = 0x%08x\n", pps_val);
> +	if (cpu_transcoder == TRANSCODER_EDP) {
> +		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val);
> +		/*
> +		 * If 2 VDSC instances are needed, configure PPS for second
> +		 * VDSC
> +		 */
> +		if (crtc_state->dsc_params.dsc_split)
> +			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_1, pps_val);
> +	} else {
> +		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), pps_val);
> +		if (crtc_state->dsc_params.dsc_split)
> +			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
> +				   pps_val);
> +	}
> +
> +	/* Populate PICTURE_PARAMETER_SET_2 registers */
> +	pps_val = 0;
> +	pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
> +		DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
> +	DRM_INFO("PPS2 = 0x%08x\n", pps_val);
> +	if (encoder->type == INTEL_OUTPUT_EDP) {
> +		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val);
> +		/*
> +		 * If 2 VDSC instances are needed, configure PPS for second
> +		 * VDSC
> +		 */
> +		if (crtc_state->dsc_params.dsc_split)
> +			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_2, pps_val);
> +	} else {
> +		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), pps_val);
> +		if (crtc_state->dsc_params.dsc_split)
> +			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),
> +				   pps_val);
> +	}
> +
> +	/* Populate PICTURE_PARAMETER_SET_3 registers */
> +	pps_val = 0;
> +	pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
> +		DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
> +	DRM_INFO("PPS3 = 0x%08x\n", pps_val);
> +	if (cpu_transcoder == TRANSCODER_EDP) {
> +		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_3, pps_val);
> +		/*
> +		 * If 2 VDSC instances are needed, configure PPS for second
> +		 * VDSC
> +		 */
> +		if (crtc_state->dsc_params.dsc_split)
> +			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_3, pps_val);
> +	} else {
> +		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), pps_val);
> +		if (crtc_state->dsc_params.dsc_split)
> +			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),
> +				   pps_val);
> +	}
> +
> +	/* Populate PICTURE_PARAMETER_SET_4 registers */
> +	pps_val = 0;
> +	pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
> +		DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
> +	DRM_INFO("PPS4 = 0x%08x\n", pps_val);
> +	if (cpu_transcoder == TRANSCODER_EDP) {
> +		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_4, pps_val);
> +		/*
> +		 * If 2 VDSC instances are needed, configure PPS for second
> +		 * VDSC
> +		 */
> +		if (crtc_state->dsc_params.dsc_split)
> +			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_4, pps_val);
> +	} else {
> +		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), pps_val);
> +		if (crtc_state->dsc_params.dsc_split)
> +			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),
> +				   pps_val);
> +	}
> +
> +	/* Populate PICTURE_PARAMETER_SET_5 registers */
> +	pps_val = 0;
> +	pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
> +		DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
> +	DRM_INFO("PPS5 = 0x%08x\n", pps_val);
> +	if (cpu_transcoder == TRANSCODER_EDP) {
> +		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_5, pps_val);
> +		/*
> +		 * If 2 VDSC instances are needed, configure PPS for second
> +		 * VDSC
> +		 */
> +		if (crtc_state->dsc_params.dsc_split)
> +			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_5, pps_val);
> +	} else {
> +		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), pps_val);
> +		if (crtc_state->dsc_params.dsc_split)
> +			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),
> +				   pps_val);
> +	}
> +
> +	/* Populate PICTURE_PARAMETER_SET_6 registers */
> +	pps_val = 0;
> +	pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
> +		DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
> +		DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
> +		DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
> +	DRM_INFO("PPS6 = 0x%08x\n", pps_val);
> +	if (cpu_transcoder == TRANSCODER_EDP) {
> +		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_6, pps_val);
> +		/*
> +		 * If 2 VDSC instances are needed, configure PPS for second
> +		 * VDSC
> +		 */
> +		if (crtc_state->dsc_params.dsc_split)
> +			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_6, pps_val);
> +	} else {
> +		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), pps_val);
> +		if (crtc_state->dsc_params.dsc_split)
> +			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),
> +				   pps_val);
> +	}
> +
> +	/* Populate PICTURE_PARAMETER_SET_7 registers */
> +	pps_val = 0;
> +	pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
> +		DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
> +	DRM_INFO("PPS7 = 0x%08x\n", pps_val);
> +	if (cpu_transcoder == TRANSCODER_EDP) {
> +		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_7, pps_val);
> +		/*
> +		 * If 2 VDSC instances are needed, configure PPS for second
> +		 * VDSC
> +		 */
> +		if (crtc_state->dsc_params.dsc_split)
> +			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_7, pps_val);
> +	} else {
> +		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), pps_val);
> +		if (crtc_state->dsc_params.dsc_split)
> +			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),
> +				   pps_val);
> +	}
> +
> +	/* Populate PICTURE_PARAMETER_SET_8 registers */
> +	pps_val = 0;
> +	pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
> +		DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
> +	DRM_INFO("PPS8 = 0x%08x\n", pps_val);
> +	if (cpu_transcoder == TRANSCODER_EDP) {
> +		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_8, pps_val);
> +		/*
> +		 * If 2 VDSC instances are needed, configure PPS for second
> +		 * VDSC
> +		 */
> +		if (crtc_state->dsc_params.dsc_split)
> +			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_8, pps_val);
> +	} else {
> +		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), pps_val);
> +		if (crtc_state->dsc_params.dsc_split)
> +			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),
> +				   pps_val);
> +	}
> +
> +	/* Populate PICTURE_PARAMETER_SET_9 registers */
> +	pps_val = 0;
> +	pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) |
> +		DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
> +	DRM_INFO("PPS9 = 0x%08x\n", pps_val);
> +	if (cpu_transcoder == TRANSCODER_EDP) {
> +		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_9, pps_val);
> +		/*
> +		 * If 2 VDSC instances are needed, configure PPS for second
> +		 * VDSC
> +		 */
> +		if (crtc_state->dsc_params.dsc_split)
> +			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_9, pps_val);
> +	} else {
> +		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), pps_val);
> +		if (crtc_state->dsc_params.dsc_split)
> +			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),
> +				   pps_val);
> +	}
> +
> +	/* Populate PICTURE_PARAMETER_SET_10 registers */
> +	pps_val = 0;
> +	pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
> +		DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
> +		DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
> +		DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
> +	DRM_INFO("PPS10 = 0x%08x\n", pps_val);
> +	if (cpu_transcoder == TRANSCODER_EDP) {
> +		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_10, pps_val);
> +		/*
> +		 * If 2 VDSC instances are needed, configure PPS for second
> +		 * VDSC
> +		 */
> +		if (crtc_state->dsc_params.dsc_split)
> +			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_10, pps_val);
> +	} else {
> +		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), pps_val);
> +		if (crtc_state->dsc_params.dsc_split)
> +			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),
> +				   pps_val);
> +	}
> +
> +	/* Populate Picture parameter set 16 */
> +	pps_val = 0;
> +	pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
> +		DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
> +				   vdsc_cfg->slice_width) |
> +		DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
> +					vdsc_cfg->slice_height);
> +	DRM_INFO("PPS16 = 0x%08x\n", pps_val);
> +	if (cpu_transcoder == TRANSCODER_EDP) {
> +		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_16, pps_val);
> +		/*
> +		 * If 2 VDSC instances are needed, configure PPS for second
> +		 * VDSC
> +		 */
> +		if (crtc_state->dsc_params.dsc_split)
> +			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_16, pps_val);
> +	} else {
> +		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), pps_val);
> +		if (crtc_state->dsc_params.dsc_split)
> +			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),
> +				   pps_val);
> +	}
> +
> +	/* Populate the RC_BUF_THRESH registers */
> +	memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
> +	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
> +		rc_buf_thresh_dword[i/4] |= (u32)(vdsc_cfg->rc_buf_thresh[i] <<
> +						  BITS_PER_BYTE * (i % 4));
> +		DRM_INFO(" RC_BUF_THRESH%d = 0x%08x\n", i,
> +			 rc_buf_thresh_dword[i/4]);
> +	}
> +	if (cpu_transcoder == TRANSCODER_EDP) {
> +		I915_WRITE(DSCA_RC_BUF_THRESH_0, rc_buf_thresh_dword[0]);
> +		I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]);
> +		I915_WRITE(DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]);
> +		I915_WRITE(DSCA_RC_BUF_THRESH_1_UDW, rc_buf_thresh_dword[3]);
> +		if (crtc_state->dsc_params.dsc_split) {
> +			I915_WRITE(DSCC_RC_BUF_THRESH_0,
> +				   rc_buf_thresh_dword[0]);
> +			I915_WRITE(DSCC_RC_BUF_THRESH_0_UDW,
> +				   rc_buf_thresh_dword[1]);
> +			I915_WRITE(DSCC_RC_BUF_THRESH_1,
> +				   rc_buf_thresh_dword[2]);
> +			I915_WRITE(DSCC_RC_BUF_THRESH_1_UDW,
> +				   rc_buf_thresh_dword[3]);
> +		}
> +	} else {
> +		I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0(pipe),
> +			   rc_buf_thresh_dword[0]);
> +		I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
> +			   rc_buf_thresh_dword[1]);
> +		I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1(pipe),
> +			   rc_buf_thresh_dword[2]);
> +		I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
> +			   rc_buf_thresh_dword[3]);
> +		if (crtc_state->dsc_params.dsc_split) {
> +			I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0(pipe),
> +				   rc_buf_thresh_dword[0]);
> +			I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
> +				   rc_buf_thresh_dword[1]);
> +			I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1(pipe),
> +				   rc_buf_thresh_dword[2]);
> +			I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),
> +				   rc_buf_thresh_dword[3]);
> +		}
> +	}
> +
> +	/* Populate the RC_RANGE_PARAMETERS registers */
> +	memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword));
> +	for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
> +		rc_range_params_dword[i/2] |= (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
> +						      RC_BPG_OFFSET_SHIFT) |
> +						     (vdsc_cfg->rc_range_params[i].range_max_qp <<
> +						      RC_MAX_QP_SHIFT) |
> +						     (vdsc_cfg->rc_range_params[i].range_min_qp <<
> +						      RC_MIN_QP_SHIFT)) << 16 * (i % 2));
> +		DRM_INFO(" RC_RANGE_PARAM_%d = 0x%08x\n", i,
> +			 rc_range_params_dword[i/2]);
> +	}
> +	if (cpu_transcoder == TRANSCODER_EDP) {
> +		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0,
> +			   rc_range_params_dword[0]);
> +		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0_UDW,
> +			   rc_range_params_dword[1]);
> +		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1,
> +			   rc_range_params_dword[2]);
> +		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1_UDW,
> +			   rc_range_params_dword[3]);
> +		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2,
> +			   rc_range_params_dword[4]);
> +		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2_UDW,
> +			   rc_range_params_dword[5]);
> +		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3,
> +			   rc_range_params_dword[6]);
> +		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3_UDW,
> +			   rc_range_params_dword[7]);
> +		if (crtc_state->dsc_params.dsc_split) {
> +			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0,
> +				   rc_range_params_dword[0]);
> +			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0_UDW,
> +				   rc_range_params_dword[1]);
> +			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1,
> +				   rc_range_params_dword[2]);
> +			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1_UDW,
> +				   rc_range_params_dword[3]);
> +			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2,
> +				   rc_range_params_dword[4]);
> +			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2_UDW,
> +				   rc_range_params_dword[5]);
> +			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3,
> +				   rc_range_params_dword[6]);
> +			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3_UDW,
> +				   rc_range_params_dword[7]);
> +		}
> +	} else {
> +		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
> +			   rc_range_params_dword[0]);
> +		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),
> +			   rc_range_params_dword[1]);
> +		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
> +			   rc_range_params_dword[2]);
> +		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),
> +			   rc_range_params_dword[3]);
> +		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
> +			   rc_range_params_dword[4]);
> +		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),
> +			   rc_range_params_dword[5]);
> +		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
> +			   rc_range_params_dword[6]);
> +		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
> +			   rc_range_params_dword[7]);
> +		if (crtc_state->dsc_params.dsc_split) {
> +			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
> +				   rc_range_params_dword[0]);
> +			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
> +				   rc_range_params_dword[1]);
> +			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),
> +				   rc_range_params_dword[2]);
> +			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),
> +				   rc_range_params_dword[3]);
> +			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),
> +				   rc_range_params_dword[4]);
> +			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),
> +				   rc_range_params_dword[5]);
> +			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),
> +				   rc_range_params_dword[6]);
> +			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),
> +				   rc_range_params_dword[7]);
> +		}
> +	}
> +}
> +
> +void intel_dsc_enable(struct intel_encoder *encoder,
> +		      const struct intel_crtc_state *crtc_state)
> +{
> +
> +	if (!crtc_state->dsc_params.compression_enable)
> +		return;
> +
> +	intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
> +
> +	return;
> +}
> -- 
> 2.18.0

-- 
Ville Syrjälä
Intel
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Intel-gfx@lists.freedesktop.org
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Re: [PATCH v7 13/19] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling

[Manasi Navare]

On Fri, Nov 02, 2018 at 07:52:53PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 01, 2018 at 11:46:53PM -0700, Manasi Navare wrote:
> > After encoder->pre_enable() hook, after link training sequence is
> > completed, PPS registers for DSC encoder are configured using the
> > DSC state parameters in intel_crtc_state as part of DSC enabling
> > routine in the source. DSC enabling routine is called after
> > encoder->pre_enable() before enbaling the pipe and after
> > compression is enabled on the sink.
> > 
> > v5:
> > * make crtc_state const (Ville)
> > v4:
> > * Use cpu_transcoder instead of encoder->type for using EDP transcoder
> > DSC registers(Ville)
> > * Keep all PSS regs together (Anusha)
> > 
> > v3:
> > * Configure Pic_width/2 for each VDSC engine when two VDSC engines per pipe
> > are used (Manasi)
> > * Add DSC slice_row_per_frame in PPS16 (Manasi)
> > 
> > v2:
> > * Enable PG2 power well for VDSC on eDP
> > 
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h      |   2 +
> >  drivers/gpu/drm/i915/intel_display.c |   6 +
> >  drivers/gpu/drm/i915/intel_vdsc.c    | 419 +++++++++++++++++++++++++++
> >  3 files changed, 427 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index d7797a41c648..f347d0d7b9eb 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -3485,6 +3485,8 @@ extern void intel_rps_mark_interactive(struct drm_i915_private *i915,
> >  				       bool interactive);
> >  extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
> >  				  bool enable);
> > +extern void intel_dsc_enable(struct intel_encoder *encoder,
> > +			     const struct intel_crtc_state *crtc_state);
> >  
> >  int i915_reg_read_ioctl(struct drm_device *dev, void *data,
> >  			struct drm_file *file);
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 477e53c37353..2e96e2004831 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5417,6 +5417,12 @@ static void intel_encoders_pre_enable(struct drm_crtc *crtc,
> >  
> >  		if (encoder->pre_enable)
> >  			encoder->pre_enable(encoder, crtc_state, conn_state);
> > +
> > +		/*
> > +		 * Enable and Configure Display Stream Compression in the source
> > +		 * if enabled in intel_crtc_state.
> > +		 */
> > +		intel_dsc_enable(encoder, crtc_state);
> 
> Didn't I ask for this to be moved into the pre_enable hook?
> We definitely don't want it here as it would be a very suprising place
> for stuff like this.

I will move it to intel_ddi_pre_enable_dp() at the end of the function.

Manasi

> 
> >  	}
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
> > index b93cb32026fa..9f80a86f95df 100644
> > --- a/drivers/gpu/drm/i915/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/intel_vdsc.c
> > @@ -580,3 +580,422 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
> >  
> >  	return 0;
> >  }
> > +
> > +static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
> > +						const struct intel_crtc_state *crtc_state)
> > +{
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg;
> > +	enum pipe pipe = crtc->pipe;
> > +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > +	u32 pps_val = 0;
> > +	u32 rc_buf_thresh_dword[4];
> > +	u32 rc_range_params_dword[8];
> > +	u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1;
> > +	int i = 0;
> > +
> > +	/* Populate PICTURE_PARAMETER_SET_0 registers */
> > +	pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
> > +		DSC_VER_MIN_SHIFT |
> > +		vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
> > +		vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
> > +	if (vdsc_cfg->block_pred_enable)
> > +		pps_val |= DSC_BLOCK_PREDICTION;
> > +	else
> > +		pps_val &= ~DSC_BLOCK_PREDICTION;
> > +	if (vdsc_cfg->convert_rgb)
> > +		pps_val |= DSC_COLOR_SPACE_CONVERSION;
> > +	else
> > +		pps_val &= ~DSC_COLOR_SPACE_CONVERSION;
> > +	if (vdsc_cfg->enable422)
> > +		pps_val |= DSC_422_ENABLE;
> > +	else
> > +		pps_val &= ~DSC_422_ENABLE;
> > +	if (vdsc_cfg->vbr_enable)
> > +		pps_val |= DSC_VBR_ENABLE;
> > +	else
> > +		pps_val &= ~DSC_VBR_ENABLE;
> > +
> > +	DRM_INFO("PPS0 = 0x%08x\n", pps_val);
> > +	 if (cpu_transcoder == TRANSCODER_EDP) {
> > +		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val);
> > +		/*
> > +		 * If 2 VDSC instances are needed, configure PPS for second
> > +		 * VDSC
> > +		 */
> > +		if (crtc_state->dsc_params.dsc_split)
> > +			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val);
> > +	} else {
> > +		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val);
> > +		if (crtc_state->dsc_params.dsc_split)
> > +			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
> > +				   pps_val);
> > +	}
> > +
> > +	/* Populate PICTURE_PARAMETER_SET_1 registers */
> > +	pps_val = 0;
> > +	pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
> > +	DRM_INFO("PPS1 = 0x%08x\n", pps_val);
> > +	if (cpu_transcoder == TRANSCODER_EDP) {
> > +		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val);
> > +		/*
> > +		 * If 2 VDSC instances are needed, configure PPS for second
> > +		 * VDSC
> > +		 */
> > +		if (crtc_state->dsc_params.dsc_split)
> > +			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_1, pps_val);
> > +	} else {
> > +		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), pps_val);
> > +		if (crtc_state->dsc_params.dsc_split)
> > +			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
> > +				   pps_val);
> > +	}
> > +
> > +	/* Populate PICTURE_PARAMETER_SET_2 registers */
> > +	pps_val = 0;
> > +	pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
> > +		DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
> > +	DRM_INFO("PPS2 = 0x%08x\n", pps_val);
> > +	if (encoder->type == INTEL_OUTPUT_EDP) {
> > +		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val);
> > +		/*
> > +		 * If 2 VDSC instances are needed, configure PPS for second
> > +		 * VDSC
> > +		 */
> > +		if (crtc_state->dsc_params.dsc_split)
> > +			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_2, pps_val);
> > +	} else {
> > +		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), pps_val);
> > +		if (crtc_state->dsc_params.dsc_split)
> > +			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),
> > +				   pps_val);
> > +	}
> > +
> > +	/* Populate PICTURE_PARAMETER_SET_3 registers */
> > +	pps_val = 0;
> > +	pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
> > +		DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
> > +	DRM_INFO("PPS3 = 0x%08x\n", pps_val);
> > +	if (cpu_transcoder == TRANSCODER_EDP) {
> > +		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_3, pps_val);
> > +		/*
> > +		 * If 2 VDSC instances are needed, configure PPS for second
> > +		 * VDSC
> > +		 */
> > +		if (crtc_state->dsc_params.dsc_split)
> > +			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_3, pps_val);
> > +	} else {
> > +		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), pps_val);
> > +		if (crtc_state->dsc_params.dsc_split)
> > +			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),
> > +				   pps_val);
> > +	}
> > +
> > +	/* Populate PICTURE_PARAMETER_SET_4 registers */
> > +	pps_val = 0;
> > +	pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
> > +		DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
> > +	DRM_INFO("PPS4 = 0x%08x\n", pps_val);
> > +	if (cpu_transcoder == TRANSCODER_EDP) {
> > +		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_4, pps_val);
> > +		/*
> > +		 * If 2 VDSC instances are needed, configure PPS for second
> > +		 * VDSC
> > +		 */
> > +		if (crtc_state->dsc_params.dsc_split)
> > +			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_4, pps_val);
> > +	} else {
> > +		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), pps_val);
> > +		if (crtc_state->dsc_params.dsc_split)
> > +			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),
> > +				   pps_val);
> > +	}
> > +
> > +	/* Populate PICTURE_PARAMETER_SET_5 registers */
> > +	pps_val = 0;
> > +	pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
> > +		DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
> > +	DRM_INFO("PPS5 = 0x%08x\n", pps_val);
> > +	if (cpu_transcoder == TRANSCODER_EDP) {
> > +		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_5, pps_val);
> > +		/*
> > +		 * If 2 VDSC instances are needed, configure PPS for second
> > +		 * VDSC
> > +		 */
> > +		if (crtc_state->dsc_params.dsc_split)
> > +			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_5, pps_val);
> > +	} else {
> > +		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), pps_val);
> > +		if (crtc_state->dsc_params.dsc_split)
> > +			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),
> > +				   pps_val);
> > +	}
> > +
> > +	/* Populate PICTURE_PARAMETER_SET_6 registers */
> > +	pps_val = 0;
> > +	pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
> > +		DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
> > +		DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
> > +		DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
> > +	DRM_INFO("PPS6 = 0x%08x\n", pps_val);
> > +	if (cpu_transcoder == TRANSCODER_EDP) {
> > +		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_6, pps_val);
> > +		/*
> > +		 * If 2 VDSC instances are needed, configure PPS for second
> > +		 * VDSC
> > +		 */
> > +		if (crtc_state->dsc_params.dsc_split)
> > +			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_6, pps_val);
> > +	} else {
> > +		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), pps_val);
> > +		if (crtc_state->dsc_params.dsc_split)
> > +			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),
> > +				   pps_val);
> > +	}
> > +
> > +	/* Populate PICTURE_PARAMETER_SET_7 registers */
> > +	pps_val = 0;
> > +	pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
> > +		DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
> > +	DRM_INFO("PPS7 = 0x%08x\n", pps_val);
> > +	if (cpu_transcoder == TRANSCODER_EDP) {
> > +		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_7, pps_val);
> > +		/*
> > +		 * If 2 VDSC instances are needed, configure PPS for second
> > +		 * VDSC
> > +		 */
> > +		if (crtc_state->dsc_params.dsc_split)
> > +			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_7, pps_val);
> > +	} else {
> > +		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), pps_val);
> > +		if (crtc_state->dsc_params.dsc_split)
> > +			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),
> > +				   pps_val);
> > +	}
> > +
> > +	/* Populate PICTURE_PARAMETER_SET_8 registers */
> > +	pps_val = 0;
> > +	pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
> > +		DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
> > +	DRM_INFO("PPS8 = 0x%08x\n", pps_val);
> > +	if (cpu_transcoder == TRANSCODER_EDP) {
> > +		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_8, pps_val);
> > +		/*
> > +		 * If 2 VDSC instances are needed, configure PPS for second
> > +		 * VDSC
> > +		 */
> > +		if (crtc_state->dsc_params.dsc_split)
> > +			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_8, pps_val);
> > +	} else {
> > +		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), pps_val);
> > +		if (crtc_state->dsc_params.dsc_split)
> > +			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),
> > +				   pps_val);
> > +	}
> > +
> > +	/* Populate PICTURE_PARAMETER_SET_9 registers */
> > +	pps_val = 0;
> > +	pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) |
> > +		DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
> > +	DRM_INFO("PPS9 = 0x%08x\n", pps_val);
> > +	if (cpu_transcoder == TRANSCODER_EDP) {
> > +		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_9, pps_val);
> > +		/*
> > +		 * If 2 VDSC instances are needed, configure PPS for second
> > +		 * VDSC
> > +		 */
> > +		if (crtc_state->dsc_params.dsc_split)
> > +			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_9, pps_val);
> > +	} else {
> > +		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), pps_val);
> > +		if (crtc_state->dsc_params.dsc_split)
> > +			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),
> > +				   pps_val);
> > +	}
> > +
> > +	/* Populate PICTURE_PARAMETER_SET_10 registers */
> > +	pps_val = 0;
> > +	pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
> > +		DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
> > +		DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
> > +		DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
> > +	DRM_INFO("PPS10 = 0x%08x\n", pps_val);
> > +	if (cpu_transcoder == TRANSCODER_EDP) {
> > +		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_10, pps_val);
> > +		/*
> > +		 * If 2 VDSC instances are needed, configure PPS for second
> > +		 * VDSC
> > +		 */
> > +		if (crtc_state->dsc_params.dsc_split)
> > +			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_10, pps_val);
> > +	} else {
> > +		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), pps_val);
> > +		if (crtc_state->dsc_params.dsc_split)
> > +			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),
> > +				   pps_val);
> > +	}
> > +
> > +	/* Populate Picture parameter set 16 */
> > +	pps_val = 0;
> > +	pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
> > +		DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
> > +				   vdsc_cfg->slice_width) |
> > +		DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
> > +					vdsc_cfg->slice_height);
> > +	DRM_INFO("PPS16 = 0x%08x\n", pps_val);
> > +	if (cpu_transcoder == TRANSCODER_EDP) {
> > +		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_16, pps_val);
> > +		/*
> > +		 * If 2 VDSC instances are needed, configure PPS for second
> > +		 * VDSC
> > +		 */
> > +		if (crtc_state->dsc_params.dsc_split)
> > +			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_16, pps_val);
> > +	} else {
> > +		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), pps_val);
> > +		if (crtc_state->dsc_params.dsc_split)
> > +			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),
> > +				   pps_val);
> > +	}
> > +
> > +	/* Populate the RC_BUF_THRESH registers */
> > +	memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
> > +	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
> > +		rc_buf_thresh_dword[i/4] |= (u32)(vdsc_cfg->rc_buf_thresh[i] <<
> > +						  BITS_PER_BYTE * (i % 4));
> > +		DRM_INFO(" RC_BUF_THRESH%d = 0x%08x\n", i,
> > +			 rc_buf_thresh_dword[i/4]);
> > +	}
> > +	if (cpu_transcoder == TRANSCODER_EDP) {
> > +		I915_WRITE(DSCA_RC_BUF_THRESH_0, rc_buf_thresh_dword[0]);
> > +		I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]);
> > +		I915_WRITE(DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]);
> > +		I915_WRITE(DSCA_RC_BUF_THRESH_1_UDW, rc_buf_thresh_dword[3]);
> > +		if (crtc_state->dsc_params.dsc_split) {
> > +			I915_WRITE(DSCC_RC_BUF_THRESH_0,
> > +				   rc_buf_thresh_dword[0]);
> > +			I915_WRITE(DSCC_RC_BUF_THRESH_0_UDW,
> > +				   rc_buf_thresh_dword[1]);
> > +			I915_WRITE(DSCC_RC_BUF_THRESH_1,
> > +				   rc_buf_thresh_dword[2]);
> > +			I915_WRITE(DSCC_RC_BUF_THRESH_1_UDW,
> > +				   rc_buf_thresh_dword[3]);
> > +		}
> > +	} else {
> > +		I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0(pipe),
> > +			   rc_buf_thresh_dword[0]);
> > +		I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
> > +			   rc_buf_thresh_dword[1]);
> > +		I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1(pipe),
> > +			   rc_buf_thresh_dword[2]);
> > +		I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
> > +			   rc_buf_thresh_dword[3]);
> > +		if (crtc_state->dsc_params.dsc_split) {
> > +			I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0(pipe),
> > +				   rc_buf_thresh_dword[0]);
> > +			I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
> > +				   rc_buf_thresh_dword[1]);
> > +			I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1(pipe),
> > +				   rc_buf_thresh_dword[2]);
> > +			I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),
> > +				   rc_buf_thresh_dword[3]);
> > +		}
> > +	}
> > +
> > +	/* Populate the RC_RANGE_PARAMETERS registers */
> > +	memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword));
> > +	for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
> > +		rc_range_params_dword[i/2] |= (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
> > +						      RC_BPG_OFFSET_SHIFT) |
> > +						     (vdsc_cfg->rc_range_params[i].range_max_qp <<
> > +						      RC_MAX_QP_SHIFT) |
> > +						     (vdsc_cfg->rc_range_params[i].range_min_qp <<
> > +						      RC_MIN_QP_SHIFT)) << 16 * (i % 2));
> > +		DRM_INFO(" RC_RANGE_PARAM_%d = 0x%08x\n", i,
> > +			 rc_range_params_dword[i/2]);
> > +	}
> > +	if (cpu_transcoder == TRANSCODER_EDP) {
> > +		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0,
> > +			   rc_range_params_dword[0]);
> > +		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0_UDW,
> > +			   rc_range_params_dword[1]);
> > +		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1,
> > +			   rc_range_params_dword[2]);
> > +		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1_UDW,
> > +			   rc_range_params_dword[3]);
> > +		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2,
> > +			   rc_range_params_dword[4]);
> > +		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2_UDW,
> > +			   rc_range_params_dword[5]);
> > +		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3,
> > +			   rc_range_params_dword[6]);
> > +		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3_UDW,
> > +			   rc_range_params_dword[7]);
> > +		if (crtc_state->dsc_params.dsc_split) {
> > +			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0,
> > +				   rc_range_params_dword[0]);
> > +			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0_UDW,
> > +				   rc_range_params_dword[1]);
> > +			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1,
> > +				   rc_range_params_dword[2]);
> > +			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1_UDW,
> > +				   rc_range_params_dword[3]);
> > +			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2,
> > +				   rc_range_params_dword[4]);
> > +			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2_UDW,
> > +				   rc_range_params_dword[5]);
> > +			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3,
> > +				   rc_range_params_dword[6]);
> > +			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3_UDW,
> > +				   rc_range_params_dword[7]);
> > +		}
> > +	} else {
> > +		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
> > +			   rc_range_params_dword[0]);
> > +		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),
> > +			   rc_range_params_dword[1]);
> > +		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
> > +			   rc_range_params_dword[2]);
> > +		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),
> > +			   rc_range_params_dword[3]);
> > +		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
> > +			   rc_range_params_dword[4]);
> > +		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),
> > +			   rc_range_params_dword[5]);
> > +		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
> > +			   rc_range_params_dword[6]);
> > +		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
> > +			   rc_range_params_dword[7]);
> > +		if (crtc_state->dsc_params.dsc_split) {
> > +			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
> > +				   rc_range_params_dword[0]);
> > +			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
> > +				   rc_range_params_dword[1]);
> > +			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),
> > +				   rc_range_params_dword[2]);
> > +			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),
> > +				   rc_range_params_dword[3]);
> > +			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),
> > +				   rc_range_params_dword[4]);
> > +			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),
> > +				   rc_range_params_dword[5]);
> > +			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),
> > +				   rc_range_params_dword[6]);
> > +			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),
> > +				   rc_range_params_dword[7]);
> > +		}
> > +	}
> > +}
> > +
> > +void intel_dsc_enable(struct intel_encoder *encoder,
> > +		      const struct intel_crtc_state *crtc_state)
> > +{
> > +
> > +	if (!crtc_state->dsc_params.compression_enable)
> > +		return;
> > +
> > +	intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
> > +
> > +	return;
> > +}
> > -- 
> > 2.18.0
> 
> -- 
> Ville Syrjälä
> Intel
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
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[PATCH v7 14/19] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs

[Manasi Navare]

Infoframes are used to send secondary data packets. This patch
adds support for DSC Picture parameter set secondary data packets
in the existing write_infoframe helpers.

v3:
* Unused variables cleanup (Ville)
v2:
* Rebase on drm-tip (Manasi)

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   |  1 +
 drivers/gpu/drm/i915/intel_hdmi.c | 21 +++++++++++++++++++--
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c0e6e14fe9fa..49c3c24965eb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4550,6 +4550,7 @@ enum {
  * of the infoframe structure specified by CEA-861. */
 #define   VIDEO_DIP_DATA_SIZE	32
 #define   VIDEO_DIP_VSC_DATA_SIZE	36
+#define   VIDEO_DIP_PPS_DATA_SIZE	132
 #define VIDEO_DIP_CTL		_MMIO(0x61170)
 /* Pre HSW: */
 #define   VIDEO_DIP_ENABLE		(1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 0c587e4503e3..61867a6733a8 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -115,6 +115,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
 	switch (type) {
 	case DP_SDP_VSC:
 		return VIDEO_DIP_ENABLE_VSC_HSW;
+	case DP_SDP_PPS:
+		return VDIP_ENABLE_PPS;
 	case HDMI_INFOFRAME_TYPE_AVI:
 		return VIDEO_DIP_ENABLE_AVI_HSW;
 	case HDMI_INFOFRAME_TYPE_SPD:
@@ -136,6 +138,8 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 	switch (type) {
 	case DP_SDP_VSC:
 		return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
+	case DP_SDP_PPS:
+		return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
 	case HDMI_INFOFRAME_TYPE_AVI:
 		return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 	case HDMI_INFOFRAME_TYPE_SPD:
@@ -148,6 +152,18 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 	}
 }
 
+static int hsw_dip_data_size(unsigned int type)
+{
+	switch (type) {
+	case DP_SDP_VSC:
+		return VIDEO_DIP_VSC_DATA_SIZE;
+	case DP_SDP_PPS:
+		return VIDEO_DIP_PPS_DATA_SIZE;
+	default:
+		return VIDEO_DIP_DATA_SIZE;
+	}
+}
+
 static void g4x_write_infoframe(struct intel_encoder *encoder,
 				const struct intel_crtc_state *crtc_state,
 				unsigned int type,
@@ -382,11 +398,12 @@ static void hsw_write_infoframe(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
-	int data_size = type == DP_SDP_VSC ?
-		VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE;
+	int data_size;
 	int i;
 	u32 val = I915_READ(ctl_reg);
 
+	data_size = hsw_dip_data_size(type);
+
 	val &= ~hsw_infoframe_enable(type);
 	I915_WRITE(ctl_reg, val);
 
-- 
2.18.0

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[PATCH v7 15/19] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes

[Manasi Navare]

DSC PPS secondary data packet infoframes are filled with
DSC picure parameter set metadata according to the DSC standard.
These infoframes are sent to the sink device and used during DSC
decoding.

v3:
* Rename to intel_dp_write_pps_sdp (Ville)
* Use const intel_crtc_state (Ville)
v2:
* Rebase ond drm-tip

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/intel_vdsc.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
index 9f80a86f95df..015c4bff85d4 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -988,6 +988,25 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
 	}
 }
 
+static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder,
+				       const struct intel_crtc_state *crtc_state)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg;
+	struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
+
+	/* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
+	drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp);
+
+	/* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
+	drm_dsc_pps_infoframe_pack(&dp_dsc_pps_sdp, vdsc_cfg);
+
+	intel_dig_port->write_infoframe(encoder, crtc_state,
+					DP_SDP_PPS, &dp_dsc_pps_sdp,
+					sizeof(dp_dsc_pps_sdp));
+}
+
 void intel_dsc_enable(struct intel_encoder *encoder,
 		      const struct intel_crtc_state *crtc_state)
 {
@@ -997,5 +1016,7 @@ void intel_dsc_enable(struct intel_encoder *encoder,
 
 	intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
 
+	intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
+
 	return;
 }
-- 
2.18.0

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[PATCH v7 16/19] drm/i915/dp: Configure Display stream splitter registers during DSC enable

[Manasi Navare]

Display Stream Splitter registers need to be programmed to enable
the joiner if two DSC engines are used and also to enable
the left and the right DSC engines. This happens as part of
the DSC enabling routine in the source in atomic commit.

v4:
* Remove redundant comment (Ville)
v3:
* Use cpu_transcoder instead of encoder->type (Ville)
v2:
* Rebase (Manasi)

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intelcom>
---
 drivers/gpu/drm/i915/intel_vdsc.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
index 015c4bff85d4..dee627af7f41 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -1010,6 +1010,12 @@ static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder,
 void intel_dsc_enable(struct intel_encoder *encoder,
 		      const struct intel_crtc_state *crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum pipe pipe = crtc->pipe;
+	i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
+	u32 dss_ctl1_val = 0;
+	u32 dss_ctl2_val = 0;
 
 	if (!crtc_state->dsc_params.compression_enable)
 		return;
@@ -1018,5 +1024,20 @@ void intel_dsc_enable(struct intel_encoder *encoder,
 
 	intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
 
+	if (crtc_state->cpu_transcoder == TRANSCODER_EDP) {
+		dss_ctl1_reg = DSS_CTL1;
+		dss_ctl2_reg = DSS_CTL2;
+	} else {
+		dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
+		dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
+	}
+	dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
+	if (crtc_state->dsc_params.dsc_split) {
+		dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
+		dss_ctl1_val |= JOINER_ENABLE;
+	}
+	I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
+	I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+
 	return;
 }
-- 
2.18.0

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[PATCH v7 17/19] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits

[Manasi Navare]

1. Disable Left/right VDSC branch in DSS Ctrl reg
    depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg

v4:
* Remove encoder, make crtc_state const (Ville)
v3 (From Manasi):
* Add Disable PG2 for VDSC on eDP
v2 (From Manasi):
* Use old_crtc_state to find dsc params
* Add a condition to disable only if
dsc state compression is enabled
* Use correct DSS CTL regs

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  1 +
 drivers/gpu/drm/i915/intel_display.c |  2 ++
 drivers/gpu/drm/i915/intel_vdsc.c    | 32 ++++++++++++++++++++++++++++
 3 files changed, 35 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f347d0d7b9eb..c80c9a1af3d1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3487,6 +3487,7 @@ extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
 				  bool enable);
 extern void intel_dsc_enable(struct intel_encoder *encoder,
 			     const struct intel_crtc_state *crtc_state);
+extern void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
 
 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
 			struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2e96e2004831..0aba7f286f75 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5853,6 +5853,8 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
 	if (!transcoder_is_dsi(cpu_transcoder))
 		intel_ddi_disable_transcoder_func(old_crtc_state);
 
+	intel_dsc_disable(old_crtc_state);
+
 	if (INTEL_GEN(dev_priv) >= 9)
 		skylake_scaler_disable(intel_crtc);
 	else
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
index dee627af7f41..219dc1517c8a 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -1041,3 +1041,35 @@ void intel_dsc_enable(struct intel_encoder *encoder,
 
 	return;
 }
+
+void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+	i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
+	u32 dss_ctl1_val = 0, dss_ctl2_val = 0;
+
+	if (!old_crtc_state->dsc_params.compression_enable)
+		return;
+
+	if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) {
+		dss_ctl1_reg = DSS_CTL1;
+		dss_ctl2_reg = DSS_CTL2;
+	} else {
+		dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
+		dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
+	}
+	dss_ctl1_val = I915_READ(dss_ctl1_reg);
+	if (dss_ctl1_val & JOINER_ENABLE)
+		dss_ctl1_val &= ~JOINER_ENABLE;
+	I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
+
+	dss_ctl2_val = I915_READ(dss_ctl2_reg);
+	if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE ||
+	    dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)
+		dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |
+				  RIGHT_BRANCH_VDSC_ENABLE);
+	I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+
+}
-- 
2.18.0

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[PATCH v7 18/19] drm/i915/dsc: Enable and disable appropriate power wells for VDSC

[Manasi Navare]

A separate power well 2 (PG2) is required for VDSC on eDP transcoder
whereas all other transcoders use the power wells associated with the
transcoders for VDSC.
This patch adds a helper to obtain correct power domain depending on
transcoder being used and enables/disables the power wells during
VDSC enabling/disabling.

v3:
* Call it intel_dsc_power_domain, add to
intel_ddi_get_power_domains (Ville)
v2:
* Fix tabs, const crtc_state, fix comments (Ville)

Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c  |  3 ++-
 drivers/gpu/drm/i915/intel_drv.h  |  2 ++
 drivers/gpu/drm/i915/intel_vdsc.c | 25 +++++++++++++++++++++++++
 3 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index af12c15ed94f..c243bb3f2be9 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2124,7 +2124,8 @@ static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder,
 	 */
 	if (intel_crtc_has_dp_encoder(crtc_state) ||
 	    intel_port_is_tc(dev_priv, encoder->port))
-		domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port));
+		domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port)) |
+			BIT_ULL(intel_dsc_power_domain(crtc_state));
 
 	return domains;
 }
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e537561b3d40..2d41dff6eed1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1859,6 +1859,8 @@ uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
 /* intel_vdsc.c */
 int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
 				struct intel_crtc_state *pipe_config);
+enum intel_display_power_domain
+intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
 
 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
 {
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
index 219dc1517c8a..9eae037a3b4d 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -581,6 +581,24 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
 	return 0;
 }
 
+enum intel_display_power_domain
+intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
+{
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	/*
+	 * On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
+	 * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
+	 * For any other transcoder, VDSC/joining uses the power well associated
+	 * with the pipe/transcoder in use. Hence another reference on the
+	 * transcoder power domain will suffice.
+	 */
+	if (cpu_transcoder == TRANSCODER_EDP)
+		return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
+	else
+		return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
+}
+
 static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
 						const struct intel_crtc_state *crtc_state)
 {
@@ -1020,6 +1038,10 @@ void intel_dsc_enable(struct intel_encoder *encoder,
 	if (!crtc_state->dsc_params.compression_enable)
 		return;
 
+	/* Enable Power wells for VDSC/joining */
+	intel_display_power_get(dev_priv,
+				intel_dsc_power_domain(crtc_state));
+
 	intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
 
 	intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
@@ -1072,4 +1094,7 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
 				  RIGHT_BRANCH_VDSC_ENABLE);
 	I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
 
+	/* Disable Power wells for VDSC/joining */
+	intel_display_power_put(dev_priv,
+				intel_dsc_power_domain(old_crtc_state));
 }
-- 
2.18.0

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Re: [PATCH v7 18/19] drm/i915/dsc: Enable and disable appropriate power wells for VDSC

[Ville Syrjälä]

On Thu, Nov 01, 2018 at 11:46:58PM -0700, Manasi Navare wrote:
> A separate power well 2 (PG2) is required for VDSC on eDP transcoder
> whereas all other transcoders use the power wells associated with the
> transcoders for VDSC.
> This patch adds a helper to obtain correct power domain depending on
> transcoder being used and enables/disables the power wells during
> VDSC enabling/disabling.
> 
> v3:
> * Call it intel_dsc_power_domain, add to
> intel_ddi_get_power_domains (Ville)
> v2:
> * Fix tabs, const crtc_state, fix comments (Ville)
> 
> Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c  |  3 ++-
>  drivers/gpu/drm/i915/intel_drv.h  |  2 ++
>  drivers/gpu/drm/i915/intel_vdsc.c | 25 +++++++++++++++++++++++++
>  3 files changed, 29 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index af12c15ed94f..c243bb3f2be9 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2124,7 +2124,8 @@ static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder,
>  	 */
>  	if (intel_crtc_has_dp_encoder(crtc_state) ||
>  	    intel_port_is_tc(dev_priv, encoder->port))
> -		domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port));
> +		domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port)) |
> +			BIT_ULL(intel_dsc_power_domain(crtc_state));

if (crtc_state->something)
	domains |= ...;

>  
>  	return domains;
>  }
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index e537561b3d40..2d41dff6eed1 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1859,6 +1859,8 @@ uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
>  /* intel_vdsc.c */
>  int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
>  				struct intel_crtc_state *pipe_config);
> +enum intel_display_power_domain
> +intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
>  
>  static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
>  {
> diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
> index 219dc1517c8a..9eae037a3b4d 100644
> --- a/drivers/gpu/drm/i915/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/intel_vdsc.c
> @@ -581,6 +581,24 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
>  	return 0;
>  }
>  
> +enum intel_display_power_domain
> +intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
> +{
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> +	/*
> +	 * On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
> +	 * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
> +	 * For any other transcoder, VDSC/joining uses the power well associated
> +	 * with the pipe/transcoder in use. Hence another reference on the
> +	 * transcoder power domain will suffice.
> +	 */
> +	if (cpu_transcoder == TRANSCODER_EDP)
> +		return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
> +	else
> +		return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
> +}
> +
>  static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
>  						const struct intel_crtc_state *crtc_state)
>  {
> @@ -1020,6 +1038,10 @@ void intel_dsc_enable(struct intel_encoder *encoder,
>  	if (!crtc_state->dsc_params.compression_enable)
>  		return;
>  
> +	/* Enable Power wells for VDSC/joining */
> +	intel_display_power_get(dev_priv,
> +				intel_dsc_power_domain(crtc_state));
> +
>  	intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
>  
>  	intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
> @@ -1072,4 +1094,7 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
>  				  RIGHT_BRANCH_VDSC_ENABLE);
>  	I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
>  
> +	/* Disable Power wells for VDSC/joining */
> +	intel_display_power_put(dev_priv,
> +				intel_dsc_power_domain(old_crtc_state));
>  }
> -- 
> 2.18.0

-- 
Ville Syrjälä
Intel
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[PATCH v7 19/19] drm/i915/dsc: Add Per connector debugfs node for DSC support/enable

[Manasi Navare]

DSC can be supported per DP connector. This patch adds a per connector
debugfs node to expose DSC support capability by the kernel.
The same node can be used from userspace to force DSC enable.

force_dsc_en written through this debugfs node is used to force
DSC even for lower resolutions.

v3:
* Combine Force_dsc_en with this patch (Ville)
v2:
* Use kstrtobool_from_user to avoid explicit error checking (Lyude)
* Rebase on drm-tip (Manasi)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Lyude Paul <lyude@redhat.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 71 ++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_dp.c     |  3 +-
 drivers/gpu/drm/i915/intel_drv.h    |  3 ++
 3 files changed, 75 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 1a4d9d996fda..fe619b54b64d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -5000,6 +5000,72 @@ static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data)
 }
 DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
 
+static int i915_dsc_support_show(struct seq_file *m, void *data)
+{
+	struct drm_connector *connector = m->private;
+	struct intel_encoder *encoder = intel_attached_encoder(connector);
+	struct intel_dp *intel_dp =
+		enc_to_intel_dp(&encoder->base);
+	struct intel_crtc *crtc;
+	struct intel_crtc_state *crtc_state;
+
+	crtc = to_intel_crtc(encoder->base.crtc);
+	crtc_state = to_intel_crtc_state(crtc->base.state);
+	drm_modeset_lock(&crtc->base.mutex, NULL);
+	seq_printf(m, "Enabled: %s\n",
+		   yesno(crtc_state->dsc_params.compression_enable));
+	seq_printf(m, "Supported: %s\n",
+		   yesno(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
+	drm_modeset_unlock(&crtc->base.mutex);
+
+	return 0;
+}
+
+static ssize_t i915_dsc_support_write(struct file *file,
+				      const char __user *ubuf,
+				      size_t len, loff_t *offp)
+{
+	bool dsc_enable = false;
+	int ret;
+	struct drm_connector *connector =
+		((struct seq_file *)file->private_data)->private;
+	struct intel_encoder *encoder = intel_attached_encoder(connector);
+	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+
+	if (len == 0)
+		return 0;
+
+	DRM_DEBUG_DRIVER("Copied %d bytes from user to force DSC\n",
+			 (unsigned int)len);
+
+	ret = kstrtobool_from_user(ubuf, len, &dsc_enable);
+	if (ret < 0)
+		return ret;
+
+	DRM_DEBUG_DRIVER("Got %s for DSC Enable\n",
+			 (dsc_enable) ? "true" : "false");
+	intel_dp->force_dsc_en = dsc_enable;
+
+	*offp += len;
+	return len;
+}
+
+static int i915_dsc_support_open(struct inode *inode,
+				 struct file *file)
+{
+	return single_open(file, i915_dsc_support_show,
+			   inode->i_private);
+}
+
+static const struct file_operations i915_dsc_support_fops = {
+	.owner = THIS_MODULE,
+	.open = i915_dsc_support_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = i915_dsc_support_write
+};
+
 /**
  * i915_debugfs_connector_add - add i915 specific connector debugfs files
  * @connector: pointer to a registered drm_connector
@@ -5018,9 +5084,12 @@ int i915_debugfs_connector_add(struct drm_connector *connector)
 		return -ENODEV;
 
 	if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
-	    connector->connector_type == DRM_MODE_CONNECTOR_eDP)
+	    connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
 		debugfs_create_file("i915_dpcd", S_IRUGO, root,
 				    connector, &i915_dpcd_fops);
+		debugfs_create_file("i915_dsc_support", S_IRUGO, root,
+				    connector, &i915_dsc_support_fops);
+	}
 
 	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
 		debugfs_create_file("i915_panel_timings", S_IRUGO, root,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4cc730e9d245..685be254347e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2155,7 +2155,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 							&limits);
 
 	/* enable compression if the mode doesn't fit available BW */
-	if (!ret) {
+	if (!ret || intel_dp->force_dsc_en) {
 		if (!intel_dp_dsc_compute_config(intel_dp, pipe_config,
 						 &limits))
 			return false;
@@ -2248,6 +2248,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 		return false;
 
+	DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp->force_dsc_en);
 	if (!intel_dp_compute_link_config(encoder, pipe_config))
 		return false;
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 2d41dff6eed1..df7b76ca3fde 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1199,6 +1199,9 @@ struct intel_dp {
 
 	/* Displayport compliance testing */
 	struct intel_dp_compliance compliance;
+
+	/* Display stream compression testing */
+	bool force_dsc_en;
 };
 
 enum lspcon_vendor {
-- 
2.18.0

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✗ Fi.CI.CHECKPATCH: warning for DSC enabling remaining patches

[Patchwork]

== Series Details ==

Series: DSC enabling remaining patches
URL   : https://patchwork.freedesktop.org/series/51916/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
318c014747fe drm/dsc: Define Display Stream Compression PPS infoframe
-:31: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#31: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 342 lines checked
6005b5b6fd09 drm/dsc: Define VESA Display Stream Compression Capabilities
-:34: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-developed-by:
#34: 
Co-developed-by: Gaurav K Singh <gaurav.k.singh@intel.com>

-:73: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#73: FILE: include/drm/drm_dsc.h:40:
+	bool convert_rgb;

-:83: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#83: FILE: include/drm/drm_dsc.h:50:
+	bool enable422;

-:108: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#108: FILE: include/drm/drm_dsc.h:75:
+	bool block_pred_enable;

-:136: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#136: FILE: include/drm/drm_dsc.h:103:
+	bool vbr_enable;

-:151: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#151: FILE: include/drm/drm_dsc.h:118:
+	bool native_422;

-:153: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#153: FILE: include/drm/drm_dsc.h:120:
+	bool native_420;

total: 0 errors, 1 warnings, 6 checks, 121 lines checked
dd95e78514f2 drm/dsc: Define Rate Control values that do not change over configurations
-:42: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Srivatsa, Anusha <anusha.srivatsa@intel.com>'

total: 0 errors, 1 warnings, 0 checks, 12 lines checked
488532545dd6 drm/dsc: Add helpers for DSC picture parameter set infoframes
-:27: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#27: 
* Add reference to added kernel-docs in Documentation/gpu/drm-kms-helpers.rst

-:78: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#78: 
new file mode 100644

total: 0 errors, 2 warnings, 0 checks, 285 lines checked
ca380ce7be74 drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
-:49: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#49: FILE: drivers/gpu/drm/i915/intel_drv.h:942:
+		bool compression_enable;

-:50: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#50: FILE: drivers/gpu/drm/i915/intel_drv.h:943:
+		bool dsc_split;

total: 0 errors, 0 warnings, 2 checks, 22 lines checked
ef64a8d0cc80 drm/i915/dp: Compute DSC pipe config in atomic check
-:163: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#163: FILE: drivers/gpu/drm/i915/intel_dp.c:1897:
+			bpp = min(bpp, 3*bpc);
 			                ^

-:292: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#292: FILE: drivers/gpu/drm/i915/intel_dp.c:2106:
+	    limits.max_bpp >= DP_DSC_MIN_SUPPORTED_BPC*3)
 	                                              ^

total: 0 errors, 0 warnings, 2 checks, 314 lines checked
74c05c0ed3b6 drm/i915/dp: Do not enable PSR2 if DSC is enabled
f5bef3714875 drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
9a5a5914e037 drm/i915/dsc: Define & Compute VESA DSC params
-:65: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-developed-by:
#65: 
Co-developed-by: Manasi Navare <manasi.d.navare@intel.com>

-:92: WARNING:MISSING_SPACE: break quoted strings at a space character
#92: FILE: drivers/gpu/drm/i915/intel_dp.c:2074:
+		DRM_ERROR("Cannot compute valid DSC parameters for Input Bpp = %d"
+			  "Compressed BPP = %d\n",

-:116: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#116: 
new file mode 100644

-:402: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#402: FILE: drivers/gpu/drm/i915/intel_vdsc.c:282:
+}
+};

total: 0 errors, 3 warnings, 1 checks, 496 lines checked
5012a28fec24 drm/i915/dsc: Compute Rate Control parameters for DSC
-:138: CHECK:SPACING: space preferred before that '*' (ctx:VxE)
#138: FILE: drivers/gpu/drm/i915/intel_vdsc.c:411:
+				vdsc_cfg->slice_bpg_offset)*
 				                           ^

-:170: CHECK:LINE_SPACING: Please don't use multiple blank lines
#170: FILE: drivers/gpu/drm/i915/intel_vdsc.c:443:
+
+

total: 0 errors, 0 warnings, 2 checks, 138 lines checked
1bbc6d669fe7 drm/i915/dp: Enable/Disable DSC in DP Sink
f4d4cef846f8 drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
47159c173f35 drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling
-:43: CHECK:AVOID_EXTERNS: extern prototypes should be avoided in .h files
#43: FILE: drivers/gpu/drm/i915/i915_drv.h:3488:
+extern void intel_dsc_enable(struct intel_encoder *encoder,

-:111: WARNING:TABSTOP: Statements should start on a tabstop
#111: FILE: drivers/gpu/drm/i915/intel_vdsc.c:621:
+	 if (cpu_transcoder == TRANSCODER_EDP) {

-:355: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#355: FILE: drivers/gpu/drm/i915/intel_vdsc.c:865:
+		rc_buf_thresh_dword[i/4] |= (u32)(vdsc_cfg->rc_buf_thresh[i] <<
 		                     ^

-:358: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#358: FILE: drivers/gpu/drm/i915/intel_vdsc.c:868:
+			 rc_buf_thresh_dword[i/4]);
 			                      ^

-:399: WARNING:LONG_LINE: line over 100 characters
#399: FILE: drivers/gpu/drm/i915/intel_vdsc.c:909:
+		rc_range_params_dword[i/2] |= (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<

-:399: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#399: FILE: drivers/gpu/drm/i915/intel_vdsc.c:909:
+		rc_range_params_dword[i/2] |= (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
 		                       ^

-:406: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#406: FILE: drivers/gpu/drm/i915/intel_vdsc.c:916:
+			 rc_range_params_dword[i/2]);
 			                        ^

-:484: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#484: FILE: drivers/gpu/drm/i915/intel_vdsc.c:994:
+{
+

-:491: WARNING:RETURN_VOID: void function return statements are not generally useful
#491: FILE: drivers/gpu/drm/i915/intel_vdsc.c:1001:
+	return;
+}

total: 0 errors, 3 warnings, 6 checks, 442 lines checked
381a0b30ab76 drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
5ca60713afaa drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
12f838b8fa8d drm/i915/dp: Configure Display stream splitter registers during DSC enable
9e8c891105fe drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
-:35: CHECK:AVOID_EXTERNS: extern prototypes should be avoided in .h files
#35: FILE: drivers/gpu/drm/i915/i915_drv.h:3490:
+extern void intel_dsc_disable(const struct intel_crtc_state *crtc_state);

-:91: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#91: FILE: drivers/gpu/drm/i915/intel_vdsc.c:1075:
+
+}

total: 0 errors, 0 warnings, 2 checks, 50 lines checked
73a2398b4b92 drm/i915/dsc: Enable and disable appropriate power wells for VDSC
4cba93695154 drm/i915/dsc: Add Per connector debugfs node for DSC support/enable
-:112: WARNING:SYMBOLIC_PERMS: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'.
#112: FILE: drivers/gpu/drm/i915/i915_debugfs.c:5090:
+		debugfs_create_file("i915_dsc_support", S_IRUGO, root,

-:149: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#149: FILE: drivers/gpu/drm/i915/intel_drv.h:1204:
+	bool force_dsc_en;

total: 0 errors, 1 warnings, 1 checks, 109 lines checked

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✗ Fi.CI.SPARSE: warning for DSC enabling remaining patches

[Patchwork]

== Series Details ==

Series: DSC enabling remaining patches
URL   : https://patchwork.freedesktop.org/series/51916/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/dsc: Define Display Stream Compression PPS infoframe
Okay!

Commit: drm/dsc: Define VESA Display Stream Compression Capabilities
Okay!

Commit: drm/dsc: Define Rate Control values that do not change over configurations
Okay!

Commit: drm/dsc: Add helpers for DSC picture parameter set infoframes
-
+drivers/gpu/drm/drm_dsc.c:200:61:    expected restricted __be16 <noident>
+drivers/gpu/drm/drm_dsc.c:200:61:    got int
+drivers/gpu/drm/drm_dsc.c:200:61: warning: incorrect type in assignment (different base types)
+drivers/gpu/drm/drm_dsc.c:207:25:    expected unsigned short [unsigned] [usertype] val
+drivers/gpu/drm/drm_dsc.c:207:25:    got restricted __be16 <noident>
+drivers/gpu/drm/drm_dsc.c:207:25: warning: cast from restricted __be16
+drivers/gpu/drm/drm_dsc.c:207:25: warning: cast from restricted __be16
+drivers/gpu/drm/drm_dsc.c:207:25: warning: cast from restricted __be16
+drivers/gpu/drm/drm_dsc.c:207:25: warning: incorrect type in argument 1 (different base types)

Commit: drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3705:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3706:16: warning: expression using sizeof(void)

Commit: drm/i915/dp: Compute DSC pipe config in atomic check
+drivers/gpu/drm/i915/intel_dp.c:1893:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:1897:31: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:1897:31: warning: expression using sizeof(void)

Commit: drm/i915/dp: Do not enable PSR2 if DSC is enabled
Okay!

Commit: drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
Okay!

Commit: drm/i915/dsc: Define & Compute VESA DSC params
+drivers/gpu/drm/i915/intel_vdsc.c:351:17: warning: expression using sizeof(void)
+./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000000000000000 becomes 0)

Commit: drm/i915/dsc: Compute Rate Control parameters for DSC
Okay!

Commit: drm/i915/dp: Enable/Disable DSC in DP Sink
Okay!

Commit: drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
Okay!

Commit: drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3706:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3708:16: warning: expression using sizeof(void)

Commit: drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
Okay!

Commit: drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
Okay!

Commit: drm/i915/dp: Configure Display stream splitter registers during DSC enable
Okay!

Commit: drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3708:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3709:16: warning: expression using sizeof(void)

Commit: drm/i915/dsc: Enable and disable appropriate power wells for VDSC
Okay!

Commit: drm/i915/dsc: Add Per connector debugfs node for DSC support/enable
Okay!

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.BAT: failure for DSC enabling remaining patches

[Patchwork]

== Series Details ==

Series: DSC enabling remaining patches
URL   : https://patchwork.freedesktop.org/series/51916/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_5074 -> Patchwork_10704 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_10704 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10704, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/51916/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10704:

  === IGT changes ===

    ==== Possible regressions ====

    igt@debugfs_test@read_all_entries:
      fi-skl-iommu:       PASS -> INCOMPLETE +1
      fi-ivb-3770:        PASS -> INCOMPLETE +1
      fi-cfl-s3:          PASS -> INCOMPLETE +1
      fi-skl-6700hq:      PASS -> INCOMPLETE +1
      fi-skl-6770hq:      PASS -> INCOMPLETE +1
      fi-skl-6260u:       PASS -> INCOMPLETE +1
      fi-snb-2600:        PASS -> INCOMPLETE +1
      fi-skl-6600u:       PASS -> INCOMPLETE
      fi-kbl-soraka:      NOTRUN -> INCOMPLETE

    igt@drv_module_reload@basic-reload:
      fi-cnl-u:           PASS -> INCOMPLETE +1
      fi-kbl-x1275:       PASS -> INCOMPLETE +1
      fi-kbl-r:           PASS -> INCOMPLETE +1
      fi-cfl-8700k:       PASS -> INCOMPLETE +1
      fi-icl-u2:          PASS -> INCOMPLETE
      fi-ivb-3520m:       PASS -> INCOMPLETE +1
      fi-hsw-4770:        PASS -> INCOMPLETE +1
      fi-bsw-n3050:       PASS -> INCOMPLETE +1
      fi-hsw-4770r:       PASS -> DMESG-WARN
      fi-bsw-kefka:       PASS -> INCOMPLETE +1
      fi-kbl-7500u:       PASS -> DMESG-WARN
      fi-kbl-7567u:       PASS -> INCOMPLETE +1
      fi-whl-u:           PASS -> INCOMPLETE +1
      fi-skl-6700k2:      PASS -> INCOMPLETE +1
      fi-hsw-peppy:       PASS -> DMESG-WARN

    igt@gem_exec_nop@basic-parallel:
      fi-icl-u:           PASS -> INCOMPLETE +2

    igt@gem_exec_suspend@basic-s3:
      fi-apl-guc:         PASS -> DMESG-WARN

    igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
      fi-icl-u2:          PASS -> FAIL +19

    igt@pm_rpm@basic-rte:
      fi-skl-guc:         PASS -> FAIL
      fi-kbl-7567u:       PASS -> FAIL
      fi-hsw-peppy:       PASS -> FAIL
      fi-kbl-r:           PASS -> FAIL
      fi-hsw-4770r:       PASS -> FAIL
      fi-cfl-s3:          PASS -> FAIL
      fi-kbl-7560u:       PASS -> FAIL
      fi-skl-6770hq:      PASS -> FAIL
      fi-skl-6600u:       PASS -> FAIL
      fi-apl-guc:         PASS -> FAIL
      fi-cnl-u:           PASS -> FAIL
      fi-kbl-7500u:       PASS -> FAIL
      fi-whl-u:           PASS -> FAIL
      fi-bxt-j4205:       PASS -> FAIL

    
    ==== Warnings ====

    igt@debugfs_test@read_all_entries:
      fi-icl-u2:          DMESG-WARN (fdo#108070) -> INCOMPLETE

    igt@pm_rpm@basic-pci-d3-state:
      fi-skl-6600u:       PASS -> SKIP
      fi-kbl-7560u:       PASS -> SKIP
      fi-whl-u:           PASS -> SKIP
      fi-apl-guc:         PASS -> SKIP
      fi-skl-6770hq:      PASS -> SKIP
      fi-bxt-j4205:       PASS -> SKIP
      fi-hsw-peppy:       PASS -> SKIP +1
      fi-kbl-r:           PASS -> SKIP
      fi-skl-guc:         PASS -> SKIP
      fi-cnl-u:           PASS -> SKIP
      fi-icl-u2:          PASS -> SKIP
      fi-cfl-s3:          PASS -> SKIP
      fi-hsw-4770r:       PASS -> SKIP +1
      fi-kbl-7567u:       PASS -> SKIP

    igt@pm_rpm@module-reload:
      fi-kbl-7500u:       PASS -> SKIP +1

    
== Known issues ==

  Here are the changes found in Patchwork_10704 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@debugfs_test@read_all_entries:
      fi-glk-dsi:         PASS -> INCOMPLETE (fdo#103359, k.org#198133) +1
      fi-bxt-j4205:       PASS -> INCOMPLETE (fdo#103927) +1
      fi-skl-gvtdvm:      PASS -> INCOMPLETE (fdo#105600) +1

    igt@drv_module_reload@basic-reload:
      fi-skl-guc:         PASS -> INCOMPLETE (fdo#106693) +1
      fi-bdw-gvtdvm:      PASS -> INCOMPLETE (fdo#105600) +1
      fi-bxt-dsi:         PASS -> INCOMPLETE (fdo#103927) +1
      fi-cfl-guc:         PASS -> INCOMPLETE (fdo#106693) +1
      fi-kbl-guc:         PASS -> INCOMPLETE (fdo#106693) +1
      fi-byt-clapper:     PASS -> INCOMPLETE (fdo#102657) +1
      fi-byt-j1900:       PASS -> INCOMPLETE (fdo#102657) +1
      fi-apl-guc:         PASS -> INCOMPLETE (fdo#103927, fdo#106693) +1
      fi-skl-6600u:       PASS -> INCOMPLETE (fdo#104108)
      fi-kbl-7560u:       PASS -> INCOMPLETE (fdo#103665) +1

    igt@gem_exec_suspend@basic-s3:
      fi-kbl-soraka:      NOTRUN -> INCOMPLETE (fdo#107859, fdo#107774, fdo#107556)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-hsw-4770r:       PASS -> DMESG-WARN (fdo#106969) +3

    
    ==== Possible fixes ====

    igt@gem_exec_suspend@basic-s3:
      fi-icl-u2:          DMESG-WARN (fdo#106612) -> PASS

    
  fdo#102657 https://bugs.freedesktop.org/show_bug.cgi?id=102657
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
  fdo#105600 https://bugs.freedesktop.org/show_bug.cgi?id=105600
  fdo#106612 https://bugs.freedesktop.org/show_bug.cgi?id=106612
  fdo#106693 https://bugs.freedesktop.org/show_bug.cgi?id=106693
  fdo#106969 https://bugs.freedesktop.org/show_bug.cgi?id=106969
  fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556
  fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774
  fdo#107859 https://bugs.freedesktop.org/show_bug.cgi?id=107859
  fdo#108070 https://bugs.freedesktop.org/show_bug.cgi?id=108070
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (44 -> 42) ==

  Additional (1): fi-kbl-soraka 
  Missing    (3): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 


== Build changes ==

    * Linux: CI_DRM_5074 -> Patchwork_10704

  CI_DRM_5074: 62b853f518dc7aaee2ef51c7633f2a03c43f1dfd @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4704: ace031dcb1e8bf2b32b4b0d54a55eb30e8f41d6f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10704: 4cba9369515401ce04bc78d357e60eb13bddeaaf @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

4cba93695154 drm/i915/dsc: Add Per connector debugfs node for DSC support/enable
73a2398b4b92 drm/i915/dsc: Enable and disable appropriate power wells for VDSC
9e8c891105fe drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
12f838b8fa8d drm/i915/dp: Configure Display stream splitter registers during DSC enable
5ca60713afaa drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
381a0b30ab76 drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
47159c173f35 drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling
f4d4cef846f8 drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
1bbc6d669fe7 drm/i915/dp: Enable/Disable DSC in DP Sink
5012a28fec24 drm/i915/dsc: Compute Rate Control parameters for DSC
9a5a5914e037 drm/i915/dsc: Define & Compute VESA DSC params
f5bef3714875 drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
74c05c0ed3b6 drm/i915/dp: Do not enable PSR2 if DSC is enabled
ef64a8d0cc80 drm/i915/dp: Compute DSC pipe config in atomic check
ca380ce7be74 drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
488532545dd6 drm/dsc: Add helpers for DSC picture parameter set infoframes
dd95e78514f2 drm/dsc: Define Rate Control values that do not change over configurations
6005b5b6fd09 drm/dsc: Define VESA Display Stream Compression Capabilities
318c014747fe drm/dsc: Define Display Stream Compression PPS infoframe

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10704/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.BAT: failure for DSC enabling remaining patches

[Patchwork]

== Series Details ==

Series: DSC enabling remaining patches
URL   : https://patchwork.freedesktop.org/series/51916/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_5079 -> Patchwork_10711 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_10711 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10711, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/51916/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10711:

  === IGT changes ===

    ==== Possible regressions ====

    igt@debugfs_test@read_all_entries:
      fi-skl-iommu:       PASS -> INCOMPLETE +1
      fi-ivb-3770:        PASS -> INCOMPLETE +1
      fi-cfl-s3:          PASS -> INCOMPLETE +1
      fi-skl-6700hq:      PASS -> INCOMPLETE +1
      fi-skl-6770hq:      PASS -> INCOMPLETE +1
      fi-skl-6260u:       PASS -> INCOMPLETE +1
      fi-snb-2600:        PASS -> INCOMPLETE +1
      fi-skl-6600u:       PASS -> INCOMPLETE
      fi-kbl-soraka:      NOTRUN -> INCOMPLETE

    igt@drv_module_reload@basic-reload:
      fi-cnl-u:           PASS -> INCOMPLETE +1
      fi-kbl-x1275:       PASS -> INCOMPLETE +1
      fi-kbl-r:           PASS -> INCOMPLETE +1
      fi-cfl-8700k:       PASS -> INCOMPLETE +1
      fi-ivb-3520m:       PASS -> INCOMPLETE +1
      fi-hsw-4770:        PASS -> INCOMPLETE +1
      fi-bsw-n3050:       PASS -> INCOMPLETE +1
      fi-hsw-4770r:       PASS -> DMESG-WARN
      fi-bsw-kefka:       PASS -> INCOMPLETE +1
      fi-kbl-7500u:       PASS -> DMESG-WARN
      fi-kbl-7567u:       PASS -> INCOMPLETE +1
      fi-cfl-8109u:       NOTRUN -> DMESG-WARN
      fi-whl-u:           PASS -> INCOMPLETE +1
      fi-skl-6700k2:      PASS -> INCOMPLETE +1
      fi-hsw-peppy:       PASS -> DMESG-WARN

    igt@gem_exec_suspend@basic-s3:
      fi-apl-guc:         PASS -> DMESG-WARN

    igt@pm_rpm@basic-rte:
      fi-skl-guc:         PASS -> FAIL
      fi-kbl-7567u:       PASS -> FAIL
      fi-hsw-peppy:       PASS -> FAIL
      fi-kbl-r:           PASS -> FAIL
      fi-hsw-4770r:       PASS -> FAIL
      fi-cfl-8109u:       NOTRUN -> FAIL
      fi-cfl-s3:          PASS -> FAIL
      fi-kbl-7560u:       PASS -> FAIL
      fi-skl-6770hq:      PASS -> FAIL
      fi-skl-6600u:       PASS -> FAIL
      fi-apl-guc:         PASS -> FAIL
      fi-cnl-u:           PASS -> FAIL
      fi-kbl-7500u:       PASS -> FAIL
      fi-whl-u:           PASS -> FAIL
      fi-bxt-j4205:       PASS -> FAIL

    
    ==== Warnings ====

    igt@pm_rpm@basic-pci-d3-state:
      fi-skl-6600u:       PASS -> SKIP
      fi-kbl-7560u:       PASS -> SKIP
      fi-whl-u:           PASS -> SKIP
      fi-apl-guc:         PASS -> SKIP
      fi-skl-6770hq:      PASS -> SKIP
      fi-bxt-j4205:       PASS -> SKIP
      fi-hsw-peppy:       PASS -> SKIP +1
      fi-kbl-r:           PASS -> SKIP
      fi-skl-guc:         PASS -> SKIP
      fi-cnl-u:           PASS -> SKIP
      fi-cfl-s3:          PASS -> SKIP
      fi-hsw-4770r:       PASS -> SKIP +1
      fi-kbl-7567u:       PASS -> SKIP

    igt@pm_rpm@module-reload:
      fi-kbl-7500u:       PASS -> SKIP +1

    
== Known issues ==

  Here are the changes found in Patchwork_10711 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@amdgpu/amd_basic@cs-compute:
      fi-kbl-8809g:       NOTRUN -> FAIL (fdo#108094)

    igt@amdgpu/amd_prime@amd-to-i915:
      fi-kbl-8809g:       NOTRUN -> FAIL (fdo#107341)

    igt@debugfs_test@read_all_entries:
      fi-glk-dsi:         PASS -> INCOMPLETE (k.org#198133, fdo#103359) +1
      fi-bxt-j4205:       PASS -> INCOMPLETE (fdo#103927) +1
      fi-elk-e7500:       NOTRUN -> INCOMPLETE (fdo#103989) +1
      fi-skl-gvtdvm:      PASS -> INCOMPLETE (fdo#105600) +1

    igt@drv_module_reload@basic-reload:
      fi-skl-guc:         PASS -> INCOMPLETE (fdo#106693) +1
      fi-bdw-gvtdvm:      PASS -> INCOMPLETE (fdo#105600) +1
      fi-bxt-dsi:         PASS -> INCOMPLETE (fdo#103927) +1
      fi-cfl-guc:         PASS -> INCOMPLETE (fdo#106693) +1
      fi-kbl-guc:         PASS -> INCOMPLETE (fdo#106693) +1
      fi-byt-clapper:     PASS -> INCOMPLETE (fdo#102657) +1
      fi-byt-j1900:       PASS -> INCOMPLETE (fdo#102657) +1
      fi-apl-guc:         PASS -> INCOMPLETE (fdo#103927, fdo#106693) +1
      fi-skl-6600u:       PASS -> INCOMPLETE (fdo#104108)
      fi-kbl-7560u:       PASS -> INCOMPLETE (fdo#103665) +1

    igt@gem_exec_suspend@basic-s3:
      fi-kbl-soraka:      NOTRUN -> INCOMPLETE (fdo#107859, fdo#107556, fdo#107774)

    igt@kms_flip@basic-flip-vs-dpms:
      fi-skl-6700hq:      PASS -> DMESG-WARN (fdo#105998)

    igt@kms_pipe_crc_basic@read-crc-pipe-b:
      fi-byt-clapper:     PASS -> FAIL (fdo#107362)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
      fi-byt-clapper:     PASS -> FAIL (fdo#103191, fdo#107362)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-hsw-4770r:       PASS -> DMESG-WARN (fdo#106969) +3

    
    ==== Possible fixes ====

    igt@drv_module_reload@basic-reload:
      fi-glk-j4005:       DMESG-WARN (fdo#106725, fdo#106248) -> PASS

    igt@kms_flip@basic-flip-vs-wf_vblank:
      fi-glk-j4005:       FAIL (fdo#100368) -> PASS

    igt@kms_frontbuffer_tracking@basic:
      fi-byt-clapper:     FAIL (fdo#103167) -> PASS

    igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence:
      fi-byt-clapper:     FAIL (fdo#103191, fdo#107362) -> PASS

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102657 https://bugs.freedesktop.org/show_bug.cgi?id=102657
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
  fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
  fdo#105600 https://bugs.freedesktop.org/show_bug.cgi?id=105600
  fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
  fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248
  fdo#106693 https://bugs.freedesktop.org/show_bug.cgi?id=106693
  fdo#106725 https://bugs.freedesktop.org/show_bug.cgi?id=106725
  fdo#106969 https://bugs.freedesktop.org/show_bug.cgi?id=106969
  fdo#107341 https://bugs.freedesktop.org/show_bug.cgi?id=107341
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556
  fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774
  fdo#107859 https://bugs.freedesktop.org/show_bug.cgi?id=107859
  fdo#108094 https://bugs.freedesktop.org/show_bug.cgi?id=108094
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (47 -> 44) ==

  Additional (4): fi-kbl-soraka fi-kbl-8809g fi-cfl-8109u fi-elk-e7500 
  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-ctg-p8600 fi-icl-u 


== Build changes ==

    * Linux: CI_DRM_5079 -> Patchwork_10711

  CI_DRM_5079: fc3d54b430337be9c61a524c65b521761d6664a8 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4704: ace031dcb1e8bf2b32b4b0d54a55eb30e8f41d6f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10711: 27f9f7d9fce042b5008b0fb3169c3d361b70b5fa @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

27f9f7d9fce0 drm/i915/dsc: Add Per connector debugfs node for DSC support/enable
bed47323e573 drm/i915/dsc: Enable and disable appropriate power wells for VDSC
ede63211a4e2 drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
b40d169bae6e drm/i915/dp: Configure Display stream splitter registers during DSC enable
eefc1b9643df drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
73dc0ab3cb56 drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
524b937fef2a drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling
59f31c5fd7a4 drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
ae468c1bde5a drm/i915/dp: Enable/Disable DSC in DP Sink
0ee2c23f4a8d drm/i915/dsc: Compute Rate Control parameters for DSC
bef342f7bbc7 drm/i915/dsc: Define & Compute VESA DSC params
a24c42a30667 drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
ffb5e8513e3f drm/i915/dp: Do not enable PSR2 if DSC is enabled
c67bf23cad51 drm/i915/dp: Compute DSC pipe config in atomic check
94c8aec279fa drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
525fa6a763a6 drm/dsc: Add helpers for DSC picture parameter set infoframes
511ecb3ecccc drm/dsc: Define Rate Control values that do not change over configurations
a763e1a1dfb7 drm/dsc: Define VESA Display Stream Compression Capabilities
3b7e0a91c614 drm/dsc: Define Display Stream Compression PPS infoframe

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10711/issues.html
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Re: [PATCH v7 00/19] DSC enabling remaining patches

[Ville Syrjälä]

On Thu, Nov 01, 2018 at 11:46:40PM -0700, Manasi Navare wrote:
> This patch series addresses review comments on previous DSC series:
> 
> https://patchwork.freedesktop.org/series/47514/
> 
> Gaurav K Singh (3):
>   drm/i915/dsc: Define & Compute VESA DSC params
>   drm/i915/dsc: Compute Rate Control parameters for DSC
>   drm/i915/dp: Enable/Disable DSC in DP Sink
> 
> Manasi Navare (15):
>   drm/dsc: Define Display Stream Compression PPS infoframe
>   drm/dsc: Define VESA Display Stream Compression Capabilities
>   drm/dsc: Add helpers for DSC picture parameter set infoframes
>   drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
>   drm/i915/dp: Compute DSC pipe config in atomic check
>   drm/i915/dp: Do not enable PSR2 if DSC is enabled
>   drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
>   drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
>   drm/i915/dp: Configure i915 Picture parameter Set registers during DSC
>     enabling
>   drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
>   drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
>   drm/i915/dp: Configure Display stream splitter registers during DSC
>     enable
>   drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
>   drm/i915/dsc: Enable and disable appropriate power wells for VDSC
>   drm/i915/dsc: Add Per connector debugfs node for DSC support/enable
> 
> Srivatsa, Anusha (1):
>   drm/dsc: Define Rate Control values that do not change over
>     configurations

I think we have these real functional issues left:
- no FEC so should reject DSC on external DP
- get_power_domains() thing wasn't right

The potentially user triggerable DRM_ERROR()s have to be
removed or explained why they can't happen (in which case
a WARN() would probably be a more clear hint to the reader).

The intel_dsc_enable() call I definitely would like see
moved into the encoder->per_enable(). No one will think to
look for it in the current location.

The i915_modparams.enable_psr change seemed unrelated, but
no idea if it's intentional or not.

And finally there were various style nits that are optional.
But I would recomment doing them since it's trivial stuff and
avoids further churn in the code later.

I think that's about it really.

> 
>  Documentation/gpu/drm-kms-helpers.rst   |   12 +
>  drivers/gpu/drm/Makefile                |    2 +-
>  drivers/gpu/drm/drm_dsc.c               |  228 +++++
>  drivers/gpu/drm/i915/Makefile           |    3 +-
>  drivers/gpu/drm/i915/i915_debugfs.c     |   71 +-
>  drivers/gpu/drm/i915/i915_drv.h         |    4 +
>  drivers/gpu/drm/i915/i915_reg.h         |    1 +
>  drivers/gpu/drm/i915/intel_ddi.c        |    8 +-
>  drivers/gpu/drm/i915/intel_display.c    |   28 +-
>  drivers/gpu/drm/i915/intel_display.h    |    4 +-
>  drivers/gpu/drm/i915/intel_dp.c         |  196 +++-
>  drivers/gpu/drm/i915/intel_dp_mst.c     |    2 +-
>  drivers/gpu/drm/i915/intel_drv.h        |   21 +
>  drivers/gpu/drm/i915/intel_hdmi.c       |   21 +-
>  drivers/gpu/drm/i915/intel_psr.c        |   16 +-
>  drivers/gpu/drm/i915/intel_runtime_pm.c |    4 +-
>  drivers/gpu/drm/i915/intel_vdsc.c       | 1100 +++++++++++++++++++++++
>  include/drm/drm_dp_helper.h             |    3 +
>  include/drm/drm_dsc.h                   |  485 ++++++++++
>  19 files changed, 2169 insertions(+), 40 deletions(-)
>  create mode 100644 drivers/gpu/drm/drm_dsc.c
>  create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c
>  create mode 100644 include/drm/drm_dsc.h
> 
> -- 
> 2.18.0
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
Ville Syrjälä
Intel
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Re: [PATCH v7 00/19] DSC enabling remaining patches

[Manasi Navare]

Thanks Ville for this detailed review. I will spin this now
with the required fixes and send it over.

Manasi

On Fri, Nov 02, 2018 at 08:06:04PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 01, 2018 at 11:46:40PM -0700, Manasi Navare wrote:
> > This patch series addresses review comments on previous DSC series:
> > 
> > https://patchwork.freedesktop.org/series/47514/
> > 
> > Gaurav K Singh (3):
> >   drm/i915/dsc: Define & Compute VESA DSC params
> >   drm/i915/dsc: Compute Rate Control parameters for DSC
> >   drm/i915/dp: Enable/Disable DSC in DP Sink
> > 
> > Manasi Navare (15):
> >   drm/dsc: Define Display Stream Compression PPS infoframe
> >   drm/dsc: Define VESA Display Stream Compression Capabilities
> >   drm/dsc: Add helpers for DSC picture parameter set infoframes
> >   drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
> >   drm/i915/dp: Compute DSC pipe config in atomic check
> >   drm/i915/dp: Do not enable PSR2 if DSC is enabled
> >   drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
> >   drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
> >   drm/i915/dp: Configure i915 Picture parameter Set registers during DSC
> >     enabling
> >   drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
> >   drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
> >   drm/i915/dp: Configure Display stream splitter registers during DSC
> >     enable
> >   drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
> >   drm/i915/dsc: Enable and disable appropriate power wells for VDSC
> >   drm/i915/dsc: Add Per connector debugfs node for DSC support/enable
> > 
> > Srivatsa, Anusha (1):
> >   drm/dsc: Define Rate Control values that do not change over
> >     configurations
> 
> I think we have these real functional issues left:
> - no FEC so should reject DSC on external DP
> - get_power_domains() thing wasn't right
> 
> The potentially user triggerable DRM_ERROR()s have to be
> removed or explained why they can't happen (in which case
> a WARN() would probably be a more clear hint to the reader).
> 
> The intel_dsc_enable() call I definitely would like see
> moved into the encoder->per_enable(). No one will think to
> look for it in the current location.
> 
> The i915_modparams.enable_psr change seemed unrelated, but
> no idea if it's intentional or not.
> 
> And finally there were various style nits that are optional.
> But I would recomment doing them since it's trivial stuff and
> avoids further churn in the code later.
> 
> I think that's about it really.
> 
> > 
> >  Documentation/gpu/drm-kms-helpers.rst   |   12 +
> >  drivers/gpu/drm/Makefile                |    2 +-
> >  drivers/gpu/drm/drm_dsc.c               |  228 +++++
> >  drivers/gpu/drm/i915/Makefile           |    3 +-
> >  drivers/gpu/drm/i915/i915_debugfs.c     |   71 +-
> >  drivers/gpu/drm/i915/i915_drv.h         |    4 +
> >  drivers/gpu/drm/i915/i915_reg.h         |    1 +
> >  drivers/gpu/drm/i915/intel_ddi.c        |    8 +-
> >  drivers/gpu/drm/i915/intel_display.c    |   28 +-
> >  drivers/gpu/drm/i915/intel_display.h    |    4 +-
> >  drivers/gpu/drm/i915/intel_dp.c         |  196 +++-
> >  drivers/gpu/drm/i915/intel_dp_mst.c     |    2 +-
> >  drivers/gpu/drm/i915/intel_drv.h        |   21 +
> >  drivers/gpu/drm/i915/intel_hdmi.c       |   21 +-
> >  drivers/gpu/drm/i915/intel_psr.c        |   16 +-
> >  drivers/gpu/drm/i915/intel_runtime_pm.c |    4 +-
> >  drivers/gpu/drm/i915/intel_vdsc.c       | 1100 +++++++++++++++++++++++
> >  include/drm/drm_dp_helper.h             |    3 +
> >  include/drm/drm_dsc.h                   |  485 ++++++++++
> >  19 files changed, 2169 insertions(+), 40 deletions(-)
> >  create mode 100644 drivers/gpu/drm/drm_dsc.c
> >  create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c
> >  create mode 100644 include/drm/drm_dsc.h
> > 
> > -- 
> > 2.18.0
> > 
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
> 
> -- 
> Ville Syrjälä
> Intel
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