* [PATCH 2/9] drm/i915/ehl: Add ElkhartLake platform
2019-03-13 21:11 [PATCH 1/9] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
@ 2019-03-13 21:11 ` Rodrigo Vivi
2019-03-14 20:45 ` Souza, Jose
2019-03-14 22:53 ` Lucas De Marchi
2019-03-13 21:11 ` [PATCH 3/9] drm/i915/ehl: ehl and icl are both gen11 Rodrigo Vivi
` (13 subsequent siblings)
14 siblings, 2 replies; 36+ messages in thread
From: Rodrigo Vivi @ 2019-03-13 21:11 UTC (permalink / raw)
To: intel-gfx
From: Bob Paauwe <bob.j.paauwe@intel.com>
Add ElkhartLake as a unique platform as there are some differences
between it and Icelake.
Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
4 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0ed6e871f609..5c61f9d0dfad 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2314,6 +2314,7 @@ static inline unsigned int i915_sg_segment_size(void)
#define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
#define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
+#define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
#define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d4d3a904950c..6b36bb0e5e0b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -726,7 +726,7 @@ static const struct intel_device_info intel_icelake_11_info = {
static const struct intel_device_info intel_elkhartlake_info = {
GEN11_FEATURES,
- PLATFORM(INTEL_ICELAKE),
+ PLATFORM(INTEL_ELKHARTLAKE),
.num_pipes = 3,
.is_alpha_support = 1,
.engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0),
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index aac19b1c419c..c8c0f4134bdb 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -57,6 +57,7 @@ static const char * const platform_names[] = {
PLATFORM_NAME(COFFEELAKE),
PLATFORM_NAME(CANNONLAKE),
PLATFORM_NAME(ICELAKE),
+ PLATFORM_NAME(ELKHARTLAKE),
};
#undef PLATFORM_NAME
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 047d10bdd455..f7b174e7ba82 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -73,6 +73,7 @@ enum intel_platform {
INTEL_CANNONLAKE,
/* gen11 */
INTEL_ICELAKE,
+ INTEL_ELKHARTLAKE,
INTEL_MAX_PLATFORMS
};
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH 2/9] drm/i915/ehl: Add ElkhartLake platform
2019-03-13 21:11 ` [PATCH 2/9] drm/i915/ehl: Add ElkhartLake platform Rodrigo Vivi
@ 2019-03-14 20:45 ` Souza, Jose
2019-03-14 22:53 ` Lucas De Marchi
1 sibling, 0 replies; 36+ messages in thread
From: Souza, Jose @ 2019-03-14 20:45 UTC (permalink / raw)
To: Vivi, Rodrigo, intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 2890 bytes --]
On Wed, 2019-03-13 at 14:11 -0700, Rodrigo Vivi wrote:
> From: Bob Paauwe <bob.j.paauwe@intel.com>
>
> Add ElkhartLake as a unique platform as there are some differences
> between it and Icelake.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_pci.c | 2 +-
> drivers/gpu/drm/i915/intel_device_info.c | 1 +
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> 4 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 0ed6e871f609..5c61f9d0dfad 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2314,6 +2314,7 @@ static inline unsigned int
> i915_sg_segment_size(void)
> #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv,
> INTEL_COFFEELAKE)
> #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv,
> INTEL_CANNONLAKE)
> #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
> +#define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv,
> INTEL_ELKHARTLAKE)
> #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0xFF00) ==
> 0x0C00)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c
> b/drivers/gpu/drm/i915/i915_pci.c
> index d4d3a904950c..6b36bb0e5e0b 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -726,7 +726,7 @@ static const struct intel_device_info
> intel_icelake_11_info = {
>
> static const struct intel_device_info intel_elkhartlake_info = {
> GEN11_FEATURES,
> - PLATFORM(INTEL_ICELAKE),
> + PLATFORM(INTEL_ELKHARTLAKE),
> .num_pipes = 3,
> .is_alpha_support = 1,
> .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0),
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index aac19b1c419c..c8c0f4134bdb 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -57,6 +57,7 @@ static const char * const platform_names[] = {
> PLATFORM_NAME(COFFEELAKE),
> PLATFORM_NAME(CANNONLAKE),
> PLATFORM_NAME(ICELAKE),
> + PLATFORM_NAME(ELKHARTLAKE),
> };
> #undef PLATFORM_NAME
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 047d10bdd455..f7b174e7ba82 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -73,6 +73,7 @@ enum intel_platform {
> INTEL_CANNONLAKE,
> /* gen11 */
> INTEL_ICELAKE,
> + INTEL_ELKHARTLAKE,
> INTEL_MAX_PLATFORMS
> };
>
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 2/9] drm/i915/ehl: Add ElkhartLake platform
2019-03-13 21:11 ` [PATCH 2/9] drm/i915/ehl: Add ElkhartLake platform Rodrigo Vivi
2019-03-14 20:45 ` Souza, Jose
@ 2019-03-14 22:53 ` Lucas De Marchi
1 sibling, 0 replies; 36+ messages in thread
From: Lucas De Marchi @ 2019-03-14 22:53 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Wed, Mar 13, 2019 at 02:11:37PM -0700, Rodrigo Vivi wrote:
>From: Bob Paauwe <bob.j.paauwe@intel.com>
>
>Add ElkhartLake as a unique platform as there are some differences
>between it and Icelake.
>
>Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_pci.c | 2 +-
> drivers/gpu/drm/i915/intel_device_info.c | 1 +
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> 4 files changed, 4 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 0ed6e871f609..5c61f9d0dfad 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -2314,6 +2314,7 @@ static inline unsigned int i915_sg_segment_size(void)
> #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
> #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
> #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
>+#define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
> #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
>diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>index d4d3a904950c..6b36bb0e5e0b 100644
>--- a/drivers/gpu/drm/i915/i915_pci.c
>+++ b/drivers/gpu/drm/i915/i915_pci.c
>@@ -726,7 +726,7 @@ static const struct intel_device_info intel_icelake_11_info = {
>
> static const struct intel_device_info intel_elkhartlake_info = {
> GEN11_FEATURES,
>- PLATFORM(INTEL_ICELAKE),
>+ PLATFORM(INTEL_ELKHARTLAKE),
> .num_pipes = 3,
> .is_alpha_support = 1,
> .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0),
>diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>index aac19b1c419c..c8c0f4134bdb 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.c
>+++ b/drivers/gpu/drm/i915/intel_device_info.c
>@@ -57,6 +57,7 @@ static const char * const platform_names[] = {
> PLATFORM_NAME(COFFEELAKE),
> PLATFORM_NAME(CANNONLAKE),
> PLATFORM_NAME(ICELAKE),
>+ PLATFORM_NAME(ELKHARTLAKE),
> };
> #undef PLATFORM_NAME
>
>diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>index 047d10bdd455..f7b174e7ba82 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.h
>+++ b/drivers/gpu/drm/i915/intel_device_info.h
>@@ -73,6 +73,7 @@ enum intel_platform {
> INTEL_CANNONLAKE,
> /* gen11 */
> INTEL_ICELAKE,
>+ INTEL_ELKHARTLAKE,
> INTEL_MAX_PLATFORMS
> };
>
>--
>2.20.1
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 3/9] drm/i915/ehl: ehl and icl are both gen11
2019-03-13 21:11 [PATCH 1/9] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
2019-03-13 21:11 ` [PATCH 2/9] drm/i915/ehl: Add ElkhartLake platform Rodrigo Vivi
@ 2019-03-13 21:11 ` Rodrigo Vivi
2019-03-14 21:11 ` Souza, Jose
2019-03-14 22:59 ` Lucas De Marchi
2019-03-13 21:11 ` [PATCH 4/9] drm/i915/ehl: Add dpll mgr Rodrigo Vivi
` (12 subsequent siblings)
14 siblings, 2 replies; 36+ messages in thread
From: Rodrigo Vivi @ 2019-03-13 21:11 UTC (permalink / raw)
To: intel-gfx
From: Bob Paauwe <bob.j.paauwe@intel.com>
Most of the conditional code for ICELAKE also applies to ELKHARTLAKE
so use IS_GEN(dev_priv, 11) even for PM and Workarounds for now.
Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 4 ++--
drivers/gpu/drm/i915/intel_workarounds.c | 8 ++++----
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d73b13ca57a0..61c581e33fe3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9468,7 +9468,7 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
*/
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_ICELAKE(dev_priv))
+ if (IS_GEN(dev_priv, 11))
dev_priv->display.init_clock_gating = icl_init_clock_gating;
else if (IS_CANNONLAKE(dev_priv))
dev_priv->display.init_clock_gating = cnl_init_clock_gating;
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 676a89bb8194..1f063c761f35 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3442,7 +3442,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
* The enabling order will be from lower to higher indexed wells,
* the disabling order is reversed.
*/
- if (IS_ICELAKE(dev_priv)) {
+ if (IS_GEN(dev_priv, 11)) {
err = set_power_wells(power_domains, icl_power_wells);
} else if (IS_CANNONLAKE(dev_priv)) {
err = set_power_wells(power_domains, cnl_power_wells);
@@ -4203,7 +4203,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
intel_power_domains_verify_state(i915);
}
- if (IS_ICELAKE(i915))
+ if (IS_GEN(i915, 11))
icl_display_core_uninit(i915);
else if (IS_CANNONLAKE(i915))
cnl_display_core_uninit(i915);
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 283e9a4ef3ca..2128cb6cf8c8 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -569,7 +569,7 @@ void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
wa_init_start(wal, "context");
- if (IS_ICELAKE(i915))
+ if (IS_GEN(i915, 11))
icl_ctx_workarounds_init(engine);
else if (IS_CANNONLAKE(i915))
cnl_ctx_workarounds_init(engine);
@@ -867,7 +867,7 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
static void
gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
- if (IS_ICELAKE(i915))
+ if (IS_GEN(i915, 11))
icl_gt_workarounds_init(i915, wal);
else if (IS_CANNONLAKE(i915))
cnl_gt_workarounds_init(i915, wal);
@@ -1064,7 +1064,7 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
wa_init_start(w, "whitelist");
- if (IS_ICELAKE(i915))
+ if (IS_GEN(i915, 11))
icl_whitelist_build(w);
else if (IS_CANNONLAKE(i915))
cnl_whitelist_build(w);
@@ -1112,7 +1112,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
- if (IS_ICELAKE(i915)) {
+ if (IS_GEN(i915, 11)) {
/* This is not an Wa. Enable for better image quality */
wa_masked_en(wal,
_3D_CHICKEN3,
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH 3/9] drm/i915/ehl: ehl and icl are both gen11
2019-03-13 21:11 ` [PATCH 3/9] drm/i915/ehl: ehl and icl are both gen11 Rodrigo Vivi
@ 2019-03-14 21:11 ` Souza, Jose
2019-04-05 0:38 ` Lucas De Marchi
2019-03-14 22:59 ` Lucas De Marchi
1 sibling, 1 reply; 36+ messages in thread
From: Souza, Jose @ 2019-03-14 21:11 UTC (permalink / raw)
To: Vivi, Rodrigo, intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 7233 bytes --]
Maybe rename the commit message to "drm/i915/ehl: Inherit ICELAKE
conditional code"?
Also there a few important places that this patch and this series is
missing:
diff --git a/drivers/gpu/drm/i915/i915_drv.c
b/drivers/gpu/drm/i915/i915_drv.c
index 0d743907e7bc..52ff142628d7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -190,7 +190,7 @@ intel_pch_type(const struct drm_i915_private
*dev_priv, unsigned short id)
return PCH_CNP;
case INTEL_PCH_ICP_DEVICE_ID_TYPE:
DRM_DEBUG_KMS("Found Ice Lake PCH\n");
- WARN_ON(!IS_ICELAKE(dev_priv));
+ WARN_ON(!IS_GEN(dev_priv, 11));
return PCH_ICP;
default:
return PCH_NONE;
@@ -219,7 +219,7 @@ intel_virt_detect_pch(const struct drm_i915_private
*dev_priv)
* make an educated guess as to which PCH is really there.
*/
- if (IS_ICELAKE(dev_priv))
+ if (IS_GEN(dev_priv, 11))
id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
else if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
diff --git a/drivers/gpu/drm/i915/intel_opregion.c
b/drivers/gpu/drm/i915/intel_opregion.c
index 5437effcb396..94511fc8b10f 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -973,9 +973,10 @@ int intel_opregion_setup(struct drm_i915_private
*dev_priv)
* opregion 2.1+: rvda is unsigned, relative offset
from
* opregion base, and should never point within
opregion.
*/
+ /* Just not sure about this one */
if (opregion->header->over.major > 2 ||
opregion->header->over.minor >= 1 ||
- IS_ICELAKE(dev_priv)) {
+ IS_GEN(dev_priv, 11)) {
WARN_ON(rvda < OPREGION_SIZE);
rvda += asls;
diff --git a/drivers/gpu/drm/i915/intel_pm.c
b/drivers/gpu/drm/i915/intel_pm.c
index 61c581e33fe3..f6fe44705b4e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4473,10 +4473,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
*cstate,
memset(&wm->wm[level], 0, sizeof(wm-
>wm[level]));
/*
- * Wa_1408961008:icl
+ * Wa_1408961008:icl,ehl
* Underruns with WM1+ disabled
*/
- if (IS_ICELAKE(dev_priv) &&
+ if (IS_GEN(dev_priv, 11) &&
level == 1 && wm->wm[0].plane_en) {
wm->wm[level].plane_res_b = wm-
>wm[0].plane_res_b;
wm->wm[level].plane_res_l = wm-
>wm[0].plane_res_l;
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 1f063c761f35..fdabb15a9672 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -703,8 +703,8 @@ icl_combo_phy_aux_power_well_enable(struct
drm_i915_private *dev_priv,
hsw_wait_for_power_well_enable(dev_priv, power_well);
- /* Display WA #1178: icl */
- if (IS_ICELAKE(dev_priv) &&
+ /* Display WA #1178: icl,ehl */
+ if (IS_GEN(dev_priv, 11) &&
pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <=
ICL_PW_CTL_IDX_AUX_B &&
!intel_bios_is_port_edp(dev_priv, port)) {
val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx));
@@ -4055,7 +4055,7 @@ void intel_power_domains_init_hw(struct
drm_i915_private *i915, bool resume)
power_domains->initializing = true;
- if (IS_ICELAKE(i915)) {
+ if (IS_GEN(i915, 11)) {
icl_display_core_init(i915, resume);
} else if (IS_CANNONLAKE(i915)) {
cnl_display_core_init(i915, resume);
On Wed, 2019-03-13 at 14:11 -0700, Rodrigo Vivi wrote:
> From: Bob Paauwe <bob.j.paauwe@intel.com>
>
> Most of the conditional code for ICELAKE also applies to ELKHARTLAKE
> so use IS_GEN(dev_priv, 11) even for PM and Workarounds for now.
>
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> drivers/gpu/drm/i915/intel_runtime_pm.c | 4 ++--
> drivers/gpu/drm/i915/intel_workarounds.c | 8 ++++----
> 3 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index d73b13ca57a0..61c581e33fe3 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -9468,7 +9468,7 @@ static void nop_init_clock_gating(struct
> drm_i915_private *dev_priv)
> */
> void intel_init_clock_gating_hooks(struct drm_i915_private
> *dev_priv)
> {
> - if (IS_ICELAKE(dev_priv))
> + if (IS_GEN(dev_priv, 11))
> dev_priv->display.init_clock_gating =
> icl_init_clock_gating;
> else if (IS_CANNONLAKE(dev_priv))
> dev_priv->display.init_clock_gating =
> cnl_init_clock_gating;
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 676a89bb8194..1f063c761f35 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -3442,7 +3442,7 @@ int intel_power_domains_init(struct
> drm_i915_private *dev_priv)
> * The enabling order will be from lower to higher indexed
> wells,
> * the disabling order is reversed.
> */
> - if (IS_ICELAKE(dev_priv)) {
> + if (IS_GEN(dev_priv, 11)) {
> err = set_power_wells(power_domains, icl_power_wells);
> } else if (IS_CANNONLAKE(dev_priv)) {
> err = set_power_wells(power_domains, cnl_power_wells);
> @@ -4203,7 +4203,7 @@ void intel_power_domains_suspend(struct
> drm_i915_private *i915,
> intel_power_domains_verify_state(i915);
> }
>
> - if (IS_ICELAKE(i915))
> + if (IS_GEN(i915, 11))
> icl_display_core_uninit(i915);
> else if (IS_CANNONLAKE(i915))
> cnl_display_core_uninit(i915);
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
> b/drivers/gpu/drm/i915/intel_workarounds.c
> index 283e9a4ef3ca..2128cb6cf8c8 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -569,7 +569,7 @@ void intel_engine_init_ctx_wa(struct
> intel_engine_cs *engine)
>
> wa_init_start(wal, "context");
>
> - if (IS_ICELAKE(i915))
> + if (IS_GEN(i915, 11))
> icl_ctx_workarounds_init(engine);
> else if (IS_CANNONLAKE(i915))
> cnl_ctx_workarounds_init(engine);
> @@ -867,7 +867,7 @@ icl_gt_workarounds_init(struct drm_i915_private
> *i915, struct i915_wa_list *wal)
> static void
> gt_init_workarounds(struct drm_i915_private *i915, struct
> i915_wa_list *wal)
> {
> - if (IS_ICELAKE(i915))
> + if (IS_GEN(i915, 11))
> icl_gt_workarounds_init(i915, wal);
> else if (IS_CANNONLAKE(i915))
> cnl_gt_workarounds_init(i915, wal);
> @@ -1064,7 +1064,7 @@ void intel_engine_init_whitelist(struct
> intel_engine_cs *engine)
>
> wa_init_start(w, "whitelist");
>
> - if (IS_ICELAKE(i915))
> + if (IS_GEN(i915, 11))
> icl_whitelist_build(w);
> else if (IS_CANNONLAKE(i915))
> cnl_whitelist_build(w);
> @@ -1112,7 +1112,7 @@ rcs_engine_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_list *wal)
> {
> struct drm_i915_private *i915 = engine->i915;
>
> - if (IS_ICELAKE(i915)) {
> + if (IS_GEN(i915, 11)) {
> /* This is not an Wa. Enable for better image quality
> */
> wa_masked_en(wal,
> _3D_CHICKEN3,
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH 3/9] drm/i915/ehl: ehl and icl are both gen11
2019-03-14 21:11 ` Souza, Jose
@ 2019-04-05 0:38 ` Lucas De Marchi
0 siblings, 0 replies; 36+ messages in thread
From: Lucas De Marchi @ 2019-04-05 0:38 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
On Thu, Mar 14, 2019 at 2:11 PM Souza, Jose <jose.souza@intel.com> wrote:
>
> Maybe rename the commit message to "drm/i915/ehl: Inherit ICELAKE
> conditional code"?
>
> Also there a few important places that this patch and this series is
> missing:
>
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> b/drivers/gpu/drm/i915/i915_drv.c
> index 0d743907e7bc..52ff142628d7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -190,7 +190,7 @@ intel_pch_type(const struct drm_i915_private
> *dev_priv, unsigned short id)
> return PCH_CNP;
> case INTEL_PCH_ICP_DEVICE_ID_TYPE:
> DRM_DEBUG_KMS("Found Ice Lake PCH\n");
> - WARN_ON(!IS_ICELAKE(dev_priv));
> + WARN_ON(!IS_GEN(dev_priv, 11));
EHL doesn't use ICP. Support for its PCH will come soon.
> return PCH_ICP;
> default:
> return PCH_NONE;
> @@ -219,7 +219,7 @@ intel_virt_detect_pch(const struct drm_i915_private
> *dev_priv)
> * make an educated guess as to which PCH is really there.
> */
>
> - if (IS_ICELAKE(dev_priv))
> + if (IS_GEN(dev_priv, 11))
ditto
> id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
> else if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
> id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
> diff --git a/drivers/gpu/drm/i915/intel_opregion.c
> b/drivers/gpu/drm/i915/intel_opregion.c
> index 5437effcb396..94511fc8b10f 100644
> --- a/drivers/gpu/drm/i915/intel_opregion.c
> +++ b/drivers/gpu/drm/i915/intel_opregion.c
> @@ -973,9 +973,10 @@ int intel_opregion_setup(struct drm_i915_private
> *dev_priv)
> * opregion 2.1+: rvda is unsigned, relative offset
> from
> * opregion base, and should never point within
> opregion.
> */
> + /* Just not sure about this one */
> if (opregion->header->over.major > 2 ||
> opregion->header->over.minor >= 1 ||
> - IS_ICELAKE(dev_priv)) {
> + IS_GEN(dev_priv, 11)) {
> WARN_ON(rvda < OPREGION_SIZE);
doesn't match code
>
> rvda += asls;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 61c581e33fe3..f6fe44705b4e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4473,10 +4473,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> *cstate,
> memset(&wm->wm[level], 0, sizeof(wm-
> >wm[level]));
>
> /*
> - * Wa_1408961008:icl
> + * Wa_1408961008:icl,ehl
> * Underruns with WM1+ disabled
> */
> - if (IS_ICELAKE(dev_priv) &&
> + if (IS_GEN(dev_priv, 11) &&
yes, this is missing. spec does say this also applied here
> level == 1 && wm->wm[0].plane_en) {
> wm->wm[level].plane_res_b = wm-
> >wm[0].plane_res_b;
> wm->wm[level].plane_res_l = wm-
> >wm[0].plane_res_l;
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 1f063c761f35..fdabb15a9672 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -703,8 +703,8 @@ icl_combo_phy_aux_power_well_enable(struct
> drm_i915_private *dev_priv,
>
> hsw_wait_for_power_well_enable(dev_priv, power_well);
>
> - /* Display WA #1178: icl */
> - if (IS_ICELAKE(dev_priv) &&
> + /* Display WA #1178: icl,ehl */
> + if (IS_GEN(dev_priv, 11) &&
I'm not sure this applies to EHL.
> pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <=
> ICL_PW_CTL_IDX_AUX_B &&
> !intel_bios_is_port_edp(dev_priv, port)) {
> val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx));
> @@ -4055,7 +4055,7 @@ void intel_power_domains_init_hw(struct
> drm_i915_private *i915, bool resume)
>
> power_domains->initializing = true;
>
> - if (IS_ICELAKE(i915)) {
> + if (IS_GEN(i915, 11)) {
this should be INTEL_GEN(i915) >= 11, to match the current trend of
assuming it's the same for next platform.
/me removes his previous r-b.
Lucas De Marchi
> icl_display_core_init(i915, resume);
> } else if (IS_CANNONLAKE(i915)) {
> cnl_display_core_init(i915, resume);
>
>
>
>
>
> On Wed, 2019-03-13 at 14:11 -0700, Rodrigo Vivi wrote:
> > From: Bob Paauwe <bob.j.paauwe@intel.com>
> >
> > Most of the conditional code for ICELAKE also applies to ELKHARTLAKE
> > so use IS_GEN(dev_priv, 11) even for PM and Workarounds for now.
> >
> > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 2 +-
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 4 ++--
> > drivers/gpu/drm/i915/intel_workarounds.c | 8 ++++----
> > 3 files changed, 7 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index d73b13ca57a0..61c581e33fe3 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -9468,7 +9468,7 @@ static void nop_init_clock_gating(struct
> > drm_i915_private *dev_priv)
> > */
> > void intel_init_clock_gating_hooks(struct drm_i915_private
> > *dev_priv)
> > {
> > - if (IS_ICELAKE(dev_priv))
> > + if (IS_GEN(dev_priv, 11))
> > dev_priv->display.init_clock_gating =
> > icl_init_clock_gating;
> > else if (IS_CANNONLAKE(dev_priv))
> > dev_priv->display.init_clock_gating =
> > cnl_init_clock_gating;
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 676a89bb8194..1f063c761f35 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -3442,7 +3442,7 @@ int intel_power_domains_init(struct
> > drm_i915_private *dev_priv)
> > * The enabling order will be from lower to higher indexed
> > wells,
> > * the disabling order is reversed.
> > */
> > - if (IS_ICELAKE(dev_priv)) {
> > + if (IS_GEN(dev_priv, 11)) {
> > err = set_power_wells(power_domains, icl_power_wells);
> > } else if (IS_CANNONLAKE(dev_priv)) {
> > err = set_power_wells(power_domains, cnl_power_wells);
> > @@ -4203,7 +4203,7 @@ void intel_power_domains_suspend(struct
> > drm_i915_private *i915,
> > intel_power_domains_verify_state(i915);
> > }
> >
> > - if (IS_ICELAKE(i915))
> > + if (IS_GEN(i915, 11))
> > icl_display_core_uninit(i915);
> > else if (IS_CANNONLAKE(i915))
> > cnl_display_core_uninit(i915);
> > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
> > b/drivers/gpu/drm/i915/intel_workarounds.c
> > index 283e9a4ef3ca..2128cb6cf8c8 100644
> > --- a/drivers/gpu/drm/i915/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> > @@ -569,7 +569,7 @@ void intel_engine_init_ctx_wa(struct
> > intel_engine_cs *engine)
> >
> > wa_init_start(wal, "context");
> >
> > - if (IS_ICELAKE(i915))
> > + if (IS_GEN(i915, 11))
> > icl_ctx_workarounds_init(engine);
> > else if (IS_CANNONLAKE(i915))
> > cnl_ctx_workarounds_init(engine);
> > @@ -867,7 +867,7 @@ icl_gt_workarounds_init(struct drm_i915_private
> > *i915, struct i915_wa_list *wal)
> > static void
> > gt_init_workarounds(struct drm_i915_private *i915, struct
> > i915_wa_list *wal)
> > {
> > - if (IS_ICELAKE(i915))
> > + if (IS_GEN(i915, 11))
> > icl_gt_workarounds_init(i915, wal);
> > else if (IS_CANNONLAKE(i915))
> > cnl_gt_workarounds_init(i915, wal);
> > @@ -1064,7 +1064,7 @@ void intel_engine_init_whitelist(struct
> > intel_engine_cs *engine)
> >
> > wa_init_start(w, "whitelist");
> >
> > - if (IS_ICELAKE(i915))
> > + if (IS_GEN(i915, 11))
> > icl_whitelist_build(w);
> > else if (IS_CANNONLAKE(i915))
> > cnl_whitelist_build(w);
> > @@ -1112,7 +1112,7 @@ rcs_engine_wa_init(struct intel_engine_cs
> > *engine, struct i915_wa_list *wal)
> > {
> > struct drm_i915_private *i915 = engine->i915;
> >
> > - if (IS_ICELAKE(i915)) {
> > + if (IS_GEN(i915, 11)) {
> > /* This is not an Wa. Enable for better image quality
> > */
> > wa_masked_en(wal,
> > _3D_CHICKEN3,
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 3/9] drm/i915/ehl: ehl and icl are both gen11
2019-03-13 21:11 ` [PATCH 3/9] drm/i915/ehl: ehl and icl are both gen11 Rodrigo Vivi
2019-03-14 21:11 ` Souza, Jose
@ 2019-03-14 22:59 ` Lucas De Marchi
1 sibling, 0 replies; 36+ messages in thread
From: Lucas De Marchi @ 2019-03-14 22:59 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Wed, Mar 13, 2019 at 02:11:38PM -0700, Rodrigo Vivi wrote:
>From: Bob Paauwe <bob.j.paauwe@intel.com>
>
>Most of the conditional code for ICELAKE also applies to ELKHARTLAKE
>so use IS_GEN(dev_priv, 11) even for PM and Workarounds for now.
>
>Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> drivers/gpu/drm/i915/intel_runtime_pm.c | 4 ++--
> drivers/gpu/drm/i915/intel_workarounds.c | 8 ++++----
> 3 files changed, 7 insertions(+), 7 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>index d73b13ca57a0..61c581e33fe3 100644
>--- a/drivers/gpu/drm/i915/intel_pm.c
>+++ b/drivers/gpu/drm/i915/intel_pm.c
>@@ -9468,7 +9468,7 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
> */
> void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
> {
>- if (IS_ICELAKE(dev_priv))
>+ if (IS_GEN(dev_priv, 11))
> dev_priv->display.init_clock_gating = icl_init_clock_gating;
> else if (IS_CANNONLAKE(dev_priv))
> dev_priv->display.init_clock_gating = cnl_init_clock_gating;
>diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
>index 676a89bb8194..1f063c761f35 100644
>--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
>+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
>@@ -3442,7 +3442,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
> * The enabling order will be from lower to higher indexed wells,
> * the disabling order is reversed.
> */
>- if (IS_ICELAKE(dev_priv)) {
>+ if (IS_GEN(dev_priv, 11)) {
> err = set_power_wells(power_domains, icl_power_wells);
> } else if (IS_CANNONLAKE(dev_priv)) {
> err = set_power_wells(power_domains, cnl_power_wells);
>@@ -4203,7 +4203,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
> intel_power_domains_verify_state(i915);
> }
>
>- if (IS_ICELAKE(i915))
>+ if (IS_GEN(i915, 11))
> icl_display_core_uninit(i915);
> else if (IS_CANNONLAKE(i915))
> cnl_display_core_uninit(i915);
>diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
>index 283e9a4ef3ca..2128cb6cf8c8 100644
>--- a/drivers/gpu/drm/i915/intel_workarounds.c
>+++ b/drivers/gpu/drm/i915/intel_workarounds.c
>@@ -569,7 +569,7 @@ void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
>
> wa_init_start(wal, "context");
>
>- if (IS_ICELAKE(i915))
>+ if (IS_GEN(i915, 11))
> icl_ctx_workarounds_init(engine);
> else if (IS_CANNONLAKE(i915))
> cnl_ctx_workarounds_init(engine);
>@@ -867,7 +867,7 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> static void
> gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
> {
>- if (IS_ICELAKE(i915))
>+ if (IS_GEN(i915, 11))
> icl_gt_workarounds_init(i915, wal);
> else if (IS_CANNONLAKE(i915))
> cnl_gt_workarounds_init(i915, wal);
>@@ -1064,7 +1064,7 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>
> wa_init_start(w, "whitelist");
>
>- if (IS_ICELAKE(i915))
>+ if (IS_GEN(i915, 11))
> icl_whitelist_build(w);
> else if (IS_CANNONLAKE(i915))
> cnl_whitelist_build(w);
>@@ -1112,7 +1112,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> {
> struct drm_i915_private *i915 = engine->i915;
>
>- if (IS_ICELAKE(i915)) {
>+ if (IS_GEN(i915, 11)) {
> /* This is not an Wa. Enable for better image quality */
> wa_masked_en(wal,
> _3D_CHICKEN3,
>--
>2.20.1
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 4/9] drm/i915/ehl: Add dpll mgr
2019-03-13 21:11 [PATCH 1/9] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
2019-03-13 21:11 ` [PATCH 2/9] drm/i915/ehl: Add ElkhartLake platform Rodrigo Vivi
2019-03-13 21:11 ` [PATCH 3/9] drm/i915/ehl: ehl and icl are both gen11 Rodrigo Vivi
@ 2019-03-13 21:11 ` Rodrigo Vivi
2019-03-14 21:38 ` Souza, Jose
2019-03-13 21:11 ` [PATCH 5/9] drm/i915/ehl: All EHL ports are combo phys Rodrigo Vivi
` (11 subsequent siblings)
14 siblings, 1 reply; 36+ messages in thread
From: Rodrigo Vivi @ 2019-03-13 21:11 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Lucas De Marchi <lucas.demarchi@intel.com>
Elkhart Lake has a different set of PLLs as compared to Ice Lake,
although programming them is very similar.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index b3fb221c2532..a9feb119c19f 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -3246,6 +3246,18 @@ static const struct intel_dpll_mgr icl_pll_mgr = {
.dump_hw_state = icl_dump_hw_state,
};
+static const struct dpll_info ehl_plls[] = {
+ { "DPLL 0", &icl_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
+ { "DPLL 1", &icl_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
+ { },
+};
+
+static const struct intel_dpll_mgr ehl_pll_mgr = {
+ .dpll_info = ehl_plls,
+ .get_dpll = icl_get_dpll,
+ .dump_hw_state = icl_dump_hw_state,
+};
+
/**
* intel_shared_dpll_init - Initialize shared DPLLs
* @dev: drm device
@@ -3259,7 +3271,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
const struct dpll_info *dpll_info;
int i;
- if (INTEL_GEN(dev_priv) >= 11)
+ if (IS_ELKHARTLAKE(dev_priv))
+ dpll_mgr = &ehl_pll_mgr;
+ else if (INTEL_GEN(dev_priv) >= 11)
dpll_mgr = &icl_pll_mgr;
else if (IS_CANNONLAKE(dev_priv))
dpll_mgr = &cnl_pll_mgr;
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH 4/9] drm/i915/ehl: Add dpll mgr
2019-03-13 21:11 ` [PATCH 4/9] drm/i915/ehl: Add dpll mgr Rodrigo Vivi
@ 2019-03-14 21:38 ` Souza, Jose
0 siblings, 0 replies; 36+ messages in thread
From: Souza, Jose @ 2019-03-14 21:38 UTC (permalink / raw)
To: Vivi, Rodrigo, intel-gfx; +Cc: De Marchi, Lucas
[-- Attachment #1.1: Type: text/plain, Size: 1737 bytes --]
On Wed, 2019-03-13 at 14:11 -0700, Rodrigo Vivi wrote:
> From: Lucas De Marchi <lucas.demarchi@intel.com>
>
> Elkhart Lake has a different set of PLLs as compared to Ice Lake,
> although programming them is very similar.
>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 16 +++++++++++++++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index b3fb221c2532..a9feb119c19f 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -3246,6 +3246,18 @@ static const struct intel_dpll_mgr icl_pll_mgr
> = {
> .dump_hw_state = icl_dump_hw_state,
> };
>
> +static const struct dpll_info ehl_plls[] = {
> + { "DPLL 0", &icl_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
> + { "DPLL 1", &icl_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
> + { },
> +};
> +
> +static const struct intel_dpll_mgr ehl_pll_mgr = {
> + .dpll_info = ehl_plls,
> + .get_dpll = icl_get_dpll,
> + .dump_hw_state = icl_dump_hw_state,
> +};
> +
> /**
> * intel_shared_dpll_init - Initialize shared DPLLs
> * @dev: drm device
> @@ -3259,7 +3271,9 @@ void intel_shared_dpll_init(struct drm_device
> *dev)
> const struct dpll_info *dpll_info;
> int i;
>
> - if (INTEL_GEN(dev_priv) >= 11)
> + if (IS_ELKHARTLAKE(dev_priv))
> + dpll_mgr = &ehl_pll_mgr;
> + else if (INTEL_GEN(dev_priv) >= 11)
> dpll_mgr = &icl_pll_mgr;
> else if (IS_CANNONLAKE(dev_priv))
> dpll_mgr = &cnl_pll_mgr;
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 5/9] drm/i915/ehl: All EHL ports are combo phys
2019-03-13 21:11 [PATCH 1/9] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
` (2 preceding siblings ...)
2019-03-13 21:11 ` [PATCH 4/9] drm/i915/ehl: Add dpll mgr Rodrigo Vivi
@ 2019-03-13 21:11 ` Rodrigo Vivi
2019-03-14 20:27 ` Souza, Jose
` (2 more replies)
2019-03-13 21:11 ` [PATCH 6/9] drm/i915/ehl: EHL outputs are different from ICL Rodrigo Vivi
` (10 subsequent siblings)
14 siblings, 3 replies; 36+ messages in thread
From: Rodrigo Vivi @ 2019-03-13 21:11 UTC (permalink / raw)
To: intel-gfx
From: Bob Paauwe <bob.j.paauwe@intel.com>
Unlike ICL, all of the output ports are combo phys so just return
true in is_port_combophy for all EHL ports to indicate that.
Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2b25098d47a9..920f647bd451 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6170,6 +6170,9 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
if (port == PORT_NONE)
return false;
+ if (IS_ELKHARTLAKE(dev_priv))
+ return port <= PORT_C;
+
if (INTEL_GEN(dev_priv) >= 11)
return port <= PORT_B;
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH 5/9] drm/i915/ehl: All EHL ports are combo phys
2019-03-13 21:11 ` [PATCH 5/9] drm/i915/ehl: All EHL ports are combo phys Rodrigo Vivi
@ 2019-03-14 20:27 ` Souza, Jose
2019-03-14 23:00 ` Lucas De Marchi
2019-03-20 21:15 ` [PATCH] drm/i915/ehl: All EHL ports are combo phys (v2) Bob Paauwe
2 siblings, 0 replies; 36+ messages in thread
From: Souza, Jose @ 2019-03-14 20:27 UTC (permalink / raw)
To: Vivi, Rodrigo, intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 1310 bytes --]
On Wed, 2019-03-13 at 14:11 -0700, Rodrigo Vivi wrote:
> From: Bob Paauwe <bob.j.paauwe@intel.com>
>
> Unlike ICL, all of the output ports are combo phys so just return
> true in is_port_combophy for all EHL ports to indicate that.
>
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 2b25098d47a9..920f647bd451 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6170,6 +6170,9 @@ bool intel_port_is_combophy(struct
> drm_i915_private *dev_priv, enum port port)
> if (port == PORT_NONE)
> return false;
>
> + if (IS_ELKHARTLAKE(dev_priv))
> + return port <= PORT_C;
> +
> if (INTEL_GEN(dev_priv) >= 11)
> return port <= PORT_B;
>
You also need to change intel_port_is_tc(), several places only checks
for it and it would be broken for PORT_C in EHL.
bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port
port)
{
if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
return port >= PORT_C && port <= PORT_F;
return false;
}
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 5/9] drm/i915/ehl: All EHL ports are combo phys
2019-03-13 21:11 ` [PATCH 5/9] drm/i915/ehl: All EHL ports are combo phys Rodrigo Vivi
2019-03-14 20:27 ` Souza, Jose
@ 2019-03-14 23:00 ` Lucas De Marchi
2019-03-20 21:15 ` [PATCH] drm/i915/ehl: All EHL ports are combo phys (v2) Bob Paauwe
2 siblings, 0 replies; 36+ messages in thread
From: Lucas De Marchi @ 2019-03-14 23:00 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Wed, Mar 13, 2019 at 02:11:40PM -0700, Rodrigo Vivi wrote:
>From: Bob Paauwe <bob.j.paauwe@intel.com>
>
>Unlike ICL, all of the output ports are combo phys so just return
>true in is_port_combophy for all EHL ports to indicate that.
>
>Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
long term I want to remove most (all?) of the users of this function,
but right now it does what it needs to do.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/intel_display.c | 3 +++
> 1 file changed, 3 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>index 2b25098d47a9..920f647bd451 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -6170,6 +6170,9 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
> if (port == PORT_NONE)
> return false;
>
>+ if (IS_ELKHARTLAKE(dev_priv))
>+ return port <= PORT_C;
>+
> if (INTEL_GEN(dev_priv) >= 11)
> return port <= PORT_B;
>
>--
>2.20.1
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH] drm/i915/ehl: All EHL ports are combo phys (v2)
2019-03-13 21:11 ` [PATCH 5/9] drm/i915/ehl: All EHL ports are combo phys Rodrigo Vivi
2019-03-14 20:27 ` Souza, Jose
2019-03-14 23:00 ` Lucas De Marchi
@ 2019-03-20 21:15 ` Bob Paauwe
2019-03-20 21:20 ` Souza, Jose
` (2 more replies)
2 siblings, 3 replies; 36+ messages in thread
From: Bob Paauwe @ 2019-03-20 21:15 UTC (permalink / raw)
To: intel-gfx
Unlike ICL, all of the output ports are combo phys so just return
true in intel_port_is_combophy for all EHL ports to indicate that.
v2: Return false in intel_port_is_tc since no EHL ports are TC. (Jose)
Cc: Jose Souza <jose.souza@intel.com>
Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2b25098d47a9..094456843c4a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6170,6 +6170,9 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
if (port == PORT_NONE)
return false;
+ if (IS_ELKHARTLAKE(dev_priv))
+ return port <= PORT_C;
+
if (INTEL_GEN(dev_priv) >= 11)
return port <= PORT_B;
@@ -6178,7 +6181,7 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
{
- if (INTEL_GEN(dev_priv) >= 11)
+ if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
return port >= PORT_C && port <= PORT_F;
return false;
--
2.19.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH] drm/i915/ehl: All EHL ports are combo phys (v2)
2019-03-20 21:15 ` [PATCH] drm/i915/ehl: All EHL ports are combo phys (v2) Bob Paauwe
@ 2019-03-20 21:20 ` Souza, Jose
2019-04-02 22:17 ` Lucas De Marchi
2019-03-21 8:09 ` kbuild test robot
2019-03-21 8:37 ` kbuild test robot
2 siblings, 1 reply; 36+ messages in thread
From: Souza, Jose @ 2019-03-20 21:20 UTC (permalink / raw)
To: Paauwe, Bob J, intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 1505 bytes --]
On Wed, 2019-03-20 at 14:15 -0700, Bob Paauwe wrote:
> Unlike ICL, all of the output ports are combo phys so just return
> true in intel_port_is_combophy for all EHL ports to indicate that.
>
> v2: Return false in intel_port_is_tc since no EHL ports are TC.
> (Jose)
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Cc: Jose Souza <jose.souza@intel.com>
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 2b25098d47a9..094456843c4a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6170,6 +6170,9 @@ bool intel_port_is_combophy(struct
> drm_i915_private *dev_priv, enum port port)
> if (port == PORT_NONE)
> return false;
>
> + if (IS_ELKHARTLAKE(dev_priv))
> + return port <= PORT_C;
> +
> if (INTEL_GEN(dev_priv) >= 11)
> return port <= PORT_B;
>
> @@ -6178,7 +6181,7 @@ bool intel_port_is_combophy(struct
> drm_i915_private *dev_priv, enum port port)
>
> bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port
> port)
> {
> - if (INTEL_GEN(dev_priv) >= 11)
> + if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> return port >= PORT_C && port <= PORT_F;
>
> return false;
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH] drm/i915/ehl: All EHL ports are combo phys (v2)
2019-03-20 21:20 ` Souza, Jose
@ 2019-04-02 22:17 ` Lucas De Marchi
0 siblings, 0 replies; 36+ messages in thread
From: Lucas De Marchi @ 2019-04-02 22:17 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
On Wed, Mar 20, 2019 at 2:20 PM Souza, Jose <jose.souza@intel.com> wrote:
>
> On Wed, 2019-03-20 at 14:15 -0700, Bob Paauwe wrote:
> > Unlike ICL, all of the output ports are combo phys so just return
> > true in intel_port_is_combophy for all EHL ports to indicate that.
> >
> > v2: Return false in intel_port_is_tc since no EHL ports are TC.
> > (Jose)
>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
I removed the (v2) from the first line of the commit message since we
don't add that normally and pushed.
Thanks.
Lucas De Marchi
>
> >
> > Cc: Jose Souza <jose.souza@intel.com>
> > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 5 ++++-
> > 1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 2b25098d47a9..094456843c4a 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -6170,6 +6170,9 @@ bool intel_port_is_combophy(struct
> > drm_i915_private *dev_priv, enum port port)
> > if (port == PORT_NONE)
> > return false;
> >
> > + if (IS_ELKHARTLAKE(dev_priv))
> > + return port <= PORT_C;
> > +
> > if (INTEL_GEN(dev_priv) >= 11)
> > return port <= PORT_B;
> >
> > @@ -6178,7 +6181,7 @@ bool intel_port_is_combophy(struct
> > drm_i915_private *dev_priv, enum port port)
> >
> > bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port
> > port)
> > {
> > - if (INTEL_GEN(dev_priv) >= 11)
> > + if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> > return port >= PORT_C && port <= PORT_F;
> >
> > return false;
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Lucas De Marchi
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH] drm/i915/ehl: All EHL ports are combo phys (v2)
2019-03-20 21:15 ` [PATCH] drm/i915/ehl: All EHL ports are combo phys (v2) Bob Paauwe
2019-03-20 21:20 ` Souza, Jose
@ 2019-03-21 8:09 ` kbuild test robot
2019-03-21 8:37 ` kbuild test robot
2 siblings, 0 replies; 36+ messages in thread
From: kbuild test robot @ 2019-03-21 8:09 UTC (permalink / raw)
To: Bob Paauwe; +Cc: intel-gfx, kbuild-all
[-- Attachment #1: Type: text/plain, Size: 1646 bytes --]
Hi Bob,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20190320]
[cannot apply to v5.1-rc1]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Bob-Paauwe/drm-i915-ehl-All-EHL-ports-are-combo-phys-v2/20190321-145619
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x000-201911 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones prefixed by >>):
drivers/gpu//drm/i915/intel_display.c: In function 'intel_port_is_combophy':
>> drivers/gpu//drm/i915/intel_display.c:6183:6: error: implicit declaration of function 'IS_ELKHARTLAKE'; did you mean 'IS_KABYLAKE'? [-Werror=implicit-function-declaration]
if (IS_ELKHARTLAKE(dev_priv))
^~~~~~~~~~~~~~
IS_KABYLAKE
cc1: some warnings being treated as errors
vim +6183 drivers/gpu//drm/i915/intel_display.c
6177
6178 bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
6179 {
6180 if (port == PORT_NONE)
6181 return false;
6182
> 6183 if (IS_ELKHARTLAKE(dev_priv))
6184 return port <= PORT_C;
6185
6186 if (INTEL_GEN(dev_priv) >= 11)
6187 return port <= PORT_B;
6188
6189 return false;
6190 }
6191
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 30626 bytes --]
[-- Attachment #3: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH] drm/i915/ehl: All EHL ports are combo phys (v2)
2019-03-20 21:15 ` [PATCH] drm/i915/ehl: All EHL ports are combo phys (v2) Bob Paauwe
2019-03-20 21:20 ` Souza, Jose
2019-03-21 8:09 ` kbuild test robot
@ 2019-03-21 8:37 ` kbuild test robot
2 siblings, 0 replies; 36+ messages in thread
From: kbuild test robot @ 2019-03-21 8:37 UTC (permalink / raw)
To: Bob Paauwe; +Cc: intel-gfx, kbuild-all
[-- Attachment #1: Type: text/plain, Size: 2199 bytes --]
Hi Bob,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on next-20190320]
[cannot apply to v5.1-rc1]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Bob-Paauwe/drm-i915-ehl-All-EHL-ports-are-combo-phys-v2/20190321-145619
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x073-201911 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All warnings (new ones prefixed by >>):
In file included from include/linux/string.h:6:0,
from include/linux/uuid.h:20,
from include/linux/mod_devicetable.h:13,
from include/linux/i2c.h:29,
from drivers/gpu/drm/i915/intel_display.c:27:
drivers/gpu/drm/i915/intel_display.c: In function 'intel_port_is_combophy':
drivers/gpu/drm/i915/intel_display.c:6183:6: error: implicit declaration of function 'IS_ELKHARTLAKE'; did you mean 'IS_KABYLAKE'? [-Werror=implicit-function-declaration]
if (IS_ELKHARTLAKE(dev_priv))
^
include/linux/compiler.h:58:30: note: in definition of macro '__trace_if'
if (__builtin_constant_p(!!(cond)) ? !!(cond) : \
^~~~
>> drivers/gpu/drm/i915/intel_display.c:6183:2: note: in expansion of macro 'if'
if (IS_ELKHARTLAKE(dev_priv))
^~
cc1: some warnings being treated as errors
vim +/if +6183 drivers/gpu/drm/i915/intel_display.c
6177
6178 bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
6179 {
6180 if (port == PORT_NONE)
6181 return false;
6182
> 6183 if (IS_ELKHARTLAKE(dev_priv))
6184 return port <= PORT_C;
6185
6186 if (INTEL_GEN(dev_priv) >= 11)
6187 return port <= PORT_B;
6188
6189 return false;
6190 }
6191
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 26235 bytes --]
[-- Attachment #3: Type: text/plain, Size: 159 bytes --]
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 6/9] drm/i915/ehl: EHL outputs are different from ICL
2019-03-13 21:11 [PATCH 1/9] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
` (3 preceding siblings ...)
2019-03-13 21:11 ` [PATCH 5/9] drm/i915/ehl: All EHL ports are combo phys Rodrigo Vivi
@ 2019-03-13 21:11 ` Rodrigo Vivi
2019-03-14 21:39 ` Souza, Jose
2019-03-14 23:19 ` Lucas De Marchi
2019-03-13 21:11 ` [PATCH 7/9] drm/i915/ehl: Set proper eu slice/subslice parameters for EHL Rodrigo Vivi
` (9 subsequent siblings)
14 siblings, 2 replies; 36+ messages in thread
From: Rodrigo Vivi @ 2019-03-13 21:11 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Bob Paauwe <bob.j.paauwe@intel.com>
Configure the correct set of outputs for EHL. EHL has three DDI's
plus MIPI.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 920f647bd451..9e39e5a3ec4f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14692,7 +14692,12 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (IS_ELKHARTLAKE(dev_priv)) {
+ intel_ddi_init(dev_priv, PORT_A);
+ intel_ddi_init(dev_priv, PORT_B);
+ intel_ddi_init(dev_priv, PORT_C);
+ icl_dsi_init(dev_priv);
+ } else if (INTEL_GEN(dev_priv) >= 11) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_C);
--
2.20.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH 6/9] drm/i915/ehl: EHL outputs are different from ICL
2019-03-13 21:11 ` [PATCH 6/9] drm/i915/ehl: EHL outputs are different from ICL Rodrigo Vivi
@ 2019-03-14 21:39 ` Souza, Jose
2019-03-14 23:19 ` Lucas De Marchi
1 sibling, 0 replies; 36+ messages in thread
From: Souza, Jose @ 2019-03-14 21:39 UTC (permalink / raw)
To: Vivi, Rodrigo, intel-gfx; +Cc: De Marchi, Lucas
[-- Attachment #1.1: Type: text/plain, Size: 1301 bytes --]
On Wed, 2019-03-13 at 14:11 -0700, Rodrigo Vivi wrote:
> From: Bob Paauwe <bob.j.paauwe@intel.com>
>
> Configure the correct set of outputs for EHL. EHL has three DDI's
> plus MIPI.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 920f647bd451..9e39e5a3ec4f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -14692,7 +14692,12 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> if (!HAS_DISPLAY(dev_priv))
> return;
>
> - if (INTEL_GEN(dev_priv) >= 11) {
> + if (IS_ELKHARTLAKE(dev_priv)) {
> + intel_ddi_init(dev_priv, PORT_A);
> + intel_ddi_init(dev_priv, PORT_B);
> + intel_ddi_init(dev_priv, PORT_C);
> + icl_dsi_init(dev_priv);
> + } else if (INTEL_GEN(dev_priv) >= 11) {
> intel_ddi_init(dev_priv, PORT_A);
> intel_ddi_init(dev_priv, PORT_B);
> intel_ddi_init(dev_priv, PORT_C);
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 6/9] drm/i915/ehl: EHL outputs are different from ICL
2019-03-13 21:11 ` [PATCH 6/9] drm/i915/ehl: EHL outputs are different from ICL Rodrigo Vivi
2019-03-14 21:39 ` Souza, Jose
@ 2019-03-14 23:19 ` Lucas De Marchi
1 sibling, 0 replies; 36+ messages in thread
From: Lucas De Marchi @ 2019-03-14 23:19 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Wed, Mar 13, 2019 at 02:11:41PM -0700, Rodrigo Vivi wrote:
>From: Bob Paauwe <bob.j.paauwe@intel.com>
>
>Configure the correct set of outputs for EHL. EHL has three DDI's
>plus MIPI.
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/intel_display.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>index 920f647bd451..9e39e5a3ec4f 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -14692,7 +14692,12 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
> if (!HAS_DISPLAY(dev_priv))
> return;
>
>- if (INTEL_GEN(dev_priv) >= 11) {
>+ if (IS_ELKHARTLAKE(dev_priv)) {
>+ intel_ddi_init(dev_priv, PORT_A);
>+ intel_ddi_init(dev_priv, PORT_B);
>+ intel_ddi_init(dev_priv, PORT_C);
>+ icl_dsi_init(dev_priv);
>+ } else if (INTEL_GEN(dev_priv) >= 11) {
> intel_ddi_init(dev_priv, PORT_A);
> intel_ddi_init(dev_priv, PORT_B);
> intel_ddi_init(dev_priv, PORT_C);
>--
>2.20.1
>
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 7/9] drm/i915/ehl: Set proper eu slice/subslice parameters for EHL
2019-03-13 21:11 [PATCH 1/9] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
` (4 preceding siblings ...)
2019-03-13 21:11 ` [PATCH 6/9] drm/i915/ehl: EHL outputs are different from ICL Rodrigo Vivi
@ 2019-03-13 21:11 ` Rodrigo Vivi
2019-03-14 21:40 ` Souza, Jose
2019-03-14 23:22 ` Lucas De Marchi
2019-03-13 21:11 ` [PATCH 8/9] drm/i915/ehl: ehl has only 36bit extended ppgtt support Rodrigo Vivi
` (8 subsequent siblings)
14 siblings, 2 replies; 36+ messages in thread
From: Rodrigo Vivi @ 2019-03-13 21:11 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Bob Paauwe <bob.j.paauwe@intel.com>
EHL has a different number of subslices.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_device_info.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index c8c0f4134bdb..31411f1cdbb4 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -156,9 +156,15 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
u8 eu_en;
int s;
- sseu->max_slices = 1;
- sseu->max_subslices = 8;
- sseu->max_eus_per_subslice = 8;
+ if (IS_ELKHARTLAKE(dev_priv)) {
+ sseu->max_slices = 1;
+ sseu->max_subslices = 4;
+ sseu->max_eus_per_subslice = 8;
+ } else {
+ sseu->max_slices = 1;
+ sseu->max_subslices = 8;
+ sseu->max_eus_per_subslice = 8;
+ }
s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH 7/9] drm/i915/ehl: Set proper eu slice/subslice parameters for EHL
2019-03-13 21:11 ` [PATCH 7/9] drm/i915/ehl: Set proper eu slice/subslice parameters for EHL Rodrigo Vivi
@ 2019-03-14 21:40 ` Souza, Jose
2019-03-14 23:22 ` Lucas De Marchi
1 sibling, 0 replies; 36+ messages in thread
From: Souza, Jose @ 2019-03-14 21:40 UTC (permalink / raw)
To: Vivi, Rodrigo, intel-gfx; +Cc: De Marchi, Lucas
[-- Attachment #1.1: Type: text/plain, Size: 1347 bytes --]
On Wed, 2019-03-13 at 14:11 -0700, Rodrigo Vivi wrote:
> From: Bob Paauwe <bob.j.paauwe@intel.com>
>
> EHL has a different number of subslices.
>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_device_info.c | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index c8c0f4134bdb..31411f1cdbb4 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -156,9 +156,15 @@ static void gen11_sseu_info_init(struct
> drm_i915_private *dev_priv)
> u8 eu_en;
> int s;
>
> - sseu->max_slices = 1;
> - sseu->max_subslices = 8;
> - sseu->max_eus_per_subslice = 8;
> + if (IS_ELKHARTLAKE(dev_priv)) {
> + sseu->max_slices = 1;
> + sseu->max_subslices = 4;
> + sseu->max_eus_per_subslice = 8;
> + } else {
> + sseu->max_slices = 1;
> + sseu->max_subslices = 8;
> + sseu->max_eus_per_subslice = 8;
> + }
>
> s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
> ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 7/9] drm/i915/ehl: Set proper eu slice/subslice parameters for EHL
2019-03-13 21:11 ` [PATCH 7/9] drm/i915/ehl: Set proper eu slice/subslice parameters for EHL Rodrigo Vivi
2019-03-14 21:40 ` Souza, Jose
@ 2019-03-14 23:22 ` Lucas De Marchi
1 sibling, 0 replies; 36+ messages in thread
From: Lucas De Marchi @ 2019-03-14 23:22 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Wed, Mar 13, 2019 at 02:11:42PM -0700, Rodrigo Vivi wrote:
>From: Bob Paauwe <bob.j.paauwe@intel.com>
>
>EHL has a different number of subslices.
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>---
> drivers/gpu/drm/i915/intel_device_info.c | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>index c8c0f4134bdb..31411f1cdbb4 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.c
>+++ b/drivers/gpu/drm/i915/intel_device_info.c
>@@ -156,9 +156,15 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
> u8 eu_en;
> int s;
>
>- sseu->max_slices = 1;
>- sseu->max_subslices = 8;
>- sseu->max_eus_per_subslice = 8;
>+ if (IS_ELKHARTLAKE(dev_priv)) {
>+ sseu->max_slices = 1;
>+ sseu->max_subslices = 4;
>+ sseu->max_eus_per_subslice = 8;
matches spec.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>+ } else {
>+ sseu->max_slices = 1;
>+ sseu->max_subslices = 8;
>+ sseu->max_eus_per_subslice = 8;
>+ }
>
> s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
> ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
>--
>2.20.1
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 8/9] drm/i915/ehl: ehl has only 36bit extended ppgtt support
2019-03-13 21:11 [PATCH 1/9] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
` (5 preceding siblings ...)
2019-03-13 21:11 ` [PATCH 7/9] drm/i915/ehl: Set proper eu slice/subslice parameters for EHL Rodrigo Vivi
@ 2019-03-13 21:11 ` Rodrigo Vivi
2019-03-14 7:34 ` Chris Wilson
2019-03-13 21:11 ` [PATCH 9/9] drm/i915/ehl: Add Support for DMC on EHL Rodrigo Vivi
` (7 subsequent siblings)
14 siblings, 1 reply; 36+ messages in thread
From: Rodrigo Vivi @ 2019-03-13 21:11 UTC (permalink / raw)
To: intel-gfx
From: Bob Paauwe <bob.j.paauwe@intel.com>
While EHL does support 4 level extended ppgtt, it only makes use
of 36 bits instead of the 48 like the other platforms that have
4 level extended ppgtt.
Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index dac08d9c3fab..584bb9898fed 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1539,9 +1539,12 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
ppgtt->vm.i915 = i915;
ppgtt->vm.dma = &i915->drm.pdev->dev;
- ppgtt->vm.total = HAS_FULL_48BIT_PPGTT(i915) ?
- 1ULL << 48 :
- 1ULL << 32;
+ if (HAS_FULL_48BIT_PPGTT(i915))
+ ppgtt->vm.total = IS_ELKHARTLAKE(i915) ?
+ 1ULL << 36 :
+ 1ULL << 48;
+ else
+ ppgtt->vm.total = 1ULL << 32;
/* From bdw, there is support for read-only pages in the PPGTT. */
ppgtt->vm.has_read_only = true;
--
2.20.1
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^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH 8/9] drm/i915/ehl: ehl has only 36bit extended ppgtt support
2019-03-13 21:11 ` [PATCH 8/9] drm/i915/ehl: ehl has only 36bit extended ppgtt support Rodrigo Vivi
@ 2019-03-14 7:34 ` Chris Wilson
0 siblings, 0 replies; 36+ messages in thread
From: Chris Wilson @ 2019-03-14 7:34 UTC (permalink / raw)
To: Rodrigo Vivi, intel-gfx
Quoting Rodrigo Vivi (2019-03-13 21:11:43)
> From: Bob Paauwe <bob.j.paauwe@intel.com>
>
> While EHL does support 4 level extended ppgtt, it only makes use
> of 36 bits instead of the 48 like the other platforms that have
> 4 level extended ppgtt.
>
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index dac08d9c3fab..584bb9898fed 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1539,9 +1539,12 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
> ppgtt->vm.i915 = i915;
> ppgtt->vm.dma = &i915->drm.pdev->dev;
>
> - ppgtt->vm.total = HAS_FULL_48BIT_PPGTT(i915) ?
> - 1ULL << 48 :
> - 1ULL << 32;
> + if (HAS_FULL_48BIT_PPGTT(i915))
> + ppgtt->vm.total = IS_ELKHARTLAKE(i915) ?
> + 1ULL << 36 :
> + 1ULL << 48;
> + else
> + ppgtt->vm.total = 1ULL << 32;
At least write this as a if-else chain if you are not going to follow
through with the device-info patches.
-Chris
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^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 9/9] drm/i915/ehl: Add Support for DMC on EHL
2019-03-13 21:11 [PATCH 1/9] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
` (6 preceding siblings ...)
2019-03-13 21:11 ` [PATCH 8/9] drm/i915/ehl: ehl has only 36bit extended ppgtt support Rodrigo Vivi
@ 2019-03-13 21:11 ` Rodrigo Vivi
2019-03-14 21:49 ` Souza, Jose
2019-03-14 23:29 ` Lucas De Marchi
2019-03-14 2:24 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs Patchwork
` (6 subsequent siblings)
14 siblings, 2 replies; 36+ messages in thread
From: Rodrigo Vivi @ 2019-03-13 21:11 UTC (permalink / raw)
To: intel-gfx
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
EHL uses the same firmware as ICL.
Cc: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index e8ac04c33e29..862a8f686ef5 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -486,7 +486,7 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
if (INTEL_GEN(dev_priv) >= 12) {
/* Allow to load fw via parameter using the last known size */
csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
- } else if (IS_ICELAKE(dev_priv)) {
+ } else if (IS_GEN(dev_priv, 11)) {
csr->fw_path = ICL_CSR_PATH;
csr->required_version = ICL_CSR_VERSION_REQUIRED;
csr->max_fw_size = ICL_CSR_MAX_FW_SIZE;
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH 9/9] drm/i915/ehl: Add Support for DMC on EHL
2019-03-13 21:11 ` [PATCH 9/9] drm/i915/ehl: Add Support for DMC on EHL Rodrigo Vivi
@ 2019-03-14 21:49 ` Souza, Jose
2019-03-14 23:29 ` Lucas De Marchi
1 sibling, 0 replies; 36+ messages in thread
From: Souza, Jose @ 2019-03-14 21:49 UTC (permalink / raw)
To: Vivi, Rodrigo, intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 1161 bytes --]
On Wed, 2019-03-13 at 14:11 -0700, Rodrigo Vivi wrote:
> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
> EHL uses the same firmware as ICL.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Cc: Bob Paauwe <bob.j.paauwe@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_csr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_csr.c
> b/drivers/gpu/drm/i915/intel_csr.c
> index e8ac04c33e29..862a8f686ef5 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -486,7 +486,7 @@ void intel_csr_ucode_init(struct drm_i915_private
> *dev_priv)
> if (INTEL_GEN(dev_priv) >= 12) {
> /* Allow to load fw via parameter using the last known
> size */
> csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
> - } else if (IS_ICELAKE(dev_priv)) {
> + } else if (IS_GEN(dev_priv, 11)) {
> csr->fw_path = ICL_CSR_PATH;
> csr->required_version = ICL_CSR_VERSION_REQUIRED;
> csr->max_fw_size = ICL_CSR_MAX_FW_SIZE;
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 9/9] drm/i915/ehl: Add Support for DMC on EHL
2019-03-13 21:11 ` [PATCH 9/9] drm/i915/ehl: Add Support for DMC on EHL Rodrigo Vivi
2019-03-14 21:49 ` Souza, Jose
@ 2019-03-14 23:29 ` Lucas De Marchi
1 sibling, 0 replies; 36+ messages in thread
From: Lucas De Marchi @ 2019-03-14 23:29 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Wed, Mar 13, 2019 at 02:11:44PM -0700, Rodrigo Vivi wrote:
>From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
>EHL uses the same firmware as ICL.
>
>Cc: Bob Paauwe <bob.j.paauwe@intel.com>
>Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/intel_csr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
>index e8ac04c33e29..862a8f686ef5 100644
>--- a/drivers/gpu/drm/i915/intel_csr.c
>+++ b/drivers/gpu/drm/i915/intel_csr.c
>@@ -486,7 +486,7 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
> if (INTEL_GEN(dev_priv) >= 12) {
> /* Allow to load fw via parameter using the last known size */
> csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
>- } else if (IS_ICELAKE(dev_priv)) {
>+ } else if (IS_GEN(dev_priv, 11)) {
> csr->fw_path = ICL_CSR_PATH;
> csr->required_version = ICL_CSR_VERSION_REQUIRED;
> csr->max_fw_size = ICL_CSR_MAX_FW_SIZE;
>--
>2.20.1
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs
2019-03-13 21:11 [PATCH 1/9] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
` (7 preceding siblings ...)
2019-03-13 21:11 ` [PATCH 9/9] drm/i915/ehl: Add Support for DMC on EHL Rodrigo Vivi
@ 2019-03-14 2:24 ` Patchwork
2019-03-14 2:28 ` ✗ Fi.CI.SPARSE: " Patchwork
` (5 subsequent siblings)
14 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2019-03-14 2:24 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs
URL : https://patchwork.freedesktop.org/series/57959/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
62bc6b41a37f drm/i915/ehl: Add EHL platform info and PCI IDs
-:60: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#60: FILE: include/drm/i915_pciids.h:476:
+#define INTEL_EHL_IDS(info) \
+ INTEL_VGA_DEVICE(0x4500, info), \
+ INTEL_VGA_DEVICE(0x4571, info), \
+ INTEL_VGA_DEVICE(0x4551, info), \
+ INTEL_VGA_DEVICE(0x4541, info)
-:60: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#60: FILE: include/drm/i915_pciids.h:476:
+#define INTEL_EHL_IDS(info) \
+ INTEL_VGA_DEVICE(0x4500, info), \
+ INTEL_VGA_DEVICE(0x4571, info), \
+ INTEL_VGA_DEVICE(0x4551, info), \
+ INTEL_VGA_DEVICE(0x4541, info)
total: 1 errors, 0 warnings, 1 checks, 39 lines checked
d031b8c63dfe drm/i915/ehl: Add ElkhartLake platform
36697ceb701e drm/i915/ehl: ehl and icl are both gen11
b48543de2bec drm/i915/ehl: Add dpll mgr
2be6ae3e1c03 drm/i915/ehl: All EHL ports are combo phys
420753bfaa6e drm/i915/ehl: EHL outputs are different from ICL
63bef8abf598 drm/i915/ehl: Set proper eu slice/subslice parameters for EHL
733f2e96ec41 drm/i915/ehl: ehl has only 36bit extended ppgtt support
fa9fba049f37 drm/i915/ehl: Add Support for DMC on EHL
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* ✗ Fi.CI.SPARSE: warning for series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs
2019-03-13 21:11 [PATCH 1/9] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
` (8 preceding siblings ...)
2019-03-14 2:24 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs Patchwork
@ 2019-03-14 2:28 ` Patchwork
2019-03-14 3:07 ` ✓ Fi.CI.BAT: success " Patchwork
` (4 subsequent siblings)
14 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2019-03-14 2:28 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs
URL : https://patchwork.freedesktop.org/series/57959/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/ehl: Add EHL platform info and PCI IDs
Okay!
Commit: drm/i915/ehl: Add ElkhartLake platform
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3560:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3561:16: warning: expression using sizeof(void)
Commit: drm/i915/ehl: ehl and icl are both gen11
Okay!
Commit: drm/i915/ehl: Add dpll mgr
Okay!
Commit: drm/i915/ehl: All EHL ports are combo phys
Okay!
Commit: drm/i915/ehl: EHL outputs are different from ICL
Okay!
Commit: drm/i915/ehl: Set proper eu slice/subslice parameters for EHL
Okay!
Commit: drm/i915/ehl: ehl has only 36bit extended ppgtt support
Okay!
Commit: drm/i915/ehl: Add Support for DMC on EHL
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs
2019-03-13 21:11 [PATCH 1/9] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
` (9 preceding siblings ...)
2019-03-14 2:28 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2019-03-14 3:07 ` Patchwork
2019-03-14 9:30 ` ✗ Fi.CI.IGT: failure " Patchwork
` (3 subsequent siblings)
14 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2019-03-14 3:07 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs
URL : https://patchwork.freedesktop.org/series/57959/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5742 -> Patchwork_12454
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/57959/revisions/1/mbox/
Known issues
------------
Here are the changes found in Patchwork_12454 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@userptr:
- fi-whl-u: NOTRUN -> SKIP [fdo#109271] +41
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109315] +17
* igt@gem_exec_basic@readonly-bsd1:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109276] +7
* igt@gem_exec_parse@basic-allowed:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109289] +1
* igt@i915_selftest@live_contexts:
- fi-icl-u2: NOTRUN -> INCOMPLETE [fdo#108569]
* igt@kms_busy@basic-flip-c:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_chamelium@dp-edid-read:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109316] +2
* igt@kms_chamelium@vga-hpd-fast:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109309] +1
* igt@kms_force_connector_basic@prune-stale-modes:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109285] +3
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: NOTRUN -> FAIL [fdo#103167]
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-c:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +20
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-blb-e6850: NOTRUN -> INCOMPLETE [fdo#107718]
* igt@kms_psr@cursor_plane_move:
- fi-whl-u: NOTRUN -> FAIL [fdo#107383] +3
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109316]: https://bugs.freedesktop.org/show_bug.cgi?id=109316
Participating hosts (42 -> 32)
------------------------------
Additional (2): fi-whl-u fi-icl-u2
Missing (12): fi-ilk-m540 fi-bsw-n3050 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-hsw-4770 fi-icl-u3 fi-pnv-d510 fi-bsw-kefka fi-byt-n2820 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_5742 -> Patchwork_12454
CI_DRM_5742: 519a3f67aadea184cb97720c838946c1ba81c875 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4884: c46051337b972f8b5a302afb6f603df06fea527d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12454: fa9fba049f3704c736e565f1068d03036a36476c @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
fa9fba049f37 drm/i915/ehl: Add Support for DMC on EHL
733f2e96ec41 drm/i915/ehl: ehl has only 36bit extended ppgtt support
63bef8abf598 drm/i915/ehl: Set proper eu slice/subslice parameters for EHL
420753bfaa6e drm/i915/ehl: EHL outputs are different from ICL
2be6ae3e1c03 drm/i915/ehl: All EHL ports are combo phys
b48543de2bec drm/i915/ehl: Add dpll mgr
36697ceb701e drm/i915/ehl: ehl and icl are both gen11
d031b8c63dfe drm/i915/ehl: Add ElkhartLake platform
62bc6b41a37f drm/i915/ehl: Add EHL platform info and PCI IDs
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12454/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* ✗ Fi.CI.IGT: failure for series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs
2019-03-13 21:11 [PATCH 1/9] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
` (10 preceding siblings ...)
2019-03-14 3:07 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-03-14 9:30 ` Patchwork
2019-03-14 20:43 ` [PATCH 1/9] " Souza, Jose
` (2 subsequent siblings)
14 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2019-03-14 9:30 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs
URL : https://patchwork.freedesktop.org/series/57959/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5742_full -> Patchwork_12454_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_12454_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12454_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_12454_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_flip@flip-vs-panning-vs-hang:
- shard-iclb: PASS -> INCOMPLETE +1
Known issues
------------
Here are the changes found in Patchwork_12454_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_param@invalid-param-get:
- shard-snb: NOTRUN -> FAIL [fdo#109559]
* igt@gem_ctx_param@invalid-param-set:
- shard-iclb: NOTRUN -> FAIL [fdo#109674]
* igt@gem_exec_big:
- shard-hsw: PASS -> TIMEOUT [fdo#107936]
* igt@gem_mocs_settings@mocs-reset-bsd2:
- shard-iclb: NOTRUN -> SKIP [fdo#109276] / [fdo#109287] +1
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-iclb: PASS -> INCOMPLETE [fdo#109100] / [fdo#109801]
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-iclb: PASS -> INCOMPLETE [fdo#107713] / [fdo#109766] / [fdo#109801]
* igt@gem_tiled_fence_blits@normal:
- shard-iclb: PASS -> TIMEOUT [fdo#109673] +1
* igt@i915_pm_lpsp@edp-native:
- shard-iclb: NOTRUN -> SKIP [fdo#109301]
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-iclb: NOTRUN -> SKIP [fdo#109293]
* igt@kms_atomic_transition@1x-modeset-transitions:
- shard-skl: PASS -> FAIL [fdo#107815] / [fdo#108470]
* igt@kms_busy@extended-modeset-hang-oldfb-render-d:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +5
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +1
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
- shard-apl: PASS -> FAIL [fdo#107725] / [fdo#108145]
* igt@kms_chamelium@hdmi-crc-abgr8888:
- shard-iclb: NOTRUN -> SKIP [fdo#109284]
* igt@kms_concurrent@pipe-e:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +8
* igt@kms_cursor_crc@cursor-256x256-random:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
- shard-iclb: PASS -> FAIL [fdo#103355] +3
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +71
* igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +59
* igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
- shard-iclb: NOTRUN -> SKIP [fdo#109274] +1
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt:
- shard-iclb: PASS -> FAIL [fdo#103167] +4
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-apl: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite:
- shard-iclb: NOTRUN -> SKIP [fdo#109280] +5
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-iclb: PASS -> FAIL [fdo#109247] +5
* igt@kms_psr@psr2_basic:
- shard-iclb: PASS -> SKIP [fdo#109441]
* igt@kms_psr@sprite_mmap_gtt:
- shard-iclb: PASS -> FAIL [fdo#107383]
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: PASS -> DMESG-FAIL [fdo#105763]
* igt@kms_setmode@basic:
- shard-kbl: PASS -> FAIL [fdo#99912]
* igt@kms_universal_plane@universal-plane-gen9-features-pipe-e:
- shard-iclb: NOTRUN -> SKIP [fdo#109278] +2
* igt@kms_universal_plane@universal-plane-pipe-c-functional:
- shard-glk: PASS -> FAIL [fdo#103166]
* igt@perf_pmu@busy-no-semaphores-vcs1:
- shard-iclb: NOTRUN -> SKIP [fdo#109276] +4
* igt@perf_pmu@rc6-runtime-pm:
- shard-iclb: PASS -> FAIL [fdo#105010]
* igt@prime_busy@wait-hang-blt:
- shard-apl: PASS -> INCOMPLETE [fdo#103927] +1
* igt@prime_nv_pcopy@test2:
- shard-iclb: NOTRUN -> SKIP [fdo#109291]
#### Possible fixes ####
* igt@kms_atomic_transition@plane-all-transition:
- shard-snb: SKIP [fdo#109271] -> PASS
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-kbl: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
- shard-snb: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_chv_cursor_fail@pipe-a-64x64-right-edge:
- shard-snb: SKIP [fdo#109271] / [fdo#109278] -> PASS
* igt@kms_color@pipe-b-degamma:
- shard-apl: FAIL [fdo#104782] -> PASS
* igt@kms_cursor_crc@cursor-128x128-dpms:
- shard-apl: FAIL [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-64x21-sliding:
- shard-skl: FAIL [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-alpha-opaque:
- shard-glk: FAIL [fdo#109350] -> PASS
* igt@kms_cursor_legacy@cursor-vs-flip-legacy:
- shard-iclb: FAIL [fdo#103355] -> PASS
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-iclb: FAIL [fdo#102670] -> PASS
* igt@kms_draw_crc@draw-method-rgb565-blt-ytiled:
- shard-skl: FAIL [fdo#103184] -> PASS
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: FAIL [fdo#105363] -> PASS
* igt@kms_flip@flip-vs-suspend:
- shard-skl: INCOMPLETE [fdo#109507] -> PASS
* igt@kms_flip_tiling@flip-yf-tiled:
- shard-skl: FAIL [fdo#108145] -> PASS
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move:
- shard-glk: FAIL [fdo#103167] -> PASS +2
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: FAIL [fdo#103167] -> PASS +5
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu:
- shard-skl: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render:
- shard-iclb: FAIL [fdo#105682] / [fdo#109247] -> PASS
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-render:
- shard-iclb: FAIL [fdo#109247] -> PASS +20
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: FAIL [fdo#107815] / [fdo#108145] -> PASS
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: FAIL [fdo#107815] -> PASS
* {igt@kms_plane_multiple@atomic-pipe-a-tiling-none}:
- shard-apl: FAIL [fdo#110037] -> PASS +1
* {igt@kms_plane_multiple@atomic-pipe-b-tiling-none}:
- shard-glk: FAIL [fdo#110037] -> PASS +1
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: SKIP [fdo#109441] -> PASS
* igt@kms_psr@sprite_mmap_cpu:
- shard-iclb: FAIL [fdo#107383] -> PASS +3
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: FAIL [fdo#109016] -> PASS
* igt@kms_universal_plane@universal-plane-pipe-b-functional:
- shard-apl: FAIL [fdo#103166] -> PASS
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-skl: INCOMPLETE [fdo#104108] -> PASS
#### Warnings ####
* igt@kms_plane_scaling@pipe-a-scaler-with-rotation:
- shard-glk: SKIP [fdo#109271] / [fdo#109278] -> FAIL [fdo#110098]
* igt@kms_plane_scaling@pipe-b-scaler-with-rotation:
- shard-glk: FAIL [fdo#110098] -> SKIP [fdo#109271] / [fdo#109278]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102670]: https://bugs.freedesktop.org/show_bug.cgi?id=102670
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#105010]: https://bugs.freedesktop.org/show_bug.cgi?id=105010
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725
[fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
[fdo#107936]: https://bugs.freedesktop.org/show_bug.cgi?id=107936
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108470]: https://bugs.freedesktop.org/show_bug.cgi?id=108470
[fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109247]: https://bugs.freedesktop.org/show_bug.cgi?id=109247
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109287]: https://bugs.freedesktop.org/show_bug.cgi?id=109287
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293
[fdo#109301]: https://bugs.freedesktop.org/show_bug.cgi?id=109301
[fdo#109350]: https://bugs.freedesktop.org/show_bug.cgi?id=109350
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#109559]: https://bugs.freedesktop.org/show_bug.cgi?id=109559
[fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
[fdo#109674]: https://bugs.freedesktop.org/show_bug.cgi?id=109674
[fdo#109766]: https://bugs.freedesktop.org/show_bug.cgi?id=109766
[fdo#109801]: https://bugs.freedesktop.org/show_bug.cgi?id=109801
[fdo#110037]: https://bugs.freedesktop.org/show_bug.cgi?id=110037
[fdo#110098]: https://bugs.freedesktop.org/show_bug.cgi?id=110098
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_5742 -> Patchwork_12454
CI_DRM_5742: 519a3f67aadea184cb97720c838946c1ba81c875 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4884: c46051337b972f8b5a302afb6f603df06fea527d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12454: fa9fba049f3704c736e565f1068d03036a36476c @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12454/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/9] drm/i915/ehl: Add EHL platform info and PCI IDs
2019-03-13 21:11 [PATCH 1/9] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
` (11 preceding siblings ...)
2019-03-14 9:30 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2019-03-14 20:43 ` Souza, Jose
2019-03-14 21:34 ` ✗ Fi.CI.BAT: failure for series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs (rev2) Patchwork
2019-03-20 23:10 ` ✗ Fi.CI.BAT: failure for series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs (rev3) Patchwork
14 siblings, 0 replies; 36+ messages in thread
From: Souza, Jose @ 2019-03-14 20:43 UTC (permalink / raw)
To: Vivi, Rodrigo, intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 2609 bytes --]
On Wed, 2019-03-13 at 14:11 -0700, Rodrigo Vivi wrote:
> From: James Ausmus <james.ausmus@intel.com>
>
> Add known EHL PCI IDs.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Cc: Bob Paauwe <bob.j.paauwe@intel.com>
> Signed-off-by: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> arch/x86/kernel/early-quirks.c | 1 +
> drivers/gpu/drm/i915/i915_pci.c | 9 +++++++++
> include/drm/i915_pciids.h | 7 +++++++
> 3 files changed, 17 insertions(+)
>
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-
> quirks.c
> index 50d5848bf22e..a8d2cde67c41 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -547,6 +547,7 @@ static const struct pci_device_id
> intel_early_ids[] __initconst = {
> INTEL_GLK_IDS(&gen9_early_ops),
> INTEL_CNL_IDS(&gen9_early_ops),
> INTEL_ICL_11_IDS(&gen11_early_ops),
> + INTEL_EHL_IDS(&gen11_early_ops),
> };
>
> struct resource intel_graphics_stolen_res __ro_after_init =
> DEFINE_RES_MEM(0, 0);
> diff --git a/drivers/gpu/drm/i915/i915_pci.c
> b/drivers/gpu/drm/i915/i915_pci.c
> index 3cf697e8f1fa..d4d3a904950c 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -724,6 +724,14 @@ static const struct intel_device_info
> intel_icelake_11_info = {
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) |
> BIT(VCS2),
> };
>
> +static const struct intel_device_info intel_elkhartlake_info = {
> + GEN11_FEATURES,
> + PLATFORM(INTEL_ICELAKE),
> + .num_pipes = 3,
> + .is_alpha_support = 1,
> + .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0),
> +};
> +
> #undef GEN
> #undef PLATFORM
>
> @@ -791,6 +799,7 @@ static const struct pci_device_id pciidlist[] = {
> INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
> INTEL_CNL_IDS(&intel_cannonlake_info),
> INTEL_ICL_11_IDS(&intel_icelake_11_info),
> + INTEL_EHL_IDS(&intel_elkhartlake_info),
> {0, 0, 0}
> };
> MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index d200000feeaa..a0e409e9e70d 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -472,4 +472,11 @@
> INTEL_VGA_DEVICE(0x8A70, info), \
> INTEL_VGA_DEVICE(0x8A53, info)
>
> +/* EHL */
> +#define INTEL_EHL_IDS(info) \
> + INTEL_VGA_DEVICE(0x4500, info), \
> + INTEL_VGA_DEVICE(0x4571, info), \
> + INTEL_VGA_DEVICE(0x4551, info), \
> + INTEL_VGA_DEVICE(0x4541, info)
> +
> #endif /* _I915_PCIIDS_H */
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs (rev2)
2019-03-13 21:11 [PATCH 1/9] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
` (12 preceding siblings ...)
2019-03-14 20:43 ` [PATCH 1/9] " Souza, Jose
@ 2019-03-14 21:34 ` Patchwork
2019-03-20 23:10 ` ✗ Fi.CI.BAT: failure for series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs (rev3) Patchwork
14 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2019-03-14 21:34 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs (rev2)
URL : https://patchwork.freedesktop.org/series/57959/
State : failure
== Summary ==
Applying: drm/i915/ehl: Add EHL platform info and PCI IDs
Applying: drm/i915/ehl: Add ElkhartLake platform
Applying: drm/i915/ehl: ehl and icl are both gen11
error: corrupt patch at line 8
error: could not build fake ancestor
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0003 drm/i915/ehl: ehl and icl are both gen11
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs (rev3)
2019-03-13 21:11 [PATCH 1/9] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
` (13 preceding siblings ...)
2019-03-14 21:34 ` ✗ Fi.CI.BAT: failure for series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs (rev2) Patchwork
@ 2019-03-20 23:10 ` Patchwork
14 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2019-03-20 23:10 UTC (permalink / raw)
To: Bob Paauwe; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs (rev3)
URL : https://patchwork.freedesktop.org/series/57959/
State : failure
== Summary ==
Applying: drm/i915/ehl: Add EHL platform info and PCI IDs
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/i915_pci.c
M include/drm/i915_pciids.h
Falling back to patching base and 3-way merge...
Auto-merging include/drm/i915_pciids.h
Auto-merging drivers/gpu/drm/i915/i915_pci.c
Applying: drm/i915/ehl: Add ElkhartLake platform
Applying: drm/i915/ehl: ehl and icl are both gen11
error: corrupt patch at line 8
error: could not build fake ancestor
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0003 drm/i915/ehl: ehl and icl are both gen11
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread