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From: Vidya Sagar <vidyas@nvidia.com>
To: lorenzo.pieralisi@arm.com, bhelgaas@google.com,
	robh+dt@kernel.org, mark.rutland@arm.com,
	thierry.reding@gmail.com, jonathanh@nvidia.com, kishon@ti.com,
	catalin.marinas@arm.com, will.deacon@arm.com,
	jingoohan1@gmail.com, gustavo.pimentel@synopsys.com
Cc: digetx@gmail.com, mperttunen@nvidia.com,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, kthota@nvidia.com,
	mmaddireddy@nvidia.com, vidyas@nvidia.com, sagar.tv@gmail.com
Subject: [PATCH V13 06/12] dt-bindings: PCI: designware: Add binding for CDM register check
Date: Wed, 10 Jul 2019 11:52:06 +0530	[thread overview]
Message-ID: <20190710062212.1745-7-vidyas@nvidia.com> (raw)
In-Reply-To: <20190710062212.1745-1-vidyas@nvidia.com>

Add support to enable CDM (Configuration Dependent Module) registers check
for any data corruption. CDM registers include standard PCIe configuration
space registers, Port Logic registers and iATU and DMA registers.
Refer Section S.4 of Synopsys DesignWare Cores PCI Express Controller Databook
Version 4.90a

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
V13:
* None

V12:
* None

V11:
* None

V10:
* None

V9:
* None

V8:
* None

V7:
* Changed "enable-cdm-check" to "snps,enable-cdm-check"

V6:
* None

V5:
* None

V4:
* None

V3:
* Changed flag name from 'cdm-check' to 'enable-cdm-check'
* Added info about Port Logic and DMA registers being part of CDM

V2:
* This is a new patch in v2 series

 Documentation/devicetree/bindings/pci/designware-pcie.txt | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index 5561a1c060d0..3fba04da6a59 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -34,6 +34,11 @@ Optional properties:
 - clock-names: Must include the following entries:
 	- "pcie"
 	- "pcie_bus"
+- snps,enable-cdm-check: This is a boolean property and if present enables
+   automatic checking of CDM (Configuration Dependent Module) registers
+   for data corruption. CDM registers include standard PCIe configuration
+   space registers, Port Logic registers, DMA and iATU (internal Address
+   Translation Unit) registers.
 RC mode:
 - num-viewport: number of view ports configured in hardware. If a platform
   does not specify it, the driver assumes 2.
-- 
2.17.1

WARNING: multiple messages have this Message-ID (diff)
From: Vidya Sagar <vidyas@nvidia.com>
To: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
	<robh+dt@kernel.org>, <mark.rutland@arm.com>,
	<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
	<kishon@ti.com>, <catalin.marinas@arm.com>, <will.deacon@arm.com>,
	<jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>
Cc: <digetx@gmail.com>, <mperttunen@nvidia.com>,
	<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>, <kthota@nvidia.com>,
	<mmaddireddy@nvidia.com>, <vidyas@nvidia.com>,
	<sagar.tv@gmail.com>
Subject: [PATCH V13 06/12] dt-bindings: PCI: designware: Add binding for CDM register check
Date: Wed, 10 Jul 2019 11:52:06 +0530	[thread overview]
Message-ID: <20190710062212.1745-7-vidyas@nvidia.com> (raw)
In-Reply-To: <20190710062212.1745-1-vidyas@nvidia.com>

Add support to enable CDM (Configuration Dependent Module) registers check
for any data corruption. CDM registers include standard PCIe configuration
space registers, Port Logic registers and iATU and DMA registers.
Refer Section S.4 of Synopsys DesignWare Cores PCI Express Controller Databook
Version 4.90a

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
V13:
* None

V12:
* None

V11:
* None

V10:
* None

V9:
* None

V8:
* None

V7:
* Changed "enable-cdm-check" to "snps,enable-cdm-check"

V6:
* None

V5:
* None

V4:
* None

V3:
* Changed flag name from 'cdm-check' to 'enable-cdm-check'
* Added info about Port Logic and DMA registers being part of CDM

V2:
* This is a new patch in v2 series

 Documentation/devicetree/bindings/pci/designware-pcie.txt | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index 5561a1c060d0..3fba04da6a59 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -34,6 +34,11 @@ Optional properties:
 - clock-names: Must include the following entries:
 	- "pcie"
 	- "pcie_bus"
+- snps,enable-cdm-check: This is a boolean property and if present enables
+   automatic checking of CDM (Configuration Dependent Module) registers
+   for data corruption. CDM registers include standard PCIe configuration
+   space registers, Port Logic registers, DMA and iATU (internal Address
+   Translation Unit) registers.
 RC mode:
 - num-viewport: number of view ports configured in hardware. If a platform
   does not specify it, the driver assumes 2.
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: Vidya Sagar <vidyas@nvidia.com>
To: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
	<robh+dt@kernel.org>,  <mark.rutland@arm.com>,
	<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
	<kishon@ti.com>, <catalin.marinas@arm.com>, <will.deacon@arm.com>,
	<jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>
Cc: devicetree@vger.kernel.org, mmaddireddy@nvidia.com,
	kthota@nvidia.com, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org, mperttunen@nvidia.com,
	linux-tegra@vger.kernel.org, digetx@gmail.com, vidyas@nvidia.com,
	linux-arm-kernel@lists.infradead.org, sagar.tv@gmail.com
Subject: [PATCH V13 06/12] dt-bindings: PCI: designware: Add binding for CDM register check
Date: Wed, 10 Jul 2019 11:52:06 +0530	[thread overview]
Message-ID: <20190710062212.1745-7-vidyas@nvidia.com> (raw)
In-Reply-To: <20190710062212.1745-1-vidyas@nvidia.com>

Add support to enable CDM (Configuration Dependent Module) registers check
for any data corruption. CDM registers include standard PCIe configuration
space registers, Port Logic registers and iATU and DMA registers.
Refer Section S.4 of Synopsys DesignWare Cores PCI Express Controller Databook
Version 4.90a

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
V13:
* None

V12:
* None

V11:
* None

V10:
* None

V9:
* None

V8:
* None

V7:
* Changed "enable-cdm-check" to "snps,enable-cdm-check"

V6:
* None

V5:
* None

V4:
* None

V3:
* Changed flag name from 'cdm-check' to 'enable-cdm-check'
* Added info about Port Logic and DMA registers being part of CDM

V2:
* This is a new patch in v2 series

 Documentation/devicetree/bindings/pci/designware-pcie.txt | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index 5561a1c060d0..3fba04da6a59 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -34,6 +34,11 @@ Optional properties:
 - clock-names: Must include the following entries:
 	- "pcie"
 	- "pcie_bus"
+- snps,enable-cdm-check: This is a boolean property and if present enables
+   automatic checking of CDM (Configuration Dependent Module) registers
+   for data corruption. CDM registers include standard PCIe configuration
+   space registers, Port Logic registers, DMA and iATU (internal Address
+   Translation Unit) registers.
 RC mode:
 - num-viewport: number of view ports configured in hardware. If a platform
   does not specify it, the driver assumes 2.
-- 
2.17.1


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  parent reply	other threads:[~2019-07-10  6:22 UTC|newest]

Thread overview: 90+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-10  6:22 [PATCH V13 00/12] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-07-10  6:22 ` Vidya Sagar
2019-07-10  6:22 ` Vidya Sagar
2019-07-10  6:22 ` [PATCH V13 01/12] PCI: Add #defines for some of PCIe spec r4.0 features Vidya Sagar
2019-07-10  6:22   ` Vidya Sagar
2019-07-10  6:22   ` Vidya Sagar
2019-07-10 20:14   ` Bjorn Helgaas
2019-07-10 20:14     ` Bjorn Helgaas
2019-07-10  6:22 ` [PATCH V13 02/12] PCI: Disable MSI for Tegra root ports Vidya Sagar
2019-07-10  6:22   ` Vidya Sagar
2019-07-10  6:22   ` Vidya Sagar
2019-07-10  6:22 ` [PATCH V13 03/12] PCI: dwc: Perform dbi regs write lock towards the end Vidya Sagar
2019-07-10  6:22   ` Vidya Sagar
2019-07-10  6:22   ` Vidya Sagar
2019-07-10  6:22 ` [PATCH V13 04/12] PCI: dwc: Move config space capability search API Vidya Sagar
2019-07-10  6:22   ` Vidya Sagar
2019-07-10  6:22   ` Vidya Sagar
2019-07-10  6:22 ` [PATCH V13 05/12] PCI: dwc: Add ext " Vidya Sagar
2019-07-10  6:22   ` Vidya Sagar
2019-07-10  6:22   ` Vidya Sagar
2019-07-10 10:37   ` Lorenzo Pieralisi
2019-07-10 10:37     ` Lorenzo Pieralisi
2019-07-10 11:27     ` Vidya Sagar
2019-07-10 11:27       ` Vidya Sagar
2019-07-10 11:27       ` Vidya Sagar
2019-07-10 14:19       ` Lorenzo Pieralisi
2019-07-10 14:19         ` Lorenzo Pieralisi
2019-07-10  6:22 ` Vidya Sagar [this message]
2019-07-10  6:22   ` [PATCH V13 06/12] dt-bindings: PCI: designware: Add binding for CDM register check Vidya Sagar
2019-07-10  6:22   ` Vidya Sagar
2019-07-10  6:22 ` [PATCH V13 07/12] PCI: dwc: Add support to enable " Vidya Sagar
2019-07-10  6:22   ` Vidya Sagar
2019-07-10  6:22   ` Vidya Sagar
2019-07-10  6:22 ` [PATCH V13 08/12] dt-bindings: Add PCIe supports-clkreq property Vidya Sagar
2019-07-10  6:22   ` Vidya Sagar
2019-07-10  6:22   ` Vidya Sagar
2019-07-10 15:28   ` Lorenzo Pieralisi
2019-07-10 15:28     ` Lorenzo Pieralisi
2019-07-10 17:14     ` Vidya Sagar
2019-07-10 17:14       ` Vidya Sagar
2019-07-10 17:14       ` Vidya Sagar
2019-07-10  6:22 ` [PATCH V13 09/12] dt-bindings: PCI: tegra: Add device tree support for Tegra194 Vidya Sagar
2019-07-10  6:22   ` Vidya Sagar
2019-07-10  6:22   ` Vidya Sagar
2019-07-10  6:22 ` [PATCH V13 10/12] dt-bindings: PHY: P2U: Add Tegra194 P2U block Vidya Sagar
2019-07-10  6:22   ` Vidya Sagar
2019-07-10  6:22   ` Vidya Sagar
2019-07-10  6:22 ` [PATCH V13 11/12] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar
2019-07-10  6:22   ` Vidya Sagar
2019-07-10  6:22   ` Vidya Sagar
2019-07-10  6:22 ` [PATCH V13 12/12] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-07-10  6:22   ` Vidya Sagar
2019-07-10  6:22   ` Vidya Sagar
2019-07-10 17:02   ` Lorenzo Pieralisi
2019-07-10 17:02     ` Lorenzo Pieralisi
2019-07-10 17:26     ` Vidya Sagar
2019-07-10 17:26       ` Vidya Sagar
2019-07-10 17:26       ` Vidya Sagar
2019-07-11 12:54   ` Lorenzo Pieralisi
2019-07-11 12:54     ` Lorenzo Pieralisi
2019-07-12 15:32     ` Vidya Sagar
2019-07-12 15:32       ` Vidya Sagar
2019-07-12 15:32       ` Vidya Sagar
2019-07-12 16:07       ` Lorenzo Pieralisi
2019-07-12 16:07         ` Lorenzo Pieralisi
2019-07-13  7:04         ` Vidya Sagar
2019-07-13  7:04           ` Vidya Sagar
2019-07-13  7:04           ` Vidya Sagar
2019-07-16 11:22           ` Lorenzo Pieralisi
2019-07-16 11:22             ` Lorenzo Pieralisi
2019-07-16 19:00             ` Bjorn Helgaas
2019-07-16 19:00               ` Bjorn Helgaas
2019-07-23 14:28               ` Vidya Sagar
2019-07-23 14:28                 ` Vidya Sagar
2019-07-23 14:28                 ` Vidya Sagar
2019-07-23 14:44             ` Vidya Sagar
2019-07-23 14:44               ` Vidya Sagar
2019-07-23 14:44               ` Vidya Sagar
2019-07-30 15:49               ` Lorenzo Pieralisi
2019-07-30 15:49                 ` Lorenzo Pieralisi
2019-08-02 12:06                 ` Vidya Sagar
2019-08-02 12:06                   ` Vidya Sagar
2019-08-02 12:06                   ` Vidya Sagar
2019-08-05 14:01                   ` Lorenzo Pieralisi
2019-08-05 14:01                     ` Lorenzo Pieralisi
2019-08-05 16:54                     ` Vidya Sagar
2019-08-05 16:54                       ` Vidya Sagar
2019-08-05 16:54                       ` Vidya Sagar
2019-08-06 14:51                       ` Lorenzo Pieralisi
2019-08-06 14:51                         ` Lorenzo Pieralisi

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