From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> To: Vidya Sagar <vidyas@nvidia.com> Cc: bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com, thierry.reding@gmail.com, jonathanh@nvidia.com, kishon@ti.com, catalin.marinas@arm.com, will.deacon@arm.com, jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, digetx@gmail.com, mperttunen@nvidia.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kthota@nvidia.com, mmaddireddy@nvidia.com, sagar.tv@gmail.com Subject: Re: [PATCH V13 05/12] PCI: dwc: Add ext config space capability search API Date: Wed, 10 Jul 2019 11:37:09 +0100 [thread overview] Message-ID: <20190710103709.GA4063@e121166-lin.cambridge.arm.com> (raw) In-Reply-To: <20190710062212.1745-6-vidyas@nvidia.com> On Wed, Jul 10, 2019 at 11:52:05AM +0530, Vidya Sagar wrote: > Add extended configuration space capability search API using struct dw_pcie * > pointer Sentences are terminated with a period and this is v13 not v1, which proves that you do not read the commit logs you write. I need you guys to understand that I can't rewrite commit logs all the time, I do not want to go as far as not accepting your patches anymore so please do pay attention to commit log details they are as important as the code itself. https://lore.kernel.org/linux-pci/20171026223701.GA25649@bhelgaas-glaptop.roam.corp.google.com/ Thanks, Lorenzo > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> > Acked-by: Thierry Reding <treding@nvidia.com> > --- > V13: > * None > > V12: > * None > > V11: > * None > > V10: > * None > > V9: > * Added Acked-by from Thierry > > V8: > * Changed data types of return and arguments to be inline with data being returned > and passed. > > V7: > * None > > V6: > * None > > V5: > * None > > V4: > * None > > V3: > * None > > V2: > * This is a new patch in v2 series > > drivers/pci/controller/dwc/pcie-designware.c | 41 ++++++++++++++++++++ > drivers/pci/controller/dwc/pcie-designware.h | 1 + > 2 files changed, 42 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index 7818b4febb08..181449e342f1 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -53,6 +53,47 @@ u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) > } > EXPORT_SYMBOL_GPL(dw_pcie_find_capability); > > +static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start, > + u8 cap) > +{ > + u32 header; > + int ttl; > + int pos = PCI_CFG_SPACE_SIZE; > + > + /* minimum 8 bytes per capability */ > + ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; > + > + if (start) > + pos = start; > + > + header = dw_pcie_readl_dbi(pci, pos); > + /* > + * If we have no capabilities, this is indicated by cap ID, > + * cap version and next pointer all being 0. > + */ > + if (header == 0) > + return 0; > + > + while (ttl-- > 0) { > + if (PCI_EXT_CAP_ID(header) == cap && pos != start) > + return pos; > + > + pos = PCI_EXT_CAP_NEXT(header); > + if (pos < PCI_CFG_SPACE_SIZE) > + break; > + > + header = dw_pcie_readl_dbi(pci, pos); > + } > + > + return 0; > +} > + > +u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) > +{ > + return dw_pcie_find_next_ext_capability(pci, 0, cap); > +} > +EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability); > + > int dw_pcie_read(void __iomem *addr, int size, u32 *val) > { > if (!IS_ALIGNED((uintptr_t)addr, size)) { > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index d8c66a6827dc..11c223471416 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -252,6 +252,7 @@ struct dw_pcie { > container_of((endpoint), struct dw_pcie, ep) > > u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap); > +u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap); > > int dw_pcie_read(void __iomem *addr, int size, u32 *val); > int dw_pcie_write(void __iomem *addr, int size, u32 val); > -- > 2.17.1 >
WARNING: multiple messages have this Message-ID (diff)
From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> To: Vidya Sagar <vidyas@nvidia.com> Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, mperttunen@nvidia.com, mmaddireddy@nvidia.com, linux-pci@vger.kernel.org, catalin.marinas@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, kthota@nvidia.com, kishon@ti.com, linux-tegra@vger.kernel.org, robh+dt@kernel.org, thierry.reding@gmail.com, gustavo.pimentel@synopsys.com, jingoohan1@gmail.com, bhelgaas@google.com, digetx@gmail.com, jonathanh@nvidia.com, linux-arm-kernel@lists.infradead.org, sagar.tv@gmail.com Subject: Re: [PATCH V13 05/12] PCI: dwc: Add ext config space capability search API Date: Wed, 10 Jul 2019 11:37:09 +0100 [thread overview] Message-ID: <20190710103709.GA4063@e121166-lin.cambridge.arm.com> (raw) In-Reply-To: <20190710062212.1745-6-vidyas@nvidia.com> On Wed, Jul 10, 2019 at 11:52:05AM +0530, Vidya Sagar wrote: > Add extended configuration space capability search API using struct dw_pcie * > pointer Sentences are terminated with a period and this is v13 not v1, which proves that you do not read the commit logs you write. I need you guys to understand that I can't rewrite commit logs all the time, I do not want to go as far as not accepting your patches anymore so please do pay attention to commit log details they are as important as the code itself. https://lore.kernel.org/linux-pci/20171026223701.GA25649@bhelgaas-glaptop.roam.corp.google.com/ Thanks, Lorenzo > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> > Acked-by: Thierry Reding <treding@nvidia.com> > --- > V13: > * None > > V12: > * None > > V11: > * None > > V10: > * None > > V9: > * Added Acked-by from Thierry > > V8: > * Changed data types of return and arguments to be inline with data being returned > and passed. > > V7: > * None > > V6: > * None > > V5: > * None > > V4: > * None > > V3: > * None > > V2: > * This is a new patch in v2 series > > drivers/pci/controller/dwc/pcie-designware.c | 41 ++++++++++++++++++++ > drivers/pci/controller/dwc/pcie-designware.h | 1 + > 2 files changed, 42 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index 7818b4febb08..181449e342f1 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -53,6 +53,47 @@ u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) > } > EXPORT_SYMBOL_GPL(dw_pcie_find_capability); > > +static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start, > + u8 cap) > +{ > + u32 header; > + int ttl; > + int pos = PCI_CFG_SPACE_SIZE; > + > + /* minimum 8 bytes per capability */ > + ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; > + > + if (start) > + pos = start; > + > + header = dw_pcie_readl_dbi(pci, pos); > + /* > + * If we have no capabilities, this is indicated by cap ID, > + * cap version and next pointer all being 0. > + */ > + if (header == 0) > + return 0; > + > + while (ttl-- > 0) { > + if (PCI_EXT_CAP_ID(header) == cap && pos != start) > + return pos; > + > + pos = PCI_EXT_CAP_NEXT(header); > + if (pos < PCI_CFG_SPACE_SIZE) > + break; > + > + header = dw_pcie_readl_dbi(pci, pos); > + } > + > + return 0; > +} > + > +u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) > +{ > + return dw_pcie_find_next_ext_capability(pci, 0, cap); > +} > +EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability); > + > int dw_pcie_read(void __iomem *addr, int size, u32 *val) > { > if (!IS_ALIGNED((uintptr_t)addr, size)) { > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index d8c66a6827dc..11c223471416 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -252,6 +252,7 @@ struct dw_pcie { > container_of((endpoint), struct dw_pcie, ep) > > u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap); > +u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap); > > int dw_pcie_read(void __iomem *addr, int size, u32 *val); > int dw_pcie_write(void __iomem *addr, int size, u32 val); > -- > 2.17.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-07-10 10:37 UTC|newest] Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-07-10 6:22 [PATCH V13 00/12] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` [PATCH V13 01/12] PCI: Add #defines for some of PCIe spec r4.0 features Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 20:14 ` Bjorn Helgaas 2019-07-10 20:14 ` Bjorn Helgaas 2019-07-10 6:22 ` [PATCH V13 02/12] PCI: Disable MSI for Tegra root ports Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` [PATCH V13 03/12] PCI: dwc: Perform dbi regs write lock towards the end Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` [PATCH V13 04/12] PCI: dwc: Move config space capability search API Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` [PATCH V13 05/12] PCI: dwc: Add ext " Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 10:37 ` Lorenzo Pieralisi [this message] 2019-07-10 10:37 ` Lorenzo Pieralisi 2019-07-10 11:27 ` Vidya Sagar 2019-07-10 11:27 ` Vidya Sagar 2019-07-10 11:27 ` Vidya Sagar 2019-07-10 14:19 ` Lorenzo Pieralisi 2019-07-10 14:19 ` Lorenzo Pieralisi 2019-07-10 6:22 ` [PATCH V13 06/12] dt-bindings: PCI: designware: Add binding for CDM register check Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` [PATCH V13 07/12] PCI: dwc: Add support to enable " Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` [PATCH V13 08/12] dt-bindings: Add PCIe supports-clkreq property Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 15:28 ` Lorenzo Pieralisi 2019-07-10 15:28 ` Lorenzo Pieralisi 2019-07-10 17:14 ` Vidya Sagar 2019-07-10 17:14 ` Vidya Sagar 2019-07-10 17:14 ` Vidya Sagar 2019-07-10 6:22 ` [PATCH V13 09/12] dt-bindings: PCI: tegra: Add device tree support for Tegra194 Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` [PATCH V13 10/12] dt-bindings: PHY: P2U: Add Tegra194 P2U block Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` [PATCH V13 11/12] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` [PATCH V13 12/12] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 17:02 ` Lorenzo Pieralisi 2019-07-10 17:02 ` Lorenzo Pieralisi 2019-07-10 17:26 ` Vidya Sagar 2019-07-10 17:26 ` Vidya Sagar 2019-07-10 17:26 ` Vidya Sagar 2019-07-11 12:54 ` Lorenzo Pieralisi 2019-07-11 12:54 ` Lorenzo Pieralisi 2019-07-12 15:32 ` Vidya Sagar 2019-07-12 15:32 ` Vidya Sagar 2019-07-12 15:32 ` Vidya Sagar 2019-07-12 16:07 ` Lorenzo Pieralisi 2019-07-12 16:07 ` Lorenzo Pieralisi 2019-07-13 7:04 ` Vidya Sagar 2019-07-13 7:04 ` Vidya Sagar 2019-07-13 7:04 ` Vidya Sagar 2019-07-16 11:22 ` Lorenzo Pieralisi 2019-07-16 11:22 ` Lorenzo Pieralisi 2019-07-16 19:00 ` Bjorn Helgaas 2019-07-16 19:00 ` Bjorn Helgaas 2019-07-23 14:28 ` Vidya Sagar 2019-07-23 14:28 ` Vidya Sagar 2019-07-23 14:28 ` Vidya Sagar 2019-07-23 14:44 ` Vidya Sagar 2019-07-23 14:44 ` Vidya Sagar 2019-07-23 14:44 ` Vidya Sagar 2019-07-30 15:49 ` Lorenzo Pieralisi 2019-07-30 15:49 ` Lorenzo Pieralisi 2019-08-02 12:06 ` Vidya Sagar 2019-08-02 12:06 ` Vidya Sagar 2019-08-02 12:06 ` Vidya Sagar 2019-08-05 14:01 ` Lorenzo Pieralisi 2019-08-05 14:01 ` Lorenzo Pieralisi 2019-08-05 16:54 ` Vidya Sagar 2019-08-05 16:54 ` Vidya Sagar 2019-08-05 16:54 ` Vidya Sagar 2019-08-06 14:51 ` Lorenzo Pieralisi 2019-08-06 14:51 ` Lorenzo Pieralisi
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