From: Bjorn Helgaas <helgaas@kernel.org> To: Vidya Sagar <vidyas@nvidia.com> Cc: lorenzo.pieralisi@arm.com, robh+dt@kernel.org, mark.rutland@arm.com, thierry.reding@gmail.com, jonathanh@nvidia.com, kishon@ti.com, catalin.marinas@arm.com, will.deacon@arm.com, jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, digetx@gmail.com, mperttunen@nvidia.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kthota@nvidia.com, mmaddireddy@nvidia.com, sagar.tv@gmail.com Subject: Re: [PATCH V13 01/12] PCI: Add #defines for some of PCIe spec r4.0 features Date: Wed, 10 Jul 2019 15:14:34 -0500 [thread overview] Message-ID: <20190710201433.GC35486@google.com> (raw) In-Reply-To: <20190710062212.1745-2-vidyas@nvidia.com> On Wed, Jul 10, 2019 at 11:52:01AM +0530, Vidya Sagar wrote: > Add #defines only for the Data Link Feature and Physical Layer 16.0 GT/s > features as defined in PCIe spec r4.0, sec 7.7.4 for Data Link Feature and > sec 7.7.5 for Physical Layer 16.0 GT/s. > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Looks good, thanks! > --- > V13: > * Updated commit message to include references from spec > * Removed unused defines and moved some from pcie-tegra194.c file > * Addressed review comments from Bjorn > > V12: > * None > > V11: > * None > > V10: > * None > > V9: > * None > > V8: > * None > > V7: > * None > > V6: > * None > > V5: > * None > > V4: > * None > > V3: > * Updated commit message and description to explicitly mention that defines are > added only for some of the features and not all. > > V2: > * None > > include/uapi/linux/pci_regs.h | 14 +++++++++++++- > 1 file changed, 13 insertions(+), 1 deletion(-) > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index f28e562d7ca8..d28d0319d932 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -713,7 +713,9 @@ > #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ > #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ > #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ > -#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM > +#define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ > +#define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ > +#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT > > #define PCI_EXT_CAP_DSN_SIZEOF 12 > #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 > @@ -1053,4 +1055,14 @@ > #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */ > #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */ > > +/* Data Link Feature */ > +#define PCI_DLF_CAP 0x04 /* Capabilities Register */ > +#define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */ > + > +/* Physical Layer 16.0 GT/s */ > +#define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */ > +#define PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK 0x0000000F > +#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK 0x000000F0 > +#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4 > + > #endif /* LINUX_PCI_REGS_H */ > -- > 2.17.1 >
WARNING: multiple messages have this Message-ID (diff)
From: Bjorn Helgaas <helgaas@kernel.org> To: Vidya Sagar <vidyas@nvidia.com> Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com, mperttunen@nvidia.com, mmaddireddy@nvidia.com, linux-pci@vger.kernel.org, catalin.marinas@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, kishon@ti.com, kthota@nvidia.com, thierry.reding@gmail.com, gustavo.pimentel@synopsys.com, jingoohan1@gmail.com, linux-tegra@vger.kernel.org, digetx@gmail.com, jonathanh@nvidia.com, linux-arm-kernel@lists.infradead.org, sagar.tv@gmail.com Subject: Re: [PATCH V13 01/12] PCI: Add #defines for some of PCIe spec r4.0 features Date: Wed, 10 Jul 2019 15:14:34 -0500 [thread overview] Message-ID: <20190710201433.GC35486@google.com> (raw) In-Reply-To: <20190710062212.1745-2-vidyas@nvidia.com> On Wed, Jul 10, 2019 at 11:52:01AM +0530, Vidya Sagar wrote: > Add #defines only for the Data Link Feature and Physical Layer 16.0 GT/s > features as defined in PCIe spec r4.0, sec 7.7.4 for Data Link Feature and > sec 7.7.5 for Physical Layer 16.0 GT/s. > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Looks good, thanks! > --- > V13: > * Updated commit message to include references from spec > * Removed unused defines and moved some from pcie-tegra194.c file > * Addressed review comments from Bjorn > > V12: > * None > > V11: > * None > > V10: > * None > > V9: > * None > > V8: > * None > > V7: > * None > > V6: > * None > > V5: > * None > > V4: > * None > > V3: > * Updated commit message and description to explicitly mention that defines are > added only for some of the features and not all. > > V2: > * None > > include/uapi/linux/pci_regs.h | 14 +++++++++++++- > 1 file changed, 13 insertions(+), 1 deletion(-) > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index f28e562d7ca8..d28d0319d932 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -713,7 +713,9 @@ > #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ > #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ > #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ > -#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM > +#define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ > +#define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ > +#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT > > #define PCI_EXT_CAP_DSN_SIZEOF 12 > #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 > @@ -1053,4 +1055,14 @@ > #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */ > #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */ > > +/* Data Link Feature */ > +#define PCI_DLF_CAP 0x04 /* Capabilities Register */ > +#define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */ > + > +/* Physical Layer 16.0 GT/s */ > +#define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */ > +#define PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK 0x0000000F > +#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK 0x000000F0 > +#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4 > + > #endif /* LINUX_PCI_REGS_H */ > -- > 2.17.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-07-10 20:14 UTC|newest] Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-07-10 6:22 [PATCH V13 00/12] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` [PATCH V13 01/12] PCI: Add #defines for some of PCIe spec r4.0 features Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 20:14 ` Bjorn Helgaas [this message] 2019-07-10 20:14 ` Bjorn Helgaas 2019-07-10 6:22 ` [PATCH V13 02/12] PCI: Disable MSI for Tegra root ports Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` [PATCH V13 03/12] PCI: dwc: Perform dbi regs write lock towards the end Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` [PATCH V13 04/12] PCI: dwc: Move config space capability search API Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` [PATCH V13 05/12] PCI: dwc: Add ext " Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 10:37 ` Lorenzo Pieralisi 2019-07-10 10:37 ` Lorenzo Pieralisi 2019-07-10 11:27 ` Vidya Sagar 2019-07-10 11:27 ` Vidya Sagar 2019-07-10 11:27 ` Vidya Sagar 2019-07-10 14:19 ` Lorenzo Pieralisi 2019-07-10 14:19 ` Lorenzo Pieralisi 2019-07-10 6:22 ` [PATCH V13 06/12] dt-bindings: PCI: designware: Add binding for CDM register check Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` [PATCH V13 07/12] PCI: dwc: Add support to enable " Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` [PATCH V13 08/12] dt-bindings: Add PCIe supports-clkreq property Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 15:28 ` Lorenzo Pieralisi 2019-07-10 15:28 ` Lorenzo Pieralisi 2019-07-10 17:14 ` Vidya Sagar 2019-07-10 17:14 ` Vidya Sagar 2019-07-10 17:14 ` Vidya Sagar 2019-07-10 6:22 ` [PATCH V13 09/12] dt-bindings: PCI: tegra: Add device tree support for Tegra194 Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` [PATCH V13 10/12] dt-bindings: PHY: P2U: Add Tegra194 P2U block Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` [PATCH V13 11/12] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` [PATCH V13 12/12] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 6:22 ` Vidya Sagar 2019-07-10 17:02 ` Lorenzo Pieralisi 2019-07-10 17:02 ` Lorenzo Pieralisi 2019-07-10 17:26 ` Vidya Sagar 2019-07-10 17:26 ` Vidya Sagar 2019-07-10 17:26 ` Vidya Sagar 2019-07-11 12:54 ` Lorenzo Pieralisi 2019-07-11 12:54 ` Lorenzo Pieralisi 2019-07-12 15:32 ` Vidya Sagar 2019-07-12 15:32 ` Vidya Sagar 2019-07-12 15:32 ` Vidya Sagar 2019-07-12 16:07 ` Lorenzo Pieralisi 2019-07-12 16:07 ` Lorenzo Pieralisi 2019-07-13 7:04 ` Vidya Sagar 2019-07-13 7:04 ` Vidya Sagar 2019-07-13 7:04 ` Vidya Sagar 2019-07-16 11:22 ` Lorenzo Pieralisi 2019-07-16 11:22 ` Lorenzo Pieralisi 2019-07-16 19:00 ` Bjorn Helgaas 2019-07-16 19:00 ` Bjorn Helgaas 2019-07-23 14:28 ` Vidya Sagar 2019-07-23 14:28 ` Vidya Sagar 2019-07-23 14:28 ` Vidya Sagar 2019-07-23 14:44 ` Vidya Sagar 2019-07-23 14:44 ` Vidya Sagar 2019-07-23 14:44 ` Vidya Sagar 2019-07-30 15:49 ` Lorenzo Pieralisi 2019-07-30 15:49 ` Lorenzo Pieralisi 2019-08-02 12:06 ` Vidya Sagar 2019-08-02 12:06 ` Vidya Sagar 2019-08-02 12:06 ` Vidya Sagar 2019-08-05 14:01 ` Lorenzo Pieralisi 2019-08-05 14:01 ` Lorenzo Pieralisi 2019-08-05 16:54 ` Vidya Sagar 2019-08-05 16:54 ` Vidya Sagar 2019-08-05 16:54 ` Vidya Sagar 2019-08-06 14:51 ` Lorenzo Pieralisi 2019-08-06 14:51 ` Lorenzo Pieralisi
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20190710201433.GC35486@google.com \ --to=helgaas@kernel.org \ --cc=catalin.marinas@arm.com \ --cc=devicetree@vger.kernel.org \ --cc=digetx@gmail.com \ --cc=gustavo.pimentel@synopsys.com \ --cc=jingoohan1@gmail.com \ --cc=jonathanh@nvidia.com \ --cc=kishon@ti.com \ --cc=kthota@nvidia.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-pci@vger.kernel.org \ --cc=linux-tegra@vger.kernel.org \ --cc=lorenzo.pieralisi@arm.com \ --cc=mark.rutland@arm.com \ --cc=mmaddireddy@nvidia.com \ --cc=mperttunen@nvidia.com \ --cc=robh+dt@kernel.org \ --cc=sagar.tv@gmail.com \ --cc=thierry.reding@gmail.com \ --cc=vidyas@nvidia.com \ --cc=will.deacon@arm.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.