From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Swati Sharma <swati2.sharma@intel.com>, dri-devel@lists.freedesktop.org
Subject: [PATCH 10/12] drm/i915: Refactor LUT read functions
Date: Thu, 7 Nov 2019 17:17:23 +0200 [thread overview]
Message-ID: <20191107151725.10507-11-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20191107151725.10507-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Extract all the 'hw value -> LUT entry' stuff into small helpers
to make the main 'read out the entire LUT' loop less bogged down
by such mundane details.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 128 ++++++++++-----------
1 file changed, 64 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index d6a20d7522a9..4b2bd5ac0e8d 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -367,6 +367,19 @@ static void chv_load_cgm_csc(struct intel_crtc *crtc,
I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
}
+/* convert hw value with given bit_precision to lut property val */
+static u32 intel_color_lut_pack(u32 val, int bit_precision)
+{
+ u32 max = 0xffff >> (16 - bit_precision);
+
+ val = clamp_val(val, 0, max);
+
+ if (bit_precision < 16)
+ val <<= 16 - bit_precision;
+
+ return val;
+}
+
static u32 i9xx_lut_8(const struct drm_color_lut *color)
{
return drm_color_lut_extract(color->red, 8) << 16 |
@@ -374,6 +387,13 @@ static u32 i9xx_lut_8(const struct drm_color_lut *color)
drm_color_lut_extract(color->blue, 8);
}
+static void i9xx_lut_8_pack(struct drm_color_lut *entry, u32 val)
+{
+ entry->red = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_RED_MASK, val), 8);
+ entry->green = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_GREEN_MASK, val), 8);
+ entry->blue = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_BLUE_MASK, val), 8);
+}
+
/* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */
static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color)
{
@@ -390,6 +410,21 @@ static u32 i965_lut_10p6_udw(const struct drm_color_lut *color)
(color->blue >> 8);
}
+static void i965_lut_10p6_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
+{
+ entry->red = REG_FIELD_GET(PALETTE_RED_MASK, udw) << 8 |
+ REG_FIELD_GET(PALETTE_RED_MASK, ldw);
+ entry->green = REG_FIELD_GET(PALETTE_GREEN_MASK, udw) << 8 |
+ REG_FIELD_GET(PALETTE_GREEN_MASK, ldw);
+ entry->blue = REG_FIELD_GET(PALETTE_BLUE_MASK, udw) << 8 |
+ REG_FIELD_GET(PALETTE_BLUE_MASK, ldw);
+}
+
+static u16 i965_lut_11p6_max_pack(u32 val)
+{
+ return REG_FIELD_GET(PIPEGCMAX_RGB_MASK, val);
+}
+
static u32 ilk_lut_10(const struct drm_color_lut *color)
{
return drm_color_lut_extract(color->red, 10) << 20 |
@@ -397,6 +432,13 @@ static u32 ilk_lut_10(const struct drm_color_lut *color)
drm_color_lut_extract(color->blue, 10);
}
+static void ilk_lut_10_pack(struct drm_color_lut *entry, u32 val)
+{
+ entry->red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_RED_MASK, val), 10);
+ entry->green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_GREEN_MASK, val), 10);
+ entry->blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10);
+}
+
static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -953,6 +995,13 @@ static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color)
return drm_color_lut_extract(color->red, 14);
}
+static void chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
+{
+ entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_MASK, ldw), 10);
+ entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_MASK, ldw), 10);
+ entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK, udw), 10);
+}
+
static void chv_load_cgm_degamma(struct intel_crtc *crtc,
const struct drm_property_blob *blob)
{
@@ -1640,19 +1689,6 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
return true;
}
-/* convert hw value with given bit_precision to lut property val */
-static u32 intel_color_lut_pack(u32 val, int bit_precision)
-{
- u32 max = 0xffff >> (16 - bit_precision);
-
- val = clamp_val(val, 0, max);
-
- if (bit_precision < 16)
- val <<= 16 - bit_precision;
-
- return val;
-}
-
static struct drm_property_blob *
i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
{
@@ -1674,12 +1710,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
u32 val = I915_READ(PALETTE(pipe, i));
- lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
- LGC_PALETTE_RED_MASK, val), 8);
- lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
- LGC_PALETTE_GREEN_MASK, val), 8);
- lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
- LGC_PALETTE_BLUE_MASK, val), 8);
+ i9xx_lut_8_pack(&lut[i], val);
}
return blob;
@@ -1712,23 +1743,15 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
lut = blob->data;
for (i = 0; i < lut_size - 1; i++) {
- u32 val1 = I915_READ(PALETTE(pipe, 2 * i + 0));
- u32 val2 = I915_READ(PALETTE(pipe, 2 * i + 1));
-
- lut[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
- REG_FIELD_GET(PALETTE_RED_MASK, val1);
- lut[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 |
- REG_FIELD_GET(PALETTE_GREEN_MASK, val1);
- lut[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 |
- REG_FIELD_GET(PALETTE_BLUE_MASK, val1);
+ u32 ldw = I915_READ(PALETTE(pipe, 2 * i + 0));
+ u32 udw = I915_READ(PALETTE(pipe, 2 * i + 1));
+
+ i965_lut_10p6_pack(&lut[i], ldw, udw);
}
- lut[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
- I915_READ(PIPEGCMAX(pipe, 0)));
- lut[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
- I915_READ(PIPEGCMAX(pipe, 1)));
- lut[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
- I915_READ(PIPEGCMAX(pipe, 2)));
+ lut[i].red = i965_lut_11p6_max_pack(I915_READ(PIPEGCMAX(pipe, 0)));
+ lut[i].green = i965_lut_11p6_max_pack(I915_READ(PIPEGCMAX(pipe, 1)));
+ lut[i].blue = i965_lut_11p6_max_pack(I915_READ(PIPEGCMAX(pipe, 2)));
return blob;
}
@@ -1763,17 +1786,10 @@ chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
lut = blob->data;
for (i = 0; i < lut_size; i++) {
- u32 val;
-
- val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 0));
- lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
- CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
- lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
- CGM_PIPE_GAMMA_BLUE_MASK, val), 10);
+ u32 ldw = I915_READ(CGM_PIPE_GAMMA(pipe, i, 0));
+ u32 udw = I915_READ(CGM_PIPE_GAMMA(pipe, i, 1));
- val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 1));
- lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
- CGM_PIPE_GAMMA_RED_MASK, val), 10);
+ chv_cgm_gamma_pack(&lut[i], ldw, udw);
}
return blob;
@@ -1808,12 +1824,7 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
u32 val = I915_READ(LGC_PALETTE(pipe, i));
- lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
- LGC_PALETTE_RED_MASK, val), 8);
- lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
- LGC_PALETTE_GREEN_MASK, val), 8);
- lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
- LGC_PALETTE_BLUE_MASK, val), 8);
+ i9xx_lut_8_pack(&lut[i], val);
}
return blob;
@@ -1840,12 +1851,7 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
for (i = 0; i < lut_size; i++) {
u32 val = I915_READ(PREC_PALETTE(pipe, i));
- lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
- PREC_PALETTE_RED_MASK, val), 10);
- lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
- PREC_PALETTE_GREEN_MASK, val), 10);
- lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
- PREC_PALETTE_BLUE_MASK, val), 10);
+ ilk_lut_10_pack(&lut[i], val);
}
return blob;
@@ -1883,18 +1889,12 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
lut = blob->data;
- I915_WRITE(PREC_PAL_INDEX(pipe), prec_index |
- PAL_PREC_AUTO_INCREMENT);
+ I915_WRITE(PREC_PAL_INDEX(pipe), prec_index | PAL_PREC_AUTO_INCREMENT);
for (i = 0; i < hw_lut_size; i++) {
u32 val = I915_READ(PREC_PAL_DATA(pipe));
- lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
- PREC_PAL_DATA_RED_MASK, val), 10);
- lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
- PREC_PAL_DATA_GREEN_MASK, val), 10);
- lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
- PREC_PAL_DATA_BLUE_MASK, val), 10);
+ ilk_lut_10_pack(&lut[i], val);
}
I915_WRITE(PREC_PAL_INDEX(pipe), 0);
--
2.23.0
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WARNING: multiple messages have this Message-ID (diff)
From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 10/12] drm/i915: Refactor LUT read functions
Date: Thu, 7 Nov 2019 17:17:23 +0200 [thread overview]
Message-ID: <20191107151725.10507-11-ville.syrjala@linux.intel.com> (raw)
Message-ID: <20191107151723.j4ICPeM1Y9Gzgk21GLZ__ZdmKbxMLUMVqe1WxYlq1xI@z> (raw)
In-Reply-To: <20191107151725.10507-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Extract all the 'hw value -> LUT entry' stuff into small helpers
to make the main 'read out the entire LUT' loop less bogged down
by such mundane details.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 128 ++++++++++-----------
1 file changed, 64 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index d6a20d7522a9..4b2bd5ac0e8d 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -367,6 +367,19 @@ static void chv_load_cgm_csc(struct intel_crtc *crtc,
I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
}
+/* convert hw value with given bit_precision to lut property val */
+static u32 intel_color_lut_pack(u32 val, int bit_precision)
+{
+ u32 max = 0xffff >> (16 - bit_precision);
+
+ val = clamp_val(val, 0, max);
+
+ if (bit_precision < 16)
+ val <<= 16 - bit_precision;
+
+ return val;
+}
+
static u32 i9xx_lut_8(const struct drm_color_lut *color)
{
return drm_color_lut_extract(color->red, 8) << 16 |
@@ -374,6 +387,13 @@ static u32 i9xx_lut_8(const struct drm_color_lut *color)
drm_color_lut_extract(color->blue, 8);
}
+static void i9xx_lut_8_pack(struct drm_color_lut *entry, u32 val)
+{
+ entry->red = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_RED_MASK, val), 8);
+ entry->green = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_GREEN_MASK, val), 8);
+ entry->blue = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_BLUE_MASK, val), 8);
+}
+
/* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */
static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color)
{
@@ -390,6 +410,21 @@ static u32 i965_lut_10p6_udw(const struct drm_color_lut *color)
(color->blue >> 8);
}
+static void i965_lut_10p6_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
+{
+ entry->red = REG_FIELD_GET(PALETTE_RED_MASK, udw) << 8 |
+ REG_FIELD_GET(PALETTE_RED_MASK, ldw);
+ entry->green = REG_FIELD_GET(PALETTE_GREEN_MASK, udw) << 8 |
+ REG_FIELD_GET(PALETTE_GREEN_MASK, ldw);
+ entry->blue = REG_FIELD_GET(PALETTE_BLUE_MASK, udw) << 8 |
+ REG_FIELD_GET(PALETTE_BLUE_MASK, ldw);
+}
+
+static u16 i965_lut_11p6_max_pack(u32 val)
+{
+ return REG_FIELD_GET(PIPEGCMAX_RGB_MASK, val);
+}
+
static u32 ilk_lut_10(const struct drm_color_lut *color)
{
return drm_color_lut_extract(color->red, 10) << 20 |
@@ -397,6 +432,13 @@ static u32 ilk_lut_10(const struct drm_color_lut *color)
drm_color_lut_extract(color->blue, 10);
}
+static void ilk_lut_10_pack(struct drm_color_lut *entry, u32 val)
+{
+ entry->red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_RED_MASK, val), 10);
+ entry->green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_GREEN_MASK, val), 10);
+ entry->blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10);
+}
+
static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -953,6 +995,13 @@ static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color)
return drm_color_lut_extract(color->red, 14);
}
+static void chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
+{
+ entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_MASK, ldw), 10);
+ entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_MASK, ldw), 10);
+ entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK, udw), 10);
+}
+
static void chv_load_cgm_degamma(struct intel_crtc *crtc,
const struct drm_property_blob *blob)
{
@@ -1640,19 +1689,6 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
return true;
}
-/* convert hw value with given bit_precision to lut property val */
-static u32 intel_color_lut_pack(u32 val, int bit_precision)
-{
- u32 max = 0xffff >> (16 - bit_precision);
-
- val = clamp_val(val, 0, max);
-
- if (bit_precision < 16)
- val <<= 16 - bit_precision;
-
- return val;
-}
-
static struct drm_property_blob *
i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
{
@@ -1674,12 +1710,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
u32 val = I915_READ(PALETTE(pipe, i));
- lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
- LGC_PALETTE_RED_MASK, val), 8);
- lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
- LGC_PALETTE_GREEN_MASK, val), 8);
- lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
- LGC_PALETTE_BLUE_MASK, val), 8);
+ i9xx_lut_8_pack(&lut[i], val);
}
return blob;
@@ -1712,23 +1743,15 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
lut = blob->data;
for (i = 0; i < lut_size - 1; i++) {
- u32 val1 = I915_READ(PALETTE(pipe, 2 * i + 0));
- u32 val2 = I915_READ(PALETTE(pipe, 2 * i + 1));
-
- lut[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
- REG_FIELD_GET(PALETTE_RED_MASK, val1);
- lut[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 |
- REG_FIELD_GET(PALETTE_GREEN_MASK, val1);
- lut[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 |
- REG_FIELD_GET(PALETTE_BLUE_MASK, val1);
+ u32 ldw = I915_READ(PALETTE(pipe, 2 * i + 0));
+ u32 udw = I915_READ(PALETTE(pipe, 2 * i + 1));
+
+ i965_lut_10p6_pack(&lut[i], ldw, udw);
}
- lut[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
- I915_READ(PIPEGCMAX(pipe, 0)));
- lut[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
- I915_READ(PIPEGCMAX(pipe, 1)));
- lut[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
- I915_READ(PIPEGCMAX(pipe, 2)));
+ lut[i].red = i965_lut_11p6_max_pack(I915_READ(PIPEGCMAX(pipe, 0)));
+ lut[i].green = i965_lut_11p6_max_pack(I915_READ(PIPEGCMAX(pipe, 1)));
+ lut[i].blue = i965_lut_11p6_max_pack(I915_READ(PIPEGCMAX(pipe, 2)));
return blob;
}
@@ -1763,17 +1786,10 @@ chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
lut = blob->data;
for (i = 0; i < lut_size; i++) {
- u32 val;
-
- val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 0));
- lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
- CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
- lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
- CGM_PIPE_GAMMA_BLUE_MASK, val), 10);
+ u32 ldw = I915_READ(CGM_PIPE_GAMMA(pipe, i, 0));
+ u32 udw = I915_READ(CGM_PIPE_GAMMA(pipe, i, 1));
- val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 1));
- lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
- CGM_PIPE_GAMMA_RED_MASK, val), 10);
+ chv_cgm_gamma_pack(&lut[i], ldw, udw);
}
return blob;
@@ -1808,12 +1824,7 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
u32 val = I915_READ(LGC_PALETTE(pipe, i));
- lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
- LGC_PALETTE_RED_MASK, val), 8);
- lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
- LGC_PALETTE_GREEN_MASK, val), 8);
- lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
- LGC_PALETTE_BLUE_MASK, val), 8);
+ i9xx_lut_8_pack(&lut[i], val);
}
return blob;
@@ -1840,12 +1851,7 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
for (i = 0; i < lut_size; i++) {
u32 val = I915_READ(PREC_PALETTE(pipe, i));
- lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
- PREC_PALETTE_RED_MASK, val), 10);
- lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
- PREC_PALETTE_GREEN_MASK, val), 10);
- lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
- PREC_PALETTE_BLUE_MASK, val), 10);
+ ilk_lut_10_pack(&lut[i], val);
}
return blob;
@@ -1883,18 +1889,12 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
lut = blob->data;
- I915_WRITE(PREC_PAL_INDEX(pipe), prec_index |
- PAL_PREC_AUTO_INCREMENT);
+ I915_WRITE(PREC_PAL_INDEX(pipe), prec_index | PAL_PREC_AUTO_INCREMENT);
for (i = 0; i < hw_lut_size; i++) {
u32 val = I915_READ(PREC_PAL_DATA(pipe));
- lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
- PREC_PAL_DATA_RED_MASK, val), 10);
- lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
- PREC_PAL_DATA_GREEN_MASK, val), 10);
- lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
- PREC_PAL_DATA_BLUE_MASK, val), 10);
+ ilk_lut_10_pack(&lut[i], val);
}
I915_WRITE(PREC_PAL_INDEX(pipe), 0);
--
2.23.0
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next prev parent reply other threads:[~2019-11-07 15:17 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-07 15:17 [PATCH 00/12] drm/i915: Gamma cleanups Ville Syrjala
2019-11-07 15:17 ` [Intel-gfx] " Ville Syrjala
2019-11-07 15:17 ` Ville Syrjala
2019-11-07 15:17 ` [PATCH 01/12] drm: Inline drm_color_lut_extract() Ville Syrjala
2019-11-07 15:17 ` [Intel-gfx] " Ville Syrjala
2019-11-07 15:17 ` Ville Syrjala
2019-11-07 15:31 ` Kazlauskas, Nicholas
2019-11-07 15:31 ` [Intel-gfx] " Kazlauskas, Nicholas
2019-11-07 15:43 ` Ville Syrjälä
2019-11-07 15:43 ` [Intel-gfx] " Ville Syrjälä
2019-11-07 15:47 ` Kazlauskas, Nicholas
2019-11-07 15:47 ` [Intel-gfx] " Kazlauskas, Nicholas
2019-11-07 17:40 ` Daniel Vetter
2019-11-07 17:40 ` Daniel Vetter
2019-11-08 13:36 ` Ville Syrjälä
2019-11-08 13:36 ` [Intel-gfx] " Ville Syrjälä
2019-11-08 13:36 ` Ville Syrjälä
2019-11-08 16:41 ` Daniel Vetter
2019-11-08 16:41 ` [Intel-gfx] " Daniel Vetter
2019-11-08 16:41 ` Daniel Vetter
2019-11-08 13:56 ` [PATCH v2 " Ville Syrjala
2019-11-08 13:56 ` [Intel-gfx] " Ville Syrjala
2019-11-07 15:17 ` [PATCH 02/12] drm/i915: Polish CHV .load_luts() a bit Ville Syrjala
2019-11-07 15:17 ` [Intel-gfx] " Ville Syrjala
2019-11-07 15:17 ` Ville Syrjala
2020-03-03 14:18 ` Sharma, Swati2
2020-03-03 14:18 ` [Intel-gfx] " Sharma, Swati2
2019-11-07 15:17 ` [PATCH 03/12] drm/i915: Polish CHV CGM CSC loading Ville Syrjala
2019-11-07 15:17 ` [Intel-gfx] " Ville Syrjala
2019-11-07 15:17 ` Ville Syrjala
2019-11-07 15:17 ` [PATCH 04/12] drm/i915: Add i9xx_lut_8() Ville Syrjala
2019-11-07 15:17 ` [Intel-gfx] " Ville Syrjala
2020-02-20 11:20 ` Emil Velikov
2020-02-20 11:20 ` Emil Velikov
2020-02-20 13:56 ` Ville Syrjälä
2020-02-20 13:56 ` Ville Syrjälä
2019-11-07 15:17 ` [PATCH 05/12] drm/i915: Clean up i9xx_load_luts_internal() Ville Syrjala
2019-11-07 15:17 ` [Intel-gfx] " Ville Syrjala
2019-11-07 15:17 ` Ville Syrjala
2019-11-07 15:17 ` [PATCH 06/12] drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants Ville Syrjala
2019-11-07 15:17 ` [Intel-gfx] " Ville Syrjala
2019-11-07 15:17 ` Ville Syrjala
2019-11-07 15:17 ` [PATCH 07/12] drm/i915: s/blob_data/lut/ Ville Syrjala
2019-11-07 15:17 ` [Intel-gfx] " Ville Syrjala
2019-11-07 15:17 ` Ville Syrjala
2019-11-07 15:17 ` [PATCH 08/12] drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/ Ville Syrjala
2019-11-07 15:17 ` [Intel-gfx] " Ville Syrjala
2019-11-07 15:17 ` Ville Syrjala
2019-11-07 15:17 ` [PATCH 09/12] drm/i915: Clean up integer types in color code Ville Syrjala
2019-11-07 15:17 ` [Intel-gfx] " Ville Syrjala
2019-11-07 15:17 ` Ville Syrjala
2019-11-07 15:17 ` Ville Syrjala [this message]
2019-11-07 15:17 ` [Intel-gfx] [PATCH 10/12] drm/i915: Refactor LUT read functions Ville Syrjala
2019-11-07 15:17 ` [PATCH 11/12] drm/i915: Fix readout of PIPEGCMAX Ville Syrjala
2019-11-07 15:17 ` [Intel-gfx] " Ville Syrjala
2019-11-07 15:17 ` [PATCH 12/12] drm/i915: Pass the crtc to the low level read_lut() funcs Ville Syrjala
2019-11-07 15:17 ` [Intel-gfx] " Ville Syrjala
2019-11-07 15:17 ` Ville Syrjala
2019-11-07 19:17 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Gamma cleanups Patchwork
2019-11-07 19:17 ` [Intel-gfx] " Patchwork
2019-11-07 19:22 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-11-07 19:22 ` [Intel-gfx] " Patchwork
2019-11-07 19:39 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-11-07 19:39 ` [Intel-gfx] " Patchwork
2019-11-08 17:48 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Gamma cleanups (rev2) Patchwork
2019-11-08 17:48 ` [Intel-gfx] " Patchwork
2019-11-08 17:53 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-11-08 17:53 ` [Intel-gfx] " Patchwork
2019-11-08 18:09 ` ✓ Fi.CI.BAT: success " Patchwork
2019-11-08 18:09 ` [Intel-gfx] " Patchwork
2019-11-10 12:13 ` ✓ Fi.CI.IGT: " Patchwork
2019-11-10 12:13 ` [Intel-gfx] " Patchwork
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