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* [PATCH 0/1] Wa_1604555607 implementation and verification skip
@ 2019-11-21 10:12 ` Ramalingam C
  0 siblings, 0 replies; 21+ messages in thread
From: Ramalingam C @ 2019-11-21 10:12 UTC (permalink / raw)
  To: intel-gfx, Tvrtko Ursulin, Chris Wilson

Implements the Wa_1604555607 and skips its verification as the FF_MODE2
register is write only till TGL B0.

Michel Thierry (1):
  drm/i915/tgl: Implement Wa_1604555607

 drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 ++++++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h             |  4 ++++
 2 files changed, 26 insertions(+), 3 deletions(-)

-- 
2.20.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 0/1] Wa_1604555607 implementation and verification skip
@ 2019-11-21 10:12 ` Ramalingam C
  0 siblings, 0 replies; 21+ messages in thread
From: Ramalingam C @ 2019-11-21 10:12 UTC (permalink / raw)
  To: intel-gfx, Tvrtko Ursulin, Chris Wilson

Implements the Wa_1604555607 and skips its verification as the FF_MODE2
register is write only till TGL B0.

Michel Thierry (1):
  drm/i915/tgl: Implement Wa_1604555607

 drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 ++++++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h             |  4 ++++
 2 files changed, 26 insertions(+), 3 deletions(-)

-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 21+ messages in thread
* [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-21 10:12   ` Ramalingam C
  0 siblings, 0 replies; 21+ messages in thread
From: Ramalingam C @ 2019-11-21 10:12 UTC (permalink / raw)
  To: intel-gfx, Tvrtko Ursulin, Chris Wilson; +Cc: Michel Thierry

From: Michel Thierry <michel.thierry@intel.com>

Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
FF_MODE2 is part of the register state context, that's why it is
implemented here.

At TGL A0 stepping, FF_MODE2 register read back is broken, hence
disabling the WA verification.

v2: Rebased on top of the WA refactoring (Oscar)
v3: Correctly add to ctx_workarounds_init (Michel)
v4:
  uncore read is used [Tvrtko]
  Macros as used for MASK definition [Chris]
v5:
  Skip the Wa_1604555607 verification [Ram]
  i915 ptr retrieved from engine. [Tvrtko]

BSpec: 19363
HSDES: 1604555607
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 ++++++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h             |  4 ++++
 2 files changed, 26 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 399acae2f33f..7cfd2442b736 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -147,19 +147,26 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
 }
 
 static void
-wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
-		   u32 val)
+__wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+		     u32 val, u32 read_mask)
 {
 	struct i915_wa wa = {
 		.reg  = reg,
 		.mask = mask,
 		.val  = val,
-		.read = mask,
+		.read = read_mask,
 	};
 
 	_wa_add(wal, &wa);
 }
 
+static void
+wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+		   u32 val)
+{
+	__wa_write_masked_or(wal, reg, mask, val, mask);
+}
+
 static void
 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
 {
@@ -568,9 +575,21 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 				     struct i915_wa_list *wal)
 {
+	u32 val;
+
 	/* Wa_1409142259:tgl */
 	WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 			  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
+
+	/* Wa_1604555607:tgl */
+	val = intel_uncore_read(engine->uncore, FF_MODE2);
+	val &= ~FF_MODE2_TDS_TIMER_MASK;
+	val |= FF_MODE2_TDS_TIMER_128;
+	if (IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0))
+		__wa_write_masked_or(wal, FF_MODE2,
+				     FF_MODE2_TDS_TIMER_MASK, val, 0);
+	else
+		wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 94d0f593eeb7..a99fdf8ea53b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7922,6 +7922,10 @@ enum {
 #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU 	(1 << 15)
 #define   PER_PIXEL_ALPHA_BYPASS_EN		(1 << 7)
 
+#define FF_MODE2			_MMIO(0x6604)
+#define   FF_MODE2_TDS_TIMER_MASK	REG_GENMASK(23, 16)
+#define   FF_MODE2_TDS_TIMER_128	REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
+
 /* PCH */
 
 #define PCH_DISPLAY_BASE	0xc0000u
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-21 10:12   ` Ramalingam C
  0 siblings, 0 replies; 21+ messages in thread
From: Ramalingam C @ 2019-11-21 10:12 UTC (permalink / raw)
  To: intel-gfx, Tvrtko Ursulin, Chris Wilson; +Cc: Michel Thierry

From: Michel Thierry <michel.thierry@intel.com>

Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
FF_MODE2 is part of the register state context, that's why it is
implemented here.

At TGL A0 stepping, FF_MODE2 register read back is broken, hence
disabling the WA verification.

v2: Rebased on top of the WA refactoring (Oscar)
v3: Correctly add to ctx_workarounds_init (Michel)
v4:
  uncore read is used [Tvrtko]
  Macros as used for MASK definition [Chris]
v5:
  Skip the Wa_1604555607 verification [Ram]
  i915 ptr retrieved from engine. [Tvrtko]

BSpec: 19363
HSDES: 1604555607
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 ++++++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h             |  4 ++++
 2 files changed, 26 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 399acae2f33f..7cfd2442b736 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -147,19 +147,26 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
 }
 
 static void
-wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
-		   u32 val)
+__wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+		     u32 val, u32 read_mask)
 {
 	struct i915_wa wa = {
 		.reg  = reg,
 		.mask = mask,
 		.val  = val,
-		.read = mask,
+		.read = read_mask,
 	};
 
 	_wa_add(wal, &wa);
 }
 
+static void
+wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+		   u32 val)
+{
+	__wa_write_masked_or(wal, reg, mask, val, mask);
+}
+
 static void
 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
 {
@@ -568,9 +575,21 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 				     struct i915_wa_list *wal)
 {
+	u32 val;
+
 	/* Wa_1409142259:tgl */
 	WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 			  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
+
+	/* Wa_1604555607:tgl */
+	val = intel_uncore_read(engine->uncore, FF_MODE2);
+	val &= ~FF_MODE2_TDS_TIMER_MASK;
+	val |= FF_MODE2_TDS_TIMER_128;
+	if (IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0))
+		__wa_write_masked_or(wal, FF_MODE2,
+				     FF_MODE2_TDS_TIMER_MASK, val, 0);
+	else
+		wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 94d0f593eeb7..a99fdf8ea53b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7922,6 +7922,10 @@ enum {
 #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU 	(1 << 15)
 #define   PER_PIXEL_ALPHA_BYPASS_EN		(1 << 7)
 
+#define FF_MODE2			_MMIO(0x6604)
+#define   FF_MODE2_TDS_TIMER_MASK	REG_GENMASK(23, 16)
+#define   FF_MODE2_TDS_TIMER_128	REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
+
 /* PCH */
 
 #define PCH_DISPLAY_BASE	0xc0000u
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 21+ messages in thread
* Re: [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-21 10:19     ` Chris Wilson
  0 siblings, 0 replies; 21+ messages in thread
From: Chris Wilson @ 2019-11-21 10:19 UTC (permalink / raw)
  To: Ramalingam C, Tvrtko Ursulin, intel-gfx; +Cc: Michel Thierry

Quoting Ramalingam C (2019-11-21 10:12:26)
> From: Michel Thierry <michel.thierry@intel.com>
> 
> Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
> FF_MODE2 is part of the register state context, that's why it is
> implemented here.
> 
> At TGL A0 stepping, FF_MODE2 register read back is broken, hence
> disabling the WA verification.
> 
> v2: Rebased on top of the WA refactoring (Oscar)
> v3: Correctly add to ctx_workarounds_init (Michel)
> v4:
>   uncore read is used [Tvrtko]
>   Macros as used for MASK definition [Chris]
> v5:
>   Skip the Wa_1604555607 verification [Ram]
>   i915 ptr retrieved from engine. [Tvrtko]
> 
> BSpec: 19363
> HSDES: 1604555607
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 ++++++++++++++++++---
>  drivers/gpu/drm/i915/i915_reg.h             |  4 ++++
>  2 files changed, 26 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 399acae2f33f..7cfd2442b736 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -147,19 +147,26 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
>  }
>  
>  static void
> -wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> -                  u32 val)
> +__wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> +                    u32 val, u32 read_mask)
>  {
>         struct i915_wa wa = {
>                 .reg  = reg,
>                 .mask = mask,
>                 .val  = val,
> -               .read = mask,
> +               .read = read_mask,
>         };
>  
>         _wa_add(wal, &wa);

You might as well call it wa_add() since it takes all the arguments to
_wa_add() and wraps them up into struct that we then copy.

>  }
>  
> +static void
> +wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> +                  u32 val)
> +{
> +       __wa_write_masked_or(wal, reg, mask, val, mask);
> +}
> +
>  static void
>  wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
>  {
> @@ -568,9 +575,21 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>  static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
>                                      struct i915_wa_list *wal)
>  {
> +       u32 val;
> +
>         /* Wa_1409142259:tgl */
>         WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
>                           GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> +
> +       /* Wa_1604555607:tgl */
> +       val = intel_uncore_read(engine->uncore, FF_MODE2);
> +       val &= ~FF_MODE2_TDS_TIMER_MASK;
> +       val |= FF_MODE2_TDS_TIMER_128;
> +       if (IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0))
> +               __wa_write_masked_or(wal, FF_MODE2,
> +                                    FF_MODE2_TDS_TIMER_MASK, val, 0);
> +       else
> +               wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);

I still have this plan to do this as MI_MATH ops... But it's not a
blocker.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-21 10:19     ` Chris Wilson
  0 siblings, 0 replies; 21+ messages in thread
From: Chris Wilson @ 2019-11-21 10:19 UTC (permalink / raw)
  To: Ramalingam C, Tvrtko Ursulin, intel-gfx; +Cc: Michel Thierry

Quoting Ramalingam C (2019-11-21 10:12:26)
> From: Michel Thierry <michel.thierry@intel.com>
> 
> Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
> FF_MODE2 is part of the register state context, that's why it is
> implemented here.
> 
> At TGL A0 stepping, FF_MODE2 register read back is broken, hence
> disabling the WA verification.
> 
> v2: Rebased on top of the WA refactoring (Oscar)
> v3: Correctly add to ctx_workarounds_init (Michel)
> v4:
>   uncore read is used [Tvrtko]
>   Macros as used for MASK definition [Chris]
> v5:
>   Skip the Wa_1604555607 verification [Ram]
>   i915 ptr retrieved from engine. [Tvrtko]
> 
> BSpec: 19363
> HSDES: 1604555607
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 ++++++++++++++++++---
>  drivers/gpu/drm/i915/i915_reg.h             |  4 ++++
>  2 files changed, 26 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 399acae2f33f..7cfd2442b736 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -147,19 +147,26 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
>  }
>  
>  static void
> -wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> -                  u32 val)
> +__wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> +                    u32 val, u32 read_mask)
>  {
>         struct i915_wa wa = {
>                 .reg  = reg,
>                 .mask = mask,
>                 .val  = val,
> -               .read = mask,
> +               .read = read_mask,
>         };
>  
>         _wa_add(wal, &wa);

You might as well call it wa_add() since it takes all the arguments to
_wa_add() and wraps them up into struct that we then copy.

>  }
>  
> +static void
> +wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> +                  u32 val)
> +{
> +       __wa_write_masked_or(wal, reg, mask, val, mask);
> +}
> +
>  static void
>  wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
>  {
> @@ -568,9 +575,21 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>  static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
>                                      struct i915_wa_list *wal)
>  {
> +       u32 val;
> +
>         /* Wa_1409142259:tgl */
>         WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
>                           GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> +
> +       /* Wa_1604555607:tgl */
> +       val = intel_uncore_read(engine->uncore, FF_MODE2);
> +       val &= ~FF_MODE2_TDS_TIMER_MASK;
> +       val |= FF_MODE2_TDS_TIMER_128;
> +       if (IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0))
> +               __wa_write_masked_or(wal, FF_MODE2,
> +                                    FF_MODE2_TDS_TIMER_MASK, val, 0);
> +       else
> +               wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);

I still have this plan to do this as MI_MATH ops... But it's not a
blocker.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 21+ messages in thread
* Re: [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-21 10:19     ` Tvrtko Ursulin
  0 siblings, 0 replies; 21+ messages in thread
From: Tvrtko Ursulin @ 2019-11-21 10:19 UTC (permalink / raw)
  To: Ramalingam C, intel-gfx, Chris Wilson; +Cc: Michel Thierry


On 21/11/2019 10:12, Ramalingam C wrote:
> From: Michel Thierry <michel.thierry@intel.com>
> 
> Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
> FF_MODE2 is part of the register state context, that's why it is
> implemented here.
> 
> At TGL A0 stepping, FF_MODE2 register read back is broken, hence
> disabling the WA verification.
> 
> v2: Rebased on top of the WA refactoring (Oscar)
> v3: Correctly add to ctx_workarounds_init (Michel)
> v4:
>    uncore read is used [Tvrtko]
>    Macros as used for MASK definition [Chris]
> v5:
>    Skip the Wa_1604555607 verification [Ram]
>    i915 ptr retrieved from engine. [Tvrtko]
> 
> BSpec: 19363
> HSDES: 1604555607
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 ++++++++++++++++++---
>   drivers/gpu/drm/i915/i915_reg.h             |  4 ++++
>   2 files changed, 26 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 399acae2f33f..7cfd2442b736 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -147,19 +147,26 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
>   }
>   
>   static void
> -wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> -		   u32 val)
> +__wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> +		     u32 val, u32 read_mask)
>   {
>   	struct i915_wa wa = {
>   		.reg  = reg,
>   		.mask = mask,
>   		.val  = val,
> -		.read = mask,
> +		.read = read_mask,
>   	};
>   
>   	_wa_add(wal, &wa);
>   }
>   
> +static void
> +wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> +		   u32 val)
> +{
> +	__wa_write_masked_or(wal, reg, mask, val, mask);
> +}
> +
>   static void
>   wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
>   {
> @@ -568,9 +575,21 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>   static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
>   				     struct i915_wa_list *wal)
>   {
> +	u32 val;
> +
>   	/* Wa_1409142259:tgl */
>   	WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
>   			  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> +
> +	/* Wa_1604555607:tgl */
> +	val = intel_uncore_read(engine->uncore, FF_MODE2);
> +	val &= ~FF_MODE2_TDS_TIMER_MASK;
> +	val |= FF_MODE2_TDS_TIMER_128;
> +	if (IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0))
> +		__wa_write_masked_or(wal, FF_MODE2,
> +				     FF_MODE2_TDS_TIMER_MASK, val, 0);
> +	else
> +		wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);

Hm a hybrid solution. I was thinking:

  __wa_write_masked_or(wal,
		       FF_MODE2,
		       FF_MODE2_TDS_TIMER_MASK,
		       val,
		       IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0) ?
		       0 : FF_MODE2_TDS_TIMER_MASK);

But yours works as well.

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko

>   }
>   
>   static void
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 94d0f593eeb7..a99fdf8ea53b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7922,6 +7922,10 @@ enum {
>   #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU 	(1 << 15)
>   #define   PER_PIXEL_ALPHA_BYPASS_EN		(1 << 7)
>   
> +#define FF_MODE2			_MMIO(0x6604)
> +#define   FF_MODE2_TDS_TIMER_MASK	REG_GENMASK(23, 16)
> +#define   FF_MODE2_TDS_TIMER_128	REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
> +
>   /* PCH */
>   
>   #define PCH_DISPLAY_BASE	0xc0000u
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-21 10:19     ` Tvrtko Ursulin
  0 siblings, 0 replies; 21+ messages in thread
From: Tvrtko Ursulin @ 2019-11-21 10:19 UTC (permalink / raw)
  To: Ramalingam C, intel-gfx, Chris Wilson; +Cc: Michel Thierry


On 21/11/2019 10:12, Ramalingam C wrote:
> From: Michel Thierry <michel.thierry@intel.com>
> 
> Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
> FF_MODE2 is part of the register state context, that's why it is
> implemented here.
> 
> At TGL A0 stepping, FF_MODE2 register read back is broken, hence
> disabling the WA verification.
> 
> v2: Rebased on top of the WA refactoring (Oscar)
> v3: Correctly add to ctx_workarounds_init (Michel)
> v4:
>    uncore read is used [Tvrtko]
>    Macros as used for MASK definition [Chris]
> v5:
>    Skip the Wa_1604555607 verification [Ram]
>    i915 ptr retrieved from engine. [Tvrtko]
> 
> BSpec: 19363
> HSDES: 1604555607
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 ++++++++++++++++++---
>   drivers/gpu/drm/i915/i915_reg.h             |  4 ++++
>   2 files changed, 26 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 399acae2f33f..7cfd2442b736 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -147,19 +147,26 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
>   }
>   
>   static void
> -wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> -		   u32 val)
> +__wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> +		     u32 val, u32 read_mask)
>   {
>   	struct i915_wa wa = {
>   		.reg  = reg,
>   		.mask = mask,
>   		.val  = val,
> -		.read = mask,
> +		.read = read_mask,
>   	};
>   
>   	_wa_add(wal, &wa);
>   }
>   
> +static void
> +wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> +		   u32 val)
> +{
> +	__wa_write_masked_or(wal, reg, mask, val, mask);
> +}
> +
>   static void
>   wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
>   {
> @@ -568,9 +575,21 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>   static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
>   				     struct i915_wa_list *wal)
>   {
> +	u32 val;
> +
>   	/* Wa_1409142259:tgl */
>   	WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
>   			  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> +
> +	/* Wa_1604555607:tgl */
> +	val = intel_uncore_read(engine->uncore, FF_MODE2);
> +	val &= ~FF_MODE2_TDS_TIMER_MASK;
> +	val |= FF_MODE2_TDS_TIMER_128;
> +	if (IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0))
> +		__wa_write_masked_or(wal, FF_MODE2,
> +				     FF_MODE2_TDS_TIMER_MASK, val, 0);
> +	else
> +		wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);

Hm a hybrid solution. I was thinking:

  __wa_write_masked_or(wal,
		       FF_MODE2,
		       FF_MODE2_TDS_TIMER_MASK,
		       val,
		       IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0) ?
		       0 : FF_MODE2_TDS_TIMER_MASK);

But yours works as well.

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko

>   }
>   
>   static void
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 94d0f593eeb7..a99fdf8ea53b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7922,6 +7922,10 @@ enum {
>   #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU 	(1 << 15)
>   #define   PER_PIXEL_ALPHA_BYPASS_EN		(1 << 7)
>   
> +#define FF_MODE2			_MMIO(0x6604)
> +#define   FF_MODE2_TDS_TIMER_MASK	REG_GENMASK(23, 16)
> +#define   FF_MODE2_TDS_TIMER_128	REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
> +
>   /* PCH */
>   
>   #define PCH_DISPLAY_BASE	0xc0000u
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 21+ messages in thread
* Re: [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-21 10:51       ` Ramalingam C
  0 siblings, 0 replies; 21+ messages in thread
From: Ramalingam C @ 2019-11-21 10:51 UTC (permalink / raw)
  To: Chris Wilson; +Cc: Michel Thierry, intel-gfx

On 2019-11-21 at 10:19:13 +0000, Chris Wilson wrote:
> Quoting Ramalingam C (2019-11-21 10:12:26)
> > From: Michel Thierry <michel.thierry@intel.com>
> > 
> > Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
> > FF_MODE2 is part of the register state context, that's why it is
> > implemented here.
> > 
> > At TGL A0 stepping, FF_MODE2 register read back is broken, hence
> > disabling the WA verification.
> > 
> > v2: Rebased on top of the WA refactoring (Oscar)
> > v3: Correctly add to ctx_workarounds_init (Michel)
> > v4:
> >   uncore read is used [Tvrtko]
> >   Macros as used for MASK definition [Chris]
> > v5:
> >   Skip the Wa_1604555607 verification [Ram]
> >   i915 ptr retrieved from engine. [Tvrtko]
> > 
> > BSpec: 19363
> > HSDES: 1604555607
> > Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> > Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 ++++++++++++++++++---
> >  drivers/gpu/drm/i915/i915_reg.h             |  4 ++++
> >  2 files changed, 26 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 399acae2f33f..7cfd2442b736 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -147,19 +147,26 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
> >  }
> >  
> >  static void
> > -wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> > -                  u32 val)
> > +__wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> > +                    u32 val, u32 read_mask)
> >  {
> >         struct i915_wa wa = {
> >                 .reg  = reg,
> >                 .mask = mask,
> >                 .val  = val,
> > -               .read = mask,
> > +               .read = read_mask,
> >         };
> >  
> >         _wa_add(wal, &wa);
> 
> You might as well call it wa_add() since it takes all the arguments to
> _wa_add() and wraps them up into struct that we then copy.
> 
Something like this?

static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
                   u32 val, u32 read_mask)
{
        struct i915_wa wa = {
                .reg  = reg,
                .mask = mask,
                .val  = val,
                .read = read_mask,
        };

        _wa_add(wal, &wa);
}

static void
__wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
                     u32 val, u32 read_mask)
{
        wa_add(wal, reg, mask, val, read_mask);
}


-Ram
> >  }
> >  
> > +static void
> > +wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> > +                  u32 val)
> > +{
> > +       __wa_write_masked_or(wal, reg, mask, val, mask);
> > +}
> > +
> >  static void
> >  wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
> >  {
> > @@ -568,9 +575,21 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> >  static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> >                                      struct i915_wa_list *wal)
> >  {
> > +       u32 val;
> > +
> >         /* Wa_1409142259:tgl */
> >         WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> >                           GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> > +
> > +       /* Wa_1604555607:tgl */
> > +       val = intel_uncore_read(engine->uncore, FF_MODE2);
> > +       val &= ~FF_MODE2_TDS_TIMER_MASK;
> > +       val |= FF_MODE2_TDS_TIMER_128;
> > +       if (IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0))
> > +               __wa_write_masked_or(wal, FF_MODE2,
> > +                                    FF_MODE2_TDS_TIMER_MASK, val, 0);
> > +       else
> > +               wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
> 
> I still have this plan to do this as MI_MATH ops... But it's not a
> blocker.
> -Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-21 10:51       ` Ramalingam C
  0 siblings, 0 replies; 21+ messages in thread
From: Ramalingam C @ 2019-11-21 10:51 UTC (permalink / raw)
  To: Chris Wilson; +Cc: Michel Thierry, intel-gfx

On 2019-11-21 at 10:19:13 +0000, Chris Wilson wrote:
> Quoting Ramalingam C (2019-11-21 10:12:26)
> > From: Michel Thierry <michel.thierry@intel.com>
> > 
> > Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
> > FF_MODE2 is part of the register state context, that's why it is
> > implemented here.
> > 
> > At TGL A0 stepping, FF_MODE2 register read back is broken, hence
> > disabling the WA verification.
> > 
> > v2: Rebased on top of the WA refactoring (Oscar)
> > v3: Correctly add to ctx_workarounds_init (Michel)
> > v4:
> >   uncore read is used [Tvrtko]
> >   Macros as used for MASK definition [Chris]
> > v5:
> >   Skip the Wa_1604555607 verification [Ram]
> >   i915 ptr retrieved from engine. [Tvrtko]
> > 
> > BSpec: 19363
> > HSDES: 1604555607
> > Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> > Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 ++++++++++++++++++---
> >  drivers/gpu/drm/i915/i915_reg.h             |  4 ++++
> >  2 files changed, 26 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 399acae2f33f..7cfd2442b736 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -147,19 +147,26 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
> >  }
> >  
> >  static void
> > -wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> > -                  u32 val)
> > +__wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> > +                    u32 val, u32 read_mask)
> >  {
> >         struct i915_wa wa = {
> >                 .reg  = reg,
> >                 .mask = mask,
> >                 .val  = val,
> > -               .read = mask,
> > +               .read = read_mask,
> >         };
> >  
> >         _wa_add(wal, &wa);
> 
> You might as well call it wa_add() since it takes all the arguments to
> _wa_add() and wraps them up into struct that we then copy.
> 
Something like this?

static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
                   u32 val, u32 read_mask)
{
        struct i915_wa wa = {
                .reg  = reg,
                .mask = mask,
                .val  = val,
                .read = read_mask,
        };

        _wa_add(wal, &wa);
}

static void
__wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
                     u32 val, u32 read_mask)
{
        wa_add(wal, reg, mask, val, read_mask);
}


-Ram
> >  }
> >  
> > +static void
> > +wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> > +                  u32 val)
> > +{
> > +       __wa_write_masked_or(wal, reg, mask, val, mask);
> > +}
> > +
> >  static void
> >  wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
> >  {
> > @@ -568,9 +575,21 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> >  static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> >                                      struct i915_wa_list *wal)
> >  {
> > +       u32 val;
> > +
> >         /* Wa_1409142259:tgl */
> >         WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> >                           GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> > +
> > +       /* Wa_1604555607:tgl */
> > +       val = intel_uncore_read(engine->uncore, FF_MODE2);
> > +       val &= ~FF_MODE2_TDS_TIMER_MASK;
> > +       val |= FF_MODE2_TDS_TIMER_128;
> > +       if (IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0))
> > +               __wa_write_masked_or(wal, FF_MODE2,
> > +                                    FF_MODE2_TDS_TIMER_MASK, val, 0);
> > +       else
> > +               wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
> 
> I still have this plan to do this as MI_MATH ops... But it's not a
> blocker.
> -Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 21+ messages in thread
* [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-21 11:12     ` Ramalingam C
  0 siblings, 0 replies; 21+ messages in thread
From: Ramalingam C @ 2019-11-21 11:12 UTC (permalink / raw)
  To: intel-gfx, Chris Wilson, Tvrtko Ursulin; +Cc: Michel Thierry, lucas.demarchi

From: Michel Thierry <michel.thierry@intel.com>

Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
FF_MODE2 is part of the register state context, that's why it is
implemented here.

At TGL A0 stepping, FF_MODE2 register read back is broken, hence
disabling the WA verification.

v2: Rebased on top of the WA refactoring (Oscar)
v3: Correctly add to ctx_workarounds_init (Michel)
v4:
  uncore read is used [Tvrtko]
  Macros as used for MASK definition [Chris]
v5:
  Skip the Wa_1604555607 verification [Ram]
  i915 ptr retrieved from engine. [Tvrtko]
v6:
  __wa_write_masked_or used with varying parameter [Tvrtko]
  Added wa_add as a wrapper for __wa_add [Chris]

BSpec: 19363
HSDES: 1604555607
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 31 ++++++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h             |  4 +++
 2 files changed, 31 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 399acae2f33f..efb43eb99e22 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -146,20 +146,33 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
 	}
 }
 
-static void
-wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
-		   u32 val)
+static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+		   u32 val, u32 read_mask)
 {
 	struct i915_wa wa = {
 		.reg  = reg,
 		.mask = mask,
 		.val  = val,
-		.read = mask,
+		.read = read_mask,
 	};
 
 	_wa_add(wal, &wa);
 }
 
+static void
+__wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+		     u32 val, u32 read_mask)
+{
+	wa_add(wal, reg, mask, val, read_mask);
+}
+
+static void
+wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+		   u32 val)
+{
+	__wa_write_masked_or(wal, reg, mask, val, mask);
+}
+
 static void
 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
 {
@@ -568,9 +581,19 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 				     struct i915_wa_list *wal)
 {
+	u32 val;
+
 	/* Wa_1409142259:tgl */
 	WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 			  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
+
+	/* Wa_1604555607:tgl */
+	val = intel_uncore_read(engine->uncore, FF_MODE2);
+	val &= ~FF_MODE2_TDS_TIMER_MASK;
+	val |= FF_MODE2_TDS_TIMER_128;
+	__wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
+			     IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0) ? 0:
+			     FF_MODE2_TDS_TIMER_MASK);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 94d0f593eeb7..a99fdf8ea53b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7922,6 +7922,10 @@ enum {
 #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU 	(1 << 15)
 #define   PER_PIXEL_ALPHA_BYPASS_EN		(1 << 7)
 
+#define FF_MODE2			_MMIO(0x6604)
+#define   FF_MODE2_TDS_TIMER_MASK	REG_GENMASK(23, 16)
+#define   FF_MODE2_TDS_TIMER_128	REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
+
 /* PCH */
 
 #define PCH_DISPLAY_BASE	0xc0000u
-- 
2.20.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-21 11:12     ` Ramalingam C
  0 siblings, 0 replies; 21+ messages in thread
From: Ramalingam C @ 2019-11-21 11:12 UTC (permalink / raw)
  To: intel-gfx, Chris Wilson, Tvrtko Ursulin; +Cc: Michel Thierry, lucas.demarchi

From: Michel Thierry <michel.thierry@intel.com>

Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
FF_MODE2 is part of the register state context, that's why it is
implemented here.

At TGL A0 stepping, FF_MODE2 register read back is broken, hence
disabling the WA verification.

v2: Rebased on top of the WA refactoring (Oscar)
v3: Correctly add to ctx_workarounds_init (Michel)
v4:
  uncore read is used [Tvrtko]
  Macros as used for MASK definition [Chris]
v5:
  Skip the Wa_1604555607 verification [Ram]
  i915 ptr retrieved from engine. [Tvrtko]
v6:
  __wa_write_masked_or used with varying parameter [Tvrtko]
  Added wa_add as a wrapper for __wa_add [Chris]

BSpec: 19363
HSDES: 1604555607
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 31 ++++++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h             |  4 +++
 2 files changed, 31 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 399acae2f33f..efb43eb99e22 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -146,20 +146,33 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
 	}
 }
 
-static void
-wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
-		   u32 val)
+static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+		   u32 val, u32 read_mask)
 {
 	struct i915_wa wa = {
 		.reg  = reg,
 		.mask = mask,
 		.val  = val,
-		.read = mask,
+		.read = read_mask,
 	};
 
 	_wa_add(wal, &wa);
 }
 
+static void
+__wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+		     u32 val, u32 read_mask)
+{
+	wa_add(wal, reg, mask, val, read_mask);
+}
+
+static void
+wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+		   u32 val)
+{
+	__wa_write_masked_or(wal, reg, mask, val, mask);
+}
+
 static void
 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
 {
@@ -568,9 +581,19 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 				     struct i915_wa_list *wal)
 {
+	u32 val;
+
 	/* Wa_1409142259:tgl */
 	WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 			  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
+
+	/* Wa_1604555607:tgl */
+	val = intel_uncore_read(engine->uncore, FF_MODE2);
+	val &= ~FF_MODE2_TDS_TIMER_MASK;
+	val |= FF_MODE2_TDS_TIMER_128;
+	__wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
+			     IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0) ? 0:
+			     FF_MODE2_TDS_TIMER_MASK);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 94d0f593eeb7..a99fdf8ea53b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7922,6 +7922,10 @@ enum {
 #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU 	(1 << 15)
 #define   PER_PIXEL_ALPHA_BYPASS_EN		(1 << 7)
 
+#define FF_MODE2			_MMIO(0x6604)
+#define   FF_MODE2_TDS_TIMER_MASK	REG_GENMASK(23, 16)
+#define   FF_MODE2_TDS_TIMER_128	REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
+
 /* PCH */
 
 #define PCH_DISPLAY_BASE	0xc0000u
-- 
2.20.1

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 21+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Wa_1604555607 implementation and verification skip (rev5)
@ 2019-11-21 14:32   ` Patchwork
  0 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2019-11-21 14:32 UTC (permalink / raw)
  To: Ramalingam C; +Cc: intel-gfx

== Series Details ==

Series: Wa_1604555607 implementation and verification skip (rev5)
URL   : https://patchwork.freedesktop.org/series/69763/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
efed46cc8be6 drm/i915/tgl: Implement Wa_1604555607
-:88: ERROR:SPACING: spaces required around that ':' (ctx:VxE)
#88: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:595:
+			     IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0) ? 0:
 			                                                    ^

total: 1 errors, 0 warnings, 0 checks, 66 lines checked

_______________________________________________
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^ permalink raw reply	[flat|nested] 21+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Wa_1604555607 implementation and verification skip (rev5)
@ 2019-11-21 14:32   ` Patchwork
  0 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2019-11-21 14:32 UTC (permalink / raw)
  To: Ramalingam C; +Cc: intel-gfx

== Series Details ==

Series: Wa_1604555607 implementation and verification skip (rev5)
URL   : https://patchwork.freedesktop.org/series/69763/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
efed46cc8be6 drm/i915/tgl: Implement Wa_1604555607
-:88: ERROR:SPACING: spaces required around that ':' (ctx:VxE)
#88: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:595:
+			     IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0) ? 0:
 			                                                    ^

total: 1 errors, 0 warnings, 0 checks, 66 lines checked

_______________________________________________
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^ permalink raw reply	[flat|nested] 21+ messages in thread
* ✓ Fi.CI.BAT: success for Wa_1604555607 implementation and verification skip (rev5)
@ 2019-11-21 15:03   ` Patchwork
  0 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2019-11-21 15:03 UTC (permalink / raw)
  To: Ramalingam C; +Cc: intel-gfx

== Series Details ==

Series: Wa_1604555607 implementation and verification skip (rev5)
URL   : https://patchwork.freedesktop.org/series/69763/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7400 -> Patchwork_15374
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15374/index.html

Known issues
------------

  Here are the changes found in Patchwork_15374 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6700k2:      [PASS][1] -> [INCOMPLETE][2] ([fdo#107807])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-skl-6700k2/igt@i915_pm_rpm@module-reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15374/fi-skl-6700k2/igt@i915_pm_rpm@module-reload.html

  * igt@kms_busy@basic-flip-pipe-a:
    - fi-icl-u2:          [PASS][3] -> [TIMEOUT][4] ([fdo#111800])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-icl-u2/igt@kms_busy@basic-flip-pipe-a.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15374/fi-icl-u2/igt@kms_busy@basic-flip-pipe-a.html

  
#### Possible fixes ####

  * igt@i915_module_load@reload-no-display:
    - fi-skl-lmem:        [DMESG-WARN][5] ([fdo#112261]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-skl-lmem/igt@i915_module_load@reload-no-display.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15374/fi-skl-lmem/igt@i915_module_load@reload-no-display.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][7] ([fdo#111045] / [fdo#111096]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15374/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111800]: https://bugs.freedesktop.org/show_bug.cgi?id=111800
  [fdo#112261]: https://bugs.freedesktop.org/show_bug.cgi?id=112261


Participating hosts (50 -> 44)
------------------------------

  Additional (1): fi-tgl-u 
  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7400 -> Patchwork_15374

  CI-20190529: 20190529
  CI_DRM_7400: 353c51b7f47ae247ea02b231dc173ba7cfdeb484 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5299: 65fed6a79adea14f7bef6d55530da47d7731d370 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15374: efed46cc8be6b82ed47fa62efed59708cb1f59a8 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

efed46cc8be6 drm/i915/tgl: Implement Wa_1604555607

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15374/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 21+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Wa_1604555607 implementation and verification skip (rev5)
@ 2019-11-21 15:03   ` Patchwork
  0 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2019-11-21 15:03 UTC (permalink / raw)
  To: Ramalingam C; +Cc: intel-gfx

== Series Details ==

Series: Wa_1604555607 implementation and verification skip (rev5)
URL   : https://patchwork.freedesktop.org/series/69763/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7400 -> Patchwork_15374
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15374/index.html

Known issues
------------

  Here are the changes found in Patchwork_15374 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6700k2:      [PASS][1] -> [INCOMPLETE][2] ([fdo#107807])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-skl-6700k2/igt@i915_pm_rpm@module-reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15374/fi-skl-6700k2/igt@i915_pm_rpm@module-reload.html

  * igt@kms_busy@basic-flip-pipe-a:
    - fi-icl-u2:          [PASS][3] -> [TIMEOUT][4] ([fdo#111800])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-icl-u2/igt@kms_busy@basic-flip-pipe-a.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15374/fi-icl-u2/igt@kms_busy@basic-flip-pipe-a.html

  
#### Possible fixes ####

  * igt@i915_module_load@reload-no-display:
    - fi-skl-lmem:        [DMESG-WARN][5] ([fdo#112261]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-skl-lmem/igt@i915_module_load@reload-no-display.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15374/fi-skl-lmem/igt@i915_module_load@reload-no-display.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][7] ([fdo#111045] / [fdo#111096]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15374/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111800]: https://bugs.freedesktop.org/show_bug.cgi?id=111800
  [fdo#112261]: https://bugs.freedesktop.org/show_bug.cgi?id=112261


Participating hosts (50 -> 44)
------------------------------

  Additional (1): fi-tgl-u 
  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7400 -> Patchwork_15374

  CI-20190529: 20190529
  CI_DRM_7400: 353c51b7f47ae247ea02b231dc173ba7cfdeb484 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5299: 65fed6a79adea14f7bef6d55530da47d7731d370 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15374: efed46cc8be6b82ed47fa62efed59708cb1f59a8 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

efed46cc8be6 drm/i915/tgl: Implement Wa_1604555607

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15374/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 21+ messages in thread
* Re: [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-21 18:29       ` Lucas De Marchi
  0 siblings, 0 replies; 21+ messages in thread
From: Lucas De Marchi @ 2019-11-21 18:29 UTC (permalink / raw)
  To: Ramalingam C; +Cc: Michel Thierry, intel-gfx

On Thu, Nov 21, 2019 at 04:42:31PM +0530, Ramalingam C wrote:
>+	/* Wa_1604555607:tgl */
>+	val = intel_uncore_read(engine->uncore, FF_MODE2);
>+	val &= ~FF_MODE2_TDS_TIMER_MASK;
>+	val |= FF_MODE2_TDS_TIMER_128;
>+	__wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
>+			     IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0) ? 0:

isn't it broken until B0 rather than only on A0? I think we could just
disable the read back for all revs and then selectively enable it
for later.

Lucas De Marchi
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^ permalink raw reply	[flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-21 18:29       ` Lucas De Marchi
  0 siblings, 0 replies; 21+ messages in thread
From: Lucas De Marchi @ 2019-11-21 18:29 UTC (permalink / raw)
  To: Ramalingam C; +Cc: Michel Thierry, intel-gfx

On Thu, Nov 21, 2019 at 04:42:31PM +0530, Ramalingam C wrote:
>+	/* Wa_1604555607:tgl */
>+	val = intel_uncore_read(engine->uncore, FF_MODE2);
>+	val &= ~FF_MODE2_TDS_TIMER_MASK;
>+	val |= FF_MODE2_TDS_TIMER_128;
>+	__wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
>+			     IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0) ? 0:

isn't it broken until B0 rather than only on A0? I think we could just
disable the read back for all revs and then selectively enable it
for later.

Lucas De Marchi
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 21+ messages in thread
* Re: [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-22  3:27         ` Ramalingam C
  0 siblings, 0 replies; 21+ messages in thread
From: Ramalingam C @ 2019-11-22  3:27 UTC (permalink / raw)
  To: Lucas De Marchi; +Cc: Michel Thierry, intel-gfx

On 2019-11-21 at 10:29:09 -0800, Lucas De Marchi wrote:
> On Thu, Nov 21, 2019 at 04:42:31PM +0530, Ramalingam C wrote:
> > +	/* Wa_1604555607:tgl */
> > +	val = intel_uncore_read(engine->uncore, FF_MODE2);
> > +	val &= ~FF_MODE2_TDS_TIMER_MASK;
> > +	val |= FF_MODE2_TDS_TIMER_128;
> > +	__wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
> > +			     IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0) ? 0:
> 
> isn't it broken until B0 rather than only on A0? I think we could just
> disable the read back for all revs and then selectively enable it
> for later.

Thought of excluding the verification when the new stepping comes in.
Hence excluded for existing stepping alone.

Even your suggestion sounds good to me. I will go with it. With a FIXME
Note to indicate that we need to enable for capable steppings.

-Ram
> 
> Lucas De Marchi
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^ permalink raw reply	[flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-22  3:27         ` Ramalingam C
  0 siblings, 0 replies; 21+ messages in thread
From: Ramalingam C @ 2019-11-22  3:27 UTC (permalink / raw)
  To: Lucas De Marchi; +Cc: Michel Thierry, intel-gfx

On 2019-11-21 at 10:29:09 -0800, Lucas De Marchi wrote:
> On Thu, Nov 21, 2019 at 04:42:31PM +0530, Ramalingam C wrote:
> > +	/* Wa_1604555607:tgl */
> > +	val = intel_uncore_read(engine->uncore, FF_MODE2);
> > +	val &= ~FF_MODE2_TDS_TIMER_MASK;
> > +	val |= FF_MODE2_TDS_TIMER_128;
> > +	__wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
> > +			     IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0) ? 0:
> 
> isn't it broken until B0 rather than only on A0? I think we could just
> disable the read back for all revs and then selectively enable it
> for later.

Thought of excluding the verification when the new stepping comes in.
Hence excluded for existing stepping alone.

Even your suggestion sounds good to me. I will go with it. With a FIXME
Note to indicate that we need to enable for capable steppings.

-Ram
> 
> Lucas De Marchi
_______________________________________________
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^ permalink raw reply	[flat|nested] 21+ messages in thread
* [PATCH 0/1] Wa_1604555607 implementation and verification skip
@ 2019-11-22  4:02 Ramalingam C
  0 siblings, 0 replies; 21+ messages in thread
From: Ramalingam C @ 2019-11-22  4:02 UTC (permalink / raw)
  To: intel-gfx, Tvrtko Ursulin, Chris Wilson

Implements the Wa_1604555607 and skips its verification as the FF_MODE2
register is write only till TGL B0.

Michel Thierry (1):
  drm/i915/tgl: Implement Wa_1604555607

 drivers/gpu/drm/i915/gt/intel_workarounds.c | 34 ++++++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h             |  4 +++
 2 files changed, 34 insertions(+), 4 deletions(-)

-- 
2.20.1

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^ permalink raw reply	[flat|nested] 21+ messages in thread
end of thread, other threads:[~2019-11-22  4:03 UTC | newest]

Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-21 10:12 [PATCH 0/1] Wa_1604555607 implementation and verification skip Ramalingam C
2019-11-21 10:12 ` [Intel-gfx] " Ramalingam C
2019-11-21 10:12 ` [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607 Ramalingam C
2019-11-21 10:12   ` [Intel-gfx] " Ramalingam C
2019-11-21 10:19   ` Chris Wilson
2019-11-21 10:19     ` [Intel-gfx] " Chris Wilson
2019-11-21 10:51     ` Ramalingam C
2019-11-21 10:51       ` [Intel-gfx] " Ramalingam C
2019-11-21 10:19   ` Tvrtko Ursulin
2019-11-21 10:19     ` [Intel-gfx] " Tvrtko Ursulin
2019-11-21 11:12   ` Ramalingam C
2019-11-21 11:12     ` [Intel-gfx] " Ramalingam C
2019-11-21 18:29     ` Lucas De Marchi
2019-11-21 18:29       ` [Intel-gfx] " Lucas De Marchi
2019-11-22  3:27       ` Ramalingam C
2019-11-22  3:27         ` [Intel-gfx] " Ramalingam C
2019-11-21 14:32 ` ✗ Fi.CI.CHECKPATCH: warning for Wa_1604555607 implementation and verification skip (rev5) Patchwork
2019-11-21 14:32   ` [Intel-gfx] " Patchwork
2019-11-21 15:03 ` ✓ Fi.CI.BAT: success " Patchwork
2019-11-21 15:03   ` [Intel-gfx] " Patchwork
2019-11-22  4:02 [PATCH 0/1] Wa_1604555607 implementation and verification skip Ramalingam C

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