From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> To: Ramalingam C <ramalingam.c@intel.com>, intel-gfx <intel-gfx@lists.freedesktop.org>, Chris Wilson <chris@chris-wilson.co.uk> Cc: Michel Thierry <michel.thierry@intel.com> Subject: Re: [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607 Date: Thu, 21 Nov 2019 10:19:17 +0000 [thread overview] Message-ID: <afc90e11-dfe5-108d-7901-c0104265853d@linux.intel.com> (raw) In-Reply-To: <20191121101226.10779-2-ramalingam.c@intel.com> On 21/11/2019 10:12, Ramalingam C wrote: > From: Michel Thierry <michel.thierry@intel.com> > > Implement Wa_1604555607 (set the DS pairing timer to 128 cycles). > FF_MODE2 is part of the register state context, that's why it is > implemented here. > > At TGL A0 stepping, FF_MODE2 register read back is broken, hence > disabling the WA verification. > > v2: Rebased on top of the WA refactoring (Oscar) > v3: Correctly add to ctx_workarounds_init (Michel) > v4: > uncore read is used [Tvrtko] > Macros as used for MASK definition [Chris] > v5: > Skip the Wa_1604555607 verification [Ram] > i915 ptr retrieved from engine. [Tvrtko] > > BSpec: 19363 > HSDES: 1604555607 > Signed-off-by: Michel Thierry <michel.thierry@intel.com> > Signed-off-by: Ramalingam C <ramlingam.c@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 ++++++++++++++++++--- > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > 2 files changed, 26 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 399acae2f33f..7cfd2442b736 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -147,19 +147,26 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) > } > > static void > -wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, > - u32 val) > +__wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, > + u32 val, u32 read_mask) > { > struct i915_wa wa = { > .reg = reg, > .mask = mask, > .val = val, > - .read = mask, > + .read = read_mask, > }; > > _wa_add(wal, &wa); > } > > +static void > +wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, > + u32 val) > +{ > + __wa_write_masked_or(wal, reg, mask, val, mask); > +} > + > static void > wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) > { > @@ -568,9 +575,21 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, > static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, > struct i915_wa_list *wal) > { > + u32 val; > + > /* Wa_1409142259:tgl */ > WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, > GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); > + > + /* Wa_1604555607:tgl */ > + val = intel_uncore_read(engine->uncore, FF_MODE2); > + val &= ~FF_MODE2_TDS_TIMER_MASK; > + val |= FF_MODE2_TDS_TIMER_128; > + if (IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0)) > + __wa_write_masked_or(wal, FF_MODE2, > + FF_MODE2_TDS_TIMER_MASK, val, 0); > + else > + wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val); Hm a hybrid solution. I was thinking: __wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0) ? 0 : FF_MODE2_TDS_TIMER_MASK); But yours works as well. Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Regards, Tvrtko > } > > static void > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 94d0f593eeb7..a99fdf8ea53b 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7922,6 +7922,10 @@ enum { > #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15) > #define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7) > > +#define FF_MODE2 _MMIO(0x6604) > +#define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16) > +#define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4) > + > /* PCH */ > > #define PCH_DISPLAY_BASE 0xc0000u > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> To: Ramalingam C <ramalingam.c@intel.com>, intel-gfx <intel-gfx@lists.freedesktop.org>, Chris Wilson <chris@chris-wilson.co.uk> Cc: Michel Thierry <michel.thierry@intel.com> Subject: Re: [Intel-gfx] [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607 Date: Thu, 21 Nov 2019 10:19:17 +0000 [thread overview] Message-ID: <afc90e11-dfe5-108d-7901-c0104265853d@linux.intel.com> (raw) Message-ID: <20191121101917.2VDZDVzQ8lkcv-f0GGbp5_8vbSYjDFsaeaInrs-R3Dc@z> (raw) In-Reply-To: <20191121101226.10779-2-ramalingam.c@intel.com> On 21/11/2019 10:12, Ramalingam C wrote: > From: Michel Thierry <michel.thierry@intel.com> > > Implement Wa_1604555607 (set the DS pairing timer to 128 cycles). > FF_MODE2 is part of the register state context, that's why it is > implemented here. > > At TGL A0 stepping, FF_MODE2 register read back is broken, hence > disabling the WA verification. > > v2: Rebased on top of the WA refactoring (Oscar) > v3: Correctly add to ctx_workarounds_init (Michel) > v4: > uncore read is used [Tvrtko] > Macros as used for MASK definition [Chris] > v5: > Skip the Wa_1604555607 verification [Ram] > i915 ptr retrieved from engine. [Tvrtko] > > BSpec: 19363 > HSDES: 1604555607 > Signed-off-by: Michel Thierry <michel.thierry@intel.com> > Signed-off-by: Ramalingam C <ramlingam.c@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 ++++++++++++++++++--- > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > 2 files changed, 26 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 399acae2f33f..7cfd2442b736 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -147,19 +147,26 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) > } > > static void > -wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, > - u32 val) > +__wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, > + u32 val, u32 read_mask) > { > struct i915_wa wa = { > .reg = reg, > .mask = mask, > .val = val, > - .read = mask, > + .read = read_mask, > }; > > _wa_add(wal, &wa); > } > > +static void > +wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, > + u32 val) > +{ > + __wa_write_masked_or(wal, reg, mask, val, mask); > +} > + > static void > wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) > { > @@ -568,9 +575,21 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, > static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, > struct i915_wa_list *wal) > { > + u32 val; > + > /* Wa_1409142259:tgl */ > WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, > GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); > + > + /* Wa_1604555607:tgl */ > + val = intel_uncore_read(engine->uncore, FF_MODE2); > + val &= ~FF_MODE2_TDS_TIMER_MASK; > + val |= FF_MODE2_TDS_TIMER_128; > + if (IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0)) > + __wa_write_masked_or(wal, FF_MODE2, > + FF_MODE2_TDS_TIMER_MASK, val, 0); > + else > + wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val); Hm a hybrid solution. I was thinking: __wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0) ? 0 : FF_MODE2_TDS_TIMER_MASK); But yours works as well. Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Regards, Tvrtko > } > > static void > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 94d0f593eeb7..a99fdf8ea53b 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7922,6 +7922,10 @@ enum { > #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15) > #define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7) > > +#define FF_MODE2 _MMIO(0x6604) > +#define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16) > +#define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4) > + > /* PCH */ > > #define PCH_DISPLAY_BASE 0xc0000u > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-11-21 10:19 UTC|newest] Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-21 10:12 [PATCH 0/1] Wa_1604555607 implementation and verification skip Ramalingam C 2019-11-21 10:12 ` [Intel-gfx] " Ramalingam C 2019-11-21 10:12 ` [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607 Ramalingam C 2019-11-21 10:12 ` [Intel-gfx] " Ramalingam C 2019-11-21 10:19 ` Chris Wilson 2019-11-21 10:19 ` [Intel-gfx] " Chris Wilson 2019-11-21 10:51 ` Ramalingam C 2019-11-21 10:51 ` [Intel-gfx] " Ramalingam C 2019-11-21 10:19 ` Tvrtko Ursulin [this message] 2019-11-21 10:19 ` Tvrtko Ursulin 2019-11-21 11:12 ` Ramalingam C 2019-11-21 11:12 ` [Intel-gfx] " Ramalingam C 2019-11-21 18:29 ` Lucas De Marchi 2019-11-21 18:29 ` [Intel-gfx] " Lucas De Marchi 2019-11-22 3:27 ` Ramalingam C 2019-11-22 3:27 ` [Intel-gfx] " Ramalingam C 2019-11-21 14:32 ` ✗ Fi.CI.CHECKPATCH: warning for Wa_1604555607 implementation and verification skip (rev5) Patchwork 2019-11-21 14:32 ` [Intel-gfx] " Patchwork 2019-11-21 15:03 ` ✓ Fi.CI.BAT: success " Patchwork 2019-11-21 15:03 ` [Intel-gfx] " Patchwork 2019-11-22 4:02 [PATCH 0/1] Wa_1604555607 implementation and verification skip Ramalingam C 2019-11-22 4:02 ` [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607 Ramalingam C 2019-11-22 9:21 ` Tvrtko Ursulin 2019-11-22 9:29 ` Chris Wilson 2019-11-26 8:00 ` Ramalingam C 2019-11-26 9:38 ` Lucas De Marchi 2019-11-26 10:10 ` Ramalingam C
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