[PATCH v3 00/17] In order to readout DP SDPs, refactors the handling of DP SDPs

[PATCH v3 00/17] In order to readout DP SDPs, refactors the handling of DP SDPs

[Gwan-gyeong Mun]

In order to readout DP SDPs (Secondary Data Packet: DP HDR Metadata
Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs codes.
It adds new compute routines for DP HDR Metadata Infoframe SDP
and DP VSC SDP. 
And new writing routines of DP SDPs (Secondary Data Packet) that uses
computed configs.
New reading routines of DP SDPs are added for readout.
It adds a logging function for DP VSC SDP.
When receiving video it is very useful to be able to log DP VSC SDP.
This greatly simplifies debugging.
In order to use a common VSC SDP Colorimetry calculating code on PSR,
it uses a new psr vsc sdp compute routine.

v2: Minor style fix
v3: 
  - Add a new drm data structure for DP VSC SDP
  - Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
  - Move logging functions to drm core [Jani N]
    And use drm core's DP VSC SDP logging function
  - Explicitly disable unused DIPs (AVI, GCP, VS, SPD, DRM. They will be
    used for HDMI), when intel_dp_set_infoframes() function will be called.

Gwan-gyeong Mun (17):
  drm: add DP 1.4 VSC SDP Payload related enums and a structure
  drm/i915/dp: Add compute routine for DP VSC SDP
  drm/i915/dp: Add compute routine for DP HDR Metadata Infoframe SDP
  drm/i915/dp: Add writing of DP SDPs (Secondary Data Packet)
  video/hdmi: Add Unpack only function for DRM infoframe
  drm/i915/dp: Read out DP SDPs (Secondary Data Packet)
  drm: Add logging function for DP VSC SDP
  drm/i915: Include HDMI DRM infoframe in the crtc state dump
  drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump
  drm/i915: Include DP VSC SDP in the crtc state dump
  drm/i915: Program DP SDPs with computed configs
  drm/i915: Add state readout for DP HDR Metadata Infoframe SDP
  drm/i915: Add state readout for DP VSC SDP
  drm/i915: Program DP SDPs on pipe updates
  drm/i915: Stop sending DP SDPs on intel_ddi_post_disable_dp()
  drm/i915/dp: Add compute routine for DP PSR VSC SDP
  drm/i915/psr: Use new DP VSC SDP compute routine on PSR

 drivers/gpu/drm/drm_dp_helper.c               | 174 +++++
 drivers/gpu/drm/i915/display/intel_ddi.c      |  19 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  61 ++
 .../drm/i915/display/intel_display_types.h    |   1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 607 +++++++++++++-----
 drivers/gpu/drm/i915/display/intel_dp.h       |  18 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |  54 +-
 drivers/gpu/drm/i915/display/intel_psr.h      |   6 +-
 drivers/gpu/drm/i915/i915_drv.h               |   1 +
 drivers/video/hdmi.c                          |  58 +-
 include/drm/drm_dp_helper.h                   |  60 ++
 include/linux/hdmi.h                          |   2 +
 12 files changed, 843 insertions(+), 218 deletions(-)

-- 
2.24.1

[PATCH v3 00/17] In order to readout DP SDPs, refactors the handling of DP SDPs

[Gwan-gyeong Mun]

In order to readout DP SDPs (Secondary Data Packet: DP HDR Metadata
Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs codes.
It adds new compute routines for DP HDR Metadata Infoframe SDP
and DP VSC SDP. 
And new writing routines of DP SDPs (Secondary Data Packet) that uses
computed configs.
New reading routines of DP SDPs are added for readout.
It adds a logging function for DP VSC SDP.
When receiving video it is very useful to be able to log DP VSC SDP.
This greatly simplifies debugging.
In order to use a common VSC SDP Colorimetry calculating code on PSR,
it uses a new psr vsc sdp compute routine.

v2: Minor style fix
v3: 
  - Add a new drm data structure for DP VSC SDP
  - Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
  - Move logging functions to drm core [Jani N]
    And use drm core's DP VSC SDP logging function
  - Explicitly disable unused DIPs (AVI, GCP, VS, SPD, DRM. They will be
    used for HDMI), when intel_dp_set_infoframes() function will be called.

Gwan-gyeong Mun (17):
  drm: add DP 1.4 VSC SDP Payload related enums and a structure
  drm/i915/dp: Add compute routine for DP VSC SDP
  drm/i915/dp: Add compute routine for DP HDR Metadata Infoframe SDP
  drm/i915/dp: Add writing of DP SDPs (Secondary Data Packet)
  video/hdmi: Add Unpack only function for DRM infoframe
  drm/i915/dp: Read out DP SDPs (Secondary Data Packet)
  drm: Add logging function for DP VSC SDP
  drm/i915: Include HDMI DRM infoframe in the crtc state dump
  drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump
  drm/i915: Include DP VSC SDP in the crtc state dump
  drm/i915: Program DP SDPs with computed configs
  drm/i915: Add state readout for DP HDR Metadata Infoframe SDP
  drm/i915: Add state readout for DP VSC SDP
  drm/i915: Program DP SDPs on pipe updates
  drm/i915: Stop sending DP SDPs on intel_ddi_post_disable_dp()
  drm/i915/dp: Add compute routine for DP PSR VSC SDP
  drm/i915/psr: Use new DP VSC SDP compute routine on PSR

 drivers/gpu/drm/drm_dp_helper.c               | 174 +++++
 drivers/gpu/drm/i915/display/intel_ddi.c      |  19 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  61 ++
 .../drm/i915/display/intel_display_types.h    |   1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 607 +++++++++++++-----
 drivers/gpu/drm/i915/display/intel_dp.h       |  18 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |  54 +-
 drivers/gpu/drm/i915/display/intel_psr.h      |   6 +-
 drivers/gpu/drm/i915/i915_drv.h               |   1 +
 drivers/video/hdmi.c                          |  58 +-
 include/drm/drm_dp_helper.h                   |  60 ++
 include/linux/hdmi.h                          |   2 +
 12 files changed, 843 insertions(+), 218 deletions(-)

-- 
2.24.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[Intel-gfx] [PATCH v3 00/17] In order to readout DP SDPs, refactors the handling of DP SDPs

[Gwan-gyeong Mun]

In order to readout DP SDPs (Secondary Data Packet: DP HDR Metadata
Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs codes.
It adds new compute routines for DP HDR Metadata Infoframe SDP
and DP VSC SDP. 
And new writing routines of DP SDPs (Secondary Data Packet) that uses
computed configs.
New reading routines of DP SDPs are added for readout.
It adds a logging function for DP VSC SDP.
When receiving video it is very useful to be able to log DP VSC SDP.
This greatly simplifies debugging.
In order to use a common VSC SDP Colorimetry calculating code on PSR,
it uses a new psr vsc sdp compute routine.

v2: Minor style fix
v3: 
  - Add a new drm data structure for DP VSC SDP
  - Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
  - Move logging functions to drm core [Jani N]
    And use drm core's DP VSC SDP logging function
  - Explicitly disable unused DIPs (AVI, GCP, VS, SPD, DRM. They will be
    used for HDMI), when intel_dp_set_infoframes() function will be called.

Gwan-gyeong Mun (17):
  drm: add DP 1.4 VSC SDP Payload related enums and a structure
  drm/i915/dp: Add compute routine for DP VSC SDP
  drm/i915/dp: Add compute routine for DP HDR Metadata Infoframe SDP
  drm/i915/dp: Add writing of DP SDPs (Secondary Data Packet)
  video/hdmi: Add Unpack only function for DRM infoframe
  drm/i915/dp: Read out DP SDPs (Secondary Data Packet)
  drm: Add logging function for DP VSC SDP
  drm/i915: Include HDMI DRM infoframe in the crtc state dump
  drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump
  drm/i915: Include DP VSC SDP in the crtc state dump
  drm/i915: Program DP SDPs with computed configs
  drm/i915: Add state readout for DP HDR Metadata Infoframe SDP
  drm/i915: Add state readout for DP VSC SDP
  drm/i915: Program DP SDPs on pipe updates
  drm/i915: Stop sending DP SDPs on intel_ddi_post_disable_dp()
  drm/i915/dp: Add compute routine for DP PSR VSC SDP
  drm/i915/psr: Use new DP VSC SDP compute routine on PSR

 drivers/gpu/drm/drm_dp_helper.c               | 174 +++++
 drivers/gpu/drm/i915/display/intel_ddi.c      |  19 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  61 ++
 .../drm/i915/display/intel_display_types.h    |   1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 607 +++++++++++++-----
 drivers/gpu/drm/i915/display/intel_dp.h       |  18 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |  54 +-
 drivers/gpu/drm/i915/display/intel_psr.h      |   6 +-
 drivers/gpu/drm/i915/i915_drv.h               |   1 +
 drivers/video/hdmi.c                          |  58 +-
 include/drm/drm_dp_helper.h                   |  60 ++
 include/linux/hdmi.h                          |   2 +
 12 files changed, 843 insertions(+), 218 deletions(-)

-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 01/17] drm: add DP 1.4 VSC SDP Payload related enums and a structure

[Gwan-gyeong Mun]

It adds new enumeration definitions for VSC SDP Payload for Pixel
Encoding/Colorimetry Format.
And it adds a new drm data structure for DP VSC SDP.

enum dp_colorspace and enum dp_colorimetry correspond "Pixel Encoding and
Colorimetry Formats". enum dp_dynamic_range corresponds "Dynamic Range".
And enum dp_content_type corresponds "Content Type"
All of them are based on DP 1.4 spec [Table 2-117: VSC SDP Payload for
DB16 through DB18].

v3: Add a new drm data structure for DP VSC SDP

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 include/drm/drm_dp_helper.h | 57 +++++++++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 262faf9e5e94..c098727681fa 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1209,6 +1209,63 @@ struct dp_sdp {
 #define EDP_VSC_PSR_UPDATE_RFB		(1<<1)
 #define EDP_VSC_PSR_CRC_VALUES_VALID	(1<<2)
 
+/* Based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through DB18] */
+enum dp_colorspace {
+	DP_COLORSPACE_RGB = 0,
+	DP_COLORSPACE_YUV444 = 0x1,
+	DP_COLORSPACE_YUV422 = 0x2,
+	DP_COLORSPACE_YUV420 = 0x3,
+	DP_COLORSPACE_Y_ONLY = 0x4,
+	DP_COLORSPACE_RAW = 0x5,
+	DP_COLORSPACE_RESERVED = 0x6,
+};
+
+/**
+ * Based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through DB18]
+ * and a name of enum member followes DRM_MODE_COLORIMETRY definition.
+ */
+enum dp_colorimetry {
+	DP_COLORIMETRY_DEFAULT = 0, /* sRGB (IEC 61966-2-1) / ITU-R BT.601 */
+	DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
+	DP_COLORIMETRY_BT709_YCC = 0x1,
+	DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
+	DP_COLORIMETRY_XVYCC_601 = 0x2,
+	DP_COLORIMETRY_OPRGB = 0x3,
+	DP_COLORIMETRY_XVYCC_709 = 0x3,
+	DP_COLORIMETRY_DCI_P3_RGB = 0x4,
+	DP_COLORIMETRY_SYCC_601 = 0x4,
+	DP_COLORIMETRY_RGB_CUSTOM = 0x5,
+	DP_COLORIMETRY_OPYCC_601 = 0x5,
+	DP_COLORIMETRY_BT2020_RGB = 0x6,
+	DP_COLORIMETRY_BT2020_CYCC = 0x6,
+	DP_COLORIMETRY_BT2020_YCC = 0x7,
+};
+
+enum dp_dynamic_range {
+	DP_DYNAMIC_RANGE_VESA = 0,
+	DP_DYNAMIC_RANGE_CTA = 1,
+};
+
+enum dp_content_type {
+	DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
+	DP_CONTENT_TYPE_GRAPHICS = 0x01,
+	DP_CONTENT_TYPE_PHOTO = 0x02,
+	DP_CONTENT_TYPE_VIDEO = 0x03,
+	DP_CONTENT_TYPE_GAME = 0x04,
+};
+
+/* DRM DP VSC SDP as per DP 1.4 spec */
+struct drm_dp_vsc_sdp {
+	unsigned char sdp_type; /* Secondary-data Packet Type */
+	unsigned char revision; /* Revision Number */
+	unsigned char length; /* Number of Valid Data Bytes */
+	enum dp_colorspace colorspace;
+	enum dp_colorimetry colorimetry;
+	int bpc; /* bit per color */
+	enum dp_dynamic_range dynamic_range;
+	enum dp_content_type content_type;
+};
+
 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
 
 static inline int
-- 
2.24.1

[PATCH v3 01/17] drm: add DP 1.4 VSC SDP Payload related enums and a structure

[Gwan-gyeong Mun]

It adds new enumeration definitions for VSC SDP Payload for Pixel
Encoding/Colorimetry Format.
And it adds a new drm data structure for DP VSC SDP.

enum dp_colorspace and enum dp_colorimetry correspond "Pixel Encoding and
Colorimetry Formats". enum dp_dynamic_range corresponds "Dynamic Range".
And enum dp_content_type corresponds "Content Type"
All of them are based on DP 1.4 spec [Table 2-117: VSC SDP Payload for
DB16 through DB18].

v3: Add a new drm data structure for DP VSC SDP

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 include/drm/drm_dp_helper.h | 57 +++++++++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 262faf9e5e94..c098727681fa 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1209,6 +1209,63 @@ struct dp_sdp {
 #define EDP_VSC_PSR_UPDATE_RFB		(1<<1)
 #define EDP_VSC_PSR_CRC_VALUES_VALID	(1<<2)
 
+/* Based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through DB18] */
+enum dp_colorspace {
+	DP_COLORSPACE_RGB = 0,
+	DP_COLORSPACE_YUV444 = 0x1,
+	DP_COLORSPACE_YUV422 = 0x2,
+	DP_COLORSPACE_YUV420 = 0x3,
+	DP_COLORSPACE_Y_ONLY = 0x4,
+	DP_COLORSPACE_RAW = 0x5,
+	DP_COLORSPACE_RESERVED = 0x6,
+};
+
+/**
+ * Based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through DB18]
+ * and a name of enum member followes DRM_MODE_COLORIMETRY definition.
+ */
+enum dp_colorimetry {
+	DP_COLORIMETRY_DEFAULT = 0, /* sRGB (IEC 61966-2-1) / ITU-R BT.601 */
+	DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
+	DP_COLORIMETRY_BT709_YCC = 0x1,
+	DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
+	DP_COLORIMETRY_XVYCC_601 = 0x2,
+	DP_COLORIMETRY_OPRGB = 0x3,
+	DP_COLORIMETRY_XVYCC_709 = 0x3,
+	DP_COLORIMETRY_DCI_P3_RGB = 0x4,
+	DP_COLORIMETRY_SYCC_601 = 0x4,
+	DP_COLORIMETRY_RGB_CUSTOM = 0x5,
+	DP_COLORIMETRY_OPYCC_601 = 0x5,
+	DP_COLORIMETRY_BT2020_RGB = 0x6,
+	DP_COLORIMETRY_BT2020_CYCC = 0x6,
+	DP_COLORIMETRY_BT2020_YCC = 0x7,
+};
+
+enum dp_dynamic_range {
+	DP_DYNAMIC_RANGE_VESA = 0,
+	DP_DYNAMIC_RANGE_CTA = 1,
+};
+
+enum dp_content_type {
+	DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
+	DP_CONTENT_TYPE_GRAPHICS = 0x01,
+	DP_CONTENT_TYPE_PHOTO = 0x02,
+	DP_CONTENT_TYPE_VIDEO = 0x03,
+	DP_CONTENT_TYPE_GAME = 0x04,
+};
+
+/* DRM DP VSC SDP as per DP 1.4 spec */
+struct drm_dp_vsc_sdp {
+	unsigned char sdp_type; /* Secondary-data Packet Type */
+	unsigned char revision; /* Revision Number */
+	unsigned char length; /* Number of Valid Data Bytes */
+	enum dp_colorspace colorspace;
+	enum dp_colorimetry colorimetry;
+	int bpc; /* bit per color */
+	enum dp_dynamic_range dynamic_range;
+	enum dp_content_type content_type;
+};
+
 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
 
 static inline int
-- 
2.24.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[Intel-gfx] [PATCH v3 01/17] drm: add DP 1.4 VSC SDP Payload related enums and a structure

[Gwan-gyeong Mun]

It adds new enumeration definitions for VSC SDP Payload for Pixel
Encoding/Colorimetry Format.
And it adds a new drm data structure for DP VSC SDP.

enum dp_colorspace and enum dp_colorimetry correspond "Pixel Encoding and
Colorimetry Formats". enum dp_dynamic_range corresponds "Dynamic Range".
And enum dp_content_type corresponds "Content Type"
All of them are based on DP 1.4 spec [Table 2-117: VSC SDP Payload for
DB16 through DB18].

v3: Add a new drm data structure for DP VSC SDP

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 include/drm/drm_dp_helper.h | 57 +++++++++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 262faf9e5e94..c098727681fa 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1209,6 +1209,63 @@ struct dp_sdp {
 #define EDP_VSC_PSR_UPDATE_RFB		(1<<1)
 #define EDP_VSC_PSR_CRC_VALUES_VALID	(1<<2)
 
+/* Based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through DB18] */
+enum dp_colorspace {
+	DP_COLORSPACE_RGB = 0,
+	DP_COLORSPACE_YUV444 = 0x1,
+	DP_COLORSPACE_YUV422 = 0x2,
+	DP_COLORSPACE_YUV420 = 0x3,
+	DP_COLORSPACE_Y_ONLY = 0x4,
+	DP_COLORSPACE_RAW = 0x5,
+	DP_COLORSPACE_RESERVED = 0x6,
+};
+
+/**
+ * Based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through DB18]
+ * and a name of enum member followes DRM_MODE_COLORIMETRY definition.
+ */
+enum dp_colorimetry {
+	DP_COLORIMETRY_DEFAULT = 0, /* sRGB (IEC 61966-2-1) / ITU-R BT.601 */
+	DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
+	DP_COLORIMETRY_BT709_YCC = 0x1,
+	DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
+	DP_COLORIMETRY_XVYCC_601 = 0x2,
+	DP_COLORIMETRY_OPRGB = 0x3,
+	DP_COLORIMETRY_XVYCC_709 = 0x3,
+	DP_COLORIMETRY_DCI_P3_RGB = 0x4,
+	DP_COLORIMETRY_SYCC_601 = 0x4,
+	DP_COLORIMETRY_RGB_CUSTOM = 0x5,
+	DP_COLORIMETRY_OPYCC_601 = 0x5,
+	DP_COLORIMETRY_BT2020_RGB = 0x6,
+	DP_COLORIMETRY_BT2020_CYCC = 0x6,
+	DP_COLORIMETRY_BT2020_YCC = 0x7,
+};
+
+enum dp_dynamic_range {
+	DP_DYNAMIC_RANGE_VESA = 0,
+	DP_DYNAMIC_RANGE_CTA = 1,
+};
+
+enum dp_content_type {
+	DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
+	DP_CONTENT_TYPE_GRAPHICS = 0x01,
+	DP_CONTENT_TYPE_PHOTO = 0x02,
+	DP_CONTENT_TYPE_VIDEO = 0x03,
+	DP_CONTENT_TYPE_GAME = 0x04,
+};
+
+/* DRM DP VSC SDP as per DP 1.4 spec */
+struct drm_dp_vsc_sdp {
+	unsigned char sdp_type; /* Secondary-data Packet Type */
+	unsigned char revision; /* Revision Number */
+	unsigned char length; /* Number of Valid Data Bytes */
+	enum dp_colorspace colorspace;
+	enum dp_colorimetry colorimetry;
+	int bpc; /* bit per color */
+	enum dp_dynamic_range dynamic_range;
+	enum dp_content_type content_type;
+};
+
 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
 
 static inline int
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 02/17] drm/i915/dp: Add compute routine for DP VSC SDP

[Gwan-gyeong Mun]

In order to support state readout for DP VSC SDP, we need to have a
structure which holds DP VSC SDP payload data such as
"union hdmi_infoframe drm" which is used for DRM infoframe.
It adds a struct drm_dp_vsc_sdp vsc to intel_crtc_state.infoframes.

And it stores computed dp vsc sdp to infoframes.vsc of crtc state.
While computing we'll also fill out the inforames.enable bitmask
appropriately.

The compute routine follows DP 1.4 spec [Table 2-117: VSC SDP Payload for
DB16 through DB18].

v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 92 +++++++++++++++++++
 2 files changed, 93 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 33ba93863488..6633c1061670 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1021,6 +1021,7 @@ struct intel_crtc_state {
 		union hdmi_infoframe spd;
 		union hdmi_infoframe hdmi;
 		union hdmi_infoframe drm;
+		struct drm_dp_vsc_sdp vsc;
 	} infoframes;
 
 	/* HDMI scrambling status */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f4dede6253f8..2bdc43c80e03 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2372,6 +2372,97 @@ static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
 	return true;
 }
 
+static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
+					     const struct drm_connector_state *conn_state,
+					     struct drm_dp_vsc_sdp *vsc)
+{
+	/*
+	 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
+	 * Colorimetry Format indication.
+	 */
+	vsc->revision = 0x5;
+	vsc->length = 0x13;
+
+	/* DP 1.4a spec, Table 2-120 */
+	switch (crtc_state->output_format) {
+	case INTEL_OUTPUT_FORMAT_YCBCR444:
+		vsc->colorspace = DP_COLORSPACE_YUV444;
+		break;
+	case INTEL_OUTPUT_FORMAT_YCBCR420:
+		vsc->colorspace = DP_COLORSPACE_YUV420;
+		break;
+	case INTEL_OUTPUT_FORMAT_RGB:
+	default:
+		vsc->colorspace = DP_COLORSPACE_RGB;
+	}
+
+	switch (conn_state->colorspace) {
+	case DRM_MODE_COLORIMETRY_BT709_YCC:
+		vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
+		break;
+	case DRM_MODE_COLORIMETRY_XVYCC_601:
+		vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
+		break;
+	case DRM_MODE_COLORIMETRY_XVYCC_709:
+		vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
+		break;
+	case DRM_MODE_COLORIMETRY_SYCC_601:
+		vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
+		break;
+	case DRM_MODE_COLORIMETRY_OPYCC_601:
+		vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
+		break;
+	case DRM_MODE_COLORIMETRY_BT2020_CYCC:
+		vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
+		break;
+	case DRM_MODE_COLORIMETRY_BT2020_RGB:
+		vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
+		break;
+	case DRM_MODE_COLORIMETRY_BT2020_YCC:
+		vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
+		break;
+	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
+	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
+		vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
+		break;
+	default:
+		/*
+		 * RGB->YCBCR color conversion uses the BT.709
+		 * color space.
+		 */
+		if (crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420)
+			vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
+		else
+			vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
+		break;
+	}
+
+	vsc->bpc = crtc_state->pipe_bpp / 3;
+	/* all YCbCr are always limited range */
+	vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
+	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
+}
+
+static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
+				     struct intel_crtc_state *crtc_state,
+				     const struct drm_connector_state *conn_state)
+{
+	struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
+
+	/* When PSR is enabled, VSC SDP is handled by PSR routine */
+	if (intel_psr_enabled(intel_dp))
+		return;
+
+	if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
+		return;
+
+	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
+	vsc->sdp_type = DP_SDP_VSC;
+	intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
+					 &crtc_state->infoframes.vsc);
+}
+
 int
 intel_dp_compute_config(struct intel_encoder *encoder,
 			struct intel_crtc_state *pipe_config,
@@ -2477,6 +2568,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 		intel_dp_set_clock(encoder, pipe_config);
 
 	intel_psr_compute_config(intel_dp, pipe_config);
+	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
 
 	return 0;
 }
-- 
2.24.1

[PATCH v3 02/17] drm/i915/dp: Add compute routine for DP VSC SDP

[Gwan-gyeong Mun]

In order to support state readout for DP VSC SDP, we need to have a
structure which holds DP VSC SDP payload data such as
"union hdmi_infoframe drm" which is used for DRM infoframe.
It adds a struct drm_dp_vsc_sdp vsc to intel_crtc_state.infoframes.

And it stores computed dp vsc sdp to infoframes.vsc of crtc state.
While computing we'll also fill out the inforames.enable bitmask
appropriately.

The compute routine follows DP 1.4 spec [Table 2-117: VSC SDP Payload for
DB16 through DB18].

v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 92 +++++++++++++++++++
 2 files changed, 93 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 33ba93863488..6633c1061670 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1021,6 +1021,7 @@ struct intel_crtc_state {
 		union hdmi_infoframe spd;
 		union hdmi_infoframe hdmi;
 		union hdmi_infoframe drm;
+		struct drm_dp_vsc_sdp vsc;
 	} infoframes;
 
 	/* HDMI scrambling status */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f4dede6253f8..2bdc43c80e03 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2372,6 +2372,97 @@ static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
 	return true;
 }
 
+static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
+					     const struct drm_connector_state *conn_state,
+					     struct drm_dp_vsc_sdp *vsc)
+{
+	/*
+	 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
+	 * Colorimetry Format indication.
+	 */
+	vsc->revision = 0x5;
+	vsc->length = 0x13;
+
+	/* DP 1.4a spec, Table 2-120 */
+	switch (crtc_state->output_format) {
+	case INTEL_OUTPUT_FORMAT_YCBCR444:
+		vsc->colorspace = DP_COLORSPACE_YUV444;
+		break;
+	case INTEL_OUTPUT_FORMAT_YCBCR420:
+		vsc->colorspace = DP_COLORSPACE_YUV420;
+		break;
+	case INTEL_OUTPUT_FORMAT_RGB:
+	default:
+		vsc->colorspace = DP_COLORSPACE_RGB;
+	}
+
+	switch (conn_state->colorspace) {
+	case DRM_MODE_COLORIMETRY_BT709_YCC:
+		vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
+		break;
+	case DRM_MODE_COLORIMETRY_XVYCC_601:
+		vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
+		break;
+	case DRM_MODE_COLORIMETRY_XVYCC_709:
+		vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
+		break;
+	case DRM_MODE_COLORIMETRY_SYCC_601:
+		vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
+		break;
+	case DRM_MODE_COLORIMETRY_OPYCC_601:
+		vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
+		break;
+	case DRM_MODE_COLORIMETRY_BT2020_CYCC:
+		vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
+		break;
+	case DRM_MODE_COLORIMETRY_BT2020_RGB:
+		vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
+		break;
+	case DRM_MODE_COLORIMETRY_BT2020_YCC:
+		vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
+		break;
+	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
+	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
+		vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
+		break;
+	default:
+		/*
+		 * RGB->YCBCR color conversion uses the BT.709
+		 * color space.
+		 */
+		if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+			vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
+		else
+			vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
+		break;
+	}
+
+	vsc->bpc = crtc_state->pipe_bpp / 3;
+	/* all YCbCr are always limited range */
+	vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
+	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
+}
+
+static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
+				     struct intel_crtc_state *crtc_state,
+				     const struct drm_connector_state *conn_state)
+{
+	struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
+
+	/* When PSR is enabled, VSC SDP is handled by PSR routine */
+	if (intel_psr_enabled(intel_dp))
+		return;
+
+	if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
+		return;
+
+	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
+	vsc->sdp_type = DP_SDP_VSC;
+	intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
+					 &crtc_state->infoframes.vsc);
+}
+
 int
 intel_dp_compute_config(struct intel_encoder *encoder,
 			struct intel_crtc_state *pipe_config,
@@ -2477,6 +2568,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 		intel_dp_set_clock(encoder, pipe_config);
 
 	intel_psr_compute_config(intel_dp, pipe_config);
+	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
 
 	return 0;
 }
-- 
2.24.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[Intel-gfx] [PATCH v3 02/17] drm/i915/dp: Add compute routine for DP VSC SDP

[Gwan-gyeong Mun]

In order to support state readout for DP VSC SDP, we need to have a
structure which holds DP VSC SDP payload data such as
"union hdmi_infoframe drm" which is used for DRM infoframe.
It adds a struct drm_dp_vsc_sdp vsc to intel_crtc_state.infoframes.

And it stores computed dp vsc sdp to infoframes.vsc of crtc state.
While computing we'll also fill out the inforames.enable bitmask
appropriately.

The compute routine follows DP 1.4 spec [Table 2-117: VSC SDP Payload for
DB16 through DB18].

v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 92 +++++++++++++++++++
 2 files changed, 93 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 33ba93863488..6633c1061670 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1021,6 +1021,7 @@ struct intel_crtc_state {
 		union hdmi_infoframe spd;
 		union hdmi_infoframe hdmi;
 		union hdmi_infoframe drm;
+		struct drm_dp_vsc_sdp vsc;
 	} infoframes;
 
 	/* HDMI scrambling status */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f4dede6253f8..2bdc43c80e03 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2372,6 +2372,97 @@ static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
 	return true;
 }
 
+static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
+					     const struct drm_connector_state *conn_state,
+					     struct drm_dp_vsc_sdp *vsc)
+{
+	/*
+	 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
+	 * Colorimetry Format indication.
+	 */
+	vsc->revision = 0x5;
+	vsc->length = 0x13;
+
+	/* DP 1.4a spec, Table 2-120 */
+	switch (crtc_state->output_format) {
+	case INTEL_OUTPUT_FORMAT_YCBCR444:
+		vsc->colorspace = DP_COLORSPACE_YUV444;
+		break;
+	case INTEL_OUTPUT_FORMAT_YCBCR420:
+		vsc->colorspace = DP_COLORSPACE_YUV420;
+		break;
+	case INTEL_OUTPUT_FORMAT_RGB:
+	default:
+		vsc->colorspace = DP_COLORSPACE_RGB;
+	}
+
+	switch (conn_state->colorspace) {
+	case DRM_MODE_COLORIMETRY_BT709_YCC:
+		vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
+		break;
+	case DRM_MODE_COLORIMETRY_XVYCC_601:
+		vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
+		break;
+	case DRM_MODE_COLORIMETRY_XVYCC_709:
+		vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
+		break;
+	case DRM_MODE_COLORIMETRY_SYCC_601:
+		vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
+		break;
+	case DRM_MODE_COLORIMETRY_OPYCC_601:
+		vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
+		break;
+	case DRM_MODE_COLORIMETRY_BT2020_CYCC:
+		vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
+		break;
+	case DRM_MODE_COLORIMETRY_BT2020_RGB:
+		vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
+		break;
+	case DRM_MODE_COLORIMETRY_BT2020_YCC:
+		vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
+		break;
+	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
+	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
+		vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
+		break;
+	default:
+		/*
+		 * RGB->YCBCR color conversion uses the BT.709
+		 * color space.
+		 */
+		if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+			vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
+		else
+			vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
+		break;
+	}
+
+	vsc->bpc = crtc_state->pipe_bpp / 3;
+	/* all YCbCr are always limited range */
+	vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
+	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
+}
+
+static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
+				     struct intel_crtc_state *crtc_state,
+				     const struct drm_connector_state *conn_state)
+{
+	struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
+
+	/* When PSR is enabled, VSC SDP is handled by PSR routine */
+	if (intel_psr_enabled(intel_dp))
+		return;
+
+	if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
+		return;
+
+	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
+	vsc->sdp_type = DP_SDP_VSC;
+	intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
+					 &crtc_state->infoframes.vsc);
+}
+
 int
 intel_dp_compute_config(struct intel_encoder *encoder,
 			struct intel_crtc_state *pipe_config,
@@ -2477,6 +2568,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 		intel_dp_set_clock(encoder, pipe_config);
 
 	intel_psr_compute_config(intel_dp, pipe_config);
+	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
 
 	return 0;
 }
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 03/17] drm/i915/dp: Add compute routine for DP HDR Metadata Infoframe SDP

[Gwan-gyeong Mun]

It stores computed dp hdr metadata infoframe sdp to infoframes.drm of
crtc state. It referenced intel_hdmi_compute_drm_infoframe().

While computing, we'll also fill out the inforames.enable bitmask
appropriately.

v2: Wrap a long line.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2bdc43c80e03..b265b5c599f2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2463,6 +2463,27 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
 					 &crtc_state->infoframes.vsc);
 }
 
+static void
+intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_crtc_state *crtc_state,
+					    const struct drm_connector_state *conn_state)
+{
+	int ret;
+	struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
+
+	if (!conn_state->hdr_output_metadata)
+		return;
+
+	ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
+
+	if (ret) {
+		DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
+		return;
+	}
+
+	crtc_state->infoframes.enable |+		intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
+}
+
 int
 intel_dp_compute_config(struct intel_encoder *encoder,
 			struct intel_crtc_state *pipe_config,
@@ -2569,6 +2590,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 
 	intel_psr_compute_config(intel_dp, pipe_config);
 	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
+	intel_dp_compute_hdr_metadata_infoframe_sdp(pipe_config, conn_state);
 
 	return 0;
 }
-- 
2.24.1

[PATCH v3 03/17] drm/i915/dp: Add compute routine for DP HDR Metadata Infoframe SDP

[Gwan-gyeong Mun]

It stores computed dp hdr metadata infoframe sdp to infoframes.drm of
crtc state. It referenced intel_hdmi_compute_drm_infoframe().

While computing, we'll also fill out the inforames.enable bitmask
appropriately.

v2: Wrap a long line.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2bdc43c80e03..b265b5c599f2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2463,6 +2463,27 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
 					 &crtc_state->infoframes.vsc);
 }
 
+static void
+intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_crtc_state *crtc_state,
+					    const struct drm_connector_state *conn_state)
+{
+	int ret;
+	struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
+
+	if (!conn_state->hdr_output_metadata)
+		return;
+
+	ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
+
+	if (ret) {
+		DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
+		return;
+	}
+
+	crtc_state->infoframes.enable |=
+		intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
+}
+
 int
 intel_dp_compute_config(struct intel_encoder *encoder,
 			struct intel_crtc_state *pipe_config,
@@ -2569,6 +2590,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 
 	intel_psr_compute_config(intel_dp, pipe_config);
 	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
+	intel_dp_compute_hdr_metadata_infoframe_sdp(pipe_config, conn_state);
 
 	return 0;
 }
-- 
2.24.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[Intel-gfx] [PATCH v3 03/17] drm/i915/dp: Add compute routine for DP HDR Metadata Infoframe SDP

[Gwan-gyeong Mun]

It stores computed dp hdr metadata infoframe sdp to infoframes.drm of
crtc state. It referenced intel_hdmi_compute_drm_infoframe().

While computing, we'll also fill out the inforames.enable bitmask
appropriately.

v2: Wrap a long line.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2bdc43c80e03..b265b5c599f2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2463,6 +2463,27 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
 					 &crtc_state->infoframes.vsc);
 }
 
+static void
+intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_crtc_state *crtc_state,
+					    const struct drm_connector_state *conn_state)
+{
+	int ret;
+	struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
+
+	if (!conn_state->hdr_output_metadata)
+		return;
+
+	ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
+
+	if (ret) {
+		DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
+		return;
+	}
+
+	crtc_state->infoframes.enable |=
+		intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
+}
+
 int
 intel_dp_compute_config(struct intel_encoder *encoder,
 			struct intel_crtc_state *pipe_config,
@@ -2569,6 +2590,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 
 	intel_psr_compute_config(intel_dp, pipe_config);
 	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
+	intel_dp_compute_hdr_metadata_infoframe_sdp(pipe_config, conn_state);
 
 	return 0;
 }
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs (Secondary Data Packet)

[Gwan-gyeong Mun]

It adds routines that write DP VSC SDP and DP HDR Metadata Infoframe SDP.
In order to pack DP VSC SDP, it adds intel_dp_vsc_sdp_pack() function.
It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and
[Table 2-117: VSC SDP Payload for DB16 through DB18]

In order to pack DP HDR Metadata Infoframe SDP, it adds
intel_dp_hdr_metadata_infoframe_sdp_pack() function.
And it follows DP 1.4a spec.
([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and
[Table 2-126: INFOFRAME SDP v1.2 Payload Data Bytes - DB0 through DB31])
and CTA-861-G spec. [Table-42 Dynamic Range and Mastering InfoFrame].

A machanism and a naming rule of intel_dp_set_infoframes() function
references intel_encoder->set_infoframes() of intel_hdmi.c .
VSC SDP is used for PSR and Pixel Encoding and Colorimetry Formats cases.
Because PSR routine has its own routine of writing a VSC SDP, when the PSR
is enabled, intel_dp_set_infoframes() does not write a VSC SDP.

v3:
  - Explicitly disable unused DIPs (AVI, GCP, VS, SPD, DRM. They will be
    used for HDMI), when intel_dp_set_infoframes() function will be called.
  - Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 194 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h |   3 +
 2 files changed, 197 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b265b5c599f2..dd7e5588001e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4731,6 +4731,200 @@ intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
 	return false;
 }
 
+static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
+				     struct dp_sdp *sdp, size_t size)
+{
+	size_t length = sizeof(struct dp_sdp);
+
+	if (size < length)
+		return -ENOSPC;
+
+	memset(sdp, 0, size);
+
+	/*
+	 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
+	 * VSC SDP Header Bytes
+	 */
+	sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
+	sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
+	sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
+	sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
+
+	/* VSC SDP Payload for DB16 through DB18 */
+	/* Pixel Encoding and Colorimetry Formats  */
+	sdp->db[16] = (vsc->colorspace & 0xf) << 4; /* DB16[7:4] */
+	sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
+
+	switch (vsc->bpc) {
+	case 8:
+		sdp->db[17] = 0x1; /* DB17[3:0] */
+		break;
+	case 10:
+		sdp->db[17] = 0x2;
+		break;
+	case 12:
+		sdp->db[17] = 0x3;
+		break;
+	case 16:
+		sdp->db[17] = 0x4;
+		break;
+	default:
+		MISSING_CASE(vsc->bpc);
+		break;
+	}
+	/* Dynamic Range and Component Bit Depth */
+	if (vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA)
+		sdp->db[17] |= 0x80;  /* DB17[7] */
+
+	/* Content Type */
+	sdp->db[18] = vsc->content_type & 0x7;
+
+	return length;
+}
+
+static ssize_t
+intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe,
+					 struct dp_sdp *sdp,
+					 size_t size)
+{
+	size_t length = sizeof(struct dp_sdp);
+	const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
+	unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
+	ssize_t len;
+
+	if (size < length)
+		return -ENOSPC;
+
+	memset(sdp, 0, size);
+
+	len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
+	if (len < 0) {
+		DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
+		return -ENOSPC;
+	}
+
+	if (len != infoframe_size) {
+		DRM_DEBUG_KMS("wrong static hdr metadata size\n");
+		return -ENOSPC;
+	}
+
+	/*
+	 * Set up the infoframe sdp packet for HDR static metadata.
+	 * Prepare VSC Header for SU as per DP 1.4a spec,
+	 * Table 2-100 and Table 2-101
+	 */
+
+	/* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
+	sdp->sdp_header.HB0 = 0;
+	/*
+	 * Packet Type 80h + Non-audio INFOFRAME Type value
+	 * HDMI_INFOFRAME_TYPE_DRM: 0x87
+	 * - 80h + Non-audio INFOFRAME Type value
+	 * - InfoFrame Type: 0x07
+	 *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
+	 */
+	sdp->sdp_header.HB1 = drm_infoframe->type;
+	/*
+	 * Least Significant Eight Bits of (Data Byte Count – 1)
+	 * infoframe_size - 1
+	 */
+	sdp->sdp_header.HB2 = 0x1D;
+	/* INFOFRAME SDP Version Number */
+	sdp->sdp_header.HB3 = (0x13 << 2);
+	/* CTA Header Byte 2 (INFOFRAME Version Number) */
+	sdp->db[0] = drm_infoframe->version;
+	/* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
+	sdp->db[1] = drm_infoframe->length;
+	/*
+	 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
+	 */
+	BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
+	memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
+	       HDMI_DRM_INFOFRAME_SIZE);
+
+	/*
+	 * Size of DP infoframe sdp packet for HDR static metadata is consist of
+	 * - DP SDP Header(struct dp_sdp_header): 4 bytes
+	 * - Two Data Blocks: 2 bytes
+	 *    CTA Header Byte2 (INFOFRAME Version Number)
+	 *    CTA Header Byte3 (Length of INFOFRAME)
+	 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
+	 *
+	 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
+	 * infoframe size. But GEN11+ has larger than that size, write_infoframe
+	 * will pad rest of the size.
+	 */
+	return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
+}
+
+static void intel_write_dp_sdp(struct intel_encoder *encoder,
+			       const struct intel_crtc_state *crtc_state,
+			       unsigned int type)
+{
+	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+	struct dp_sdp sdp = {};
+	ssize_t len;
+
+	if ((crtc_state->infoframes.enable &
+	     intel_hdmi_infoframe_enable(type)) = 0)
+		return;
+
+	switch (type) {
+	case DP_SDP_VSC:
+		len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
+					    sizeof(sdp));
+		break;
+	case HDMI_PACKET_TYPE_GAMUT_METADATA:
+		len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm,
+							       &sdp, sizeof(sdp));
+		break;
+	default:
+		MISSING_CASE(type);
+		break;
+	}
+
+	if (WARN_ON(len < 0))
+		return;
+
+	intel_dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
+}
+
+void intel_dp_set_infoframes(struct intel_encoder *encoder,
+			     bool enable,
+			     const struct intel_crtc_state *crtc_state,
+			     const struct drm_connector_state *conn_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
+	u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
+			 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
+			 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
+	u32 val = I915_READ(reg);
+
+	/* TODO: Add DSC case (DIP_ENABLE_PPS) */
+	/* When PSR is enabled, this routine doesn't disable VSC DIP */
+	if (intel_psr_enabled(intel_dp))
+		val &= ~dip_enable;
+	else
+		val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
+
+	if (!enable) {
+		I915_WRITE(reg, val);
+		POSTING_READ(reg);
+		return;
+	}
+
+	I915_WRITE(reg, val);
+	POSTING_READ(reg);
+
+	/* When PSR is enabled, VSC SDP is handled by PSR routine */
+	if (!intel_psr_enabled(intel_dp))
+		intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
+
+	intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
+}
+
 static void
 intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
 		       const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 3da166054788..0dc09a463ee1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -116,6 +116,9 @@ void intel_dp_vsc_enable(struct intel_dp *intel_dp,
 void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
 				  const struct intel_crtc_state *crtc_state,
 				  const struct drm_connector_state *conn_state);
+void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
+			     const struct intel_crtc_state *crtc_state,
+			     const struct drm_connector_state *conn_state);
 bool intel_digital_port_connected(struct intel_encoder *encoder);
 
 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
-- 
2.24.1

[PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs (Secondary Data Packet)

[Gwan-gyeong Mun]

It adds routines that write DP VSC SDP and DP HDR Metadata Infoframe SDP.
In order to pack DP VSC SDP, it adds intel_dp_vsc_sdp_pack() function.
It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and
[Table 2-117: VSC SDP Payload for DB16 through DB18]

In order to pack DP HDR Metadata Infoframe SDP, it adds
intel_dp_hdr_metadata_infoframe_sdp_pack() function.
And it follows DP 1.4a spec.
([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and
[Table 2-126: INFOFRAME SDP v1.2 Payload Data Bytes - DB0 through DB31])
and CTA-861-G spec. [Table-42 Dynamic Range and Mastering InfoFrame].

A machanism and a naming rule of intel_dp_set_infoframes() function
references intel_encoder->set_infoframes() of intel_hdmi.c .
VSC SDP is used for PSR and Pixel Encoding and Colorimetry Formats cases.
Because PSR routine has its own routine of writing a VSC SDP, when the PSR
is enabled, intel_dp_set_infoframes() does not write a VSC SDP.

v3:
  - Explicitly disable unused DIPs (AVI, GCP, VS, SPD, DRM. They will be
    used for HDMI), when intel_dp_set_infoframes() function will be called.
  - Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 194 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h |   3 +
 2 files changed, 197 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b265b5c599f2..dd7e5588001e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4731,6 +4731,200 @@ intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
 	return false;
 }
 
+static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
+				     struct dp_sdp *sdp, size_t size)
+{
+	size_t length = sizeof(struct dp_sdp);
+
+	if (size < length)
+		return -ENOSPC;
+
+	memset(sdp, 0, size);
+
+	/*
+	 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
+	 * VSC SDP Header Bytes
+	 */
+	sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
+	sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
+	sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
+	sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
+
+	/* VSC SDP Payload for DB16 through DB18 */
+	/* Pixel Encoding and Colorimetry Formats  */
+	sdp->db[16] = (vsc->colorspace & 0xf) << 4; /* DB16[7:4] */
+	sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
+
+	switch (vsc->bpc) {
+	case 8:
+		sdp->db[17] = 0x1; /* DB17[3:0] */
+		break;
+	case 10:
+		sdp->db[17] = 0x2;
+		break;
+	case 12:
+		sdp->db[17] = 0x3;
+		break;
+	case 16:
+		sdp->db[17] = 0x4;
+		break;
+	default:
+		MISSING_CASE(vsc->bpc);
+		break;
+	}
+	/* Dynamic Range and Component Bit Depth */
+	if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
+		sdp->db[17] |= 0x80;  /* DB17[7] */
+
+	/* Content Type */
+	sdp->db[18] = vsc->content_type & 0x7;
+
+	return length;
+}
+
+static ssize_t
+intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe,
+					 struct dp_sdp *sdp,
+					 size_t size)
+{
+	size_t length = sizeof(struct dp_sdp);
+	const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
+	unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
+	ssize_t len;
+
+	if (size < length)
+		return -ENOSPC;
+
+	memset(sdp, 0, size);
+
+	len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
+	if (len < 0) {
+		DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
+		return -ENOSPC;
+	}
+
+	if (len != infoframe_size) {
+		DRM_DEBUG_KMS("wrong static hdr metadata size\n");
+		return -ENOSPC;
+	}
+
+	/*
+	 * Set up the infoframe sdp packet for HDR static metadata.
+	 * Prepare VSC Header for SU as per DP 1.4a spec,
+	 * Table 2-100 and Table 2-101
+	 */
+
+	/* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
+	sdp->sdp_header.HB0 = 0;
+	/*
+	 * Packet Type 80h + Non-audio INFOFRAME Type value
+	 * HDMI_INFOFRAME_TYPE_DRM: 0x87
+	 * - 80h + Non-audio INFOFRAME Type value
+	 * - InfoFrame Type: 0x07
+	 *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
+	 */
+	sdp->sdp_header.HB1 = drm_infoframe->type;
+	/*
+	 * Least Significant Eight Bits of (Data Byte Count – 1)
+	 * infoframe_size - 1
+	 */
+	sdp->sdp_header.HB2 = 0x1D;
+	/* INFOFRAME SDP Version Number */
+	sdp->sdp_header.HB3 = (0x13 << 2);
+	/* CTA Header Byte 2 (INFOFRAME Version Number) */
+	sdp->db[0] = drm_infoframe->version;
+	/* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
+	sdp->db[1] = drm_infoframe->length;
+	/*
+	 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
+	 */
+	BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
+	memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
+	       HDMI_DRM_INFOFRAME_SIZE);
+
+	/*
+	 * Size of DP infoframe sdp packet for HDR static metadata is consist of
+	 * - DP SDP Header(struct dp_sdp_header): 4 bytes
+	 * - Two Data Blocks: 2 bytes
+	 *    CTA Header Byte2 (INFOFRAME Version Number)
+	 *    CTA Header Byte3 (Length of INFOFRAME)
+	 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
+	 *
+	 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
+	 * infoframe size. But GEN11+ has larger than that size, write_infoframe
+	 * will pad rest of the size.
+	 */
+	return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
+}
+
+static void intel_write_dp_sdp(struct intel_encoder *encoder,
+			       const struct intel_crtc_state *crtc_state,
+			       unsigned int type)
+{
+	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+	struct dp_sdp sdp = {};
+	ssize_t len;
+
+	if ((crtc_state->infoframes.enable &
+	     intel_hdmi_infoframe_enable(type)) == 0)
+		return;
+
+	switch (type) {
+	case DP_SDP_VSC:
+		len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
+					    sizeof(sdp));
+		break;
+	case HDMI_PACKET_TYPE_GAMUT_METADATA:
+		len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm,
+							       &sdp, sizeof(sdp));
+		break;
+	default:
+		MISSING_CASE(type);
+		break;
+	}
+
+	if (WARN_ON(len < 0))
+		return;
+
+	intel_dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
+}
+
+void intel_dp_set_infoframes(struct intel_encoder *encoder,
+			     bool enable,
+			     const struct intel_crtc_state *crtc_state,
+			     const struct drm_connector_state *conn_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
+	u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
+			 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
+			 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
+	u32 val = I915_READ(reg);
+
+	/* TODO: Add DSC case (DIP_ENABLE_PPS) */
+	/* When PSR is enabled, this routine doesn't disable VSC DIP */
+	if (intel_psr_enabled(intel_dp))
+		val &= ~dip_enable;
+	else
+		val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
+
+	if (!enable) {
+		I915_WRITE(reg, val);
+		POSTING_READ(reg);
+		return;
+	}
+
+	I915_WRITE(reg, val);
+	POSTING_READ(reg);
+
+	/* When PSR is enabled, VSC SDP is handled by PSR routine */
+	if (!intel_psr_enabled(intel_dp))
+		intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
+
+	intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
+}
+
 static void
 intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
 		       const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 3da166054788..0dc09a463ee1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -116,6 +116,9 @@ void intel_dp_vsc_enable(struct intel_dp *intel_dp,
 void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
 				  const struct intel_crtc_state *crtc_state,
 				  const struct drm_connector_state *conn_state);
+void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
+			     const struct intel_crtc_state *crtc_state,
+			     const struct drm_connector_state *conn_state);
 bool intel_digital_port_connected(struct intel_encoder *encoder);
 
 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
-- 
2.24.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[Intel-gfx] [PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs (Secondary Data Packet)

[Gwan-gyeong Mun]

It adds routines that write DP VSC SDP and DP HDR Metadata Infoframe SDP.
In order to pack DP VSC SDP, it adds intel_dp_vsc_sdp_pack() function.
It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and
[Table 2-117: VSC SDP Payload for DB16 through DB18]

In order to pack DP HDR Metadata Infoframe SDP, it adds
intel_dp_hdr_metadata_infoframe_sdp_pack() function.
And it follows DP 1.4a spec.
([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and
[Table 2-126: INFOFRAME SDP v1.2 Payload Data Bytes - DB0 through DB31])
and CTA-861-G spec. [Table-42 Dynamic Range and Mastering InfoFrame].

A machanism and a naming rule of intel_dp_set_infoframes() function
references intel_encoder->set_infoframes() of intel_hdmi.c .
VSC SDP is used for PSR and Pixel Encoding and Colorimetry Formats cases.
Because PSR routine has its own routine of writing a VSC SDP, when the PSR
is enabled, intel_dp_set_infoframes() does not write a VSC SDP.

v3:
  - Explicitly disable unused DIPs (AVI, GCP, VS, SPD, DRM. They will be
    used for HDMI), when intel_dp_set_infoframes() function will be called.
  - Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 194 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h |   3 +
 2 files changed, 197 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b265b5c599f2..dd7e5588001e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4731,6 +4731,200 @@ intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
 	return false;
 }
 
+static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
+				     struct dp_sdp *sdp, size_t size)
+{
+	size_t length = sizeof(struct dp_sdp);
+
+	if (size < length)
+		return -ENOSPC;
+
+	memset(sdp, 0, size);
+
+	/*
+	 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
+	 * VSC SDP Header Bytes
+	 */
+	sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
+	sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
+	sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
+	sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
+
+	/* VSC SDP Payload for DB16 through DB18 */
+	/* Pixel Encoding and Colorimetry Formats  */
+	sdp->db[16] = (vsc->colorspace & 0xf) << 4; /* DB16[7:4] */
+	sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
+
+	switch (vsc->bpc) {
+	case 8:
+		sdp->db[17] = 0x1; /* DB17[3:0] */
+		break;
+	case 10:
+		sdp->db[17] = 0x2;
+		break;
+	case 12:
+		sdp->db[17] = 0x3;
+		break;
+	case 16:
+		sdp->db[17] = 0x4;
+		break;
+	default:
+		MISSING_CASE(vsc->bpc);
+		break;
+	}
+	/* Dynamic Range and Component Bit Depth */
+	if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
+		sdp->db[17] |= 0x80;  /* DB17[7] */
+
+	/* Content Type */
+	sdp->db[18] = vsc->content_type & 0x7;
+
+	return length;
+}
+
+static ssize_t
+intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe,
+					 struct dp_sdp *sdp,
+					 size_t size)
+{
+	size_t length = sizeof(struct dp_sdp);
+	const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
+	unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
+	ssize_t len;
+
+	if (size < length)
+		return -ENOSPC;
+
+	memset(sdp, 0, size);
+
+	len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
+	if (len < 0) {
+		DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
+		return -ENOSPC;
+	}
+
+	if (len != infoframe_size) {
+		DRM_DEBUG_KMS("wrong static hdr metadata size\n");
+		return -ENOSPC;
+	}
+
+	/*
+	 * Set up the infoframe sdp packet for HDR static metadata.
+	 * Prepare VSC Header for SU as per DP 1.4a spec,
+	 * Table 2-100 and Table 2-101
+	 */
+
+	/* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
+	sdp->sdp_header.HB0 = 0;
+	/*
+	 * Packet Type 80h + Non-audio INFOFRAME Type value
+	 * HDMI_INFOFRAME_TYPE_DRM: 0x87
+	 * - 80h + Non-audio INFOFRAME Type value
+	 * - InfoFrame Type: 0x07
+	 *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
+	 */
+	sdp->sdp_header.HB1 = drm_infoframe->type;
+	/*
+	 * Least Significant Eight Bits of (Data Byte Count – 1)
+	 * infoframe_size - 1
+	 */
+	sdp->sdp_header.HB2 = 0x1D;
+	/* INFOFRAME SDP Version Number */
+	sdp->sdp_header.HB3 = (0x13 << 2);
+	/* CTA Header Byte 2 (INFOFRAME Version Number) */
+	sdp->db[0] = drm_infoframe->version;
+	/* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
+	sdp->db[1] = drm_infoframe->length;
+	/*
+	 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
+	 */
+	BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
+	memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
+	       HDMI_DRM_INFOFRAME_SIZE);
+
+	/*
+	 * Size of DP infoframe sdp packet for HDR static metadata is consist of
+	 * - DP SDP Header(struct dp_sdp_header): 4 bytes
+	 * - Two Data Blocks: 2 bytes
+	 *    CTA Header Byte2 (INFOFRAME Version Number)
+	 *    CTA Header Byte3 (Length of INFOFRAME)
+	 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
+	 *
+	 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
+	 * infoframe size. But GEN11+ has larger than that size, write_infoframe
+	 * will pad rest of the size.
+	 */
+	return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
+}
+
+static void intel_write_dp_sdp(struct intel_encoder *encoder,
+			       const struct intel_crtc_state *crtc_state,
+			       unsigned int type)
+{
+	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+	struct dp_sdp sdp = {};
+	ssize_t len;
+
+	if ((crtc_state->infoframes.enable &
+	     intel_hdmi_infoframe_enable(type)) == 0)
+		return;
+
+	switch (type) {
+	case DP_SDP_VSC:
+		len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
+					    sizeof(sdp));
+		break;
+	case HDMI_PACKET_TYPE_GAMUT_METADATA:
+		len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm,
+							       &sdp, sizeof(sdp));
+		break;
+	default:
+		MISSING_CASE(type);
+		break;
+	}
+
+	if (WARN_ON(len < 0))
+		return;
+
+	intel_dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
+}
+
+void intel_dp_set_infoframes(struct intel_encoder *encoder,
+			     bool enable,
+			     const struct intel_crtc_state *crtc_state,
+			     const struct drm_connector_state *conn_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
+	u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
+			 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
+			 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
+	u32 val = I915_READ(reg);
+
+	/* TODO: Add DSC case (DIP_ENABLE_PPS) */
+	/* When PSR is enabled, this routine doesn't disable VSC DIP */
+	if (intel_psr_enabled(intel_dp))
+		val &= ~dip_enable;
+	else
+		val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
+
+	if (!enable) {
+		I915_WRITE(reg, val);
+		POSTING_READ(reg);
+		return;
+	}
+
+	I915_WRITE(reg, val);
+	POSTING_READ(reg);
+
+	/* When PSR is enabled, VSC SDP is handled by PSR routine */
+	if (!intel_psr_enabled(intel_dp))
+		intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
+
+	intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
+}
+
 static void
 intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
 		       const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 3da166054788..0dc09a463ee1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -116,6 +116,9 @@ void intel_dp_vsc_enable(struct intel_dp *intel_dp,
 void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
 				  const struct intel_crtc_state *crtc_state,
 				  const struct drm_connector_state *conn_state);
+void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
+			     const struct intel_crtc_state *crtc_state,
+			     const struct drm_connector_state *conn_state);
 bool intel_digital_port_connected(struct intel_encoder *encoder);
 
 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 05/17] video/hdmi: Add Unpack only function for DRM infoframe

[Gwan-gyeong Mun]

It adds an unpack only function for DRM infoframe for dynamic range and
mastering infoframe readout.
It unpacks the information data block contained in the binary buffer into
a structured frame of the HDMI Dynamic Range and Mastering (DRM)
information frame.

In contrast to hdmi_drm_infoframe_unpack() function, it does not verify
a checksum.

It can be used for unpacking a DP HDR Metadata Infoframe SDP case.
DP HDR Metadata Infoframe SDP uses the same Dynamic Range and Mastering
(DRM) information (CTA-861-G spec.) such as HDMI DRM infoframe.
But DP SDP header and payload structure are different from HDMI DRM
Infoframe. Therefore unpacking DRM infoframe for DP requires skipping of
a verifying checksum.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/video/hdmi.c | 58 +++++++++++++++++++++++++++++++-------------
 include/linux/hdmi.h |  2 ++
 2 files changed, 43 insertions(+), 17 deletions(-)

diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 9c82e2a0a411..9818836d82b7 100644
--- a/drivers/video/hdmi.c
+++ b/drivers/video/hdmi.c
@@ -1775,20 +1775,18 @@ hdmi_vendor_any_infoframe_unpack(union hdmi_vendor_any_infoframe *frame,
 }
 
 /**
- * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
+ * hdmi_drm_infoframe_unpack_only() - unpack binary buffer to a HDMI DRM infoframe
  * @frame: HDMI DRM infoframe
  * @buffer: source buffer
  * @size: size of buffer
  *
- * Unpacks the information contained in binary @buffer into a structured
+ * Unpacks the information data block contained in binary @buffer into a structured
  * @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
- * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4
- * specification.
  *
  * Returns 0 on success or a negative error code on failure.
  */
-static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
-				     const void *buffer, size_t size)
+int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
+				   const void *buffer, size_t size)
 {
 	const u8 *ptr = buffer;
 	const u8 *temp;
@@ -1797,23 +1795,13 @@ static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
 	int ret;
 	int i;
 
-	if (size < HDMI_INFOFRAME_SIZE(DRM))
-		return -EINVAL;
-
-	if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
-	    ptr[1] != 1 ||
-	    ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
-		return -EINVAL;
-
-	if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
+	if (size < HDMI_DRM_INFOFRAME_SIZE)
 		return -EINVAL;
 
 	ret = hdmi_drm_infoframe_init(frame);
 	if (ret)
 		return ret;
 
-	ptr += HDMI_INFOFRAME_HEADER_SIZE;
-
 	frame->eotf = ptr[0] & 0x7;
 	frame->metadata_type = ptr[1] & 0x7;
 
@@ -1837,6 +1825,42 @@ static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
 
 	return 0;
 }
+EXPORT_SYMBOL(hdmi_drm_infoframe_unpack_only);
+
+/**
+ * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
+ * @frame: HDMI DRM infoframe
+ * @buffer: source buffer
+ * @size: size of buffer
+ *
+ * Unpacks the information contained in binary @buffer into a structured
+ * @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
+ * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4
+ * specification.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
+				     const void *buffer, size_t size)
+{
+	const u8 *ptr = buffer;
+	int ret;
+
+	if (size < HDMI_INFOFRAME_SIZE(DRM))
+		return -EINVAL;
+
+	if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
+	    ptr[1] != 1 ||
+	    ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
+		return -EINVAL;
+
+	if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
+		return -EINVAL;
+
+	ret = hdmi_drm_infoframe_unpack_only(frame, ptr + HDMI_INFOFRAME_HEADER_SIZE,
+					     size - HDMI_INFOFRAME_HEADER_SIZE);
+	return ret;
+}
 
 /**
  * hdmi_infoframe_unpack() - unpack binary buffer to a HDMI infoframe
diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
index 9918a6c910c5..afb43efc03e0 100644
--- a/include/linux/hdmi.h
+++ b/include/linux/hdmi.h
@@ -219,6 +219,8 @@ ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe *frame, void *buffer,
 ssize_t hdmi_drm_infoframe_pack_only(const struct hdmi_drm_infoframe *frame,
 				     void *buffer, size_t size);
 int hdmi_drm_infoframe_check(struct hdmi_drm_infoframe *frame);
+int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
+				   const void *buffer, size_t size);
 
 enum hdmi_spd_sdi {
 	HDMI_SPD_SDI_UNKNOWN,
-- 
2.24.1

[PATCH v3 05/17] video/hdmi: Add Unpack only function for DRM infoframe

[Gwan-gyeong Mun]

It adds an unpack only function for DRM infoframe for dynamic range and
mastering infoframe readout.
It unpacks the information data block contained in the binary buffer into
a structured frame of the HDMI Dynamic Range and Mastering (DRM)
information frame.

In contrast to hdmi_drm_infoframe_unpack() function, it does not verify
a checksum.

It can be used for unpacking a DP HDR Metadata Infoframe SDP case.
DP HDR Metadata Infoframe SDP uses the same Dynamic Range and Mastering
(DRM) information (CTA-861-G spec.) such as HDMI DRM infoframe.
But DP SDP header and payload structure are different from HDMI DRM
Infoframe. Therefore unpacking DRM infoframe for DP requires skipping of
a verifying checksum.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/video/hdmi.c | 58 +++++++++++++++++++++++++++++++-------------
 include/linux/hdmi.h |  2 ++
 2 files changed, 43 insertions(+), 17 deletions(-)

diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 9c82e2a0a411..9818836d82b7 100644
--- a/drivers/video/hdmi.c
+++ b/drivers/video/hdmi.c
@@ -1775,20 +1775,18 @@ hdmi_vendor_any_infoframe_unpack(union hdmi_vendor_any_infoframe *frame,
 }
 
 /**
- * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
+ * hdmi_drm_infoframe_unpack_only() - unpack binary buffer to a HDMI DRM infoframe
  * @frame: HDMI DRM infoframe
  * @buffer: source buffer
  * @size: size of buffer
  *
- * Unpacks the information contained in binary @buffer into a structured
+ * Unpacks the information data block contained in binary @buffer into a structured
  * @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
- * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4
- * specification.
  *
  * Returns 0 on success or a negative error code on failure.
  */
-static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
-				     const void *buffer, size_t size)
+int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
+				   const void *buffer, size_t size)
 {
 	const u8 *ptr = buffer;
 	const u8 *temp;
@@ -1797,23 +1795,13 @@ static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
 	int ret;
 	int i;
 
-	if (size < HDMI_INFOFRAME_SIZE(DRM))
-		return -EINVAL;
-
-	if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
-	    ptr[1] != 1 ||
-	    ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
-		return -EINVAL;
-
-	if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
+	if (size < HDMI_DRM_INFOFRAME_SIZE)
 		return -EINVAL;
 
 	ret = hdmi_drm_infoframe_init(frame);
 	if (ret)
 		return ret;
 
-	ptr += HDMI_INFOFRAME_HEADER_SIZE;
-
 	frame->eotf = ptr[0] & 0x7;
 	frame->metadata_type = ptr[1] & 0x7;
 
@@ -1837,6 +1825,42 @@ static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
 
 	return 0;
 }
+EXPORT_SYMBOL(hdmi_drm_infoframe_unpack_only);
+
+/**
+ * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
+ * @frame: HDMI DRM infoframe
+ * @buffer: source buffer
+ * @size: size of buffer
+ *
+ * Unpacks the information contained in binary @buffer into a structured
+ * @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
+ * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4
+ * specification.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
+				     const void *buffer, size_t size)
+{
+	const u8 *ptr = buffer;
+	int ret;
+
+	if (size < HDMI_INFOFRAME_SIZE(DRM))
+		return -EINVAL;
+
+	if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
+	    ptr[1] != 1 ||
+	    ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
+		return -EINVAL;
+
+	if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
+		return -EINVAL;
+
+	ret = hdmi_drm_infoframe_unpack_only(frame, ptr + HDMI_INFOFRAME_HEADER_SIZE,
+					     size - HDMI_INFOFRAME_HEADER_SIZE);
+	return ret;
+}
 
 /**
  * hdmi_infoframe_unpack() - unpack binary buffer to a HDMI infoframe
diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
index 9918a6c910c5..afb43efc03e0 100644
--- a/include/linux/hdmi.h
+++ b/include/linux/hdmi.h
@@ -219,6 +219,8 @@ ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe *frame, void *buffer,
 ssize_t hdmi_drm_infoframe_pack_only(const struct hdmi_drm_infoframe *frame,
 				     void *buffer, size_t size);
 int hdmi_drm_infoframe_check(struct hdmi_drm_infoframe *frame);
+int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
+				   const void *buffer, size_t size);
 
 enum hdmi_spd_sdi {
 	HDMI_SPD_SDI_UNKNOWN,
-- 
2.24.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[Intel-gfx] [PATCH v3 05/17] video/hdmi: Add Unpack only function for DRM infoframe

[Gwan-gyeong Mun]

It adds an unpack only function for DRM infoframe for dynamic range and
mastering infoframe readout.
It unpacks the information data block contained in the binary buffer into
a structured frame of the HDMI Dynamic Range and Mastering (DRM)
information frame.

In contrast to hdmi_drm_infoframe_unpack() function, it does not verify
a checksum.

It can be used for unpacking a DP HDR Metadata Infoframe SDP case.
DP HDR Metadata Infoframe SDP uses the same Dynamic Range and Mastering
(DRM) information (CTA-861-G spec.) such as HDMI DRM infoframe.
But DP SDP header and payload structure are different from HDMI DRM
Infoframe. Therefore unpacking DRM infoframe for DP requires skipping of
a verifying checksum.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/video/hdmi.c | 58 +++++++++++++++++++++++++++++++-------------
 include/linux/hdmi.h |  2 ++
 2 files changed, 43 insertions(+), 17 deletions(-)

diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 9c82e2a0a411..9818836d82b7 100644
--- a/drivers/video/hdmi.c
+++ b/drivers/video/hdmi.c
@@ -1775,20 +1775,18 @@ hdmi_vendor_any_infoframe_unpack(union hdmi_vendor_any_infoframe *frame,
 }
 
 /**
- * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
+ * hdmi_drm_infoframe_unpack_only() - unpack binary buffer to a HDMI DRM infoframe
  * @frame: HDMI DRM infoframe
  * @buffer: source buffer
  * @size: size of buffer
  *
- * Unpacks the information contained in binary @buffer into a structured
+ * Unpacks the information data block contained in binary @buffer into a structured
  * @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
- * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4
- * specification.
  *
  * Returns 0 on success or a negative error code on failure.
  */
-static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
-				     const void *buffer, size_t size)
+int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
+				   const void *buffer, size_t size)
 {
 	const u8 *ptr = buffer;
 	const u8 *temp;
@@ -1797,23 +1795,13 @@ static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
 	int ret;
 	int i;
 
-	if (size < HDMI_INFOFRAME_SIZE(DRM))
-		return -EINVAL;
-
-	if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
-	    ptr[1] != 1 ||
-	    ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
-		return -EINVAL;
-
-	if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
+	if (size < HDMI_DRM_INFOFRAME_SIZE)
 		return -EINVAL;
 
 	ret = hdmi_drm_infoframe_init(frame);
 	if (ret)
 		return ret;
 
-	ptr += HDMI_INFOFRAME_HEADER_SIZE;
-
 	frame->eotf = ptr[0] & 0x7;
 	frame->metadata_type = ptr[1] & 0x7;
 
@@ -1837,6 +1825,42 @@ static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
 
 	return 0;
 }
+EXPORT_SYMBOL(hdmi_drm_infoframe_unpack_only);
+
+/**
+ * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
+ * @frame: HDMI DRM infoframe
+ * @buffer: source buffer
+ * @size: size of buffer
+ *
+ * Unpacks the information contained in binary @buffer into a structured
+ * @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
+ * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4
+ * specification.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
+				     const void *buffer, size_t size)
+{
+	const u8 *ptr = buffer;
+	int ret;
+
+	if (size < HDMI_INFOFRAME_SIZE(DRM))
+		return -EINVAL;
+
+	if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
+	    ptr[1] != 1 ||
+	    ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
+		return -EINVAL;
+
+	if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
+		return -EINVAL;
+
+	ret = hdmi_drm_infoframe_unpack_only(frame, ptr + HDMI_INFOFRAME_HEADER_SIZE,
+					     size - HDMI_INFOFRAME_HEADER_SIZE);
+	return ret;
+}
 
 /**
  * hdmi_infoframe_unpack() - unpack binary buffer to a HDMI infoframe
diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
index 9918a6c910c5..afb43efc03e0 100644
--- a/include/linux/hdmi.h
+++ b/include/linux/hdmi.h
@@ -219,6 +219,8 @@ ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe *frame, void *buffer,
 ssize_t hdmi_drm_infoframe_pack_only(const struct hdmi_drm_infoframe *frame,
 				     void *buffer, size_t size);
 int hdmi_drm_infoframe_check(struct hdmi_drm_infoframe *frame);
+int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
+				   const void *buffer, size_t size);
 
 enum hdmi_spd_sdi {
 	HDMI_SPD_SDI_UNKNOWN,
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 06/17] drm/i915/dp: Read out DP SDPs (Secondary Data Packet)

[Gwan-gyeong Mun]

It adds code to read the DP SDPs from the video DIP and unpack them into
the crtc state.

It adds routines that read out DP VSC SDP and DP HDR Metadata Infoframe SDP
In order to unpack DP VSC SDP, it adds intel_dp_vsc_sdp_unpack() function.
It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and
[Table 2-117: VSC SDP Payload for DB16 through DB18]

In order to unpack DP HDR Metadata Infoframe SDP, it adds
intel_dp_hdr_metadata_infoframe_sdp_unpack(). And it follows DP 1.4a spec.
([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and
[Table 2-126: INFOFRAME SDP v1.2 Payload Data Bytes - DB0 through DB31])
and CTA-861-G spec. [Table-42 Dynamic Range and Mastering InfoFrame].

A nameing rule and style of intel_read_dp_sdp() function references
intel_read_infoframe() function of intel_hdmi.c

v2: Minor style fix
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 170 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h |   3 +
 2 files changed, 173 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index dd7e5588001e..d4ece0a824c0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4925,6 +4925,176 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
 	intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
 }
 
+static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
+				   const void *buffer, size_t size)
+{
+	const struct dp_sdp *sdp = buffer;
+
+	if (size < sizeof(struct dp_sdp))
+		return -EINVAL;
+
+	memset(vsc, 0, size);
+
+	if (sdp->sdp_header.HB0 != 0)
+		return -EINVAL;
+
+	if (sdp->sdp_header.HB1 != DP_SDP_VSC)
+		return -EINVAL;
+	vsc->sdp_type = sdp->sdp_header.HB1;
+
+	if (sdp->sdp_header.HB2 = 0x2 && sdp->sdp_header.HB3 = 0x8) {
+		vsc->revision = sdp->sdp_header.HB2;
+		vsc->length = sdp->sdp_header.HB3;
+	} else if (sdp->sdp_header.HB2 = 0x4 && sdp->sdp_header.HB3 = 0xe) {
+		vsc->revision = sdp->sdp_header.HB2;
+		vsc->length = sdp->sdp_header.HB3;
+	} else if (sdp->sdp_header.HB2 = 0x5 && sdp->sdp_header.HB3 = 0x13) {
+		vsc->revision = sdp->sdp_header.HB2;
+		vsc->length = sdp->sdp_header.HB3;
+		vsc->colorspace = (sdp->db[16] >> 4) & 0xf;
+		vsc->colorimetry = sdp->db[16] & 0xf;
+		vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
+
+		switch (sdp->db[17] & 0x7) {
+		case 0x1:
+			vsc->bpc = 8;
+			break;
+		case 0x2:
+			vsc->bpc = 10;
+			break;
+		case 0x3:
+			vsc->bpc = 12;
+			break;
+		case 0x4:
+			vsc->bpc = 16;
+			break;
+		default:
+			MISSING_CASE(sdp->db[17] & 0x7);
+			return -EINVAL;
+		}
+
+		vsc->content_type = sdp->db[18] & 0x7;
+	} else {
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int
+intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
+					   const void *buffer, size_t size)
+{
+	int ret;
+
+	const struct dp_sdp *sdp = buffer;
+
+	if (size < sizeof(struct dp_sdp))
+		return -EINVAL;
+
+	if (sdp->sdp_header.HB0 != 0)
+		return -EINVAL;
+
+	if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
+		return -EINVAL;
+
+	/*
+	 * Least Significant Eight Bits of (Data Byte Count – 1)
+	 * 1Dh (i.e., Data Byte Count = 30 bytes).
+	 */
+	if (sdp->sdp_header.HB2 != 0x1D)
+		return -EINVAL;
+
+	/* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
+	if ((sdp->sdp_header.HB3 & 0x3) != 0)
+		return -EINVAL;
+
+	/* INFOFRAME SDP Version Number */
+	if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
+		return -EINVAL;
+
+	/* CTA Header Byte 2 (INFOFRAME Version Number) */
+	if (sdp->db[0] != 1)
+		return -EINVAL;
+
+	/* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
+	if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
+		return -EINVAL;
+
+	ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
+					     HDMI_DRM_INFOFRAME_SIZE);
+
+	return ret;
+}
+
+static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
+				  struct intel_crtc_state *crtc_state,
+				  struct drm_dp_vsc_sdp *vsc)
+{
+	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	unsigned int type = DP_SDP_VSC;
+	struct dp_sdp sdp = {};
+	int ret;
+
+	/* When PSR is enabled, VSC SDP is handled by PSR routine */
+	if (intel_psr_enabled(intel_dp))
+		return;
+
+	if ((crtc_state->infoframes.enable &
+	     intel_hdmi_infoframe_enable(type)) = 0)
+		return;
+
+	intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
+
+	ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
+
+	if (ret)
+		DRM_DEBUG_KMS("Failed to unpack DP VSC SDP\n");
+}
+
+static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
+						     struct intel_crtc_state *crtc_state,
+						     struct hdmi_drm_infoframe *drm_infoframe)
+{
+	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+	unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
+	struct dp_sdp sdp = {};
+	int ret;
+
+	if ((crtc_state->infoframes.enable &
+	    intel_hdmi_infoframe_enable(type)) = 0)
+		return;
+
+	intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
+				       sizeof(sdp));
+
+	ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
+							 sizeof(sdp));
+
+	if (ret)
+		DRM_DEBUG_KMS("Failed to unpack DP HDR Metadata Infoframe SDP\n");
+}
+
+void intel_read_dp_sdp(struct intel_encoder *encoder,
+		       struct intel_crtc_state *crtc_state,
+		       unsigned int type)
+{
+	switch (type) {
+	case DP_SDP_VSC:
+		intel_read_dp_vsc_sdp(encoder, crtc_state,
+				      &crtc_state->infoframes.vsc);
+		break;
+	case HDMI_PACKET_TYPE_GAMUT_METADATA:
+		intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
+							 &crtc_state->infoframes.drm.drm);
+		break;
+	default:
+		MISSING_CASE(type);
+		break;
+	}
+}
+
 static void
 intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
 		       const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 0dc09a463ee1..e8f9ba962d09 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -119,6 +119,9 @@ void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
 void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
 			     const struct intel_crtc_state *crtc_state,
 			     const struct drm_connector_state *conn_state);
+void intel_read_dp_sdp(struct intel_encoder *encoder,
+		       struct intel_crtc_state *crtc_state,
+		       unsigned int type);
 bool intel_digital_port_connected(struct intel_encoder *encoder);
 
 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
-- 
2.24.1

[PATCH v3 06/17] drm/i915/dp: Read out DP SDPs (Secondary Data Packet)

[Gwan-gyeong Mun]

It adds code to read the DP SDPs from the video DIP and unpack them into
the crtc state.

It adds routines that read out DP VSC SDP and DP HDR Metadata Infoframe SDP
In order to unpack DP VSC SDP, it adds intel_dp_vsc_sdp_unpack() function.
It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and
[Table 2-117: VSC SDP Payload for DB16 through DB18]

In order to unpack DP HDR Metadata Infoframe SDP, it adds
intel_dp_hdr_metadata_infoframe_sdp_unpack(). And it follows DP 1.4a spec.
([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and
[Table 2-126: INFOFRAME SDP v1.2 Payload Data Bytes - DB0 through DB31])
and CTA-861-G spec. [Table-42 Dynamic Range and Mastering InfoFrame].

A nameing rule and style of intel_read_dp_sdp() function references
intel_read_infoframe() function of intel_hdmi.c

v2: Minor style fix
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 170 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h |   3 +
 2 files changed, 173 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index dd7e5588001e..d4ece0a824c0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4925,6 +4925,176 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
 	intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
 }
 
+static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
+				   const void *buffer, size_t size)
+{
+	const struct dp_sdp *sdp = buffer;
+
+	if (size < sizeof(struct dp_sdp))
+		return -EINVAL;
+
+	memset(vsc, 0, size);
+
+	if (sdp->sdp_header.HB0 != 0)
+		return -EINVAL;
+
+	if (sdp->sdp_header.HB1 != DP_SDP_VSC)
+		return -EINVAL;
+	vsc->sdp_type = sdp->sdp_header.HB1;
+
+	if (sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) {
+		vsc->revision = sdp->sdp_header.HB2;
+		vsc->length = sdp->sdp_header.HB3;
+	} else if (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) {
+		vsc->revision = sdp->sdp_header.HB2;
+		vsc->length = sdp->sdp_header.HB3;
+	} else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
+		vsc->revision = sdp->sdp_header.HB2;
+		vsc->length = sdp->sdp_header.HB3;
+		vsc->colorspace = (sdp->db[16] >> 4) & 0xf;
+		vsc->colorimetry = sdp->db[16] & 0xf;
+		vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
+
+		switch (sdp->db[17] & 0x7) {
+		case 0x1:
+			vsc->bpc = 8;
+			break;
+		case 0x2:
+			vsc->bpc = 10;
+			break;
+		case 0x3:
+			vsc->bpc = 12;
+			break;
+		case 0x4:
+			vsc->bpc = 16;
+			break;
+		default:
+			MISSING_CASE(sdp->db[17] & 0x7);
+			return -EINVAL;
+		}
+
+		vsc->content_type = sdp->db[18] & 0x7;
+	} else {
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int
+intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
+					   const void *buffer, size_t size)
+{
+	int ret;
+
+	const struct dp_sdp *sdp = buffer;
+
+	if (size < sizeof(struct dp_sdp))
+		return -EINVAL;
+
+	if (sdp->sdp_header.HB0 != 0)
+		return -EINVAL;
+
+	if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
+		return -EINVAL;
+
+	/*
+	 * Least Significant Eight Bits of (Data Byte Count – 1)
+	 * 1Dh (i.e., Data Byte Count = 30 bytes).
+	 */
+	if (sdp->sdp_header.HB2 != 0x1D)
+		return -EINVAL;
+
+	/* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
+	if ((sdp->sdp_header.HB3 & 0x3) != 0)
+		return -EINVAL;
+
+	/* INFOFRAME SDP Version Number */
+	if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
+		return -EINVAL;
+
+	/* CTA Header Byte 2 (INFOFRAME Version Number) */
+	if (sdp->db[0] != 1)
+		return -EINVAL;
+
+	/* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
+	if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
+		return -EINVAL;
+
+	ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
+					     HDMI_DRM_INFOFRAME_SIZE);
+
+	return ret;
+}
+
+static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
+				  struct intel_crtc_state *crtc_state,
+				  struct drm_dp_vsc_sdp *vsc)
+{
+	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	unsigned int type = DP_SDP_VSC;
+	struct dp_sdp sdp = {};
+	int ret;
+
+	/* When PSR is enabled, VSC SDP is handled by PSR routine */
+	if (intel_psr_enabled(intel_dp))
+		return;
+
+	if ((crtc_state->infoframes.enable &
+	     intel_hdmi_infoframe_enable(type)) == 0)
+		return;
+
+	intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
+
+	ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
+
+	if (ret)
+		DRM_DEBUG_KMS("Failed to unpack DP VSC SDP\n");
+}
+
+static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
+						     struct intel_crtc_state *crtc_state,
+						     struct hdmi_drm_infoframe *drm_infoframe)
+{
+	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+	unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
+	struct dp_sdp sdp = {};
+	int ret;
+
+	if ((crtc_state->infoframes.enable &
+	    intel_hdmi_infoframe_enable(type)) == 0)
+		return;
+
+	intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
+				       sizeof(sdp));
+
+	ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
+							 sizeof(sdp));
+
+	if (ret)
+		DRM_DEBUG_KMS("Failed to unpack DP HDR Metadata Infoframe SDP\n");
+}
+
+void intel_read_dp_sdp(struct intel_encoder *encoder,
+		       struct intel_crtc_state *crtc_state,
+		       unsigned int type)
+{
+	switch (type) {
+	case DP_SDP_VSC:
+		intel_read_dp_vsc_sdp(encoder, crtc_state,
+				      &crtc_state->infoframes.vsc);
+		break;
+	case HDMI_PACKET_TYPE_GAMUT_METADATA:
+		intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
+							 &crtc_state->infoframes.drm.drm);
+		break;
+	default:
+		MISSING_CASE(type);
+		break;
+	}
+}
+
 static void
 intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
 		       const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 0dc09a463ee1..e8f9ba962d09 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -119,6 +119,9 @@ void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
 void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
 			     const struct intel_crtc_state *crtc_state,
 			     const struct drm_connector_state *conn_state);
+void intel_read_dp_sdp(struct intel_encoder *encoder,
+		       struct intel_crtc_state *crtc_state,
+		       unsigned int type);
 bool intel_digital_port_connected(struct intel_encoder *encoder);
 
 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
-- 
2.24.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[Intel-gfx] [PATCH v3 06/17] drm/i915/dp: Read out DP SDPs (Secondary Data Packet)

[Gwan-gyeong Mun]

It adds code to read the DP SDPs from the video DIP and unpack them into
the crtc state.

It adds routines that read out DP VSC SDP and DP HDR Metadata Infoframe SDP
In order to unpack DP VSC SDP, it adds intel_dp_vsc_sdp_unpack() function.
It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and
[Table 2-117: VSC SDP Payload for DB16 through DB18]

In order to unpack DP HDR Metadata Infoframe SDP, it adds
intel_dp_hdr_metadata_infoframe_sdp_unpack(). And it follows DP 1.4a spec.
([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and
[Table 2-126: INFOFRAME SDP v1.2 Payload Data Bytes - DB0 through DB31])
and CTA-861-G spec. [Table-42 Dynamic Range and Mastering InfoFrame].

A nameing rule and style of intel_read_dp_sdp() function references
intel_read_infoframe() function of intel_hdmi.c

v2: Minor style fix
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 170 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h |   3 +
 2 files changed, 173 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index dd7e5588001e..d4ece0a824c0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4925,6 +4925,176 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
 	intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
 }
 
+static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
+				   const void *buffer, size_t size)
+{
+	const struct dp_sdp *sdp = buffer;
+
+	if (size < sizeof(struct dp_sdp))
+		return -EINVAL;
+
+	memset(vsc, 0, size);
+
+	if (sdp->sdp_header.HB0 != 0)
+		return -EINVAL;
+
+	if (sdp->sdp_header.HB1 != DP_SDP_VSC)
+		return -EINVAL;
+	vsc->sdp_type = sdp->sdp_header.HB1;
+
+	if (sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) {
+		vsc->revision = sdp->sdp_header.HB2;
+		vsc->length = sdp->sdp_header.HB3;
+	} else if (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) {
+		vsc->revision = sdp->sdp_header.HB2;
+		vsc->length = sdp->sdp_header.HB3;
+	} else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
+		vsc->revision = sdp->sdp_header.HB2;
+		vsc->length = sdp->sdp_header.HB3;
+		vsc->colorspace = (sdp->db[16] >> 4) & 0xf;
+		vsc->colorimetry = sdp->db[16] & 0xf;
+		vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
+
+		switch (sdp->db[17] & 0x7) {
+		case 0x1:
+			vsc->bpc = 8;
+			break;
+		case 0x2:
+			vsc->bpc = 10;
+			break;
+		case 0x3:
+			vsc->bpc = 12;
+			break;
+		case 0x4:
+			vsc->bpc = 16;
+			break;
+		default:
+			MISSING_CASE(sdp->db[17] & 0x7);
+			return -EINVAL;
+		}
+
+		vsc->content_type = sdp->db[18] & 0x7;
+	} else {
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int
+intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
+					   const void *buffer, size_t size)
+{
+	int ret;
+
+	const struct dp_sdp *sdp = buffer;
+
+	if (size < sizeof(struct dp_sdp))
+		return -EINVAL;
+
+	if (sdp->sdp_header.HB0 != 0)
+		return -EINVAL;
+
+	if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
+		return -EINVAL;
+
+	/*
+	 * Least Significant Eight Bits of (Data Byte Count – 1)
+	 * 1Dh (i.e., Data Byte Count = 30 bytes).
+	 */
+	if (sdp->sdp_header.HB2 != 0x1D)
+		return -EINVAL;
+
+	/* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
+	if ((sdp->sdp_header.HB3 & 0x3) != 0)
+		return -EINVAL;
+
+	/* INFOFRAME SDP Version Number */
+	if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
+		return -EINVAL;
+
+	/* CTA Header Byte 2 (INFOFRAME Version Number) */
+	if (sdp->db[0] != 1)
+		return -EINVAL;
+
+	/* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
+	if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
+		return -EINVAL;
+
+	ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
+					     HDMI_DRM_INFOFRAME_SIZE);
+
+	return ret;
+}
+
+static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
+				  struct intel_crtc_state *crtc_state,
+				  struct drm_dp_vsc_sdp *vsc)
+{
+	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	unsigned int type = DP_SDP_VSC;
+	struct dp_sdp sdp = {};
+	int ret;
+
+	/* When PSR is enabled, VSC SDP is handled by PSR routine */
+	if (intel_psr_enabled(intel_dp))
+		return;
+
+	if ((crtc_state->infoframes.enable &
+	     intel_hdmi_infoframe_enable(type)) == 0)
+		return;
+
+	intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
+
+	ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
+
+	if (ret)
+		DRM_DEBUG_KMS("Failed to unpack DP VSC SDP\n");
+}
+
+static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
+						     struct intel_crtc_state *crtc_state,
+						     struct hdmi_drm_infoframe *drm_infoframe)
+{
+	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+	unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
+	struct dp_sdp sdp = {};
+	int ret;
+
+	if ((crtc_state->infoframes.enable &
+	    intel_hdmi_infoframe_enable(type)) == 0)
+		return;
+
+	intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
+				       sizeof(sdp));
+
+	ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
+							 sizeof(sdp));
+
+	if (ret)
+		DRM_DEBUG_KMS("Failed to unpack DP HDR Metadata Infoframe SDP\n");
+}
+
+void intel_read_dp_sdp(struct intel_encoder *encoder,
+		       struct intel_crtc_state *crtc_state,
+		       unsigned int type)
+{
+	switch (type) {
+	case DP_SDP_VSC:
+		intel_read_dp_vsc_sdp(encoder, crtc_state,
+				      &crtc_state->infoframes.vsc);
+		break;
+	case HDMI_PACKET_TYPE_GAMUT_METADATA:
+		intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
+							 &crtc_state->infoframes.drm.drm);
+		break;
+	default:
+		MISSING_CASE(type);
+		break;
+	}
+}
+
 static void
 intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
 		       const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 0dc09a463ee1..e8f9ba962d09 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -119,6 +119,9 @@ void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
 void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
 			     const struct intel_crtc_state *crtc_state,
 			     const struct drm_connector_state *conn_state);
+void intel_read_dp_sdp(struct intel_encoder *encoder,
+		       struct intel_crtc_state *crtc_state,
+		       unsigned int type);
 bool intel_digital_port_connected(struct intel_encoder *encoder);
 
 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 07/17] drm: Add logging function for DP VSC SDP

[Gwan-gyeong Mun]

When receiving video it is very useful to be able to log DP VSC SDP.
This greatly simplifies debugging.

v2: Minor style fix
v3: Move logging functions to drm core [Jani N]

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 174 ++++++++++++++++++++++++++++++++
 include/drm/drm_dp_helper.h     |   3 +
 2 files changed, 177 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 5a103e9b3c86..5e3aef8c32e0 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1395,3 +1395,177 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
 	return num_bpc;
 }
 EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
+
+static const char *dp_colorspace_get_name(enum dp_colorspace colorspace)
+{
+	if (colorspace < 0 || colorspace > DP_COLORSPACE_RESERVED)
+		return "Invalid";
+
+	switch (colorspace) {
+	case DP_COLORSPACE_RGB:
+		return "RGB";
+	case DP_COLORSPACE_YUV444:
+		return "YUV444";
+	case DP_COLORSPACE_YUV422:
+		return "YUV422";
+	case DP_COLORSPACE_YUV420:
+		return "YUV420";
+	case DP_COLORSPACE_Y_ONLY:
+		return "Y_ONLY";
+	case DP_COLORSPACE_RAW:
+		return "RAW";
+	default:
+		return "Reserved";
+	}
+}
+
+static const char *dp_colorimetry_get_name(enum dp_colorspace colorspace,
+					   enum dp_colorimetry colorimetry)
+{
+	if (colorspace < 0 || colorspace > DP_COLORSPACE_RESERVED)
+		return "Invalid";
+
+	switch (colorimetry) {
+	case DP_COLORIMETRY_DEFAULT:
+		switch (colorspace) {
+		case DP_COLORSPACE_RGB:
+			return "sRGB";
+		case DP_COLORSPACE_YUV444:
+		case DP_COLORSPACE_YUV422:
+		case DP_COLORSPACE_YUV420:
+			return "BT.601";
+		case DP_COLORSPACE_Y_ONLY:
+			return "DICOM PS3.14";
+		case DP_COLORSPACE_RAW:
+			return "Custom Color Profile";
+		default:
+			return "Reserved";
+		}
+	case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */
+		switch (colorspace) {
+		case DP_COLORSPACE_RGB:
+			return "Wide Fixed";
+		case DP_COLORSPACE_YUV444:
+		case DP_COLORSPACE_YUV422:
+		case DP_COLORSPACE_YUV420:
+			return "BT.709";
+		default:
+			return "Reserved";
+		}
+	case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */
+		switch (colorspace) {
+		case DP_COLORSPACE_RGB:
+			return "Wide Float";
+		case DP_COLORSPACE_YUV444:
+		case DP_COLORSPACE_YUV422:
+		case DP_COLORSPACE_YUV420:
+			return "xvYCC 601";
+		default:
+			return "Reserved";
+		}
+	case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
+		switch (colorspace) {
+		case DP_COLORSPACE_RGB:
+			return "OpRGB";
+		case DP_COLORSPACE_YUV444:
+		case DP_COLORSPACE_YUV422:
+		case DP_COLORSPACE_YUV420:
+			return "xvYCC 709";
+		default:
+			return "Reserved";
+		}
+	case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */
+		switch (colorspace) {
+		case DP_COLORSPACE_RGB:
+			return "DCI-P3";
+		case DP_COLORSPACE_YUV444:
+		case DP_COLORSPACE_YUV422:
+		case DP_COLORSPACE_YUV420:
+			return "sYCC 601";
+		default:
+			return "Reserved";
+		}
+	case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */
+		switch (colorspace) {
+		case DP_COLORSPACE_RGB:
+			return "Custom Profile";
+		case DP_COLORSPACE_YUV444:
+		case DP_COLORSPACE_YUV422:
+		case DP_COLORSPACE_YUV420:
+			return "OpYCC 601";
+		default:
+			return "Reserved";
+		}
+	case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */
+		switch (colorspace) {
+		case DP_COLORSPACE_RGB:
+			return "BT.2020 RGB";
+		case DP_COLORSPACE_YUV444:
+		case DP_COLORSPACE_YUV422:
+		case DP_COLORSPACE_YUV420:
+			return "BT.2020 CYCC";
+		default:
+			return "Reserved";
+		}
+	case DP_COLORIMETRY_BT2020_YCC:
+		switch (colorspace) {
+		case DP_COLORSPACE_YUV444:
+		case DP_COLORSPACE_YUV422:
+		case DP_COLORSPACE_YUV420:
+			return "BT.2020 YCC";
+		default:
+			return "Reserved";
+		}
+	default:
+		return "Invalid";
+	}
+}
+
+static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range)
+{
+	switch (dynamic_range) {
+	case DP_DYNAMIC_RANGE_VESA:
+		return "VESA range";
+	case DP_DYNAMIC_RANGE_CTA:
+		return "CTA range";
+	default:
+		return "Invalid";
+	}
+}
+
+static const char *dp_content_type_get_name(enum dp_content_type content_type)
+{
+	switch (content_type) {
+	case DP_CONTENT_TYPE_NOT_DEFINED:
+		return "Not defined";
+	case DP_CONTENT_TYPE_GRAPHICS:
+		return "Graphics";
+	case DP_CONTENT_TYPE_PHOTO:
+		return "Photo";
+	case DP_CONTENT_TYPE_VIDEO:
+		return "Video";
+	case DP_CONTENT_TYPE_GAME:
+		return "Game";
+	default:
+		return "Reserved";
+	}
+}
+
+void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
+			const struct drm_dp_vsc_sdp *vsc)
+{
+#define DP_SDP_LOG(fmt, ...) dev_printk(level, dev, fmt, ##__VA_ARGS__)
+	DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC",
+		   vsc->revision, vsc->length);
+	DP_SDP_LOG("    colorspace: %s\n",
+		   dp_colorspace_get_name(vsc->colorspace));
+	DP_SDP_LOG("    colorimetry: %s\n",
+		   dp_colorimetry_get_name(vsc->colorspace, vsc->colorimetry));
+	DP_SDP_LOG("    bpc: %u\n", vsc->bpc);
+	DP_SDP_LOG("    dynamic range: %s\n",
+		   dp_dynamic_range_get_name(vsc->dynamic_range));
+	DP_SDP_LOG("    content type: %s\n",
+		   dp_content_type_get_name(vsc->content_type));
+#undef DP_SDP_LOG
+}
+EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index c098727681fa..00b775df6241 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1266,6 +1266,9 @@ struct drm_dp_vsc_sdp {
 	enum dp_content_type content_type;
 };
 
+void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
+			const struct drm_dp_vsc_sdp *vsc);
+
 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
 
 static inline int
-- 
2.24.1

[PATCH v3 07/17] drm: Add logging function for DP VSC SDP

[Gwan-gyeong Mun]

When receiving video it is very useful to be able to log DP VSC SDP.
This greatly simplifies debugging.

v2: Minor style fix
v3: Move logging functions to drm core [Jani N]

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 174 ++++++++++++++++++++++++++++++++
 include/drm/drm_dp_helper.h     |   3 +
 2 files changed, 177 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 5a103e9b3c86..5e3aef8c32e0 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1395,3 +1395,177 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
 	return num_bpc;
 }
 EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
+
+static const char *dp_colorspace_get_name(enum dp_colorspace colorspace)
+{
+	if (colorspace < 0 || colorspace > DP_COLORSPACE_RESERVED)
+		return "Invalid";
+
+	switch (colorspace) {
+	case DP_COLORSPACE_RGB:
+		return "RGB";
+	case DP_COLORSPACE_YUV444:
+		return "YUV444";
+	case DP_COLORSPACE_YUV422:
+		return "YUV422";
+	case DP_COLORSPACE_YUV420:
+		return "YUV420";
+	case DP_COLORSPACE_Y_ONLY:
+		return "Y_ONLY";
+	case DP_COLORSPACE_RAW:
+		return "RAW";
+	default:
+		return "Reserved";
+	}
+}
+
+static const char *dp_colorimetry_get_name(enum dp_colorspace colorspace,
+					   enum dp_colorimetry colorimetry)
+{
+	if (colorspace < 0 || colorspace > DP_COLORSPACE_RESERVED)
+		return "Invalid";
+
+	switch (colorimetry) {
+	case DP_COLORIMETRY_DEFAULT:
+		switch (colorspace) {
+		case DP_COLORSPACE_RGB:
+			return "sRGB";
+		case DP_COLORSPACE_YUV444:
+		case DP_COLORSPACE_YUV422:
+		case DP_COLORSPACE_YUV420:
+			return "BT.601";
+		case DP_COLORSPACE_Y_ONLY:
+			return "DICOM PS3.14";
+		case DP_COLORSPACE_RAW:
+			return "Custom Color Profile";
+		default:
+			return "Reserved";
+		}
+	case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */
+		switch (colorspace) {
+		case DP_COLORSPACE_RGB:
+			return "Wide Fixed";
+		case DP_COLORSPACE_YUV444:
+		case DP_COLORSPACE_YUV422:
+		case DP_COLORSPACE_YUV420:
+			return "BT.709";
+		default:
+			return "Reserved";
+		}
+	case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */
+		switch (colorspace) {
+		case DP_COLORSPACE_RGB:
+			return "Wide Float";
+		case DP_COLORSPACE_YUV444:
+		case DP_COLORSPACE_YUV422:
+		case DP_COLORSPACE_YUV420:
+			return "xvYCC 601";
+		default:
+			return "Reserved";
+		}
+	case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
+		switch (colorspace) {
+		case DP_COLORSPACE_RGB:
+			return "OpRGB";
+		case DP_COLORSPACE_YUV444:
+		case DP_COLORSPACE_YUV422:
+		case DP_COLORSPACE_YUV420:
+			return "xvYCC 709";
+		default:
+			return "Reserved";
+		}
+	case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */
+		switch (colorspace) {
+		case DP_COLORSPACE_RGB:
+			return "DCI-P3";
+		case DP_COLORSPACE_YUV444:
+		case DP_COLORSPACE_YUV422:
+		case DP_COLORSPACE_YUV420:
+			return "sYCC 601";
+		default:
+			return "Reserved";
+		}
+	case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */
+		switch (colorspace) {
+		case DP_COLORSPACE_RGB:
+			return "Custom Profile";
+		case DP_COLORSPACE_YUV444:
+		case DP_COLORSPACE_YUV422:
+		case DP_COLORSPACE_YUV420:
+			return "OpYCC 601";
+		default:
+			return "Reserved";
+		}
+	case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */
+		switch (colorspace) {
+		case DP_COLORSPACE_RGB:
+			return "BT.2020 RGB";
+		case DP_COLORSPACE_YUV444:
+		case DP_COLORSPACE_YUV422:
+		case DP_COLORSPACE_YUV420:
+			return "BT.2020 CYCC";
+		default:
+			return "Reserved";
+		}
+	case DP_COLORIMETRY_BT2020_YCC:
+		switch (colorspace) {
+		case DP_COLORSPACE_YUV444:
+		case DP_COLORSPACE_YUV422:
+		case DP_COLORSPACE_YUV420:
+			return "BT.2020 YCC";
+		default:
+			return "Reserved";
+		}
+	default:
+		return "Invalid";
+	}
+}
+
+static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range)
+{
+	switch (dynamic_range) {
+	case DP_DYNAMIC_RANGE_VESA:
+		return "VESA range";
+	case DP_DYNAMIC_RANGE_CTA:
+		return "CTA range";
+	default:
+		return "Invalid";
+	}
+}
+
+static const char *dp_content_type_get_name(enum dp_content_type content_type)
+{
+	switch (content_type) {
+	case DP_CONTENT_TYPE_NOT_DEFINED:
+		return "Not defined";
+	case DP_CONTENT_TYPE_GRAPHICS:
+		return "Graphics";
+	case DP_CONTENT_TYPE_PHOTO:
+		return "Photo";
+	case DP_CONTENT_TYPE_VIDEO:
+		return "Video";
+	case DP_CONTENT_TYPE_GAME:
+		return "Game";
+	default:
+		return "Reserved";
+	}
+}
+
+void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
+			const struct drm_dp_vsc_sdp *vsc)
+{
+#define DP_SDP_LOG(fmt, ...) dev_printk(level, dev, fmt, ##__VA_ARGS__)
+	DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC",
+		   vsc->revision, vsc->length);
+	DP_SDP_LOG("    colorspace: %s\n",
+		   dp_colorspace_get_name(vsc->colorspace));
+	DP_SDP_LOG("    colorimetry: %s\n",
+		   dp_colorimetry_get_name(vsc->colorspace, vsc->colorimetry));
+	DP_SDP_LOG("    bpc: %u\n", vsc->bpc);
+	DP_SDP_LOG("    dynamic range: %s\n",
+		   dp_dynamic_range_get_name(vsc->dynamic_range));
+	DP_SDP_LOG("    content type: %s\n",
+		   dp_content_type_get_name(vsc->content_type));
+#undef DP_SDP_LOG
+}
+EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index c098727681fa..00b775df6241 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1266,6 +1266,9 @@ struct drm_dp_vsc_sdp {
 	enum dp_content_type content_type;
 };
 
+void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
+			const struct drm_dp_vsc_sdp *vsc);
+
 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
 
 static inline int
-- 
2.24.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[Intel-gfx] [PATCH v3 07/17] drm: Add logging function for DP VSC SDP

[Gwan-gyeong Mun]

When receiving video it is very useful to be able to log DP VSC SDP.
This greatly simplifies debugging.

v2: Minor style fix
v3: Move logging functions to drm core [Jani N]

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 174 ++++++++++++++++++++++++++++++++
 include/drm/drm_dp_helper.h     |   3 +
 2 files changed, 177 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 5a103e9b3c86..5e3aef8c32e0 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1395,3 +1395,177 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
 	return num_bpc;
 }
 EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
+
+static const char *dp_colorspace_get_name(enum dp_colorspace colorspace)
+{
+	if (colorspace < 0 || colorspace > DP_COLORSPACE_RESERVED)
+		return "Invalid";
+
+	switch (colorspace) {
+	case DP_COLORSPACE_RGB:
+		return "RGB";
+	case DP_COLORSPACE_YUV444:
+		return "YUV444";
+	case DP_COLORSPACE_YUV422:
+		return "YUV422";
+	case DP_COLORSPACE_YUV420:
+		return "YUV420";
+	case DP_COLORSPACE_Y_ONLY:
+		return "Y_ONLY";
+	case DP_COLORSPACE_RAW:
+		return "RAW";
+	default:
+		return "Reserved";
+	}
+}
+
+static const char *dp_colorimetry_get_name(enum dp_colorspace colorspace,
+					   enum dp_colorimetry colorimetry)
+{
+	if (colorspace < 0 || colorspace > DP_COLORSPACE_RESERVED)
+		return "Invalid";
+
+	switch (colorimetry) {
+	case DP_COLORIMETRY_DEFAULT:
+		switch (colorspace) {
+		case DP_COLORSPACE_RGB:
+			return "sRGB";
+		case DP_COLORSPACE_YUV444:
+		case DP_COLORSPACE_YUV422:
+		case DP_COLORSPACE_YUV420:
+			return "BT.601";
+		case DP_COLORSPACE_Y_ONLY:
+			return "DICOM PS3.14";
+		case DP_COLORSPACE_RAW:
+			return "Custom Color Profile";
+		default:
+			return "Reserved";
+		}
+	case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */
+		switch (colorspace) {
+		case DP_COLORSPACE_RGB:
+			return "Wide Fixed";
+		case DP_COLORSPACE_YUV444:
+		case DP_COLORSPACE_YUV422:
+		case DP_COLORSPACE_YUV420:
+			return "BT.709";
+		default:
+			return "Reserved";
+		}
+	case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */
+		switch (colorspace) {
+		case DP_COLORSPACE_RGB:
+			return "Wide Float";
+		case DP_COLORSPACE_YUV444:
+		case DP_COLORSPACE_YUV422:
+		case DP_COLORSPACE_YUV420:
+			return "xvYCC 601";
+		default:
+			return "Reserved";
+		}
+	case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
+		switch (colorspace) {
+		case DP_COLORSPACE_RGB:
+			return "OpRGB";
+		case DP_COLORSPACE_YUV444:
+		case DP_COLORSPACE_YUV422:
+		case DP_COLORSPACE_YUV420:
+			return "xvYCC 709";
+		default:
+			return "Reserved";
+		}
+	case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */
+		switch (colorspace) {
+		case DP_COLORSPACE_RGB:
+			return "DCI-P3";
+		case DP_COLORSPACE_YUV444:
+		case DP_COLORSPACE_YUV422:
+		case DP_COLORSPACE_YUV420:
+			return "sYCC 601";
+		default:
+			return "Reserved";
+		}
+	case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */
+		switch (colorspace) {
+		case DP_COLORSPACE_RGB:
+			return "Custom Profile";
+		case DP_COLORSPACE_YUV444:
+		case DP_COLORSPACE_YUV422:
+		case DP_COLORSPACE_YUV420:
+			return "OpYCC 601";
+		default:
+			return "Reserved";
+		}
+	case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */
+		switch (colorspace) {
+		case DP_COLORSPACE_RGB:
+			return "BT.2020 RGB";
+		case DP_COLORSPACE_YUV444:
+		case DP_COLORSPACE_YUV422:
+		case DP_COLORSPACE_YUV420:
+			return "BT.2020 CYCC";
+		default:
+			return "Reserved";
+		}
+	case DP_COLORIMETRY_BT2020_YCC:
+		switch (colorspace) {
+		case DP_COLORSPACE_YUV444:
+		case DP_COLORSPACE_YUV422:
+		case DP_COLORSPACE_YUV420:
+			return "BT.2020 YCC";
+		default:
+			return "Reserved";
+		}
+	default:
+		return "Invalid";
+	}
+}
+
+static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range)
+{
+	switch (dynamic_range) {
+	case DP_DYNAMIC_RANGE_VESA:
+		return "VESA range";
+	case DP_DYNAMIC_RANGE_CTA:
+		return "CTA range";
+	default:
+		return "Invalid";
+	}
+}
+
+static const char *dp_content_type_get_name(enum dp_content_type content_type)
+{
+	switch (content_type) {
+	case DP_CONTENT_TYPE_NOT_DEFINED:
+		return "Not defined";
+	case DP_CONTENT_TYPE_GRAPHICS:
+		return "Graphics";
+	case DP_CONTENT_TYPE_PHOTO:
+		return "Photo";
+	case DP_CONTENT_TYPE_VIDEO:
+		return "Video";
+	case DP_CONTENT_TYPE_GAME:
+		return "Game";
+	default:
+		return "Reserved";
+	}
+}
+
+void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
+			const struct drm_dp_vsc_sdp *vsc)
+{
+#define DP_SDP_LOG(fmt, ...) dev_printk(level, dev, fmt, ##__VA_ARGS__)
+	DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC",
+		   vsc->revision, vsc->length);
+	DP_SDP_LOG("    colorspace: %s\n",
+		   dp_colorspace_get_name(vsc->colorspace));
+	DP_SDP_LOG("    colorimetry: %s\n",
+		   dp_colorimetry_get_name(vsc->colorspace, vsc->colorimetry));
+	DP_SDP_LOG("    bpc: %u\n", vsc->bpc);
+	DP_SDP_LOG("    dynamic range: %s\n",
+		   dp_dynamic_range_get_name(vsc->dynamic_range));
+	DP_SDP_LOG("    content type: %s\n",
+		   dp_content_type_get_name(vsc->content_type));
+#undef DP_SDP_LOG
+}
+EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index c098727681fa..00b775df6241 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1266,6 +1266,9 @@ struct drm_dp_vsc_sdp {
 	enum dp_content_type content_type;
 };
 
+void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
+			const struct drm_dp_vsc_sdp *vsc);
+
 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
 
 static inline int
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 08/17] drm/i915: Include HDMI DRM infoframe in the crtc state dump

[Gwan-gyeong Mun]

Dump out the HDMI Dynamic Range and Mastering (DRM) infoframe in the
normal crtc state dump.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c0e5002ce64c..239861bcedba 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13030,6 +13030,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
 	if (pipe_config->infoframes.enable &
 	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
 		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
+	if (pipe_config->infoframes.enable &
+	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
+		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
 
 	drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
 	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
-- 
2.24.1

[PATCH v3 08/17] drm/i915: Include HDMI DRM infoframe in the crtc state dump

[Gwan-gyeong Mun]

Dump out the HDMI Dynamic Range and Mastering (DRM) infoframe in the
normal crtc state dump.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c0e5002ce64c..239861bcedba 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13030,6 +13030,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
 	if (pipe_config->infoframes.enable &
 	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
 		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
+	if (pipe_config->infoframes.enable &
+	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
+		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
 
 	drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
 	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
-- 
2.24.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[Intel-gfx] [PATCH v3 08/17] drm/i915: Include HDMI DRM infoframe in the crtc state dump

[Gwan-gyeong Mun]

Dump out the HDMI Dynamic Range and Mastering (DRM) infoframe in the
normal crtc state dump.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c0e5002ce64c..239861bcedba 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13030,6 +13030,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
 	if (pipe_config->infoframes.enable &
 	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
 		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
+	if (pipe_config->infoframes.enable &
+	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
+		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
 
 	drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
 	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 09/17] drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump

[Gwan-gyeong Mun]

Dump out the DP HDR Metadata Infoframe SDP in the normal crtc state dump.

HDMI Dynamic Range and Mastering (DRM) infoframe and DP HDR Metadata
Infoframe SDP use the same member variable in infoframes of crtc state.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 239861bcedba..593c63f51210 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13033,6 +13033,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
 	if (pipe_config->infoframes.enable &
 	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
 		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
+	if (pipe_config->infoframes.enable &
+	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
+		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
 
 	drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
 	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
-- 
2.24.1

[PATCH v3 09/17] drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump

[Gwan-gyeong Mun]

Dump out the DP HDR Metadata Infoframe SDP in the normal crtc state dump.

HDMI Dynamic Range and Mastering (DRM) infoframe and DP HDR Metadata
Infoframe SDP use the same member variable in infoframes of crtc state.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 239861bcedba..593c63f51210 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13033,6 +13033,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
 	if (pipe_config->infoframes.enable &
 	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
 		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
+	if (pipe_config->infoframes.enable &
+	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
+		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
 
 	drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
 	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
-- 
2.24.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[Intel-gfx] [PATCH v3 09/17] drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump

[Gwan-gyeong Mun]

Dump out the DP HDR Metadata Infoframe SDP in the normal crtc state dump.

HDMI Dynamic Range and Mastering (DRM) infoframe and DP HDR Metadata
Infoframe SDP use the same member variable in infoframes of crtc state.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 239861bcedba..593c63f51210 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13033,6 +13033,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
 	if (pipe_config->infoframes.enable &
 	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
 		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
+	if (pipe_config->infoframes.enable &
+	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
+		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
 
 	drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
 	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 10/17] drm/i915: Include DP VSC SDP in the crtc state dump

[Gwan-gyeong Mun]

Dump out the DP VSC SDP in the normal crtc state dump

v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
    Use drm core's DP VSC SDP logging function

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 593c63f51210..4f187fd330e8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12878,6 +12878,16 @@ intel_dump_infoframe(struct drm_i915_private *dev_priv,
 	hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
 }
 
+static void
+intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
+		      const struct drm_dp_vsc_sdp *vsc)
+{
+	if (!drm_debug_enabled(DRM_UT_KMS))
+		return;
+
+	drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
+}
+
 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
 
 static const char * const output_type_str[] = {
@@ -13036,6 +13046,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
 	if (pipe_config->infoframes.enable &
 	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
 		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
+	if (pipe_config->infoframes.enable &
+	    intel_hdmi_infoframe_enable(DP_SDP_VSC))
+		intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
 
 	drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
 	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
-- 
2.24.1

[PATCH v3 10/17] drm/i915: Include DP VSC SDP in the crtc state dump

[Gwan-gyeong Mun]

Dump out the DP VSC SDP in the normal crtc state dump

v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
    Use drm core's DP VSC SDP logging function

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 593c63f51210..4f187fd330e8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12878,6 +12878,16 @@ intel_dump_infoframe(struct drm_i915_private *dev_priv,
 	hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
 }
 
+static void
+intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
+		      const struct drm_dp_vsc_sdp *vsc)
+{
+	if (!drm_debug_enabled(DRM_UT_KMS))
+		return;
+
+	drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
+}
+
 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
 
 static const char * const output_type_str[] = {
@@ -13036,6 +13046,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
 	if (pipe_config->infoframes.enable &
 	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
 		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
+	if (pipe_config->infoframes.enable &
+	    intel_hdmi_infoframe_enable(DP_SDP_VSC))
+		intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
 
 	drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
 	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
-- 
2.24.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[Intel-gfx] [PATCH v3 10/17] drm/i915: Include DP VSC SDP in the crtc state dump

[Gwan-gyeong Mun]

Dump out the DP VSC SDP in the normal crtc state dump

v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
    Use drm core's DP VSC SDP logging function

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 593c63f51210..4f187fd330e8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12878,6 +12878,16 @@ intel_dump_infoframe(struct drm_i915_private *dev_priv,
 	hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
 }
 
+static void
+intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
+		      const struct drm_dp_vsc_sdp *vsc)
+{
+	if (!drm_debug_enabled(DRM_UT_KMS))
+		return;
+
+	drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
+}
+
 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
 
 static const char * const output_type_str[] = {
@@ -13036,6 +13046,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
 	if (pipe_config->infoframes.enable &
 	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
 		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
+	if (pipe_config->infoframes.enable &
+	    intel_hdmi_infoframe_enable(DP_SDP_VSC))
+		intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
 
 	drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
 	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 11/17] drm/i915: Program DP SDPs with computed configs

[Gwan-gyeong Mun]

In order to use computed config for DP SDPs (DP VSC SDP and DP HDR Metadata
Infoframe SDP), it replaces intel_dp_vsc_enable() function and
intel_dp_hdr_metadata_enable() function to intel_dp_set_infoframes()
function.

Before applying it, routines of program SDP always calculated configs when
they called. And it removes unused functions.

v3: Rebased

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c |   3 +-
 drivers/gpu/drm/i915/display/intel_dp.c  | 226 -----------------------
 drivers/gpu/drm/i915/display/intel_dp.h  |   6 -
 3 files changed, 1 insertion(+), 234 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index c96f629cddc3..374ab6a3757c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3900,8 +3900,7 @@ static void intel_enable_ddi_dp(struct intel_encoder *encoder,
 
 	intel_edp_backlight_on(crtc_state, conn_state);
 	intel_psr_enable(intel_dp, crtc_state);
-	intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
-	intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
+	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
 	intel_edp_drrs_enable(intel_dp, crtc_state);
 
 	if (crtc_state->has_audio)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d4ece0a824c0..cffb77daec96 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5095,232 +5095,6 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
 	}
 }
 
-static void
-intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
-		       const struct intel_crtc_state *crtc_state,
-		       const struct drm_connector_state *conn_state)
-{
-	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
-	struct dp_sdp vsc_sdp = {};
-
-	/* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
-	vsc_sdp.sdp_header.HB0 = 0;
-	vsc_sdp.sdp_header.HB1 = 0x7;
-
-	/*
-	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
-	 * Colorimetry Format indication.
-	 */
-	vsc_sdp.sdp_header.HB2 = 0x5;
-
-	/*
-	 * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
-	 * Colorimetry Format indication (HB2 = 05h).
-	 */
-	vsc_sdp.sdp_header.HB3 = 0x13;
-
-	/* DP 1.4a spec, Table 2-120 */
-	switch (crtc_state->output_format) {
-	case INTEL_OUTPUT_FORMAT_YCBCR444:
-		vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */
-		break;
-	case INTEL_OUTPUT_FORMAT_YCBCR420:
-		vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */
-		break;
-	case INTEL_OUTPUT_FORMAT_RGB:
-	default:
-		/* RGB: DB16[7:4] = 0h */
-		break;
-	}
-
-	switch (conn_state->colorspace) {
-	case DRM_MODE_COLORIMETRY_BT709_YCC:
-		vsc_sdp.db[16] |= 0x1;
-		break;
-	case DRM_MODE_COLORIMETRY_XVYCC_601:
-		vsc_sdp.db[16] |= 0x2;
-		break;
-	case DRM_MODE_COLORIMETRY_XVYCC_709:
-		vsc_sdp.db[16] |= 0x3;
-		break;
-	case DRM_MODE_COLORIMETRY_SYCC_601:
-		vsc_sdp.db[16] |= 0x4;
-		break;
-	case DRM_MODE_COLORIMETRY_OPYCC_601:
-		vsc_sdp.db[16] |= 0x5;
-		break;
-	case DRM_MODE_COLORIMETRY_BT2020_CYCC:
-	case DRM_MODE_COLORIMETRY_BT2020_RGB:
-		vsc_sdp.db[16] |= 0x6;
-		break;
-	case DRM_MODE_COLORIMETRY_BT2020_YCC:
-		vsc_sdp.db[16] |= 0x7;
-		break;
-	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
-	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
-		vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */
-		break;
-	default:
-		/* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */
-
-		/* RGB->YCBCR color conversion uses the BT.709 color space. */
-		if (crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420)
-			vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
-		break;
-	}
-
-	/*
-	 * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
-	 * the following Component Bit Depth values are defined:
-	 * 001b = 8bpc.
-	 * 010b = 10bpc.
-	 * 011b = 12bpc.
-	 * 100b = 16bpc.
-	 */
-	switch (crtc_state->pipe_bpp) {
-	case 24: /* 8bpc */
-		vsc_sdp.db[17] = 0x1;
-		break;
-	case 30: /* 10bpc */
-		vsc_sdp.db[17] = 0x2;
-		break;
-	case 36: /* 12bpc */
-		vsc_sdp.db[17] = 0x3;
-		break;
-	case 48: /* 16bpc */
-		vsc_sdp.db[17] = 0x4;
-		break;
-	default:
-		MISSING_CASE(crtc_state->pipe_bpp);
-		break;
-	}
-
-	/*
-	 * Dynamic Range (Bit 7)
-	 * 0 = VESA range, 1 = CTA range.
-	 * all YCbCr are always limited range
-	 */
-	vsc_sdp.db[17] |= 0x80;
-
-	/*
-	 * Content Type (Bits 2:0)
-	 * 000b = Not defined.
-	 * 001b = Graphics.
-	 * 010b = Photo.
-	 * 011b = Video.
-	 * 100b = Game
-	 * All other values are RESERVED.
-	 * Note: See CTA-861-G for the definition and expected
-	 * processing by a stream sink for the above contect types.
-	 */
-	vsc_sdp.db[18] = 0;
-
-	intel_dig_port->write_infoframe(&intel_dig_port->base,
-			crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
-}
-
-static void
-intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
-					  const struct intel_crtc_state *crtc_state,
-					  const struct drm_connector_state *conn_state)
-{
-	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
-	struct dp_sdp infoframe_sdp = {};
-	struct hdmi_drm_infoframe drm_infoframe = {};
-	const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
-	unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
-	ssize_t len;
-	int ret;
-
-	ret = drm_hdmi_infoframe_set_hdr_metadata(&drm_infoframe, conn_state);
-	if (ret) {
-		DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
-		return;
-	}
-
-	len = hdmi_drm_infoframe_pack_only(&drm_infoframe, buf, sizeof(buf));
-	if (len < 0) {
-		DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
-		return;
-	}
-
-	if (len != infoframe_size) {
-		DRM_DEBUG_KMS("wrong static hdr metadata size\n");
-		return;
-	}
-
-	/*
-	 * Set up the infoframe sdp packet for HDR static metadata.
-	 * Prepare VSC Header for SU as per DP 1.4a spec,
-	 * Table 2-100 and Table 2-101
-	 */
-
-	/* Packet ID, 00h for non-Audio INFOFRAME */
-	infoframe_sdp.sdp_header.HB0 = 0;
-	/*
-	 * Packet Type 80h + Non-audio INFOFRAME Type value
-	 * HDMI_INFOFRAME_TYPE_DRM: 0x87,
-	 */
-	infoframe_sdp.sdp_header.HB1 = drm_infoframe.type;
-	/*
-	 * Least Significant Eight Bits of (Data Byte Count – 1)
-	 * infoframe_size - 1,
-	 */
-	infoframe_sdp.sdp_header.HB2 = 0x1D;
-	/* INFOFRAME SDP Version Number */
-	infoframe_sdp.sdp_header.HB3 = (0x13 << 2);
-	/* CTA Header Byte 2 (INFOFRAME Version Number) */
-	infoframe_sdp.db[0] = drm_infoframe.version;
-	/* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
-	infoframe_sdp.db[1] = drm_infoframe.length;
-	/*
-	 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
-	 * HDMI_INFOFRAME_HEADER_SIZE
-	 */
-	BUILD_BUG_ON(sizeof(infoframe_sdp.db) < HDMI_DRM_INFOFRAME_SIZE + 2);
-	memcpy(&infoframe_sdp.db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
-	       HDMI_DRM_INFOFRAME_SIZE);
-
-	/*
-	 * Size of DP infoframe sdp packet for HDR static metadata is consist of
-	 * - DP SDP Header(struct dp_sdp_header): 4 bytes
-	 * - Two Data Blocks: 2 bytes
-	 *    CTA Header Byte2 (INFOFRAME Version Number)
-	 *    CTA Header Byte3 (Length of INFOFRAME)
-	 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
-	 *
-	 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
-	 * infoframe size. But GEN11+ has larger than that size, write_infoframe
-	 * will pad rest of the size.
-	 */
-	intel_dig_port->write_infoframe(&intel_dig_port->base, crtc_state,
-					HDMI_PACKET_TYPE_GAMUT_METADATA,
-					&infoframe_sdp,
-					sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE);
-}
-
-void intel_dp_vsc_enable(struct intel_dp *intel_dp,
-			 const struct intel_crtc_state *crtc_state,
-			 const struct drm_connector_state *conn_state)
-{
-	if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
-		return;
-
-	intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);
-}
-
-void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
-				  const struct intel_crtc_state *crtc_state,
-				  const struct drm_connector_state *conn_state)
-{
-	if (!conn_state->hdr_output_metadata)
-		return;
-
-	intel_dp_setup_hdr_metadata_infoframe_sdp(intel_dp,
-						  crtc_state,
-						  conn_state);
-}
-
 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
 {
 	int status = 0;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index e8f9ba962d09..6562bb8edeba 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -110,12 +110,6 @@ int intel_dp_link_required(int pixel_clock, int bpp);
 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
 bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
 			    const struct drm_connector_state *conn_state);
-void intel_dp_vsc_enable(struct intel_dp *intel_dp,
-			 const struct intel_crtc_state *crtc_state,
-			 const struct drm_connector_state *conn_state);
-void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
-				  const struct intel_crtc_state *crtc_state,
-				  const struct drm_connector_state *conn_state);
 void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
 			     const struct intel_crtc_state *crtc_state,
 			     const struct drm_connector_state *conn_state);
-- 
2.24.1

[PATCH v3 11/17] drm/i915: Program DP SDPs with computed configs

[Gwan-gyeong Mun]

In order to use computed config for DP SDPs (DP VSC SDP and DP HDR Metadata
Infoframe SDP), it replaces intel_dp_vsc_enable() function and
intel_dp_hdr_metadata_enable() function to intel_dp_set_infoframes()
function.

Before applying it, routines of program SDP always calculated configs when
they called. And it removes unused functions.

v3: Rebased

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c |   3 +-
 drivers/gpu/drm/i915/display/intel_dp.c  | 226 -----------------------
 drivers/gpu/drm/i915/display/intel_dp.h  |   6 -
 3 files changed, 1 insertion(+), 234 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index c96f629cddc3..374ab6a3757c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3900,8 +3900,7 @@ static void intel_enable_ddi_dp(struct intel_encoder *encoder,
 
 	intel_edp_backlight_on(crtc_state, conn_state);
 	intel_psr_enable(intel_dp, crtc_state);
-	intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
-	intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
+	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
 	intel_edp_drrs_enable(intel_dp, crtc_state);
 
 	if (crtc_state->has_audio)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d4ece0a824c0..cffb77daec96 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5095,232 +5095,6 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
 	}
 }
 
-static void
-intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
-		       const struct intel_crtc_state *crtc_state,
-		       const struct drm_connector_state *conn_state)
-{
-	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
-	struct dp_sdp vsc_sdp = {};
-
-	/* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
-	vsc_sdp.sdp_header.HB0 = 0;
-	vsc_sdp.sdp_header.HB1 = 0x7;
-
-	/*
-	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
-	 * Colorimetry Format indication.
-	 */
-	vsc_sdp.sdp_header.HB2 = 0x5;
-
-	/*
-	 * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
-	 * Colorimetry Format indication (HB2 = 05h).
-	 */
-	vsc_sdp.sdp_header.HB3 = 0x13;
-
-	/* DP 1.4a spec, Table 2-120 */
-	switch (crtc_state->output_format) {
-	case INTEL_OUTPUT_FORMAT_YCBCR444:
-		vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */
-		break;
-	case INTEL_OUTPUT_FORMAT_YCBCR420:
-		vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */
-		break;
-	case INTEL_OUTPUT_FORMAT_RGB:
-	default:
-		/* RGB: DB16[7:4] = 0h */
-		break;
-	}
-
-	switch (conn_state->colorspace) {
-	case DRM_MODE_COLORIMETRY_BT709_YCC:
-		vsc_sdp.db[16] |= 0x1;
-		break;
-	case DRM_MODE_COLORIMETRY_XVYCC_601:
-		vsc_sdp.db[16] |= 0x2;
-		break;
-	case DRM_MODE_COLORIMETRY_XVYCC_709:
-		vsc_sdp.db[16] |= 0x3;
-		break;
-	case DRM_MODE_COLORIMETRY_SYCC_601:
-		vsc_sdp.db[16] |= 0x4;
-		break;
-	case DRM_MODE_COLORIMETRY_OPYCC_601:
-		vsc_sdp.db[16] |= 0x5;
-		break;
-	case DRM_MODE_COLORIMETRY_BT2020_CYCC:
-	case DRM_MODE_COLORIMETRY_BT2020_RGB:
-		vsc_sdp.db[16] |= 0x6;
-		break;
-	case DRM_MODE_COLORIMETRY_BT2020_YCC:
-		vsc_sdp.db[16] |= 0x7;
-		break;
-	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
-	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
-		vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */
-		break;
-	default:
-		/* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */
-
-		/* RGB->YCBCR color conversion uses the BT.709 color space. */
-		if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
-			vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
-		break;
-	}
-
-	/*
-	 * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
-	 * the following Component Bit Depth values are defined:
-	 * 001b = 8bpc.
-	 * 010b = 10bpc.
-	 * 011b = 12bpc.
-	 * 100b = 16bpc.
-	 */
-	switch (crtc_state->pipe_bpp) {
-	case 24: /* 8bpc */
-		vsc_sdp.db[17] = 0x1;
-		break;
-	case 30: /* 10bpc */
-		vsc_sdp.db[17] = 0x2;
-		break;
-	case 36: /* 12bpc */
-		vsc_sdp.db[17] = 0x3;
-		break;
-	case 48: /* 16bpc */
-		vsc_sdp.db[17] = 0x4;
-		break;
-	default:
-		MISSING_CASE(crtc_state->pipe_bpp);
-		break;
-	}
-
-	/*
-	 * Dynamic Range (Bit 7)
-	 * 0 = VESA range, 1 = CTA range.
-	 * all YCbCr are always limited range
-	 */
-	vsc_sdp.db[17] |= 0x80;
-
-	/*
-	 * Content Type (Bits 2:0)
-	 * 000b = Not defined.
-	 * 001b = Graphics.
-	 * 010b = Photo.
-	 * 011b = Video.
-	 * 100b = Game
-	 * All other values are RESERVED.
-	 * Note: See CTA-861-G for the definition and expected
-	 * processing by a stream sink for the above contect types.
-	 */
-	vsc_sdp.db[18] = 0;
-
-	intel_dig_port->write_infoframe(&intel_dig_port->base,
-			crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
-}
-
-static void
-intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
-					  const struct intel_crtc_state *crtc_state,
-					  const struct drm_connector_state *conn_state)
-{
-	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
-	struct dp_sdp infoframe_sdp = {};
-	struct hdmi_drm_infoframe drm_infoframe = {};
-	const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
-	unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
-	ssize_t len;
-	int ret;
-
-	ret = drm_hdmi_infoframe_set_hdr_metadata(&drm_infoframe, conn_state);
-	if (ret) {
-		DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
-		return;
-	}
-
-	len = hdmi_drm_infoframe_pack_only(&drm_infoframe, buf, sizeof(buf));
-	if (len < 0) {
-		DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
-		return;
-	}
-
-	if (len != infoframe_size) {
-		DRM_DEBUG_KMS("wrong static hdr metadata size\n");
-		return;
-	}
-
-	/*
-	 * Set up the infoframe sdp packet for HDR static metadata.
-	 * Prepare VSC Header for SU as per DP 1.4a spec,
-	 * Table 2-100 and Table 2-101
-	 */
-
-	/* Packet ID, 00h for non-Audio INFOFRAME */
-	infoframe_sdp.sdp_header.HB0 = 0;
-	/*
-	 * Packet Type 80h + Non-audio INFOFRAME Type value
-	 * HDMI_INFOFRAME_TYPE_DRM: 0x87,
-	 */
-	infoframe_sdp.sdp_header.HB1 = drm_infoframe.type;
-	/*
-	 * Least Significant Eight Bits of (Data Byte Count – 1)
-	 * infoframe_size - 1,
-	 */
-	infoframe_sdp.sdp_header.HB2 = 0x1D;
-	/* INFOFRAME SDP Version Number */
-	infoframe_sdp.sdp_header.HB3 = (0x13 << 2);
-	/* CTA Header Byte 2 (INFOFRAME Version Number) */
-	infoframe_sdp.db[0] = drm_infoframe.version;
-	/* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
-	infoframe_sdp.db[1] = drm_infoframe.length;
-	/*
-	 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
-	 * HDMI_INFOFRAME_HEADER_SIZE
-	 */
-	BUILD_BUG_ON(sizeof(infoframe_sdp.db) < HDMI_DRM_INFOFRAME_SIZE + 2);
-	memcpy(&infoframe_sdp.db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
-	       HDMI_DRM_INFOFRAME_SIZE);
-
-	/*
-	 * Size of DP infoframe sdp packet for HDR static metadata is consist of
-	 * - DP SDP Header(struct dp_sdp_header): 4 bytes
-	 * - Two Data Blocks: 2 bytes
-	 *    CTA Header Byte2 (INFOFRAME Version Number)
-	 *    CTA Header Byte3 (Length of INFOFRAME)
-	 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
-	 *
-	 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
-	 * infoframe size. But GEN11+ has larger than that size, write_infoframe
-	 * will pad rest of the size.
-	 */
-	intel_dig_port->write_infoframe(&intel_dig_port->base, crtc_state,
-					HDMI_PACKET_TYPE_GAMUT_METADATA,
-					&infoframe_sdp,
-					sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE);
-}
-
-void intel_dp_vsc_enable(struct intel_dp *intel_dp,
-			 const struct intel_crtc_state *crtc_state,
-			 const struct drm_connector_state *conn_state)
-{
-	if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
-		return;
-
-	intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);
-}
-
-void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
-				  const struct intel_crtc_state *crtc_state,
-				  const struct drm_connector_state *conn_state)
-{
-	if (!conn_state->hdr_output_metadata)
-		return;
-
-	intel_dp_setup_hdr_metadata_infoframe_sdp(intel_dp,
-						  crtc_state,
-						  conn_state);
-}
-
 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
 {
 	int status = 0;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index e8f9ba962d09..6562bb8edeba 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -110,12 +110,6 @@ int intel_dp_link_required(int pixel_clock, int bpp);
 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
 bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
 			    const struct drm_connector_state *conn_state);
-void intel_dp_vsc_enable(struct intel_dp *intel_dp,
-			 const struct intel_crtc_state *crtc_state,
-			 const struct drm_connector_state *conn_state);
-void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
-				  const struct intel_crtc_state *crtc_state,
-				  const struct drm_connector_state *conn_state);
 void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
 			     const struct intel_crtc_state *crtc_state,
 			     const struct drm_connector_state *conn_state);
-- 
2.24.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[Intel-gfx] [PATCH v3 11/17] drm/i915: Program DP SDPs with computed configs

[Gwan-gyeong Mun]

In order to use computed config for DP SDPs (DP VSC SDP and DP HDR Metadata
Infoframe SDP), it replaces intel_dp_vsc_enable() function and
intel_dp_hdr_metadata_enable() function to intel_dp_set_infoframes()
function.

Before applying it, routines of program SDP always calculated configs when
they called. And it removes unused functions.

v3: Rebased

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c |   3 +-
 drivers/gpu/drm/i915/display/intel_dp.c  | 226 -----------------------
 drivers/gpu/drm/i915/display/intel_dp.h  |   6 -
 3 files changed, 1 insertion(+), 234 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index c96f629cddc3..374ab6a3757c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3900,8 +3900,7 @@ static void intel_enable_ddi_dp(struct intel_encoder *encoder,
 
 	intel_edp_backlight_on(crtc_state, conn_state);
 	intel_psr_enable(intel_dp, crtc_state);
-	intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
-	intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
+	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
 	intel_edp_drrs_enable(intel_dp, crtc_state);
 
 	if (crtc_state->has_audio)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d4ece0a824c0..cffb77daec96 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5095,232 +5095,6 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
 	}
 }
 
-static void
-intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
-		       const struct intel_crtc_state *crtc_state,
-		       const struct drm_connector_state *conn_state)
-{
-	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
-	struct dp_sdp vsc_sdp = {};
-
-	/* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
-	vsc_sdp.sdp_header.HB0 = 0;
-	vsc_sdp.sdp_header.HB1 = 0x7;
-
-	/*
-	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
-	 * Colorimetry Format indication.
-	 */
-	vsc_sdp.sdp_header.HB2 = 0x5;
-
-	/*
-	 * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
-	 * Colorimetry Format indication (HB2 = 05h).
-	 */
-	vsc_sdp.sdp_header.HB3 = 0x13;
-
-	/* DP 1.4a spec, Table 2-120 */
-	switch (crtc_state->output_format) {
-	case INTEL_OUTPUT_FORMAT_YCBCR444:
-		vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */
-		break;
-	case INTEL_OUTPUT_FORMAT_YCBCR420:
-		vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */
-		break;
-	case INTEL_OUTPUT_FORMAT_RGB:
-	default:
-		/* RGB: DB16[7:4] = 0h */
-		break;
-	}
-
-	switch (conn_state->colorspace) {
-	case DRM_MODE_COLORIMETRY_BT709_YCC:
-		vsc_sdp.db[16] |= 0x1;
-		break;
-	case DRM_MODE_COLORIMETRY_XVYCC_601:
-		vsc_sdp.db[16] |= 0x2;
-		break;
-	case DRM_MODE_COLORIMETRY_XVYCC_709:
-		vsc_sdp.db[16] |= 0x3;
-		break;
-	case DRM_MODE_COLORIMETRY_SYCC_601:
-		vsc_sdp.db[16] |= 0x4;
-		break;
-	case DRM_MODE_COLORIMETRY_OPYCC_601:
-		vsc_sdp.db[16] |= 0x5;
-		break;
-	case DRM_MODE_COLORIMETRY_BT2020_CYCC:
-	case DRM_MODE_COLORIMETRY_BT2020_RGB:
-		vsc_sdp.db[16] |= 0x6;
-		break;
-	case DRM_MODE_COLORIMETRY_BT2020_YCC:
-		vsc_sdp.db[16] |= 0x7;
-		break;
-	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
-	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
-		vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */
-		break;
-	default:
-		/* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */
-
-		/* RGB->YCBCR color conversion uses the BT.709 color space. */
-		if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
-			vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
-		break;
-	}
-
-	/*
-	 * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
-	 * the following Component Bit Depth values are defined:
-	 * 001b = 8bpc.
-	 * 010b = 10bpc.
-	 * 011b = 12bpc.
-	 * 100b = 16bpc.
-	 */
-	switch (crtc_state->pipe_bpp) {
-	case 24: /* 8bpc */
-		vsc_sdp.db[17] = 0x1;
-		break;
-	case 30: /* 10bpc */
-		vsc_sdp.db[17] = 0x2;
-		break;
-	case 36: /* 12bpc */
-		vsc_sdp.db[17] = 0x3;
-		break;
-	case 48: /* 16bpc */
-		vsc_sdp.db[17] = 0x4;
-		break;
-	default:
-		MISSING_CASE(crtc_state->pipe_bpp);
-		break;
-	}
-
-	/*
-	 * Dynamic Range (Bit 7)
-	 * 0 = VESA range, 1 = CTA range.
-	 * all YCbCr are always limited range
-	 */
-	vsc_sdp.db[17] |= 0x80;
-
-	/*
-	 * Content Type (Bits 2:0)
-	 * 000b = Not defined.
-	 * 001b = Graphics.
-	 * 010b = Photo.
-	 * 011b = Video.
-	 * 100b = Game
-	 * All other values are RESERVED.
-	 * Note: See CTA-861-G for the definition and expected
-	 * processing by a stream sink for the above contect types.
-	 */
-	vsc_sdp.db[18] = 0;
-
-	intel_dig_port->write_infoframe(&intel_dig_port->base,
-			crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
-}
-
-static void
-intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
-					  const struct intel_crtc_state *crtc_state,
-					  const struct drm_connector_state *conn_state)
-{
-	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
-	struct dp_sdp infoframe_sdp = {};
-	struct hdmi_drm_infoframe drm_infoframe = {};
-	const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
-	unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
-	ssize_t len;
-	int ret;
-
-	ret = drm_hdmi_infoframe_set_hdr_metadata(&drm_infoframe, conn_state);
-	if (ret) {
-		DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
-		return;
-	}
-
-	len = hdmi_drm_infoframe_pack_only(&drm_infoframe, buf, sizeof(buf));
-	if (len < 0) {
-		DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
-		return;
-	}
-
-	if (len != infoframe_size) {
-		DRM_DEBUG_KMS("wrong static hdr metadata size\n");
-		return;
-	}
-
-	/*
-	 * Set up the infoframe sdp packet for HDR static metadata.
-	 * Prepare VSC Header for SU as per DP 1.4a spec,
-	 * Table 2-100 and Table 2-101
-	 */
-
-	/* Packet ID, 00h for non-Audio INFOFRAME */
-	infoframe_sdp.sdp_header.HB0 = 0;
-	/*
-	 * Packet Type 80h + Non-audio INFOFRAME Type value
-	 * HDMI_INFOFRAME_TYPE_DRM: 0x87,
-	 */
-	infoframe_sdp.sdp_header.HB1 = drm_infoframe.type;
-	/*
-	 * Least Significant Eight Bits of (Data Byte Count – 1)
-	 * infoframe_size - 1,
-	 */
-	infoframe_sdp.sdp_header.HB2 = 0x1D;
-	/* INFOFRAME SDP Version Number */
-	infoframe_sdp.sdp_header.HB3 = (0x13 << 2);
-	/* CTA Header Byte 2 (INFOFRAME Version Number) */
-	infoframe_sdp.db[0] = drm_infoframe.version;
-	/* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
-	infoframe_sdp.db[1] = drm_infoframe.length;
-	/*
-	 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
-	 * HDMI_INFOFRAME_HEADER_SIZE
-	 */
-	BUILD_BUG_ON(sizeof(infoframe_sdp.db) < HDMI_DRM_INFOFRAME_SIZE + 2);
-	memcpy(&infoframe_sdp.db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
-	       HDMI_DRM_INFOFRAME_SIZE);
-
-	/*
-	 * Size of DP infoframe sdp packet for HDR static metadata is consist of
-	 * - DP SDP Header(struct dp_sdp_header): 4 bytes
-	 * - Two Data Blocks: 2 bytes
-	 *    CTA Header Byte2 (INFOFRAME Version Number)
-	 *    CTA Header Byte3 (Length of INFOFRAME)
-	 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
-	 *
-	 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
-	 * infoframe size. But GEN11+ has larger than that size, write_infoframe
-	 * will pad rest of the size.
-	 */
-	intel_dig_port->write_infoframe(&intel_dig_port->base, crtc_state,
-					HDMI_PACKET_TYPE_GAMUT_METADATA,
-					&infoframe_sdp,
-					sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE);
-}
-
-void intel_dp_vsc_enable(struct intel_dp *intel_dp,
-			 const struct intel_crtc_state *crtc_state,
-			 const struct drm_connector_state *conn_state)
-{
-	if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
-		return;
-
-	intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);
-}
-
-void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
-				  const struct intel_crtc_state *crtc_state,
-				  const struct drm_connector_state *conn_state)
-{
-	if (!conn_state->hdr_output_metadata)
-		return;
-
-	intel_dp_setup_hdr_metadata_infoframe_sdp(intel_dp,
-						  crtc_state,
-						  conn_state);
-}
-
 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
 {
 	int status = 0;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index e8f9ba962d09..6562bb8edeba 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -110,12 +110,6 @@ int intel_dp_link_required(int pixel_clock, int bpp);
 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
 bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
 			    const struct drm_connector_state *conn_state);
-void intel_dp_vsc_enable(struct intel_dp *intel_dp,
-			 const struct intel_crtc_state *crtc_state,
-			 const struct drm_connector_state *conn_state);
-void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
-				  const struct intel_crtc_state *crtc_state,
-				  const struct drm_connector_state *conn_state);
 void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
 			     const struct intel_crtc_state *crtc_state,
 			     const struct drm_connector_state *conn_state);
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 12/17] drm/i915: Add state readout for DP HDR Metadata Infoframe SDP

[Gwan-gyeong Mun]

Added state readout for DP HDR Metadata Infoframe SDP.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 374ab6a3757c..a9eaf7a6bc15 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4322,6 +4322,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 				      pipe_config->fec_enable);
 		}
 
+		pipe_config->infoframes.enable |+			intel_hdmi_infoframes_enabled(encoder, pipe_config);
+
 		break;
 	case TRANS_DDI_MODE_SELECT_DP_MST:
 		pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
@@ -4333,6 +4336,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 					REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
 
 		intel_dp_get_m_n(intel_crtc, pipe_config);
+
+		pipe_config->infoframes.enable |+			intel_hdmi_infoframes_enabled(encoder, pipe_config);
 		break;
 	default:
 		break;
@@ -4383,6 +4389,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 	intel_read_infoframe(encoder, pipe_config,
 			     HDMI_INFOFRAME_TYPE_DRM,
 			     &pipe_config->infoframes.drm);
+
+	intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
 }
 
 static enum intel_output_type
-- 
2.24.1

[PATCH v3 12/17] drm/i915: Add state readout for DP HDR Metadata Infoframe SDP

[Gwan-gyeong Mun]

Added state readout for DP HDR Metadata Infoframe SDP.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 374ab6a3757c..a9eaf7a6bc15 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4322,6 +4322,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 				      pipe_config->fec_enable);
 		}
 
+		pipe_config->infoframes.enable |=
+			intel_hdmi_infoframes_enabled(encoder, pipe_config);
+
 		break;
 	case TRANS_DDI_MODE_SELECT_DP_MST:
 		pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
@@ -4333,6 +4336,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 					REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
 
 		intel_dp_get_m_n(intel_crtc, pipe_config);
+
+		pipe_config->infoframes.enable |=
+			intel_hdmi_infoframes_enabled(encoder, pipe_config);
 		break;
 	default:
 		break;
@@ -4383,6 +4389,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 	intel_read_infoframe(encoder, pipe_config,
 			     HDMI_INFOFRAME_TYPE_DRM,
 			     &pipe_config->infoframes.drm);
+
+	intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
 }
 
 static enum intel_output_type
-- 
2.24.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[Intel-gfx] [PATCH v3 12/17] drm/i915: Add state readout for DP HDR Metadata Infoframe SDP

[Gwan-gyeong Mun]

Added state readout for DP HDR Metadata Infoframe SDP.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 374ab6a3757c..a9eaf7a6bc15 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4322,6 +4322,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 				      pipe_config->fec_enable);
 		}
 
+		pipe_config->infoframes.enable |=
+			intel_hdmi_infoframes_enabled(encoder, pipe_config);
+
 		break;
 	case TRANS_DDI_MODE_SELECT_DP_MST:
 		pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
@@ -4333,6 +4336,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 					REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
 
 		intel_dp_get_m_n(intel_crtc, pipe_config);
+
+		pipe_config->infoframes.enable |=
+			intel_hdmi_infoframes_enabled(encoder, pipe_config);
 		break;
 	default:
 		break;
@@ -4383,6 +4389,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 	intel_read_infoframe(encoder, pipe_config,
 			     HDMI_INFOFRAME_TYPE_DRM,
 			     &pipe_config->infoframes.drm);
+
+	intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
 }
 
 static enum intel_output_type
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 13/17] drm/i915: Add state readout for DP VSC SDP

[Gwan-gyeong Mun]

Added state readout for DP VSC SDP and enabled state validation
for DP VSC SDP.

v2: Minor style fix
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c     |  1 +
 drivers/gpu/drm/i915/display/intel_display.c | 42 ++++++++++++++++++++
 2 files changed, 43 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a9eaf7a6bc15..64e4edefa998 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4391,6 +4391,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 			     &pipe_config->infoframes.drm);
 
 	intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
+	intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
 }
 
 static enum intel_output_type
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4f187fd330e8..02471c7aa6e7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13503,6 +13503,13 @@ intel_compare_infoframe(const union hdmi_infoframe *a,
 	return memcmp(a, b, sizeof(*a)) = 0;
 }
 
+static bool
+intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
+			 const struct drm_dp_vsc_sdp *b)
+{
+	return memcmp(a, b, sizeof(*a)) = 0;
+}
+
 static void
 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
 			       bool fastset, const char *name,
@@ -13528,6 +13535,30 @@ pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
 	}
 }
 
+static void
+pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
+				bool fastset, const char *name,
+				const struct drm_dp_vsc_sdp *a,
+				const struct drm_dp_vsc_sdp *b)
+{
+	if (fastset) {
+		if (!drm_debug_enabled(DRM_UT_KMS))
+			return;
+
+		DRM_DEBUG_KMS("fastset mismatch in %s dp sdp\n", name);
+		DRM_DEBUG_KMS("expected:\n");
+		drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
+		DRM_DEBUG_KMS("found:\n");
+		drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
+	} else {
+		DRM_ERROR("mismatch in %s dp sdp\n", name);
+		DRM_ERROR("expected:\n");
+		drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
+		DRM_ERROR("found:\n");
+		drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
+	}
+}
+
 static void __printf(4, 5)
 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
 		     const char *name, const char *format, ...)
@@ -13729,6 +13760,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	} \
 } while (0)
 
+#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
+	if (!intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
+				      &pipe_config->infoframes.name)) { \
+		pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
+						&current_config->infoframes.name, \
+						&pipe_config->infoframes.name); \
+		ret = false; \
+	} \
+} while (0)
+
 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
 	if (current_config->name1 != pipe_config->name1) { \
 		pipe_config_mismatch(fastset, crtc, __stringify(name1), \
@@ -13902,6 +13943,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	PIPE_CONF_CHECK_INFOFRAME(spd);
 	PIPE_CONF_CHECK_INFOFRAME(hdmi);
 	PIPE_CONF_CHECK_INFOFRAME(drm);
+	PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
 
 	PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
 	PIPE_CONF_CHECK_I(master_transcoder);
-- 
2.24.1

[PATCH v3 13/17] drm/i915: Add state readout for DP VSC SDP

[Gwan-gyeong Mun]

Added state readout for DP VSC SDP and enabled state validation
for DP VSC SDP.

v2: Minor style fix
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c     |  1 +
 drivers/gpu/drm/i915/display/intel_display.c | 42 ++++++++++++++++++++
 2 files changed, 43 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a9eaf7a6bc15..64e4edefa998 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4391,6 +4391,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 			     &pipe_config->infoframes.drm);
 
 	intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
+	intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
 }
 
 static enum intel_output_type
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4f187fd330e8..02471c7aa6e7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13503,6 +13503,13 @@ intel_compare_infoframe(const union hdmi_infoframe *a,
 	return memcmp(a, b, sizeof(*a)) == 0;
 }
 
+static bool
+intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
+			 const struct drm_dp_vsc_sdp *b)
+{
+	return memcmp(a, b, sizeof(*a)) == 0;
+}
+
 static void
 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
 			       bool fastset, const char *name,
@@ -13528,6 +13535,30 @@ pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
 	}
 }
 
+static void
+pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
+				bool fastset, const char *name,
+				const struct drm_dp_vsc_sdp *a,
+				const struct drm_dp_vsc_sdp *b)
+{
+	if (fastset) {
+		if (!drm_debug_enabled(DRM_UT_KMS))
+			return;
+
+		DRM_DEBUG_KMS("fastset mismatch in %s dp sdp\n", name);
+		DRM_DEBUG_KMS("expected:\n");
+		drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
+		DRM_DEBUG_KMS("found:\n");
+		drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
+	} else {
+		DRM_ERROR("mismatch in %s dp sdp\n", name);
+		DRM_ERROR("expected:\n");
+		drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
+		DRM_ERROR("found:\n");
+		drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
+	}
+}
+
 static void __printf(4, 5)
 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
 		     const char *name, const char *format, ...)
@@ -13729,6 +13760,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	} \
 } while (0)
 
+#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
+	if (!intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
+				      &pipe_config->infoframes.name)) { \
+		pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
+						&current_config->infoframes.name, \
+						&pipe_config->infoframes.name); \
+		ret = false; \
+	} \
+} while (0)
+
 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
 	if (current_config->name1 != pipe_config->name1) { \
 		pipe_config_mismatch(fastset, crtc, __stringify(name1), \
@@ -13902,6 +13943,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	PIPE_CONF_CHECK_INFOFRAME(spd);
 	PIPE_CONF_CHECK_INFOFRAME(hdmi);
 	PIPE_CONF_CHECK_INFOFRAME(drm);
+	PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
 
 	PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
 	PIPE_CONF_CHECK_I(master_transcoder);
-- 
2.24.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[Intel-gfx] [PATCH v3 13/17] drm/i915: Add state readout for DP VSC SDP

[Gwan-gyeong Mun]

Added state readout for DP VSC SDP and enabled state validation
for DP VSC SDP.

v2: Minor style fix
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c     |  1 +
 drivers/gpu/drm/i915/display/intel_display.c | 42 ++++++++++++++++++++
 2 files changed, 43 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a9eaf7a6bc15..64e4edefa998 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4391,6 +4391,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 			     &pipe_config->infoframes.drm);
 
 	intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
+	intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
 }
 
 static enum intel_output_type
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4f187fd330e8..02471c7aa6e7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13503,6 +13503,13 @@ intel_compare_infoframe(const union hdmi_infoframe *a,
 	return memcmp(a, b, sizeof(*a)) == 0;
 }
 
+static bool
+intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
+			 const struct drm_dp_vsc_sdp *b)
+{
+	return memcmp(a, b, sizeof(*a)) == 0;
+}
+
 static void
 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
 			       bool fastset, const char *name,
@@ -13528,6 +13535,30 @@ pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
 	}
 }
 
+static void
+pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
+				bool fastset, const char *name,
+				const struct drm_dp_vsc_sdp *a,
+				const struct drm_dp_vsc_sdp *b)
+{
+	if (fastset) {
+		if (!drm_debug_enabled(DRM_UT_KMS))
+			return;
+
+		DRM_DEBUG_KMS("fastset mismatch in %s dp sdp\n", name);
+		DRM_DEBUG_KMS("expected:\n");
+		drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
+		DRM_DEBUG_KMS("found:\n");
+		drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
+	} else {
+		DRM_ERROR("mismatch in %s dp sdp\n", name);
+		DRM_ERROR("expected:\n");
+		drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
+		DRM_ERROR("found:\n");
+		drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
+	}
+}
+
 static void __printf(4, 5)
 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
 		     const char *name, const char *format, ...)
@@ -13729,6 +13760,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	} \
 } while (0)
 
+#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
+	if (!intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
+				      &pipe_config->infoframes.name)) { \
+		pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
+						&current_config->infoframes.name, \
+						&pipe_config->infoframes.name); \
+		ret = false; \
+	} \
+} while (0)
+
 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
 	if (current_config->name1 != pipe_config->name1) { \
 		pipe_config_mismatch(fastset, crtc, __stringify(name1), \
@@ -13902,6 +13943,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	PIPE_CONF_CHECK_INFOFRAME(spd);
 	PIPE_CONF_CHECK_INFOFRAME(hdmi);
 	PIPE_CONF_CHECK_INFOFRAME(drm);
+	PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
 
 	PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
 	PIPE_CONF_CHECK_I(master_transcoder);
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 14/17] drm/i915: Program DP SDPs on pipe updates

[Gwan-gyeong Mun]

Call intel_dp_set_infoframes() function on pipe updates to make sure
that we send VSC SDP and HDR Metadata Infoframe SDP (when applicable)
on fastsets.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 64e4edefa998..69073a15edb8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4062,6 +4062,7 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
 	intel_ddi_set_dp_msa(crtc_state, conn_state);
 
 	intel_psr_update(intel_dp, crtc_state);
+	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
 	intel_edp_drrs_enable(intel_dp, crtc_state);
 
 	intel_panel_update_backlight(encoder, crtc_state, conn_state);
-- 
2.24.1

[PATCH v3 14/17] drm/i915: Program DP SDPs on pipe updates

[Gwan-gyeong Mun]

Call intel_dp_set_infoframes() function on pipe updates to make sure
that we send VSC SDP and HDR Metadata Infoframe SDP (when applicable)
on fastsets.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 64e4edefa998..69073a15edb8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4062,6 +4062,7 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
 	intel_ddi_set_dp_msa(crtc_state, conn_state);
 
 	intel_psr_update(intel_dp, crtc_state);
+	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
 	intel_edp_drrs_enable(intel_dp, crtc_state);
 
 	intel_panel_update_backlight(encoder, crtc_state, conn_state);
-- 
2.24.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[Intel-gfx] [PATCH v3 14/17] drm/i915: Program DP SDPs on pipe updates

[Gwan-gyeong Mun]

Call intel_dp_set_infoframes() function on pipe updates to make sure
that we send VSC SDP and HDR Metadata Infoframe SDP (when applicable)
on fastsets.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 64e4edefa998..69073a15edb8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4062,6 +4062,7 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
 	intel_ddi_set_dp_msa(crtc_state, conn_state);
 
 	intel_psr_update(intel_dp, crtc_state);
+	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
 	intel_edp_drrs_enable(intel_dp, crtc_state);
 
 	intel_panel_update_backlight(encoder, crtc_state, conn_state);
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 15/17] drm/i915: Stop sending DP SDPs on intel_ddi_post_disable_dp()

[Gwan-gyeong Mun]

Call intel_dp_set_infoframes(false) function on intel_ddi_post_disable_dp()
to make sure not to send VSC SDP and HDR Metadata Infoframe SDP.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 69073a15edb8..8509cd33569e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3713,6 +3713,8 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
 					  INTEL_OUTPUT_DP_MST);
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
+	intel_dp_set_infoframes(encoder, false, old_crtc_state, old_conn_state);
+
 	/*
 	 * Power down sink before disabling the port, otherwise we end
 	 * up getting interrupts from the sink on detecting link loss.
-- 
2.24.1

[PATCH v3 15/17] drm/i915: Stop sending DP SDPs on intel_ddi_post_disable_dp()

[Gwan-gyeong Mun]

Call intel_dp_set_infoframes(false) function on intel_ddi_post_disable_dp()
to make sure not to send VSC SDP and HDR Metadata Infoframe SDP.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 69073a15edb8..8509cd33569e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3713,6 +3713,8 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
 					  INTEL_OUTPUT_DP_MST);
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
+	intel_dp_set_infoframes(encoder, false, old_crtc_state, old_conn_state);
+
 	/*
 	 * Power down sink before disabling the port, otherwise we end
 	 * up getting interrupts from the sink on detecting link loss.
-- 
2.24.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[Intel-gfx] [PATCH v3 15/17] drm/i915: Stop sending DP SDPs on intel_ddi_post_disable_dp()

[Gwan-gyeong Mun]

Call intel_dp_set_infoframes(false) function on intel_ddi_post_disable_dp()
to make sure not to send VSC SDP and HDR Metadata Infoframe SDP.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 69073a15edb8..8509cd33569e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3713,6 +3713,8 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
 					  INTEL_OUTPUT_DP_MST);
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
+	intel_dp_set_infoframes(encoder, false, old_crtc_state, old_conn_state);
+
 	/*
 	 * Power down sink before disabling the port, otherwise we end
 	 * up getting interrupts from the sink on detecting link loss.
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 16/17] drm/i915/dp: Add compute routine for DP PSR VSC SDP

[Gwan-gyeong Mun]

In order to use a common VSC SDP Colorimetry calculating code on PSR,
it adds a compute routine for PSR VSC SDP.
As PSR routine can not use infoframes.vsc of crtc state, it also adds new
writing of DP SDPs (Secondary Data Packet) for PSR.
PSR routine has its own scenario and timings of writing a VSC SDP.

v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 53 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h |  8 ++++
 2 files changed, 61 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index cffb77daec96..4d65ef36577f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2463,6 +2463,42 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
 					 &crtc_state->infoframes.vsc);
 }
 
+void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
+				  const struct intel_crtc_state *crtc_state,
+				  const struct drm_connector_state *conn_state,
+				  struct drm_dp_vsc_sdp *vsc)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+	vsc->sdp_type = DP_SDP_VSC;
+
+	if (dev_priv->psr.psr2_enabled) {
+		if (dev_priv->psr.colorimetry_support &&
+		    intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
+			/* [PSR2, +Colorimetry] */
+			intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
+							 vsc);
+		} else {
+			/*
+			 * [PSR2, -Colorimetry]
+			 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
+			 * 3D stereo + PSR/PSR2 + Y-coordinate.
+			 */
+			vsc->revision = 0x4;
+			vsc->length = 0xe;
+		}
+	} else {
+		/*
+		 * [PSR1]
+		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+		 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
+		 * higher).
+		 */
+		vsc->revision = 0x2;
+		vsc->length = 0x8;
+	}
+}
+
 static void
 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_crtc_state *crtc_state,
 					    const struct drm_connector_state *conn_state)
@@ -4889,6 +4925,23 @@ static void intel_write_dp_sdp(struct intel_encoder *encoder,
 	intel_dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
 }
 
+void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
+			    const struct intel_crtc_state *crtc_state,
+			    struct drm_dp_vsc_sdp *vsc)
+{
+	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+	struct dp_sdp sdp = {};
+	ssize_t len;
+
+	len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
+
+	if (WARN_ON(len < 0))
+		return;
+
+	intel_dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
+					&sdp, len);
+}
+
 void intel_dp_set_infoframes(struct intel_encoder *encoder,
 			     bool enable,
 			     const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 6562bb8edeba..5074e52722c0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -18,6 +18,7 @@ struct drm_connector_state;
 struct drm_encoder;
 struct drm_i915_private;
 struct drm_modeset_acquire_ctx;
+struct drm_dp_vsc_sdp;
 struct intel_connector;
 struct intel_crtc_state;
 struct intel_digital_port;
@@ -110,6 +111,13 @@ int intel_dp_link_required(int pixel_clock, int bpp);
 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
 bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
 			    const struct drm_connector_state *conn_state);
+void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
+				  const struct intel_crtc_state *crtc_state,
+				  const struct drm_connector_state *conn_state,
+				  struct drm_dp_vsc_sdp *vsc);
+void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
+			    const struct intel_crtc_state *crtc_state,
+			    struct drm_dp_vsc_sdp *vsc);
 void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
 			     const struct intel_crtc_state *crtc_state,
 			     const struct drm_connector_state *conn_state);
-- 
2.24.1

[PATCH v3 16/17] drm/i915/dp: Add compute routine for DP PSR VSC SDP

[Gwan-gyeong Mun]

In order to use a common VSC SDP Colorimetry calculating code on PSR,
it adds a compute routine for PSR VSC SDP.
As PSR routine can not use infoframes.vsc of crtc state, it also adds new
writing of DP SDPs (Secondary Data Packet) for PSR.
PSR routine has its own scenario and timings of writing a VSC SDP.

v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 53 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h |  8 ++++
 2 files changed, 61 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index cffb77daec96..4d65ef36577f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2463,6 +2463,42 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
 					 &crtc_state->infoframes.vsc);
 }
 
+void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
+				  const struct intel_crtc_state *crtc_state,
+				  const struct drm_connector_state *conn_state,
+				  struct drm_dp_vsc_sdp *vsc)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+	vsc->sdp_type = DP_SDP_VSC;
+
+	if (dev_priv->psr.psr2_enabled) {
+		if (dev_priv->psr.colorimetry_support &&
+		    intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
+			/* [PSR2, +Colorimetry] */
+			intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
+							 vsc);
+		} else {
+			/*
+			 * [PSR2, -Colorimetry]
+			 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
+			 * 3D stereo + PSR/PSR2 + Y-coordinate.
+			 */
+			vsc->revision = 0x4;
+			vsc->length = 0xe;
+		}
+	} else {
+		/*
+		 * [PSR1]
+		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+		 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
+		 * higher).
+		 */
+		vsc->revision = 0x2;
+		vsc->length = 0x8;
+	}
+}
+
 static void
 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_crtc_state *crtc_state,
 					    const struct drm_connector_state *conn_state)
@@ -4889,6 +4925,23 @@ static void intel_write_dp_sdp(struct intel_encoder *encoder,
 	intel_dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
 }
 
+void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
+			    const struct intel_crtc_state *crtc_state,
+			    struct drm_dp_vsc_sdp *vsc)
+{
+	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+	struct dp_sdp sdp = {};
+	ssize_t len;
+
+	len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
+
+	if (WARN_ON(len < 0))
+		return;
+
+	intel_dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
+					&sdp, len);
+}
+
 void intel_dp_set_infoframes(struct intel_encoder *encoder,
 			     bool enable,
 			     const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 6562bb8edeba..5074e52722c0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -18,6 +18,7 @@ struct drm_connector_state;
 struct drm_encoder;
 struct drm_i915_private;
 struct drm_modeset_acquire_ctx;
+struct drm_dp_vsc_sdp;
 struct intel_connector;
 struct intel_crtc_state;
 struct intel_digital_port;
@@ -110,6 +111,13 @@ int intel_dp_link_required(int pixel_clock, int bpp);
 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
 bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
 			    const struct drm_connector_state *conn_state);
+void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
+				  const struct intel_crtc_state *crtc_state,
+				  const struct drm_connector_state *conn_state,
+				  struct drm_dp_vsc_sdp *vsc);
+void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
+			    const struct intel_crtc_state *crtc_state,
+			    struct drm_dp_vsc_sdp *vsc);
 void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
 			     const struct intel_crtc_state *crtc_state,
 			     const struct drm_connector_state *conn_state);
-- 
2.24.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[Intel-gfx] [PATCH v3 16/17] drm/i915/dp: Add compute routine for DP PSR VSC SDP

[Gwan-gyeong Mun]

In order to use a common VSC SDP Colorimetry calculating code on PSR,
it adds a compute routine for PSR VSC SDP.
As PSR routine can not use infoframes.vsc of crtc state, it also adds new
writing of DP SDPs (Secondary Data Packet) for PSR.
PSR routine has its own scenario and timings of writing a VSC SDP.

v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 53 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h |  8 ++++
 2 files changed, 61 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index cffb77daec96..4d65ef36577f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2463,6 +2463,42 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
 					 &crtc_state->infoframes.vsc);
 }
 
+void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
+				  const struct intel_crtc_state *crtc_state,
+				  const struct drm_connector_state *conn_state,
+				  struct drm_dp_vsc_sdp *vsc)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+	vsc->sdp_type = DP_SDP_VSC;
+
+	if (dev_priv->psr.psr2_enabled) {
+		if (dev_priv->psr.colorimetry_support &&
+		    intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
+			/* [PSR2, +Colorimetry] */
+			intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
+							 vsc);
+		} else {
+			/*
+			 * [PSR2, -Colorimetry]
+			 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
+			 * 3D stereo + PSR/PSR2 + Y-coordinate.
+			 */
+			vsc->revision = 0x4;
+			vsc->length = 0xe;
+		}
+	} else {
+		/*
+		 * [PSR1]
+		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+		 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
+		 * higher).
+		 */
+		vsc->revision = 0x2;
+		vsc->length = 0x8;
+	}
+}
+
 static void
 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_crtc_state *crtc_state,
 					    const struct drm_connector_state *conn_state)
@@ -4889,6 +4925,23 @@ static void intel_write_dp_sdp(struct intel_encoder *encoder,
 	intel_dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
 }
 
+void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
+			    const struct intel_crtc_state *crtc_state,
+			    struct drm_dp_vsc_sdp *vsc)
+{
+	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+	struct dp_sdp sdp = {};
+	ssize_t len;
+
+	len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
+
+	if (WARN_ON(len < 0))
+		return;
+
+	intel_dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
+					&sdp, len);
+}
+
 void intel_dp_set_infoframes(struct intel_encoder *encoder,
 			     bool enable,
 			     const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 6562bb8edeba..5074e52722c0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -18,6 +18,7 @@ struct drm_connector_state;
 struct drm_encoder;
 struct drm_i915_private;
 struct drm_modeset_acquire_ctx;
+struct drm_dp_vsc_sdp;
 struct intel_connector;
 struct intel_crtc_state;
 struct intel_digital_port;
@@ -110,6 +111,13 @@ int intel_dp_link_required(int pixel_clock, int bpp);
 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
 bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
 			    const struct drm_connector_state *conn_state);
+void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
+				  const struct intel_crtc_state *crtc_state,
+				  const struct drm_connector_state *conn_state,
+				  struct drm_dp_vsc_sdp *vsc);
+void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
+			    const struct intel_crtc_state *crtc_state,
+			    struct drm_dp_vsc_sdp *vsc);
 void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
 			     const struct intel_crtc_state *crtc_state,
 			     const struct drm_connector_state *conn_state);
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 17/17] drm/i915/psr: Use new DP VSC SDP compute routine on PSR

[Gwan-gyeong Mun]

In order to use a common VSC SDP Colorimetry calculating code on PSR,
it uses a new psr vsc sdp compute routine.
Because PSR routine has its own scenario and timings of writing a VSC SDP,
the current PSR routine needs to have its own drm_dp_vsc_sdp structure
member variable on struct i915_psr.

In order to calculate colorimetry information, intel_psr_update()
function and intel_psr_enable() function extend a drm_connector_state
argument.

There are no changes to PSR mechanism.

v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c |  4 +-
 drivers/gpu/drm/i915/display/intel_psr.c | 54 +++++++-----------------
 drivers/gpu/drm/i915/display/intel_psr.h |  6 ++-
 drivers/gpu/drm/i915/i915_drv.h          |  1 +
 4 files changed, 22 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 8509cd33569e..00b46c45f6a8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3901,7 +3901,7 @@ static void intel_enable_ddi_dp(struct intel_encoder *encoder,
 		intel_dp_stop_link_train(intel_dp);
 
 	intel_edp_backlight_on(crtc_state, conn_state);
-	intel_psr_enable(intel_dp, crtc_state);
+	intel_psr_enable(intel_dp, crtc_state, conn_state);
 	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
 	intel_edp_drrs_enable(intel_dp, crtc_state);
 
@@ -4063,7 +4063,7 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
 
 	intel_ddi_set_dp_msa(crtc_state, conn_state);
 
-	intel_psr_update(intel_dp, crtc_state);
+	intel_psr_update(intel_dp, crtc_state, conn_state);
 	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
 	intel_edp_drrs_enable(intel_dp, crtc_state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index e41ed962aa80..a4564607b6c5 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -330,39 +330,6 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 	}
 }
 
-static void intel_psr_setup_vsc(struct intel_dp *intel_dp,
-				const struct intel_crtc_state *crtc_state)
-{
-	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
-	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-	struct dp_sdp psr_vsc;
-
-	if (dev_priv->psr.psr2_enabled) {
-		/* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
-		memset(&psr_vsc, 0, sizeof(psr_vsc));
-		psr_vsc.sdp_header.HB0 = 0;
-		psr_vsc.sdp_header.HB1 = 0x7;
-		if (dev_priv->psr.colorimetry_support) {
-			psr_vsc.sdp_header.HB2 = 0x5;
-			psr_vsc.sdp_header.HB3 = 0x13;
-		} else {
-			psr_vsc.sdp_header.HB2 = 0x4;
-			psr_vsc.sdp_header.HB3 = 0xe;
-		}
-	} else {
-		/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
-		memset(&psr_vsc, 0, sizeof(psr_vsc));
-		psr_vsc.sdp_header.HB0 = 0;
-		psr_vsc.sdp_header.HB1 = 0x7;
-		psr_vsc.sdp_header.HB2 = 0x2;
-		psr_vsc.sdp_header.HB3 = 0x8;
-	}
-
-	intel_dig_port->write_infoframe(&intel_dig_port->base,
-					crtc_state,
-					DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc));
-}
-
 static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -841,9 +808,12 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 }
 
 static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
-				    const struct intel_crtc_state *crtc_state)
+				    const struct intel_crtc_state *crtc_state,
+				    const struct drm_connector_state *conn_state)
 {
 	struct intel_dp *intel_dp = dev_priv->psr.dp;
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct intel_encoder *encoder = &intel_dig_port->base;
 	u32 val;
 
 	WARN_ON(dev_priv->psr.enabled);
@@ -881,7 +851,9 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
 
 	DRM_DEBUG_KMS("Enabling PSR%s\n",
 		      dev_priv->psr.psr2_enabled ? "2" : "1");
-	intel_psr_setup_vsc(intel_dp, crtc_state);
+	intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
+				     &dev_priv->psr.vsc);
+	intel_write_dp_vsc_sdp(encoder, crtc_state, &dev_priv->psr.vsc);
 	intel_psr_enable_sink(intel_dp);
 	intel_psr_enable_source(intel_dp, crtc_state);
 	dev_priv->psr.enabled = true;
@@ -893,11 +865,13 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
  * intel_psr_enable - Enable PSR
  * @intel_dp: Intel DP
  * @crtc_state: new CRTC state
+ * @conn_state: new CONNECTOR state
  *
  * This function can only be called after the pipe is fully trained and enabled.
  */
 void intel_psr_enable(struct intel_dp *intel_dp,
-		      const struct intel_crtc_state *crtc_state)
+		      const struct intel_crtc_state *crtc_state,
+		      const struct drm_connector_state *conn_state)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
@@ -916,7 +890,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
 		goto unlock;
 	}
 
-	intel_psr_enable_locked(dev_priv, crtc_state);
+	intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
 
 unlock:
 	mutex_unlock(&dev_priv->psr.lock);
@@ -1049,13 +1023,15 @@ static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv)
  * intel_psr_update - Update PSR state
  * @intel_dp: Intel DP
  * @crtc_state: new CRTC state
+ * @conn_state: new CONNECTOR state
  *
  * This functions will update PSR states, disabling, enabling or switching PSR
  * version when executing fastsets. For full modeset, intel_psr_disable() and
  * intel_psr_enable() should be called instead.
  */
 void intel_psr_update(struct intel_dp *intel_dp,
-		      const struct intel_crtc_state *crtc_state)
+		      const struct intel_crtc_state *crtc_state,
+		      const struct drm_connector_state *conn_state)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	struct i915_psr *psr = &dev_priv->psr;
@@ -1090,7 +1066,7 @@ void intel_psr_update(struct intel_dp *intel_dp,
 		intel_psr_disable_locked(intel_dp);
 
 	if (enable)
-		intel_psr_enable_locked(dev_priv, crtc_state);
+		intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
 
 unlock:
 	mutex_unlock(&dev_priv->psr.lock);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index c58a1d438808..a003fb18105a 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -17,11 +17,13 @@ struct intel_dp;
 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
 void intel_psr_enable(struct intel_dp *intel_dp,
-		      const struct intel_crtc_state *crtc_state);
+		      const struct intel_crtc_state *crtc_state,
+		      const struct drm_connector_state *conn_state);
 void intel_psr_disable(struct intel_dp *intel_dp,
 		       const struct intel_crtc_state *old_crtc_state);
 void intel_psr_update(struct intel_dp *intel_dp,
-		      const struct intel_crtc_state *crtc_state);
+		      const struct intel_crtc_state *crtc_state,
+		      const struct drm_connector_state *conn_state);
 int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 value);
 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
 			  unsigned frontbuffer_bits,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a8a08c63278e..fa2f1a18ffe0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -504,6 +504,7 @@ struct i915_psr {
 	u32 dc3co_exit_delay;
 	struct delayed_work idle_work;
 	bool initially_probed;
+	struct drm_dp_vsc_sdp vsc;
 };
 
 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
-- 
2.24.1

[PATCH v3 17/17] drm/i915/psr: Use new DP VSC SDP compute routine on PSR

[Gwan-gyeong Mun]

In order to use a common VSC SDP Colorimetry calculating code on PSR,
it uses a new psr vsc sdp compute routine.
Because PSR routine has its own scenario and timings of writing a VSC SDP,
the current PSR routine needs to have its own drm_dp_vsc_sdp structure
member variable on struct i915_psr.

In order to calculate colorimetry information, intel_psr_update()
function and intel_psr_enable() function extend a drm_connector_state
argument.

There are no changes to PSR mechanism.

v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c |  4 +-
 drivers/gpu/drm/i915/display/intel_psr.c | 54 +++++++-----------------
 drivers/gpu/drm/i915/display/intel_psr.h |  6 ++-
 drivers/gpu/drm/i915/i915_drv.h          |  1 +
 4 files changed, 22 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 8509cd33569e..00b46c45f6a8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3901,7 +3901,7 @@ static void intel_enable_ddi_dp(struct intel_encoder *encoder,
 		intel_dp_stop_link_train(intel_dp);
 
 	intel_edp_backlight_on(crtc_state, conn_state);
-	intel_psr_enable(intel_dp, crtc_state);
+	intel_psr_enable(intel_dp, crtc_state, conn_state);
 	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
 	intel_edp_drrs_enable(intel_dp, crtc_state);
 
@@ -4063,7 +4063,7 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
 
 	intel_ddi_set_dp_msa(crtc_state, conn_state);
 
-	intel_psr_update(intel_dp, crtc_state);
+	intel_psr_update(intel_dp, crtc_state, conn_state);
 	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
 	intel_edp_drrs_enable(intel_dp, crtc_state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index e41ed962aa80..a4564607b6c5 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -330,39 +330,6 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 	}
 }
 
-static void intel_psr_setup_vsc(struct intel_dp *intel_dp,
-				const struct intel_crtc_state *crtc_state)
-{
-	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
-	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-	struct dp_sdp psr_vsc;
-
-	if (dev_priv->psr.psr2_enabled) {
-		/* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
-		memset(&psr_vsc, 0, sizeof(psr_vsc));
-		psr_vsc.sdp_header.HB0 = 0;
-		psr_vsc.sdp_header.HB1 = 0x7;
-		if (dev_priv->psr.colorimetry_support) {
-			psr_vsc.sdp_header.HB2 = 0x5;
-			psr_vsc.sdp_header.HB3 = 0x13;
-		} else {
-			psr_vsc.sdp_header.HB2 = 0x4;
-			psr_vsc.sdp_header.HB3 = 0xe;
-		}
-	} else {
-		/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
-		memset(&psr_vsc, 0, sizeof(psr_vsc));
-		psr_vsc.sdp_header.HB0 = 0;
-		psr_vsc.sdp_header.HB1 = 0x7;
-		psr_vsc.sdp_header.HB2 = 0x2;
-		psr_vsc.sdp_header.HB3 = 0x8;
-	}
-
-	intel_dig_port->write_infoframe(&intel_dig_port->base,
-					crtc_state,
-					DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc));
-}
-
 static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -841,9 +808,12 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 }
 
 static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
-				    const struct intel_crtc_state *crtc_state)
+				    const struct intel_crtc_state *crtc_state,
+				    const struct drm_connector_state *conn_state)
 {
 	struct intel_dp *intel_dp = dev_priv->psr.dp;
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct intel_encoder *encoder = &intel_dig_port->base;
 	u32 val;
 
 	WARN_ON(dev_priv->psr.enabled);
@@ -881,7 +851,9 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
 
 	DRM_DEBUG_KMS("Enabling PSR%s\n",
 		      dev_priv->psr.psr2_enabled ? "2" : "1");
-	intel_psr_setup_vsc(intel_dp, crtc_state);
+	intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
+				     &dev_priv->psr.vsc);
+	intel_write_dp_vsc_sdp(encoder, crtc_state, &dev_priv->psr.vsc);
 	intel_psr_enable_sink(intel_dp);
 	intel_psr_enable_source(intel_dp, crtc_state);
 	dev_priv->psr.enabled = true;
@@ -893,11 +865,13 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
  * intel_psr_enable - Enable PSR
  * @intel_dp: Intel DP
  * @crtc_state: new CRTC state
+ * @conn_state: new CONNECTOR state
  *
  * This function can only be called after the pipe is fully trained and enabled.
  */
 void intel_psr_enable(struct intel_dp *intel_dp,
-		      const struct intel_crtc_state *crtc_state)
+		      const struct intel_crtc_state *crtc_state,
+		      const struct drm_connector_state *conn_state)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
@@ -916,7 +890,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
 		goto unlock;
 	}
 
-	intel_psr_enable_locked(dev_priv, crtc_state);
+	intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
 
 unlock:
 	mutex_unlock(&dev_priv->psr.lock);
@@ -1049,13 +1023,15 @@ static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv)
  * intel_psr_update - Update PSR state
  * @intel_dp: Intel DP
  * @crtc_state: new CRTC state
+ * @conn_state: new CONNECTOR state
  *
  * This functions will update PSR states, disabling, enabling or switching PSR
  * version when executing fastsets. For full modeset, intel_psr_disable() and
  * intel_psr_enable() should be called instead.
  */
 void intel_psr_update(struct intel_dp *intel_dp,
-		      const struct intel_crtc_state *crtc_state)
+		      const struct intel_crtc_state *crtc_state,
+		      const struct drm_connector_state *conn_state)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	struct i915_psr *psr = &dev_priv->psr;
@@ -1090,7 +1066,7 @@ void intel_psr_update(struct intel_dp *intel_dp,
 		intel_psr_disable_locked(intel_dp);
 
 	if (enable)
-		intel_psr_enable_locked(dev_priv, crtc_state);
+		intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
 
 unlock:
 	mutex_unlock(&dev_priv->psr.lock);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index c58a1d438808..a003fb18105a 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -17,11 +17,13 @@ struct intel_dp;
 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
 void intel_psr_enable(struct intel_dp *intel_dp,
-		      const struct intel_crtc_state *crtc_state);
+		      const struct intel_crtc_state *crtc_state,
+		      const struct drm_connector_state *conn_state);
 void intel_psr_disable(struct intel_dp *intel_dp,
 		       const struct intel_crtc_state *old_crtc_state);
 void intel_psr_update(struct intel_dp *intel_dp,
-		      const struct intel_crtc_state *crtc_state);
+		      const struct intel_crtc_state *crtc_state,
+		      const struct drm_connector_state *conn_state);
 int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 value);
 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
 			  unsigned frontbuffer_bits,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a8a08c63278e..fa2f1a18ffe0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -504,6 +504,7 @@ struct i915_psr {
 	u32 dc3co_exit_delay;
 	struct delayed_work idle_work;
 	bool initially_probed;
+	struct drm_dp_vsc_sdp vsc;
 };
 
 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
-- 
2.24.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[Intel-gfx] [PATCH v3 17/17] drm/i915/psr: Use new DP VSC SDP compute routine on PSR

[Gwan-gyeong Mun]

In order to use a common VSC SDP Colorimetry calculating code on PSR,
it uses a new psr vsc sdp compute routine.
Because PSR routine has its own scenario and timings of writing a VSC SDP,
the current PSR routine needs to have its own drm_dp_vsc_sdp structure
member variable on struct i915_psr.

In order to calculate colorimetry information, intel_psr_update()
function and intel_psr_enable() function extend a drm_connector_state
argument.

There are no changes to PSR mechanism.

v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c |  4 +-
 drivers/gpu/drm/i915/display/intel_psr.c | 54 +++++++-----------------
 drivers/gpu/drm/i915/display/intel_psr.h |  6 ++-
 drivers/gpu/drm/i915/i915_drv.h          |  1 +
 4 files changed, 22 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 8509cd33569e..00b46c45f6a8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3901,7 +3901,7 @@ static void intel_enable_ddi_dp(struct intel_encoder *encoder,
 		intel_dp_stop_link_train(intel_dp);
 
 	intel_edp_backlight_on(crtc_state, conn_state);
-	intel_psr_enable(intel_dp, crtc_state);
+	intel_psr_enable(intel_dp, crtc_state, conn_state);
 	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
 	intel_edp_drrs_enable(intel_dp, crtc_state);
 
@@ -4063,7 +4063,7 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
 
 	intel_ddi_set_dp_msa(crtc_state, conn_state);
 
-	intel_psr_update(intel_dp, crtc_state);
+	intel_psr_update(intel_dp, crtc_state, conn_state);
 	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
 	intel_edp_drrs_enable(intel_dp, crtc_state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index e41ed962aa80..a4564607b6c5 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -330,39 +330,6 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 	}
 }
 
-static void intel_psr_setup_vsc(struct intel_dp *intel_dp,
-				const struct intel_crtc_state *crtc_state)
-{
-	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
-	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-	struct dp_sdp psr_vsc;
-
-	if (dev_priv->psr.psr2_enabled) {
-		/* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
-		memset(&psr_vsc, 0, sizeof(psr_vsc));
-		psr_vsc.sdp_header.HB0 = 0;
-		psr_vsc.sdp_header.HB1 = 0x7;
-		if (dev_priv->psr.colorimetry_support) {
-			psr_vsc.sdp_header.HB2 = 0x5;
-			psr_vsc.sdp_header.HB3 = 0x13;
-		} else {
-			psr_vsc.sdp_header.HB2 = 0x4;
-			psr_vsc.sdp_header.HB3 = 0xe;
-		}
-	} else {
-		/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
-		memset(&psr_vsc, 0, sizeof(psr_vsc));
-		psr_vsc.sdp_header.HB0 = 0;
-		psr_vsc.sdp_header.HB1 = 0x7;
-		psr_vsc.sdp_header.HB2 = 0x2;
-		psr_vsc.sdp_header.HB3 = 0x8;
-	}
-
-	intel_dig_port->write_infoframe(&intel_dig_port->base,
-					crtc_state,
-					DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc));
-}
-
 static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -841,9 +808,12 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 }
 
 static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
-				    const struct intel_crtc_state *crtc_state)
+				    const struct intel_crtc_state *crtc_state,
+				    const struct drm_connector_state *conn_state)
 {
 	struct intel_dp *intel_dp = dev_priv->psr.dp;
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct intel_encoder *encoder = &intel_dig_port->base;
 	u32 val;
 
 	WARN_ON(dev_priv->psr.enabled);
@@ -881,7 +851,9 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
 
 	DRM_DEBUG_KMS("Enabling PSR%s\n",
 		      dev_priv->psr.psr2_enabled ? "2" : "1");
-	intel_psr_setup_vsc(intel_dp, crtc_state);
+	intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
+				     &dev_priv->psr.vsc);
+	intel_write_dp_vsc_sdp(encoder, crtc_state, &dev_priv->psr.vsc);
 	intel_psr_enable_sink(intel_dp);
 	intel_psr_enable_source(intel_dp, crtc_state);
 	dev_priv->psr.enabled = true;
@@ -893,11 +865,13 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
  * intel_psr_enable - Enable PSR
  * @intel_dp: Intel DP
  * @crtc_state: new CRTC state
+ * @conn_state: new CONNECTOR state
  *
  * This function can only be called after the pipe is fully trained and enabled.
  */
 void intel_psr_enable(struct intel_dp *intel_dp,
-		      const struct intel_crtc_state *crtc_state)
+		      const struct intel_crtc_state *crtc_state,
+		      const struct drm_connector_state *conn_state)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
@@ -916,7 +890,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
 		goto unlock;
 	}
 
-	intel_psr_enable_locked(dev_priv, crtc_state);
+	intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
 
 unlock:
 	mutex_unlock(&dev_priv->psr.lock);
@@ -1049,13 +1023,15 @@ static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv)
  * intel_psr_update - Update PSR state
  * @intel_dp: Intel DP
  * @crtc_state: new CRTC state
+ * @conn_state: new CONNECTOR state
  *
  * This functions will update PSR states, disabling, enabling or switching PSR
  * version when executing fastsets. For full modeset, intel_psr_disable() and
  * intel_psr_enable() should be called instead.
  */
 void intel_psr_update(struct intel_dp *intel_dp,
-		      const struct intel_crtc_state *crtc_state)
+		      const struct intel_crtc_state *crtc_state,
+		      const struct drm_connector_state *conn_state)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	struct i915_psr *psr = &dev_priv->psr;
@@ -1090,7 +1066,7 @@ void intel_psr_update(struct intel_dp *intel_dp,
 		intel_psr_disable_locked(intel_dp);
 
 	if (enable)
-		intel_psr_enable_locked(dev_priv, crtc_state);
+		intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
 
 unlock:
 	mutex_unlock(&dev_priv->psr.lock);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index c58a1d438808..a003fb18105a 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -17,11 +17,13 @@ struct intel_dp;
 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
 void intel_psr_enable(struct intel_dp *intel_dp,
-		      const struct intel_crtc_state *crtc_state);
+		      const struct intel_crtc_state *crtc_state,
+		      const struct drm_connector_state *conn_state);
 void intel_psr_disable(struct intel_dp *intel_dp,
 		       const struct intel_crtc_state *old_crtc_state);
 void intel_psr_update(struct intel_dp *intel_dp,
-		      const struct intel_crtc_state *crtc_state);
+		      const struct intel_crtc_state *crtc_state,
+		      const struct drm_connector_state *conn_state);
 int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 value);
 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
 			  unsigned frontbuffer_bits,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a8a08c63278e..fa2f1a18ffe0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -504,6 +504,7 @@ struct i915_psr {
 	u32 dc3co_exit_delay;
 	struct delayed_work idle_work;
 	bool initially_probed;
+	struct drm_dp_vsc_sdp vsc;
 };
 
 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.BUILD: failure for In order to readout DP SDPs, refactors the handling of DP SDPs (rev3)

[Patchwork]

== Series Details ==

Series: In order to readout DP SDPs, refactors the handling of DP SDPs (rev3)
URL   : https://patchwork.freedesktop.org/series/72853/
State : failure

== Summary ==

Applying: drm: add DP 1.4 VSC SDP Payload related enums and a structure
Applying: drm/i915/dp: Add compute routine for DP VSC SDP
Applying: drm/i915/dp: Add compute routine for DP HDR Metadata Infoframe SDP
Applying: drm/i915/dp: Add writing of DP SDPs (Secondary Data Packet)
Applying: video/hdmi: Add Unpack only function for DRM infoframe
Applying: drm/i915/dp: Read out DP SDPs (Secondary Data Packet)
Applying: drm: Add logging function for DP VSC SDP
Applying: drm/i915: Include HDMI DRM infoframe in the crtc state dump
Applying: drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump
Applying: drm/i915: Include DP VSC SDP in the crtc state dump
Applying: drm/i915: Program DP SDPs with computed configs
Applying: drm/i915: Add state readout for DP HDR Metadata Infoframe SDP
Applying: drm/i915: Add state readout for DP VSC SDP
Applying: drm/i915: Program DP SDPs on pipe updates
Applying: drm/i915: Stop sending DP SDPs on intel_ddi_post_disable_dp()
Applying: drm/i915/dp: Add compute routine for DP PSR VSC SDP
Applying: drm/i915/psr: Use new DP VSC SDP compute routine on PSR
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/display/intel_ddi.c).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0017 drm/i915/psr: Use new DP VSC SDP compute routine on PSR
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

RE: [PATCH v3 01/17] drm: add DP 1.4 VSC SDP Payload related enums and a structure

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 01/17] drm: add DP 1.4 VSC SDP Payload related enums and a
> structure

%s/add/Add/
Also you can rephrase this as " Add DP1.4 VSC SDP Payload related Data Structures"/

> It adds new enumeration definitions for VSC SDP Payload for Pixel
> Encoding/Colorimetry Format.
> And it adds a new drm data structure for DP VSC SDP.
> 
> enum dp_colorspace and enum dp_colorimetry correspond "Pixel Encoding and
> Colorimetry Formats". enum dp_dynamic_range corresponds "Dynamic Range".
> And enum dp_content_type corresponds "Content Type"
> All of them are based on DP 1.4 spec [Table 2-117: VSC SDP Payload for
> DB16 through DB18].
> 
> v3: Add a new drm data structure for DP VSC SDP
> 
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  include/drm/drm_dp_helper.h | 57 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 57 insertions(+)
> 
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index
> 262faf9e5e94..c098727681fa 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1209,6 +1209,63 @@ struct dp_sdp {
>  #define EDP_VSC_PSR_UPDATE_RFB		(1<<1)
>  #define EDP_VSC_PSR_CRC_VALUES_VALID	(1<<2)
> 
> +/* Based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
> +DB18] */ enum dp_colorspace {

We should not call this colorspace, rather rename it to dp_pixelformat.
These are not colorspaces.

Also add these to kernel docs as they are standard definitions.

> +	DP_COLORSPACE_RGB = 0,

Make this as DP_PIXELFORMAT_RGB and rename all the below ones as well.

> +	DP_COLORSPACE_YUV444 = 0x1,
> +	DP_COLORSPACE_YUV422 = 0x2,
> +	DP_COLORSPACE_YUV420 = 0x3,
> +	DP_COLORSPACE_Y_ONLY = 0x4,
> +	DP_COLORSPACE_RAW = 0x5,
> +	DP_COLORSPACE_RESERVED = 0x6,
> +};
> +
> +/**
> + * Based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
> +DB18]
> + * and a name of enum member followes DRM_MODE_COLORIMETRY definition.

Typo in follows

> + */
> +enum dp_colorimetry {

You can call this as dp_colorspace (this is actual colorspace), you can stick with colorimetry as well.
Will leave that to you.

> +	DP_COLORIMETRY_DEFAULT = 0, /* sRGB (IEC 61966-2-1) / ITU-R BT.601 */
> +	DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
> +	DP_COLORIMETRY_BT709_YCC = 0x1,
> +	DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
> +	DP_COLORIMETRY_XVYCC_601 = 0x2,
> +	DP_COLORIMETRY_OPRGB = 0x3,
> +	DP_COLORIMETRY_XVYCC_709 = 0x3,
> +	DP_COLORIMETRY_DCI_P3_RGB = 0x4,
> +	DP_COLORIMETRY_SYCC_601 = 0x4,
> +	DP_COLORIMETRY_RGB_CUSTOM = 0x5,
> +	DP_COLORIMETRY_OPYCC_601 = 0x5,
> +	DP_COLORIMETRY_BT2020_RGB = 0x6,
> +	DP_COLORIMETRY_BT2020_CYCC = 0x6,
> +	DP_COLORIMETRY_BT2020_YCC = 0x7,
> +};
> +
> +enum dp_dynamic_range {
> +	DP_DYNAMIC_RANGE_VESA = 0,
> +	DP_DYNAMIC_RANGE_CTA = 1,
> +};
> +
> +enum dp_content_type {
> +	DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
> +	DP_CONTENT_TYPE_GRAPHICS = 0x01,
> +	DP_CONTENT_TYPE_PHOTO = 0x02,
> +	DP_CONTENT_TYPE_VIDEO = 0x03,
> +	DP_CONTENT_TYPE_GAME = 0x04,
> +};
> +
> +/* DRM DP VSC SDP as per DP 1.4 spec */ struct drm_dp_vsc_sdp {
> +	unsigned char sdp_type; /* Secondary-data Packet Type */
> +	unsigned char revision; /* Revision Number */

These comments seems self-explanatory, you can probably drop them.

> +	unsigned char length; /* Number of Valid Data Bytes */
> +	enum dp_colorspace colorspace;
> +	enum dp_colorimetry colorimetry;
> +	int bpc; /* bit per color */
> +	enum dp_dynamic_range dynamic_range;
> +	enum dp_content_type content_type;
> +};
> +
>  int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
> 
>  static inline int
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

RE: [PATCH v3 01/17] drm: add DP 1.4 VSC SDP Payload related enums and a structure

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 01/17] drm: add DP 1.4 VSC SDP Payload related enums and a
> structure

%s/add/Add/
Also you can rephrase this as " Add DP1.4 VSC SDP Payload related Data Structures"/

> It adds new enumeration definitions for VSC SDP Payload for Pixel
> Encoding/Colorimetry Format.
> And it adds a new drm data structure for DP VSC SDP.
> 
> enum dp_colorspace and enum dp_colorimetry correspond "Pixel Encoding and
> Colorimetry Formats". enum dp_dynamic_range corresponds "Dynamic Range".
> And enum dp_content_type corresponds "Content Type"
> All of them are based on DP 1.4 spec [Table 2-117: VSC SDP Payload for
> DB16 through DB18].
> 
> v3: Add a new drm data structure for DP VSC SDP
> 
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  include/drm/drm_dp_helper.h | 57 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 57 insertions(+)
> 
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index
> 262faf9e5e94..c098727681fa 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1209,6 +1209,63 @@ struct dp_sdp {
>  #define EDP_VSC_PSR_UPDATE_RFB		(1<<1)
>  #define EDP_VSC_PSR_CRC_VALUES_VALID	(1<<2)
> 
> +/* Based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
> +DB18] */ enum dp_colorspace {

We should not call this colorspace, rather rename it to dp_pixelformat.
These are not colorspaces.

Also add these to kernel docs as they are standard definitions.

> +	DP_COLORSPACE_RGB = 0,

Make this as DP_PIXELFORMAT_RGB and rename all the below ones as well.

> +	DP_COLORSPACE_YUV444 = 0x1,
> +	DP_COLORSPACE_YUV422 = 0x2,
> +	DP_COLORSPACE_YUV420 = 0x3,
> +	DP_COLORSPACE_Y_ONLY = 0x4,
> +	DP_COLORSPACE_RAW = 0x5,
> +	DP_COLORSPACE_RESERVED = 0x6,
> +};
> +
> +/**
> + * Based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
> +DB18]
> + * and a name of enum member followes DRM_MODE_COLORIMETRY definition.

Typo in follows

> + */
> +enum dp_colorimetry {

You can call this as dp_colorspace (this is actual colorspace), you can stick with colorimetry as well.
Will leave that to you.

> +	DP_COLORIMETRY_DEFAULT = 0, /* sRGB (IEC 61966-2-1) / ITU-R BT.601 */
> +	DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
> +	DP_COLORIMETRY_BT709_YCC = 0x1,
> +	DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
> +	DP_COLORIMETRY_XVYCC_601 = 0x2,
> +	DP_COLORIMETRY_OPRGB = 0x3,
> +	DP_COLORIMETRY_XVYCC_709 = 0x3,
> +	DP_COLORIMETRY_DCI_P3_RGB = 0x4,
> +	DP_COLORIMETRY_SYCC_601 = 0x4,
> +	DP_COLORIMETRY_RGB_CUSTOM = 0x5,
> +	DP_COLORIMETRY_OPYCC_601 = 0x5,
> +	DP_COLORIMETRY_BT2020_RGB = 0x6,
> +	DP_COLORIMETRY_BT2020_CYCC = 0x6,
> +	DP_COLORIMETRY_BT2020_YCC = 0x7,
> +};
> +
> +enum dp_dynamic_range {
> +	DP_DYNAMIC_RANGE_VESA = 0,
> +	DP_DYNAMIC_RANGE_CTA = 1,
> +};
> +
> +enum dp_content_type {
> +	DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
> +	DP_CONTENT_TYPE_GRAPHICS = 0x01,
> +	DP_CONTENT_TYPE_PHOTO = 0x02,
> +	DP_CONTENT_TYPE_VIDEO = 0x03,
> +	DP_CONTENT_TYPE_GAME = 0x04,
> +};
> +
> +/* DRM DP VSC SDP as per DP 1.4 spec */ struct drm_dp_vsc_sdp {
> +	unsigned char sdp_type; /* Secondary-data Packet Type */
> +	unsigned char revision; /* Revision Number */

These comments seems self-explanatory, you can probably drop them.

> +	unsigned char length; /* Number of Valid Data Bytes */
> +	enum dp_colorspace colorspace;
> +	enum dp_colorimetry colorimetry;
> +	int bpc; /* bit per color */
> +	enum dp_dynamic_range dynamic_range;
> +	enum dp_content_type content_type;
> +};
> +
>  int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
> 
>  static inline int
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Intel-gfx] [PATCH v3 01/17] drm: add DP 1.4 VSC SDP Payload related enums and a structure

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 01/17] drm: add DP 1.4 VSC SDP Payload related enums and a
> structure

%s/add/Add/
Also you can rephrase this as " Add DP1.4 VSC SDP Payload related Data Structures"/

> It adds new enumeration definitions for VSC SDP Payload for Pixel
> Encoding/Colorimetry Format.
> And it adds a new drm data structure for DP VSC SDP.
> 
> enum dp_colorspace and enum dp_colorimetry correspond "Pixel Encoding and
> Colorimetry Formats". enum dp_dynamic_range corresponds "Dynamic Range".
> And enum dp_content_type corresponds "Content Type"
> All of them are based on DP 1.4 spec [Table 2-117: VSC SDP Payload for
> DB16 through DB18].
> 
> v3: Add a new drm data structure for DP VSC SDP
> 
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  include/drm/drm_dp_helper.h | 57 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 57 insertions(+)
> 
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index
> 262faf9e5e94..c098727681fa 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1209,6 +1209,63 @@ struct dp_sdp {
>  #define EDP_VSC_PSR_UPDATE_RFB		(1<<1)
>  #define EDP_VSC_PSR_CRC_VALUES_VALID	(1<<2)
> 
> +/* Based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
> +DB18] */ enum dp_colorspace {

We should not call this colorspace, rather rename it to dp_pixelformat.
These are not colorspaces.

Also add these to kernel docs as they are standard definitions.

> +	DP_COLORSPACE_RGB = 0,

Make this as DP_PIXELFORMAT_RGB and rename all the below ones as well.

> +	DP_COLORSPACE_YUV444 = 0x1,
> +	DP_COLORSPACE_YUV422 = 0x2,
> +	DP_COLORSPACE_YUV420 = 0x3,
> +	DP_COLORSPACE_Y_ONLY = 0x4,
> +	DP_COLORSPACE_RAW = 0x5,
> +	DP_COLORSPACE_RESERVED = 0x6,
> +};
> +
> +/**
> + * Based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
> +DB18]
> + * and a name of enum member followes DRM_MODE_COLORIMETRY definition.

Typo in follows

> + */
> +enum dp_colorimetry {

You can call this as dp_colorspace (this is actual colorspace), you can stick with colorimetry as well.
Will leave that to you.

> +	DP_COLORIMETRY_DEFAULT = 0, /* sRGB (IEC 61966-2-1) / ITU-R BT.601 */
> +	DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
> +	DP_COLORIMETRY_BT709_YCC = 0x1,
> +	DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
> +	DP_COLORIMETRY_XVYCC_601 = 0x2,
> +	DP_COLORIMETRY_OPRGB = 0x3,
> +	DP_COLORIMETRY_XVYCC_709 = 0x3,
> +	DP_COLORIMETRY_DCI_P3_RGB = 0x4,
> +	DP_COLORIMETRY_SYCC_601 = 0x4,
> +	DP_COLORIMETRY_RGB_CUSTOM = 0x5,
> +	DP_COLORIMETRY_OPYCC_601 = 0x5,
> +	DP_COLORIMETRY_BT2020_RGB = 0x6,
> +	DP_COLORIMETRY_BT2020_CYCC = 0x6,
> +	DP_COLORIMETRY_BT2020_YCC = 0x7,
> +};
> +
> +enum dp_dynamic_range {
> +	DP_DYNAMIC_RANGE_VESA = 0,
> +	DP_DYNAMIC_RANGE_CTA = 1,
> +};
> +
> +enum dp_content_type {
> +	DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
> +	DP_CONTENT_TYPE_GRAPHICS = 0x01,
> +	DP_CONTENT_TYPE_PHOTO = 0x02,
> +	DP_CONTENT_TYPE_VIDEO = 0x03,
> +	DP_CONTENT_TYPE_GAME = 0x04,
> +};
> +
> +/* DRM DP VSC SDP as per DP 1.4 spec */ struct drm_dp_vsc_sdp {
> +	unsigned char sdp_type; /* Secondary-data Packet Type */
> +	unsigned char revision; /* Revision Number */

These comments seems self-explanatory, you can probably drop them.

> +	unsigned char length; /* Number of Valid Data Bytes */
> +	enum dp_colorspace colorspace;
> +	enum dp_colorimetry colorimetry;
> +	int bpc; /* bit per color */
> +	enum dp_dynamic_range dynamic_range;
> +	enum dp_content_type content_type;
> +};
> +
>  int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
> 
>  static inline int
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

RE: [PATCH v3 02/17] drm/i915/dp: Add compute routine for DP VSC SDP

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 02/17] drm/i915/dp: Add compute routine for DP VSC SDP
> 
> In order to support state readout for DP VSC SDP, we need to have a structure which
> holds DP VSC SDP payload data such as "union hdmi_infoframe drm" which is used
> for DRM infoframe.
> It adds a struct drm_dp_vsc_sdp vsc to intel_crtc_state.infoframes.
> 
> And it stores computed dp vsc sdp to infoframes.vsc of crtc state.
> While computing we'll also fill out the inforames.enable bitmask appropriately.
> 
> The compute routine follows DP 1.4 spec [Table 2-117: VSC SDP Payload for
> DB16 through DB18].
> 
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
>

With the structure names updated, this looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_dp.c       | 92 +++++++++++++++++++
>  2 files changed, 93 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 33ba93863488..6633c1061670 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1021,6 +1021,7 @@ struct intel_crtc_state {
>  		union hdmi_infoframe spd;
>  		union hdmi_infoframe hdmi;
>  		union hdmi_infoframe drm;
> +		struct drm_dp_vsc_sdp vsc;
>  	} infoframes;
> 
>  	/* HDMI scrambling status */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index f4dede6253f8..2bdc43c80e03 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2372,6 +2372,97 @@ static bool intel_dp_port_has_audio(struct
> drm_i915_private *dev_priv,
>  	return true;
>  }
> 
> +static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state
> *crtc_state,
> +					     const struct drm_connector_state
> *conn_state,
> +					     struct drm_dp_vsc_sdp *vsc)
> +{
> +	/*
> +	 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> +	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> +	 * Colorimetry Format indication.
> +	 */
> +	vsc->revision = 0x5;
> +	vsc->length = 0x13;
> +
> +	/* DP 1.4a spec, Table 2-120 */
> +	switch (crtc_state->output_format) {
> +	case INTEL_OUTPUT_FORMAT_YCBCR444:
> +		vsc->colorspace = DP_COLORSPACE_YUV444;
> +		break;
> +	case INTEL_OUTPUT_FORMAT_YCBCR420:
> +		vsc->colorspace = DP_COLORSPACE_YUV420;
> +		break;
> +	case INTEL_OUTPUT_FORMAT_RGB:
> +	default:
> +		vsc->colorspace = DP_COLORSPACE_RGB;
> +	}
> +
> +	switch (conn_state->colorspace) {
> +	case DRM_MODE_COLORIMETRY_BT709_YCC:
> +		vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
> +		break;
> +	case DRM_MODE_COLORIMETRY_XVYCC_601:
> +		vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
> +		break;
> +	case DRM_MODE_COLORIMETRY_XVYCC_709:
> +		vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
> +		break;
> +	case DRM_MODE_COLORIMETRY_SYCC_601:
> +		vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
> +		break;
> +	case DRM_MODE_COLORIMETRY_OPYCC_601:
> +		vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
> +		break;
> +	case DRM_MODE_COLORIMETRY_BT2020_CYCC:
> +		vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
> +		break;
> +	case DRM_MODE_COLORIMETRY_BT2020_RGB:
> +		vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
> +		break;
> +	case DRM_MODE_COLORIMETRY_BT2020_YCC:
> +		vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
> +		break;
> +	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
> +	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
> +		vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
> +		break;
> +	default:
> +		/*
> +		 * RGB->YCBCR color conversion uses the BT.709
> +		 * color space.
> +		 */
> +		if (crtc_state->output_format =
> INTEL_OUTPUT_FORMAT_YCBCR420)
> +			vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
> +		else
> +			vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
> +		break;
> +	}
> +
> +	vsc->bpc = crtc_state->pipe_bpp / 3;
> +	/* all YCbCr are always limited range */
> +	vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
> +	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED; }
> +
> +static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
> +				     struct intel_crtc_state *crtc_state,
> +				     const struct drm_connector_state *conn_state) {
> +	struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
> +
> +	/* When PSR is enabled, VSC SDP is handled by PSR routine */
> +	if (intel_psr_enabled(intel_dp))
> +		return;
> +
> +	if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
> +		return;
> +
> +	crtc_state->infoframes.enable |> intel_hdmi_infoframe_enable(DP_SDP_VSC);
> +	vsc->sdp_type = DP_SDP_VSC;
> +	intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
> +					 &crtc_state->infoframes.vsc);
> +}
> +
>  int
>  intel_dp_compute_config(struct intel_encoder *encoder,
>  			struct intel_crtc_state *pipe_config, @@ -2477,6 +2568,7
> @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  		intel_dp_set_clock(encoder, pipe_config);
> 
>  	intel_psr_compute_config(intel_dp, pipe_config);
> +	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
> 
>  	return 0;
>  }
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

RE: [PATCH v3 02/17] drm/i915/dp: Add compute routine for DP VSC SDP

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 02/17] drm/i915/dp: Add compute routine for DP VSC SDP
> 
> In order to support state readout for DP VSC SDP, we need to have a structure which
> holds DP VSC SDP payload data such as "union hdmi_infoframe drm" which is used
> for DRM infoframe.
> It adds a struct drm_dp_vsc_sdp vsc to intel_crtc_state.infoframes.
> 
> And it stores computed dp vsc sdp to infoframes.vsc of crtc state.
> While computing we'll also fill out the inforames.enable bitmask appropriately.
> 
> The compute routine follows DP 1.4 spec [Table 2-117: VSC SDP Payload for
> DB16 through DB18].
> 
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
>

With the structure names updated, this looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_dp.c       | 92 +++++++++++++++++++
>  2 files changed, 93 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 33ba93863488..6633c1061670 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1021,6 +1021,7 @@ struct intel_crtc_state {
>  		union hdmi_infoframe spd;
>  		union hdmi_infoframe hdmi;
>  		union hdmi_infoframe drm;
> +		struct drm_dp_vsc_sdp vsc;
>  	} infoframes;
> 
>  	/* HDMI scrambling status */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index f4dede6253f8..2bdc43c80e03 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2372,6 +2372,97 @@ static bool intel_dp_port_has_audio(struct
> drm_i915_private *dev_priv,
>  	return true;
>  }
> 
> +static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state
> *crtc_state,
> +					     const struct drm_connector_state
> *conn_state,
> +					     struct drm_dp_vsc_sdp *vsc)
> +{
> +	/*
> +	 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> +	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> +	 * Colorimetry Format indication.
> +	 */
> +	vsc->revision = 0x5;
> +	vsc->length = 0x13;
> +
> +	/* DP 1.4a spec, Table 2-120 */
> +	switch (crtc_state->output_format) {
> +	case INTEL_OUTPUT_FORMAT_YCBCR444:
> +		vsc->colorspace = DP_COLORSPACE_YUV444;
> +		break;
> +	case INTEL_OUTPUT_FORMAT_YCBCR420:
> +		vsc->colorspace = DP_COLORSPACE_YUV420;
> +		break;
> +	case INTEL_OUTPUT_FORMAT_RGB:
> +	default:
> +		vsc->colorspace = DP_COLORSPACE_RGB;
> +	}
> +
> +	switch (conn_state->colorspace) {
> +	case DRM_MODE_COLORIMETRY_BT709_YCC:
> +		vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
> +		break;
> +	case DRM_MODE_COLORIMETRY_XVYCC_601:
> +		vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
> +		break;
> +	case DRM_MODE_COLORIMETRY_XVYCC_709:
> +		vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
> +		break;
> +	case DRM_MODE_COLORIMETRY_SYCC_601:
> +		vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
> +		break;
> +	case DRM_MODE_COLORIMETRY_OPYCC_601:
> +		vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
> +		break;
> +	case DRM_MODE_COLORIMETRY_BT2020_CYCC:
> +		vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
> +		break;
> +	case DRM_MODE_COLORIMETRY_BT2020_RGB:
> +		vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
> +		break;
> +	case DRM_MODE_COLORIMETRY_BT2020_YCC:
> +		vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
> +		break;
> +	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
> +	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
> +		vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
> +		break;
> +	default:
> +		/*
> +		 * RGB->YCBCR color conversion uses the BT.709
> +		 * color space.
> +		 */
> +		if (crtc_state->output_format ==
> INTEL_OUTPUT_FORMAT_YCBCR420)
> +			vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
> +		else
> +			vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
> +		break;
> +	}
> +
> +	vsc->bpc = crtc_state->pipe_bpp / 3;
> +	/* all YCbCr are always limited range */
> +	vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
> +	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED; }
> +
> +static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
> +				     struct intel_crtc_state *crtc_state,
> +				     const struct drm_connector_state *conn_state) {
> +	struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
> +
> +	/* When PSR is enabled, VSC SDP is handled by PSR routine */
> +	if (intel_psr_enabled(intel_dp))
> +		return;
> +
> +	if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
> +		return;
> +
> +	crtc_state->infoframes.enable |=
> intel_hdmi_infoframe_enable(DP_SDP_VSC);
> +	vsc->sdp_type = DP_SDP_VSC;
> +	intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
> +					 &crtc_state->infoframes.vsc);
> +}
> +
>  int
>  intel_dp_compute_config(struct intel_encoder *encoder,
>  			struct intel_crtc_state *pipe_config, @@ -2477,6 +2568,7
> @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  		intel_dp_set_clock(encoder, pipe_config);
> 
>  	intel_psr_compute_config(intel_dp, pipe_config);
> +	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
> 
>  	return 0;
>  }
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Intel-gfx] [PATCH v3 02/17] drm/i915/dp: Add compute routine for DP VSC SDP

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 02/17] drm/i915/dp: Add compute routine for DP VSC SDP
> 
> In order to support state readout for DP VSC SDP, we need to have a structure which
> holds DP VSC SDP payload data such as "union hdmi_infoframe drm" which is used
> for DRM infoframe.
> It adds a struct drm_dp_vsc_sdp vsc to intel_crtc_state.infoframes.
> 
> And it stores computed dp vsc sdp to infoframes.vsc of crtc state.
> While computing we'll also fill out the inforames.enable bitmask appropriately.
> 
> The compute routine follows DP 1.4 spec [Table 2-117: VSC SDP Payload for
> DB16 through DB18].
> 
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
>

With the structure names updated, this looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_dp.c       | 92 +++++++++++++++++++
>  2 files changed, 93 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 33ba93863488..6633c1061670 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1021,6 +1021,7 @@ struct intel_crtc_state {
>  		union hdmi_infoframe spd;
>  		union hdmi_infoframe hdmi;
>  		union hdmi_infoframe drm;
> +		struct drm_dp_vsc_sdp vsc;
>  	} infoframes;
> 
>  	/* HDMI scrambling status */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index f4dede6253f8..2bdc43c80e03 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2372,6 +2372,97 @@ static bool intel_dp_port_has_audio(struct
> drm_i915_private *dev_priv,
>  	return true;
>  }
> 
> +static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state
> *crtc_state,
> +					     const struct drm_connector_state
> *conn_state,
> +					     struct drm_dp_vsc_sdp *vsc)
> +{
> +	/*
> +	 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> +	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> +	 * Colorimetry Format indication.
> +	 */
> +	vsc->revision = 0x5;
> +	vsc->length = 0x13;
> +
> +	/* DP 1.4a spec, Table 2-120 */
> +	switch (crtc_state->output_format) {
> +	case INTEL_OUTPUT_FORMAT_YCBCR444:
> +		vsc->colorspace = DP_COLORSPACE_YUV444;
> +		break;
> +	case INTEL_OUTPUT_FORMAT_YCBCR420:
> +		vsc->colorspace = DP_COLORSPACE_YUV420;
> +		break;
> +	case INTEL_OUTPUT_FORMAT_RGB:
> +	default:
> +		vsc->colorspace = DP_COLORSPACE_RGB;
> +	}
> +
> +	switch (conn_state->colorspace) {
> +	case DRM_MODE_COLORIMETRY_BT709_YCC:
> +		vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
> +		break;
> +	case DRM_MODE_COLORIMETRY_XVYCC_601:
> +		vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
> +		break;
> +	case DRM_MODE_COLORIMETRY_XVYCC_709:
> +		vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
> +		break;
> +	case DRM_MODE_COLORIMETRY_SYCC_601:
> +		vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
> +		break;
> +	case DRM_MODE_COLORIMETRY_OPYCC_601:
> +		vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
> +		break;
> +	case DRM_MODE_COLORIMETRY_BT2020_CYCC:
> +		vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
> +		break;
> +	case DRM_MODE_COLORIMETRY_BT2020_RGB:
> +		vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
> +		break;
> +	case DRM_MODE_COLORIMETRY_BT2020_YCC:
> +		vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
> +		break;
> +	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
> +	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
> +		vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
> +		break;
> +	default:
> +		/*
> +		 * RGB->YCBCR color conversion uses the BT.709
> +		 * color space.
> +		 */
> +		if (crtc_state->output_format ==
> INTEL_OUTPUT_FORMAT_YCBCR420)
> +			vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
> +		else
> +			vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
> +		break;
> +	}
> +
> +	vsc->bpc = crtc_state->pipe_bpp / 3;
> +	/* all YCbCr are always limited range */
> +	vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
> +	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED; }
> +
> +static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
> +				     struct intel_crtc_state *crtc_state,
> +				     const struct drm_connector_state *conn_state) {
> +	struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
> +
> +	/* When PSR is enabled, VSC SDP is handled by PSR routine */
> +	if (intel_psr_enabled(intel_dp))
> +		return;
> +
> +	if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
> +		return;
> +
> +	crtc_state->infoframes.enable |=
> intel_hdmi_infoframe_enable(DP_SDP_VSC);
> +	vsc->sdp_type = DP_SDP_VSC;
> +	intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
> +					 &crtc_state->infoframes.vsc);
> +}
> +
>  int
>  intel_dp_compute_config(struct intel_encoder *encoder,
>  			struct intel_crtc_state *pipe_config, @@ -2477,6 +2568,7
> @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  		intel_dp_set_clock(encoder, pipe_config);
> 
>  	intel_psr_compute_config(intel_dp, pipe_config);
> +	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
> 
>  	return 0;
>  }
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

RE: [PATCH v3 03/17] drm/i915/dp: Add compute routine for DP HDR Metadata Infoframe SDP

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 03/17] drm/i915/dp: Add compute routine for DP HDR Metadata
> Infoframe SDP
> 
> It stores computed dp hdr metadata infoframe sdp to infoframes.drm of crtc state.
> It referenced intel_hdmi_compute_drm_infoframe().
> 
> While computing, we'll also fill out the inforames.enable bitmask appropriately.

Typo in infoframes

With the above fixed, this is
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> 
> v2: Wrap a long line.
> 
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 2bdc43c80e03..b265b5c599f2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2463,6 +2463,27 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp
> *intel_dp,
>  					 &crtc_state->infoframes.vsc);
>  }
> 
> +static void
> +intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_crtc_state
> *crtc_state,
> +					    const struct drm_connector_state
> *conn_state) {
> +	int ret;
> +	struct hdmi_drm_infoframe *drm_infoframe > +&crtc_state->infoframes.drm.drm;
> +
> +	if (!conn_state->hdr_output_metadata)
> +		return;
> +
> +	ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
> +
> +	if (ret) {
> +		DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
> +		return;
> +	}
> +
> +	crtc_state->infoframes.enable |> +
> 	intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
> +}
> +
>  int
>  intel_dp_compute_config(struct intel_encoder *encoder,
>  			struct intel_crtc_state *pipe_config, @@ -2569,6 +2590,7
> @@ intel_dp_compute_config(struct intel_encoder *encoder,
> 
>  	intel_psr_compute_config(intel_dp, pipe_config);
>  	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
> +	intel_dp_compute_hdr_metadata_infoframe_sdp(pipe_config, conn_state);
> 
>  	return 0;
>  }
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

RE: [PATCH v3 03/17] drm/i915/dp: Add compute routine for DP HDR Metadata Infoframe SDP

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 03/17] drm/i915/dp: Add compute routine for DP HDR Metadata
> Infoframe SDP
> 
> It stores computed dp hdr metadata infoframe sdp to infoframes.drm of crtc state.
> It referenced intel_hdmi_compute_drm_infoframe().
> 
> While computing, we'll also fill out the inforames.enable bitmask appropriately.

Typo in infoframes

With the above fixed, this is
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> 
> v2: Wrap a long line.
> 
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 2bdc43c80e03..b265b5c599f2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2463,6 +2463,27 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp
> *intel_dp,
>  					 &crtc_state->infoframes.vsc);
>  }
> 
> +static void
> +intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_crtc_state
> *crtc_state,
> +					    const struct drm_connector_state
> *conn_state) {
> +	int ret;
> +	struct hdmi_drm_infoframe *drm_infoframe =
> +&crtc_state->infoframes.drm.drm;
> +
> +	if (!conn_state->hdr_output_metadata)
> +		return;
> +
> +	ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
> +
> +	if (ret) {
> +		DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
> +		return;
> +	}
> +
> +	crtc_state->infoframes.enable |=
> +
> 	intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
> +}
> +
>  int
>  intel_dp_compute_config(struct intel_encoder *encoder,
>  			struct intel_crtc_state *pipe_config, @@ -2569,6 +2590,7
> @@ intel_dp_compute_config(struct intel_encoder *encoder,
> 
>  	intel_psr_compute_config(intel_dp, pipe_config);
>  	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
> +	intel_dp_compute_hdr_metadata_infoframe_sdp(pipe_config, conn_state);
> 
>  	return 0;
>  }
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Intel-gfx] [PATCH v3 03/17] drm/i915/dp: Add compute routine for DP HDR Metadata Infoframe SDP

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 03/17] drm/i915/dp: Add compute routine for DP HDR Metadata
> Infoframe SDP
> 
> It stores computed dp hdr metadata infoframe sdp to infoframes.drm of crtc state.
> It referenced intel_hdmi_compute_drm_infoframe().
> 
> While computing, we'll also fill out the inforames.enable bitmask appropriately.

Typo in infoframes

With the above fixed, this is
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> 
> v2: Wrap a long line.
> 
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 2bdc43c80e03..b265b5c599f2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2463,6 +2463,27 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp
> *intel_dp,
>  					 &crtc_state->infoframes.vsc);
>  }
> 
> +static void
> +intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_crtc_state
> *crtc_state,
> +					    const struct drm_connector_state
> *conn_state) {
> +	int ret;
> +	struct hdmi_drm_infoframe *drm_infoframe =
> +&crtc_state->infoframes.drm.drm;
> +
> +	if (!conn_state->hdr_output_metadata)
> +		return;
> +
> +	ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
> +
> +	if (ret) {
> +		DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
> +		return;
> +	}
> +
> +	crtc_state->infoframes.enable |=
> +
> 	intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
> +}
> +
>  int
>  intel_dp_compute_config(struct intel_encoder *encoder,
>  			struct intel_crtc_state *pipe_config, @@ -2569,6 +2590,7
> @@ intel_dp_compute_config(struct intel_encoder *encoder,
> 
>  	intel_psr_compute_config(intel_dp, pipe_config);
>  	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
> +	intel_dp_compute_hdr_metadata_infoframe_sdp(pipe_config, conn_state);
> 
>  	return 0;
>  }
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

RE: [PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs (Secondary Data Packet)

[Shankar, Uma]

DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogZHJpLWRldmVsIDxkcmkt
ZGV2ZWwtYm91bmNlc0BsaXN0cy5mcmVlZGVza3RvcC5vcmc+IE9uIEJlaGFsZiBPZiBHd2FuLQ0K
PiBneWVvbmcgTXVuDQo+IFNlbnQ6IFR1ZXNkYXksIEZlYnJ1YXJ5IDQsIDIwMjAgNDo1MCBBTQ0K
PiBUbzogaW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZw0KPiBDYzogbGludXgtZmJkZXZA
dmdlci5rZXJuZWwub3JnOyBkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnDQo+IFN1Ympl
Y3Q6IFtQQVRDSCB2MyAwNC8xN10gZHJtL2k5MTUvZHA6IEFkZCB3cml0aW5nIG9mIERQIFNEUHMg
KFNlY29uZGFyeSBEYXRhDQo+IFBhY2tldCkNCg0KRHJvcCB0aGluZ3MgaW4gKCksIG5vdCBuZWVk
ZWQuDQoNCj4gSXQgYWRkcyByb3V0aW5lcyB0aGF0IHdyaXRlIERQIFZTQyBTRFAgYW5kIERQIEhE
UiBNZXRhZGF0YSBJbmZvZnJhbWUgU0RQLg0KPiBJbiBvcmRlciB0byBwYWNrIERQIFZTQyBTRFAs
IGl0IGFkZHMgaW50ZWxfZHBfdnNjX3NkcF9wYWNrKCkgZnVuY3Rpb24uDQo+IEl0IGZvbGxvd3Mg
RFAgMS40YSBzcGVjLiBbVGFibGUgMi0xMTY6IFZTQyBTRFAgSGVhZGVyIEJ5dGVzXSBhbmQgW1Rh
YmxlIDItMTE3OiBWU0MNCj4gU0RQIFBheWxvYWQgZm9yIERCMTYgdGhyb3VnaCBEQjE4XQ0KPiAN
Cj4gSW4gb3JkZXIgdG8gcGFjayBEUCBIRFIgTWV0YWRhdGEgSW5mb2ZyYW1lIFNEUCwgaXQgYWRk
cw0KPiBpbnRlbF9kcF9oZHJfbWV0YWRhdGFfaW5mb2ZyYW1lX3NkcF9wYWNrKCkgZnVuY3Rpb24u
DQo+IEFuZCBpdCBmb2xsb3dzIERQIDEuNGEgc3BlYy4NCj4gKFtUYWJsZSAyLTEyNTogSU5GT0ZS
QU1FIFNEUCB2MS4yIEhlYWRlciBCeXRlc10gYW5kIFtUYWJsZSAyLTEyNjogSU5GT0ZSQU1FDQo+
IFNEUCB2MS4yIFBheWxvYWQgRGF0YSBCeXRlcyAtIERCMCB0aHJvdWdoIERCMzFdKSBhbmQgQ1RB
LTg2MS1HIHNwZWMuIFtUYWJsZS00Mg0KPiBEeW5hbWljIFJhbmdlIGFuZCBNYXN0ZXJpbmcgSW5m
b0ZyYW1lXS4NCj4gDQo+IEEgbWFjaGFuaXNtIGFuZCBhIG5hbWluZyBydWxlIG9mIGludGVsX2Rw
X3NldF9pbmZvZnJhbWVzKCkgZnVuY3Rpb24gcmVmZXJlbmNlcw0KDQpUeXBvIGluIG1lY2hhbmlz
bS4NCg0KPiBpbnRlbF9lbmNvZGVyLT5zZXRfaW5mb2ZyYW1lcygpIG9mIGludGVsX2hkbWkuYyAu
DQo+IFZTQyBTRFAgaXMgdXNlZCBmb3IgUFNSIGFuZCBQaXhlbCBFbmNvZGluZyBhbmQgQ29sb3Jp
bWV0cnkgRm9ybWF0cyBjYXNlcy4NCj4gQmVjYXVzZSBQU1Igcm91dGluZSBoYXMgaXRzIG93biBy
b3V0aW5lIG9mIHdyaXRpbmcgYSBWU0MgU0RQLCB3aGVuIHRoZSBQU1IgaXMNCj4gZW5hYmxlZCwg
aW50ZWxfZHBfc2V0X2luZm9mcmFtZXMoKSBkb2VzIG5vdCB3cml0ZSBhIFZTQyBTRFAuDQo+IA0K
PiB2MzoNCj4gICAtIEV4cGxpY2l0bHkgZGlzYWJsZSB1bnVzZWQgRElQcyAoQVZJLCBHQ1AsIFZT
LCBTUEQsIERSTS4gVGhleSB3aWxsIGJlDQo+ICAgICB1c2VkIGZvciBIRE1JKSwgd2hlbiBpbnRl
bF9kcF9zZXRfaW5mb2ZyYW1lcygpIGZ1bmN0aW9uIHdpbGwgYmUgY2FsbGVkLg0KPiAgIC0gUmVw
bGFjZSBhIHN0cnVjdHVyZSBuYW1lIHRvIGRybV9kcF92c2Nfc2RwIGZyb20gaW50ZWxfZHBfdnNj
X3NkcC4NCj4gDQo+IFNpZ25lZC1vZmYtYnk6IEd3YW4tZ3llb25nIE11biA8Z3dhbi1neWVvbmcu
bXVuQGludGVsLmNvbT4NCj4gLS0tDQo+ICBkcml2ZXJzL2dwdS9kcm0vaTkxNS9kaXNwbGF5L2lu
dGVsX2RwLmMgfCAxOTQgKysrKysrKysrKysrKysrKysrKysrKysrDQo+ICBkcml2ZXJzL2dwdS9k
cm0vaTkxNS9kaXNwbGF5L2ludGVsX2RwLmggfCAgIDMgKw0KPiAgMiBmaWxlcyBjaGFuZ2VkLCAx
OTcgaW5zZXJ0aW9ucygrKQ0KPiANCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1
L2Rpc3BsYXkvaW50ZWxfZHAuYw0KPiBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2Rpc3BsYXkvaW50
ZWxfZHAuYw0KPiBpbmRleCBiMjY1YjVjNTk5ZjIuLmRkN2U1NTg4MDAxZSAxMDA2NDQNCj4gLS0t
IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9kcC5jDQo+ICsrKyBiL2RyaXZl
cnMvZ3B1L2RybS9pOTE1L2Rpc3BsYXkvaW50ZWxfZHAuYw0KPiBAQCAtNDczMSw2ICs0NzMxLDIw
MCBAQCBpbnRlbF9kcF9uZWVkc192c2Nfc2RwKGNvbnN0IHN0cnVjdCBpbnRlbF9jcnRjX3N0YXRl
DQo+ICpjcnRjX3N0YXRlLA0KPiAgCXJldHVybiBmYWxzZTsNCj4gIH0NCj4gDQo+ICtzdGF0aWMg
c3NpemVfdCBpbnRlbF9kcF92c2Nfc2RwX3BhY2soY29uc3Qgc3RydWN0IGRybV9kcF92c2Nfc2Rw
ICp2c2MsDQo+ICsJCQkJICAgICBzdHJ1Y3QgZHBfc2RwICpzZHAsIHNpemVfdCBzaXplKSB7DQo+
ICsJc2l6ZV90IGxlbmd0aCA9IHNpemVvZihzdHJ1Y3QgZHBfc2RwKTsNCj4gKw0KPiArCWlmIChz
aXplIDwgbGVuZ3RoKQ0KPiArCQlyZXR1cm4gLUVOT1NQQzsNCj4gKw0KPiArCW1lbXNldChzZHAs
IDAsIHNpemUpOw0KPiArDQo+ICsJLyoNCj4gKwkgKiBQcmVwYXJlIFZTQyBIZWFkZXIgZm9yIFNV
IGFzIHBlciBEUCAxLjRhIHNwZWMsIFRhYmxlIDItMTE5DQo+ICsJICogVlNDIFNEUCBIZWFkZXIg
Qnl0ZXMNCj4gKwkgKi8NCj4gKwlzZHAtPnNkcF9oZWFkZXIuSEIwID0gMDsgLyogU2Vjb25kYXJ5
LURhdGEgUGFja2V0IElEID0gMCAqLw0KPiArCXNkcC0+c2RwX2hlYWRlci5IQjEgPSB2c2MtPnNk
cF90eXBlOyAvKiBTZWNvbmRhcnktZGF0YSBQYWNrZXQgVHlwZSAqLw0KPiArCXNkcC0+c2RwX2hl
YWRlci5IQjIgPSB2c2MtPnJldmlzaW9uOyAvKiBSZXZpc2lvbiBOdW1iZXIgKi8NCj4gKwlzZHAt
PnNkcF9oZWFkZXIuSEIzID0gdnNjLT5sZW5ndGg7IC8qIE51bWJlciBvZiBWYWxpZCBEYXRhIEJ5
dGVzICovDQo+ICsNCj4gKwkvKiBWU0MgU0RQIFBheWxvYWQgZm9yIERCMTYgdGhyb3VnaCBEQjE4
ICovDQo+ICsJLyogUGl4ZWwgRW5jb2RpbmcgYW5kIENvbG9yaW1ldHJ5IEZvcm1hdHMgICovDQo+
ICsJc2RwLT5kYlsxNl0gPSAodnNjLT5jb2xvcnNwYWNlICYgMHhmKSA8PCA0OyAvKiBEQjE2Wzc6
NF0gKi8NCj4gKwlzZHAtPmRiWzE2XSB8PSB2c2MtPmNvbG9yaW1ldHJ5ICYgMHhmOyAvKiBEQjE2
WzM6MF0gKi8NCj4gKw0KPiArCXN3aXRjaCAodnNjLT5icGMpIHsNCj4gKwljYXNlIDg6DQo+ICsJ
CXNkcC0+ZGJbMTddID0gMHgxOyAvKiBEQjE3WzM6MF0gKi8NCj4gKwkJYnJlYWs7DQo+ICsJY2Fz
ZSAxMDoNCj4gKwkJc2RwLT5kYlsxN10gPSAweDI7DQo+ICsJCWJyZWFrOw0KPiArCWNhc2UgMTI6
DQo+ICsJCXNkcC0+ZGJbMTddID0gMHgzOw0KPiArCQlicmVhazsNCj4gKwljYXNlIDE2Og0KPiAr
CQlzZHAtPmRiWzE3XSA9IDB4NDsNCj4gKwkJYnJlYWs7DQo+ICsJZGVmYXVsdDoNCj4gKwkJTUlT
U0lOR19DQVNFKHZzYy0+YnBjKTsNCg0KNmJwYyBpcyBub3QgaGFuZGxlZCBoZXJlLCBhZGQgdGhh
dCBhcyB3ZWxsLg0KDQo+ICsJCWJyZWFrOw0KPiArCX0NCj4gKwkvKiBEeW5hbWljIFJhbmdlIGFu
ZCBDb21wb25lbnQgQml0IERlcHRoICovDQo+ICsJaWYgKHZzYy0+ZHluYW1pY19yYW5nZSA9PSBE
UF9EWU5BTUlDX1JBTkdFX0NUQSkNCj4gKwkJc2RwLT5kYlsxN10gfD0gMHg4MDsgIC8qIERCMTdb
N10gKi8NCj4gKw0KPiArCS8qIENvbnRlbnQgVHlwZSAqLw0KPiArCXNkcC0+ZGJbMThdID0gdnNj
LT5jb250ZW50X3R5cGUgJiAweDc7DQo+ICsNCj4gKwlyZXR1cm4gbGVuZ3RoOw0KPiArfQ0KPiAr
DQo+ICtzdGF0aWMgc3NpemVfdA0KPiAraW50ZWxfZHBfaGRyX21ldGFkYXRhX2luZm9mcmFtZV9z
ZHBfcGFjayhjb25zdCBzdHJ1Y3QgaGRtaV9kcm1faW5mb2ZyYW1lDQo+ICpkcm1faW5mb2ZyYW1l
LA0KPiArCQkJCQkgc3RydWN0IGRwX3NkcCAqc2RwLA0KPiArCQkJCQkgc2l6ZV90IHNpemUpDQo+
ICt7DQo+ICsJc2l6ZV90IGxlbmd0aCA9IHNpemVvZihzdHJ1Y3QgZHBfc2RwKTsNCj4gKwljb25z
dCBpbnQgaW5mb2ZyYW1lX3NpemUgPSBIRE1JX0lORk9GUkFNRV9IRUFERVJfU0laRSArDQo+IEhE
TUlfRFJNX0lORk9GUkFNRV9TSVpFOw0KPiArCXVuc2lnbmVkIGNoYXIgYnVmW0hETUlfSU5GT0ZS
QU1FX0hFQURFUl9TSVpFICsNCj4gSERNSV9EUk1fSU5GT0ZSQU1FX1NJWkVdOw0KPiArCXNzaXpl
X3QgbGVuOw0KPiArDQo+ICsJaWYgKHNpemUgPCBsZW5ndGgpDQo+ICsJCXJldHVybiAtRU5PU1BD
Ow0KPiArDQo+ICsJbWVtc2V0KHNkcCwgMCwgc2l6ZSk7DQo+ICsNCj4gKwlsZW4gPSBoZG1pX2Ry
bV9pbmZvZnJhbWVfcGFja19vbmx5KGRybV9pbmZvZnJhbWUsIGJ1Ziwgc2l6ZW9mKGJ1ZikpOw0K
PiArCWlmIChsZW4gPCAwKSB7DQo+ICsJCURSTV9ERUJVR19LTVMoImJ1ZmZlciBzaXplIGlzIHNt
YWxsZXIgdGhhbiBoZHIgbWV0YWRhdGENCj4gaW5mb2ZyYW1lXG4iKTsNCj4gKwkJcmV0dXJuIC1F
Tk9TUEM7DQo+ICsJfQ0KPiArDQo+ICsJaWYgKGxlbiAhPSBpbmZvZnJhbWVfc2l6ZSkgew0KPiAr
CQlEUk1fREVCVUdfS01TKCJ3cm9uZyBzdGF0aWMgaGRyIG1ldGFkYXRhIHNpemVcbiIpOw0KPiAr
CQlyZXR1cm4gLUVOT1NQQzsNCj4gKwl9DQo+ICsNCj4gKwkvKg0KPiArCSAqIFNldCB1cCB0aGUg
aW5mb2ZyYW1lIHNkcCBwYWNrZXQgZm9yIEhEUiBzdGF0aWMgbWV0YWRhdGEuDQo+ICsJICogUHJl
cGFyZSBWU0MgSGVhZGVyIGZvciBTVSBhcyBwZXIgRFAgMS40YSBzcGVjLA0KPiArCSAqIFRhYmxl
IDItMTAwIGFuZCBUYWJsZSAyLTEwMQ0KPiArCSAqLw0KPiArDQo+ICsJLyogU2Vjb25kYXJ5LURh
dGEgUGFja2V0IElELCAwMGggZm9yIG5vbi1BdWRpbyBJTkZPRlJBTUUgKi8NCj4gKwlzZHAtPnNk
cF9oZWFkZXIuSEIwID0gMDsNCj4gKwkvKg0KPiArCSAqIFBhY2tldCBUeXBlIDgwaCArIE5vbi1h
dWRpbyBJTkZPRlJBTUUgVHlwZSB2YWx1ZQ0KPiArCSAqIEhETUlfSU5GT0ZSQU1FX1RZUEVfRFJN
OiAweDg3DQo+ICsJICogLSA4MGggKyBOb24tYXVkaW8gSU5GT0ZSQU1FIFR5cGUgdmFsdWUNCj4g
KwkgKiAtIEluZm9GcmFtZSBUeXBlOiAweDA3DQo+ICsJICogICAgW0NUQS04NjEtRyBUYWJsZS00
MiBEeW5hbWljIFJhbmdlIGFuZCBNYXN0ZXJpbmcgSW5mb0ZyYW1lXQ0KPiArCSAqLw0KPiArCXNk
cC0+c2RwX2hlYWRlci5IQjEgPSBkcm1faW5mb2ZyYW1lLT50eXBlOw0KPiArCS8qDQo+ICsJICog
TGVhc3QgU2lnbmlmaWNhbnQgRWlnaHQgQml0cyBvZiAoRGF0YSBCeXRlIENvdW50IOKAkyAxKQ0K
PiArCSAqIGluZm9mcmFtZV9zaXplIC0gMQ0KPiArCSAqLw0KPiArCXNkcC0+c2RwX2hlYWRlci5I
QjIgPSAweDFEOw0KPiArCS8qIElORk9GUkFNRSBTRFAgVmVyc2lvbiBOdW1iZXIgKi8NCj4gKwlz
ZHAtPnNkcF9oZWFkZXIuSEIzID0gKDB4MTMgPDwgMik7DQo+ICsJLyogQ1RBIEhlYWRlciBCeXRl
IDIgKElORk9GUkFNRSBWZXJzaW9uIE51bWJlcikgKi8NCj4gKwlzZHAtPmRiWzBdID0gZHJtX2lu
Zm9mcmFtZS0+dmVyc2lvbjsNCj4gKwkvKiBDVEEgSGVhZGVyIEJ5dGUgMyAoTGVuZ3RoIG9mIElO
Rk9GUkFNRSk6DQo+IEhETUlfRFJNX0lORk9GUkFNRV9TSVpFICovDQo+ICsJc2RwLT5kYlsxXSA9
IGRybV9pbmZvZnJhbWUtPmxlbmd0aDsNCj4gKwkvKg0KPiArCSAqIENvcHkgSERNSV9EUk1fSU5G
T0ZSQU1FX1NJWkUgc2l6ZSBmcm9tIGEgYnVmZmVyIGFmdGVyDQoNCkNvbW1lbnQgTG9va3MgaW5j
b21wbGV0ZS4NCg0KPiArCSAqLw0KPiArCUJVSUxEX0JVR19PTihzaXplb2Yoc2RwLT5kYikgPCBI
RE1JX0RSTV9JTkZPRlJBTUVfU0laRSArIDIpOw0KPiArCW1lbWNweSgmc2RwLT5kYlsyXSwgJmJ1
ZltIRE1JX0lORk9GUkFNRV9IRUFERVJfU0laRV0sDQo+ICsJICAgICAgIEhETUlfRFJNX0lORk9G
UkFNRV9TSVpFKTsNCj4gKw0KPiArCS8qDQo+ICsJICogU2l6ZSBvZiBEUCBpbmZvZnJhbWUgc2Rw
IHBhY2tldCBmb3IgSERSIHN0YXRpYyBtZXRhZGF0YSBpcyBjb25zaXN0IG9mDQoNCkRyb3AgImlz
Ig0KDQo+ICsJICogLSBEUCBTRFAgSGVhZGVyKHN0cnVjdCBkcF9zZHBfaGVhZGVyKTogNCBieXRl
cw0KPiArCSAqIC0gVHdvIERhdGEgQmxvY2tzOiAyIGJ5dGVzDQo+ICsJICogICAgQ1RBIEhlYWRl
ciBCeXRlMiAoSU5GT0ZSQU1FIFZlcnNpb24gTnVtYmVyKQ0KPiArCSAqICAgIENUQSBIZWFkZXIg
Qnl0ZTMgKExlbmd0aCBvZiBJTkZPRlJBTUUpDQo+ICsJICogLSBIRE1JX0RSTV9JTkZPRlJBTUVf
U0laRTogMjYgYnl0ZXMNCj4gKwkgKg0KPiArCSAqIFByaW9yIHRvIEdFTjExJ3MgR01QIHJlZ2lz
dGVyIHNpemUgaXMgaWRlbnRpY2FsIHRvIERQIEhEUiBzdGF0aWMgbWV0YWRhdGENCj4gKwkgKiBp
bmZvZnJhbWUgc2l6ZS4gQnV0IEdFTjExKyBoYXMgbGFyZ2VyIHRoYW4gdGhhdCBzaXplLCB3cml0
ZV9pbmZvZnJhbWUNCj4gKwkgKiB3aWxsIHBhZCByZXN0IG9mIHRoZSBzaXplLg0KPiArCSAqLw0K
PiArCXJldHVybiBzaXplb2Yoc3RydWN0IGRwX3NkcF9oZWFkZXIpICsgMiArIEhETUlfRFJNX0lO
Rk9GUkFNRV9TSVpFOyB9DQo+ICsNCj4gK3N0YXRpYyB2b2lkIGludGVsX3dyaXRlX2RwX3NkcChz
dHJ1Y3QgaW50ZWxfZW5jb2RlciAqZW5jb2RlciwNCj4gKwkJCSAgICAgICBjb25zdCBzdHJ1Y3Qg
aW50ZWxfY3J0Y19zdGF0ZSAqY3J0Y19zdGF0ZSwNCj4gKwkJCSAgICAgICB1bnNpZ25lZCBpbnQg
dHlwZSkNCj4gK3sNCj4gKwlzdHJ1Y3QgaW50ZWxfZGlnaXRhbF9wb3J0ICppbnRlbF9kaWdfcG9y
dCA9IGVuY190b19kaWdfcG9ydChlbmNvZGVyKTsNCj4gKwlzdHJ1Y3QgZHBfc2RwIHNkcCA9IHt9
Ow0KPiArCXNzaXplX3QgbGVuOw0KPiArDQo+ICsJaWYgKChjcnRjX3N0YXRlLT5pbmZvZnJhbWVz
LmVuYWJsZSAmDQo+ICsJICAgICBpbnRlbF9oZG1pX2luZm9mcmFtZV9lbmFibGUodHlwZSkpID09
IDApDQo+ICsJCXJldHVybjsNCj4gKw0KPiArCXN3aXRjaCAodHlwZSkgew0KPiArCWNhc2UgRFBf
U0RQX1ZTQzoNCj4gKwkJbGVuID0gaW50ZWxfZHBfdnNjX3NkcF9wYWNrKCZjcnRjX3N0YXRlLT5p
bmZvZnJhbWVzLnZzYywgJnNkcCwNCj4gKwkJCQkJICAgIHNpemVvZihzZHApKTsNCj4gKwkJYnJl
YWs7DQo+ICsJY2FzZSBIRE1JX1BBQ0tFVF9UWVBFX0dBTVVUX01FVEFEQVRBOg0KPiArCQlsZW4g
PSBpbnRlbF9kcF9oZHJfbWV0YWRhdGFfaW5mb2ZyYW1lX3NkcF9wYWNrKCZjcnRjX3N0YXRlLQ0K
PiA+aW5mb2ZyYW1lcy5kcm0uZHJtLA0KPiArCQkJCQkJCSAgICAgICAmc2RwLCBzaXplb2Yoc2Rw
KSk7DQo+ICsJCWJyZWFrOw0KPiArCWRlZmF1bHQ6DQo+ICsJCU1JU1NJTkdfQ0FTRSh0eXBlKTsN
Cj4gKwkJYnJlYWs7DQo+ICsJfQ0KPiArDQo+ICsJaWYgKFdBUk5fT04obGVuIDwgMCkpDQo+ICsJ
CXJldHVybjsNCj4gKw0KPiArCWludGVsX2RpZ19wb3J0LT53cml0ZV9pbmZvZnJhbWUoZW5jb2Rl
ciwgY3J0Y19zdGF0ZSwgdHlwZSwgJnNkcCwgbGVuKTsNCj4gK30NCj4gKw0KPiArdm9pZCBpbnRl
bF9kcF9zZXRfaW5mb2ZyYW1lcyhzdHJ1Y3QgaW50ZWxfZW5jb2RlciAqZW5jb2RlciwNCj4gKwkJ
CSAgICAgYm9vbCBlbmFibGUsDQo+ICsJCQkgICAgIGNvbnN0IHN0cnVjdCBpbnRlbF9jcnRjX3N0
YXRlICpjcnRjX3N0YXRlLA0KPiArCQkJICAgICBjb25zdCBzdHJ1Y3QgZHJtX2Nvbm5lY3Rvcl9z
dGF0ZSAqY29ubl9zdGF0ZSkgew0KPiArCXN0cnVjdCBkcm1faTkxNV9wcml2YXRlICpkZXZfcHJp
diA9IHRvX2k5MTUoZW5jb2Rlci0+YmFzZS5kZXYpOw0KPiArCXN0cnVjdCBpbnRlbF9kcCAqaW50
ZWxfZHAgPSBlbmNfdG9faW50ZWxfZHAoZW5jb2Rlcik7DQo+ICsJaTkxNV9yZWdfdCByZWcgPSBI
U1dfVFZJREVPX0RJUF9DVEwoY3J0Y19zdGF0ZS0+Y3B1X3RyYW5zY29kZXIpOw0KPiArCXUzMiBk
aXBfZW5hYmxlID0gVklERU9fRElQX0VOQUJMRV9BVklfSFNXIHwNCj4gVklERU9fRElQX0VOQUJM
RV9HQ1BfSFNXIHwNCj4gKwkJCSBWSURFT19ESVBfRU5BQkxFX1ZTX0hTVyB8DQo+IFZJREVPX0RJ
UF9FTkFCTEVfR01QX0hTVyB8DQo+ICsJCQkgVklERU9fRElQX0VOQUJMRV9TUERfSFNXIHwNCj4g
VklERU9fRElQX0VOQUJMRV9EUk1fR0xLOw0KPiArCXUzMiB2YWwgPSBJOTE1X1JFQUQocmVnKTsN
Cj4gKw0KPiArCS8qIFRPRE86IEFkZCBEU0MgY2FzZSAoRElQX0VOQUJMRV9QUFMpICovDQo+ICsJ
LyogV2hlbiBQU1IgaXMgZW5hYmxlZCwgdGhpcyByb3V0aW5lIGRvZXNuJ3QgZGlzYWJsZSBWU0Mg
RElQICovDQo+ICsJaWYgKGludGVsX3Bzcl9lbmFibGVkKGludGVsX2RwKSkNCj4gKwkJdmFsICY9
IH5kaXBfZW5hYmxlOw0KPiArCWVsc2UNCj4gKwkJdmFsICY9IH4oZGlwX2VuYWJsZSB8IFZJREVP
X0RJUF9FTkFCTEVfVlNDX0hTVyk7DQoNCmRpcF9lbmFibGUgaGFzIFZJREVPX0RJUF9FTkFCTEVf
VlNDX0hTVyBhbHJlYWR5IGluIGl0LiBQbGVhc2UgZml4IHRoaXMuDQoNCj4gKw0KPiArCWlmICgh
ZW5hYmxlKSB7DQo+ICsJCUk5MTVfV1JJVEUocmVnLCB2YWwpOw0KPiArCQlQT1NUSU5HX1JFQUQo
cmVnKTsNCj4gKwkJcmV0dXJuOw0KPiArCX0NCj4gKw0KPiArCUk5MTVfV1JJVEUocmVnLCB2YWwp
Ow0KPiArCVBPU1RJTkdfUkVBRChyZWcpOw0KPiArDQo+ICsJLyogV2hlbiBQU1IgaXMgZW5hYmxl
ZCwgVlNDIFNEUCBpcyBoYW5kbGVkIGJ5IFBTUiByb3V0aW5lICovDQo+ICsJaWYgKCFpbnRlbF9w
c3JfZW5hYmxlZChpbnRlbF9kcCkpDQo+ICsJCWludGVsX3dyaXRlX2RwX3NkcChlbmNvZGVyLCBj
cnRjX3N0YXRlLCBEUF9TRFBfVlNDKTsNCj4gKw0KPiArCWludGVsX3dyaXRlX2RwX3NkcChlbmNv
ZGVyLCBjcnRjX3N0YXRlLA0KPiArSERNSV9QQUNLRVRfVFlQRV9HQU1VVF9NRVRBREFUQSk7IH0N
Cj4gKw0KPiAgc3RhdGljIHZvaWQNCj4gIGludGVsX2RwX3NldHVwX3ZzY19zZHAoc3RydWN0IGlu
dGVsX2RwICppbnRlbF9kcCwNCj4gIAkJICAgICAgIGNvbnN0IHN0cnVjdCBpbnRlbF9jcnRjX3N0
YXRlICpjcnRjX3N0YXRlLCBkaWZmIC0tZ2l0DQo+IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlz
cGxheS9pbnRlbF9kcC5oDQo+IGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9k
cC5oDQo+IGluZGV4IDNkYTE2NjA1NDc4OC4uMGRjMDlhNDYzZWUxIDEwMDY0NA0KPiAtLS0gYS9k
cml2ZXJzL2dwdS9kcm0vaTkxNS9kaXNwbGF5L2ludGVsX2RwLmgNCj4gKysrIGIvZHJpdmVycy9n
cHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9kcC5oDQo+IEBAIC0xMTYsNiArMTE2LDkgQEAgdm9p
ZCBpbnRlbF9kcF92c2NfZW5hYmxlKHN0cnVjdCBpbnRlbF9kcCAqaW50ZWxfZHAsICB2b2lkDQo+
IGludGVsX2RwX2hkcl9tZXRhZGF0YV9lbmFibGUoc3RydWN0IGludGVsX2RwICppbnRlbF9kcCwN
Cj4gIAkJCQkgIGNvbnN0IHN0cnVjdCBpbnRlbF9jcnRjX3N0YXRlICpjcnRjX3N0YXRlLA0KPiAg
CQkJCSAgY29uc3Qgc3RydWN0IGRybV9jb25uZWN0b3Jfc3RhdGUgKmNvbm5fc3RhdGUpOw0KPiAr
dm9pZCBpbnRlbF9kcF9zZXRfaW5mb2ZyYW1lcyhzdHJ1Y3QgaW50ZWxfZW5jb2RlciAqZW5jb2Rl
ciwgYm9vbCBlbmFibGUsDQo+ICsJCQkgICAgIGNvbnN0IHN0cnVjdCBpbnRlbF9jcnRjX3N0YXRl
ICpjcnRjX3N0YXRlLA0KPiArCQkJICAgICBjb25zdCBzdHJ1Y3QgZHJtX2Nvbm5lY3Rvcl9zdGF0
ZSAqY29ubl9zdGF0ZSk7DQo+ICBib29sIGludGVsX2RpZ2l0YWxfcG9ydF9jb25uZWN0ZWQoc3Ry
dWN0IGludGVsX2VuY29kZXIgKmVuY29kZXIpOw0KPiANCj4gIHN0YXRpYyBpbmxpbmUgdW5zaWdu
ZWQgaW50IGludGVsX2RwX3VudXNlZF9sYW5lX21hc2soaW50IGxhbmVfY291bnQpDQo+IC0tDQo+
IDIuMjQuMQ0KPiANCj4gX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f
X19fX18NCj4gZHJpLWRldmVsIG1haWxpbmcgbGlzdA0KPiBkcmktZGV2ZWxAbGlzdHMuZnJlZWRl
c2t0b3Aub3JnDQo+IGh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGlu
Zm8vZHJpLWRldmVsDQo

RE: [PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs (Secondary Data Packet)

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs (Secondary Data
> Packet)

Drop things in (), not needed.

> It adds routines that write DP VSC SDP and DP HDR Metadata Infoframe SDP.
> In order to pack DP VSC SDP, it adds intel_dp_vsc_sdp_pack() function.
> It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and [Table 2-117: VSC
> SDP Payload for DB16 through DB18]
> 
> In order to pack DP HDR Metadata Infoframe SDP, it adds
> intel_dp_hdr_metadata_infoframe_sdp_pack() function.
> And it follows DP 1.4a spec.
> ([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and [Table 2-126: INFOFRAME
> SDP v1.2 Payload Data Bytes - DB0 through DB31]) and CTA-861-G spec. [Table-42
> Dynamic Range and Mastering InfoFrame].
> 
> A machanism and a naming rule of intel_dp_set_infoframes() function references

Typo in mechanism.

> intel_encoder->set_infoframes() of intel_hdmi.c .
> VSC SDP is used for PSR and Pixel Encoding and Colorimetry Formats cases.
> Because PSR routine has its own routine of writing a VSC SDP, when the PSR is
> enabled, intel_dp_set_infoframes() does not write a VSC SDP.
> 
> v3:
>   - Explicitly disable unused DIPs (AVI, GCP, VS, SPD, DRM. They will be
>     used for HDMI), when intel_dp_set_infoframes() function will be called.
>   - Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp.
> 
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 194 ++++++++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_dp.h |   3 +
>  2 files changed, 197 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index b265b5c599f2..dd7e5588001e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4731,6 +4731,200 @@ intel_dp_needs_vsc_sdp(const struct intel_crtc_state
> *crtc_state,
>  	return false;
>  }
> 
> +static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
> +				     struct dp_sdp *sdp, size_t size) {
> +	size_t length = sizeof(struct dp_sdp);
> +
> +	if (size < length)
> +		return -ENOSPC;
> +
> +	memset(sdp, 0, size);
> +
> +	/*
> +	 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
> +	 * VSC SDP Header Bytes
> +	 */
> +	sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
> +	sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
> +	sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
> +	sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
> +
> +	/* VSC SDP Payload for DB16 through DB18 */
> +	/* Pixel Encoding and Colorimetry Formats  */
> +	sdp->db[16] = (vsc->colorspace & 0xf) << 4; /* DB16[7:4] */
> +	sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
> +
> +	switch (vsc->bpc) {
> +	case 8:
> +		sdp->db[17] = 0x1; /* DB17[3:0] */
> +		break;
> +	case 10:
> +		sdp->db[17] = 0x2;
> +		break;
> +	case 12:
> +		sdp->db[17] = 0x3;
> +		break;
> +	case 16:
> +		sdp->db[17] = 0x4;
> +		break;
> +	default:
> +		MISSING_CASE(vsc->bpc);

6bpc is not handled here, add that as well.

> +		break;
> +	}
> +	/* Dynamic Range and Component Bit Depth */
> +	if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
> +		sdp->db[17] |= 0x80;  /* DB17[7] */
> +
> +	/* Content Type */
> +	sdp->db[18] = vsc->content_type & 0x7;
> +
> +	return length;
> +}
> +
> +static ssize_t
> +intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe
> *drm_infoframe,
> +					 struct dp_sdp *sdp,
> +					 size_t size)
> +{
> +	size_t length = sizeof(struct dp_sdp);
> +	const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE +
> HDMI_DRM_INFOFRAME_SIZE;
> +	unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE +
> HDMI_DRM_INFOFRAME_SIZE];
> +	ssize_t len;
> +
> +	if (size < length)
> +		return -ENOSPC;
> +
> +	memset(sdp, 0, size);
> +
> +	len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
> +	if (len < 0) {
> +		DRM_DEBUG_KMS("buffer size is smaller than hdr metadata
> infoframe\n");
> +		return -ENOSPC;
> +	}
> +
> +	if (len != infoframe_size) {
> +		DRM_DEBUG_KMS("wrong static hdr metadata size\n");
> +		return -ENOSPC;
> +	}
> +
> +	/*
> +	 * Set up the infoframe sdp packet for HDR static metadata.
> +	 * Prepare VSC Header for SU as per DP 1.4a spec,
> +	 * Table 2-100 and Table 2-101
> +	 */
> +
> +	/* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
> +	sdp->sdp_header.HB0 = 0;
> +	/*
> +	 * Packet Type 80h + Non-audio INFOFRAME Type value
> +	 * HDMI_INFOFRAME_TYPE_DRM: 0x87
> +	 * - 80h + Non-audio INFOFRAME Type value
> +	 * - InfoFrame Type: 0x07
> +	 *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
> +	 */
> +	sdp->sdp_header.HB1 = drm_infoframe->type;
> +	/*
> +	 * Least Significant Eight Bits of (Data Byte Count – 1)
> +	 * infoframe_size - 1
> +	 */
> +	sdp->sdp_header.HB2 = 0x1D;
> +	/* INFOFRAME SDP Version Number */
> +	sdp->sdp_header.HB3 = (0x13 << 2);
> +	/* CTA Header Byte 2 (INFOFRAME Version Number) */
> +	sdp->db[0] = drm_infoframe->version;
> +	/* CTA Header Byte 3 (Length of INFOFRAME):
> HDMI_DRM_INFOFRAME_SIZE */
> +	sdp->db[1] = drm_infoframe->length;
> +	/*
> +	 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after

Comment Looks incomplete.

> +	 */
> +	BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
> +	memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
> +	       HDMI_DRM_INFOFRAME_SIZE);
> +
> +	/*
> +	 * Size of DP infoframe sdp packet for HDR static metadata is consist of

Drop "is"

> +	 * - DP SDP Header(struct dp_sdp_header): 4 bytes
> +	 * - Two Data Blocks: 2 bytes
> +	 *    CTA Header Byte2 (INFOFRAME Version Number)
> +	 *    CTA Header Byte3 (Length of INFOFRAME)
> +	 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
> +	 *
> +	 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
> +	 * infoframe size. But GEN11+ has larger than that size, write_infoframe
> +	 * will pad rest of the size.
> +	 */
> +	return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE; }
> +
> +static void intel_write_dp_sdp(struct intel_encoder *encoder,
> +			       const struct intel_crtc_state *crtc_state,
> +			       unsigned int type)
> +{
> +	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
> +	struct dp_sdp sdp = {};
> +	ssize_t len;
> +
> +	if ((crtc_state->infoframes.enable &
> +	     intel_hdmi_infoframe_enable(type)) == 0)
> +		return;
> +
> +	switch (type) {
> +	case DP_SDP_VSC:
> +		len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
> +					    sizeof(sdp));
> +		break;
> +	case HDMI_PACKET_TYPE_GAMUT_METADATA:
> +		len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state-
> >infoframes.drm.drm,
> +							       &sdp, sizeof(sdp));
> +		break;
> +	default:
> +		MISSING_CASE(type);
> +		break;
> +	}
> +
> +	if (WARN_ON(len < 0))
> +		return;
> +
> +	intel_dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
> +}
> +
> +void intel_dp_set_infoframes(struct intel_encoder *encoder,
> +			     bool enable,
> +			     const struct intel_crtc_state *crtc_state,
> +			     const struct drm_connector_state *conn_state) {
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
> +	u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW |
> VIDEO_DIP_ENABLE_GCP_HSW |
> +			 VIDEO_DIP_ENABLE_VS_HSW |
> VIDEO_DIP_ENABLE_GMP_HSW |
> +			 VIDEO_DIP_ENABLE_SPD_HSW |
> VIDEO_DIP_ENABLE_DRM_GLK;
> +	u32 val = I915_READ(reg);
> +
> +	/* TODO: Add DSC case (DIP_ENABLE_PPS) */
> +	/* When PSR is enabled, this routine doesn't disable VSC DIP */
> +	if (intel_psr_enabled(intel_dp))
> +		val &= ~dip_enable;
> +	else
> +		val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);

dip_enable has VIDEO_DIP_ENABLE_VSC_HSW already in it. Please fix this.

> +
> +	if (!enable) {
> +		I915_WRITE(reg, val);
> +		POSTING_READ(reg);
> +		return;
> +	}
> +
> +	I915_WRITE(reg, val);
> +	POSTING_READ(reg);
> +
> +	/* When PSR is enabled, VSC SDP is handled by PSR routine */
> +	if (!intel_psr_enabled(intel_dp))
> +		intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
> +
> +	intel_write_dp_sdp(encoder, crtc_state,
> +HDMI_PACKET_TYPE_GAMUT_METADATA); }
> +
>  static void
>  intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
>  		       const struct intel_crtc_state *crtc_state, diff --git
> a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index 3da166054788..0dc09a463ee1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -116,6 +116,9 @@ void intel_dp_vsc_enable(struct intel_dp *intel_dp,  void
> intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
>  				  const struct intel_crtc_state *crtc_state,
>  				  const struct drm_connector_state *conn_state);
> +void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
> +			     const struct intel_crtc_state *crtc_state,
> +			     const struct drm_connector_state *conn_state);
>  bool intel_digital_port_connected(struct intel_encoder *encoder);
> 
>  static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Intel-gfx] [PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs (Secondary Data Packet)

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs (Secondary Data
> Packet)

Drop things in (), not needed.

> It adds routines that write DP VSC SDP and DP HDR Metadata Infoframe SDP.
> In order to pack DP VSC SDP, it adds intel_dp_vsc_sdp_pack() function.
> It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and [Table 2-117: VSC
> SDP Payload for DB16 through DB18]
> 
> In order to pack DP HDR Metadata Infoframe SDP, it adds
> intel_dp_hdr_metadata_infoframe_sdp_pack() function.
> And it follows DP 1.4a spec.
> ([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and [Table 2-126: INFOFRAME
> SDP v1.2 Payload Data Bytes - DB0 through DB31]) and CTA-861-G spec. [Table-42
> Dynamic Range and Mastering InfoFrame].
> 
> A machanism and a naming rule of intel_dp_set_infoframes() function references

Typo in mechanism.

> intel_encoder->set_infoframes() of intel_hdmi.c .
> VSC SDP is used for PSR and Pixel Encoding and Colorimetry Formats cases.
> Because PSR routine has its own routine of writing a VSC SDP, when the PSR is
> enabled, intel_dp_set_infoframes() does not write a VSC SDP.
> 
> v3:
>   - Explicitly disable unused DIPs (AVI, GCP, VS, SPD, DRM. They will be
>     used for HDMI), when intel_dp_set_infoframes() function will be called.
>   - Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp.
> 
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 194 ++++++++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_dp.h |   3 +
>  2 files changed, 197 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index b265b5c599f2..dd7e5588001e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4731,6 +4731,200 @@ intel_dp_needs_vsc_sdp(const struct intel_crtc_state
> *crtc_state,
>  	return false;
>  }
> 
> +static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
> +				     struct dp_sdp *sdp, size_t size) {
> +	size_t length = sizeof(struct dp_sdp);
> +
> +	if (size < length)
> +		return -ENOSPC;
> +
> +	memset(sdp, 0, size);
> +
> +	/*
> +	 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
> +	 * VSC SDP Header Bytes
> +	 */
> +	sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
> +	sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
> +	sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
> +	sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
> +
> +	/* VSC SDP Payload for DB16 through DB18 */
> +	/* Pixel Encoding and Colorimetry Formats  */
> +	sdp->db[16] = (vsc->colorspace & 0xf) << 4; /* DB16[7:4] */
> +	sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
> +
> +	switch (vsc->bpc) {
> +	case 8:
> +		sdp->db[17] = 0x1; /* DB17[3:0] */
> +		break;
> +	case 10:
> +		sdp->db[17] = 0x2;
> +		break;
> +	case 12:
> +		sdp->db[17] = 0x3;
> +		break;
> +	case 16:
> +		sdp->db[17] = 0x4;
> +		break;
> +	default:
> +		MISSING_CASE(vsc->bpc);

6bpc is not handled here, add that as well.

> +		break;
> +	}
> +	/* Dynamic Range and Component Bit Depth */
> +	if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
> +		sdp->db[17] |= 0x80;  /* DB17[7] */
> +
> +	/* Content Type */
> +	sdp->db[18] = vsc->content_type & 0x7;
> +
> +	return length;
> +}
> +
> +static ssize_t
> +intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe
> *drm_infoframe,
> +					 struct dp_sdp *sdp,
> +					 size_t size)
> +{
> +	size_t length = sizeof(struct dp_sdp);
> +	const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE +
> HDMI_DRM_INFOFRAME_SIZE;
> +	unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE +
> HDMI_DRM_INFOFRAME_SIZE];
> +	ssize_t len;
> +
> +	if (size < length)
> +		return -ENOSPC;
> +
> +	memset(sdp, 0, size);
> +
> +	len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
> +	if (len < 0) {
> +		DRM_DEBUG_KMS("buffer size is smaller than hdr metadata
> infoframe\n");
> +		return -ENOSPC;
> +	}
> +
> +	if (len != infoframe_size) {
> +		DRM_DEBUG_KMS("wrong static hdr metadata size\n");
> +		return -ENOSPC;
> +	}
> +
> +	/*
> +	 * Set up the infoframe sdp packet for HDR static metadata.
> +	 * Prepare VSC Header for SU as per DP 1.4a spec,
> +	 * Table 2-100 and Table 2-101
> +	 */
> +
> +	/* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
> +	sdp->sdp_header.HB0 = 0;
> +	/*
> +	 * Packet Type 80h + Non-audio INFOFRAME Type value
> +	 * HDMI_INFOFRAME_TYPE_DRM: 0x87
> +	 * - 80h + Non-audio INFOFRAME Type value
> +	 * - InfoFrame Type: 0x07
> +	 *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
> +	 */
> +	sdp->sdp_header.HB1 = drm_infoframe->type;
> +	/*
> +	 * Least Significant Eight Bits of (Data Byte Count – 1)
> +	 * infoframe_size - 1
> +	 */
> +	sdp->sdp_header.HB2 = 0x1D;
> +	/* INFOFRAME SDP Version Number */
> +	sdp->sdp_header.HB3 = (0x13 << 2);
> +	/* CTA Header Byte 2 (INFOFRAME Version Number) */
> +	sdp->db[0] = drm_infoframe->version;
> +	/* CTA Header Byte 3 (Length of INFOFRAME):
> HDMI_DRM_INFOFRAME_SIZE */
> +	sdp->db[1] = drm_infoframe->length;
> +	/*
> +	 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after

Comment Looks incomplete.

> +	 */
> +	BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
> +	memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
> +	       HDMI_DRM_INFOFRAME_SIZE);
> +
> +	/*
> +	 * Size of DP infoframe sdp packet for HDR static metadata is consist of

Drop "is"

> +	 * - DP SDP Header(struct dp_sdp_header): 4 bytes
> +	 * - Two Data Blocks: 2 bytes
> +	 *    CTA Header Byte2 (INFOFRAME Version Number)
> +	 *    CTA Header Byte3 (Length of INFOFRAME)
> +	 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
> +	 *
> +	 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
> +	 * infoframe size. But GEN11+ has larger than that size, write_infoframe
> +	 * will pad rest of the size.
> +	 */
> +	return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE; }
> +
> +static void intel_write_dp_sdp(struct intel_encoder *encoder,
> +			       const struct intel_crtc_state *crtc_state,
> +			       unsigned int type)
> +{
> +	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
> +	struct dp_sdp sdp = {};
> +	ssize_t len;
> +
> +	if ((crtc_state->infoframes.enable &
> +	     intel_hdmi_infoframe_enable(type)) == 0)
> +		return;
> +
> +	switch (type) {
> +	case DP_SDP_VSC:
> +		len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
> +					    sizeof(sdp));
> +		break;
> +	case HDMI_PACKET_TYPE_GAMUT_METADATA:
> +		len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state-
> >infoframes.drm.drm,
> +							       &sdp, sizeof(sdp));
> +		break;
> +	default:
> +		MISSING_CASE(type);
> +		break;
> +	}
> +
> +	if (WARN_ON(len < 0))
> +		return;
> +
> +	intel_dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
> +}
> +
> +void intel_dp_set_infoframes(struct intel_encoder *encoder,
> +			     bool enable,
> +			     const struct intel_crtc_state *crtc_state,
> +			     const struct drm_connector_state *conn_state) {
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
> +	u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW |
> VIDEO_DIP_ENABLE_GCP_HSW |
> +			 VIDEO_DIP_ENABLE_VS_HSW |
> VIDEO_DIP_ENABLE_GMP_HSW |
> +			 VIDEO_DIP_ENABLE_SPD_HSW |
> VIDEO_DIP_ENABLE_DRM_GLK;
> +	u32 val = I915_READ(reg);
> +
> +	/* TODO: Add DSC case (DIP_ENABLE_PPS) */
> +	/* When PSR is enabled, this routine doesn't disable VSC DIP */
> +	if (intel_psr_enabled(intel_dp))
> +		val &= ~dip_enable;
> +	else
> +		val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);

dip_enable has VIDEO_DIP_ENABLE_VSC_HSW already in it. Please fix this.

> +
> +	if (!enable) {
> +		I915_WRITE(reg, val);
> +		POSTING_READ(reg);
> +		return;
> +	}
> +
> +	I915_WRITE(reg, val);
> +	POSTING_READ(reg);
> +
> +	/* When PSR is enabled, VSC SDP is handled by PSR routine */
> +	if (!intel_psr_enabled(intel_dp))
> +		intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
> +
> +	intel_write_dp_sdp(encoder, crtc_state,
> +HDMI_PACKET_TYPE_GAMUT_METADATA); }
> +
>  static void
>  intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
>  		       const struct intel_crtc_state *crtc_state, diff --git
> a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index 3da166054788..0dc09a463ee1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -116,6 +116,9 @@ void intel_dp_vsc_enable(struct intel_dp *intel_dp,  void
> intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
>  				  const struct intel_crtc_state *crtc_state,
>  				  const struct drm_connector_state *conn_state);
> +void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
> +			     const struct intel_crtc_state *crtc_state,
> +			     const struct drm_connector_state *conn_state);
>  bool intel_digital_port_connected(struct intel_encoder *encoder);
> 
>  static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

RE: [Intel-gfx] [PATCH v3 05/17] video/hdmi: Add Unpack only function for DRM infoframe

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 05/17] video/hdmi: Add Unpack only function for DRM
> infoframe
> 
> It adds an unpack only function for DRM infoframe for dynamic range and mastering
> infoframe readout.
> It unpacks the information data block contained in the binary buffer into a structured
> frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
> 
> In contrast to hdmi_drm_infoframe_unpack() function, it does not verify a
> checksum.
> 
> It can be used for unpacking a DP HDR Metadata Infoframe SDP case.
> DP HDR Metadata Infoframe SDP uses the same Dynamic Range and Mastering
> (DRM) information (CTA-861-G spec.) such as HDMI DRM infoframe.
> But DP SDP header and payload structure are different from HDMI DRM Infoframe.
> Therefore unpacking DRM infoframe for DP requires skipping of a verifying
> checksum.

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/video/hdmi.c | 58 +++++++++++++++++++++++++++++++-------------
>  include/linux/hdmi.h |  2 ++
>  2 files changed, 43 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c index
> 9c82e2a0a411..9818836d82b7 100644
> --- a/drivers/video/hdmi.c
> +++ b/drivers/video/hdmi.c
> @@ -1775,20 +1775,18 @@ hdmi_vendor_any_infoframe_unpack(union
> hdmi_vendor_any_infoframe *frame,  }
> 
>  /**
> - * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
> + * hdmi_drm_infoframe_unpack_only() - unpack binary buffer to a HDMI
> + DRM infoframe
>   * @frame: HDMI DRM infoframe
>   * @buffer: source buffer
>   * @size: size of buffer
>   *
> - * Unpacks the information contained in binary @buffer into a structured
> + * Unpacks the information data block contained in binary @buffer into
> + a structured
>   * @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
> - * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4
> - * specification.
>   *
>   * Returns 0 on success or a negative error code on failure.
>   */
> -static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
> -				     const void *buffer, size_t size)
> +int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
> +				   const void *buffer, size_t size)
>  {
>  	const u8 *ptr = buffer;
>  	const u8 *temp;
> @@ -1797,23 +1795,13 @@ static int hdmi_drm_infoframe_unpack(struct
> hdmi_drm_infoframe *frame,
>  	int ret;
>  	int i;
> 
> -	if (size < HDMI_INFOFRAME_SIZE(DRM))
> -		return -EINVAL;
> -
> -	if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
> -	    ptr[1] != 1 ||
> -	    ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
> -		return -EINVAL;
> -
> -	if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
> +	if (size < HDMI_DRM_INFOFRAME_SIZE)
>  		return -EINVAL;
> 
>  	ret = hdmi_drm_infoframe_init(frame);
>  	if (ret)
>  		return ret;
> 
> -	ptr += HDMI_INFOFRAME_HEADER_SIZE;
> -
>  	frame->eotf = ptr[0] & 0x7;
>  	frame->metadata_type = ptr[1] & 0x7;
> 
> @@ -1837,6 +1825,42 @@ static int hdmi_drm_infoframe_unpack(struct
> hdmi_drm_infoframe *frame,
> 
>  	return 0;
>  }
> +EXPORT_SYMBOL(hdmi_drm_infoframe_unpack_only);
> +
> +/**
> + * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM
> +infoframe
> + * @frame: HDMI DRM infoframe
> + * @buffer: source buffer
> + * @size: size of buffer
> + *
> + * Unpacks the information contained in binary @buffer into a
> +structured
> + * @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
> + * Also verifies the checksum as required by section 5.3.5 of the HDMI
> +1.4
> + * specification.
> + *
> + * Returns 0 on success or a negative error code on failure.
> + */
> +static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
> +				     const void *buffer, size_t size) {
> +	const u8 *ptr = buffer;
> +	int ret;
> +
> +	if (size < HDMI_INFOFRAME_SIZE(DRM))
> +		return -EINVAL;
> +
> +	if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
> +	    ptr[1] != 1 ||
> +	    ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
> +		return -EINVAL;
> +
> +	if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
> +		return -EINVAL;
> +
> +	ret = hdmi_drm_infoframe_unpack_only(frame, ptr +
> HDMI_INFOFRAME_HEADER_SIZE,
> +					     size - HDMI_INFOFRAME_HEADER_SIZE);
> +	return ret;
> +}
> 
>  /**
>   * hdmi_infoframe_unpack() - unpack binary buffer to a HDMI infoframe diff --git
> a/include/linux/hdmi.h b/include/linux/hdmi.h index 9918a6c910c5..afb43efc03e0
> 100644
> --- a/include/linux/hdmi.h
> +++ b/include/linux/hdmi.h
> @@ -219,6 +219,8 @@ ssize_t hdmi_drm_infoframe_pack(struct
> hdmi_drm_infoframe *frame, void *buffer,  ssize_t
> hdmi_drm_infoframe_pack_only(const struct hdmi_drm_infoframe *frame,
>  				     void *buffer, size_t size);
>  int hdmi_drm_infoframe_check(struct hdmi_drm_infoframe *frame);
> +int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
> +				   const void *buffer, size_t size);
> 
>  enum hdmi_spd_sdi {
>  	HDMI_SPD_SDI_UNKNOWN,
> --
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

RE: [Intel-gfx] [PATCH v3 05/17] video/hdmi: Add Unpack only function for DRM infoframe

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 05/17] video/hdmi: Add Unpack only function for DRM
> infoframe
> 
> It adds an unpack only function for DRM infoframe for dynamic range and mastering
> infoframe readout.
> It unpacks the information data block contained in the binary buffer into a structured
> frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
> 
> In contrast to hdmi_drm_infoframe_unpack() function, it does not verify a
> checksum.
> 
> It can be used for unpacking a DP HDR Metadata Infoframe SDP case.
> DP HDR Metadata Infoframe SDP uses the same Dynamic Range and Mastering
> (DRM) information (CTA-861-G spec.) such as HDMI DRM infoframe.
> But DP SDP header and payload structure are different from HDMI DRM Infoframe.
> Therefore unpacking DRM infoframe for DP requires skipping of a verifying
> checksum.

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/video/hdmi.c | 58 +++++++++++++++++++++++++++++++-------------
>  include/linux/hdmi.h |  2 ++
>  2 files changed, 43 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c index
> 9c82e2a0a411..9818836d82b7 100644
> --- a/drivers/video/hdmi.c
> +++ b/drivers/video/hdmi.c
> @@ -1775,20 +1775,18 @@ hdmi_vendor_any_infoframe_unpack(union
> hdmi_vendor_any_infoframe *frame,  }
> 
>  /**
> - * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
> + * hdmi_drm_infoframe_unpack_only() - unpack binary buffer to a HDMI
> + DRM infoframe
>   * @frame: HDMI DRM infoframe
>   * @buffer: source buffer
>   * @size: size of buffer
>   *
> - * Unpacks the information contained in binary @buffer into a structured
> + * Unpacks the information data block contained in binary @buffer into
> + a structured
>   * @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
> - * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4
> - * specification.
>   *
>   * Returns 0 on success or a negative error code on failure.
>   */
> -static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
> -				     const void *buffer, size_t size)
> +int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
> +				   const void *buffer, size_t size)
>  {
>  	const u8 *ptr = buffer;
>  	const u8 *temp;
> @@ -1797,23 +1795,13 @@ static int hdmi_drm_infoframe_unpack(struct
> hdmi_drm_infoframe *frame,
>  	int ret;
>  	int i;
> 
> -	if (size < HDMI_INFOFRAME_SIZE(DRM))
> -		return -EINVAL;
> -
> -	if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
> -	    ptr[1] != 1 ||
> -	    ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
> -		return -EINVAL;
> -
> -	if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
> +	if (size < HDMI_DRM_INFOFRAME_SIZE)
>  		return -EINVAL;
> 
>  	ret = hdmi_drm_infoframe_init(frame);
>  	if (ret)
>  		return ret;
> 
> -	ptr += HDMI_INFOFRAME_HEADER_SIZE;
> -
>  	frame->eotf = ptr[0] & 0x7;
>  	frame->metadata_type = ptr[1] & 0x7;
> 
> @@ -1837,6 +1825,42 @@ static int hdmi_drm_infoframe_unpack(struct
> hdmi_drm_infoframe *frame,
> 
>  	return 0;
>  }
> +EXPORT_SYMBOL(hdmi_drm_infoframe_unpack_only);
> +
> +/**
> + * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM
> +infoframe
> + * @frame: HDMI DRM infoframe
> + * @buffer: source buffer
> + * @size: size of buffer
> + *
> + * Unpacks the information contained in binary @buffer into a
> +structured
> + * @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
> + * Also verifies the checksum as required by section 5.3.5 of the HDMI
> +1.4
> + * specification.
> + *
> + * Returns 0 on success or a negative error code on failure.
> + */
> +static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
> +				     const void *buffer, size_t size) {
> +	const u8 *ptr = buffer;
> +	int ret;
> +
> +	if (size < HDMI_INFOFRAME_SIZE(DRM))
> +		return -EINVAL;
> +
> +	if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
> +	    ptr[1] != 1 ||
> +	    ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
> +		return -EINVAL;
> +
> +	if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
> +		return -EINVAL;
> +
> +	ret = hdmi_drm_infoframe_unpack_only(frame, ptr +
> HDMI_INFOFRAME_HEADER_SIZE,
> +					     size - HDMI_INFOFRAME_HEADER_SIZE);
> +	return ret;
> +}
> 
>  /**
>   * hdmi_infoframe_unpack() - unpack binary buffer to a HDMI infoframe diff --git
> a/include/linux/hdmi.h b/include/linux/hdmi.h index 9918a6c910c5..afb43efc03e0
> 100644
> --- a/include/linux/hdmi.h
> +++ b/include/linux/hdmi.h
> @@ -219,6 +219,8 @@ ssize_t hdmi_drm_infoframe_pack(struct
> hdmi_drm_infoframe *frame, void *buffer,  ssize_t
> hdmi_drm_infoframe_pack_only(const struct hdmi_drm_infoframe *frame,
>  				     void *buffer, size_t size);
>  int hdmi_drm_infoframe_check(struct hdmi_drm_infoframe *frame);
> +int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
> +				   const void *buffer, size_t size);
> 
>  enum hdmi_spd_sdi {
>  	HDMI_SPD_SDI_UNKNOWN,
> --
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Intel-gfx] [PATCH v3 05/17] video/hdmi: Add Unpack only function for DRM infoframe

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 05/17] video/hdmi: Add Unpack only function for DRM
> infoframe
> 
> It adds an unpack only function for DRM infoframe for dynamic range and mastering
> infoframe readout.
> It unpacks the information data block contained in the binary buffer into a structured
> frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
> 
> In contrast to hdmi_drm_infoframe_unpack() function, it does not verify a
> checksum.
> 
> It can be used for unpacking a DP HDR Metadata Infoframe SDP case.
> DP HDR Metadata Infoframe SDP uses the same Dynamic Range and Mastering
> (DRM) information (CTA-861-G spec.) such as HDMI DRM infoframe.
> But DP SDP header and payload structure are different from HDMI DRM Infoframe.
> Therefore unpacking DRM infoframe for DP requires skipping of a verifying
> checksum.

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/video/hdmi.c | 58 +++++++++++++++++++++++++++++++-------------
>  include/linux/hdmi.h |  2 ++
>  2 files changed, 43 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c index
> 9c82e2a0a411..9818836d82b7 100644
> --- a/drivers/video/hdmi.c
> +++ b/drivers/video/hdmi.c
> @@ -1775,20 +1775,18 @@ hdmi_vendor_any_infoframe_unpack(union
> hdmi_vendor_any_infoframe *frame,  }
> 
>  /**
> - * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
> + * hdmi_drm_infoframe_unpack_only() - unpack binary buffer to a HDMI
> + DRM infoframe
>   * @frame: HDMI DRM infoframe
>   * @buffer: source buffer
>   * @size: size of buffer
>   *
> - * Unpacks the information contained in binary @buffer into a structured
> + * Unpacks the information data block contained in binary @buffer into
> + a structured
>   * @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
> - * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4
> - * specification.
>   *
>   * Returns 0 on success or a negative error code on failure.
>   */
> -static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
> -				     const void *buffer, size_t size)
> +int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
> +				   const void *buffer, size_t size)
>  {
>  	const u8 *ptr = buffer;
>  	const u8 *temp;
> @@ -1797,23 +1795,13 @@ static int hdmi_drm_infoframe_unpack(struct
> hdmi_drm_infoframe *frame,
>  	int ret;
>  	int i;
> 
> -	if (size < HDMI_INFOFRAME_SIZE(DRM))
> -		return -EINVAL;
> -
> -	if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
> -	    ptr[1] != 1 ||
> -	    ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
> -		return -EINVAL;
> -
> -	if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
> +	if (size < HDMI_DRM_INFOFRAME_SIZE)
>  		return -EINVAL;
> 
>  	ret = hdmi_drm_infoframe_init(frame);
>  	if (ret)
>  		return ret;
> 
> -	ptr += HDMI_INFOFRAME_HEADER_SIZE;
> -
>  	frame->eotf = ptr[0] & 0x7;
>  	frame->metadata_type = ptr[1] & 0x7;
> 
> @@ -1837,6 +1825,42 @@ static int hdmi_drm_infoframe_unpack(struct
> hdmi_drm_infoframe *frame,
> 
>  	return 0;
>  }
> +EXPORT_SYMBOL(hdmi_drm_infoframe_unpack_only);
> +
> +/**
> + * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM
> +infoframe
> + * @frame: HDMI DRM infoframe
> + * @buffer: source buffer
> + * @size: size of buffer
> + *
> + * Unpacks the information contained in binary @buffer into a
> +structured
> + * @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
> + * Also verifies the checksum as required by section 5.3.5 of the HDMI
> +1.4
> + * specification.
> + *
> + * Returns 0 on success or a negative error code on failure.
> + */
> +static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
> +				     const void *buffer, size_t size) {
> +	const u8 *ptr = buffer;
> +	int ret;
> +
> +	if (size < HDMI_INFOFRAME_SIZE(DRM))
> +		return -EINVAL;
> +
> +	if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
> +	    ptr[1] != 1 ||
> +	    ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
> +		return -EINVAL;
> +
> +	if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
> +		return -EINVAL;
> +
> +	ret = hdmi_drm_infoframe_unpack_only(frame, ptr +
> HDMI_INFOFRAME_HEADER_SIZE,
> +					     size - HDMI_INFOFRAME_HEADER_SIZE);
> +	return ret;
> +}
> 
>  /**
>   * hdmi_infoframe_unpack() - unpack binary buffer to a HDMI infoframe diff --git
> a/include/linux/hdmi.h b/include/linux/hdmi.h index 9918a6c910c5..afb43efc03e0
> 100644
> --- a/include/linux/hdmi.h
> +++ b/include/linux/hdmi.h
> @@ -219,6 +219,8 @@ ssize_t hdmi_drm_infoframe_pack(struct
> hdmi_drm_infoframe *frame, void *buffer,  ssize_t
> hdmi_drm_infoframe_pack_only(const struct hdmi_drm_infoframe *frame,
>  				     void *buffer, size_t size);
>  int hdmi_drm_infoframe_check(struct hdmi_drm_infoframe *frame);
> +int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
> +				   const void *buffer, size_t size);
> 
>  enum hdmi_spd_sdi {
>  	HDMI_SPD_SDI_UNKNOWN,
> --
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

RE: [PATCH v3 06/17] drm/i915/dp: Read out DP SDPs (Secondary Data Packet)

[Shankar, Uma]

DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogZHJpLWRldmVsIDxkcmkt
ZGV2ZWwtYm91bmNlc0BsaXN0cy5mcmVlZGVza3RvcC5vcmc+IE9uIEJlaGFsZiBPZiBHd2FuLQ0K
PiBneWVvbmcgTXVuDQo+IFNlbnQ6IFR1ZXNkYXksIEZlYnJ1YXJ5IDQsIDIwMjAgNDo1MCBBTQ0K
PiBUbzogaW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZw0KPiBDYzogbGludXgtZmJkZXZA
dmdlci5rZXJuZWwub3JnOyBkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnDQo+IFN1Ympl
Y3Q6IFtQQVRDSCB2MyAwNi8xN10gZHJtL2k5MTUvZHA6IFJlYWQgb3V0IERQIFNEUHMgKFNlY29u
ZGFyeSBEYXRhIFBhY2tldCkNCg0KRHJvcCB0aGUgY29udGVudCBpbiBicmFja2V0Lg0KDQo+IEl0
IGFkZHMgY29kZSB0byByZWFkIHRoZSBEUCBTRFBzIGZyb20gdGhlIHZpZGVvIERJUCBhbmQgdW5w
YWNrIHRoZW0gaW50byB0aGUgY3J0Yw0KPiBzdGF0ZS4NCj4gDQo+IEl0IGFkZHMgcm91dGluZXMg
dGhhdCByZWFkIG91dCBEUCBWU0MgU0RQIGFuZCBEUCBIRFIgTWV0YWRhdGEgSW5mb2ZyYW1lIFNE
UCBJbg0KPiBvcmRlciB0byB1bnBhY2sgRFAgVlNDIFNEUCwgaXQgYWRkcyBpbnRlbF9kcF92c2Nf
c2RwX3VucGFjaygpIGZ1bmN0aW9uLg0KPiBJdCBmb2xsb3dzIERQIDEuNGEgc3BlYy4gW1RhYmxl
IDItMTE2OiBWU0MgU0RQIEhlYWRlciBCeXRlc10gYW5kIFtUYWJsZSAyLTExNzogVlNDDQo+IFNE
UCBQYXlsb2FkIGZvciBEQjE2IHRocm91Z2ggREIxOF0NCj4gDQo+IEluIG9yZGVyIHRvIHVucGFj
ayBEUCBIRFIgTWV0YWRhdGEgSW5mb2ZyYW1lIFNEUCwgaXQgYWRkcw0KPiBpbnRlbF9kcF9oZHJf
bWV0YWRhdGFfaW5mb2ZyYW1lX3NkcF91bnBhY2soKS4gQW5kIGl0IGZvbGxvd3MgRFAgMS40YSBz
cGVjLg0KPiAoW1RhYmxlIDItMTI1OiBJTkZPRlJBTUUgU0RQIHYxLjIgSGVhZGVyIEJ5dGVzXSBh
bmQgW1RhYmxlIDItMTI2OiBJTkZPRlJBTUUNCj4gU0RQIHYxLjIgUGF5bG9hZCBEYXRhIEJ5dGVz
IC0gREIwIHRocm91Z2ggREIzMV0pIGFuZCBDVEEtODYxLUcgc3BlYy4gW1RhYmxlLTQyDQo+IER5
bmFtaWMgUmFuZ2UgYW5kIE1hc3RlcmluZyBJbmZvRnJhbWVdLg0KPiANCj4gQSBuYW1laW5nIHJ1
bGUgYW5kIHN0eWxlIG9mIGludGVsX3JlYWRfZHBfc2RwKCkgZnVuY3Rpb24gcmVmZXJlbmNlcw0K
DQpUeXBvIGluIG5hbWluZy4NCg0KPiBpbnRlbF9yZWFkX2luZm9mcmFtZSgpIGZ1bmN0aW9uIG9m
IGludGVsX2hkbWkuYw0KPiANCj4gdjI6IE1pbm9yIHN0eWxlIGZpeA0KPiB2MzogUmVwbGFjZSBh
IHN0cnVjdHVyZSBuYW1lIHRvIGRybV9kcF92c2Nfc2RwIGZyb20gaW50ZWxfZHBfdnNjX3NkcA0K
PiANCj4gU2lnbmVkLW9mZi1ieTogR3dhbi1neWVvbmcgTXVuIDxnd2FuLWd5ZW9uZy5tdW5AaW50
ZWwuY29tPg0KPiAtLS0NCj4gIGRyaXZlcnMvZ3B1L2RybS9pOTE1L2Rpc3BsYXkvaW50ZWxfZHAu
YyB8IDE3MCArKysrKysrKysrKysrKysrKysrKysrKysNCj4gIGRyaXZlcnMvZ3B1L2RybS9pOTE1
L2Rpc3BsYXkvaW50ZWxfZHAuaCB8ICAgMyArDQo+ICAyIGZpbGVzIGNoYW5nZWQsIDE3MyBpbnNl
cnRpb25zKCspDQo+IA0KPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxh
eS9pbnRlbF9kcC5jDQo+IGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9kcC5j
DQo+IGluZGV4IGRkN2U1NTg4MDAxZS4uZDRlY2UwYTgyNGMwIDEwMDY0NA0KPiAtLS0gYS9kcml2
ZXJzL2dwdS9kcm0vaTkxNS9kaXNwbGF5L2ludGVsX2RwLmMNCj4gKysrIGIvZHJpdmVycy9ncHUv
ZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9kcC5jDQo+IEBAIC00OTI1LDYgKzQ5MjUsMTc2IEBAIHZv
aWQgaW50ZWxfZHBfc2V0X2luZm9mcmFtZXMoc3RydWN0IGludGVsX2VuY29kZXINCj4gKmVuY29k
ZXIsDQo+ICAJaW50ZWxfd3JpdGVfZHBfc2RwKGVuY29kZXIsIGNydGNfc3RhdGUsDQo+IEhETUlf
UEFDS0VUX1RZUEVfR0FNVVRfTUVUQURBVEEpOyAgfQ0KPiANCj4gK3N0YXRpYyBpbnQgaW50ZWxf
ZHBfdnNjX3NkcF91bnBhY2soc3RydWN0IGRybV9kcF92c2Nfc2RwICp2c2MsDQo+ICsJCQkJICAg
Y29uc3Qgdm9pZCAqYnVmZmVyLCBzaXplX3Qgc2l6ZSkgew0KPiArCWNvbnN0IHN0cnVjdCBkcF9z
ZHAgKnNkcCA9IGJ1ZmZlcjsNCj4gKw0KPiArCWlmIChzaXplIDwgc2l6ZW9mKHN0cnVjdCBkcF9z
ZHApKQ0KPiArCQlyZXR1cm4gLUVJTlZBTDsNCj4gKw0KPiArCW1lbXNldCh2c2MsIDAsIHNpemUp
Ow0KPiArDQo+ICsJaWYgKHNkcC0+c2RwX2hlYWRlci5IQjAgIT0gMCkNCj4gKwkJcmV0dXJuIC1F
SU5WQUw7DQo+ICsNCj4gKwlpZiAoc2RwLT5zZHBfaGVhZGVyLkhCMSAhPSBEUF9TRFBfVlNDKQ0K
PiArCQlyZXR1cm4gLUVJTlZBTDsNCj4gKwl2c2MtPnNkcF90eXBlID0gc2RwLT5zZHBfaGVhZGVy
LkhCMTsNCj4gKw0KPiArCWlmIChzZHAtPnNkcF9oZWFkZXIuSEIyID09IDB4MiAmJiBzZHAtPnNk
cF9oZWFkZXIuSEIzID09IDB4OCkgew0KPiArCQl2c2MtPnJldmlzaW9uID0gc2RwLT5zZHBfaGVh
ZGVyLkhCMjsNCj4gKwkJdnNjLT5sZW5ndGggPSBzZHAtPnNkcF9oZWFkZXIuSEIzOw0KPiArCX0g
ZWxzZSBpZiAoc2RwLT5zZHBfaGVhZGVyLkhCMiA9PSAweDQgJiYgc2RwLT5zZHBfaGVhZGVyLkhC
MyA9PSAweGUpIHsNCj4gKwkJdnNjLT5yZXZpc2lvbiA9IHNkcC0+c2RwX2hlYWRlci5IQjI7DQo+
ICsJCXZzYy0+bGVuZ3RoID0gc2RwLT5zZHBfaGVhZGVyLkhCMzsNCj4gKwl9IGVsc2UgaWYgKHNk
cC0+c2RwX2hlYWRlci5IQjIgPT0gMHg1ICYmIHNkcC0+c2RwX2hlYWRlci5IQjMgPT0gMHgxMykg
ew0KPiArCQl2c2MtPnJldmlzaW9uID0gc2RwLT5zZHBfaGVhZGVyLkhCMjsNCj4gKwkJdnNjLT5s
ZW5ndGggPSBzZHAtPnNkcF9oZWFkZXIuSEIzOw0KDQpUaGUgYWJvdmUgMiBsaW5lcyBjYW4gYmUg
ZG9uZSB1bmNvbmRpdGlvbmFsbHksIG1heSBiZSBjb21iaW5lIHRoZSBpZiBjaGVja3MuDQoNCj4g
KwkJdnNjLT5jb2xvcnNwYWNlID0gKHNkcC0+ZGJbMTZdID4+IDQpICYgMHhmOw0KPiArCQl2c2Mt
PmNvbG9yaW1ldHJ5ID0gc2RwLT5kYlsxNl0gJiAweGY7DQo+ICsJCXZzYy0+ZHluYW1pY19yYW5n
ZSA9IChzZHAtPmRiWzE3XSA+PiA3KSAmIDB4MTsNCj4gKw0KPiArCQlzd2l0Y2ggKHNkcC0+ZGJb
MTddICYgMHg3KSB7DQo+ICsJCWNhc2UgMHgxOg0KPiArCQkJdnNjLT5icGMgPSA4Ow0KPiArCQkJ
YnJlYWs7DQo+ICsJCWNhc2UgMHgyOg0KPiArCQkJdnNjLT5icGMgPSAxMDsNCj4gKwkJCWJyZWFr
Ow0KPiArCQljYXNlIDB4MzoNCj4gKwkJCXZzYy0+YnBjID0gMTI7DQo+ICsJCQlicmVhazsNCj4g
KwkJY2FzZSAweDQ6DQo+ICsJCQl2c2MtPmJwYyA9IDE2Ow0KPiArCQkJYnJlYWs7DQo+ICsJCWRl
ZmF1bHQ6DQo+ICsJCQlNSVNTSU5HX0NBU0Uoc2RwLT5kYlsxN10gJiAweDcpOw0KDQpIYW5kbGUg
NmJwYyBjYXNlIGFzIHdlbGwuDQoNCj4gKwkJCXJldHVybiAtRUlOVkFMOw0KPiArCQl9DQo+ICsN
Cj4gKwkJdnNjLT5jb250ZW50X3R5cGUgPSBzZHAtPmRiWzE4XSAmIDB4NzsNCj4gKwl9IGVsc2Ug
ew0KPiArCQlyZXR1cm4gLUVJTlZBTDsNCj4gKwl9DQo+ICsNCj4gKwlyZXR1cm4gMDsNCj4gK30N
Cj4gKw0KPiArc3RhdGljIGludA0KPiAraW50ZWxfZHBfaGRyX21ldGFkYXRhX2luZm9mcmFtZV9z
ZHBfdW5wYWNrKHN0cnVjdCBoZG1pX2RybV9pbmZvZnJhbWUNCj4gKmRybV9pbmZvZnJhbWUsDQo+
ICsJCQkJCSAgIGNvbnN0IHZvaWQgKmJ1ZmZlciwgc2l6ZV90IHNpemUpIHsNCj4gKwlpbnQgcmV0
Ow0KPiArDQo+ICsJY29uc3Qgc3RydWN0IGRwX3NkcCAqc2RwID0gYnVmZmVyOw0KPiArDQo+ICsJ
aWYgKHNpemUgPCBzaXplb2Yoc3RydWN0IGRwX3NkcCkpDQo+ICsJCXJldHVybiAtRUlOVkFMOw0K
PiArDQo+ICsJaWYgKHNkcC0+c2RwX2hlYWRlci5IQjAgIT0gMCkNCj4gKwkJcmV0dXJuIC1FSU5W
QUw7DQo+ICsNCj4gKwlpZiAoc2RwLT5zZHBfaGVhZGVyLkhCMSAhPSBIRE1JX0lORk9GUkFNRV9U
WVBFX0RSTSkNCj4gKwkJcmV0dXJuIC1FSU5WQUw7DQo+ICsNCj4gKwkvKg0KPiArCSAqIExlYXN0
IFNpZ25pZmljYW50IEVpZ2h0IEJpdHMgb2YgKERhdGEgQnl0ZSBDb3VudCDigJMgMSkNCj4gKwkg
KiAxRGggKGkuZS4sIERhdGEgQnl0ZSBDb3VudCA9IDMwIGJ5dGVzKS4NCj4gKwkgKi8NCj4gKwlp
ZiAoc2RwLT5zZHBfaGVhZGVyLkhCMiAhPSAweDFEKQ0KPiArCQlyZXR1cm4gLUVJTlZBTDsNCj4g
Kw0KPiArCS8qIE1vc3QgU2lnbmlmaWNhbnQgVHdvIEJpdHMgb2YgKERhdGEgQnl0ZSBDb3VudCDi
gJMgMSksIENsZWFyIHRvIDAwYi4gKi8NCj4gKwlpZiAoKHNkcC0+c2RwX2hlYWRlci5IQjMgJiAw
eDMpICE9IDApDQo+ICsJCXJldHVybiAtRUlOVkFMOw0KPiArDQo+ICsJLyogSU5GT0ZSQU1FIFNE
UCBWZXJzaW9uIE51bWJlciAqLw0KPiArCWlmICgoKHNkcC0+c2RwX2hlYWRlci5IQjMgPj4gMikg
JiAweDNmKSAhPSAweDEzKQ0KPiArCQlyZXR1cm4gLUVJTlZBTDsNCj4gKw0KPiArCS8qIENUQSBI
ZWFkZXIgQnl0ZSAyIChJTkZPRlJBTUUgVmVyc2lvbiBOdW1iZXIpICovDQo+ICsJaWYgKHNkcC0+
ZGJbMF0gIT0gMSkNCj4gKwkJcmV0dXJuIC1FSU5WQUw7DQo+ICsNCj4gKwkvKiBDVEEgSGVhZGVy
IEJ5dGUgMyAoTGVuZ3RoIG9mIElORk9GUkFNRSk6DQo+IEhETUlfRFJNX0lORk9GUkFNRV9TSVpF
ICovDQo+ICsJaWYgKHNkcC0+ZGJbMV0gIT0gSERNSV9EUk1fSU5GT0ZSQU1FX1NJWkUpDQo+ICsJ
CXJldHVybiAtRUlOVkFMOw0KPiArDQo+ICsJcmV0ID0gaGRtaV9kcm1faW5mb2ZyYW1lX3VucGFj
a19vbmx5KGRybV9pbmZvZnJhbWUsICZzZHAtPmRiWzJdLA0KPiArCQkJCQkgICAgIEhETUlfRFJN
X0lORk9GUkFNRV9TSVpFKTsNCj4gKw0KPiArCXJldHVybiByZXQ7DQo+ICt9DQo+ICsNCj4gK3N0
YXRpYyB2b2lkIGludGVsX3JlYWRfZHBfdnNjX3NkcChzdHJ1Y3QgaW50ZWxfZW5jb2RlciAqZW5j
b2RlciwNCj4gKwkJCQkgIHN0cnVjdCBpbnRlbF9jcnRjX3N0YXRlICpjcnRjX3N0YXRlLA0KPiAr
CQkJCSAgc3RydWN0IGRybV9kcF92c2Nfc2RwICp2c2MpDQo+ICt7DQo+ICsJc3RydWN0IGludGVs
X2RpZ2l0YWxfcG9ydCAqaW50ZWxfZGlnX3BvcnQgPSBlbmNfdG9fZGlnX3BvcnQoZW5jb2Rlcik7
DQo+ICsJc3RydWN0IGludGVsX2RwICppbnRlbF9kcCA9IGVuY190b19pbnRlbF9kcChlbmNvZGVy
KTsNCj4gKwl1bnNpZ25lZCBpbnQgdHlwZSA9IERQX1NEUF9WU0M7DQo+ICsJc3RydWN0IGRwX3Nk
cCBzZHAgPSB7fTsNCj4gKwlpbnQgcmV0Ow0KPiArDQo+ICsJLyogV2hlbiBQU1IgaXMgZW5hYmxl
ZCwgVlNDIFNEUCBpcyBoYW5kbGVkIGJ5IFBTUiByb3V0aW5lICovDQo+ICsJaWYgKGludGVsX3Bz
cl9lbmFibGVkKGludGVsX2RwKSkNCj4gKwkJcmV0dXJuOw0KPiArDQo+ICsJaWYgKChjcnRjX3N0
YXRlLT5pbmZvZnJhbWVzLmVuYWJsZSAmDQo+ICsJICAgICBpbnRlbF9oZG1pX2luZm9mcmFtZV9l
bmFibGUodHlwZSkpID09IDApDQo+ICsJCXJldHVybjsNCj4gKw0KPiArCWludGVsX2RpZ19wb3J0
LT5yZWFkX2luZm9mcmFtZShlbmNvZGVyLCBjcnRjX3N0YXRlLCB0eXBlLCAmc2RwLA0KPiArc2l6
ZW9mKHNkcCkpOw0KPiArDQo+ICsJcmV0ID0gaW50ZWxfZHBfdnNjX3NkcF91bnBhY2sodnNjLCAm
c2RwLCBzaXplb2Yoc2RwKSk7DQo+ICsNCj4gKwlpZiAocmV0KQ0KPiArCQlEUk1fREVCVUdfS01T
KCJGYWlsZWQgdG8gdW5wYWNrIERQIFZTQyBTRFBcbiIpOyB9DQo+ICsNCj4gK3N0YXRpYyB2b2lk
IGludGVsX3JlYWRfZHBfaGRyX21ldGFkYXRhX2luZm9mcmFtZV9zZHAoc3RydWN0IGludGVsX2Vu
Y29kZXINCj4gKmVuY29kZXIsDQo+ICsJCQkJCQkgICAgIHN0cnVjdCBpbnRlbF9jcnRjX3N0YXRl
DQo+ICpjcnRjX3N0YXRlLA0KPiArCQkJCQkJICAgICBzdHJ1Y3QgaGRtaV9kcm1faW5mb2ZyYW1l
DQo+ICpkcm1faW5mb2ZyYW1lKSB7DQo+ICsJc3RydWN0IGludGVsX2RpZ2l0YWxfcG9ydCAqaW50
ZWxfZGlnX3BvcnQgPSBlbmNfdG9fZGlnX3BvcnQoZW5jb2Rlcik7DQo+ICsJdW5zaWduZWQgaW50
IHR5cGUgPSBIRE1JX1BBQ0tFVF9UWVBFX0dBTVVUX01FVEFEQVRBOw0KPiArCXN0cnVjdCBkcF9z
ZHAgc2RwID0ge307DQo+ICsJaW50IHJldDsNCj4gKw0KPiArCWlmICgoY3J0Y19zdGF0ZS0+aW5m
b2ZyYW1lcy5lbmFibGUgJg0KPiArCSAgICBpbnRlbF9oZG1pX2luZm9mcmFtZV9lbmFibGUodHlw
ZSkpID09IDApDQo+ICsJCXJldHVybjsNCj4gKw0KPiArCWludGVsX2RpZ19wb3J0LT5yZWFkX2lu
Zm9mcmFtZShlbmNvZGVyLCBjcnRjX3N0YXRlLCB0eXBlLCAmc2RwLA0KPiArCQkJCSAgICAgICBz
aXplb2Yoc2RwKSk7DQo+ICsNCj4gKwlyZXQgPSBpbnRlbF9kcF9oZHJfbWV0YWRhdGFfaW5mb2Zy
YW1lX3NkcF91bnBhY2soZHJtX2luZm9mcmFtZSwgJnNkcCwNCj4gKwkJCQkJCQkgc2l6ZW9mKHNk
cCkpOw0KPiArDQo+ICsJaWYgKHJldCkNCj4gKwkJRFJNX0RFQlVHX0tNUygiRmFpbGVkIHRvIHVu
cGFjayBEUCBIRFIgTWV0YWRhdGEgSW5mb2ZyYW1lDQo+IFNEUFxuIik7IH0NCj4gKw0KPiArdm9p
ZCBpbnRlbF9yZWFkX2RwX3NkcChzdHJ1Y3QgaW50ZWxfZW5jb2RlciAqZW5jb2RlciwNCj4gKwkJ
ICAgICAgIHN0cnVjdCBpbnRlbF9jcnRjX3N0YXRlICpjcnRjX3N0YXRlLA0KPiArCQkgICAgICAg
dW5zaWduZWQgaW50IHR5cGUpDQo+ICt7DQo+ICsJc3dpdGNoICh0eXBlKSB7DQo+ICsJY2FzZSBE
UF9TRFBfVlNDOg0KPiArCQlpbnRlbF9yZWFkX2RwX3ZzY19zZHAoZW5jb2RlciwgY3J0Y19zdGF0
ZSwNCj4gKwkJCQkgICAgICAmY3J0Y19zdGF0ZS0+aW5mb2ZyYW1lcy52c2MpOw0KPiArCQlicmVh
azsNCj4gKwljYXNlIEhETUlfUEFDS0VUX1RZUEVfR0FNVVRfTUVUQURBVEE6DQo+ICsJCWludGVs
X3JlYWRfZHBfaGRyX21ldGFkYXRhX2luZm9mcmFtZV9zZHAoZW5jb2RlciwgY3J0Y19zdGF0ZSwN
Cj4gKwkJCQkJCQkgJmNydGNfc3RhdGUtDQo+ID5pbmZvZnJhbWVzLmRybS5kcm0pOw0KPiArCQli
cmVhazsNCj4gKwlkZWZhdWx0Og0KPiArCQlNSVNTSU5HX0NBU0UodHlwZSk7DQo+ICsJCWJyZWFr
Ow0KPiArCX0NCj4gK30NCj4gKw0KPiAgc3RhdGljIHZvaWQNCj4gIGludGVsX2RwX3NldHVwX3Zz
Y19zZHAoc3RydWN0IGludGVsX2RwICppbnRlbF9kcCwNCj4gIAkJICAgICAgIGNvbnN0IHN0cnVj
dCBpbnRlbF9jcnRjX3N0YXRlICpjcnRjX3N0YXRlLCBkaWZmIC0tZ2l0DQo+IGEvZHJpdmVycy9n
cHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9kcC5oDQo+IGIvZHJpdmVycy9ncHUvZHJtL2k5MTUv
ZGlzcGxheS9pbnRlbF9kcC5oDQo+IGluZGV4IDBkYzA5YTQ2M2VlMS4uZThmOWJhOTYyZDA5IDEw
MDY0NA0KPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9kaXNwbGF5L2ludGVsX2RwLmgNCj4g
KysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9kcC5oDQo+IEBAIC0xMTks
NiArMTE5LDkgQEAgdm9pZCBpbnRlbF9kcF9oZHJfbWV0YWRhdGFfZW5hYmxlKHN0cnVjdCBpbnRl
bF9kcA0KPiAqaW50ZWxfZHAsICB2b2lkIGludGVsX2RwX3NldF9pbmZvZnJhbWVzKHN0cnVjdCBp
bnRlbF9lbmNvZGVyICplbmNvZGVyLCBib29sDQo+IGVuYWJsZSwNCj4gIAkJCSAgICAgY29uc3Qg
c3RydWN0IGludGVsX2NydGNfc3RhdGUgKmNydGNfc3RhdGUsDQo+ICAJCQkgICAgIGNvbnN0IHN0
cnVjdCBkcm1fY29ubmVjdG9yX3N0YXRlICpjb25uX3N0YXRlKTsNCj4gK3ZvaWQgaW50ZWxfcmVh
ZF9kcF9zZHAoc3RydWN0IGludGVsX2VuY29kZXIgKmVuY29kZXIsDQo+ICsJCSAgICAgICBzdHJ1
Y3QgaW50ZWxfY3J0Y19zdGF0ZSAqY3J0Y19zdGF0ZSwNCj4gKwkJICAgICAgIHVuc2lnbmVkIGlu
dCB0eXBlKTsNCj4gIGJvb2wgaW50ZWxfZGlnaXRhbF9wb3J0X2Nvbm5lY3RlZChzdHJ1Y3QgaW50
ZWxfZW5jb2RlciAqZW5jb2Rlcik7DQo+IA0KPiAgc3RhdGljIGlubGluZSB1bnNpZ25lZCBpbnQg
aW50ZWxfZHBfdW51c2VkX2xhbmVfbWFzayhpbnQgbGFuZV9jb3VudCkNCj4gLS0NCj4gMi4yNC4x
DQo+IA0KPiBfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXw0K
PiBkcmktZGV2ZWwgbWFpbGluZyBsaXN0DQo+IGRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5v
cmcNCj4gaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmkt
ZGV2ZWwNCg=

RE: [PATCH v3 06/17] drm/i915/dp: Read out DP SDPs (Secondary Data Packet)

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 06/17] drm/i915/dp: Read out DP SDPs (Secondary Data Packet)

Drop the content in bracket.

> It adds code to read the DP SDPs from the video DIP and unpack them into the crtc
> state.
> 
> It adds routines that read out DP VSC SDP and DP HDR Metadata Infoframe SDP In
> order to unpack DP VSC SDP, it adds intel_dp_vsc_sdp_unpack() function.
> It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and [Table 2-117: VSC
> SDP Payload for DB16 through DB18]
> 
> In order to unpack DP HDR Metadata Infoframe SDP, it adds
> intel_dp_hdr_metadata_infoframe_sdp_unpack(). And it follows DP 1.4a spec.
> ([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and [Table 2-126: INFOFRAME
> SDP v1.2 Payload Data Bytes - DB0 through DB31]) and CTA-861-G spec. [Table-42
> Dynamic Range and Mastering InfoFrame].
> 
> A nameing rule and style of intel_read_dp_sdp() function references

Typo in naming.

> intel_read_infoframe() function of intel_hdmi.c
> 
> v2: Minor style fix
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
> 
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 170 ++++++++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_dp.h |   3 +
>  2 files changed, 173 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index dd7e5588001e..d4ece0a824c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4925,6 +4925,176 @@ void intel_dp_set_infoframes(struct intel_encoder
> *encoder,
>  	intel_write_dp_sdp(encoder, crtc_state,
> HDMI_PACKET_TYPE_GAMUT_METADATA);  }
> 
> +static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
> +				   const void *buffer, size_t size) {
> +	const struct dp_sdp *sdp = buffer;
> +
> +	if (size < sizeof(struct dp_sdp))
> +		return -EINVAL;
> +
> +	memset(vsc, 0, size);
> +
> +	if (sdp->sdp_header.HB0 != 0)
> +		return -EINVAL;
> +
> +	if (sdp->sdp_header.HB1 != DP_SDP_VSC)
> +		return -EINVAL;
> +	vsc->sdp_type = sdp->sdp_header.HB1;
> +
> +	if (sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) {
> +		vsc->revision = sdp->sdp_header.HB2;
> +		vsc->length = sdp->sdp_header.HB3;
> +	} else if (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) {
> +		vsc->revision = sdp->sdp_header.HB2;
> +		vsc->length = sdp->sdp_header.HB3;
> +	} else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
> +		vsc->revision = sdp->sdp_header.HB2;
> +		vsc->length = sdp->sdp_header.HB3;

The above 2 lines can be done unconditionally, may be combine the if checks.

> +		vsc->colorspace = (sdp->db[16] >> 4) & 0xf;
> +		vsc->colorimetry = sdp->db[16] & 0xf;
> +		vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
> +
> +		switch (sdp->db[17] & 0x7) {
> +		case 0x1:
> +			vsc->bpc = 8;
> +			break;
> +		case 0x2:
> +			vsc->bpc = 10;
> +			break;
> +		case 0x3:
> +			vsc->bpc = 12;
> +			break;
> +		case 0x4:
> +			vsc->bpc = 16;
> +			break;
> +		default:
> +			MISSING_CASE(sdp->db[17] & 0x7);

Handle 6bpc case as well.

> +			return -EINVAL;
> +		}
> +
> +		vsc->content_type = sdp->db[18] & 0x7;
> +	} else {
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
> +static int
> +intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe
> *drm_infoframe,
> +					   const void *buffer, size_t size) {
> +	int ret;
> +
> +	const struct dp_sdp *sdp = buffer;
> +
> +	if (size < sizeof(struct dp_sdp))
> +		return -EINVAL;
> +
> +	if (sdp->sdp_header.HB0 != 0)
> +		return -EINVAL;
> +
> +	if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
> +		return -EINVAL;
> +
> +	/*
> +	 * Least Significant Eight Bits of (Data Byte Count – 1)
> +	 * 1Dh (i.e., Data Byte Count = 30 bytes).
> +	 */
> +	if (sdp->sdp_header.HB2 != 0x1D)
> +		return -EINVAL;
> +
> +	/* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
> +	if ((sdp->sdp_header.HB3 & 0x3) != 0)
> +		return -EINVAL;
> +
> +	/* INFOFRAME SDP Version Number */
> +	if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
> +		return -EINVAL;
> +
> +	/* CTA Header Byte 2 (INFOFRAME Version Number) */
> +	if (sdp->db[0] != 1)
> +		return -EINVAL;
> +
> +	/* CTA Header Byte 3 (Length of INFOFRAME):
> HDMI_DRM_INFOFRAME_SIZE */
> +	if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
> +		return -EINVAL;
> +
> +	ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
> +					     HDMI_DRM_INFOFRAME_SIZE);
> +
> +	return ret;
> +}
> +
> +static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
> +				  struct intel_crtc_state *crtc_state,
> +				  struct drm_dp_vsc_sdp *vsc)
> +{
> +	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +	unsigned int type = DP_SDP_VSC;
> +	struct dp_sdp sdp = {};
> +	int ret;
> +
> +	/* When PSR is enabled, VSC SDP is handled by PSR routine */
> +	if (intel_psr_enabled(intel_dp))
> +		return;
> +
> +	if ((crtc_state->infoframes.enable &
> +	     intel_hdmi_infoframe_enable(type)) == 0)
> +		return;
> +
> +	intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
> +sizeof(sdp));
> +
> +	ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
> +
> +	if (ret)
> +		DRM_DEBUG_KMS("Failed to unpack DP VSC SDP\n"); }
> +
> +static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder
> *encoder,
> +						     struct intel_crtc_state
> *crtc_state,
> +						     struct hdmi_drm_infoframe
> *drm_infoframe) {
> +	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
> +	unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
> +	struct dp_sdp sdp = {};
> +	int ret;
> +
> +	if ((crtc_state->infoframes.enable &
> +	    intel_hdmi_infoframe_enable(type)) == 0)
> +		return;
> +
> +	intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
> +				       sizeof(sdp));
> +
> +	ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
> +							 sizeof(sdp));
> +
> +	if (ret)
> +		DRM_DEBUG_KMS("Failed to unpack DP HDR Metadata Infoframe
> SDP\n"); }
> +
> +void intel_read_dp_sdp(struct intel_encoder *encoder,
> +		       struct intel_crtc_state *crtc_state,
> +		       unsigned int type)
> +{
> +	switch (type) {
> +	case DP_SDP_VSC:
> +		intel_read_dp_vsc_sdp(encoder, crtc_state,
> +				      &crtc_state->infoframes.vsc);
> +		break;
> +	case HDMI_PACKET_TYPE_GAMUT_METADATA:
> +		intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
> +							 &crtc_state-
> >infoframes.drm.drm);
> +		break;
> +	default:
> +		MISSING_CASE(type);
> +		break;
> +	}
> +}
> +
>  static void
>  intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
>  		       const struct intel_crtc_state *crtc_state, diff --git
> a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index 0dc09a463ee1..e8f9ba962d09 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -119,6 +119,9 @@ void intel_dp_hdr_metadata_enable(struct intel_dp
> *intel_dp,  void intel_dp_set_infoframes(struct intel_encoder *encoder, bool
> enable,
>  			     const struct intel_crtc_state *crtc_state,
>  			     const struct drm_connector_state *conn_state);
> +void intel_read_dp_sdp(struct intel_encoder *encoder,
> +		       struct intel_crtc_state *crtc_state,
> +		       unsigned int type);
>  bool intel_digital_port_connected(struct intel_encoder *encoder);
> 
>  static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Intel-gfx] [PATCH v3 06/17] drm/i915/dp: Read out DP SDPs (Secondary Data Packet)

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 06/17] drm/i915/dp: Read out DP SDPs (Secondary Data Packet)

Drop the content in bracket.

> It adds code to read the DP SDPs from the video DIP and unpack them into the crtc
> state.
> 
> It adds routines that read out DP VSC SDP and DP HDR Metadata Infoframe SDP In
> order to unpack DP VSC SDP, it adds intel_dp_vsc_sdp_unpack() function.
> It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and [Table 2-117: VSC
> SDP Payload for DB16 through DB18]
> 
> In order to unpack DP HDR Metadata Infoframe SDP, it adds
> intel_dp_hdr_metadata_infoframe_sdp_unpack(). And it follows DP 1.4a spec.
> ([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and [Table 2-126: INFOFRAME
> SDP v1.2 Payload Data Bytes - DB0 through DB31]) and CTA-861-G spec. [Table-42
> Dynamic Range and Mastering InfoFrame].
> 
> A nameing rule and style of intel_read_dp_sdp() function references

Typo in naming.

> intel_read_infoframe() function of intel_hdmi.c
> 
> v2: Minor style fix
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
> 
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 170 ++++++++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_dp.h |   3 +
>  2 files changed, 173 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index dd7e5588001e..d4ece0a824c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4925,6 +4925,176 @@ void intel_dp_set_infoframes(struct intel_encoder
> *encoder,
>  	intel_write_dp_sdp(encoder, crtc_state,
> HDMI_PACKET_TYPE_GAMUT_METADATA);  }
> 
> +static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
> +				   const void *buffer, size_t size) {
> +	const struct dp_sdp *sdp = buffer;
> +
> +	if (size < sizeof(struct dp_sdp))
> +		return -EINVAL;
> +
> +	memset(vsc, 0, size);
> +
> +	if (sdp->sdp_header.HB0 != 0)
> +		return -EINVAL;
> +
> +	if (sdp->sdp_header.HB1 != DP_SDP_VSC)
> +		return -EINVAL;
> +	vsc->sdp_type = sdp->sdp_header.HB1;
> +
> +	if (sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) {
> +		vsc->revision = sdp->sdp_header.HB2;
> +		vsc->length = sdp->sdp_header.HB3;
> +	} else if (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) {
> +		vsc->revision = sdp->sdp_header.HB2;
> +		vsc->length = sdp->sdp_header.HB3;
> +	} else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
> +		vsc->revision = sdp->sdp_header.HB2;
> +		vsc->length = sdp->sdp_header.HB3;

The above 2 lines can be done unconditionally, may be combine the if checks.

> +		vsc->colorspace = (sdp->db[16] >> 4) & 0xf;
> +		vsc->colorimetry = sdp->db[16] & 0xf;
> +		vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
> +
> +		switch (sdp->db[17] & 0x7) {
> +		case 0x1:
> +			vsc->bpc = 8;
> +			break;
> +		case 0x2:
> +			vsc->bpc = 10;
> +			break;
> +		case 0x3:
> +			vsc->bpc = 12;
> +			break;
> +		case 0x4:
> +			vsc->bpc = 16;
> +			break;
> +		default:
> +			MISSING_CASE(sdp->db[17] & 0x7);

Handle 6bpc case as well.

> +			return -EINVAL;
> +		}
> +
> +		vsc->content_type = sdp->db[18] & 0x7;
> +	} else {
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
> +static int
> +intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe
> *drm_infoframe,
> +					   const void *buffer, size_t size) {
> +	int ret;
> +
> +	const struct dp_sdp *sdp = buffer;
> +
> +	if (size < sizeof(struct dp_sdp))
> +		return -EINVAL;
> +
> +	if (sdp->sdp_header.HB0 != 0)
> +		return -EINVAL;
> +
> +	if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
> +		return -EINVAL;
> +
> +	/*
> +	 * Least Significant Eight Bits of (Data Byte Count – 1)
> +	 * 1Dh (i.e., Data Byte Count = 30 bytes).
> +	 */
> +	if (sdp->sdp_header.HB2 != 0x1D)
> +		return -EINVAL;
> +
> +	/* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
> +	if ((sdp->sdp_header.HB3 & 0x3) != 0)
> +		return -EINVAL;
> +
> +	/* INFOFRAME SDP Version Number */
> +	if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
> +		return -EINVAL;
> +
> +	/* CTA Header Byte 2 (INFOFRAME Version Number) */
> +	if (sdp->db[0] != 1)
> +		return -EINVAL;
> +
> +	/* CTA Header Byte 3 (Length of INFOFRAME):
> HDMI_DRM_INFOFRAME_SIZE */
> +	if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
> +		return -EINVAL;
> +
> +	ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
> +					     HDMI_DRM_INFOFRAME_SIZE);
> +
> +	return ret;
> +}
> +
> +static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
> +				  struct intel_crtc_state *crtc_state,
> +				  struct drm_dp_vsc_sdp *vsc)
> +{
> +	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +	unsigned int type = DP_SDP_VSC;
> +	struct dp_sdp sdp = {};
> +	int ret;
> +
> +	/* When PSR is enabled, VSC SDP is handled by PSR routine */
> +	if (intel_psr_enabled(intel_dp))
> +		return;
> +
> +	if ((crtc_state->infoframes.enable &
> +	     intel_hdmi_infoframe_enable(type)) == 0)
> +		return;
> +
> +	intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
> +sizeof(sdp));
> +
> +	ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
> +
> +	if (ret)
> +		DRM_DEBUG_KMS("Failed to unpack DP VSC SDP\n"); }
> +
> +static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder
> *encoder,
> +						     struct intel_crtc_state
> *crtc_state,
> +						     struct hdmi_drm_infoframe
> *drm_infoframe) {
> +	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
> +	unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
> +	struct dp_sdp sdp = {};
> +	int ret;
> +
> +	if ((crtc_state->infoframes.enable &
> +	    intel_hdmi_infoframe_enable(type)) == 0)
> +		return;
> +
> +	intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
> +				       sizeof(sdp));
> +
> +	ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
> +							 sizeof(sdp));
> +
> +	if (ret)
> +		DRM_DEBUG_KMS("Failed to unpack DP HDR Metadata Infoframe
> SDP\n"); }
> +
> +void intel_read_dp_sdp(struct intel_encoder *encoder,
> +		       struct intel_crtc_state *crtc_state,
> +		       unsigned int type)
> +{
> +	switch (type) {
> +	case DP_SDP_VSC:
> +		intel_read_dp_vsc_sdp(encoder, crtc_state,
> +				      &crtc_state->infoframes.vsc);
> +		break;
> +	case HDMI_PACKET_TYPE_GAMUT_METADATA:
> +		intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
> +							 &crtc_state-
> >infoframes.drm.drm);
> +		break;
> +	default:
> +		MISSING_CASE(type);
> +		break;
> +	}
> +}
> +
>  static void
>  intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
>  		       const struct intel_crtc_state *crtc_state, diff --git
> a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index 0dc09a463ee1..e8f9ba962d09 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -119,6 +119,9 @@ void intel_dp_hdr_metadata_enable(struct intel_dp
> *intel_dp,  void intel_dp_set_infoframes(struct intel_encoder *encoder, bool
> enable,
>  			     const struct intel_crtc_state *crtc_state,
>  			     const struct drm_connector_state *conn_state);
> +void intel_read_dp_sdp(struct intel_encoder *encoder,
> +		       struct intel_crtc_state *crtc_state,
> +		       unsigned int type);
>  bool intel_digital_port_connected(struct intel_encoder *encoder);
> 
>  static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

RE: [Intel-gfx] [PATCH v3 07/17] drm: Add logging function for DP VSC SDP

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 07/17] drm: Add logging function for DP VSC SDP
> 
> When receiving video it is very useful to be able to log DP VSC SDP.
> This greatly simplifies debugging.
> 
> v2: Minor style fix
> v3: Move logging functions to drm core [Jani N]

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/drm_dp_helper.c | 174 ++++++++++++++++++++++++++++++++
>  include/drm/drm_dp_helper.h     |   3 +
>  2 files changed, 177 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 5a103e9b3c86..5e3aef8c32e0 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -1395,3 +1395,177 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8
> dsc_dpcd[DP_DSC_RECEIVER_CAP_S
>  	return num_bpc;
>  }
>  EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
> +
> +static const char *dp_colorspace_get_name(enum dp_colorspace
> +colorspace) {
> +	if (colorspace < 0 || colorspace > DP_COLORSPACE_RESERVED)
> +		return "Invalid";
> +
> +	switch (colorspace) {
> +	case DP_COLORSPACE_RGB:
> +		return "RGB";
> +	case DP_COLORSPACE_YUV444:
> +		return "YUV444";
> +	case DP_COLORSPACE_YUV422:
> +		return "YUV422";
> +	case DP_COLORSPACE_YUV420:
> +		return "YUV420";
> +	case DP_COLORSPACE_Y_ONLY:
> +		return "Y_ONLY";
> +	case DP_COLORSPACE_RAW:
> +		return "RAW";
> +	default:
> +		return "Reserved";
> +	}
> +}
> +
> +static const char *dp_colorimetry_get_name(enum dp_colorspace colorspace,
> +					   enum dp_colorimetry colorimetry) {
> +	if (colorspace < 0 || colorspace > DP_COLORSPACE_RESERVED)
> +		return "Invalid";
> +
> +	switch (colorimetry) {
> +	case DP_COLORIMETRY_DEFAULT:
> +		switch (colorspace) {
> +		case DP_COLORSPACE_RGB:
> +			return "sRGB";
> +		case DP_COLORSPACE_YUV444:
> +		case DP_COLORSPACE_YUV422:
> +		case DP_COLORSPACE_YUV420:
> +			return "BT.601";
> +		case DP_COLORSPACE_Y_ONLY:
> +			return "DICOM PS3.14";
> +		case DP_COLORSPACE_RAW:
> +			return "Custom Color Profile";
> +		default:
> +			return "Reserved";
> +		}
> +	case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and
> DP_COLORIMETRY_BT709_YCC */
> +		switch (colorspace) {
> +		case DP_COLORSPACE_RGB:
> +			return "Wide Fixed";
> +		case DP_COLORSPACE_YUV444:
> +		case DP_COLORSPACE_YUV422:
> +		case DP_COLORSPACE_YUV420:
> +			return "BT.709";
> +		default:
> +			return "Reserved";
> +		}
> +	case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and
> DP_COLORIMETRY_XVYCC_601 */
> +		switch (colorspace) {
> +		case DP_COLORSPACE_RGB:
> +			return "Wide Float";
> +		case DP_COLORSPACE_YUV444:
> +		case DP_COLORSPACE_YUV422:
> +		case DP_COLORSPACE_YUV420:
> +			return "xvYCC 601";
> +		default:
> +			return "Reserved";
> +		}
> +	case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
> +		switch (colorspace) {
> +		case DP_COLORSPACE_RGB:
> +			return "OpRGB";
> +		case DP_COLORSPACE_YUV444:
> +		case DP_COLORSPACE_YUV422:
> +		case DP_COLORSPACE_YUV420:
> +			return "xvYCC 709";
> +		default:
> +			return "Reserved";
> +		}
> +	case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601
> */
> +		switch (colorspace) {
> +		case DP_COLORSPACE_RGB:
> +			return "DCI-P3";
> +		case DP_COLORSPACE_YUV444:
> +		case DP_COLORSPACE_YUV422:
> +		case DP_COLORSPACE_YUV420:
> +			return "sYCC 601";
> +		default:
> +			return "Reserved";
> +		}
> +	case DP_COLORIMETRY_RGB_CUSTOM: /* and
> DP_COLORIMETRY_OPYCC_601 */
> +		switch (colorspace) {
> +		case DP_COLORSPACE_RGB:
> +			return "Custom Profile";
> +		case DP_COLORSPACE_YUV444:
> +		case DP_COLORSPACE_YUV422:
> +		case DP_COLORSPACE_YUV420:
> +			return "OpYCC 601";
> +		default:
> +			return "Reserved";
> +		}
> +	case DP_COLORIMETRY_BT2020_RGB: /* and
> DP_COLORIMETRY_BT2020_CYCC */
> +		switch (colorspace) {
> +		case DP_COLORSPACE_RGB:
> +			return "BT.2020 RGB";
> +		case DP_COLORSPACE_YUV444:
> +		case DP_COLORSPACE_YUV422:
> +		case DP_COLORSPACE_YUV420:
> +			return "BT.2020 CYCC";
> +		default:
> +			return "Reserved";
> +		}
> +	case DP_COLORIMETRY_BT2020_YCC:
> +		switch (colorspace) {
> +		case DP_COLORSPACE_YUV444:
> +		case DP_COLORSPACE_YUV422:
> +		case DP_COLORSPACE_YUV420:
> +			return "BT.2020 YCC";
> +		default:
> +			return "Reserved";
> +		}
> +	default:
> +		return "Invalid";
> +	}
> +}
> +
> +static const char *dp_dynamic_range_get_name(enum dp_dynamic_range
> +dynamic_range) {
> +	switch (dynamic_range) {
> +	case DP_DYNAMIC_RANGE_VESA:
> +		return "VESA range";
> +	case DP_DYNAMIC_RANGE_CTA:
> +		return "CTA range";
> +	default:
> +		return "Invalid";
> +	}
> +}
> +
> +static const char *dp_content_type_get_name(enum dp_content_type
> +content_type) {
> +	switch (content_type) {
> +	case DP_CONTENT_TYPE_NOT_DEFINED:
> +		return "Not defined";
> +	case DP_CONTENT_TYPE_GRAPHICS:
> +		return "Graphics";
> +	case DP_CONTENT_TYPE_PHOTO:
> +		return "Photo";
> +	case DP_CONTENT_TYPE_VIDEO:
> +		return "Video";
> +	case DP_CONTENT_TYPE_GAME:
> +		return "Game";
> +	default:
> +		return "Reserved";
> +	}
> +}
> +
> +void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
> +			const struct drm_dp_vsc_sdp *vsc)
> +{
> +#define DP_SDP_LOG(fmt, ...) dev_printk(level, dev, fmt, ##__VA_ARGS__)
> +	DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC",
> +		   vsc->revision, vsc->length);
> +	DP_SDP_LOG("    colorspace: %s\n",
> +		   dp_colorspace_get_name(vsc->colorspace));
> +	DP_SDP_LOG("    colorimetry: %s\n",
> +		   dp_colorimetry_get_name(vsc->colorspace, vsc->colorimetry));
> +	DP_SDP_LOG("    bpc: %u\n", vsc->bpc);
> +	DP_SDP_LOG("    dynamic range: %s\n",
> +		   dp_dynamic_range_get_name(vsc->dynamic_range));
> +	DP_SDP_LOG("    content type: %s\n",
> +		   dp_content_type_get_name(vsc->content_type));
> +#undef DP_SDP_LOG
> +}
> +EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index
> c098727681fa..00b775df6241 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1266,6 +1266,9 @@ struct drm_dp_vsc_sdp {
>  	enum dp_content_type content_type;
>  };
> 
> +void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
> +			const struct drm_dp_vsc_sdp *vsc);
> +
>  int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
> 
>  static inline int
> --
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

RE: [Intel-gfx] [PATCH v3 07/17] drm: Add logging function for DP VSC SDP

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 07/17] drm: Add logging function for DP VSC SDP
> 
> When receiving video it is very useful to be able to log DP VSC SDP.
> This greatly simplifies debugging.
> 
> v2: Minor style fix
> v3: Move logging functions to drm core [Jani N]

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/drm_dp_helper.c | 174 ++++++++++++++++++++++++++++++++
>  include/drm/drm_dp_helper.h     |   3 +
>  2 files changed, 177 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 5a103e9b3c86..5e3aef8c32e0 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -1395,3 +1395,177 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8
> dsc_dpcd[DP_DSC_RECEIVER_CAP_S
>  	return num_bpc;
>  }
>  EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
> +
> +static const char *dp_colorspace_get_name(enum dp_colorspace
> +colorspace) {
> +	if (colorspace < 0 || colorspace > DP_COLORSPACE_RESERVED)
> +		return "Invalid";
> +
> +	switch (colorspace) {
> +	case DP_COLORSPACE_RGB:
> +		return "RGB";
> +	case DP_COLORSPACE_YUV444:
> +		return "YUV444";
> +	case DP_COLORSPACE_YUV422:
> +		return "YUV422";
> +	case DP_COLORSPACE_YUV420:
> +		return "YUV420";
> +	case DP_COLORSPACE_Y_ONLY:
> +		return "Y_ONLY";
> +	case DP_COLORSPACE_RAW:
> +		return "RAW";
> +	default:
> +		return "Reserved";
> +	}
> +}
> +
> +static const char *dp_colorimetry_get_name(enum dp_colorspace colorspace,
> +					   enum dp_colorimetry colorimetry) {
> +	if (colorspace < 0 || colorspace > DP_COLORSPACE_RESERVED)
> +		return "Invalid";
> +
> +	switch (colorimetry) {
> +	case DP_COLORIMETRY_DEFAULT:
> +		switch (colorspace) {
> +		case DP_COLORSPACE_RGB:
> +			return "sRGB";
> +		case DP_COLORSPACE_YUV444:
> +		case DP_COLORSPACE_YUV422:
> +		case DP_COLORSPACE_YUV420:
> +			return "BT.601";
> +		case DP_COLORSPACE_Y_ONLY:
> +			return "DICOM PS3.14";
> +		case DP_COLORSPACE_RAW:
> +			return "Custom Color Profile";
> +		default:
> +			return "Reserved";
> +		}
> +	case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and
> DP_COLORIMETRY_BT709_YCC */
> +		switch (colorspace) {
> +		case DP_COLORSPACE_RGB:
> +			return "Wide Fixed";
> +		case DP_COLORSPACE_YUV444:
> +		case DP_COLORSPACE_YUV422:
> +		case DP_COLORSPACE_YUV420:
> +			return "BT.709";
> +		default:
> +			return "Reserved";
> +		}
> +	case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and
> DP_COLORIMETRY_XVYCC_601 */
> +		switch (colorspace) {
> +		case DP_COLORSPACE_RGB:
> +			return "Wide Float";
> +		case DP_COLORSPACE_YUV444:
> +		case DP_COLORSPACE_YUV422:
> +		case DP_COLORSPACE_YUV420:
> +			return "xvYCC 601";
> +		default:
> +			return "Reserved";
> +		}
> +	case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
> +		switch (colorspace) {
> +		case DP_COLORSPACE_RGB:
> +			return "OpRGB";
> +		case DP_COLORSPACE_YUV444:
> +		case DP_COLORSPACE_YUV422:
> +		case DP_COLORSPACE_YUV420:
> +			return "xvYCC 709";
> +		default:
> +			return "Reserved";
> +		}
> +	case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601
> */
> +		switch (colorspace) {
> +		case DP_COLORSPACE_RGB:
> +			return "DCI-P3";
> +		case DP_COLORSPACE_YUV444:
> +		case DP_COLORSPACE_YUV422:
> +		case DP_COLORSPACE_YUV420:
> +			return "sYCC 601";
> +		default:
> +			return "Reserved";
> +		}
> +	case DP_COLORIMETRY_RGB_CUSTOM: /* and
> DP_COLORIMETRY_OPYCC_601 */
> +		switch (colorspace) {
> +		case DP_COLORSPACE_RGB:
> +			return "Custom Profile";
> +		case DP_COLORSPACE_YUV444:
> +		case DP_COLORSPACE_YUV422:
> +		case DP_COLORSPACE_YUV420:
> +			return "OpYCC 601";
> +		default:
> +			return "Reserved";
> +		}
> +	case DP_COLORIMETRY_BT2020_RGB: /* and
> DP_COLORIMETRY_BT2020_CYCC */
> +		switch (colorspace) {
> +		case DP_COLORSPACE_RGB:
> +			return "BT.2020 RGB";
> +		case DP_COLORSPACE_YUV444:
> +		case DP_COLORSPACE_YUV422:
> +		case DP_COLORSPACE_YUV420:
> +			return "BT.2020 CYCC";
> +		default:
> +			return "Reserved";
> +		}
> +	case DP_COLORIMETRY_BT2020_YCC:
> +		switch (colorspace) {
> +		case DP_COLORSPACE_YUV444:
> +		case DP_COLORSPACE_YUV422:
> +		case DP_COLORSPACE_YUV420:
> +			return "BT.2020 YCC";
> +		default:
> +			return "Reserved";
> +		}
> +	default:
> +		return "Invalid";
> +	}
> +}
> +
> +static const char *dp_dynamic_range_get_name(enum dp_dynamic_range
> +dynamic_range) {
> +	switch (dynamic_range) {
> +	case DP_DYNAMIC_RANGE_VESA:
> +		return "VESA range";
> +	case DP_DYNAMIC_RANGE_CTA:
> +		return "CTA range";
> +	default:
> +		return "Invalid";
> +	}
> +}
> +
> +static const char *dp_content_type_get_name(enum dp_content_type
> +content_type) {
> +	switch (content_type) {
> +	case DP_CONTENT_TYPE_NOT_DEFINED:
> +		return "Not defined";
> +	case DP_CONTENT_TYPE_GRAPHICS:
> +		return "Graphics";
> +	case DP_CONTENT_TYPE_PHOTO:
> +		return "Photo";
> +	case DP_CONTENT_TYPE_VIDEO:
> +		return "Video";
> +	case DP_CONTENT_TYPE_GAME:
> +		return "Game";
> +	default:
> +		return "Reserved";
> +	}
> +}
> +
> +void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
> +			const struct drm_dp_vsc_sdp *vsc)
> +{
> +#define DP_SDP_LOG(fmt, ...) dev_printk(level, dev, fmt, ##__VA_ARGS__)
> +	DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC",
> +		   vsc->revision, vsc->length);
> +	DP_SDP_LOG("    colorspace: %s\n",
> +		   dp_colorspace_get_name(vsc->colorspace));
> +	DP_SDP_LOG("    colorimetry: %s\n",
> +		   dp_colorimetry_get_name(vsc->colorspace, vsc->colorimetry));
> +	DP_SDP_LOG("    bpc: %u\n", vsc->bpc);
> +	DP_SDP_LOG("    dynamic range: %s\n",
> +		   dp_dynamic_range_get_name(vsc->dynamic_range));
> +	DP_SDP_LOG("    content type: %s\n",
> +		   dp_content_type_get_name(vsc->content_type));
> +#undef DP_SDP_LOG
> +}
> +EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index
> c098727681fa..00b775df6241 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1266,6 +1266,9 @@ struct drm_dp_vsc_sdp {
>  	enum dp_content_type content_type;
>  };
> 
> +void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
> +			const struct drm_dp_vsc_sdp *vsc);
> +
>  int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
> 
>  static inline int
> --
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Intel-gfx] [PATCH v3 07/17] drm: Add logging function for DP VSC SDP

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 07/17] drm: Add logging function for DP VSC SDP
> 
> When receiving video it is very useful to be able to log DP VSC SDP.
> This greatly simplifies debugging.
> 
> v2: Minor style fix
> v3: Move logging functions to drm core [Jani N]

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/drm_dp_helper.c | 174 ++++++++++++++++++++++++++++++++
>  include/drm/drm_dp_helper.h     |   3 +
>  2 files changed, 177 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 5a103e9b3c86..5e3aef8c32e0 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -1395,3 +1395,177 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8
> dsc_dpcd[DP_DSC_RECEIVER_CAP_S
>  	return num_bpc;
>  }
>  EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
> +
> +static const char *dp_colorspace_get_name(enum dp_colorspace
> +colorspace) {
> +	if (colorspace < 0 || colorspace > DP_COLORSPACE_RESERVED)
> +		return "Invalid";
> +
> +	switch (colorspace) {
> +	case DP_COLORSPACE_RGB:
> +		return "RGB";
> +	case DP_COLORSPACE_YUV444:
> +		return "YUV444";
> +	case DP_COLORSPACE_YUV422:
> +		return "YUV422";
> +	case DP_COLORSPACE_YUV420:
> +		return "YUV420";
> +	case DP_COLORSPACE_Y_ONLY:
> +		return "Y_ONLY";
> +	case DP_COLORSPACE_RAW:
> +		return "RAW";
> +	default:
> +		return "Reserved";
> +	}
> +}
> +
> +static const char *dp_colorimetry_get_name(enum dp_colorspace colorspace,
> +					   enum dp_colorimetry colorimetry) {
> +	if (colorspace < 0 || colorspace > DP_COLORSPACE_RESERVED)
> +		return "Invalid";
> +
> +	switch (colorimetry) {
> +	case DP_COLORIMETRY_DEFAULT:
> +		switch (colorspace) {
> +		case DP_COLORSPACE_RGB:
> +			return "sRGB";
> +		case DP_COLORSPACE_YUV444:
> +		case DP_COLORSPACE_YUV422:
> +		case DP_COLORSPACE_YUV420:
> +			return "BT.601";
> +		case DP_COLORSPACE_Y_ONLY:
> +			return "DICOM PS3.14";
> +		case DP_COLORSPACE_RAW:
> +			return "Custom Color Profile";
> +		default:
> +			return "Reserved";
> +		}
> +	case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and
> DP_COLORIMETRY_BT709_YCC */
> +		switch (colorspace) {
> +		case DP_COLORSPACE_RGB:
> +			return "Wide Fixed";
> +		case DP_COLORSPACE_YUV444:
> +		case DP_COLORSPACE_YUV422:
> +		case DP_COLORSPACE_YUV420:
> +			return "BT.709";
> +		default:
> +			return "Reserved";
> +		}
> +	case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and
> DP_COLORIMETRY_XVYCC_601 */
> +		switch (colorspace) {
> +		case DP_COLORSPACE_RGB:
> +			return "Wide Float";
> +		case DP_COLORSPACE_YUV444:
> +		case DP_COLORSPACE_YUV422:
> +		case DP_COLORSPACE_YUV420:
> +			return "xvYCC 601";
> +		default:
> +			return "Reserved";
> +		}
> +	case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
> +		switch (colorspace) {
> +		case DP_COLORSPACE_RGB:
> +			return "OpRGB";
> +		case DP_COLORSPACE_YUV444:
> +		case DP_COLORSPACE_YUV422:
> +		case DP_COLORSPACE_YUV420:
> +			return "xvYCC 709";
> +		default:
> +			return "Reserved";
> +		}
> +	case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601
> */
> +		switch (colorspace) {
> +		case DP_COLORSPACE_RGB:
> +			return "DCI-P3";
> +		case DP_COLORSPACE_YUV444:
> +		case DP_COLORSPACE_YUV422:
> +		case DP_COLORSPACE_YUV420:
> +			return "sYCC 601";
> +		default:
> +			return "Reserved";
> +		}
> +	case DP_COLORIMETRY_RGB_CUSTOM: /* and
> DP_COLORIMETRY_OPYCC_601 */
> +		switch (colorspace) {
> +		case DP_COLORSPACE_RGB:
> +			return "Custom Profile";
> +		case DP_COLORSPACE_YUV444:
> +		case DP_COLORSPACE_YUV422:
> +		case DP_COLORSPACE_YUV420:
> +			return "OpYCC 601";
> +		default:
> +			return "Reserved";
> +		}
> +	case DP_COLORIMETRY_BT2020_RGB: /* and
> DP_COLORIMETRY_BT2020_CYCC */
> +		switch (colorspace) {
> +		case DP_COLORSPACE_RGB:
> +			return "BT.2020 RGB";
> +		case DP_COLORSPACE_YUV444:
> +		case DP_COLORSPACE_YUV422:
> +		case DP_COLORSPACE_YUV420:
> +			return "BT.2020 CYCC";
> +		default:
> +			return "Reserved";
> +		}
> +	case DP_COLORIMETRY_BT2020_YCC:
> +		switch (colorspace) {
> +		case DP_COLORSPACE_YUV444:
> +		case DP_COLORSPACE_YUV422:
> +		case DP_COLORSPACE_YUV420:
> +			return "BT.2020 YCC";
> +		default:
> +			return "Reserved";
> +		}
> +	default:
> +		return "Invalid";
> +	}
> +}
> +
> +static const char *dp_dynamic_range_get_name(enum dp_dynamic_range
> +dynamic_range) {
> +	switch (dynamic_range) {
> +	case DP_DYNAMIC_RANGE_VESA:
> +		return "VESA range";
> +	case DP_DYNAMIC_RANGE_CTA:
> +		return "CTA range";
> +	default:
> +		return "Invalid";
> +	}
> +}
> +
> +static const char *dp_content_type_get_name(enum dp_content_type
> +content_type) {
> +	switch (content_type) {
> +	case DP_CONTENT_TYPE_NOT_DEFINED:
> +		return "Not defined";
> +	case DP_CONTENT_TYPE_GRAPHICS:
> +		return "Graphics";
> +	case DP_CONTENT_TYPE_PHOTO:
> +		return "Photo";
> +	case DP_CONTENT_TYPE_VIDEO:
> +		return "Video";
> +	case DP_CONTENT_TYPE_GAME:
> +		return "Game";
> +	default:
> +		return "Reserved";
> +	}
> +}
> +
> +void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
> +			const struct drm_dp_vsc_sdp *vsc)
> +{
> +#define DP_SDP_LOG(fmt, ...) dev_printk(level, dev, fmt, ##__VA_ARGS__)
> +	DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC",
> +		   vsc->revision, vsc->length);
> +	DP_SDP_LOG("    colorspace: %s\n",
> +		   dp_colorspace_get_name(vsc->colorspace));
> +	DP_SDP_LOG("    colorimetry: %s\n",
> +		   dp_colorimetry_get_name(vsc->colorspace, vsc->colorimetry));
> +	DP_SDP_LOG("    bpc: %u\n", vsc->bpc);
> +	DP_SDP_LOG("    dynamic range: %s\n",
> +		   dp_dynamic_range_get_name(vsc->dynamic_range));
> +	DP_SDP_LOG("    content type: %s\n",
> +		   dp_content_type_get_name(vsc->content_type));
> +#undef DP_SDP_LOG
> +}
> +EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index
> c098727681fa..00b775df6241 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1266,6 +1266,9 @@ struct drm_dp_vsc_sdp {
>  	enum dp_content_type content_type;
>  };
> 
> +void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
> +			const struct drm_dp_vsc_sdp *vsc);
> +
>  int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
> 
>  static inline int
> --
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

RE: [PATCH v3 08/17] drm/i915: Include HDMI DRM infoframe in the crtc state dump

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 08/17] drm/i915: Include HDMI DRM infoframe in the crtc state
> dump
> 
> Dump out the HDMI Dynamic Range and Mastering (DRM) infoframe in the normal
> crtc state dump.

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index c0e5002ce64c..239861bcedba 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13030,6 +13030,9 @@ static void intel_dump_pipe_config(const struct
> intel_crtc_state *pipe_config,
>  	if (pipe_config->infoframes.enable &
>  	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
>  		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
> +	if (pipe_config->infoframes.enable &
> +	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
> +		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
> 
>  	drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
>  	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

RE: [PATCH v3 08/17] drm/i915: Include HDMI DRM infoframe in the crtc state dump

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 08/17] drm/i915: Include HDMI DRM infoframe in the crtc state
> dump
> 
> Dump out the HDMI Dynamic Range and Mastering (DRM) infoframe in the normal
> crtc state dump.

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index c0e5002ce64c..239861bcedba 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13030,6 +13030,9 @@ static void intel_dump_pipe_config(const struct
> intel_crtc_state *pipe_config,
>  	if (pipe_config->infoframes.enable &
>  	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
>  		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
> +	if (pipe_config->infoframes.enable &
> +	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
> +		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
> 
>  	drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
>  	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Intel-gfx] [PATCH v3 08/17] drm/i915: Include HDMI DRM infoframe in the crtc state dump

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 08/17] drm/i915: Include HDMI DRM infoframe in the crtc state
> dump
> 
> Dump out the HDMI Dynamic Range and Mastering (DRM) infoframe in the normal
> crtc state dump.

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index c0e5002ce64c..239861bcedba 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13030,6 +13030,9 @@ static void intel_dump_pipe_config(const struct
> intel_crtc_state *pipe_config,
>  	if (pipe_config->infoframes.enable &
>  	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
>  		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
> +	if (pipe_config->infoframes.enable &
> +	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
> +		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
> 
>  	drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
>  	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

RE: [PATCH v3 09/17] drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 09/17] drm/i915: Include DP HDR Metadata Infoframe SDP in the
> crtc state dump
> 
> Dump out the DP HDR Metadata Infoframe SDP in the normal crtc state dump.
> 
> HDMI Dynamic Range and Mastering (DRM) infoframe and DP HDR Metadata
> Infoframe SDP use the same member variable in infoframes of crtc state.

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 239861bcedba..593c63f51210 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13033,6 +13033,9 @@ static void intel_dump_pipe_config(const struct
> intel_crtc_state *pipe_config,
>  	if (pipe_config->infoframes.enable &
>  	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
>  		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
> +	if (pipe_config->infoframes.enable &
> +	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
> +		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
> 
>  	drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
>  	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

RE: [PATCH v3 09/17] drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 09/17] drm/i915: Include DP HDR Metadata Infoframe SDP in the
> crtc state dump
> 
> Dump out the DP HDR Metadata Infoframe SDP in the normal crtc state dump.
> 
> HDMI Dynamic Range and Mastering (DRM) infoframe and DP HDR Metadata
> Infoframe SDP use the same member variable in infoframes of crtc state.

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 239861bcedba..593c63f51210 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13033,6 +13033,9 @@ static void intel_dump_pipe_config(const struct
> intel_crtc_state *pipe_config,
>  	if (pipe_config->infoframes.enable &
>  	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
>  		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
> +	if (pipe_config->infoframes.enable &
> +	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
> +		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
> 
>  	drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
>  	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Intel-gfx] [PATCH v3 09/17] drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 09/17] drm/i915: Include DP HDR Metadata Infoframe SDP in the
> crtc state dump
> 
> Dump out the DP HDR Metadata Infoframe SDP in the normal crtc state dump.
> 
> HDMI Dynamic Range and Mastering (DRM) infoframe and DP HDR Metadata
> Infoframe SDP use the same member variable in infoframes of crtc state.

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 239861bcedba..593c63f51210 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13033,6 +13033,9 @@ static void intel_dump_pipe_config(const struct
> intel_crtc_state *pipe_config,
>  	if (pipe_config->infoframes.enable &
>  	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
>  		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
> +	if (pipe_config->infoframes.enable &
> +	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
> +		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
> 
>  	drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
>  	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

RE: [PATCH v3 10/17] drm/i915: Include DP VSC SDP in the crtc state dump

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 10/17] drm/i915: Include DP VSC SDP in the crtc state dump
> 
> Dump out the DP VSC SDP in the normal crtc state dump
> 
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
>     Use drm core's DP VSC SDP logging function

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 593c63f51210..4f187fd330e8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -12878,6 +12878,16 @@ intel_dump_infoframe(struct drm_i915_private
> *dev_priv,
>  	hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);  }
> 
> +static void
> +intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
> +		      const struct drm_dp_vsc_sdp *vsc) {
> +	if (!drm_debug_enabled(DRM_UT_KMS))
> +		return;
> +
> +	drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc); }
> +
>  #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
> 
>  static const char * const output_type_str[] = { @@ -13036,6 +13046,9 @@ static
> void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
>  	if (pipe_config->infoframes.enable &
>  	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
>  		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
> +	if (pipe_config->infoframes.enable &
> +	    intel_hdmi_infoframe_enable(DP_SDP_VSC))
> +		intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
> 
>  	drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
>  	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

RE: [PATCH v3 10/17] drm/i915: Include DP VSC SDP in the crtc state dump

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 10/17] drm/i915: Include DP VSC SDP in the crtc state dump
> 
> Dump out the DP VSC SDP in the normal crtc state dump
> 
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
>     Use drm core's DP VSC SDP logging function

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 593c63f51210..4f187fd330e8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -12878,6 +12878,16 @@ intel_dump_infoframe(struct drm_i915_private
> *dev_priv,
>  	hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);  }
> 
> +static void
> +intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
> +		      const struct drm_dp_vsc_sdp *vsc) {
> +	if (!drm_debug_enabled(DRM_UT_KMS))
> +		return;
> +
> +	drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc); }
> +
>  #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
> 
>  static const char * const output_type_str[] = { @@ -13036,6 +13046,9 @@ static
> void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
>  	if (pipe_config->infoframes.enable &
>  	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
>  		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
> +	if (pipe_config->infoframes.enable &
> +	    intel_hdmi_infoframe_enable(DP_SDP_VSC))
> +		intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
> 
>  	drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
>  	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Intel-gfx] [PATCH v3 10/17] drm/i915: Include DP VSC SDP in the crtc state dump

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 10/17] drm/i915: Include DP VSC SDP in the crtc state dump
> 
> Dump out the DP VSC SDP in the normal crtc state dump
> 
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
>     Use drm core's DP VSC SDP logging function

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 593c63f51210..4f187fd330e8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -12878,6 +12878,16 @@ intel_dump_infoframe(struct drm_i915_private
> *dev_priv,
>  	hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);  }
> 
> +static void
> +intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
> +		      const struct drm_dp_vsc_sdp *vsc) {
> +	if (!drm_debug_enabled(DRM_UT_KMS))
> +		return;
> +
> +	drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc); }
> +
>  #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
> 
>  static const char * const output_type_str[] = { @@ -13036,6 +13046,9 @@ static
> void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
>  	if (pipe_config->infoframes.enable &
>  	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
>  		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
> +	if (pipe_config->infoframes.enable &
> +	    intel_hdmi_infoframe_enable(DP_SDP_VSC))
> +		intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
> 
>  	drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
>  	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

RE: [Intel-gfx] [PATCH v3 11/17] drm/i915: Program DP SDPs with computed configs

[Shankar, Uma]

DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogSW50ZWwtZ2Z4IDxpbnRl
bC1nZngtYm91bmNlc0BsaXN0cy5mcmVlZGVza3RvcC5vcmc+IE9uIEJlaGFsZiBPZiBHd2FuLQ0K
PiBneWVvbmcgTXVuDQo+IFNlbnQ6IFR1ZXNkYXksIEZlYnJ1YXJ5IDQsIDIwMjAgNDo1MCBBTQ0K
PiBUbzogaW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZw0KPiBDYzogbGludXgtZmJkZXZA
dmdlci5rZXJuZWwub3JnOyBkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnDQo+IFN1Ympl
Y3Q6IFtJbnRlbC1nZnhdIFtQQVRDSCB2MyAxMS8xN10gZHJtL2k5MTU6IFByb2dyYW0gRFAgU0RQ
cyB3aXRoIGNvbXB1dGVkDQo+IGNvbmZpZ3MNCj4gDQo+IEluIG9yZGVyIHRvIHVzZSBjb21wdXRl
ZCBjb25maWcgZm9yIERQIFNEUHMgKERQIFZTQyBTRFAgYW5kIERQIEhEUiBNZXRhZGF0YQ0KPiBJ
bmZvZnJhbWUgU0RQKSwgaXQgcmVwbGFjZXMgaW50ZWxfZHBfdnNjX2VuYWJsZSgpIGZ1bmN0aW9u
IGFuZA0KPiBpbnRlbF9kcF9oZHJfbWV0YWRhdGFfZW5hYmxlKCkgZnVuY3Rpb24gdG8gaW50ZWxf
ZHBfc2V0X2luZm9mcmFtZXMoKSBmdW5jdGlvbi4NCj4gDQo+IEJlZm9yZSBhcHBseWluZyBpdCwg
cm91dGluZXMgb2YgcHJvZ3JhbSBTRFAgYWx3YXlzIGNhbGN1bGF0ZWQgY29uZmlncyB3aGVuIHRo
ZXkNCj4gY2FsbGVkLiBBbmQgaXQgcmVtb3ZlcyB1bnVzZWQgZnVuY3Rpb25zLg0KDQpGaXggdGhl
IHNlbnRlbmNlLCBzZWVtcyB1bmNsZWFyLg0KV2l0aCB0aGF0IGZpeGVkLA0KUmV2aWV3ZWQtYnk6
IFVtYSBTaGFua2FyIDx1bWEuc2hhbmthckBpbnRlbC5jb20+DQoNCj4gDQo+IHYzOiBSZWJhc2Vk
DQo+IA0KPiBTaWduZWQtb2ZmLWJ5OiBHd2FuLWd5ZW9uZyBNdW4gPGd3YW4tZ3llb25nLm11bkBp
bnRlbC5jb20+DQo+IC0tLQ0KPiAgZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9k
ZGkuYyB8ICAgMyArLQ0KPiAgZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9kcC5j
ICB8IDIyNiAtLS0tLS0tLS0tLS0tLS0tLS0tLS0tLQ0KPiAgZHJpdmVycy9ncHUvZHJtL2k5MTUv
ZGlzcGxheS9pbnRlbF9kcC5oICB8ICAgNiAtDQo+ICAzIGZpbGVzIGNoYW5nZWQsIDEgaW5zZXJ0
aW9uKCspLCAyMzQgZGVsZXRpb25zKC0pDQo+IA0KPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUv
ZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9kZGkuYw0KPiBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2Rp
c3BsYXkvaW50ZWxfZGRpLmMNCj4gaW5kZXggYzk2ZjYyOWNkZGMzLi4zNzRhYjZhMzc1N2MgMTAw
NjQ0DQo+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2Rpc3BsYXkvaW50ZWxfZGRpLmMNCj4g
KysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9kZGkuYw0KPiBAQCAtMzkw
MCw4ICszOTAwLDcgQEAgc3RhdGljIHZvaWQgaW50ZWxfZW5hYmxlX2RkaV9kcChzdHJ1Y3QgaW50
ZWxfZW5jb2Rlcg0KPiAqZW5jb2RlciwNCj4gDQo+ICAJaW50ZWxfZWRwX2JhY2tsaWdodF9vbihj
cnRjX3N0YXRlLCBjb25uX3N0YXRlKTsNCj4gIAlpbnRlbF9wc3JfZW5hYmxlKGludGVsX2RwLCBj
cnRjX3N0YXRlKTsNCj4gLQlpbnRlbF9kcF92c2NfZW5hYmxlKGludGVsX2RwLCBjcnRjX3N0YXRl
LCBjb25uX3N0YXRlKTsNCj4gLQlpbnRlbF9kcF9oZHJfbWV0YWRhdGFfZW5hYmxlKGludGVsX2Rw
LCBjcnRjX3N0YXRlLCBjb25uX3N0YXRlKTsNCj4gKwlpbnRlbF9kcF9zZXRfaW5mb2ZyYW1lcyhl
bmNvZGVyLCB0cnVlLCBjcnRjX3N0YXRlLCBjb25uX3N0YXRlKTsNCj4gIAlpbnRlbF9lZHBfZHJy
c19lbmFibGUoaW50ZWxfZHAsIGNydGNfc3RhdGUpOw0KPiANCj4gIAlpZiAoY3J0Y19zdGF0ZS0+
aGFzX2F1ZGlvKQ0KPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9p
bnRlbF9kcC5jDQo+IGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9kcC5jDQo+
IGluZGV4IGQ0ZWNlMGE4MjRjMC4uY2ZmYjc3ZGFlYzk2IDEwMDY0NA0KPiAtLS0gYS9kcml2ZXJz
L2dwdS9kcm0vaTkxNS9kaXNwbGF5L2ludGVsX2RwLmMNCj4gKysrIGIvZHJpdmVycy9ncHUvZHJt
L2k5MTUvZGlzcGxheS9pbnRlbF9kcC5jDQo+IEBAIC01MDk1LDIzMiArNTA5NSw2IEBAIHZvaWQg
aW50ZWxfcmVhZF9kcF9zZHAoc3RydWN0IGludGVsX2VuY29kZXIgKmVuY29kZXIsDQo+ICAJfQ0K
PiAgfQ0KPiANCj4gLXN0YXRpYyB2b2lkDQo+IC1pbnRlbF9kcF9zZXR1cF92c2Nfc2RwKHN0cnVj
dCBpbnRlbF9kcCAqaW50ZWxfZHAsDQo+IC0JCSAgICAgICBjb25zdCBzdHJ1Y3QgaW50ZWxfY3J0
Y19zdGF0ZSAqY3J0Y19zdGF0ZSwNCj4gLQkJICAgICAgIGNvbnN0IHN0cnVjdCBkcm1fY29ubmVj
dG9yX3N0YXRlICpjb25uX3N0YXRlKQ0KPiAtew0KPiAtCXN0cnVjdCBpbnRlbF9kaWdpdGFsX3Bv
cnQgKmludGVsX2RpZ19wb3J0ID0gZHBfdG9fZGlnX3BvcnQoaW50ZWxfZHApOw0KPiAtCXN0cnVj
dCBkcF9zZHAgdnNjX3NkcCA9IHt9Ow0KPiAtDQo+IC0JLyogUHJlcGFyZSBWU0MgSGVhZGVyIGZv
ciBTVSBhcyBwZXIgRFAgMS40YSBzcGVjLCBUYWJsZSAyLTExOSAqLw0KPiAtCXZzY19zZHAuc2Rw
X2hlYWRlci5IQjAgPSAwOw0KPiAtCXZzY19zZHAuc2RwX2hlYWRlci5IQjEgPSAweDc7DQo+IC0N
Cj4gLQkvKg0KPiAtCSAqIFZTQyBTRFAgc3VwcG9ydGluZyAzRCBzdGVyZW8sIFBTUjIsIGFuZCBQ
aXhlbCBFbmNvZGluZy8NCj4gLQkgKiBDb2xvcmltZXRyeSBGb3JtYXQgaW5kaWNhdGlvbi4NCj4g
LQkgKi8NCj4gLQl2c2Nfc2RwLnNkcF9oZWFkZXIuSEIyID0gMHg1Ow0KPiAtDQo+IC0JLyoNCj4g
LQkgKiBWU0MgU0RQIHN1cHBvcnRpbmcgM0Qgc3RlcmVvLCArIFBTUjIsICsgUGl4ZWwgRW5jb2Rp
bmcvDQo+IC0JICogQ29sb3JpbWV0cnkgRm9ybWF0IGluZGljYXRpb24gKEhCMiA9IDA1aCkuDQo+
IC0JICovDQo+IC0JdnNjX3NkcC5zZHBfaGVhZGVyLkhCMyA9IDB4MTM7DQo+IC0NCj4gLQkvKiBE
UCAxLjRhIHNwZWMsIFRhYmxlIDItMTIwICovDQo+IC0Jc3dpdGNoIChjcnRjX3N0YXRlLT5vdXRw
dXRfZm9ybWF0KSB7DQo+IC0JY2FzZSBJTlRFTF9PVVRQVVRfRk9STUFUX1lDQkNSNDQ0Og0KPiAt
CQl2c2Nfc2RwLmRiWzE2XSA9IDB4MSA8PCA0OyAvKiBZQ2JDciA0NDQgOiBEQjE2Wzc6NF0gPSAx
aCAqLw0KPiAtCQlicmVhazsNCj4gLQljYXNlIElOVEVMX09VVFBVVF9GT1JNQVRfWUNCQ1I0MjA6
DQo+IC0JCXZzY19zZHAuZGJbMTZdID0gMHgzIDw8IDQ7IC8qIFlDYkNyIDQyMCA6IERCMTZbNzo0
XSA9IDNoICovDQo+IC0JCWJyZWFrOw0KPiAtCWNhc2UgSU5URUxfT1VUUFVUX0ZPUk1BVF9SR0I6
DQo+IC0JZGVmYXVsdDoNCj4gLQkJLyogUkdCOiBEQjE2Wzc6NF0gPSAwaCAqLw0KPiAtCQlicmVh
azsNCj4gLQl9DQo+IC0NCj4gLQlzd2l0Y2ggKGNvbm5fc3RhdGUtPmNvbG9yc3BhY2UpIHsNCj4g
LQljYXNlIERSTV9NT0RFX0NPTE9SSU1FVFJZX0JUNzA5X1lDQzoNCj4gLQkJdnNjX3NkcC5kYlsx
Nl0gfD0gMHgxOw0KPiAtCQlicmVhazsNCj4gLQljYXNlIERSTV9NT0RFX0NPTE9SSU1FVFJZX1hW
WUNDXzYwMToNCj4gLQkJdnNjX3NkcC5kYlsxNl0gfD0gMHgyOw0KPiAtCQlicmVhazsNCj4gLQlj
YXNlIERSTV9NT0RFX0NPTE9SSU1FVFJZX1hWWUNDXzcwOToNCj4gLQkJdnNjX3NkcC5kYlsxNl0g
fD0gMHgzOw0KPiAtCQlicmVhazsNCj4gLQljYXNlIERSTV9NT0RFX0NPTE9SSU1FVFJZX1NZQ0Nf
NjAxOg0KPiAtCQl2c2Nfc2RwLmRiWzE2XSB8PSAweDQ7DQo+IC0JCWJyZWFrOw0KPiAtCWNhc2Ug
RFJNX01PREVfQ09MT1JJTUVUUllfT1BZQ0NfNjAxOg0KPiAtCQl2c2Nfc2RwLmRiWzE2XSB8PSAw
eDU7DQo+IC0JCWJyZWFrOw0KPiAtCWNhc2UgRFJNX01PREVfQ09MT1JJTUVUUllfQlQyMDIwX0NZ
Q0M6DQo+IC0JY2FzZSBEUk1fTU9ERV9DT0xPUklNRVRSWV9CVDIwMjBfUkdCOg0KPiAtCQl2c2Nf
c2RwLmRiWzE2XSB8PSAweDY7DQo+IC0JCWJyZWFrOw0KPiAtCWNhc2UgRFJNX01PREVfQ09MT1JJ
TUVUUllfQlQyMDIwX1lDQzoNCj4gLQkJdnNjX3NkcC5kYlsxNl0gfD0gMHg3Ow0KPiAtCQlicmVh
azsNCj4gLQljYXNlIERSTV9NT0RFX0NPTE9SSU1FVFJZX0RDSV9QM19SR0JfRDY1Og0KPiAtCWNh
c2UgRFJNX01PREVfQ09MT1JJTUVUUllfRENJX1AzX1JHQl9USEVBVEVSOg0KPiAtCQl2c2Nfc2Rw
LmRiWzE2XSB8PSAweDQ7IC8qIERDSS1QMyAoU01QVEUgUlAgNDMxLTIpICovDQo+IC0JCWJyZWFr
Ow0KPiAtCWRlZmF1bHQ6DQo+IC0JCS8qIHNSR0IgKElFQyA2MTk2Ni0yLTEpIC8gSVRVLVIgQlQu
NjAxOiBEQjE2WzA6M10gPSAwaCAqLw0KPiAtDQo+IC0JCS8qIFJHQi0+WUNCQ1IgY29sb3IgY29u
dmVyc2lvbiB1c2VzIHRoZSBCVC43MDkgY29sb3Igc3BhY2UuICovDQo+IC0JCWlmIChjcnRjX3N0
YXRlLT5vdXRwdXRfZm9ybWF0ID09DQo+IElOVEVMX09VVFBVVF9GT1JNQVRfWUNCQ1I0MjApDQo+
IC0JCQl2c2Nfc2RwLmRiWzE2XSB8PSAweDE7IC8qIDB4MSwgSVRVLVIgQlQuNzA5ICovDQo+IC0J
CWJyZWFrOw0KPiAtCX0NCj4gLQ0KPiAtCS8qDQo+IC0JICogRm9yIHBpeGVsIGVuY29kaW5nIGZv
cm1hdHMgWUNiQ3I0NDQsIFlDYkNyNDIyLCBZQ2JDcjQyMCwgYW5kIFkgT25seSwNCj4gLQkgKiB0
aGUgZm9sbG93aW5nIENvbXBvbmVudCBCaXQgRGVwdGggdmFsdWVzIGFyZSBkZWZpbmVkOg0KPiAt
CSAqIDAwMWIgPSA4YnBjLg0KPiAtCSAqIDAxMGIgPSAxMGJwYy4NCj4gLQkgKiAwMTFiID0gMTJi
cGMuDQo+IC0JICogMTAwYiA9IDE2YnBjLg0KPiAtCSAqLw0KPiAtCXN3aXRjaCAoY3J0Y19zdGF0
ZS0+cGlwZV9icHApIHsNCj4gLQljYXNlIDI0OiAvKiA4YnBjICovDQo+IC0JCXZzY19zZHAuZGJb
MTddID0gMHgxOw0KPiAtCQlicmVhazsNCj4gLQljYXNlIDMwOiAvKiAxMGJwYyAqLw0KPiAtCQl2
c2Nfc2RwLmRiWzE3XSA9IDB4MjsNCj4gLQkJYnJlYWs7DQo+IC0JY2FzZSAzNjogLyogMTJicGMg
Ki8NCj4gLQkJdnNjX3NkcC5kYlsxN10gPSAweDM7DQo+IC0JCWJyZWFrOw0KPiAtCWNhc2UgNDg6
IC8qIDE2YnBjICovDQo+IC0JCXZzY19zZHAuZGJbMTddID0gMHg0Ow0KPiAtCQlicmVhazsNCj4g
LQlkZWZhdWx0Og0KPiAtCQlNSVNTSU5HX0NBU0UoY3J0Y19zdGF0ZS0+cGlwZV9icHApOw0KPiAt
CQlicmVhazsNCj4gLQl9DQo+IC0NCj4gLQkvKg0KPiAtCSAqIER5bmFtaWMgUmFuZ2UgKEJpdCA3
KQ0KPiAtCSAqIDAgPSBWRVNBIHJhbmdlLCAxID0gQ1RBIHJhbmdlLg0KPiAtCSAqIGFsbCBZQ2JD
ciBhcmUgYWx3YXlzIGxpbWl0ZWQgcmFuZ2UNCj4gLQkgKi8NCj4gLQl2c2Nfc2RwLmRiWzE3XSB8
PSAweDgwOw0KPiAtDQo+IC0JLyoNCj4gLQkgKiBDb250ZW50IFR5cGUgKEJpdHMgMjowKQ0KPiAt
CSAqIDAwMGIgPSBOb3QgZGVmaW5lZC4NCj4gLQkgKiAwMDFiID0gR3JhcGhpY3MuDQo+IC0JICog
MDEwYiA9IFBob3RvLg0KPiAtCSAqIDAxMWIgPSBWaWRlby4NCj4gLQkgKiAxMDBiID0gR2FtZQ0K
PiAtCSAqIEFsbCBvdGhlciB2YWx1ZXMgYXJlIFJFU0VSVkVELg0KPiAtCSAqIE5vdGU6IFNlZSBD
VEEtODYxLUcgZm9yIHRoZSBkZWZpbml0aW9uIGFuZCBleHBlY3RlZA0KPiAtCSAqIHByb2Nlc3Np
bmcgYnkgYSBzdHJlYW0gc2luayBmb3IgdGhlIGFib3ZlIGNvbnRlY3QgdHlwZXMuDQo+IC0JICov
DQo+IC0JdnNjX3NkcC5kYlsxOF0gPSAwOw0KPiAtDQo+IC0JaW50ZWxfZGlnX3BvcnQtPndyaXRl
X2luZm9mcmFtZSgmaW50ZWxfZGlnX3BvcnQtPmJhc2UsDQo+IC0JCQljcnRjX3N0YXRlLCBEUF9T
RFBfVlNDLCAmdnNjX3NkcCwgc2l6ZW9mKHZzY19zZHApKTsNCj4gLX0NCj4gLQ0KPiAtc3RhdGlj
IHZvaWQNCj4gLWludGVsX2RwX3NldHVwX2hkcl9tZXRhZGF0YV9pbmZvZnJhbWVfc2RwKHN0cnVj
dCBpbnRlbF9kcCAqaW50ZWxfZHAsDQo+IC0JCQkJCSAgY29uc3Qgc3RydWN0IGludGVsX2NydGNf
c3RhdGUgKmNydGNfc3RhdGUsDQo+IC0JCQkJCSAgY29uc3Qgc3RydWN0IGRybV9jb25uZWN0b3Jf
c3RhdGUNCj4gKmNvbm5fc3RhdGUpDQo+IC17DQo+IC0Jc3RydWN0IGludGVsX2RpZ2l0YWxfcG9y
dCAqaW50ZWxfZGlnX3BvcnQgPSBkcF90b19kaWdfcG9ydChpbnRlbF9kcCk7DQo+IC0Jc3RydWN0
IGRwX3NkcCBpbmZvZnJhbWVfc2RwID0ge307DQo+IC0Jc3RydWN0IGhkbWlfZHJtX2luZm9mcmFt
ZSBkcm1faW5mb2ZyYW1lID0ge307DQo+IC0JY29uc3QgaW50IGluZm9mcmFtZV9zaXplID0gSERN
SV9JTkZPRlJBTUVfSEVBREVSX1NJWkUgKw0KPiBIRE1JX0RSTV9JTkZPRlJBTUVfU0laRTsNCj4g
LQl1bnNpZ25lZCBjaGFyIGJ1ZltIRE1JX0lORk9GUkFNRV9IRUFERVJfU0laRSArDQo+IEhETUlf
RFJNX0lORk9GUkFNRV9TSVpFXTsNCj4gLQlzc2l6ZV90IGxlbjsNCj4gLQlpbnQgcmV0Ow0KPiAt
DQo+IC0JcmV0ID0gZHJtX2hkbWlfaW5mb2ZyYW1lX3NldF9oZHJfbWV0YWRhdGEoJmRybV9pbmZv
ZnJhbWUsDQo+IGNvbm5fc3RhdGUpOw0KPiAtCWlmIChyZXQpIHsNCj4gLQkJRFJNX0RFQlVHX0tN
UygiY291bGRuJ3Qgc2V0IEhEUiBtZXRhZGF0YSBpbiBpbmZvZnJhbWVcbiIpOw0KPiAtCQlyZXR1
cm47DQo+IC0JfQ0KPiAtDQo+IC0JbGVuID0gaGRtaV9kcm1faW5mb2ZyYW1lX3BhY2tfb25seSgm
ZHJtX2luZm9mcmFtZSwgYnVmLCBzaXplb2YoYnVmKSk7DQo+IC0JaWYgKGxlbiA8IDApIHsNCj4g
LQkJRFJNX0RFQlVHX0tNUygiYnVmZmVyIHNpemUgaXMgc21hbGxlciB0aGFuIGhkciBtZXRhZGF0
YQ0KPiBpbmZvZnJhbWVcbiIpOw0KPiAtCQlyZXR1cm47DQo+IC0JfQ0KPiAtDQo+IC0JaWYgKGxl
biAhPSBpbmZvZnJhbWVfc2l6ZSkgew0KPiAtCQlEUk1fREVCVUdfS01TKCJ3cm9uZyBzdGF0aWMg
aGRyIG1ldGFkYXRhIHNpemVcbiIpOw0KPiAtCQlyZXR1cm47DQo+IC0JfQ0KPiAtDQo+IC0JLyoN
Cj4gLQkgKiBTZXQgdXAgdGhlIGluZm9mcmFtZSBzZHAgcGFja2V0IGZvciBIRFIgc3RhdGljIG1l
dGFkYXRhLg0KPiAtCSAqIFByZXBhcmUgVlNDIEhlYWRlciBmb3IgU1UgYXMgcGVyIERQIDEuNGEg
c3BlYywNCj4gLQkgKiBUYWJsZSAyLTEwMCBhbmQgVGFibGUgMi0xMDENCj4gLQkgKi8NCj4gLQ0K
PiAtCS8qIFBhY2tldCBJRCwgMDBoIGZvciBub24tQXVkaW8gSU5GT0ZSQU1FICovDQo+IC0JaW5m
b2ZyYW1lX3NkcC5zZHBfaGVhZGVyLkhCMCA9IDA7DQo+IC0JLyoNCj4gLQkgKiBQYWNrZXQgVHlw
ZSA4MGggKyBOb24tYXVkaW8gSU5GT0ZSQU1FIFR5cGUgdmFsdWUNCj4gLQkgKiBIRE1JX0lORk9G
UkFNRV9UWVBFX0RSTTogMHg4NywNCj4gLQkgKi8NCj4gLQlpbmZvZnJhbWVfc2RwLnNkcF9oZWFk
ZXIuSEIxID0gZHJtX2luZm9mcmFtZS50eXBlOw0KPiAtCS8qDQo+IC0JICogTGVhc3QgU2lnbmlm
aWNhbnQgRWlnaHQgQml0cyBvZiAoRGF0YSBCeXRlIENvdW50IOKAkyAxKQ0KPiAtCSAqIGluZm9m
cmFtZV9zaXplIC0gMSwNCj4gLQkgKi8NCj4gLQlpbmZvZnJhbWVfc2RwLnNkcF9oZWFkZXIuSEIy
ID0gMHgxRDsNCj4gLQkvKiBJTkZPRlJBTUUgU0RQIFZlcnNpb24gTnVtYmVyICovDQo+IC0JaW5m
b2ZyYW1lX3NkcC5zZHBfaGVhZGVyLkhCMyA9ICgweDEzIDw8IDIpOw0KPiAtCS8qIENUQSBIZWFk
ZXIgQnl0ZSAyIChJTkZPRlJBTUUgVmVyc2lvbiBOdW1iZXIpICovDQo+IC0JaW5mb2ZyYW1lX3Nk
cC5kYlswXSA9IGRybV9pbmZvZnJhbWUudmVyc2lvbjsNCj4gLQkvKiBDVEEgSGVhZGVyIEJ5dGUg
MyAoTGVuZ3RoIG9mIElORk9GUkFNRSk6DQo+IEhETUlfRFJNX0lORk9GUkFNRV9TSVpFICovDQo+
IC0JaW5mb2ZyYW1lX3NkcC5kYlsxXSA9IGRybV9pbmZvZnJhbWUubGVuZ3RoOw0KPiAtCS8qDQo+
IC0JICogQ29weSBIRE1JX0RSTV9JTkZPRlJBTUVfU0laRSBzaXplIGZyb20gYSBidWZmZXIgYWZ0
ZXINCj4gLQkgKiBIRE1JX0lORk9GUkFNRV9IRUFERVJfU0laRQ0KPiAtCSAqLw0KPiAtCUJVSUxE
X0JVR19PTihzaXplb2YoaW5mb2ZyYW1lX3NkcC5kYikgPCBIRE1JX0RSTV9JTkZPRlJBTUVfU0la
RQ0KPiArIDIpOw0KPiAtCW1lbWNweSgmaW5mb2ZyYW1lX3NkcC5kYlsyXSwgJmJ1ZltIRE1JX0lO
Rk9GUkFNRV9IRUFERVJfU0laRV0sDQo+IC0JICAgICAgIEhETUlfRFJNX0lORk9GUkFNRV9TSVpF
KTsNCj4gLQ0KPiAtCS8qDQo+IC0JICogU2l6ZSBvZiBEUCBpbmZvZnJhbWUgc2RwIHBhY2tldCBm
b3IgSERSIHN0YXRpYyBtZXRhZGF0YSBpcyBjb25zaXN0IG9mDQo+IC0JICogLSBEUCBTRFAgSGVh
ZGVyKHN0cnVjdCBkcF9zZHBfaGVhZGVyKTogNCBieXRlcw0KPiAtCSAqIC0gVHdvIERhdGEgQmxv
Y2tzOiAyIGJ5dGVzDQo+IC0JICogICAgQ1RBIEhlYWRlciBCeXRlMiAoSU5GT0ZSQU1FIFZlcnNp
b24gTnVtYmVyKQ0KPiAtCSAqICAgIENUQSBIZWFkZXIgQnl0ZTMgKExlbmd0aCBvZiBJTkZPRlJB
TUUpDQo+IC0JICogLSBIRE1JX0RSTV9JTkZPRlJBTUVfU0laRTogMjYgYnl0ZXMNCj4gLQkgKg0K
PiAtCSAqIFByaW9yIHRvIEdFTjExJ3MgR01QIHJlZ2lzdGVyIHNpemUgaXMgaWRlbnRpY2FsIHRv
IERQIEhEUiBzdGF0aWMgbWV0YWRhdGENCj4gLQkgKiBpbmZvZnJhbWUgc2l6ZS4gQnV0IEdFTjEx
KyBoYXMgbGFyZ2VyIHRoYW4gdGhhdCBzaXplLCB3cml0ZV9pbmZvZnJhbWUNCj4gLQkgKiB3aWxs
IHBhZCByZXN0IG9mIHRoZSBzaXplLg0KPiAtCSAqLw0KPiAtCWludGVsX2RpZ19wb3J0LT53cml0
ZV9pbmZvZnJhbWUoJmludGVsX2RpZ19wb3J0LT5iYXNlLCBjcnRjX3N0YXRlLA0KPiAtCQkJCQlI
RE1JX1BBQ0tFVF9UWVBFX0dBTVVUX01FVEFEQVRBLA0KPiAtCQkJCQkmaW5mb2ZyYW1lX3NkcCwN
Cj4gLQkJCQkJc2l6ZW9mKHN0cnVjdCBkcF9zZHBfaGVhZGVyKSArIDIgKw0KPiBIRE1JX0RSTV9J
TkZPRlJBTUVfU0laRSk7DQo+IC19DQo+IC0NCj4gLXZvaWQgaW50ZWxfZHBfdnNjX2VuYWJsZShz
dHJ1Y3QgaW50ZWxfZHAgKmludGVsX2RwLA0KPiAtCQkJIGNvbnN0IHN0cnVjdCBpbnRlbF9jcnRj
X3N0YXRlICpjcnRjX3N0YXRlLA0KPiAtCQkJIGNvbnN0IHN0cnVjdCBkcm1fY29ubmVjdG9yX3N0
YXRlICpjb25uX3N0YXRlKQ0KPiAtew0KPiAtCWlmICghaW50ZWxfZHBfbmVlZHNfdnNjX3NkcChj
cnRjX3N0YXRlLCBjb25uX3N0YXRlKSkNCj4gLQkJcmV0dXJuOw0KPiAtDQo+IC0JaW50ZWxfZHBf
c2V0dXBfdnNjX3NkcChpbnRlbF9kcCwgY3J0Y19zdGF0ZSwgY29ubl9zdGF0ZSk7DQo+IC19DQo+
IC0NCj4gLXZvaWQgaW50ZWxfZHBfaGRyX21ldGFkYXRhX2VuYWJsZShzdHJ1Y3QgaW50ZWxfZHAg
KmludGVsX2RwLA0KPiAtCQkJCSAgY29uc3Qgc3RydWN0IGludGVsX2NydGNfc3RhdGUgKmNydGNf
c3RhdGUsDQo+IC0JCQkJICBjb25zdCBzdHJ1Y3QgZHJtX2Nvbm5lY3Rvcl9zdGF0ZSAqY29ubl9z
dGF0ZSkNCj4gLXsNCj4gLQlpZiAoIWNvbm5fc3RhdGUtPmhkcl9vdXRwdXRfbWV0YWRhdGEpDQo+
IC0JCXJldHVybjsNCj4gLQ0KPiAtCWludGVsX2RwX3NldHVwX2hkcl9tZXRhZGF0YV9pbmZvZnJh
bWVfc2RwKGludGVsX2RwLA0KPiAtCQkJCQkJICBjcnRjX3N0YXRlLA0KPiAtCQkJCQkJICBjb25u
X3N0YXRlKTsNCj4gLX0NCj4gLQ0KPiAgc3RhdGljIHU4IGludGVsX2RwX2F1dG90ZXN0X2xpbmtf
dHJhaW5pbmcoc3RydWN0IGludGVsX2RwICppbnRlbF9kcCkgIHsNCj4gIAlpbnQgc3RhdHVzID0g
MDsNCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2Rpc3BsYXkvaW50ZWxfZHAu
aA0KPiBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2Rpc3BsYXkvaW50ZWxfZHAuaA0KPiBpbmRleCBl
OGY5YmE5NjJkMDkuLjY1NjJiYjhlZGViYSAxMDA2NDQNCj4gLS0tIGEvZHJpdmVycy9ncHUvZHJt
L2k5MTUvZGlzcGxheS9pbnRlbF9kcC5oDQo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2Rp
c3BsYXkvaW50ZWxfZHAuaA0KPiBAQCAtMTEwLDEyICsxMTAsNiBAQCBpbnQgaW50ZWxfZHBfbGlu
a19yZXF1aXJlZChpbnQgcGl4ZWxfY2xvY2ssIGludCBicHApOyAgaW50DQo+IGludGVsX2RwX21h
eF9kYXRhX3JhdGUoaW50IG1heF9saW5rX2Nsb2NrLCBpbnQgbWF4X2xhbmVzKTsgIGJvb2wNCj4g
aW50ZWxfZHBfbmVlZHNfdnNjX3NkcChjb25zdCBzdHJ1Y3QgaW50ZWxfY3J0Y19zdGF0ZSAqY3J0
Y19zdGF0ZSwNCj4gIAkJCSAgICBjb25zdCBzdHJ1Y3QgZHJtX2Nvbm5lY3Rvcl9zdGF0ZSAqY29u
bl9zdGF0ZSk7IC12b2lkDQo+IGludGVsX2RwX3ZzY19lbmFibGUoc3RydWN0IGludGVsX2RwICpp
bnRlbF9kcCwNCj4gLQkJCSBjb25zdCBzdHJ1Y3QgaW50ZWxfY3J0Y19zdGF0ZSAqY3J0Y19zdGF0
ZSwNCj4gLQkJCSBjb25zdCBzdHJ1Y3QgZHJtX2Nvbm5lY3Rvcl9zdGF0ZSAqY29ubl9zdGF0ZSk7
DQo+IC12b2lkIGludGVsX2RwX2hkcl9tZXRhZGF0YV9lbmFibGUoc3RydWN0IGludGVsX2RwICpp
bnRlbF9kcCwNCj4gLQkJCQkgIGNvbnN0IHN0cnVjdCBpbnRlbF9jcnRjX3N0YXRlICpjcnRjX3N0
YXRlLA0KPiAtCQkJCSAgY29uc3Qgc3RydWN0IGRybV9jb25uZWN0b3Jfc3RhdGUgKmNvbm5fc3Rh
dGUpOw0KPiAgdm9pZCBpbnRlbF9kcF9zZXRfaW5mb2ZyYW1lcyhzdHJ1Y3QgaW50ZWxfZW5jb2Rl
ciAqZW5jb2RlciwgYm9vbCBlbmFibGUsDQo+ICAJCQkgICAgIGNvbnN0IHN0cnVjdCBpbnRlbF9j
cnRjX3N0YXRlICpjcnRjX3N0YXRlLA0KPiAgCQkJICAgICBjb25zdCBzdHJ1Y3QgZHJtX2Nvbm5l
Y3Rvcl9zdGF0ZSAqY29ubl9zdGF0ZSk7DQo+IC0tDQo+IDIuMjQuMQ0KPiANCj4gX19fX19fX19f
X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18NCj4gSW50ZWwtZ2Z4IG1haWxp
bmcgbGlzdA0KPiBJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnDQo+IGh0dHBzOi8vbGlz
dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4DQo

RE: [Intel-gfx] [PATCH v3 11/17] drm/i915: Program DP SDPs with computed configs

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 11/17] drm/i915: Program DP SDPs with computed
> configs
> 
> In order to use computed config for DP SDPs (DP VSC SDP and DP HDR Metadata
> Infoframe SDP), it replaces intel_dp_vsc_enable() function and
> intel_dp_hdr_metadata_enable() function to intel_dp_set_infoframes() function.
> 
> Before applying it, routines of program SDP always calculated configs when they
> called. And it removes unused functions.

Fix the sentence, seems unclear.
With that fixed,
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> 
> v3: Rebased
> 
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c |   3 +-
>  drivers/gpu/drm/i915/display/intel_dp.c  | 226 -----------------------
>  drivers/gpu/drm/i915/display/intel_dp.h  |   6 -
>  3 files changed, 1 insertion(+), 234 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index c96f629cddc3..374ab6a3757c 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3900,8 +3900,7 @@ static void intel_enable_ddi_dp(struct intel_encoder
> *encoder,
> 
>  	intel_edp_backlight_on(crtc_state, conn_state);
>  	intel_psr_enable(intel_dp, crtc_state);
> -	intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
> -	intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
> +	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
>  	intel_edp_drrs_enable(intel_dp, crtc_state);
> 
>  	if (crtc_state->has_audio)
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index d4ece0a824c0..cffb77daec96 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5095,232 +5095,6 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
>  	}
>  }
> 
> -static void
> -intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
> -		       const struct intel_crtc_state *crtc_state,
> -		       const struct drm_connector_state *conn_state)
> -{
> -	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> -	struct dp_sdp vsc_sdp = {};
> -
> -	/* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
> -	vsc_sdp.sdp_header.HB0 = 0;
> -	vsc_sdp.sdp_header.HB1 = 0x7;
> -
> -	/*
> -	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> -	 * Colorimetry Format indication.
> -	 */
> -	vsc_sdp.sdp_header.HB2 = 0x5;
> -
> -	/*
> -	 * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
> -	 * Colorimetry Format indication (HB2 = 05h).
> -	 */
> -	vsc_sdp.sdp_header.HB3 = 0x13;
> -
> -	/* DP 1.4a spec, Table 2-120 */
> -	switch (crtc_state->output_format) {
> -	case INTEL_OUTPUT_FORMAT_YCBCR444:
> -		vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */
> -		break;
> -	case INTEL_OUTPUT_FORMAT_YCBCR420:
> -		vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */
> -		break;
> -	case INTEL_OUTPUT_FORMAT_RGB:
> -	default:
> -		/* RGB: DB16[7:4] = 0h */
> -		break;
> -	}
> -
> -	switch (conn_state->colorspace) {
> -	case DRM_MODE_COLORIMETRY_BT709_YCC:
> -		vsc_sdp.db[16] |= 0x1;
> -		break;
> -	case DRM_MODE_COLORIMETRY_XVYCC_601:
> -		vsc_sdp.db[16] |= 0x2;
> -		break;
> -	case DRM_MODE_COLORIMETRY_XVYCC_709:
> -		vsc_sdp.db[16] |= 0x3;
> -		break;
> -	case DRM_MODE_COLORIMETRY_SYCC_601:
> -		vsc_sdp.db[16] |= 0x4;
> -		break;
> -	case DRM_MODE_COLORIMETRY_OPYCC_601:
> -		vsc_sdp.db[16] |= 0x5;
> -		break;
> -	case DRM_MODE_COLORIMETRY_BT2020_CYCC:
> -	case DRM_MODE_COLORIMETRY_BT2020_RGB:
> -		vsc_sdp.db[16] |= 0x6;
> -		break;
> -	case DRM_MODE_COLORIMETRY_BT2020_YCC:
> -		vsc_sdp.db[16] |= 0x7;
> -		break;
> -	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
> -	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
> -		vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */
> -		break;
> -	default:
> -		/* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */
> -
> -		/* RGB->YCBCR color conversion uses the BT.709 color space. */
> -		if (crtc_state->output_format ==
> INTEL_OUTPUT_FORMAT_YCBCR420)
> -			vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
> -		break;
> -	}
> -
> -	/*
> -	 * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
> -	 * the following Component Bit Depth values are defined:
> -	 * 001b = 8bpc.
> -	 * 010b = 10bpc.
> -	 * 011b = 12bpc.
> -	 * 100b = 16bpc.
> -	 */
> -	switch (crtc_state->pipe_bpp) {
> -	case 24: /* 8bpc */
> -		vsc_sdp.db[17] = 0x1;
> -		break;
> -	case 30: /* 10bpc */
> -		vsc_sdp.db[17] = 0x2;
> -		break;
> -	case 36: /* 12bpc */
> -		vsc_sdp.db[17] = 0x3;
> -		break;
> -	case 48: /* 16bpc */
> -		vsc_sdp.db[17] = 0x4;
> -		break;
> -	default:
> -		MISSING_CASE(crtc_state->pipe_bpp);
> -		break;
> -	}
> -
> -	/*
> -	 * Dynamic Range (Bit 7)
> -	 * 0 = VESA range, 1 = CTA range.
> -	 * all YCbCr are always limited range
> -	 */
> -	vsc_sdp.db[17] |= 0x80;
> -
> -	/*
> -	 * Content Type (Bits 2:0)
> -	 * 000b = Not defined.
> -	 * 001b = Graphics.
> -	 * 010b = Photo.
> -	 * 011b = Video.
> -	 * 100b = Game
> -	 * All other values are RESERVED.
> -	 * Note: See CTA-861-G for the definition and expected
> -	 * processing by a stream sink for the above contect types.
> -	 */
> -	vsc_sdp.db[18] = 0;
> -
> -	intel_dig_port->write_infoframe(&intel_dig_port->base,
> -			crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
> -}
> -
> -static void
> -intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
> -					  const struct intel_crtc_state *crtc_state,
> -					  const struct drm_connector_state
> *conn_state)
> -{
> -	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> -	struct dp_sdp infoframe_sdp = {};
> -	struct hdmi_drm_infoframe drm_infoframe = {};
> -	const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE +
> HDMI_DRM_INFOFRAME_SIZE;
> -	unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE +
> HDMI_DRM_INFOFRAME_SIZE];
> -	ssize_t len;
> -	int ret;
> -
> -	ret = drm_hdmi_infoframe_set_hdr_metadata(&drm_infoframe,
> conn_state);
> -	if (ret) {
> -		DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
> -		return;
> -	}
> -
> -	len = hdmi_drm_infoframe_pack_only(&drm_infoframe, buf, sizeof(buf));
> -	if (len < 0) {
> -		DRM_DEBUG_KMS("buffer size is smaller than hdr metadata
> infoframe\n");
> -		return;
> -	}
> -
> -	if (len != infoframe_size) {
> -		DRM_DEBUG_KMS("wrong static hdr metadata size\n");
> -		return;
> -	}
> -
> -	/*
> -	 * Set up the infoframe sdp packet for HDR static metadata.
> -	 * Prepare VSC Header for SU as per DP 1.4a spec,
> -	 * Table 2-100 and Table 2-101
> -	 */
> -
> -	/* Packet ID, 00h for non-Audio INFOFRAME */
> -	infoframe_sdp.sdp_header.HB0 = 0;
> -	/*
> -	 * Packet Type 80h + Non-audio INFOFRAME Type value
> -	 * HDMI_INFOFRAME_TYPE_DRM: 0x87,
> -	 */
> -	infoframe_sdp.sdp_header.HB1 = drm_infoframe.type;
> -	/*
> -	 * Least Significant Eight Bits of (Data Byte Count – 1)
> -	 * infoframe_size - 1,
> -	 */
> -	infoframe_sdp.sdp_header.HB2 = 0x1D;
> -	/* INFOFRAME SDP Version Number */
> -	infoframe_sdp.sdp_header.HB3 = (0x13 << 2);
> -	/* CTA Header Byte 2 (INFOFRAME Version Number) */
> -	infoframe_sdp.db[0] = drm_infoframe.version;
> -	/* CTA Header Byte 3 (Length of INFOFRAME):
> HDMI_DRM_INFOFRAME_SIZE */
> -	infoframe_sdp.db[1] = drm_infoframe.length;
> -	/*
> -	 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
> -	 * HDMI_INFOFRAME_HEADER_SIZE
> -	 */
> -	BUILD_BUG_ON(sizeof(infoframe_sdp.db) < HDMI_DRM_INFOFRAME_SIZE
> + 2);
> -	memcpy(&infoframe_sdp.db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
> -	       HDMI_DRM_INFOFRAME_SIZE);
> -
> -	/*
> -	 * Size of DP infoframe sdp packet for HDR static metadata is consist of
> -	 * - DP SDP Header(struct dp_sdp_header): 4 bytes
> -	 * - Two Data Blocks: 2 bytes
> -	 *    CTA Header Byte2 (INFOFRAME Version Number)
> -	 *    CTA Header Byte3 (Length of INFOFRAME)
> -	 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
> -	 *
> -	 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
> -	 * infoframe size. But GEN11+ has larger than that size, write_infoframe
> -	 * will pad rest of the size.
> -	 */
> -	intel_dig_port->write_infoframe(&intel_dig_port->base, crtc_state,
> -					HDMI_PACKET_TYPE_GAMUT_METADATA,
> -					&infoframe_sdp,
> -					sizeof(struct dp_sdp_header) + 2 +
> HDMI_DRM_INFOFRAME_SIZE);
> -}
> -
> -void intel_dp_vsc_enable(struct intel_dp *intel_dp,
> -			 const struct intel_crtc_state *crtc_state,
> -			 const struct drm_connector_state *conn_state)
> -{
> -	if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
> -		return;
> -
> -	intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);
> -}
> -
> -void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
> -				  const struct intel_crtc_state *crtc_state,
> -				  const struct drm_connector_state *conn_state)
> -{
> -	if (!conn_state->hdr_output_metadata)
> -		return;
> -
> -	intel_dp_setup_hdr_metadata_infoframe_sdp(intel_dp,
> -						  crtc_state,
> -						  conn_state);
> -}
> -
>  static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)  {
>  	int status = 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index e8f9ba962d09..6562bb8edeba 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -110,12 +110,6 @@ int intel_dp_link_required(int pixel_clock, int bpp);  int
> intel_dp_max_data_rate(int max_link_clock, int max_lanes);  bool
> intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
>  			    const struct drm_connector_state *conn_state); -void
> intel_dp_vsc_enable(struct intel_dp *intel_dp,
> -			 const struct intel_crtc_state *crtc_state,
> -			 const struct drm_connector_state *conn_state);
> -void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
> -				  const struct intel_crtc_state *crtc_state,
> -				  const struct drm_connector_state *conn_state);
>  void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
>  			     const struct intel_crtc_state *crtc_state,
>  			     const struct drm_connector_state *conn_state);
> --
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Intel-gfx] [PATCH v3 11/17] drm/i915: Program DP SDPs with computed configs

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 11/17] drm/i915: Program DP SDPs with computed
> configs
> 
> In order to use computed config for DP SDPs (DP VSC SDP and DP HDR Metadata
> Infoframe SDP), it replaces intel_dp_vsc_enable() function and
> intel_dp_hdr_metadata_enable() function to intel_dp_set_infoframes() function.
> 
> Before applying it, routines of program SDP always calculated configs when they
> called. And it removes unused functions.

Fix the sentence, seems unclear.
With that fixed,
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> 
> v3: Rebased
> 
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c |   3 +-
>  drivers/gpu/drm/i915/display/intel_dp.c  | 226 -----------------------
>  drivers/gpu/drm/i915/display/intel_dp.h  |   6 -
>  3 files changed, 1 insertion(+), 234 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index c96f629cddc3..374ab6a3757c 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3900,8 +3900,7 @@ static void intel_enable_ddi_dp(struct intel_encoder
> *encoder,
> 
>  	intel_edp_backlight_on(crtc_state, conn_state);
>  	intel_psr_enable(intel_dp, crtc_state);
> -	intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
> -	intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
> +	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
>  	intel_edp_drrs_enable(intel_dp, crtc_state);
> 
>  	if (crtc_state->has_audio)
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index d4ece0a824c0..cffb77daec96 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5095,232 +5095,6 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
>  	}
>  }
> 
> -static void
> -intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
> -		       const struct intel_crtc_state *crtc_state,
> -		       const struct drm_connector_state *conn_state)
> -{
> -	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> -	struct dp_sdp vsc_sdp = {};
> -
> -	/* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
> -	vsc_sdp.sdp_header.HB0 = 0;
> -	vsc_sdp.sdp_header.HB1 = 0x7;
> -
> -	/*
> -	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> -	 * Colorimetry Format indication.
> -	 */
> -	vsc_sdp.sdp_header.HB2 = 0x5;
> -
> -	/*
> -	 * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
> -	 * Colorimetry Format indication (HB2 = 05h).
> -	 */
> -	vsc_sdp.sdp_header.HB3 = 0x13;
> -
> -	/* DP 1.4a spec, Table 2-120 */
> -	switch (crtc_state->output_format) {
> -	case INTEL_OUTPUT_FORMAT_YCBCR444:
> -		vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */
> -		break;
> -	case INTEL_OUTPUT_FORMAT_YCBCR420:
> -		vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */
> -		break;
> -	case INTEL_OUTPUT_FORMAT_RGB:
> -	default:
> -		/* RGB: DB16[7:4] = 0h */
> -		break;
> -	}
> -
> -	switch (conn_state->colorspace) {
> -	case DRM_MODE_COLORIMETRY_BT709_YCC:
> -		vsc_sdp.db[16] |= 0x1;
> -		break;
> -	case DRM_MODE_COLORIMETRY_XVYCC_601:
> -		vsc_sdp.db[16] |= 0x2;
> -		break;
> -	case DRM_MODE_COLORIMETRY_XVYCC_709:
> -		vsc_sdp.db[16] |= 0x3;
> -		break;
> -	case DRM_MODE_COLORIMETRY_SYCC_601:
> -		vsc_sdp.db[16] |= 0x4;
> -		break;
> -	case DRM_MODE_COLORIMETRY_OPYCC_601:
> -		vsc_sdp.db[16] |= 0x5;
> -		break;
> -	case DRM_MODE_COLORIMETRY_BT2020_CYCC:
> -	case DRM_MODE_COLORIMETRY_BT2020_RGB:
> -		vsc_sdp.db[16] |= 0x6;
> -		break;
> -	case DRM_MODE_COLORIMETRY_BT2020_YCC:
> -		vsc_sdp.db[16] |= 0x7;
> -		break;
> -	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
> -	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
> -		vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */
> -		break;
> -	default:
> -		/* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */
> -
> -		/* RGB->YCBCR color conversion uses the BT.709 color space. */
> -		if (crtc_state->output_format ==
> INTEL_OUTPUT_FORMAT_YCBCR420)
> -			vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
> -		break;
> -	}
> -
> -	/*
> -	 * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
> -	 * the following Component Bit Depth values are defined:
> -	 * 001b = 8bpc.
> -	 * 010b = 10bpc.
> -	 * 011b = 12bpc.
> -	 * 100b = 16bpc.
> -	 */
> -	switch (crtc_state->pipe_bpp) {
> -	case 24: /* 8bpc */
> -		vsc_sdp.db[17] = 0x1;
> -		break;
> -	case 30: /* 10bpc */
> -		vsc_sdp.db[17] = 0x2;
> -		break;
> -	case 36: /* 12bpc */
> -		vsc_sdp.db[17] = 0x3;
> -		break;
> -	case 48: /* 16bpc */
> -		vsc_sdp.db[17] = 0x4;
> -		break;
> -	default:
> -		MISSING_CASE(crtc_state->pipe_bpp);
> -		break;
> -	}
> -
> -	/*
> -	 * Dynamic Range (Bit 7)
> -	 * 0 = VESA range, 1 = CTA range.
> -	 * all YCbCr are always limited range
> -	 */
> -	vsc_sdp.db[17] |= 0x80;
> -
> -	/*
> -	 * Content Type (Bits 2:0)
> -	 * 000b = Not defined.
> -	 * 001b = Graphics.
> -	 * 010b = Photo.
> -	 * 011b = Video.
> -	 * 100b = Game
> -	 * All other values are RESERVED.
> -	 * Note: See CTA-861-G for the definition and expected
> -	 * processing by a stream sink for the above contect types.
> -	 */
> -	vsc_sdp.db[18] = 0;
> -
> -	intel_dig_port->write_infoframe(&intel_dig_port->base,
> -			crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
> -}
> -
> -static void
> -intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
> -					  const struct intel_crtc_state *crtc_state,
> -					  const struct drm_connector_state
> *conn_state)
> -{
> -	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> -	struct dp_sdp infoframe_sdp = {};
> -	struct hdmi_drm_infoframe drm_infoframe = {};
> -	const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE +
> HDMI_DRM_INFOFRAME_SIZE;
> -	unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE +
> HDMI_DRM_INFOFRAME_SIZE];
> -	ssize_t len;
> -	int ret;
> -
> -	ret = drm_hdmi_infoframe_set_hdr_metadata(&drm_infoframe,
> conn_state);
> -	if (ret) {
> -		DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
> -		return;
> -	}
> -
> -	len = hdmi_drm_infoframe_pack_only(&drm_infoframe, buf, sizeof(buf));
> -	if (len < 0) {
> -		DRM_DEBUG_KMS("buffer size is smaller than hdr metadata
> infoframe\n");
> -		return;
> -	}
> -
> -	if (len != infoframe_size) {
> -		DRM_DEBUG_KMS("wrong static hdr metadata size\n");
> -		return;
> -	}
> -
> -	/*
> -	 * Set up the infoframe sdp packet for HDR static metadata.
> -	 * Prepare VSC Header for SU as per DP 1.4a spec,
> -	 * Table 2-100 and Table 2-101
> -	 */
> -
> -	/* Packet ID, 00h for non-Audio INFOFRAME */
> -	infoframe_sdp.sdp_header.HB0 = 0;
> -	/*
> -	 * Packet Type 80h + Non-audio INFOFRAME Type value
> -	 * HDMI_INFOFRAME_TYPE_DRM: 0x87,
> -	 */
> -	infoframe_sdp.sdp_header.HB1 = drm_infoframe.type;
> -	/*
> -	 * Least Significant Eight Bits of (Data Byte Count – 1)
> -	 * infoframe_size - 1,
> -	 */
> -	infoframe_sdp.sdp_header.HB2 = 0x1D;
> -	/* INFOFRAME SDP Version Number */
> -	infoframe_sdp.sdp_header.HB3 = (0x13 << 2);
> -	/* CTA Header Byte 2 (INFOFRAME Version Number) */
> -	infoframe_sdp.db[0] = drm_infoframe.version;
> -	/* CTA Header Byte 3 (Length of INFOFRAME):
> HDMI_DRM_INFOFRAME_SIZE */
> -	infoframe_sdp.db[1] = drm_infoframe.length;
> -	/*
> -	 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
> -	 * HDMI_INFOFRAME_HEADER_SIZE
> -	 */
> -	BUILD_BUG_ON(sizeof(infoframe_sdp.db) < HDMI_DRM_INFOFRAME_SIZE
> + 2);
> -	memcpy(&infoframe_sdp.db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
> -	       HDMI_DRM_INFOFRAME_SIZE);
> -
> -	/*
> -	 * Size of DP infoframe sdp packet for HDR static metadata is consist of
> -	 * - DP SDP Header(struct dp_sdp_header): 4 bytes
> -	 * - Two Data Blocks: 2 bytes
> -	 *    CTA Header Byte2 (INFOFRAME Version Number)
> -	 *    CTA Header Byte3 (Length of INFOFRAME)
> -	 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
> -	 *
> -	 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
> -	 * infoframe size. But GEN11+ has larger than that size, write_infoframe
> -	 * will pad rest of the size.
> -	 */
> -	intel_dig_port->write_infoframe(&intel_dig_port->base, crtc_state,
> -					HDMI_PACKET_TYPE_GAMUT_METADATA,
> -					&infoframe_sdp,
> -					sizeof(struct dp_sdp_header) + 2 +
> HDMI_DRM_INFOFRAME_SIZE);
> -}
> -
> -void intel_dp_vsc_enable(struct intel_dp *intel_dp,
> -			 const struct intel_crtc_state *crtc_state,
> -			 const struct drm_connector_state *conn_state)
> -{
> -	if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
> -		return;
> -
> -	intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);
> -}
> -
> -void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
> -				  const struct intel_crtc_state *crtc_state,
> -				  const struct drm_connector_state *conn_state)
> -{
> -	if (!conn_state->hdr_output_metadata)
> -		return;
> -
> -	intel_dp_setup_hdr_metadata_infoframe_sdp(intel_dp,
> -						  crtc_state,
> -						  conn_state);
> -}
> -
>  static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)  {
>  	int status = 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index e8f9ba962d09..6562bb8edeba 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -110,12 +110,6 @@ int intel_dp_link_required(int pixel_clock, int bpp);  int
> intel_dp_max_data_rate(int max_link_clock, int max_lanes);  bool
> intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
>  			    const struct drm_connector_state *conn_state); -void
> intel_dp_vsc_enable(struct intel_dp *intel_dp,
> -			 const struct intel_crtc_state *crtc_state,
> -			 const struct drm_connector_state *conn_state);
> -void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
> -				  const struct intel_crtc_state *crtc_state,
> -				  const struct drm_connector_state *conn_state);
>  void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
>  			     const struct intel_crtc_state *crtc_state,
>  			     const struct drm_connector_state *conn_state);
> --
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

RE: [Intel-gfx] [PATCH v3 12/17] drm/i915: Add state readout for DP HDR Metadata Infoframe SDP

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 12/17] drm/i915: Add state readout for DP HDR
> Metadata Infoframe SDP
> 
> Added state readout for DP HDR Metadata Infoframe SDP.

Looks good.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 374ab6a3757c..a9eaf7a6bc15 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4322,6 +4322,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
>  				      pipe_config->fec_enable);
>  		}
> 
> +		pipe_config->infoframes.enable |> +			intel_hdmi_infoframes_enabled(encoder, pipe_config);
> +
>  		break;
>  	case TRANS_DDI_MODE_SELECT_DP_MST:
>  		pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); @@ -
> 4333,6 +4336,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> 
> 	REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
> 
>  		intel_dp_get_m_n(intel_crtc, pipe_config);
> +
> +		pipe_config->infoframes.enable |> +			intel_hdmi_infoframes_enabled(encoder, pipe_config);
>  		break;
>  	default:
>  		break;
> @@ -4383,6 +4389,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
>  	intel_read_infoframe(encoder, pipe_config,
>  			     HDMI_INFOFRAME_TYPE_DRM,
>  			     &pipe_config->infoframes.drm);
> +
> +	intel_read_dp_sdp(encoder, pipe_config,
> +HDMI_PACKET_TYPE_GAMUT_METADATA);
>  }
> 
>  static enum intel_output_type
> --
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

RE: [Intel-gfx] [PATCH v3 12/17] drm/i915: Add state readout for DP HDR Metadata Infoframe SDP

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 12/17] drm/i915: Add state readout for DP HDR
> Metadata Infoframe SDP
> 
> Added state readout for DP HDR Metadata Infoframe SDP.

Looks good.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 374ab6a3757c..a9eaf7a6bc15 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4322,6 +4322,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
>  				      pipe_config->fec_enable);
>  		}
> 
> +		pipe_config->infoframes.enable |=
> +			intel_hdmi_infoframes_enabled(encoder, pipe_config);
> +
>  		break;
>  	case TRANS_DDI_MODE_SELECT_DP_MST:
>  		pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); @@ -
> 4333,6 +4336,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> 
> 	REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
> 
>  		intel_dp_get_m_n(intel_crtc, pipe_config);
> +
> +		pipe_config->infoframes.enable |=
> +			intel_hdmi_infoframes_enabled(encoder, pipe_config);
>  		break;
>  	default:
>  		break;
> @@ -4383,6 +4389,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
>  	intel_read_infoframe(encoder, pipe_config,
>  			     HDMI_INFOFRAME_TYPE_DRM,
>  			     &pipe_config->infoframes.drm);
> +
> +	intel_read_dp_sdp(encoder, pipe_config,
> +HDMI_PACKET_TYPE_GAMUT_METADATA);
>  }
> 
>  static enum intel_output_type
> --
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Intel-gfx] [PATCH v3 12/17] drm/i915: Add state readout for DP HDR Metadata Infoframe SDP

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 12/17] drm/i915: Add state readout for DP HDR
> Metadata Infoframe SDP
> 
> Added state readout for DP HDR Metadata Infoframe SDP.

Looks good.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 374ab6a3757c..a9eaf7a6bc15 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4322,6 +4322,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
>  				      pipe_config->fec_enable);
>  		}
> 
> +		pipe_config->infoframes.enable |=
> +			intel_hdmi_infoframes_enabled(encoder, pipe_config);
> +
>  		break;
>  	case TRANS_DDI_MODE_SELECT_DP_MST:
>  		pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); @@ -
> 4333,6 +4336,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> 
> 	REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
> 
>  		intel_dp_get_m_n(intel_crtc, pipe_config);
> +
> +		pipe_config->infoframes.enable |=
> +			intel_hdmi_infoframes_enabled(encoder, pipe_config);
>  		break;
>  	default:
>  		break;
> @@ -4383,6 +4389,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
>  	intel_read_infoframe(encoder, pipe_config,
>  			     HDMI_INFOFRAME_TYPE_DRM,
>  			     &pipe_config->infoframes.drm);
> +
> +	intel_read_dp_sdp(encoder, pipe_config,
> +HDMI_PACKET_TYPE_GAMUT_METADATA);
>  }
> 
>  static enum intel_output_type
> --
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

RE: [PATCH v3 13/17] drm/i915: Add state readout for DP VSC SDP

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 13/17] drm/i915: Add state readout for DP VSC SDP
> 
> Added state readout for DP VSC SDP and enabled state validation for DP VSC SDP.
> 
> v2: Minor style fix
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp

Looks good.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c     |  1 +
>  drivers/gpu/drm/i915/display/intel_display.c | 42 ++++++++++++++++++++
>  2 files changed, 43 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a9eaf7a6bc15..64e4edefa998 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4391,6 +4391,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
>  			     &pipe_config->infoframes.drm);
> 
>  	intel_read_dp_sdp(encoder, pipe_config,
> HDMI_PACKET_TYPE_GAMUT_METADATA);
> +	intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
>  }
> 
>  static enum intel_output_type
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 4f187fd330e8..02471c7aa6e7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13503,6 +13503,13 @@ intel_compare_infoframe(const union
> hdmi_infoframe *a,
>  	return memcmp(a, b, sizeof(*a)) = 0;
>  }
> 
> +static bool
> +intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
> +			 const struct drm_dp_vsc_sdp *b)
> +{
> +	return memcmp(a, b, sizeof(*a)) = 0;
> +}
> +
>  static void
>  pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
>  			       bool fastset, const char *name, @@ -13528,6
> +13535,30 @@ pipe_config_infoframe_mismatch(struct drm_i915_private
> *dev_priv,
>  	}
>  }
> 
> +static void
> +pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
> +				bool fastset, const char *name,
> +				const struct drm_dp_vsc_sdp *a,
> +				const struct drm_dp_vsc_sdp *b)
> +{
> +	if (fastset) {
> +		if (!drm_debug_enabled(DRM_UT_KMS))
> +			return;
> +
> +		DRM_DEBUG_KMS("fastset mismatch in %s dp sdp\n", name);
> +		DRM_DEBUG_KMS("expected:\n");
> +		drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
> +		DRM_DEBUG_KMS("found:\n");
> +		drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
> +	} else {
> +		DRM_ERROR("mismatch in %s dp sdp\n", name);
> +		DRM_ERROR("expected:\n");
> +		drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
> +		DRM_ERROR("found:\n");
> +		drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
> +	}
> +}
> +
>  static void __printf(4, 5)
>  pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
>  		     const char *name, const char *format, ...) @@ -13729,6
> +13760,16 @@ intel_pipe_config_compare(const struct intel_crtc_state
> *current_config,
>  	} \
>  } while (0)
> 
> +#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
> +	if (!intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
> +				      &pipe_config->infoframes.name)) { \
> +		pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset,
> __stringify(name), \
> +						&current_config-
> >infoframes.name, \
> +						&pipe_config->infoframes.name);
> \
> +		ret = false; \
> +	} \
> +} while (0)
> +
>  #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
>  	if (current_config->name1 != pipe_config->name1) { \
>  		pipe_config_mismatch(fastset, crtc, __stringify(name1), \ @@ -
> 13902,6 +13943,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
> *current_config,
>  	PIPE_CONF_CHECK_INFOFRAME(spd);
>  	PIPE_CONF_CHECK_INFOFRAME(hdmi);
>  	PIPE_CONF_CHECK_INFOFRAME(drm);
> +	PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
> 
>  	PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
>  	PIPE_CONF_CHECK_I(master_transcoder);
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

RE: [PATCH v3 13/17] drm/i915: Add state readout for DP VSC SDP

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 13/17] drm/i915: Add state readout for DP VSC SDP
> 
> Added state readout for DP VSC SDP and enabled state validation for DP VSC SDP.
> 
> v2: Minor style fix
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp

Looks good.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c     |  1 +
>  drivers/gpu/drm/i915/display/intel_display.c | 42 ++++++++++++++++++++
>  2 files changed, 43 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a9eaf7a6bc15..64e4edefa998 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4391,6 +4391,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
>  			     &pipe_config->infoframes.drm);
> 
>  	intel_read_dp_sdp(encoder, pipe_config,
> HDMI_PACKET_TYPE_GAMUT_METADATA);
> +	intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
>  }
> 
>  static enum intel_output_type
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 4f187fd330e8..02471c7aa6e7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13503,6 +13503,13 @@ intel_compare_infoframe(const union
> hdmi_infoframe *a,
>  	return memcmp(a, b, sizeof(*a)) == 0;
>  }
> 
> +static bool
> +intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
> +			 const struct drm_dp_vsc_sdp *b)
> +{
> +	return memcmp(a, b, sizeof(*a)) == 0;
> +}
> +
>  static void
>  pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
>  			       bool fastset, const char *name, @@ -13528,6
> +13535,30 @@ pipe_config_infoframe_mismatch(struct drm_i915_private
> *dev_priv,
>  	}
>  }
> 
> +static void
> +pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
> +				bool fastset, const char *name,
> +				const struct drm_dp_vsc_sdp *a,
> +				const struct drm_dp_vsc_sdp *b)
> +{
> +	if (fastset) {
> +		if (!drm_debug_enabled(DRM_UT_KMS))
> +			return;
> +
> +		DRM_DEBUG_KMS("fastset mismatch in %s dp sdp\n", name);
> +		DRM_DEBUG_KMS("expected:\n");
> +		drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
> +		DRM_DEBUG_KMS("found:\n");
> +		drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
> +	} else {
> +		DRM_ERROR("mismatch in %s dp sdp\n", name);
> +		DRM_ERROR("expected:\n");
> +		drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
> +		DRM_ERROR("found:\n");
> +		drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
> +	}
> +}
> +
>  static void __printf(4, 5)
>  pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
>  		     const char *name, const char *format, ...) @@ -13729,6
> +13760,16 @@ intel_pipe_config_compare(const struct intel_crtc_state
> *current_config,
>  	} \
>  } while (0)
> 
> +#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
> +	if (!intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
> +				      &pipe_config->infoframes.name)) { \
> +		pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset,
> __stringify(name), \
> +						&current_config-
> >infoframes.name, \
> +						&pipe_config->infoframes.name);
> \
> +		ret = false; \
> +	} \
> +} while (0)
> +
>  #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
>  	if (current_config->name1 != pipe_config->name1) { \
>  		pipe_config_mismatch(fastset, crtc, __stringify(name1), \ @@ -
> 13902,6 +13943,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
> *current_config,
>  	PIPE_CONF_CHECK_INFOFRAME(spd);
>  	PIPE_CONF_CHECK_INFOFRAME(hdmi);
>  	PIPE_CONF_CHECK_INFOFRAME(drm);
> +	PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
> 
>  	PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
>  	PIPE_CONF_CHECK_I(master_transcoder);
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Intel-gfx] [PATCH v3 13/17] drm/i915: Add state readout for DP VSC SDP

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 13/17] drm/i915: Add state readout for DP VSC SDP
> 
> Added state readout for DP VSC SDP and enabled state validation for DP VSC SDP.
> 
> v2: Minor style fix
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp

Looks good.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c     |  1 +
>  drivers/gpu/drm/i915/display/intel_display.c | 42 ++++++++++++++++++++
>  2 files changed, 43 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a9eaf7a6bc15..64e4edefa998 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4391,6 +4391,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
>  			     &pipe_config->infoframes.drm);
> 
>  	intel_read_dp_sdp(encoder, pipe_config,
> HDMI_PACKET_TYPE_GAMUT_METADATA);
> +	intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
>  }
> 
>  static enum intel_output_type
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 4f187fd330e8..02471c7aa6e7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13503,6 +13503,13 @@ intel_compare_infoframe(const union
> hdmi_infoframe *a,
>  	return memcmp(a, b, sizeof(*a)) == 0;
>  }
> 
> +static bool
> +intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
> +			 const struct drm_dp_vsc_sdp *b)
> +{
> +	return memcmp(a, b, sizeof(*a)) == 0;
> +}
> +
>  static void
>  pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
>  			       bool fastset, const char *name, @@ -13528,6
> +13535,30 @@ pipe_config_infoframe_mismatch(struct drm_i915_private
> *dev_priv,
>  	}
>  }
> 
> +static void
> +pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
> +				bool fastset, const char *name,
> +				const struct drm_dp_vsc_sdp *a,
> +				const struct drm_dp_vsc_sdp *b)
> +{
> +	if (fastset) {
> +		if (!drm_debug_enabled(DRM_UT_KMS))
> +			return;
> +
> +		DRM_DEBUG_KMS("fastset mismatch in %s dp sdp\n", name);
> +		DRM_DEBUG_KMS("expected:\n");
> +		drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
> +		DRM_DEBUG_KMS("found:\n");
> +		drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
> +	} else {
> +		DRM_ERROR("mismatch in %s dp sdp\n", name);
> +		DRM_ERROR("expected:\n");
> +		drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
> +		DRM_ERROR("found:\n");
> +		drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
> +	}
> +}
> +
>  static void __printf(4, 5)
>  pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
>  		     const char *name, const char *format, ...) @@ -13729,6
> +13760,16 @@ intel_pipe_config_compare(const struct intel_crtc_state
> *current_config,
>  	} \
>  } while (0)
> 
> +#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
> +	if (!intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
> +				      &pipe_config->infoframes.name)) { \
> +		pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset,
> __stringify(name), \
> +						&current_config-
> >infoframes.name, \
> +						&pipe_config->infoframes.name);
> \
> +		ret = false; \
> +	} \
> +} while (0)
> +
>  #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
>  	if (current_config->name1 != pipe_config->name1) { \
>  		pipe_config_mismatch(fastset, crtc, __stringify(name1), \ @@ -
> 13902,6 +13943,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
> *current_config,
>  	PIPE_CONF_CHECK_INFOFRAME(spd);
>  	PIPE_CONF_CHECK_INFOFRAME(hdmi);
>  	PIPE_CONF_CHECK_INFOFRAME(drm);
> +	PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
> 
>  	PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
>  	PIPE_CONF_CHECK_I(master_transcoder);
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

RE: [PATCH v3 14/17] drm/i915: Program DP SDPs on pipe updates

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 14/17] drm/i915: Program DP SDPs on pipe updates
> 
> Call intel_dp_set_infoframes() function on pipe updates to make sure that we send
> VSC SDP and HDR Metadata Infoframe SDP (when applicable) on fastsets.

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 64e4edefa998..69073a15edb8 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4062,6 +4062,7 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder
> *encoder,
>  	intel_ddi_set_dp_msa(crtc_state, conn_state);
> 
>  	intel_psr_update(intel_dp, crtc_state);
> +	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
>  	intel_edp_drrs_enable(intel_dp, crtc_state);
> 
>  	intel_panel_update_backlight(encoder, crtc_state, conn_state);
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

RE: [PATCH v3 14/17] drm/i915: Program DP SDPs on pipe updates

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 14/17] drm/i915: Program DP SDPs on pipe updates
> 
> Call intel_dp_set_infoframes() function on pipe updates to make sure that we send
> VSC SDP and HDR Metadata Infoframe SDP (when applicable) on fastsets.

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 64e4edefa998..69073a15edb8 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4062,6 +4062,7 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder
> *encoder,
>  	intel_ddi_set_dp_msa(crtc_state, conn_state);
> 
>  	intel_psr_update(intel_dp, crtc_state);
> +	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
>  	intel_edp_drrs_enable(intel_dp, crtc_state);
> 
>  	intel_panel_update_backlight(encoder, crtc_state, conn_state);
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Intel-gfx] [PATCH v3 14/17] drm/i915: Program DP SDPs on pipe updates

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 14/17] drm/i915: Program DP SDPs on pipe updates
> 
> Call intel_dp_set_infoframes() function on pipe updates to make sure that we send
> VSC SDP and HDR Metadata Infoframe SDP (when applicable) on fastsets.

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 64e4edefa998..69073a15edb8 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4062,6 +4062,7 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder
> *encoder,
>  	intel_ddi_set_dp_msa(crtc_state, conn_state);
> 
>  	intel_psr_update(intel_dp, crtc_state);
> +	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
>  	intel_edp_drrs_enable(intel_dp, crtc_state);
> 
>  	intel_panel_update_backlight(encoder, crtc_state, conn_state);
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

RE: [PATCH v3 15/17] drm/i915: Stop sending DP SDPs on intel_ddi_post_disable_dp()

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 15/17] drm/i915: Stop sending DP SDPs on
> intel_ddi_post_disable_dp()

Just say " Stop sending DP SDPs on ddi disable"

> Call intel_dp_set_infoframes(false) function on intel_ddi_post_disable_dp() to make
> sure not to send VSC SDP and HDR Metadata Infoframe SDP.

With the above fixed.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 69073a15edb8..8509cd33569e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3713,6 +3713,8 @@ static void intel_ddi_post_disable_dp(struct intel_encoder
> *encoder,
>  					  INTEL_OUTPUT_DP_MST);
>  	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> 
> +	intel_dp_set_infoframes(encoder, false, old_crtc_state,
> +old_conn_state);
> +
>  	/*
>  	 * Power down sink before disabling the port, otherwise we end
>  	 * up getting interrupts from the sink on detecting link loss.
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

RE: [PATCH v3 15/17] drm/i915: Stop sending DP SDPs on intel_ddi_post_disable_dp()

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 15/17] drm/i915: Stop sending DP SDPs on
> intel_ddi_post_disable_dp()

Just say " Stop sending DP SDPs on ddi disable"

> Call intel_dp_set_infoframes(false) function on intel_ddi_post_disable_dp() to make
> sure not to send VSC SDP and HDR Metadata Infoframe SDP.

With the above fixed.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 69073a15edb8..8509cd33569e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3713,6 +3713,8 @@ static void intel_ddi_post_disable_dp(struct intel_encoder
> *encoder,
>  					  INTEL_OUTPUT_DP_MST);
>  	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> 
> +	intel_dp_set_infoframes(encoder, false, old_crtc_state,
> +old_conn_state);
> +
>  	/*
>  	 * Power down sink before disabling the port, otherwise we end
>  	 * up getting interrupts from the sink on detecting link loss.
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Intel-gfx] [PATCH v3 15/17] drm/i915: Stop sending DP SDPs on intel_ddi_post_disable_dp()

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 15/17] drm/i915: Stop sending DP SDPs on
> intel_ddi_post_disable_dp()

Just say " Stop sending DP SDPs on ddi disable"

> Call intel_dp_set_infoframes(false) function on intel_ddi_post_disable_dp() to make
> sure not to send VSC SDP and HDR Metadata Infoframe SDP.

With the above fixed.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 69073a15edb8..8509cd33569e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3713,6 +3713,8 @@ static void intel_ddi_post_disable_dp(struct intel_encoder
> *encoder,
>  					  INTEL_OUTPUT_DP_MST);
>  	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> 
> +	intel_dp_set_infoframes(encoder, false, old_crtc_state,
> +old_conn_state);
> +
>  	/*
>  	 * Power down sink before disabling the port, otherwise we end
>  	 * up getting interrupts from the sink on detecting link loss.
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

RE: [PATCH v3 16/17] drm/i915/dp: Add compute routine for DP PSR VSC SDP

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 16/17] drm/i915/dp: Add compute routine for DP PSR VSC SDP
> 
> In order to use a common VSC SDP Colorimetry calculating code on PSR, it adds a
> compute routine for PSR VSC SDP.
> As PSR routine can not use infoframes.vsc of crtc state, it also adds new writing of
> DP SDPs (Secondary Data Packet) for PSR.
> PSR routine has its own scenario and timings of writing a VSC SDP.
> 
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 53 +++++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dp.h |  8 ++++
>  2 files changed, 61 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index cffb77daec96..4d65ef36577f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2463,6 +2463,42 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp
> *intel_dp,
>  					 &crtc_state->infoframes.vsc);
>  }
> 
> +void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
> +				  const struct intel_crtc_state *crtc_state,
> +				  const struct drm_connector_state *conn_state,
> +				  struct drm_dp_vsc_sdp *vsc)
> +{
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> +	vsc->sdp_type = DP_SDP_VSC;
> +
> +	if (dev_priv->psr.psr2_enabled) {
> +		if (dev_priv->psr.colorimetry_support &&
> +		    intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> +			/* [PSR2, +Colorimetry] */
> +			intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
> +							 vsc);
> +		} else {
> +			/*
> +			 * [PSR2, -Colorimetry]
> +			 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-
> 11
> +			 * 3D stereo + PSR/PSR2 + Y-coordinate.
> +			 */
> +			vsc->revision = 0x4;
> +			vsc->length = 0xe;
> +		}
> +	} else {
> +		/*
> +		 * [PSR1]
> +		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> +		 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
> +		 * higher).
> +		 */
> +		vsc->revision = 0x2;
> +		vsc->length = 0x8;
> +	}
> +}
> +
>  static void
>  intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_crtc_state
> *crtc_state,
>  					    const struct drm_connector_state
> *conn_state) @@ -4889,6 +4925,23 @@ static void intel_write_dp_sdp(struct
> intel_encoder *encoder,
>  	intel_dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);  }
> 
> +void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
> +			    const struct intel_crtc_state *crtc_state,
> +			    struct drm_dp_vsc_sdp *vsc)
> +{
> +	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
> +	struct dp_sdp sdp = {};
> +	ssize_t len;
> +
> +	len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
> +
> +	if (WARN_ON(len < 0))
> +		return;
> +
> +	intel_dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
> +					&sdp, len);
> +}
> +
>  void intel_dp_set_infoframes(struct intel_encoder *encoder,
>  			     bool enable,
>  			     const struct intel_crtc_state *crtc_state, diff --git
> a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index 6562bb8edeba..5074e52722c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -18,6 +18,7 @@ struct drm_connector_state;  struct drm_encoder;  struct
> drm_i915_private;  struct drm_modeset_acquire_ctx;
> +struct drm_dp_vsc_sdp;
>  struct intel_connector;
>  struct intel_crtc_state;
>  struct intel_digital_port;
> @@ -110,6 +111,13 @@ int intel_dp_link_required(int pixel_clock, int bpp);  int
> intel_dp_max_data_rate(int max_link_clock, int max_lanes);  bool
> intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
>  			    const struct drm_connector_state *conn_state);
> +void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
> +				  const struct intel_crtc_state *crtc_state,
> +				  const struct drm_connector_state *conn_state,
> +				  struct drm_dp_vsc_sdp *vsc);
> +void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
> +			    const struct intel_crtc_state *crtc_state,
> +			    struct drm_dp_vsc_sdp *vsc);
>  void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
>  			     const struct intel_crtc_state *crtc_state,
>  			     const struct drm_connector_state *conn_state);
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

RE: [PATCH v3 16/17] drm/i915/dp: Add compute routine for DP PSR VSC SDP

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 16/17] drm/i915/dp: Add compute routine for DP PSR VSC SDP
> 
> In order to use a common VSC SDP Colorimetry calculating code on PSR, it adds a
> compute routine for PSR VSC SDP.
> As PSR routine can not use infoframes.vsc of crtc state, it also adds new writing of
> DP SDPs (Secondary Data Packet) for PSR.
> PSR routine has its own scenario and timings of writing a VSC SDP.
> 
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 53 +++++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dp.h |  8 ++++
>  2 files changed, 61 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index cffb77daec96..4d65ef36577f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2463,6 +2463,42 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp
> *intel_dp,
>  					 &crtc_state->infoframes.vsc);
>  }
> 
> +void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
> +				  const struct intel_crtc_state *crtc_state,
> +				  const struct drm_connector_state *conn_state,
> +				  struct drm_dp_vsc_sdp *vsc)
> +{
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> +	vsc->sdp_type = DP_SDP_VSC;
> +
> +	if (dev_priv->psr.psr2_enabled) {
> +		if (dev_priv->psr.colorimetry_support &&
> +		    intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> +			/* [PSR2, +Colorimetry] */
> +			intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
> +							 vsc);
> +		} else {
> +			/*
> +			 * [PSR2, -Colorimetry]
> +			 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-
> 11
> +			 * 3D stereo + PSR/PSR2 + Y-coordinate.
> +			 */
> +			vsc->revision = 0x4;
> +			vsc->length = 0xe;
> +		}
> +	} else {
> +		/*
> +		 * [PSR1]
> +		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> +		 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
> +		 * higher).
> +		 */
> +		vsc->revision = 0x2;
> +		vsc->length = 0x8;
> +	}
> +}
> +
>  static void
>  intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_crtc_state
> *crtc_state,
>  					    const struct drm_connector_state
> *conn_state) @@ -4889,6 +4925,23 @@ static void intel_write_dp_sdp(struct
> intel_encoder *encoder,
>  	intel_dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);  }
> 
> +void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
> +			    const struct intel_crtc_state *crtc_state,
> +			    struct drm_dp_vsc_sdp *vsc)
> +{
> +	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
> +	struct dp_sdp sdp = {};
> +	ssize_t len;
> +
> +	len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
> +
> +	if (WARN_ON(len < 0))
> +		return;
> +
> +	intel_dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
> +					&sdp, len);
> +}
> +
>  void intel_dp_set_infoframes(struct intel_encoder *encoder,
>  			     bool enable,
>  			     const struct intel_crtc_state *crtc_state, diff --git
> a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index 6562bb8edeba..5074e52722c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -18,6 +18,7 @@ struct drm_connector_state;  struct drm_encoder;  struct
> drm_i915_private;  struct drm_modeset_acquire_ctx;
> +struct drm_dp_vsc_sdp;
>  struct intel_connector;
>  struct intel_crtc_state;
>  struct intel_digital_port;
> @@ -110,6 +111,13 @@ int intel_dp_link_required(int pixel_clock, int bpp);  int
> intel_dp_max_data_rate(int max_link_clock, int max_lanes);  bool
> intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
>  			    const struct drm_connector_state *conn_state);
> +void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
> +				  const struct intel_crtc_state *crtc_state,
> +				  const struct drm_connector_state *conn_state,
> +				  struct drm_dp_vsc_sdp *vsc);
> +void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
> +			    const struct intel_crtc_state *crtc_state,
> +			    struct drm_dp_vsc_sdp *vsc);
>  void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
>  			     const struct intel_crtc_state *crtc_state,
>  			     const struct drm_connector_state *conn_state);
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Intel-gfx] [PATCH v3 16/17] drm/i915/dp: Add compute routine for DP PSR VSC SDP

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [PATCH v3 16/17] drm/i915/dp: Add compute routine for DP PSR VSC SDP
> 
> In order to use a common VSC SDP Colorimetry calculating code on PSR, it adds a
> compute routine for PSR VSC SDP.
> As PSR routine can not use infoframes.vsc of crtc state, it also adds new writing of
> DP SDPs (Secondary Data Packet) for PSR.
> PSR routine has its own scenario and timings of writing a VSC SDP.
> 
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 53 +++++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dp.h |  8 ++++
>  2 files changed, 61 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index cffb77daec96..4d65ef36577f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2463,6 +2463,42 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp
> *intel_dp,
>  					 &crtc_state->infoframes.vsc);
>  }
> 
> +void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
> +				  const struct intel_crtc_state *crtc_state,
> +				  const struct drm_connector_state *conn_state,
> +				  struct drm_dp_vsc_sdp *vsc)
> +{
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> +	vsc->sdp_type = DP_SDP_VSC;
> +
> +	if (dev_priv->psr.psr2_enabled) {
> +		if (dev_priv->psr.colorimetry_support &&
> +		    intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> +			/* [PSR2, +Colorimetry] */
> +			intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
> +							 vsc);
> +		} else {
> +			/*
> +			 * [PSR2, -Colorimetry]
> +			 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-
> 11
> +			 * 3D stereo + PSR/PSR2 + Y-coordinate.
> +			 */
> +			vsc->revision = 0x4;
> +			vsc->length = 0xe;
> +		}
> +	} else {
> +		/*
> +		 * [PSR1]
> +		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> +		 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
> +		 * higher).
> +		 */
> +		vsc->revision = 0x2;
> +		vsc->length = 0x8;
> +	}
> +}
> +
>  static void
>  intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_crtc_state
> *crtc_state,
>  					    const struct drm_connector_state
> *conn_state) @@ -4889,6 +4925,23 @@ static void intel_write_dp_sdp(struct
> intel_encoder *encoder,
>  	intel_dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);  }
> 
> +void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
> +			    const struct intel_crtc_state *crtc_state,
> +			    struct drm_dp_vsc_sdp *vsc)
> +{
> +	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
> +	struct dp_sdp sdp = {};
> +	ssize_t len;
> +
> +	len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
> +
> +	if (WARN_ON(len < 0))
> +		return;
> +
> +	intel_dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
> +					&sdp, len);
> +}
> +
>  void intel_dp_set_infoframes(struct intel_encoder *encoder,
>  			     bool enable,
>  			     const struct intel_crtc_state *crtc_state, diff --git
> a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index 6562bb8edeba..5074e52722c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -18,6 +18,7 @@ struct drm_connector_state;  struct drm_encoder;  struct
> drm_i915_private;  struct drm_modeset_acquire_ctx;
> +struct drm_dp_vsc_sdp;
>  struct intel_connector;
>  struct intel_crtc_state;
>  struct intel_digital_port;
> @@ -110,6 +111,13 @@ int intel_dp_link_required(int pixel_clock, int bpp);  int
> intel_dp_max_data_rate(int max_link_clock, int max_lanes);  bool
> intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
>  			    const struct drm_connector_state *conn_state);
> +void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
> +				  const struct intel_crtc_state *crtc_state,
> +				  const struct drm_connector_state *conn_state,
> +				  struct drm_dp_vsc_sdp *vsc);
> +void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
> +			    const struct intel_crtc_state *crtc_state,
> +			    struct drm_dp_vsc_sdp *vsc);
>  void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
>  			     const struct intel_crtc_state *crtc_state,
>  			     const struct drm_connector_state *conn_state);
> --
> 2.24.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

RE: [Intel-gfx] [PATCH v3 17/17] drm/i915/psr: Use new DP VSC SDP compute routine on PSR

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 17/17] drm/i915/psr: Use new DP VSC SDP compute
> routine on PSR
> 
> In order to use a common VSC SDP Colorimetry calculating code on PSR, it uses a
> new psr vsc sdp compute routine.
> Because PSR routine has its own scenario and timings of writing a VSC SDP, the
> current PSR routine needs to have its own drm_dp_vsc_sdp structure member
> variable on struct i915_psr.
> 
> In order to calculate colorimetry information, intel_psr_update() function and
> intel_psr_enable() function extend a drm_connector_state argument.
> 
> There are no changes to PSR mechanism.
> 
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp

Looks good.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

Note: Please rebase, fix the comments and resend to trigger a full CI run.

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c |  4 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 54 +++++++-----------------
> drivers/gpu/drm/i915/display/intel_psr.h |  6 ++-
>  drivers/gpu/drm/i915/i915_drv.h          |  1 +
>  4 files changed, 22 insertions(+), 43 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 8509cd33569e..00b46c45f6a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3901,7 +3901,7 @@ static void intel_enable_ddi_dp(struct intel_encoder
> *encoder,
>  		intel_dp_stop_link_train(intel_dp);
> 
>  	intel_edp_backlight_on(crtc_state, conn_state);
> -	intel_psr_enable(intel_dp, crtc_state);
> +	intel_psr_enable(intel_dp, crtc_state, conn_state);
>  	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
>  	intel_edp_drrs_enable(intel_dp, crtc_state);
> 
> @@ -4063,7 +4063,7 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder
> *encoder,
> 
>  	intel_ddi_set_dp_msa(crtc_state, conn_state);
> 
> -	intel_psr_update(intel_dp, crtc_state);
> +	intel_psr_update(intel_dp, crtc_state, conn_state);
>  	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
>  	intel_edp_drrs_enable(intel_dp, crtc_state);
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index e41ed962aa80..a4564607b6c5 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -330,39 +330,6 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>  	}
>  }
> 
> -static void intel_psr_setup_vsc(struct intel_dp *intel_dp,
> -				const struct intel_crtc_state *crtc_state)
> -{
> -	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> -	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -	struct dp_sdp psr_vsc;
> -
> -	if (dev_priv->psr.psr2_enabled) {
> -		/* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
> -		memset(&psr_vsc, 0, sizeof(psr_vsc));
> -		psr_vsc.sdp_header.HB0 = 0;
> -		psr_vsc.sdp_header.HB1 = 0x7;
> -		if (dev_priv->psr.colorimetry_support) {
> -			psr_vsc.sdp_header.HB2 = 0x5;
> -			psr_vsc.sdp_header.HB3 = 0x13;
> -		} else {
> -			psr_vsc.sdp_header.HB2 = 0x4;
> -			psr_vsc.sdp_header.HB3 = 0xe;
> -		}
> -	} else {
> -		/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
> -		memset(&psr_vsc, 0, sizeof(psr_vsc));
> -		psr_vsc.sdp_header.HB0 = 0;
> -		psr_vsc.sdp_header.HB1 = 0x7;
> -		psr_vsc.sdp_header.HB2 = 0x2;
> -		psr_vsc.sdp_header.HB3 = 0x8;
> -	}
> -
> -	intel_dig_port->write_infoframe(&intel_dig_port->base,
> -					crtc_state,
> -					DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc));
> -}
> -
>  static void hsw_psr_setup_aux(struct intel_dp *intel_dp)  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -841,9
> +808,12 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,  }
> 
>  static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
> -				    const struct intel_crtc_state *crtc_state)
> +				    const struct intel_crtc_state *crtc_state,
> +				    const struct drm_connector_state *conn_state)
>  {
>  	struct intel_dp *intel_dp = dev_priv->psr.dp;
> +	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> +	struct intel_encoder *encoder = &intel_dig_port->base;
>  	u32 val;
> 
>  	WARN_ON(dev_priv->psr.enabled);
> @@ -881,7 +851,9 @@ static void intel_psr_enable_locked(struct drm_i915_private
> *dev_priv,
> 
>  	DRM_DEBUG_KMS("Enabling PSR%s\n",
>  		      dev_priv->psr.psr2_enabled ? "2" : "1");
> -	intel_psr_setup_vsc(intel_dp, crtc_state);
> +	intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
> +				     &dev_priv->psr.vsc);
> +	intel_write_dp_vsc_sdp(encoder, crtc_state, &dev_priv->psr.vsc);
>  	intel_psr_enable_sink(intel_dp);
>  	intel_psr_enable_source(intel_dp, crtc_state);
>  	dev_priv->psr.enabled = true;
> @@ -893,11 +865,13 @@ static void intel_psr_enable_locked(struct
> drm_i915_private *dev_priv,
>   * intel_psr_enable - Enable PSR
>   * @intel_dp: Intel DP
>   * @crtc_state: new CRTC state
> + * @conn_state: new CONNECTOR state
>   *
>   * This function can only be called after the pipe is fully trained and enabled.
>   */
>  void intel_psr_enable(struct intel_dp *intel_dp,
> -		      const struct intel_crtc_state *crtc_state)
> +		      const struct intel_crtc_state *crtc_state,
> +		      const struct drm_connector_state *conn_state)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> 
> @@ -916,7 +890,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
>  		goto unlock;
>  	}
> 
> -	intel_psr_enable_locked(dev_priv, crtc_state);
> +	intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
> 
>  unlock:
>  	mutex_unlock(&dev_priv->psr.lock);
> @@ -1049,13 +1023,15 @@ static void psr_force_hw_tracking_exit(struct
> drm_i915_private *dev_priv)
>   * intel_psr_update - Update PSR state
>   * @intel_dp: Intel DP
>   * @crtc_state: new CRTC state
> + * @conn_state: new CONNECTOR state
>   *
>   * This functions will update PSR states, disabling, enabling or switching PSR
>   * version when executing fastsets. For full modeset, intel_psr_disable() and
>   * intel_psr_enable() should be called instead.
>   */
>  void intel_psr_update(struct intel_dp *intel_dp,
> -		      const struct intel_crtc_state *crtc_state)
> +		      const struct intel_crtc_state *crtc_state,
> +		      const struct drm_connector_state *conn_state)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	struct i915_psr *psr = &dev_priv->psr; @@ -1090,7 +1066,7 @@ void
> intel_psr_update(struct intel_dp *intel_dp,
>  		intel_psr_disable_locked(intel_dp);
> 
>  	if (enable)
> -		intel_psr_enable_locked(dev_priv, crtc_state);
> +		intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
> 
>  unlock:
>  	mutex_unlock(&dev_priv->psr.lock);
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index c58a1d438808..a003fb18105a 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -17,11 +17,13 @@ struct intel_dp;
>  #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
> void intel_psr_init_dpcd(struct intel_dp *intel_dp);  void intel_psr_enable(struct
> intel_dp *intel_dp,
> -		      const struct intel_crtc_state *crtc_state);
> +		      const struct intel_crtc_state *crtc_state,
> +		      const struct drm_connector_state *conn_state);
>  void intel_psr_disable(struct intel_dp *intel_dp,
>  		       const struct intel_crtc_state *old_crtc_state);  void
> intel_psr_update(struct intel_dp *intel_dp,
> -		      const struct intel_crtc_state *crtc_state);
> +		      const struct intel_crtc_state *crtc_state,
> +		      const struct drm_connector_state *conn_state);
>  int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 value);  void
> intel_psr_invalidate(struct drm_i915_private *dev_priv,
>  			  unsigned frontbuffer_bits,
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a8a08c63278e..fa2f1a18ffe0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -504,6 +504,7 @@ struct i915_psr {
>  	u32 dc3co_exit_delay;
>  	struct delayed_work idle_work;
>  	bool initially_probed;
> +	struct drm_dp_vsc_sdp vsc;
>  };
> 
>  #define QUIRK_LVDS_SSC_DISABLE (1<<1)
> --
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

RE: [Intel-gfx] [PATCH v3 17/17] drm/i915/psr: Use new DP VSC SDP compute routine on PSR

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 17/17] drm/i915/psr: Use new DP VSC SDP compute
> routine on PSR
> 
> In order to use a common VSC SDP Colorimetry calculating code on PSR, it uses a
> new psr vsc sdp compute routine.
> Because PSR routine has its own scenario and timings of writing a VSC SDP, the
> current PSR routine needs to have its own drm_dp_vsc_sdp structure member
> variable on struct i915_psr.
> 
> In order to calculate colorimetry information, intel_psr_update() function and
> intel_psr_enable() function extend a drm_connector_state argument.
> 
> There are no changes to PSR mechanism.
> 
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp

Looks good.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

Note: Please rebase, fix the comments and resend to trigger a full CI run.

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c |  4 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 54 +++++++-----------------
> drivers/gpu/drm/i915/display/intel_psr.h |  6 ++-
>  drivers/gpu/drm/i915/i915_drv.h          |  1 +
>  4 files changed, 22 insertions(+), 43 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 8509cd33569e..00b46c45f6a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3901,7 +3901,7 @@ static void intel_enable_ddi_dp(struct intel_encoder
> *encoder,
>  		intel_dp_stop_link_train(intel_dp);
> 
>  	intel_edp_backlight_on(crtc_state, conn_state);
> -	intel_psr_enable(intel_dp, crtc_state);
> +	intel_psr_enable(intel_dp, crtc_state, conn_state);
>  	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
>  	intel_edp_drrs_enable(intel_dp, crtc_state);
> 
> @@ -4063,7 +4063,7 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder
> *encoder,
> 
>  	intel_ddi_set_dp_msa(crtc_state, conn_state);
> 
> -	intel_psr_update(intel_dp, crtc_state);
> +	intel_psr_update(intel_dp, crtc_state, conn_state);
>  	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
>  	intel_edp_drrs_enable(intel_dp, crtc_state);
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index e41ed962aa80..a4564607b6c5 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -330,39 +330,6 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>  	}
>  }
> 
> -static void intel_psr_setup_vsc(struct intel_dp *intel_dp,
> -				const struct intel_crtc_state *crtc_state)
> -{
> -	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> -	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -	struct dp_sdp psr_vsc;
> -
> -	if (dev_priv->psr.psr2_enabled) {
> -		/* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
> -		memset(&psr_vsc, 0, sizeof(psr_vsc));
> -		psr_vsc.sdp_header.HB0 = 0;
> -		psr_vsc.sdp_header.HB1 = 0x7;
> -		if (dev_priv->psr.colorimetry_support) {
> -			psr_vsc.sdp_header.HB2 = 0x5;
> -			psr_vsc.sdp_header.HB3 = 0x13;
> -		} else {
> -			psr_vsc.sdp_header.HB2 = 0x4;
> -			psr_vsc.sdp_header.HB3 = 0xe;
> -		}
> -	} else {
> -		/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
> -		memset(&psr_vsc, 0, sizeof(psr_vsc));
> -		psr_vsc.sdp_header.HB0 = 0;
> -		psr_vsc.sdp_header.HB1 = 0x7;
> -		psr_vsc.sdp_header.HB2 = 0x2;
> -		psr_vsc.sdp_header.HB3 = 0x8;
> -	}
> -
> -	intel_dig_port->write_infoframe(&intel_dig_port->base,
> -					crtc_state,
> -					DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc));
> -}
> -
>  static void hsw_psr_setup_aux(struct intel_dp *intel_dp)  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -841,9
> +808,12 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,  }
> 
>  static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
> -				    const struct intel_crtc_state *crtc_state)
> +				    const struct intel_crtc_state *crtc_state,
> +				    const struct drm_connector_state *conn_state)
>  {
>  	struct intel_dp *intel_dp = dev_priv->psr.dp;
> +	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> +	struct intel_encoder *encoder = &intel_dig_port->base;
>  	u32 val;
> 
>  	WARN_ON(dev_priv->psr.enabled);
> @@ -881,7 +851,9 @@ static void intel_psr_enable_locked(struct drm_i915_private
> *dev_priv,
> 
>  	DRM_DEBUG_KMS("Enabling PSR%s\n",
>  		      dev_priv->psr.psr2_enabled ? "2" : "1");
> -	intel_psr_setup_vsc(intel_dp, crtc_state);
> +	intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
> +				     &dev_priv->psr.vsc);
> +	intel_write_dp_vsc_sdp(encoder, crtc_state, &dev_priv->psr.vsc);
>  	intel_psr_enable_sink(intel_dp);
>  	intel_psr_enable_source(intel_dp, crtc_state);
>  	dev_priv->psr.enabled = true;
> @@ -893,11 +865,13 @@ static void intel_psr_enable_locked(struct
> drm_i915_private *dev_priv,
>   * intel_psr_enable - Enable PSR
>   * @intel_dp: Intel DP
>   * @crtc_state: new CRTC state
> + * @conn_state: new CONNECTOR state
>   *
>   * This function can only be called after the pipe is fully trained and enabled.
>   */
>  void intel_psr_enable(struct intel_dp *intel_dp,
> -		      const struct intel_crtc_state *crtc_state)
> +		      const struct intel_crtc_state *crtc_state,
> +		      const struct drm_connector_state *conn_state)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> 
> @@ -916,7 +890,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
>  		goto unlock;
>  	}
> 
> -	intel_psr_enable_locked(dev_priv, crtc_state);
> +	intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
> 
>  unlock:
>  	mutex_unlock(&dev_priv->psr.lock);
> @@ -1049,13 +1023,15 @@ static void psr_force_hw_tracking_exit(struct
> drm_i915_private *dev_priv)
>   * intel_psr_update - Update PSR state
>   * @intel_dp: Intel DP
>   * @crtc_state: new CRTC state
> + * @conn_state: new CONNECTOR state
>   *
>   * This functions will update PSR states, disabling, enabling or switching PSR
>   * version when executing fastsets. For full modeset, intel_psr_disable() and
>   * intel_psr_enable() should be called instead.
>   */
>  void intel_psr_update(struct intel_dp *intel_dp,
> -		      const struct intel_crtc_state *crtc_state)
> +		      const struct intel_crtc_state *crtc_state,
> +		      const struct drm_connector_state *conn_state)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	struct i915_psr *psr = &dev_priv->psr; @@ -1090,7 +1066,7 @@ void
> intel_psr_update(struct intel_dp *intel_dp,
>  		intel_psr_disable_locked(intel_dp);
> 
>  	if (enable)
> -		intel_psr_enable_locked(dev_priv, crtc_state);
> +		intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
> 
>  unlock:
>  	mutex_unlock(&dev_priv->psr.lock);
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index c58a1d438808..a003fb18105a 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -17,11 +17,13 @@ struct intel_dp;
>  #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
> void intel_psr_init_dpcd(struct intel_dp *intel_dp);  void intel_psr_enable(struct
> intel_dp *intel_dp,
> -		      const struct intel_crtc_state *crtc_state);
> +		      const struct intel_crtc_state *crtc_state,
> +		      const struct drm_connector_state *conn_state);
>  void intel_psr_disable(struct intel_dp *intel_dp,
>  		       const struct intel_crtc_state *old_crtc_state);  void
> intel_psr_update(struct intel_dp *intel_dp,
> -		      const struct intel_crtc_state *crtc_state);
> +		      const struct intel_crtc_state *crtc_state,
> +		      const struct drm_connector_state *conn_state);
>  int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 value);  void
> intel_psr_invalidate(struct drm_i915_private *dev_priv,
>  			  unsigned frontbuffer_bits,
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a8a08c63278e..fa2f1a18ffe0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -504,6 +504,7 @@ struct i915_psr {
>  	u32 dc3co_exit_delay;
>  	struct delayed_work idle_work;
>  	bool initially_probed;
> +	struct drm_dp_vsc_sdp vsc;
>  };
> 
>  #define QUIRK_LVDS_SSC_DISABLE (1<<1)
> --
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Intel-gfx] [PATCH v3 17/17] drm/i915/psr: Use new DP VSC SDP compute routine on PSR

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 17/17] drm/i915/psr: Use new DP VSC SDP compute
> routine on PSR
> 
> In order to use a common VSC SDP Colorimetry calculating code on PSR, it uses a
> new psr vsc sdp compute routine.
> Because PSR routine has its own scenario and timings of writing a VSC SDP, the
> current PSR routine needs to have its own drm_dp_vsc_sdp structure member
> variable on struct i915_psr.
> 
> In order to calculate colorimetry information, intel_psr_update() function and
> intel_psr_enable() function extend a drm_connector_state argument.
> 
> There are no changes to PSR mechanism.
> 
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp

Looks good.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

Note: Please rebase, fix the comments and resend to trigger a full CI run.

> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c |  4 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 54 +++++++-----------------
> drivers/gpu/drm/i915/display/intel_psr.h |  6 ++-
>  drivers/gpu/drm/i915/i915_drv.h          |  1 +
>  4 files changed, 22 insertions(+), 43 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 8509cd33569e..00b46c45f6a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3901,7 +3901,7 @@ static void intel_enable_ddi_dp(struct intel_encoder
> *encoder,
>  		intel_dp_stop_link_train(intel_dp);
> 
>  	intel_edp_backlight_on(crtc_state, conn_state);
> -	intel_psr_enable(intel_dp, crtc_state);
> +	intel_psr_enable(intel_dp, crtc_state, conn_state);
>  	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
>  	intel_edp_drrs_enable(intel_dp, crtc_state);
> 
> @@ -4063,7 +4063,7 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder
> *encoder,
> 
>  	intel_ddi_set_dp_msa(crtc_state, conn_state);
> 
> -	intel_psr_update(intel_dp, crtc_state);
> +	intel_psr_update(intel_dp, crtc_state, conn_state);
>  	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
>  	intel_edp_drrs_enable(intel_dp, crtc_state);
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index e41ed962aa80..a4564607b6c5 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -330,39 +330,6 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>  	}
>  }
> 
> -static void intel_psr_setup_vsc(struct intel_dp *intel_dp,
> -				const struct intel_crtc_state *crtc_state)
> -{
> -	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> -	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -	struct dp_sdp psr_vsc;
> -
> -	if (dev_priv->psr.psr2_enabled) {
> -		/* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
> -		memset(&psr_vsc, 0, sizeof(psr_vsc));
> -		psr_vsc.sdp_header.HB0 = 0;
> -		psr_vsc.sdp_header.HB1 = 0x7;
> -		if (dev_priv->psr.colorimetry_support) {
> -			psr_vsc.sdp_header.HB2 = 0x5;
> -			psr_vsc.sdp_header.HB3 = 0x13;
> -		} else {
> -			psr_vsc.sdp_header.HB2 = 0x4;
> -			psr_vsc.sdp_header.HB3 = 0xe;
> -		}
> -	} else {
> -		/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
> -		memset(&psr_vsc, 0, sizeof(psr_vsc));
> -		psr_vsc.sdp_header.HB0 = 0;
> -		psr_vsc.sdp_header.HB1 = 0x7;
> -		psr_vsc.sdp_header.HB2 = 0x2;
> -		psr_vsc.sdp_header.HB3 = 0x8;
> -	}
> -
> -	intel_dig_port->write_infoframe(&intel_dig_port->base,
> -					crtc_state,
> -					DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc));
> -}
> -
>  static void hsw_psr_setup_aux(struct intel_dp *intel_dp)  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -841,9
> +808,12 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,  }
> 
>  static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
> -				    const struct intel_crtc_state *crtc_state)
> +				    const struct intel_crtc_state *crtc_state,
> +				    const struct drm_connector_state *conn_state)
>  {
>  	struct intel_dp *intel_dp = dev_priv->psr.dp;
> +	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> +	struct intel_encoder *encoder = &intel_dig_port->base;
>  	u32 val;
> 
>  	WARN_ON(dev_priv->psr.enabled);
> @@ -881,7 +851,9 @@ static void intel_psr_enable_locked(struct drm_i915_private
> *dev_priv,
> 
>  	DRM_DEBUG_KMS("Enabling PSR%s\n",
>  		      dev_priv->psr.psr2_enabled ? "2" : "1");
> -	intel_psr_setup_vsc(intel_dp, crtc_state);
> +	intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
> +				     &dev_priv->psr.vsc);
> +	intel_write_dp_vsc_sdp(encoder, crtc_state, &dev_priv->psr.vsc);
>  	intel_psr_enable_sink(intel_dp);
>  	intel_psr_enable_source(intel_dp, crtc_state);
>  	dev_priv->psr.enabled = true;
> @@ -893,11 +865,13 @@ static void intel_psr_enable_locked(struct
> drm_i915_private *dev_priv,
>   * intel_psr_enable - Enable PSR
>   * @intel_dp: Intel DP
>   * @crtc_state: new CRTC state
> + * @conn_state: new CONNECTOR state
>   *
>   * This function can only be called after the pipe is fully trained and enabled.
>   */
>  void intel_psr_enable(struct intel_dp *intel_dp,
> -		      const struct intel_crtc_state *crtc_state)
> +		      const struct intel_crtc_state *crtc_state,
> +		      const struct drm_connector_state *conn_state)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> 
> @@ -916,7 +890,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
>  		goto unlock;
>  	}
> 
> -	intel_psr_enable_locked(dev_priv, crtc_state);
> +	intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
> 
>  unlock:
>  	mutex_unlock(&dev_priv->psr.lock);
> @@ -1049,13 +1023,15 @@ static void psr_force_hw_tracking_exit(struct
> drm_i915_private *dev_priv)
>   * intel_psr_update - Update PSR state
>   * @intel_dp: Intel DP
>   * @crtc_state: new CRTC state
> + * @conn_state: new CONNECTOR state
>   *
>   * This functions will update PSR states, disabling, enabling or switching PSR
>   * version when executing fastsets. For full modeset, intel_psr_disable() and
>   * intel_psr_enable() should be called instead.
>   */
>  void intel_psr_update(struct intel_dp *intel_dp,
> -		      const struct intel_crtc_state *crtc_state)
> +		      const struct intel_crtc_state *crtc_state,
> +		      const struct drm_connector_state *conn_state)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	struct i915_psr *psr = &dev_priv->psr; @@ -1090,7 +1066,7 @@ void
> intel_psr_update(struct intel_dp *intel_dp,
>  		intel_psr_disable_locked(intel_dp);
> 
>  	if (enable)
> -		intel_psr_enable_locked(dev_priv, crtc_state);
> +		intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
> 
>  unlock:
>  	mutex_unlock(&dev_priv->psr.lock);
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index c58a1d438808..a003fb18105a 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -17,11 +17,13 @@ struct intel_dp;
>  #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
> void intel_psr_init_dpcd(struct intel_dp *intel_dp);  void intel_psr_enable(struct
> intel_dp *intel_dp,
> -		      const struct intel_crtc_state *crtc_state);
> +		      const struct intel_crtc_state *crtc_state,
> +		      const struct drm_connector_state *conn_state);
>  void intel_psr_disable(struct intel_dp *intel_dp,
>  		       const struct intel_crtc_state *old_crtc_state);  void
> intel_psr_update(struct intel_dp *intel_dp,
> -		      const struct intel_crtc_state *crtc_state);
> +		      const struct intel_crtc_state *crtc_state,
> +		      const struct drm_connector_state *conn_state);
>  int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 value);  void
> intel_psr_invalidate(struct drm_i915_private *dev_priv,
>  			  unsigned frontbuffer_bits,
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a8a08c63278e..fa2f1a18ffe0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -504,6 +504,7 @@ struct i915_psr {
>  	u32 dc3co_exit_delay;
>  	struct delayed_work idle_work;
>  	bool initially_probed;
> +	struct drm_dp_vsc_sdp vsc;
>  };
> 
>  #define QUIRK_LVDS_SSC_DISABLE (1<<1)
> --
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v3 01/17] drm: add DP 1.4 VSC SDP Payload related enums and a structure

[Mun, Gwan-gyeong]

T24gV2VkLCAyMDIwLTAyLTA1IGF0IDIwOjEyICswNTMwLCBTaGFua2FyLCBVbWEgd3JvdGU6DQo+
ID4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gPiBGcm9tOiBkcmktZGV2ZWwgPGRyaS1k
ZXZlbC1ib3VuY2VzQGxpc3RzLmZyZWVkZXNrdG9wLm9yZz4gT24gQmVoYWxmDQo+ID4gT2YgR3dh
bi0NCj4gPiBneWVvbmcgTXVuDQo+ID4gU2VudDogVHVlc2RheSwgRmVicnVhcnkgNCwgMjAyMCA0
OjUwIEFNDQo+ID4gVG86IGludGVsLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcNCj4gPiBDYzog
bGludXgtZmJkZXZAdmdlci5rZXJuZWwub3JnOyBkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Au
b3JnDQo+ID4gU3ViamVjdDogW1BBVENIIHYzIDAxLzE3XSBkcm06IGFkZCBEUCAxLjQgVlNDIFNE
UCBQYXlsb2FkIHJlbGF0ZWQNCj4gPiBlbnVtcyBhbmQgYQ0KPiA+IHN0cnVjdHVyZQ0KPiANCj4g
JXMvYWRkL0FkZC8NCj4gQWxzbyB5b3UgY2FuIHJlcGhyYXNlIHRoaXMgYXMgIiBBZGQgRFAxLjQg
VlNDIFNEUCBQYXlsb2FkIHJlbGF0ZWQNCj4gRGF0YSBTdHJ1Y3R1cmVzIi8NCj4gDQpIaSBVbWEs
DQpUaGFuayB5b3UgZm9yIHJldmlld2luZyBhIHBhdGNoIHNlcmllcy4NCg0KT2theSBJJ2xsIHJl
cGhyYXNlIGNvbW1pdCBtZXNzYWdlIHdpdGggeW91ciBndWlkZS4NCg0KPiA+IEl0IGFkZHMgbmV3
IGVudW1lcmF0aW9uIGRlZmluaXRpb25zIGZvciBWU0MgU0RQIFBheWxvYWQgZm9yIFBpeGVsDQo+
ID4gRW5jb2RpbmcvQ29sb3JpbWV0cnkgRm9ybWF0Lg0KPiA+IEFuZCBpdCBhZGRzIGEgbmV3IGRy
bSBkYXRhIHN0cnVjdHVyZSBmb3IgRFAgVlNDIFNEUC4NCj4gPiANCj4gPiBlbnVtIGRwX2NvbG9y
c3BhY2UgYW5kIGVudW0gZHBfY29sb3JpbWV0cnkgY29ycmVzcG9uZCAiUGl4ZWwNCj4gPiBFbmNv
ZGluZyBhbmQNCj4gPiBDb2xvcmltZXRyeSBGb3JtYXRzIi4gZW51bSBkcF9keW5hbWljX3Jhbmdl
IGNvcnJlc3BvbmRzICJEeW5hbWljDQo+ID4gUmFuZ2UiLg0KPiA+IEFuZCBlbnVtIGRwX2NvbnRl
bnRfdHlwZSBjb3JyZXNwb25kcyAiQ29udGVudCBUeXBlIg0KPiA+IEFsbCBvZiB0aGVtIGFyZSBi
YXNlZCBvbiBEUCAxLjQgc3BlYyBbVGFibGUgMi0xMTc6IFZTQyBTRFAgUGF5bG9hZA0KPiA+IGZv
cg0KPiA+IERCMTYgdGhyb3VnaCBEQjE4XS4NCj4gPiANCj4gPiB2MzogQWRkIGEgbmV3IGRybSBk
YXRhIHN0cnVjdHVyZSBmb3IgRFAgVlNDIFNEUA0KPiA+IA0KPiA+IFNpZ25lZC1vZmYtYnk6IEd3
YW4tZ3llb25nIE11biA8Z3dhbi1neWVvbmcubXVuQGludGVsLmNvbT4NCj4gPiAtLS0NCj4gPiAg
aW5jbHVkZS9kcm0vZHJtX2RwX2hlbHBlci5oIHwgNTcNCj4gPiArKysrKysrKysrKysrKysrKysr
KysrKysrKysrKysrKysrKysrDQo+ID4gIDEgZmlsZSBjaGFuZ2VkLCA1NyBpbnNlcnRpb25zKCsp
DQo+ID4gDQo+ID4gZGlmZiAtLWdpdCBhL2luY2x1ZGUvZHJtL2RybV9kcF9oZWxwZXIuaA0KPiA+
IGIvaW5jbHVkZS9kcm0vZHJtX2RwX2hlbHBlci5oIGluZGV4DQo+ID4gMjYyZmFmOWU1ZTk0Li5j
MDk4NzI3NjgxZmEgMTAwNjQ0DQo+ID4gLS0tIGEvaW5jbHVkZS9kcm0vZHJtX2RwX2hlbHBlci5o
DQo+ID4gKysrIGIvaW5jbHVkZS9kcm0vZHJtX2RwX2hlbHBlci5oDQo+ID4gQEAgLTEyMDksNiAr
MTIwOSw2MyBAQCBzdHJ1Y3QgZHBfc2RwIHsNCj4gPiAgI2RlZmluZSBFRFBfVlNDX1BTUl9VUERB
VEVfUkZCCQkoMTw8MSkNCj4gPiAgI2RlZmluZSBFRFBfVlNDX1BTUl9DUkNfVkFMVUVTX1ZBTElE
CSgxPDwyKQ0KPiA+IA0KPiA+ICsvKiBCYXNlZCBvbiBEUCAxLjQgc3BlYyBbVGFibGUgMi0xMTc6
IFZTQyBTRFAgUGF5bG9hZCBmb3IgREIxNg0KPiA+IHRocm91Z2gNCj4gPiArREIxOF0gKi8gZW51
bSBkcF9jb2xvcnNwYWNlIHsNCj4gDQo+IFdlIHNob3VsZCBub3QgY2FsbCB0aGlzIGNvbG9yc3Bh
Y2UsIHJhdGhlciByZW5hbWUgaXQgdG8NCj4gZHBfcGl4ZWxmb3JtYXQuDQo+IFRoZXNlIGFyZSBu
b3QgY29sb3JzcGFjZXMuDQo+IA0KPiBBbHNvIGFkZCB0aGVzZSB0byBrZXJuZWwgZG9jcyBhcyB0
aGV5IGFyZSBzdGFuZGFyZCBkZWZpbml0aW9ucy4NCj4gDQo+ID4gKwlEUF9DT0xPUlNQQUNFX1JH
QiA9IDAsDQo+IA0KPiBNYWtlIHRoaXMgYXMgRFBfUElYRUxGT1JNQVRfUkdCIGFuZCByZW5hbWUg
YWxsIHRoZSBiZWxvdyBvbmVzIGFzDQo+IHdlbGwuDQo+IA0KPiA+ICsJRFBfQ09MT1JTUEFDRV9Z
VVY0NDQgPSAweDEsDQo+ID4gKwlEUF9DT0xPUlNQQUNFX1lVVjQyMiA9IDB4MiwNCj4gPiArCURQ
X0NPTE9SU1BBQ0VfWVVWNDIwID0gMHgzLA0KPiA+ICsJRFBfQ09MT1JTUEFDRV9ZX09OTFkgPSAw
eDQsDQo+ID4gKwlEUF9DT0xPUlNQQUNFX1JBVyA9IDB4NSwNCj4gPiArCURQX0NPTE9SU1BBQ0Vf
UkVTRVJWRUQgPSAweDYsDQo+ID4gK307DQo+ID4gKw0KPiA+ICsvKioNCj4gPiArICogQmFzZWQg
b24gRFAgMS40IHNwZWMgW1RhYmxlIDItMTE3OiBWU0MgU0RQIFBheWxvYWQgZm9yIERCMTYNCj4g
PiB0aHJvdWdoDQo+ID4gK0RCMThdDQo+ID4gKyAqIGFuZCBhIG5hbWUgb2YgZW51bSBtZW1iZXIg
Zm9sbG93ZXMgRFJNX01PREVfQ09MT1JJTUVUUlkNCj4gPiBkZWZpbml0aW9uLg0KPiANCj4gVHlw
byBpbiBmb2xsb3dzDQo+IA0KPiA+ICsgKi8NCj4gPiArZW51bSBkcF9jb2xvcmltZXRyeSB7DQo+
IA0KPiBZb3UgY2FuIGNhbGwgdGhpcyBhcyBkcF9jb2xvcnNwYWNlICh0aGlzIGlzIGFjdHVhbCBj
b2xvcnNwYWNlKSwgeW91DQo+IGNhbiBzdGljayB3aXRoIGNvbG9yaW1ldHJ5IGFzIHdlbGwuDQo+
IFdpbGwgbGVhdmUgdGhhdCB0byB5b3UuDQpZZXMsIHRoZSBEUCBzcGVjIHVzZXMgY29sb3JpbWV0
cnkgYXMgdGhlIHRlcm0sIEkgcHJlZmVyIGNvbG9yaW1ldHJ5Lg0KPiANCj4gPiArCURQX0NPTE9S
SU1FVFJZX0RFRkFVTFQgPSAwLCAvKiBzUkdCIChJRUMgNjE5NjYtMi0xKSAvIElUVS1SDQo+ID4g
QlQuNjAxICovDQo+ID4gKwlEUF9DT0xPUklNRVRSWV9SR0JfV0lERV9GSVhFRCA9IDB4MSwNCj4g
PiArCURQX0NPTE9SSU1FVFJZX0JUNzA5X1lDQyA9IDB4MSwNCj4gPiArCURQX0NPTE9SSU1FVFJZ
X1JHQl9XSURFX0ZMT0FUID0gMHgyLA0KPiA+ICsJRFBfQ09MT1JJTUVUUllfWFZZQ0NfNjAxID0g
MHgyLA0KPiA+ICsJRFBfQ09MT1JJTUVUUllfT1BSR0IgPSAweDMsDQo+ID4gKwlEUF9DT0xPUklN
RVRSWV9YVllDQ183MDkgPSAweDMsDQo+ID4gKwlEUF9DT0xPUklNRVRSWV9EQ0lfUDNfUkdCID0g
MHg0LA0KPiA+ICsJRFBfQ09MT1JJTUVUUllfU1lDQ182MDEgPSAweDQsDQo+ID4gKwlEUF9DT0xP
UklNRVRSWV9SR0JfQ1VTVE9NID0gMHg1LA0KPiA+ICsJRFBfQ09MT1JJTUVUUllfT1BZQ0NfNjAx
ID0gMHg1LA0KPiA+ICsJRFBfQ09MT1JJTUVUUllfQlQyMDIwX1JHQiA9IDB4NiwNCj4gPiArCURQ
X0NPTE9SSU1FVFJZX0JUMjAyMF9DWUNDID0gMHg2LA0KPiA+ICsJRFBfQ09MT1JJTUVUUllfQlQy
MDIwX1lDQyA9IDB4NywNCj4gPiArfTsNCj4gPiArDQo+ID4gK2VudW0gZHBfZHluYW1pY19yYW5n
ZSB7DQo+ID4gKwlEUF9EWU5BTUlDX1JBTkdFX1ZFU0EgPSAwLA0KPiA+ICsJRFBfRFlOQU1JQ19S
QU5HRV9DVEEgPSAxLA0KPiA+ICt9Ow0KPiA+ICsNCj4gPiArZW51bSBkcF9jb250ZW50X3R5cGUg
ew0KPiA+ICsJRFBfQ09OVEVOVF9UWVBFX05PVF9ERUZJTkVEID0gMHgwMCwNCj4gPiArCURQX0NP
TlRFTlRfVFlQRV9HUkFQSElDUyA9IDB4MDEsDQo+ID4gKwlEUF9DT05URU5UX1RZUEVfUEhPVE8g
PSAweDAyLA0KPiA+ICsJRFBfQ09OVEVOVF9UWVBFX1ZJREVPID0gMHgwMywNCj4gPiArCURQX0NP
TlRFTlRfVFlQRV9HQU1FID0gMHgwNCwNCj4gPiArfTsNCj4gPiArDQo+ID4gKy8qIERSTSBEUCBW
U0MgU0RQIGFzIHBlciBEUCAxLjQgc3BlYyAqLyBzdHJ1Y3QgZHJtX2RwX3ZzY19zZHAgew0KPiA+
ICsJdW5zaWduZWQgY2hhciBzZHBfdHlwZTsgLyogU2Vjb25kYXJ5LWRhdGEgUGFja2V0IFR5cGUg
Ki8NCj4gPiArCXVuc2lnbmVkIGNoYXIgcmV2aXNpb247IC8qIFJldmlzaW9uIE51bWJlciAqLw0K
PiANCj4gVGhlc2UgY29tbWVudHMgc2VlbXMgc2VsZi1leHBsYW5hdG9yeSwgeW91IGNhbiBwcm9i
YWJseSBkcm9wIHRoZW0uDQo+IA0KVGhhbmsgeW91IGZvciByZXZpZXcgaW4gZGV0YWlsLCBJJ2xs
IHVwZGF0ZSBldmVyeXRoaW5nIHRoYXQgeW91IGNvbW1lbnRlZC4NCj4gPiArCXVuc2lnbmVkIGNo
YXIgbGVuZ3RoOyAvKiBOdW1iZXIgb2YgVmFsaWQgRGF0YSBCeXRlcyAqLw0KPiA+ICsJZW51bSBk
cF9jb2xvcnNwYWNlIGNvbG9yc3BhY2U7DQo+ID4gKwllbnVtIGRwX2NvbG9yaW1ldHJ5IGNvbG9y
aW1ldHJ5Ow0KPiA+ICsJaW50IGJwYzsgLyogYml0IHBlciBjb2xvciAqLw0KPiA+ICsJZW51bSBk
cF9keW5hbWljX3JhbmdlIGR5bmFtaWNfcmFuZ2U7DQo+ID4gKwllbnVtIGRwX2NvbnRlbnRfdHlw
ZSBjb250ZW50X3R5cGU7DQo+ID4gK307DQo+ID4gKw0KPiA+ICBpbnQgZHJtX2RwX3Bzcl9zZXR1
cF90aW1lKGNvbnN0IHU4DQo+ID4gcHNyX2NhcFtFRFBfUFNSX1JFQ0VJVkVSX0NBUF9TSVpFXSk7
DQo+ID4gDQo+ID4gIHN0YXRpYyBpbmxpbmUgaW50DQo+ID4gLS0NCj4gPiAyLjI0LjENCj4gPiAN
Cj4gPiBfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXw0KPiA+
IGRyaS1kZXZlbCBtYWlsaW5nIGxpc3QNCj4gPiBkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Au
b3JnDQo+ID4gaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9k
cmktZGV2ZWwNCg=

Re: [PATCH v3 01/17] drm: add DP 1.4 VSC SDP Payload related enums and a structure

[Mun, Gwan-gyeong]

On Wed, 2020-02-05 at 20:12 +0530, Shankar, Uma wrote:
> > -----Original Message-----
> > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf
> > Of Gwan-
> > gyeong Mun
> > Sent: Tuesday, February 4, 2020 4:50 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> > Subject: [PATCH v3 01/17] drm: add DP 1.4 VSC SDP Payload related
> > enums and a
> > structure
> 
> %s/add/Add/
> Also you can rephrase this as " Add DP1.4 VSC SDP Payload related
> Data Structures"/
> 
Hi Uma,
Thank you for reviewing a patch series.

Okay I'll rephrase commit message with your guide.

> > It adds new enumeration definitions for VSC SDP Payload for Pixel
> > Encoding/Colorimetry Format.
> > And it adds a new drm data structure for DP VSC SDP.
> > 
> > enum dp_colorspace and enum dp_colorimetry correspond "Pixel
> > Encoding and
> > Colorimetry Formats". enum dp_dynamic_range corresponds "Dynamic
> > Range".
> > And enum dp_content_type corresponds "Content Type"
> > All of them are based on DP 1.4 spec [Table 2-117: VSC SDP Payload
> > for
> > DB16 through DB18].
> > 
> > v3: Add a new drm data structure for DP VSC SDP
> > 
> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > ---
> >  include/drm/drm_dp_helper.h | 57
> > +++++++++++++++++++++++++++++++++++++
> >  1 file changed, 57 insertions(+)
> > 
> > diff --git a/include/drm/drm_dp_helper.h
> > b/include/drm/drm_dp_helper.h index
> > 262faf9e5e94..c098727681fa 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -1209,6 +1209,63 @@ struct dp_sdp {
> >  #define EDP_VSC_PSR_UPDATE_RFB		(1<<1)
> >  #define EDP_VSC_PSR_CRC_VALUES_VALID	(1<<2)
> > 
> > +/* Based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16
> > through
> > +DB18] */ enum dp_colorspace {
> 
> We should not call this colorspace, rather rename it to
> dp_pixelformat.
> These are not colorspaces.
> 
> Also add these to kernel docs as they are standard definitions.
> 
> > +	DP_COLORSPACE_RGB = 0,
> 
> Make this as DP_PIXELFORMAT_RGB and rename all the below ones as
> well.
> 
> > +	DP_COLORSPACE_YUV444 = 0x1,
> > +	DP_COLORSPACE_YUV422 = 0x2,
> > +	DP_COLORSPACE_YUV420 = 0x3,
> > +	DP_COLORSPACE_Y_ONLY = 0x4,
> > +	DP_COLORSPACE_RAW = 0x5,
> > +	DP_COLORSPACE_RESERVED = 0x6,
> > +};
> > +
> > +/**
> > + * Based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16
> > through
> > +DB18]
> > + * and a name of enum member followes DRM_MODE_COLORIMETRY
> > definition.
> 
> Typo in follows
> 
> > + */
> > +enum dp_colorimetry {
> 
> You can call this as dp_colorspace (this is actual colorspace), you
> can stick with colorimetry as well.
> Will leave that to you.
Yes, the DP spec uses colorimetry as the term, I prefer colorimetry.
> 
> > +	DP_COLORIMETRY_DEFAULT = 0, /* sRGB (IEC 61966-2-1) / ITU-R
> > BT.601 */
> > +	DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
> > +	DP_COLORIMETRY_BT709_YCC = 0x1,
> > +	DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
> > +	DP_COLORIMETRY_XVYCC_601 = 0x2,
> > +	DP_COLORIMETRY_OPRGB = 0x3,
> > +	DP_COLORIMETRY_XVYCC_709 = 0x3,
> > +	DP_COLORIMETRY_DCI_P3_RGB = 0x4,
> > +	DP_COLORIMETRY_SYCC_601 = 0x4,
> > +	DP_COLORIMETRY_RGB_CUSTOM = 0x5,
> > +	DP_COLORIMETRY_OPYCC_601 = 0x5,
> > +	DP_COLORIMETRY_BT2020_RGB = 0x6,
> > +	DP_COLORIMETRY_BT2020_CYCC = 0x6,
> > +	DP_COLORIMETRY_BT2020_YCC = 0x7,
> > +};
> > +
> > +enum dp_dynamic_range {
> > +	DP_DYNAMIC_RANGE_VESA = 0,
> > +	DP_DYNAMIC_RANGE_CTA = 1,
> > +};
> > +
> > +enum dp_content_type {
> > +	DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
> > +	DP_CONTENT_TYPE_GRAPHICS = 0x01,
> > +	DP_CONTENT_TYPE_PHOTO = 0x02,
> > +	DP_CONTENT_TYPE_VIDEO = 0x03,
> > +	DP_CONTENT_TYPE_GAME = 0x04,
> > +};
> > +
> > +/* DRM DP VSC SDP as per DP 1.4 spec */ struct drm_dp_vsc_sdp {
> > +	unsigned char sdp_type; /* Secondary-data Packet Type */
> > +	unsigned char revision; /* Revision Number */
> 
> These comments seems self-explanatory, you can probably drop them.
> 
Thank you for review in detail, I'll update everything that you commented.
> > +	unsigned char length; /* Number of Valid Data Bytes */
> > +	enum dp_colorspace colorspace;
> > +	enum dp_colorimetry colorimetry;
> > +	int bpc; /* bit per color */
> > +	enum dp_dynamic_range dynamic_range;
> > +	enum dp_content_type content_type;
> > +};
> > +
> >  int drm_dp_psr_setup_time(const u8
> > psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
> > 
> >  static inline int
> > --
> > 2.24.1
> > 
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Intel-gfx] [PATCH v3 01/17] drm: add DP 1.4 VSC SDP Payload related enums and a structure

[Mun, Gwan-gyeong]

On Wed, 2020-02-05 at 20:12 +0530, Shankar, Uma wrote:
> > -----Original Message-----
> > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf
> > Of Gwan-
> > gyeong Mun
> > Sent: Tuesday, February 4, 2020 4:50 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> > Subject: [PATCH v3 01/17] drm: add DP 1.4 VSC SDP Payload related
> > enums and a
> > structure
> 
> %s/add/Add/
> Also you can rephrase this as " Add DP1.4 VSC SDP Payload related
> Data Structures"/
> 
Hi Uma,
Thank you for reviewing a patch series.

Okay I'll rephrase commit message with your guide.

> > It adds new enumeration definitions for VSC SDP Payload for Pixel
> > Encoding/Colorimetry Format.
> > And it adds a new drm data structure for DP VSC SDP.
> > 
> > enum dp_colorspace and enum dp_colorimetry correspond "Pixel
> > Encoding and
> > Colorimetry Formats". enum dp_dynamic_range corresponds "Dynamic
> > Range".
> > And enum dp_content_type corresponds "Content Type"
> > All of them are based on DP 1.4 spec [Table 2-117: VSC SDP Payload
> > for
> > DB16 through DB18].
> > 
> > v3: Add a new drm data structure for DP VSC SDP
> > 
> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > ---
> >  include/drm/drm_dp_helper.h | 57
> > +++++++++++++++++++++++++++++++++++++
> >  1 file changed, 57 insertions(+)
> > 
> > diff --git a/include/drm/drm_dp_helper.h
> > b/include/drm/drm_dp_helper.h index
> > 262faf9e5e94..c098727681fa 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -1209,6 +1209,63 @@ struct dp_sdp {
> >  #define EDP_VSC_PSR_UPDATE_RFB		(1<<1)
> >  #define EDP_VSC_PSR_CRC_VALUES_VALID	(1<<2)
> > 
> > +/* Based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16
> > through
> > +DB18] */ enum dp_colorspace {
> 
> We should not call this colorspace, rather rename it to
> dp_pixelformat.
> These are not colorspaces.
> 
> Also add these to kernel docs as they are standard definitions.
> 
> > +	DP_COLORSPACE_RGB = 0,
> 
> Make this as DP_PIXELFORMAT_RGB and rename all the below ones as
> well.
> 
> > +	DP_COLORSPACE_YUV444 = 0x1,
> > +	DP_COLORSPACE_YUV422 = 0x2,
> > +	DP_COLORSPACE_YUV420 = 0x3,
> > +	DP_COLORSPACE_Y_ONLY = 0x4,
> > +	DP_COLORSPACE_RAW = 0x5,
> > +	DP_COLORSPACE_RESERVED = 0x6,
> > +};
> > +
> > +/**
> > + * Based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16
> > through
> > +DB18]
> > + * and a name of enum member followes DRM_MODE_COLORIMETRY
> > definition.
> 
> Typo in follows
> 
> > + */
> > +enum dp_colorimetry {
> 
> You can call this as dp_colorspace (this is actual colorspace), you
> can stick with colorimetry as well.
> Will leave that to you.
Yes, the DP spec uses colorimetry as the term, I prefer colorimetry.
> 
> > +	DP_COLORIMETRY_DEFAULT = 0, /* sRGB (IEC 61966-2-1) / ITU-R
> > BT.601 */
> > +	DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
> > +	DP_COLORIMETRY_BT709_YCC = 0x1,
> > +	DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
> > +	DP_COLORIMETRY_XVYCC_601 = 0x2,
> > +	DP_COLORIMETRY_OPRGB = 0x3,
> > +	DP_COLORIMETRY_XVYCC_709 = 0x3,
> > +	DP_COLORIMETRY_DCI_P3_RGB = 0x4,
> > +	DP_COLORIMETRY_SYCC_601 = 0x4,
> > +	DP_COLORIMETRY_RGB_CUSTOM = 0x5,
> > +	DP_COLORIMETRY_OPYCC_601 = 0x5,
> > +	DP_COLORIMETRY_BT2020_RGB = 0x6,
> > +	DP_COLORIMETRY_BT2020_CYCC = 0x6,
> > +	DP_COLORIMETRY_BT2020_YCC = 0x7,
> > +};
> > +
> > +enum dp_dynamic_range {
> > +	DP_DYNAMIC_RANGE_VESA = 0,
> > +	DP_DYNAMIC_RANGE_CTA = 1,
> > +};
> > +
> > +enum dp_content_type {
> > +	DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
> > +	DP_CONTENT_TYPE_GRAPHICS = 0x01,
> > +	DP_CONTENT_TYPE_PHOTO = 0x02,
> > +	DP_CONTENT_TYPE_VIDEO = 0x03,
> > +	DP_CONTENT_TYPE_GAME = 0x04,
> > +};
> > +
> > +/* DRM DP VSC SDP as per DP 1.4 spec */ struct drm_dp_vsc_sdp {
> > +	unsigned char sdp_type; /* Secondary-data Packet Type */
> > +	unsigned char revision; /* Revision Number */
> 
> These comments seems self-explanatory, you can probably drop them.
> 
Thank you for review in detail, I'll update everything that you commented.
> > +	unsigned char length; /* Number of Valid Data Bytes */
> > +	enum dp_colorspace colorspace;
> > +	enum dp_colorimetry colorimetry;
> > +	int bpc; /* bit per color */
> > +	enum dp_dynamic_range dynamic_range;
> > +	enum dp_content_type content_type;
> > +};
> > +
> >  int drm_dp_psr_setup_time(const u8
> > psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
> > 
> >  static inline int
> > --
> > 2.24.1
> > 
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs (Secondary Data Packet)

[Mun, Gwan-gyeong]

T24gV2VkLCAyMDIwLTAyLTA1IGF0IDIxOjM5ICswNTMwLCBTaGFua2FyLCBVbWEgd3JvdGU6DQo+
ID4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gPiBGcm9tOiBkcmktZGV2ZWwgPGRyaS1k
ZXZlbC1ib3VuY2VzQGxpc3RzLmZyZWVkZXNrdG9wLm9yZz4gT24gQmVoYWxmDQo+ID4gT2YgR3dh
bi0NCj4gPiBneWVvbmcgTXVuDQo+ID4gU2VudDogVHVlc2RheSwgRmVicnVhcnkgNCwgMjAyMCA0
OjUwIEFNDQo+ID4gVG86IGludGVsLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcNCj4gPiBDYzog
bGludXgtZmJkZXZAdmdlci5rZXJuZWwub3JnOyBkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Au
b3JnDQo+ID4gU3ViamVjdDogW1BBVENIIHYzIDA0LzE3XSBkcm0vaTkxNS9kcDogQWRkIHdyaXRp
bmcgb2YgRFAgU0RQcw0KPiA+IChTZWNvbmRhcnkgRGF0YQ0KPiA+IFBhY2tldCkNCj4gDQo+IERy
b3AgdGhpbmdzIGluICgpLCBub3QgbmVlZGVkLg0KPiANCj4gPiBJdCBhZGRzIHJvdXRpbmVzIHRo
YXQgd3JpdGUgRFAgVlNDIFNEUCBhbmQgRFAgSERSIE1ldGFkYXRhDQo+ID4gSW5mb2ZyYW1lIFNE
UC4NCj4gPiBJbiBvcmRlciB0byBwYWNrIERQIFZTQyBTRFAsIGl0IGFkZHMgaW50ZWxfZHBfdnNj
X3NkcF9wYWNrKCkNCj4gPiBmdW5jdGlvbi4NCj4gPiBJdCBmb2xsb3dzIERQIDEuNGEgc3BlYy4g
W1RhYmxlIDItMTE2OiBWU0MgU0RQIEhlYWRlciBCeXRlc10gYW5kDQo+ID4gW1RhYmxlIDItMTE3
OiBWU0MNCj4gPiBTRFAgUGF5bG9hZCBmb3IgREIxNiB0aHJvdWdoIERCMThdDQo+ID4gDQo+ID4g
SW4gb3JkZXIgdG8gcGFjayBEUCBIRFIgTWV0YWRhdGEgSW5mb2ZyYW1lIFNEUCwgaXQgYWRkcw0K
PiA+IGludGVsX2RwX2hkcl9tZXRhZGF0YV9pbmZvZnJhbWVfc2RwX3BhY2soKSBmdW5jdGlvbi4N
Cj4gPiBBbmQgaXQgZm9sbG93cyBEUCAxLjRhIHNwZWMuDQo+ID4gKFtUYWJsZSAyLTEyNTogSU5G
T0ZSQU1FIFNEUCB2MS4yIEhlYWRlciBCeXRlc10gYW5kIFtUYWJsZSAyLTEyNjoNCj4gPiBJTkZP
RlJBTUUNCj4gPiBTRFAgdjEuMiBQYXlsb2FkIERhdGEgQnl0ZXMgLSBEQjAgdGhyb3VnaCBEQjMx
XSkgYW5kIENUQS04NjEtRw0KPiA+IHNwZWMuIFtUYWJsZS00Mg0KPiA+IER5bmFtaWMgUmFuZ2Ug
YW5kIE1hc3RlcmluZyBJbmZvRnJhbWVdLg0KPiA+IA0KPiA+IEEgbWFjaGFuaXNtIGFuZCBhIG5h
bWluZyBydWxlIG9mIGludGVsX2RwX3NldF9pbmZvZnJhbWVzKCkgZnVuY3Rpb24NCj4gPiByZWZl
cmVuY2VzDQo+IA0KPiBUeXBvIGluIG1lY2hhbmlzbS4NCj4gDQo+ID4gaW50ZWxfZW5jb2Rlci0+
c2V0X2luZm9mcmFtZXMoKSBvZiBpbnRlbF9oZG1pLmMgLg0KPiA+IFZTQyBTRFAgaXMgdXNlZCBm
b3IgUFNSIGFuZCBQaXhlbCBFbmNvZGluZyBhbmQgQ29sb3JpbWV0cnkgRm9ybWF0cw0KPiA+IGNh
c2VzLg0KPiA+IEJlY2F1c2UgUFNSIHJvdXRpbmUgaGFzIGl0cyBvd24gcm91dGluZSBvZiB3cml0
aW5nIGEgVlNDIFNEUCwgd2hlbg0KPiA+IHRoZSBQU1IgaXMNCj4gPiBlbmFibGVkLCBpbnRlbF9k
cF9zZXRfaW5mb2ZyYW1lcygpIGRvZXMgbm90IHdyaXRlIGEgVlNDIFNEUC4NCj4gPiANCj4gPiB2
MzoNCj4gPiAgIC0gRXhwbGljaXRseSBkaXNhYmxlIHVudXNlZCBESVBzIChBVkksIEdDUCwgVlMs
IFNQRCwgRFJNLiBUaGV5DQo+ID4gd2lsbCBiZQ0KPiA+ICAgICB1c2VkIGZvciBIRE1JKSwgd2hl
biBpbnRlbF9kcF9zZXRfaW5mb2ZyYW1lcygpIGZ1bmN0aW9uIHdpbGwgYmUNCj4gPiBjYWxsZWQu
DQo+ID4gICAtIFJlcGxhY2UgYSBzdHJ1Y3R1cmUgbmFtZSB0byBkcm1fZHBfdnNjX3NkcCBmcm9t
DQo+ID4gaW50ZWxfZHBfdnNjX3NkcC4NCj4gPiANCj4gPiBTaWduZWQtb2ZmLWJ5OiBHd2FuLWd5
ZW9uZyBNdW4gPGd3YW4tZ3llb25nLm11bkBpbnRlbC5jb20+DQo+ID4gLS0tDQo+ID4gIGRyaXZl
cnMvZ3B1L2RybS9pOTE1L2Rpc3BsYXkvaW50ZWxfZHAuYyB8IDE5NA0KPiA+ICsrKysrKysrKysr
KysrKysrKysrKysrKw0KPiA+ICBkcml2ZXJzL2dwdS9kcm0vaTkxNS9kaXNwbGF5L2ludGVsX2Rw
LmggfCAgIDMgKw0KPiA+ICAyIGZpbGVzIGNoYW5nZWQsIDE5NyBpbnNlcnRpb25zKCspDQo+ID4g
DQo+ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2Rpc3BsYXkvaW50ZWxfZHAu
Yw0KPiA+IGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9kcC5jDQo+ID4gaW5k
ZXggYjI2NWI1YzU5OWYyLi5kZDdlNTU4ODAwMWUgMTAwNjQ0DQo+ID4gLS0tIGEvZHJpdmVycy9n
cHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9kcC5jDQo+ID4gKysrIGIvZHJpdmVycy9ncHUvZHJt
L2k5MTUvZGlzcGxheS9pbnRlbF9kcC5jDQo+ID4gQEAgLTQ3MzEsNiArNDczMSwyMDAgQEAgaW50
ZWxfZHBfbmVlZHNfdnNjX3NkcChjb25zdCBzdHJ1Y3QNCj4gPiBpbnRlbF9jcnRjX3N0YXRlDQo+
ID4gKmNydGNfc3RhdGUsDQo+ID4gIAlyZXR1cm4gZmFsc2U7DQo+ID4gIH0NCj4gPiANCj4gPiAr
c3RhdGljIHNzaXplX3QgaW50ZWxfZHBfdnNjX3NkcF9wYWNrKGNvbnN0IHN0cnVjdCBkcm1fZHBf
dnNjX3NkcA0KPiA+ICp2c2MsDQo+ID4gKwkJCQkgICAgIHN0cnVjdCBkcF9zZHAgKnNkcCwgc2l6
ZV90IHNpemUpIHsNCj4gPiArCXNpemVfdCBsZW5ndGggPSBzaXplb2Yoc3RydWN0IGRwX3NkcCk7
DQo+ID4gKw0KPiA+ICsJaWYgKHNpemUgPCBsZW5ndGgpDQo+ID4gKwkJcmV0dXJuIC1FTk9TUEM7
DQo+ID4gKw0KPiA+ICsJbWVtc2V0KHNkcCwgMCwgc2l6ZSk7DQo+ID4gKw0KPiA+ICsJLyoNCj4g
PiArCSAqIFByZXBhcmUgVlNDIEhlYWRlciBmb3IgU1UgYXMgcGVyIERQIDEuNGEgc3BlYywgVGFi
bGUgMi0xMTkNCj4gPiArCSAqIFZTQyBTRFAgSGVhZGVyIEJ5dGVzDQo+ID4gKwkgKi8NCj4gPiAr
CXNkcC0+c2RwX2hlYWRlci5IQjAgPSAwOyAvKiBTZWNvbmRhcnktRGF0YSBQYWNrZXQgSUQgPSAw
ICovDQo+ID4gKwlzZHAtPnNkcF9oZWFkZXIuSEIxID0gdnNjLT5zZHBfdHlwZTsgLyogU2Vjb25k
YXJ5LWRhdGEgUGFja2V0DQo+ID4gVHlwZSAqLw0KPiA+ICsJc2RwLT5zZHBfaGVhZGVyLkhCMiA9
IHZzYy0+cmV2aXNpb247IC8qIFJldmlzaW9uIE51bWJlciAqLw0KPiA+ICsJc2RwLT5zZHBfaGVh
ZGVyLkhCMyA9IHZzYy0+bGVuZ3RoOyAvKiBOdW1iZXIgb2YgVmFsaWQgRGF0YQ0KPiA+IEJ5dGVz
ICovDQo+ID4gKw0KPiA+ICsJLyogVlNDIFNEUCBQYXlsb2FkIGZvciBEQjE2IHRocm91Z2ggREIx
OCAqLw0KPiA+ICsJLyogUGl4ZWwgRW5jb2RpbmcgYW5kIENvbG9yaW1ldHJ5IEZvcm1hdHMgICov
DQo+ID4gKwlzZHAtPmRiWzE2XSA9ICh2c2MtPmNvbG9yc3BhY2UgJiAweGYpIDw8IDQ7IC8qIERC
MTZbNzo0XSAqLw0KPiA+ICsJc2RwLT5kYlsxNl0gfD0gdnNjLT5jb2xvcmltZXRyeSAmIDB4Zjsg
LyogREIxNlszOjBdICovDQo+ID4gKw0KPiA+ICsJc3dpdGNoICh2c2MtPmJwYykgew0KPiA+ICsJ
Y2FzZSA4Og0KPiA+ICsJCXNkcC0+ZGJbMTddID0gMHgxOyAvKiBEQjE3WzM6MF0gKi8NCj4gPiAr
CQlicmVhazsNCj4gPiArCWNhc2UgMTA6DQo+ID4gKwkJc2RwLT5kYlsxN10gPSAweDI7DQo+ID4g
KwkJYnJlYWs7DQo+ID4gKwljYXNlIDEyOg0KPiA+ICsJCXNkcC0+ZGJbMTddID0gMHgzOw0KPiA+
ICsJCWJyZWFrOw0KPiA+ICsJY2FzZSAxNjoNCj4gPiArCQlzZHAtPmRiWzE3XSA9IDB4NDsNCj4g
PiArCQlicmVhazsNCj4gPiArCWRlZmF1bHQ6DQo+ID4gKwkJTUlTU0lOR19DQVNFKHZzYy0+YnBj
KTsNCj4gDQo+IDZicGMgaXMgbm90IGhhbmRsZWQgaGVyZSwgYWRkIHRoYXQgYXMgd2VsbC4NCj4g
DQpZZXMsIEkgbWlzc2VkIDZicGMgY2FzZSwgSSdsbCB1cGRhdGUgaXQuDQo+ID4gKwkJYnJlYWs7
DQo+ID4gKwl9DQo+ID4gKwkvKiBEeW5hbWljIFJhbmdlIGFuZCBDb21wb25lbnQgQml0IERlcHRo
ICovDQo+ID4gKwlpZiAodnNjLT5keW5hbWljX3JhbmdlID09IERQX0RZTkFNSUNfUkFOR0VfQ1RB
KQ0KPiA+ICsJCXNkcC0+ZGJbMTddIHw9IDB4ODA7ICAvKiBEQjE3WzddICovDQo+ID4gKw0KPiA+
ICsJLyogQ29udGVudCBUeXBlICovDQo+ID4gKwlzZHAtPmRiWzE4XSA9IHZzYy0+Y29udGVudF90
eXBlICYgMHg3Ow0KPiA+ICsNCj4gPiArCXJldHVybiBsZW5ndGg7DQo+ID4gK30NCj4gPiArDQo+
ID4gK3N0YXRpYyBzc2l6ZV90DQo+ID4gK2ludGVsX2RwX2hkcl9tZXRhZGF0YV9pbmZvZnJhbWVf
c2RwX3BhY2soY29uc3Qgc3RydWN0DQo+ID4gaGRtaV9kcm1faW5mb2ZyYW1lDQo+ID4gKmRybV9p
bmZvZnJhbWUsDQo+ID4gKwkJCQkJIHN0cnVjdCBkcF9zZHAgKnNkcCwNCj4gPiArCQkJCQkgc2l6
ZV90IHNpemUpDQo+ID4gK3sNCj4gPiArCXNpemVfdCBsZW5ndGggPSBzaXplb2Yoc3RydWN0IGRw
X3NkcCk7DQo+ID4gKwljb25zdCBpbnQgaW5mb2ZyYW1lX3NpemUgPSBIRE1JX0lORk9GUkFNRV9I
RUFERVJfU0laRSArDQo+ID4gSERNSV9EUk1fSU5GT0ZSQU1FX1NJWkU7DQo+ID4gKwl1bnNpZ25l
ZCBjaGFyIGJ1ZltIRE1JX0lORk9GUkFNRV9IRUFERVJfU0laRSArDQo+ID4gSERNSV9EUk1fSU5G
T0ZSQU1FX1NJWkVdOw0KPiA+ICsJc3NpemVfdCBsZW47DQo+ID4gKw0KPiA+ICsJaWYgKHNpemUg
PCBsZW5ndGgpDQo+ID4gKwkJcmV0dXJuIC1FTk9TUEM7DQo+ID4gKw0KPiA+ICsJbWVtc2V0KHNk
cCwgMCwgc2l6ZSk7DQo+ID4gKw0KPiA+ICsJbGVuID0gaGRtaV9kcm1faW5mb2ZyYW1lX3BhY2tf
b25seShkcm1faW5mb2ZyYW1lLCBidWYsDQo+ID4gc2l6ZW9mKGJ1ZikpOw0KPiA+ICsJaWYgKGxl
biA8IDApIHsNCj4gPiArCQlEUk1fREVCVUdfS01TKCJidWZmZXIgc2l6ZSBpcyBzbWFsbGVyIHRo
YW4gaGRyIG1ldGFkYXRhDQo+ID4gaW5mb2ZyYW1lXG4iKTsNCj4gPiArCQlyZXR1cm4gLUVOT1NQ
QzsNCj4gPiArCX0NCj4gPiArDQo+ID4gKwlpZiAobGVuICE9IGluZm9mcmFtZV9zaXplKSB7DQo+
ID4gKwkJRFJNX0RFQlVHX0tNUygid3Jvbmcgc3RhdGljIGhkciBtZXRhZGF0YSBzaXplXG4iKTsN
Cj4gPiArCQlyZXR1cm4gLUVOT1NQQzsNCj4gPiArCX0NCj4gPiArDQo+ID4gKwkvKg0KPiA+ICsJ
ICogU2V0IHVwIHRoZSBpbmZvZnJhbWUgc2RwIHBhY2tldCBmb3IgSERSIHN0YXRpYyBtZXRhZGF0
YS4NCj4gPiArCSAqIFByZXBhcmUgVlNDIEhlYWRlciBmb3IgU1UgYXMgcGVyIERQIDEuNGEgc3Bl
YywNCj4gPiArCSAqIFRhYmxlIDItMTAwIGFuZCBUYWJsZSAyLTEwMQ0KPiA+ICsJICovDQo+ID4g
Kw0KPiA+ICsJLyogU2Vjb25kYXJ5LURhdGEgUGFja2V0IElELCAwMGggZm9yIG5vbi1BdWRpbyBJ
TkZPRlJBTUUgKi8NCj4gPiArCXNkcC0+c2RwX2hlYWRlci5IQjAgPSAwOw0KPiA+ICsJLyoNCj4g
PiArCSAqIFBhY2tldCBUeXBlIDgwaCArIE5vbi1hdWRpbyBJTkZPRlJBTUUgVHlwZSB2YWx1ZQ0K
PiA+ICsJICogSERNSV9JTkZPRlJBTUVfVFlQRV9EUk06IDB4ODcNCj4gPiArCSAqIC0gODBoICsg
Tm9uLWF1ZGlvIElORk9GUkFNRSBUeXBlIHZhbHVlDQo+ID4gKwkgKiAtIEluZm9GcmFtZSBUeXBl
OiAweDA3DQo+ID4gKwkgKiAgICBbQ1RBLTg2MS1HIFRhYmxlLTQyIER5bmFtaWMgUmFuZ2UgYW5k
IE1hc3RlcmluZw0KPiA+IEluZm9GcmFtZV0NCj4gPiArCSAqLw0KPiA+ICsJc2RwLT5zZHBfaGVh
ZGVyLkhCMSA9IGRybV9pbmZvZnJhbWUtPnR5cGU7DQo+ID4gKwkvKg0KPiA+ICsJICogTGVhc3Qg
U2lnbmlmaWNhbnQgRWlnaHQgQml0cyBvZiAoRGF0YSBCeXRlIENvdW50IOKAkyAxKQ0KPiA+ICsJ
ICogaW5mb2ZyYW1lX3NpemUgLSAxDQo+ID4gKwkgKi8NCj4gPiArCXNkcC0+c2RwX2hlYWRlci5I
QjIgPSAweDFEOw0KPiA+ICsJLyogSU5GT0ZSQU1FIFNEUCBWZXJzaW9uIE51bWJlciAqLw0KPiA+
ICsJc2RwLT5zZHBfaGVhZGVyLkhCMyA9ICgweDEzIDw8IDIpOw0KPiA+ICsJLyogQ1RBIEhlYWRl
ciBCeXRlIDIgKElORk9GUkFNRSBWZXJzaW9uIE51bWJlcikgKi8NCj4gPiArCXNkcC0+ZGJbMF0g
PSBkcm1faW5mb2ZyYW1lLT52ZXJzaW9uOw0KPiA+ICsJLyogQ1RBIEhlYWRlciBCeXRlIDMgKExl
bmd0aCBvZiBJTkZPRlJBTUUpOg0KPiA+IEhETUlfRFJNX0lORk9GUkFNRV9TSVpFICovDQo+ID4g
KwlzZHAtPmRiWzFdID0gZHJtX2luZm9mcmFtZS0+bGVuZ3RoOw0KPiA+ICsJLyoNCj4gPiArCSAq
IENvcHkgSERNSV9EUk1fSU5GT0ZSQU1FX1NJWkUgc2l6ZSBmcm9tIGEgYnVmZmVyIGFmdGVyDQo+
IA0KPiBDb21tZW50IExvb2tzIGluY29tcGxldGUuDQo+IA0KSSBtaXNzZWQgc29tZSBjb21tZW50
cywgSSdsbCB1cGRhdGUgaXQuDQo+ID4gKwkgKi8NCj4gPiArCUJVSUxEX0JVR19PTihzaXplb2Yo
c2RwLT5kYikgPCBIRE1JX0RSTV9JTkZPRlJBTUVfU0laRSArIDIpOw0KPiA+ICsJbWVtY3B5KCZz
ZHAtPmRiWzJdLCAmYnVmW0hETUlfSU5GT0ZSQU1FX0hFQURFUl9TSVpFXSwNCj4gPiArCSAgICAg
ICBIRE1JX0RSTV9JTkZPRlJBTUVfU0laRSk7DQo+ID4gKw0KPiA+ICsJLyoNCj4gPiArCSAqIFNp
emUgb2YgRFAgaW5mb2ZyYW1lIHNkcCBwYWNrZXQgZm9yIEhEUiBzdGF0aWMgbWV0YWRhdGEgaXMN
Cj4gPiBjb25zaXN0IG9mDQo+IA0KPiBEcm9wICJpcyINCj4gDQpJbmNsdWRlcyB0aGlzLCBJJ2xs
IHBvbGlzaCBwb2xpc2ggY29tbWl0IG1lc3NhZ2UgYW5kIGNvbW1lbnRzLg0KDQo+ID4gKwkgKiAt
IERQIFNEUCBIZWFkZXIoc3RydWN0IGRwX3NkcF9oZWFkZXIpOiA0IGJ5dGVzDQo+ID4gKwkgKiAt
IFR3byBEYXRhIEJsb2NrczogMiBieXRlcw0KPiA+ICsJICogICAgQ1RBIEhlYWRlciBCeXRlMiAo
SU5GT0ZSQU1FIFZlcnNpb24gTnVtYmVyKQ0KPiA+ICsJICogICAgQ1RBIEhlYWRlciBCeXRlMyAo
TGVuZ3RoIG9mIElORk9GUkFNRSkNCj4gPiArCSAqIC0gSERNSV9EUk1fSU5GT0ZSQU1FX1NJWkU6
IDI2IGJ5dGVzDQo+ID4gKwkgKg0KPiA+ICsJICogUHJpb3IgdG8gR0VOMTEncyBHTVAgcmVnaXN0
ZXIgc2l6ZSBpcyBpZGVudGljYWwgdG8gRFAgSERSDQo+ID4gc3RhdGljIG1ldGFkYXRhDQo+ID4g
KwkgKiBpbmZvZnJhbWUgc2l6ZS4gQnV0IEdFTjExKyBoYXMgbGFyZ2VyIHRoYW4gdGhhdCBzaXpl
LA0KPiA+IHdyaXRlX2luZm9mcmFtZQ0KPiA+ICsJICogd2lsbCBwYWQgcmVzdCBvZiB0aGUgc2l6
ZS4NCj4gPiArCSAqLw0KPiA+ICsJcmV0dXJuIHNpemVvZihzdHJ1Y3QgZHBfc2RwX2hlYWRlcikg
KyAyICsNCj4gPiBIRE1JX0RSTV9JTkZPRlJBTUVfU0laRTsgfQ0KPiA+ICsNCj4gPiArc3RhdGlj
IHZvaWQgaW50ZWxfd3JpdGVfZHBfc2RwKHN0cnVjdCBpbnRlbF9lbmNvZGVyICplbmNvZGVyLA0K
PiA+ICsJCQkgICAgICAgY29uc3Qgc3RydWN0IGludGVsX2NydGNfc3RhdGUNCj4gPiAqY3J0Y19z
dGF0ZSwNCj4gPiArCQkJICAgICAgIHVuc2lnbmVkIGludCB0eXBlKQ0KPiA+ICt7DQo+ID4gKwlz
dHJ1Y3QgaW50ZWxfZGlnaXRhbF9wb3J0ICppbnRlbF9kaWdfcG9ydCA9DQo+ID4gZW5jX3RvX2Rp
Z19wb3J0KGVuY29kZXIpOw0KPiA+ICsJc3RydWN0IGRwX3NkcCBzZHAgPSB7fTsNCj4gPiArCXNz
aXplX3QgbGVuOw0KPiA+ICsNCj4gPiArCWlmICgoY3J0Y19zdGF0ZS0+aW5mb2ZyYW1lcy5lbmFi
bGUgJg0KPiA+ICsJICAgICBpbnRlbF9oZG1pX2luZm9mcmFtZV9lbmFibGUodHlwZSkpID09IDAp
DQo+ID4gKwkJcmV0dXJuOw0KPiA+ICsNCj4gPiArCXN3aXRjaCAodHlwZSkgew0KPiA+ICsJY2Fz
ZSBEUF9TRFBfVlNDOg0KPiA+ICsJCWxlbiA9IGludGVsX2RwX3ZzY19zZHBfcGFjaygmY3J0Y19z
dGF0ZS0NCj4gPiA+aW5mb2ZyYW1lcy52c2MsICZzZHAsDQo+ID4gKwkJCQkJICAgIHNpemVvZihz
ZHApKTsNCj4gPiArCQlicmVhazsNCj4gPiArCWNhc2UgSERNSV9QQUNLRVRfVFlQRV9HQU1VVF9N
RVRBREFUQToNCj4gPiArCQlsZW4gPQ0KPiA+IGludGVsX2RwX2hkcl9tZXRhZGF0YV9pbmZvZnJh
bWVfc2RwX3BhY2soJmNydGNfc3RhdGUtDQo+ID4gPiBpbmZvZnJhbWVzLmRybS5kcm0sDQo+ID4g
KwkJCQkJCQkgICAgICAgJnNkcCwNCj4gPiBzaXplb2Yoc2RwKSk7DQo+ID4gKwkJYnJlYWs7DQo+
ID4gKwlkZWZhdWx0Og0KPiA+ICsJCU1JU1NJTkdfQ0FTRSh0eXBlKTsNCj4gPiArCQlicmVhazsN
Cj4gPiArCX0NCj4gPiArDQo+ID4gKwlpZiAoV0FSTl9PTihsZW4gPCAwKSkNCj4gPiArCQlyZXR1
cm47DQo+ID4gKw0KPiA+ICsJaW50ZWxfZGlnX3BvcnQtPndyaXRlX2luZm9mcmFtZShlbmNvZGVy
LCBjcnRjX3N0YXRlLCB0eXBlLA0KPiA+ICZzZHAsIGxlbik7DQo+ID4gK30NCj4gPiArDQo+ID4g
K3ZvaWQgaW50ZWxfZHBfc2V0X2luZm9mcmFtZXMoc3RydWN0IGludGVsX2VuY29kZXIgKmVuY29k
ZXIsDQo+ID4gKwkJCSAgICAgYm9vbCBlbmFibGUsDQo+ID4gKwkJCSAgICAgY29uc3Qgc3RydWN0
IGludGVsX2NydGNfc3RhdGUgKmNydGNfc3RhdGUsDQo+ID4gKwkJCSAgICAgY29uc3Qgc3RydWN0
IGRybV9jb25uZWN0b3Jfc3RhdGUNCj4gPiAqY29ubl9zdGF0ZSkgew0KPiA+ICsJc3RydWN0IGRy
bV9pOTE1X3ByaXZhdGUgKmRldl9wcml2ID0gdG9faTkxNShlbmNvZGVyLT5iYXNlLmRldik7DQo+
ID4gKwlzdHJ1Y3QgaW50ZWxfZHAgKmludGVsX2RwID0gZW5jX3RvX2ludGVsX2RwKGVuY29kZXIp
Ow0KPiA+ICsJaTkxNV9yZWdfdCByZWcgPSBIU1dfVFZJREVPX0RJUF9DVEwoY3J0Y19zdGF0ZS0N
Cj4gPiA+Y3B1X3RyYW5zY29kZXIpOw0KPiA+ICsJdTMyIGRpcF9lbmFibGUgPSBWSURFT19ESVBf
RU5BQkxFX0FWSV9IU1cgfA0KPiA+IFZJREVPX0RJUF9FTkFCTEVfR0NQX0hTVyB8DQo+ID4gKwkJ
CSBWSURFT19ESVBfRU5BQkxFX1ZTX0hTVyB8DQo+ID4gVklERU9fRElQX0VOQUJMRV9HTVBfSFNX
IHwNCj4gPiArCQkJIFZJREVPX0RJUF9FTkFCTEVfU1BEX0hTVyB8DQo+ID4gVklERU9fRElQX0VO
QUJMRV9EUk1fR0xLOw0KPiA+ICsJdTMyIHZhbCA9IEk5MTVfUkVBRChyZWcpOw0KPiA+ICsNCj4g
PiArCS8qIFRPRE86IEFkZCBEU0MgY2FzZSAoRElQX0VOQUJMRV9QUFMpICovDQo+ID4gKwkvKiBX
aGVuIFBTUiBpcyBlbmFibGVkLCB0aGlzIHJvdXRpbmUgZG9lc24ndCBkaXNhYmxlIFZTQyBESVAg
Ki8NCj4gPiArCWlmIChpbnRlbF9wc3JfZW5hYmxlZChpbnRlbF9kcCkpDQo+ID4gKwkJdmFsICY9
IH5kaXBfZW5hYmxlOw0KPiA+ICsJZWxzZQ0KPiA+ICsJCXZhbCAmPSB+KGRpcF9lbmFibGUgfCBW
SURFT19ESVBfRU5BQkxFX1ZTQ19IU1cpOw0KPiANCj4gZGlwX2VuYWJsZSBoYXMgVklERU9fRElQ
X0VOQUJMRV9WU0NfSFNXIGFscmVhZHkgaW4gaXQuIFBsZWFzZSBmaXgNCj4gdGhpcy4NCj4gDQpE
ZWNsYXJpbmcgb2YgZGlwX2VuYWJsZSBkb2VzIG5vdCBpbmNsdWRlIFZJREVPX0RJUF9FTkFCTEVf
VlNDX0hTVy4NCnRoZXJlZm9yZSB3ZSBuZWVkIGl0IGhlcmUgdG8gZGlzYWJsZSBWU0MgU0RQIERJ
UC4NCg0KPiA+ICsNCj4gPiArCWlmICghZW5hYmxlKSB7DQo+ID4gKwkJSTkxNV9XUklURShyZWcs
IHZhbCk7DQo+ID4gKwkJUE9TVElOR19SRUFEKHJlZyk7DQo+ID4gKwkJcmV0dXJuOw0KPiA+ICsJ
fQ0KPiA+ICsNCj4gPiArCUk5MTVfV1JJVEUocmVnLCB2YWwpOw0KPiA+ICsJUE9TVElOR19SRUFE
KHJlZyk7DQo+ID4gKw0KPiA+ICsJLyogV2hlbiBQU1IgaXMgZW5hYmxlZCwgVlNDIFNEUCBpcyBo
YW5kbGVkIGJ5IFBTUiByb3V0aW5lICovDQo+ID4gKwlpZiAoIWludGVsX3Bzcl9lbmFibGVkKGlu
dGVsX2RwKSkNCj4gPiArCQlpbnRlbF93cml0ZV9kcF9zZHAoZW5jb2RlciwgY3J0Y19zdGF0ZSwg
RFBfU0RQX1ZTQyk7DQo+ID4gKw0KPiA+ICsJaW50ZWxfd3JpdGVfZHBfc2RwKGVuY29kZXIsIGNy
dGNfc3RhdGUsDQo+ID4gK0hETUlfUEFDS0VUX1RZUEVfR0FNVVRfTUVUQURBVEEpOyB9DQo+ID4g
Kw0KPiA+ICBzdGF0aWMgdm9pZA0KPiA+ICBpbnRlbF9kcF9zZXR1cF92c2Nfc2RwKHN0cnVjdCBp
bnRlbF9kcCAqaW50ZWxfZHAsDQo+ID4gIAkJICAgICAgIGNvbnN0IHN0cnVjdCBpbnRlbF9jcnRj
X3N0YXRlICpjcnRjX3N0YXRlLCBkaWZmDQo+ID4gLS1naXQNCj4gPiBhL2RyaXZlcnMvZ3B1L2Ry
bS9pOTE1L2Rpc3BsYXkvaW50ZWxfZHAuaA0KPiA+IGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlz
cGxheS9pbnRlbF9kcC5oDQo+ID4gaW5kZXggM2RhMTY2MDU0Nzg4Li4wZGMwOWE0NjNlZTEgMTAw
NjQ0DQo+ID4gLS0tIGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9kcC5oDQo+
ID4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9kcC5oDQo+ID4gQEAg
LTExNiw2ICsxMTYsOSBAQCB2b2lkIGludGVsX2RwX3ZzY19lbmFibGUoc3RydWN0IGludGVsX2Rw
DQo+ID4gKmludGVsX2RwLCAgdm9pZA0KPiA+IGludGVsX2RwX2hkcl9tZXRhZGF0YV9lbmFibGUo
c3RydWN0IGludGVsX2RwICppbnRlbF9kcCwNCj4gPiAgCQkJCSAgY29uc3Qgc3RydWN0IGludGVs
X2NydGNfc3RhdGUNCj4gPiAqY3J0Y19zdGF0ZSwNCj4gPiAgCQkJCSAgY29uc3Qgc3RydWN0IGRy
bV9jb25uZWN0b3Jfc3RhdGUNCj4gPiAqY29ubl9zdGF0ZSk7DQo+ID4gK3ZvaWQgaW50ZWxfZHBf
c2V0X2luZm9mcmFtZXMoc3RydWN0IGludGVsX2VuY29kZXIgKmVuY29kZXIsIGJvb2wNCj4gPiBl
bmFibGUsDQo+ID4gKwkJCSAgICAgY29uc3Qgc3RydWN0IGludGVsX2NydGNfc3RhdGUgKmNydGNf
c3RhdGUsDQo+ID4gKwkJCSAgICAgY29uc3Qgc3RydWN0IGRybV9jb25uZWN0b3Jfc3RhdGUNCj4g
PiAqY29ubl9zdGF0ZSk7DQo+ID4gIGJvb2wgaW50ZWxfZGlnaXRhbF9wb3J0X2Nvbm5lY3RlZChz
dHJ1Y3QgaW50ZWxfZW5jb2RlciAqZW5jb2Rlcik7DQo+ID4gDQo+ID4gIHN0YXRpYyBpbmxpbmUg
dW5zaWduZWQgaW50IGludGVsX2RwX3VudXNlZF9sYW5lX21hc2soaW50DQo+ID4gbGFuZV9jb3Vu
dCkNCj4gPiAtLQ0KPiA+IDIuMjQuMQ0KPiA+IA0KPiA+IF9fX19fX19fX19fX19fX19fX19fX19f
X19fX19fX19fX19fX19fX19fX19fX19fDQo+ID4gZHJpLWRldmVsIG1haWxpbmcgbGlzdA0KPiA+
IGRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcNCj4gPiBodHRwczovL2xpc3RzLmZyZWVk
ZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2RyaS1kZXZlbA0K

Re: [PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs (Secondary Data Packet)

[Mun, Gwan-gyeong]

On Wed, 2020-02-05 at 21:39 +0530, Shankar, Uma wrote:
> > -----Original Message-----
> > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf
> > Of Gwan-
> > gyeong Mun
> > Sent: Tuesday, February 4, 2020 4:50 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> > Subject: [PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs
> > (Secondary Data
> > Packet)
> 
> Drop things in (), not needed.
> 
> > It adds routines that write DP VSC SDP and DP HDR Metadata
> > Infoframe SDP.
> > In order to pack DP VSC SDP, it adds intel_dp_vsc_sdp_pack()
> > function.
> > It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and
> > [Table 2-117: VSC
> > SDP Payload for DB16 through DB18]
> > 
> > In order to pack DP HDR Metadata Infoframe SDP, it adds
> > intel_dp_hdr_metadata_infoframe_sdp_pack() function.
> > And it follows DP 1.4a spec.
> > ([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and [Table 2-126:
> > INFOFRAME
> > SDP v1.2 Payload Data Bytes - DB0 through DB31]) and CTA-861-G
> > spec. [Table-42
> > Dynamic Range and Mastering InfoFrame].
> > 
> > A machanism and a naming rule of intel_dp_set_infoframes() function
> > references
> 
> Typo in mechanism.
> 
> > intel_encoder->set_infoframes() of intel_hdmi.c .
> > VSC SDP is used for PSR and Pixel Encoding and Colorimetry Formats
> > cases.
> > Because PSR routine has its own routine of writing a VSC SDP, when
> > the PSR is
> > enabled, intel_dp_set_infoframes() does not write a VSC SDP.
> > 
> > v3:
> >   - Explicitly disable unused DIPs (AVI, GCP, VS, SPD, DRM. They
> > will be
> >     used for HDMI), when intel_dp_set_infoframes() function will be
> > called.
> >   - Replace a structure name to drm_dp_vsc_sdp from
> > intel_dp_vsc_sdp.
> > 
> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c | 194
> > ++++++++++++++++++++++++
> >  drivers/gpu/drm/i915/display/intel_dp.h |   3 +
> >  2 files changed, 197 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index b265b5c599f2..dd7e5588001e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -4731,6 +4731,200 @@ intel_dp_needs_vsc_sdp(const struct
> > intel_crtc_state
> > *crtc_state,
> >  	return false;
> >  }
> > 
> > +static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp
> > *vsc,
> > +				     struct dp_sdp *sdp, size_t size) {
> > +	size_t length = sizeof(struct dp_sdp);
> > +
> > +	if (size < length)
> > +		return -ENOSPC;
> > +
> > +	memset(sdp, 0, size);
> > +
> > +	/*
> > +	 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
> > +	 * VSC SDP Header Bytes
> > +	 */
> > +	sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
> > +	sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet
> > Type */
> > +	sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
> > +	sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data
> > Bytes */
> > +
> > +	/* VSC SDP Payload for DB16 through DB18 */
> > +	/* Pixel Encoding and Colorimetry Formats  */
> > +	sdp->db[16] = (vsc->colorspace & 0xf) << 4; /* DB16[7:4] */
> > +	sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
> > +
> > +	switch (vsc->bpc) {
> > +	case 8:
> > +		sdp->db[17] = 0x1; /* DB17[3:0] */
> > +		break;
> > +	case 10:
> > +		sdp->db[17] = 0x2;
> > +		break;
> > +	case 12:
> > +		sdp->db[17] = 0x3;
> > +		break;
> > +	case 16:
> > +		sdp->db[17] = 0x4;
> > +		break;
> > +	default:
> > +		MISSING_CASE(vsc->bpc);
> 
> 6bpc is not handled here, add that as well.
> 
Yes, I missed 6bpc case, I'll update it.
> > +		break;
> > +	}
> > +	/* Dynamic Range and Component Bit Depth */
> > +	if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
> > +		sdp->db[17] |= 0x80;  /* DB17[7] */
> > +
> > +	/* Content Type */
> > +	sdp->db[18] = vsc->content_type & 0x7;
> > +
> > +	return length;
> > +}
> > +
> > +static ssize_t
> > +intel_dp_hdr_metadata_infoframe_sdp_pack(const struct
> > hdmi_drm_infoframe
> > *drm_infoframe,
> > +					 struct dp_sdp *sdp,
> > +					 size_t size)
> > +{
> > +	size_t length = sizeof(struct dp_sdp);
> > +	const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE +
> > HDMI_DRM_INFOFRAME_SIZE;
> > +	unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE +
> > HDMI_DRM_INFOFRAME_SIZE];
> > +	ssize_t len;
> > +
> > +	if (size < length)
> > +		return -ENOSPC;
> > +
> > +	memset(sdp, 0, size);
> > +
> > +	len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf,
> > sizeof(buf));
> > +	if (len < 0) {
> > +		DRM_DEBUG_KMS("buffer size is smaller than hdr metadata
> > infoframe\n");
> > +		return -ENOSPC;
> > +	}
> > +
> > +	if (len != infoframe_size) {
> > +		DRM_DEBUG_KMS("wrong static hdr metadata size\n");
> > +		return -ENOSPC;
> > +	}
> > +
> > +	/*
> > +	 * Set up the infoframe sdp packet for HDR static metadata.
> > +	 * Prepare VSC Header for SU as per DP 1.4a spec,
> > +	 * Table 2-100 and Table 2-101
> > +	 */
> > +
> > +	/* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
> > +	sdp->sdp_header.HB0 = 0;
> > +	/*
> > +	 * Packet Type 80h + Non-audio INFOFRAME Type value
> > +	 * HDMI_INFOFRAME_TYPE_DRM: 0x87
> > +	 * - 80h + Non-audio INFOFRAME Type value
> > +	 * - InfoFrame Type: 0x07
> > +	 *    [CTA-861-G Table-42 Dynamic Range and Mastering
> > InfoFrame]
> > +	 */
> > +	sdp->sdp_header.HB1 = drm_infoframe->type;
> > +	/*
> > +	 * Least Significant Eight Bits of (Data Byte Count – 1)
> > +	 * infoframe_size - 1
> > +	 */
> > +	sdp->sdp_header.HB2 = 0x1D;
> > +	/* INFOFRAME SDP Version Number */
> > +	sdp->sdp_header.HB3 = (0x13 << 2);
> > +	/* CTA Header Byte 2 (INFOFRAME Version Number) */
> > +	sdp->db[0] = drm_infoframe->version;
> > +	/* CTA Header Byte 3 (Length of INFOFRAME):
> > HDMI_DRM_INFOFRAME_SIZE */
> > +	sdp->db[1] = drm_infoframe->length;
> > +	/*
> > +	 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
> 
> Comment Looks incomplete.
> 
I missed some comments, I'll update it.
> > +	 */
> > +	BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
> > +	memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
> > +	       HDMI_DRM_INFOFRAME_SIZE);
> > +
> > +	/*
> > +	 * Size of DP infoframe sdp packet for HDR static metadata is
> > consist of
> 
> Drop "is"
> 
Includes this, I'll polish polish commit message and comments.

> > +	 * - DP SDP Header(struct dp_sdp_header): 4 bytes
> > +	 * - Two Data Blocks: 2 bytes
> > +	 *    CTA Header Byte2 (INFOFRAME Version Number)
> > +	 *    CTA Header Byte3 (Length of INFOFRAME)
> > +	 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
> > +	 *
> > +	 * Prior to GEN11's GMP register size is identical to DP HDR
> > static metadata
> > +	 * infoframe size. But GEN11+ has larger than that size,
> > write_infoframe
> > +	 * will pad rest of the size.
> > +	 */
> > +	return sizeof(struct dp_sdp_header) + 2 +
> > HDMI_DRM_INFOFRAME_SIZE; }
> > +
> > +static void intel_write_dp_sdp(struct intel_encoder *encoder,
> > +			       const struct intel_crtc_state
> > *crtc_state,
> > +			       unsigned int type)
> > +{
> > +	struct intel_digital_port *intel_dig_port =
> > enc_to_dig_port(encoder);
> > +	struct dp_sdp sdp = {};
> > +	ssize_t len;
> > +
> > +	if ((crtc_state->infoframes.enable &
> > +	     intel_hdmi_infoframe_enable(type)) == 0)
> > +		return;
> > +
> > +	switch (type) {
> > +	case DP_SDP_VSC:
> > +		len = intel_dp_vsc_sdp_pack(&crtc_state-
> > >infoframes.vsc, &sdp,
> > +					    sizeof(sdp));
> > +		break;
> > +	case HDMI_PACKET_TYPE_GAMUT_METADATA:
> > +		len =
> > intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state-
> > > infoframes.drm.drm,
> > +							       &sdp,
> > sizeof(sdp));
> > +		break;
> > +	default:
> > +		MISSING_CASE(type);
> > +		break;
> > +	}
> > +
> > +	if (WARN_ON(len < 0))
> > +		return;
> > +
> > +	intel_dig_port->write_infoframe(encoder, crtc_state, type,
> > &sdp, len);
> > +}
> > +
> > +void intel_dp_set_infoframes(struct intel_encoder *encoder,
> > +			     bool enable,
> > +			     const struct intel_crtc_state *crtc_state,
> > +			     const struct drm_connector_state
> > *conn_state) {
> > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > +	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state-
> > >cpu_transcoder);
> > +	u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW |
> > VIDEO_DIP_ENABLE_GCP_HSW |
> > +			 VIDEO_DIP_ENABLE_VS_HSW |
> > VIDEO_DIP_ENABLE_GMP_HSW |
> > +			 VIDEO_DIP_ENABLE_SPD_HSW |
> > VIDEO_DIP_ENABLE_DRM_GLK;
> > +	u32 val = I915_READ(reg);
> > +
> > +	/* TODO: Add DSC case (DIP_ENABLE_PPS) */
> > +	/* When PSR is enabled, this routine doesn't disable VSC DIP */
> > +	if (intel_psr_enabled(intel_dp))
> > +		val &= ~dip_enable;
> > +	else
> > +		val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
> 
> dip_enable has VIDEO_DIP_ENABLE_VSC_HSW already in it. Please fix
> this.
> 
Declaring of dip_enable does not include VIDEO_DIP_ENABLE_VSC_HSW.
therefore we need it here to disable VSC SDP DIP.

> > +
> > +	if (!enable) {
> > +		I915_WRITE(reg, val);
> > +		POSTING_READ(reg);
> > +		return;
> > +	}
> > +
> > +	I915_WRITE(reg, val);
> > +	POSTING_READ(reg);
> > +
> > +	/* When PSR is enabled, VSC SDP is handled by PSR routine */
> > +	if (!intel_psr_enabled(intel_dp))
> > +		intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
> > +
> > +	intel_write_dp_sdp(encoder, crtc_state,
> > +HDMI_PACKET_TYPE_GAMUT_METADATA); }
> > +
> >  static void
> >  intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
> >  		       const struct intel_crtc_state *crtc_state, diff
> > --git
> > a/drivers/gpu/drm/i915/display/intel_dp.h
> > b/drivers/gpu/drm/i915/display/intel_dp.h
> > index 3da166054788..0dc09a463ee1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > @@ -116,6 +116,9 @@ void intel_dp_vsc_enable(struct intel_dp
> > *intel_dp,  void
> > intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
> >  				  const struct intel_crtc_state
> > *crtc_state,
> >  				  const struct drm_connector_state
> > *conn_state);
> > +void intel_dp_set_infoframes(struct intel_encoder *encoder, bool
> > enable,
> > +			     const struct intel_crtc_state *crtc_state,
> > +			     const struct drm_connector_state
> > *conn_state);
> >  bool intel_digital_port_connected(struct intel_encoder *encoder);
> > 
> >  static inline unsigned int intel_dp_unused_lane_mask(int
> > lane_count)
> > --
> > 2.24.1
> > 
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Intel-gfx] [PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs (Secondary Data Packet)

[Mun, Gwan-gyeong]

On Wed, 2020-02-05 at 21:39 +0530, Shankar, Uma wrote:
> > -----Original Message-----
> > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf
> > Of Gwan-
> > gyeong Mun
> > Sent: Tuesday, February 4, 2020 4:50 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> > Subject: [PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs
> > (Secondary Data
> > Packet)
> 
> Drop things in (), not needed.
> 
> > It adds routines that write DP VSC SDP and DP HDR Metadata
> > Infoframe SDP.
> > In order to pack DP VSC SDP, it adds intel_dp_vsc_sdp_pack()
> > function.
> > It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and
> > [Table 2-117: VSC
> > SDP Payload for DB16 through DB18]
> > 
> > In order to pack DP HDR Metadata Infoframe SDP, it adds
> > intel_dp_hdr_metadata_infoframe_sdp_pack() function.
> > And it follows DP 1.4a spec.
> > ([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and [Table 2-126:
> > INFOFRAME
> > SDP v1.2 Payload Data Bytes - DB0 through DB31]) and CTA-861-G
> > spec. [Table-42
> > Dynamic Range and Mastering InfoFrame].
> > 
> > A machanism and a naming rule of intel_dp_set_infoframes() function
> > references
> 
> Typo in mechanism.
> 
> > intel_encoder->set_infoframes() of intel_hdmi.c .
> > VSC SDP is used for PSR and Pixel Encoding and Colorimetry Formats
> > cases.
> > Because PSR routine has its own routine of writing a VSC SDP, when
> > the PSR is
> > enabled, intel_dp_set_infoframes() does not write a VSC SDP.
> > 
> > v3:
> >   - Explicitly disable unused DIPs (AVI, GCP, VS, SPD, DRM. They
> > will be
> >     used for HDMI), when intel_dp_set_infoframes() function will be
> > called.
> >   - Replace a structure name to drm_dp_vsc_sdp from
> > intel_dp_vsc_sdp.
> > 
> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c | 194
> > ++++++++++++++++++++++++
> >  drivers/gpu/drm/i915/display/intel_dp.h |   3 +
> >  2 files changed, 197 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index b265b5c599f2..dd7e5588001e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -4731,6 +4731,200 @@ intel_dp_needs_vsc_sdp(const struct
> > intel_crtc_state
> > *crtc_state,
> >  	return false;
> >  }
> > 
> > +static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp
> > *vsc,
> > +				     struct dp_sdp *sdp, size_t size) {
> > +	size_t length = sizeof(struct dp_sdp);
> > +
> > +	if (size < length)
> > +		return -ENOSPC;
> > +
> > +	memset(sdp, 0, size);
> > +
> > +	/*
> > +	 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
> > +	 * VSC SDP Header Bytes
> > +	 */
> > +	sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
> > +	sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet
> > Type */
> > +	sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
> > +	sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data
> > Bytes */
> > +
> > +	/* VSC SDP Payload for DB16 through DB18 */
> > +	/* Pixel Encoding and Colorimetry Formats  */
> > +	sdp->db[16] = (vsc->colorspace & 0xf) << 4; /* DB16[7:4] */
> > +	sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
> > +
> > +	switch (vsc->bpc) {
> > +	case 8:
> > +		sdp->db[17] = 0x1; /* DB17[3:0] */
> > +		break;
> > +	case 10:
> > +		sdp->db[17] = 0x2;
> > +		break;
> > +	case 12:
> > +		sdp->db[17] = 0x3;
> > +		break;
> > +	case 16:
> > +		sdp->db[17] = 0x4;
> > +		break;
> > +	default:
> > +		MISSING_CASE(vsc->bpc);
> 
> 6bpc is not handled here, add that as well.
> 
Yes, I missed 6bpc case, I'll update it.
> > +		break;
> > +	}
> > +	/* Dynamic Range and Component Bit Depth */
> > +	if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
> > +		sdp->db[17] |= 0x80;  /* DB17[7] */
> > +
> > +	/* Content Type */
> > +	sdp->db[18] = vsc->content_type & 0x7;
> > +
> > +	return length;
> > +}
> > +
> > +static ssize_t
> > +intel_dp_hdr_metadata_infoframe_sdp_pack(const struct
> > hdmi_drm_infoframe
> > *drm_infoframe,
> > +					 struct dp_sdp *sdp,
> > +					 size_t size)
> > +{
> > +	size_t length = sizeof(struct dp_sdp);
> > +	const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE +
> > HDMI_DRM_INFOFRAME_SIZE;
> > +	unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE +
> > HDMI_DRM_INFOFRAME_SIZE];
> > +	ssize_t len;
> > +
> > +	if (size < length)
> > +		return -ENOSPC;
> > +
> > +	memset(sdp, 0, size);
> > +
> > +	len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf,
> > sizeof(buf));
> > +	if (len < 0) {
> > +		DRM_DEBUG_KMS("buffer size is smaller than hdr metadata
> > infoframe\n");
> > +		return -ENOSPC;
> > +	}
> > +
> > +	if (len != infoframe_size) {
> > +		DRM_DEBUG_KMS("wrong static hdr metadata size\n");
> > +		return -ENOSPC;
> > +	}
> > +
> > +	/*
> > +	 * Set up the infoframe sdp packet for HDR static metadata.
> > +	 * Prepare VSC Header for SU as per DP 1.4a spec,
> > +	 * Table 2-100 and Table 2-101
> > +	 */
> > +
> > +	/* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
> > +	sdp->sdp_header.HB0 = 0;
> > +	/*
> > +	 * Packet Type 80h + Non-audio INFOFRAME Type value
> > +	 * HDMI_INFOFRAME_TYPE_DRM: 0x87
> > +	 * - 80h + Non-audio INFOFRAME Type value
> > +	 * - InfoFrame Type: 0x07
> > +	 *    [CTA-861-G Table-42 Dynamic Range and Mastering
> > InfoFrame]
> > +	 */
> > +	sdp->sdp_header.HB1 = drm_infoframe->type;
> > +	/*
> > +	 * Least Significant Eight Bits of (Data Byte Count – 1)
> > +	 * infoframe_size - 1
> > +	 */
> > +	sdp->sdp_header.HB2 = 0x1D;
> > +	/* INFOFRAME SDP Version Number */
> > +	sdp->sdp_header.HB3 = (0x13 << 2);
> > +	/* CTA Header Byte 2 (INFOFRAME Version Number) */
> > +	sdp->db[0] = drm_infoframe->version;
> > +	/* CTA Header Byte 3 (Length of INFOFRAME):
> > HDMI_DRM_INFOFRAME_SIZE */
> > +	sdp->db[1] = drm_infoframe->length;
> > +	/*
> > +	 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
> 
> Comment Looks incomplete.
> 
I missed some comments, I'll update it.
> > +	 */
> > +	BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
> > +	memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
> > +	       HDMI_DRM_INFOFRAME_SIZE);
> > +
> > +	/*
> > +	 * Size of DP infoframe sdp packet for HDR static metadata is
> > consist of
> 
> Drop "is"
> 
Includes this, I'll polish polish commit message and comments.

> > +	 * - DP SDP Header(struct dp_sdp_header): 4 bytes
> > +	 * - Two Data Blocks: 2 bytes
> > +	 *    CTA Header Byte2 (INFOFRAME Version Number)
> > +	 *    CTA Header Byte3 (Length of INFOFRAME)
> > +	 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
> > +	 *
> > +	 * Prior to GEN11's GMP register size is identical to DP HDR
> > static metadata
> > +	 * infoframe size. But GEN11+ has larger than that size,
> > write_infoframe
> > +	 * will pad rest of the size.
> > +	 */
> > +	return sizeof(struct dp_sdp_header) + 2 +
> > HDMI_DRM_INFOFRAME_SIZE; }
> > +
> > +static void intel_write_dp_sdp(struct intel_encoder *encoder,
> > +			       const struct intel_crtc_state
> > *crtc_state,
> > +			       unsigned int type)
> > +{
> > +	struct intel_digital_port *intel_dig_port =
> > enc_to_dig_port(encoder);
> > +	struct dp_sdp sdp = {};
> > +	ssize_t len;
> > +
> > +	if ((crtc_state->infoframes.enable &
> > +	     intel_hdmi_infoframe_enable(type)) == 0)
> > +		return;
> > +
> > +	switch (type) {
> > +	case DP_SDP_VSC:
> > +		len = intel_dp_vsc_sdp_pack(&crtc_state-
> > >infoframes.vsc, &sdp,
> > +					    sizeof(sdp));
> > +		break;
> > +	case HDMI_PACKET_TYPE_GAMUT_METADATA:
> > +		len =
> > intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state-
> > > infoframes.drm.drm,
> > +							       &sdp,
> > sizeof(sdp));
> > +		break;
> > +	default:
> > +		MISSING_CASE(type);
> > +		break;
> > +	}
> > +
> > +	if (WARN_ON(len < 0))
> > +		return;
> > +
> > +	intel_dig_port->write_infoframe(encoder, crtc_state, type,
> > &sdp, len);
> > +}
> > +
> > +void intel_dp_set_infoframes(struct intel_encoder *encoder,
> > +			     bool enable,
> > +			     const struct intel_crtc_state *crtc_state,
> > +			     const struct drm_connector_state
> > *conn_state) {
> > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > +	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state-
> > >cpu_transcoder);
> > +	u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW |
> > VIDEO_DIP_ENABLE_GCP_HSW |
> > +			 VIDEO_DIP_ENABLE_VS_HSW |
> > VIDEO_DIP_ENABLE_GMP_HSW |
> > +			 VIDEO_DIP_ENABLE_SPD_HSW |
> > VIDEO_DIP_ENABLE_DRM_GLK;
> > +	u32 val = I915_READ(reg);
> > +
> > +	/* TODO: Add DSC case (DIP_ENABLE_PPS) */
> > +	/* When PSR is enabled, this routine doesn't disable VSC DIP */
> > +	if (intel_psr_enabled(intel_dp))
> > +		val &= ~dip_enable;
> > +	else
> > +		val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
> 
> dip_enable has VIDEO_DIP_ENABLE_VSC_HSW already in it. Please fix
> this.
> 
Declaring of dip_enable does not include VIDEO_DIP_ENABLE_VSC_HSW.
therefore we need it here to disable VSC SDP DIP.

> > +
> > +	if (!enable) {
> > +		I915_WRITE(reg, val);
> > +		POSTING_READ(reg);
> > +		return;
> > +	}
> > +
> > +	I915_WRITE(reg, val);
> > +	POSTING_READ(reg);
> > +
> > +	/* When PSR is enabled, VSC SDP is handled by PSR routine */
> > +	if (!intel_psr_enabled(intel_dp))
> > +		intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
> > +
> > +	intel_write_dp_sdp(encoder, crtc_state,
> > +HDMI_PACKET_TYPE_GAMUT_METADATA); }
> > +
> >  static void
> >  intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
> >  		       const struct intel_crtc_state *crtc_state, diff
> > --git
> > a/drivers/gpu/drm/i915/display/intel_dp.h
> > b/drivers/gpu/drm/i915/display/intel_dp.h
> > index 3da166054788..0dc09a463ee1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > @@ -116,6 +116,9 @@ void intel_dp_vsc_enable(struct intel_dp
> > *intel_dp,  void
> > intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
> >  				  const struct intel_crtc_state
> > *crtc_state,
> >  				  const struct drm_connector_state
> > *conn_state);
> > +void intel_dp_set_infoframes(struct intel_encoder *encoder, bool
> > enable,
> > +			     const struct intel_crtc_state *crtc_state,
> > +			     const struct drm_connector_state
> > *conn_state);
> >  bool intel_digital_port_connected(struct intel_encoder *encoder);
> > 
> >  static inline unsigned int intel_dp_unused_lane_mask(int
> > lane_count)
> > --
> > 2.24.1
> > 
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v3 06/17] drm/i915/dp: Read out DP SDPs (Secondary Data Packet)

[Mun, Gwan-gyeong]

T24gV2VkLCAyMDIwLTAyLTA1IGF0IDIxOjU5ICswNTMwLCBTaGFua2FyLCBVbWEgd3JvdGU6DQo+
ID4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gPiBGcm9tOiBkcmktZGV2ZWwgPGRyaS1k
ZXZlbC1ib3VuY2VzQGxpc3RzLmZyZWVkZXNrdG9wLm9yZz4gT24gQmVoYWxmDQo+ID4gT2YgR3dh
bi0NCj4gPiBneWVvbmcgTXVuDQo+ID4gU2VudDogVHVlc2RheSwgRmVicnVhcnkgNCwgMjAyMCA0
OjUwIEFNDQo+ID4gVG86IGludGVsLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcNCj4gPiBDYzog
bGludXgtZmJkZXZAdmdlci5rZXJuZWwub3JnOyBkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Au
b3JnDQo+ID4gU3ViamVjdDogW1BBVENIIHYzIDA2LzE3XSBkcm0vaTkxNS9kcDogUmVhZCBvdXQg
RFAgU0RQcyAoU2Vjb25kYXJ5DQo+ID4gRGF0YSBQYWNrZXQpDQo+IA0KPiBEcm9wIHRoZSBjb250
ZW50IGluIGJyYWNrZXQuDQo+IA0KPiA+IEl0IGFkZHMgY29kZSB0byByZWFkIHRoZSBEUCBTRFBz
IGZyb20gdGhlIHZpZGVvIERJUCBhbmQgdW5wYWNrIHRoZW0NCj4gPiBpbnRvIHRoZSBjcnRjDQo+
ID4gc3RhdGUuDQo+ID4gDQo+ID4gSXQgYWRkcyByb3V0aW5lcyB0aGF0IHJlYWQgb3V0IERQIFZT
QyBTRFAgYW5kIERQIEhEUiBNZXRhZGF0YQ0KPiA+IEluZm9mcmFtZSBTRFAgSW4NCj4gPiBvcmRl
ciB0byB1bnBhY2sgRFAgVlNDIFNEUCwgaXQgYWRkcyBpbnRlbF9kcF92c2Nfc2RwX3VucGFjaygp
DQo+ID4gZnVuY3Rpb24uDQo+ID4gSXQgZm9sbG93cyBEUCAxLjRhIHNwZWMuIFtUYWJsZSAyLTEx
NjogVlNDIFNEUCBIZWFkZXIgQnl0ZXNdIGFuZA0KPiA+IFtUYWJsZSAyLTExNzogVlNDDQo+ID4g
U0RQIFBheWxvYWQgZm9yIERCMTYgdGhyb3VnaCBEQjE4XQ0KPiA+IA0KPiA+IEluIG9yZGVyIHRv
IHVucGFjayBEUCBIRFIgTWV0YWRhdGEgSW5mb2ZyYW1lIFNEUCwgaXQgYWRkcw0KPiA+IGludGVs
X2RwX2hkcl9tZXRhZGF0YV9pbmZvZnJhbWVfc2RwX3VucGFjaygpLiBBbmQgaXQgZm9sbG93cyBE
UA0KPiA+IDEuNGEgc3BlYy4NCj4gPiAoW1RhYmxlIDItMTI1OiBJTkZPRlJBTUUgU0RQIHYxLjIg
SGVhZGVyIEJ5dGVzXSBhbmQgW1RhYmxlIDItMTI2Og0KPiA+IElORk9GUkFNRQ0KPiA+IFNEUCB2
MS4yIFBheWxvYWQgRGF0YSBCeXRlcyAtIERCMCB0aHJvdWdoIERCMzFdKSBhbmQgQ1RBLTg2MS1H
DQo+ID4gc3BlYy4gW1RhYmxlLTQyDQo+ID4gRHluYW1pYyBSYW5nZSBhbmQgTWFzdGVyaW5nIElu
Zm9GcmFtZV0uDQo+ID4gDQo+ID4gQSBuYW1laW5nIHJ1bGUgYW5kIHN0eWxlIG9mIGludGVsX3Jl
YWRfZHBfc2RwKCkgZnVuY3Rpb24gcmVmZXJlbmNlcw0KPiANCj4gVHlwbyBpbiBuYW1pbmcuDQo+
IA0KPiA+IGludGVsX3JlYWRfaW5mb2ZyYW1lKCkgZnVuY3Rpb24gb2YgaW50ZWxfaGRtaS5jDQo+
ID4gDQo+ID4gdjI6IE1pbm9yIHN0eWxlIGZpeA0KPiA+IHYzOiBSZXBsYWNlIGEgc3RydWN0dXJl
IG5hbWUgdG8gZHJtX2RwX3ZzY19zZHAgZnJvbQ0KPiA+IGludGVsX2RwX3ZzY19zZHANCj4gPiAN
Cj4gPiBTaWduZWQtb2ZmLWJ5OiBHd2FuLWd5ZW9uZyBNdW4gPGd3YW4tZ3llb25nLm11bkBpbnRl
bC5jb20+DQo+ID4gLS0tDQo+ID4gIGRyaXZlcnMvZ3B1L2RybS9pOTE1L2Rpc3BsYXkvaW50ZWxf
ZHAuYyB8IDE3MA0KPiA+ICsrKysrKysrKysrKysrKysrKysrKysrKw0KPiA+ICBkcml2ZXJzL2dw
dS9kcm0vaTkxNS9kaXNwbGF5L2ludGVsX2RwLmggfCAgIDMgKw0KPiA+ICAyIGZpbGVzIGNoYW5n
ZWQsIDE3MyBpbnNlcnRpb25zKCspDQo+ID4gDQo+ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1
L2RybS9pOTE1L2Rpc3BsYXkvaW50ZWxfZHAuYw0KPiA+IGIvZHJpdmVycy9ncHUvZHJtL2k5MTUv
ZGlzcGxheS9pbnRlbF9kcC5jDQo+ID4gaW5kZXggZGQ3ZTU1ODgwMDFlLi5kNGVjZTBhODI0YzAg
MTAwNjQ0DQo+ID4gLS0tIGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9kcC5j
DQo+ID4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9kcC5jDQo+ID4g
QEAgLTQ5MjUsNiArNDkyNSwxNzYgQEAgdm9pZCBpbnRlbF9kcF9zZXRfaW5mb2ZyYW1lcyhzdHJ1
Y3QNCj4gPiBpbnRlbF9lbmNvZGVyDQo+ID4gKmVuY29kZXIsDQo+ID4gIAlpbnRlbF93cml0ZV9k
cF9zZHAoZW5jb2RlciwgY3J0Y19zdGF0ZSwNCj4gPiBIRE1JX1BBQ0tFVF9UWVBFX0dBTVVUX01F
VEFEQVRBKTsgIH0NCj4gPiANCj4gPiArc3RhdGljIGludCBpbnRlbF9kcF92c2Nfc2RwX3VucGFj
ayhzdHJ1Y3QgZHJtX2RwX3ZzY19zZHAgKnZzYywNCj4gPiArCQkJCSAgIGNvbnN0IHZvaWQgKmJ1
ZmZlciwgc2l6ZV90IHNpemUpIHsNCj4gPiArCWNvbnN0IHN0cnVjdCBkcF9zZHAgKnNkcCA9IGJ1
ZmZlcjsNCj4gPiArDQo+ID4gKwlpZiAoc2l6ZSA8IHNpemVvZihzdHJ1Y3QgZHBfc2RwKSkNCj4g
PiArCQlyZXR1cm4gLUVJTlZBTDsNCj4gPiArDQo+ID4gKwltZW1zZXQodnNjLCAwLCBzaXplKTsN
Cj4gPiArDQo+ID4gKwlpZiAoc2RwLT5zZHBfaGVhZGVyLkhCMCAhPSAwKQ0KPiA+ICsJCXJldHVy
biAtRUlOVkFMOw0KPiA+ICsNCj4gPiArCWlmIChzZHAtPnNkcF9oZWFkZXIuSEIxICE9IERQX1NE
UF9WU0MpDQo+ID4gKwkJcmV0dXJuIC1FSU5WQUw7DQo+ID4gKwl2c2MtPnNkcF90eXBlID0gc2Rw
LT5zZHBfaGVhZGVyLkhCMTsNCj4gPiArDQo+ID4gKwlpZiAoc2RwLT5zZHBfaGVhZGVyLkhCMiA9
PSAweDIgJiYgc2RwLT5zZHBfaGVhZGVyLkhCMyA9PSAweDgpIHsNCj4gPiArCQl2c2MtPnJldmlz
aW9uID0gc2RwLT5zZHBfaGVhZGVyLkhCMjsNCj4gPiArCQl2c2MtPmxlbmd0aCA9IHNkcC0+c2Rw
X2hlYWRlci5IQjM7DQo+ID4gKwl9IGVsc2UgaWYgKHNkcC0+c2RwX2hlYWRlci5IQjIgPT0gMHg0
ICYmIHNkcC0+c2RwX2hlYWRlci5IQjMgPT0NCj4gPiAweGUpIHsNCj4gPiArCQl2c2MtPnJldmlz
aW9uID0gc2RwLT5zZHBfaGVhZGVyLkhCMjsNCj4gPiArCQl2c2MtPmxlbmd0aCA9IHNkcC0+c2Rw
X2hlYWRlci5IQjM7DQo+ID4gKwl9IGVsc2UgaWYgKHNkcC0+c2RwX2hlYWRlci5IQjIgPT0gMHg1
ICYmIHNkcC0+c2RwX2hlYWRlci5IQjMgPT0NCj4gPiAweDEzKSB7DQo+ID4gKwkJdnNjLT5yZXZp
c2lvbiA9IHNkcC0+c2RwX2hlYWRlci5IQjI7DQo+ID4gKwkJdnNjLT5sZW5ndGggPSBzZHAtPnNk
cF9oZWFkZXIuSEIzOw0KPiANCj4gVGhlIGFib3ZlIDIgbGluZXMgY2FuIGJlIGRvbmUgdW5jb25k
aXRpb25hbGx5LCBtYXkgYmUgY29tYmluZSB0aGUgaWYNCj4gY2hlY2tzLg0KPiANCj4gPiArCQl2
c2MtPmNvbG9yc3BhY2UgPSAoc2RwLT5kYlsxNl0gPj4gNCkgJiAweGY7DQo+ID4gKwkJdnNjLT5j
b2xvcmltZXRyeSA9IHNkcC0+ZGJbMTZdICYgMHhmOw0KPiA+ICsJCXZzYy0+ZHluYW1pY19yYW5n
ZSA9IChzZHAtPmRiWzE3XSA+PiA3KSAmIDB4MTsNCj4gPiArDQo+ID4gKwkJc3dpdGNoIChzZHAt
PmRiWzE3XSAmIDB4Nykgew0KPiA+ICsJCWNhc2UgMHgxOg0KPiA+ICsJCQl2c2MtPmJwYyA9IDg7
DQo+ID4gKwkJCWJyZWFrOw0KPiA+ICsJCWNhc2UgMHgyOg0KPiA+ICsJCQl2c2MtPmJwYyA9IDEw
Ow0KPiA+ICsJCQlicmVhazsNCj4gPiArCQljYXNlIDB4MzoNCj4gPiArCQkJdnNjLT5icGMgPSAx
MjsNCj4gPiArCQkJYnJlYWs7DQo+ID4gKwkJY2FzZSAweDQ6DQo+ID4gKwkJCXZzYy0+YnBjID0g
MTY7DQo+ID4gKwkJCWJyZWFrOw0KPiA+ICsJCWRlZmF1bHQ6DQo+ID4gKwkJCU1JU1NJTkdfQ0FT
RShzZHAtPmRiWzE3XSAmIDB4Nyk7DQo+IA0KPiBIYW5kbGUgNmJwYyBjYXNlIGFzIHdlbGwuDQo+
IA0KWWVzLCAgSSdsbCB1cGRhdGUgZXZlcnl0aGluZyB0aGF0IHlvdSBjb21tZW50ZWQuDQo+ID4g
KwkJCXJldHVybiAtRUlOVkFMOw0KPiA+ICsJCX0NCj4gPiArDQo+ID4gKwkJdnNjLT5jb250ZW50
X3R5cGUgPSBzZHAtPmRiWzE4XSAmIDB4NzsNCj4gPiArCX0gZWxzZSB7DQo+ID4gKwkJcmV0dXJu
IC1FSU5WQUw7DQo+ID4gKwl9DQo+ID4gKw0KPiA+ICsJcmV0dXJuIDA7DQo+ID4gK30NCj4gPiAr
DQo+ID4gK3N0YXRpYyBpbnQNCj4gPiAraW50ZWxfZHBfaGRyX21ldGFkYXRhX2luZm9mcmFtZV9z
ZHBfdW5wYWNrKHN0cnVjdA0KPiA+IGhkbWlfZHJtX2luZm9mcmFtZQ0KPiA+ICpkcm1faW5mb2Zy
YW1lLA0KPiA+ICsJCQkJCSAgIGNvbnN0IHZvaWQgKmJ1ZmZlciwgc2l6ZV90DQo+ID4gc2l6ZSkg
ew0KPiA+ICsJaW50IHJldDsNCj4gPiArDQo+ID4gKwljb25zdCBzdHJ1Y3QgZHBfc2RwICpzZHAg
PSBidWZmZXI7DQo+ID4gKw0KPiA+ICsJaWYgKHNpemUgPCBzaXplb2Yoc3RydWN0IGRwX3NkcCkp
DQo+ID4gKwkJcmV0dXJuIC1FSU5WQUw7DQo+ID4gKw0KPiA+ICsJaWYgKHNkcC0+c2RwX2hlYWRl
ci5IQjAgIT0gMCkNCj4gPiArCQlyZXR1cm4gLUVJTlZBTDsNCj4gPiArDQo+ID4gKwlpZiAoc2Rw
LT5zZHBfaGVhZGVyLkhCMSAhPSBIRE1JX0lORk9GUkFNRV9UWVBFX0RSTSkNCj4gPiArCQlyZXR1
cm4gLUVJTlZBTDsNCj4gPiArDQo+ID4gKwkvKg0KPiA+ICsJICogTGVhc3QgU2lnbmlmaWNhbnQg
RWlnaHQgQml0cyBvZiAoRGF0YSBCeXRlIENvdW50IOKAkyAxKQ0KPiA+ICsJICogMURoIChpLmUu
LCBEYXRhIEJ5dGUgQ291bnQgPSAzMCBieXRlcykuDQo+ID4gKwkgKi8NCj4gPiArCWlmIChzZHAt
PnNkcF9oZWFkZXIuSEIyICE9IDB4MUQpDQo+ID4gKwkJcmV0dXJuIC1FSU5WQUw7DQo+ID4gKw0K
PiA+ICsJLyogTW9zdCBTaWduaWZpY2FudCBUd28gQml0cyBvZiAoRGF0YSBCeXRlIENvdW50IOKA
kyAxKSwgQ2xlYXIgdG8NCj4gPiAwMGIuICovDQo+ID4gKwlpZiAoKHNkcC0+c2RwX2hlYWRlci5I
QjMgJiAweDMpICE9IDApDQo+ID4gKwkJcmV0dXJuIC1FSU5WQUw7DQo+ID4gKw0KPiA+ICsJLyog
SU5GT0ZSQU1FIFNEUCBWZXJzaW9uIE51bWJlciAqLw0KPiA+ICsJaWYgKCgoc2RwLT5zZHBfaGVh
ZGVyLkhCMyA+PiAyKSAmIDB4M2YpICE9IDB4MTMpDQo+ID4gKwkJcmV0dXJuIC1FSU5WQUw7DQo+
ID4gKw0KPiA+ICsJLyogQ1RBIEhlYWRlciBCeXRlIDIgKElORk9GUkFNRSBWZXJzaW9uIE51bWJl
cikgKi8NCj4gPiArCWlmIChzZHAtPmRiWzBdICE9IDEpDQo+ID4gKwkJcmV0dXJuIC1FSU5WQUw7
DQo+ID4gKw0KPiA+ICsJLyogQ1RBIEhlYWRlciBCeXRlIDMgKExlbmd0aCBvZiBJTkZPRlJBTUUp
Og0KPiA+IEhETUlfRFJNX0lORk9GUkFNRV9TSVpFICovDQo+ID4gKwlpZiAoc2RwLT5kYlsxXSAh
PSBIRE1JX0RSTV9JTkZPRlJBTUVfU0laRSkNCj4gPiArCQlyZXR1cm4gLUVJTlZBTDsNCj4gPiAr
DQo+ID4gKwlyZXQgPSBoZG1pX2RybV9pbmZvZnJhbWVfdW5wYWNrX29ubHkoZHJtX2luZm9mcmFt
ZSwgJnNkcC0NCj4gPiA+ZGJbMl0sDQo+ID4gKwkJCQkJICAgICBIRE1JX0RSTV9JTkZPRlJBTUVf
U0laRSk7DQo+ID4gKw0KPiA+ICsJcmV0dXJuIHJldDsNCj4gPiArfQ0KPiA+ICsNCj4gPiArc3Rh
dGljIHZvaWQgaW50ZWxfcmVhZF9kcF92c2Nfc2RwKHN0cnVjdCBpbnRlbF9lbmNvZGVyICplbmNv
ZGVyLA0KPiA+ICsJCQkJICBzdHJ1Y3QgaW50ZWxfY3J0Y19zdGF0ZSAqY3J0Y19zdGF0ZSwNCj4g
PiArCQkJCSAgc3RydWN0IGRybV9kcF92c2Nfc2RwICp2c2MpDQo+ID4gK3sNCj4gPiArCXN0cnVj
dCBpbnRlbF9kaWdpdGFsX3BvcnQgKmludGVsX2RpZ19wb3J0ID0NCj4gPiBlbmNfdG9fZGlnX3Bv
cnQoZW5jb2Rlcik7DQo+ID4gKwlzdHJ1Y3QgaW50ZWxfZHAgKmludGVsX2RwID0gZW5jX3RvX2lu
dGVsX2RwKGVuY29kZXIpOw0KPiA+ICsJdW5zaWduZWQgaW50IHR5cGUgPSBEUF9TRFBfVlNDOw0K
PiA+ICsJc3RydWN0IGRwX3NkcCBzZHAgPSB7fTsNCj4gPiArCWludCByZXQ7DQo+ID4gKw0KPiA+
ICsJLyogV2hlbiBQU1IgaXMgZW5hYmxlZCwgVlNDIFNEUCBpcyBoYW5kbGVkIGJ5IFBTUiByb3V0
aW5lICovDQo+ID4gKwlpZiAoaW50ZWxfcHNyX2VuYWJsZWQoaW50ZWxfZHApKQ0KPiA+ICsJCXJl
dHVybjsNCj4gPiArDQo+ID4gKwlpZiAoKGNydGNfc3RhdGUtPmluZm9mcmFtZXMuZW5hYmxlICYN
Cj4gPiArCSAgICAgaW50ZWxfaGRtaV9pbmZvZnJhbWVfZW5hYmxlKHR5cGUpKSA9PSAwKQ0KPiA+
ICsJCXJldHVybjsNCj4gPiArDQo+ID4gKwlpbnRlbF9kaWdfcG9ydC0+cmVhZF9pbmZvZnJhbWUo
ZW5jb2RlciwgY3J0Y19zdGF0ZSwgdHlwZSwgJnNkcCwNCj4gPiArc2l6ZW9mKHNkcCkpOw0KPiA+
ICsNCj4gPiArCXJldCA9IGludGVsX2RwX3ZzY19zZHBfdW5wYWNrKHZzYywgJnNkcCwgc2l6ZW9m
KHNkcCkpOw0KPiA+ICsNCj4gPiArCWlmIChyZXQpDQo+ID4gKwkJRFJNX0RFQlVHX0tNUygiRmFp
bGVkIHRvIHVucGFjayBEUCBWU0MgU0RQXG4iKTsgfQ0KPiA+ICsNCj4gPiArc3RhdGljIHZvaWQg
aW50ZWxfcmVhZF9kcF9oZHJfbWV0YWRhdGFfaW5mb2ZyYW1lX3NkcChzdHJ1Y3QNCj4gPiBpbnRl
bF9lbmNvZGVyDQo+ID4gKmVuY29kZXIsDQo+ID4gKwkJCQkJCSAgICAgc3RydWN0DQo+ID4gaW50
ZWxfY3J0Y19zdGF0ZQ0KPiA+ICpjcnRjX3N0YXRlLA0KPiA+ICsJCQkJCQkgICAgIHN0cnVjdA0K
PiA+IGhkbWlfZHJtX2luZm9mcmFtZQ0KPiA+ICpkcm1faW5mb2ZyYW1lKSB7DQo+ID4gKwlzdHJ1
Y3QgaW50ZWxfZGlnaXRhbF9wb3J0ICppbnRlbF9kaWdfcG9ydCA9DQo+ID4gZW5jX3RvX2RpZ19w
b3J0KGVuY29kZXIpOw0KPiA+ICsJdW5zaWduZWQgaW50IHR5cGUgPSBIRE1JX1BBQ0tFVF9UWVBF
X0dBTVVUX01FVEFEQVRBOw0KPiA+ICsJc3RydWN0IGRwX3NkcCBzZHAgPSB7fTsNCj4gPiArCWlu
dCByZXQ7DQo+ID4gKw0KPiA+ICsJaWYgKChjcnRjX3N0YXRlLT5pbmZvZnJhbWVzLmVuYWJsZSAm
DQo+ID4gKwkgICAgaW50ZWxfaGRtaV9pbmZvZnJhbWVfZW5hYmxlKHR5cGUpKSA9PSAwKQ0KPiA+
ICsJCXJldHVybjsNCj4gPiArDQo+ID4gKwlpbnRlbF9kaWdfcG9ydC0+cmVhZF9pbmZvZnJhbWUo
ZW5jb2RlciwgY3J0Y19zdGF0ZSwgdHlwZSwgJnNkcCwNCj4gPiArCQkJCSAgICAgICBzaXplb2Yo
c2RwKSk7DQo+ID4gKw0KPiA+ICsJcmV0ID0gaW50ZWxfZHBfaGRyX21ldGFkYXRhX2luZm9mcmFt
ZV9zZHBfdW5wYWNrKGRybV9pbmZvZnJhbWUsDQo+ID4gJnNkcCwNCj4gPiArCQkJCQkJCSBzaXpl
b2Yoc2RwKSk7DQo+ID4gKw0KPiA+ICsJaWYgKHJldCkNCj4gPiArCQlEUk1fREVCVUdfS01TKCJG
YWlsZWQgdG8gdW5wYWNrIERQIEhEUiBNZXRhZGF0YQ0KPiA+IEluZm9mcmFtZQ0KPiA+IFNEUFxu
Iik7IH0NCj4gPiArDQo+ID4gK3ZvaWQgaW50ZWxfcmVhZF9kcF9zZHAoc3RydWN0IGludGVsX2Vu
Y29kZXIgKmVuY29kZXIsDQo+ID4gKwkJICAgICAgIHN0cnVjdCBpbnRlbF9jcnRjX3N0YXRlICpj
cnRjX3N0YXRlLA0KPiA+ICsJCSAgICAgICB1bnNpZ25lZCBpbnQgdHlwZSkNCj4gPiArew0KPiA+
ICsJc3dpdGNoICh0eXBlKSB7DQo+ID4gKwljYXNlIERQX1NEUF9WU0M6DQo+ID4gKwkJaW50ZWxf
cmVhZF9kcF92c2Nfc2RwKGVuY29kZXIsIGNydGNfc3RhdGUsDQo+ID4gKwkJCQkgICAgICAmY3J0
Y19zdGF0ZS0+aW5mb2ZyYW1lcy52c2MpOw0KPiA+ICsJCWJyZWFrOw0KPiA+ICsJY2FzZSBIRE1J
X1BBQ0tFVF9UWVBFX0dBTVVUX01FVEFEQVRBOg0KPiA+ICsJCWludGVsX3JlYWRfZHBfaGRyX21l
dGFkYXRhX2luZm9mcmFtZV9zZHAoZW5jb2RlciwNCj4gPiBjcnRjX3N0YXRlLA0KPiA+ICsJCQkJ
CQkJICZjcnRjX3N0YXRlLQ0KPiA+ID4gaW5mb2ZyYW1lcy5kcm0uZHJtKTsNCj4gPiArCQlicmVh
azsNCj4gPiArCWRlZmF1bHQ6DQo+ID4gKwkJTUlTU0lOR19DQVNFKHR5cGUpOw0KPiA+ICsJCWJy
ZWFrOw0KPiA+ICsJfQ0KPiA+ICt9DQo+ID4gKw0KPiA+ICBzdGF0aWMgdm9pZA0KPiA+ICBpbnRl
bF9kcF9zZXR1cF92c2Nfc2RwKHN0cnVjdCBpbnRlbF9kcCAqaW50ZWxfZHAsDQo+ID4gIAkJICAg
ICAgIGNvbnN0IHN0cnVjdCBpbnRlbF9jcnRjX3N0YXRlICpjcnRjX3N0YXRlLCBkaWZmDQo+ID4g
LS1naXQNCj4gPiBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2Rpc3BsYXkvaW50ZWxfZHAuaA0KPiA+
IGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9kcC5oDQo+ID4gaW5kZXggMGRj
MDlhNDYzZWUxLi5lOGY5YmE5NjJkMDkgMTAwNjQ0DQo+ID4gLS0tIGEvZHJpdmVycy9ncHUvZHJt
L2k5MTUvZGlzcGxheS9pbnRlbF9kcC5oDQo+ID4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUv
ZGlzcGxheS9pbnRlbF9kcC5oDQo+ID4gQEAgLTExOSw2ICsxMTksOSBAQCB2b2lkIGludGVsX2Rw
X2hkcl9tZXRhZGF0YV9lbmFibGUoc3RydWN0DQo+ID4gaW50ZWxfZHANCj4gPiAqaW50ZWxfZHAs
ICB2b2lkIGludGVsX2RwX3NldF9pbmZvZnJhbWVzKHN0cnVjdCBpbnRlbF9lbmNvZGVyDQo+ID4g
KmVuY29kZXIsIGJvb2wNCj4gPiBlbmFibGUsDQo+ID4gIAkJCSAgICAgY29uc3Qgc3RydWN0IGlu
dGVsX2NydGNfc3RhdGUgKmNydGNfc3RhdGUsDQo+ID4gIAkJCSAgICAgY29uc3Qgc3RydWN0IGRy
bV9jb25uZWN0b3Jfc3RhdGUNCj4gPiAqY29ubl9zdGF0ZSk7DQo+ID4gK3ZvaWQgaW50ZWxfcmVh
ZF9kcF9zZHAoc3RydWN0IGludGVsX2VuY29kZXIgKmVuY29kZXIsDQo+ID4gKwkJICAgICAgIHN0
cnVjdCBpbnRlbF9jcnRjX3N0YXRlICpjcnRjX3N0YXRlLA0KPiA+ICsJCSAgICAgICB1bnNpZ25l
ZCBpbnQgdHlwZSk7DQo+ID4gIGJvb2wgaW50ZWxfZGlnaXRhbF9wb3J0X2Nvbm5lY3RlZChzdHJ1
Y3QgaW50ZWxfZW5jb2RlciAqZW5jb2Rlcik7DQo+ID4gDQo+ID4gIHN0YXRpYyBpbmxpbmUgdW5z
aWduZWQgaW50IGludGVsX2RwX3VudXNlZF9sYW5lX21hc2soaW50DQo+ID4gbGFuZV9jb3VudCkN
Cj4gPiAtLQ0KPiA+IDIuMjQuMQ0KPiA+IA0KPiA+IF9fX19fX19fX19fX19fX19fX19fX19fX19f
X19fX19fX19fX19fX19fX19fX19fDQo+ID4gZHJpLWRldmVsIG1haWxpbmcgbGlzdA0KPiA+IGRy
aS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcNCj4gPiBodHRwczovL2xpc3RzLmZyZWVkZXNr
dG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2RyaS1kZXZlbA0K

Re: [PATCH v3 06/17] drm/i915/dp: Read out DP SDPs (Secondary Data Packet)

[Mun, Gwan-gyeong]

On Wed, 2020-02-05 at 21:59 +0530, Shankar, Uma wrote:
> > -----Original Message-----
> > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf
> > Of Gwan-
> > gyeong Mun
> > Sent: Tuesday, February 4, 2020 4:50 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> > Subject: [PATCH v3 06/17] drm/i915/dp: Read out DP SDPs (Secondary
> > Data Packet)
> 
> Drop the content in bracket.
> 
> > It adds code to read the DP SDPs from the video DIP and unpack them
> > into the crtc
> > state.
> > 
> > It adds routines that read out DP VSC SDP and DP HDR Metadata
> > Infoframe SDP In
> > order to unpack DP VSC SDP, it adds intel_dp_vsc_sdp_unpack()
> > function.
> > It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and
> > [Table 2-117: VSC
> > SDP Payload for DB16 through DB18]
> > 
> > In order to unpack DP HDR Metadata Infoframe SDP, it adds
> > intel_dp_hdr_metadata_infoframe_sdp_unpack(). And it follows DP
> > 1.4a spec.
> > ([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and [Table 2-126:
> > INFOFRAME
> > SDP v1.2 Payload Data Bytes - DB0 through DB31]) and CTA-861-G
> > spec. [Table-42
> > Dynamic Range and Mastering InfoFrame].
> > 
> > A nameing rule and style of intel_read_dp_sdp() function references
> 
> Typo in naming.
> 
> > intel_read_infoframe() function of intel_hdmi.c
> > 
> > v2: Minor style fix
> > v3: Replace a structure name to drm_dp_vsc_sdp from
> > intel_dp_vsc_sdp
> > 
> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c | 170
> > ++++++++++++++++++++++++
> >  drivers/gpu/drm/i915/display/intel_dp.h |   3 +
> >  2 files changed, 173 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index dd7e5588001e..d4ece0a824c0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -4925,6 +4925,176 @@ void intel_dp_set_infoframes(struct
> > intel_encoder
> > *encoder,
> >  	intel_write_dp_sdp(encoder, crtc_state,
> > HDMI_PACKET_TYPE_GAMUT_METADATA);  }
> > 
> > +static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
> > +				   const void *buffer, size_t size) {
> > +	const struct dp_sdp *sdp = buffer;
> > +
> > +	if (size < sizeof(struct dp_sdp))
> > +		return -EINVAL;
> > +
> > +	memset(vsc, 0, size);
> > +
> > +	if (sdp->sdp_header.HB0 != 0)
> > +		return -EINVAL;
> > +
> > +	if (sdp->sdp_header.HB1 != DP_SDP_VSC)
> > +		return -EINVAL;
> > +	vsc->sdp_type = sdp->sdp_header.HB1;
> > +
> > +	if (sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) {
> > +		vsc->revision = sdp->sdp_header.HB2;
> > +		vsc->length = sdp->sdp_header.HB3;
> > +	} else if (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 ==
> > 0xe) {
> > +		vsc->revision = sdp->sdp_header.HB2;
> > +		vsc->length = sdp->sdp_header.HB3;
> > +	} else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 ==
> > 0x13) {
> > +		vsc->revision = sdp->sdp_header.HB2;
> > +		vsc->length = sdp->sdp_header.HB3;
> 
> The above 2 lines can be done unconditionally, may be combine the if
> checks.
> 
> > +		vsc->colorspace = (sdp->db[16] >> 4) & 0xf;
> > +		vsc->colorimetry = sdp->db[16] & 0xf;
> > +		vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
> > +
> > +		switch (sdp->db[17] & 0x7) {
> > +		case 0x1:
> > +			vsc->bpc = 8;
> > +			break;
> > +		case 0x2:
> > +			vsc->bpc = 10;
> > +			break;
> > +		case 0x3:
> > +			vsc->bpc = 12;
> > +			break;
> > +		case 0x4:
> > +			vsc->bpc = 16;
> > +			break;
> > +		default:
> > +			MISSING_CASE(sdp->db[17] & 0x7);
> 
> Handle 6bpc case as well.
> 
Yes,  I'll update everything that you commented.
> > +			return -EINVAL;
> > +		}
> > +
> > +		vsc->content_type = sdp->db[18] & 0x7;
> > +	} else {
> > +		return -EINVAL;
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> > +static int
> > +intel_dp_hdr_metadata_infoframe_sdp_unpack(struct
> > hdmi_drm_infoframe
> > *drm_infoframe,
> > +					   const void *buffer, size_t
> > size) {
> > +	int ret;
> > +
> > +	const struct dp_sdp *sdp = buffer;
> > +
> > +	if (size < sizeof(struct dp_sdp))
> > +		return -EINVAL;
> > +
> > +	if (sdp->sdp_header.HB0 != 0)
> > +		return -EINVAL;
> > +
> > +	if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
> > +		return -EINVAL;
> > +
> > +	/*
> > +	 * Least Significant Eight Bits of (Data Byte Count – 1)
> > +	 * 1Dh (i.e., Data Byte Count = 30 bytes).
> > +	 */
> > +	if (sdp->sdp_header.HB2 != 0x1D)
> > +		return -EINVAL;
> > +
> > +	/* Most Significant Two Bits of (Data Byte Count – 1), Clear to
> > 00b. */
> > +	if ((sdp->sdp_header.HB3 & 0x3) != 0)
> > +		return -EINVAL;
> > +
> > +	/* INFOFRAME SDP Version Number */
> > +	if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
> > +		return -EINVAL;
> > +
> > +	/* CTA Header Byte 2 (INFOFRAME Version Number) */
> > +	if (sdp->db[0] != 1)
> > +		return -EINVAL;
> > +
> > +	/* CTA Header Byte 3 (Length of INFOFRAME):
> > HDMI_DRM_INFOFRAME_SIZE */
> > +	if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
> > +		return -EINVAL;
> > +
> > +	ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp-
> > >db[2],
> > +					     HDMI_DRM_INFOFRAME_SIZE);
> > +
> > +	return ret;
> > +}
> > +
> > +static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
> > +				  struct intel_crtc_state *crtc_state,
> > +				  struct drm_dp_vsc_sdp *vsc)
> > +{
> > +	struct intel_digital_port *intel_dig_port =
> > enc_to_dig_port(encoder);
> > +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > +	unsigned int type = DP_SDP_VSC;
> > +	struct dp_sdp sdp = {};
> > +	int ret;
> > +
> > +	/* When PSR is enabled, VSC SDP is handled by PSR routine */
> > +	if (intel_psr_enabled(intel_dp))
> > +		return;
> > +
> > +	if ((crtc_state->infoframes.enable &
> > +	     intel_hdmi_infoframe_enable(type)) == 0)
> > +		return;
> > +
> > +	intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
> > +sizeof(sdp));
> > +
> > +	ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
> > +
> > +	if (ret)
> > +		DRM_DEBUG_KMS("Failed to unpack DP VSC SDP\n"); }
> > +
> > +static void intel_read_dp_hdr_metadata_infoframe_sdp(struct
> > intel_encoder
> > *encoder,
> > +						     struct
> > intel_crtc_state
> > *crtc_state,
> > +						     struct
> > hdmi_drm_infoframe
> > *drm_infoframe) {
> > +	struct intel_digital_port *intel_dig_port =
> > enc_to_dig_port(encoder);
> > +	unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
> > +	struct dp_sdp sdp = {};
> > +	int ret;
> > +
> > +	if ((crtc_state->infoframes.enable &
> > +	    intel_hdmi_infoframe_enable(type)) == 0)
> > +		return;
> > +
> > +	intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
> > +				       sizeof(sdp));
> > +
> > +	ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe,
> > &sdp,
> > +							 sizeof(sdp));
> > +
> > +	if (ret)
> > +		DRM_DEBUG_KMS("Failed to unpack DP HDR Metadata
> > Infoframe
> > SDP\n"); }
> > +
> > +void intel_read_dp_sdp(struct intel_encoder *encoder,
> > +		       struct intel_crtc_state *crtc_state,
> > +		       unsigned int type)
> > +{
> > +	switch (type) {
> > +	case DP_SDP_VSC:
> > +		intel_read_dp_vsc_sdp(encoder, crtc_state,
> > +				      &crtc_state->infoframes.vsc);
> > +		break;
> > +	case HDMI_PACKET_TYPE_GAMUT_METADATA:
> > +		intel_read_dp_hdr_metadata_infoframe_sdp(encoder,
> > crtc_state,
> > +							 &crtc_state-
> > > infoframes.drm.drm);
> > +		break;
> > +	default:
> > +		MISSING_CASE(type);
> > +		break;
> > +	}
> > +}
> > +
> >  static void
> >  intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
> >  		       const struct intel_crtc_state *crtc_state, diff
> > --git
> > a/drivers/gpu/drm/i915/display/intel_dp.h
> > b/drivers/gpu/drm/i915/display/intel_dp.h
> > index 0dc09a463ee1..e8f9ba962d09 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > @@ -119,6 +119,9 @@ void intel_dp_hdr_metadata_enable(struct
> > intel_dp
> > *intel_dp,  void intel_dp_set_infoframes(struct intel_encoder
> > *encoder, bool
> > enable,
> >  			     const struct intel_crtc_state *crtc_state,
> >  			     const struct drm_connector_state
> > *conn_state);
> > +void intel_read_dp_sdp(struct intel_encoder *encoder,
> > +		       struct intel_crtc_state *crtc_state,
> > +		       unsigned int type);
> >  bool intel_digital_port_connected(struct intel_encoder *encoder);
> > 
> >  static inline unsigned int intel_dp_unused_lane_mask(int
> > lane_count)
> > --
> > 2.24.1
> > 
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Intel-gfx] [PATCH v3 06/17] drm/i915/dp: Read out DP SDPs (Secondary Data Packet)

[Mun, Gwan-gyeong]

On Wed, 2020-02-05 at 21:59 +0530, Shankar, Uma wrote:
> > -----Original Message-----
> > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf
> > Of Gwan-
> > gyeong Mun
> > Sent: Tuesday, February 4, 2020 4:50 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> > Subject: [PATCH v3 06/17] drm/i915/dp: Read out DP SDPs (Secondary
> > Data Packet)
> 
> Drop the content in bracket.
> 
> > It adds code to read the DP SDPs from the video DIP and unpack them
> > into the crtc
> > state.
> > 
> > It adds routines that read out DP VSC SDP and DP HDR Metadata
> > Infoframe SDP In
> > order to unpack DP VSC SDP, it adds intel_dp_vsc_sdp_unpack()
> > function.
> > It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and
> > [Table 2-117: VSC
> > SDP Payload for DB16 through DB18]
> > 
> > In order to unpack DP HDR Metadata Infoframe SDP, it adds
> > intel_dp_hdr_metadata_infoframe_sdp_unpack(). And it follows DP
> > 1.4a spec.
> > ([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and [Table 2-126:
> > INFOFRAME
> > SDP v1.2 Payload Data Bytes - DB0 through DB31]) and CTA-861-G
> > spec. [Table-42
> > Dynamic Range and Mastering InfoFrame].
> > 
> > A nameing rule and style of intel_read_dp_sdp() function references
> 
> Typo in naming.
> 
> > intel_read_infoframe() function of intel_hdmi.c
> > 
> > v2: Minor style fix
> > v3: Replace a structure name to drm_dp_vsc_sdp from
> > intel_dp_vsc_sdp
> > 
> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c | 170
> > ++++++++++++++++++++++++
> >  drivers/gpu/drm/i915/display/intel_dp.h |   3 +
> >  2 files changed, 173 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index dd7e5588001e..d4ece0a824c0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -4925,6 +4925,176 @@ void intel_dp_set_infoframes(struct
> > intel_encoder
> > *encoder,
> >  	intel_write_dp_sdp(encoder, crtc_state,
> > HDMI_PACKET_TYPE_GAMUT_METADATA);  }
> > 
> > +static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
> > +				   const void *buffer, size_t size) {
> > +	const struct dp_sdp *sdp = buffer;
> > +
> > +	if (size < sizeof(struct dp_sdp))
> > +		return -EINVAL;
> > +
> > +	memset(vsc, 0, size);
> > +
> > +	if (sdp->sdp_header.HB0 != 0)
> > +		return -EINVAL;
> > +
> > +	if (sdp->sdp_header.HB1 != DP_SDP_VSC)
> > +		return -EINVAL;
> > +	vsc->sdp_type = sdp->sdp_header.HB1;
> > +
> > +	if (sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) {
> > +		vsc->revision = sdp->sdp_header.HB2;
> > +		vsc->length = sdp->sdp_header.HB3;
> > +	} else if (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 ==
> > 0xe) {
> > +		vsc->revision = sdp->sdp_header.HB2;
> > +		vsc->length = sdp->sdp_header.HB3;
> > +	} else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 ==
> > 0x13) {
> > +		vsc->revision = sdp->sdp_header.HB2;
> > +		vsc->length = sdp->sdp_header.HB3;
> 
> The above 2 lines can be done unconditionally, may be combine the if
> checks.
> 
> > +		vsc->colorspace = (sdp->db[16] >> 4) & 0xf;
> > +		vsc->colorimetry = sdp->db[16] & 0xf;
> > +		vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
> > +
> > +		switch (sdp->db[17] & 0x7) {
> > +		case 0x1:
> > +			vsc->bpc = 8;
> > +			break;
> > +		case 0x2:
> > +			vsc->bpc = 10;
> > +			break;
> > +		case 0x3:
> > +			vsc->bpc = 12;
> > +			break;
> > +		case 0x4:
> > +			vsc->bpc = 16;
> > +			break;
> > +		default:
> > +			MISSING_CASE(sdp->db[17] & 0x7);
> 
> Handle 6bpc case as well.
> 
Yes,  I'll update everything that you commented.
> > +			return -EINVAL;
> > +		}
> > +
> > +		vsc->content_type = sdp->db[18] & 0x7;
> > +	} else {
> > +		return -EINVAL;
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> > +static int
> > +intel_dp_hdr_metadata_infoframe_sdp_unpack(struct
> > hdmi_drm_infoframe
> > *drm_infoframe,
> > +					   const void *buffer, size_t
> > size) {
> > +	int ret;
> > +
> > +	const struct dp_sdp *sdp = buffer;
> > +
> > +	if (size < sizeof(struct dp_sdp))
> > +		return -EINVAL;
> > +
> > +	if (sdp->sdp_header.HB0 != 0)
> > +		return -EINVAL;
> > +
> > +	if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
> > +		return -EINVAL;
> > +
> > +	/*
> > +	 * Least Significant Eight Bits of (Data Byte Count – 1)
> > +	 * 1Dh (i.e., Data Byte Count = 30 bytes).
> > +	 */
> > +	if (sdp->sdp_header.HB2 != 0x1D)
> > +		return -EINVAL;
> > +
> > +	/* Most Significant Two Bits of (Data Byte Count – 1), Clear to
> > 00b. */
> > +	if ((sdp->sdp_header.HB3 & 0x3) != 0)
> > +		return -EINVAL;
> > +
> > +	/* INFOFRAME SDP Version Number */
> > +	if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
> > +		return -EINVAL;
> > +
> > +	/* CTA Header Byte 2 (INFOFRAME Version Number) */
> > +	if (sdp->db[0] != 1)
> > +		return -EINVAL;
> > +
> > +	/* CTA Header Byte 3 (Length of INFOFRAME):
> > HDMI_DRM_INFOFRAME_SIZE */
> > +	if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
> > +		return -EINVAL;
> > +
> > +	ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp-
> > >db[2],
> > +					     HDMI_DRM_INFOFRAME_SIZE);
> > +
> > +	return ret;
> > +}
> > +
> > +static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
> > +				  struct intel_crtc_state *crtc_state,
> > +				  struct drm_dp_vsc_sdp *vsc)
> > +{
> > +	struct intel_digital_port *intel_dig_port =
> > enc_to_dig_port(encoder);
> > +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > +	unsigned int type = DP_SDP_VSC;
> > +	struct dp_sdp sdp = {};
> > +	int ret;
> > +
> > +	/* When PSR is enabled, VSC SDP is handled by PSR routine */
> > +	if (intel_psr_enabled(intel_dp))
> > +		return;
> > +
> > +	if ((crtc_state->infoframes.enable &
> > +	     intel_hdmi_infoframe_enable(type)) == 0)
> > +		return;
> > +
> > +	intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
> > +sizeof(sdp));
> > +
> > +	ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
> > +
> > +	if (ret)
> > +		DRM_DEBUG_KMS("Failed to unpack DP VSC SDP\n"); }
> > +
> > +static void intel_read_dp_hdr_metadata_infoframe_sdp(struct
> > intel_encoder
> > *encoder,
> > +						     struct
> > intel_crtc_state
> > *crtc_state,
> > +						     struct
> > hdmi_drm_infoframe
> > *drm_infoframe) {
> > +	struct intel_digital_port *intel_dig_port =
> > enc_to_dig_port(encoder);
> > +	unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
> > +	struct dp_sdp sdp = {};
> > +	int ret;
> > +
> > +	if ((crtc_state->infoframes.enable &
> > +	    intel_hdmi_infoframe_enable(type)) == 0)
> > +		return;
> > +
> > +	intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
> > +				       sizeof(sdp));
> > +
> > +	ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe,
> > &sdp,
> > +							 sizeof(sdp));
> > +
> > +	if (ret)
> > +		DRM_DEBUG_KMS("Failed to unpack DP HDR Metadata
> > Infoframe
> > SDP\n"); }
> > +
> > +void intel_read_dp_sdp(struct intel_encoder *encoder,
> > +		       struct intel_crtc_state *crtc_state,
> > +		       unsigned int type)
> > +{
> > +	switch (type) {
> > +	case DP_SDP_VSC:
> > +		intel_read_dp_vsc_sdp(encoder, crtc_state,
> > +				      &crtc_state->infoframes.vsc);
> > +		break;
> > +	case HDMI_PACKET_TYPE_GAMUT_METADATA:
> > +		intel_read_dp_hdr_metadata_infoframe_sdp(encoder,
> > crtc_state,
> > +							 &crtc_state-
> > > infoframes.drm.drm);
> > +		break;
> > +	default:
> > +		MISSING_CASE(type);
> > +		break;
> > +	}
> > +}
> > +
> >  static void
> >  intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
> >  		       const struct intel_crtc_state *crtc_state, diff
> > --git
> > a/drivers/gpu/drm/i915/display/intel_dp.h
> > b/drivers/gpu/drm/i915/display/intel_dp.h
> > index 0dc09a463ee1..e8f9ba962d09 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > @@ -119,6 +119,9 @@ void intel_dp_hdr_metadata_enable(struct
> > intel_dp
> > *intel_dp,  void intel_dp_set_infoframes(struct intel_encoder
> > *encoder, bool
> > enable,
> >  			     const struct intel_crtc_state *crtc_state,
> >  			     const struct drm_connector_state
> > *conn_state);
> > +void intel_read_dp_sdp(struct intel_encoder *encoder,
> > +		       struct intel_crtc_state *crtc_state,
> > +		       unsigned int type);
> >  bool intel_digital_port_connected(struct intel_encoder *encoder);
> > 
> >  static inline unsigned int intel_dp_unused_lane_mask(int
> > lane_count)
> > --
> > 2.24.1
> > 
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v3 11/17] drm/i915: Program DP SDPs with computed configs

[Mun, Gwan-gyeong]

T24gV2VkLCAyMDIwLTAyLTA1IGF0IDIyOjIxICswNTMwLCBTaGFua2FyLCBVbWEgd3JvdGU6DQo+
ID4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gPiBGcm9tOiBJbnRlbC1nZnggPGludGVs
LWdmeC1ib3VuY2VzQGxpc3RzLmZyZWVkZXNrdG9wLm9yZz4gT24gQmVoYWxmDQo+ID4gT2YgR3dh
bi0NCj4gPiBneWVvbmcgTXVuDQo+ID4gU2VudDogVHVlc2RheSwgRmVicnVhcnkgNCwgMjAyMCA0
OjUwIEFNDQo+ID4gVG86IGludGVsLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcNCj4gPiBDYzog
bGludXgtZmJkZXZAdmdlci5rZXJuZWwub3JnOyBkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Au
b3JnDQo+ID4gU3ViamVjdDogW0ludGVsLWdmeF0gW1BBVENIIHYzIDExLzE3XSBkcm0vaTkxNTog
UHJvZ3JhbSBEUCBTRFBzDQo+ID4gd2l0aCBjb21wdXRlZA0KPiA+IGNvbmZpZ3MNCj4gPiANCj4g
PiBJbiBvcmRlciB0byB1c2UgY29tcHV0ZWQgY29uZmlnIGZvciBEUCBTRFBzIChEUCBWU0MgU0RQ
IGFuZCBEUCBIRFINCj4gPiBNZXRhZGF0YQ0KPiA+IEluZm9mcmFtZSBTRFApLCBpdCByZXBsYWNl
cyBpbnRlbF9kcF92c2NfZW5hYmxlKCkgZnVuY3Rpb24gYW5kDQo+ID4gaW50ZWxfZHBfaGRyX21l
dGFkYXRhX2VuYWJsZSgpIGZ1bmN0aW9uIHRvDQo+ID4gaW50ZWxfZHBfc2V0X2luZm9mcmFtZXMo
KSBmdW5jdGlvbi4NCj4gPiANCj4gPiBCZWZvcmUgYXBwbHlpbmcgaXQsIHJvdXRpbmVzIG9mIHBy
b2dyYW0gU0RQIGFsd2F5cyBjYWxjdWxhdGVkDQo+ID4gY29uZmlncyB3aGVuIHRoZXkNCj4gPiBj
YWxsZWQuIEFuZCBpdCByZW1vdmVzIHVudXNlZCBmdW5jdGlvbnMuDQo+IA0KPiBGaXggdGhlIHNl
bnRlbmNlLCBzZWVtcyB1bmNsZWFyLg0KPiBXaXRoIHRoYXQgZml4ZWQsDQpPa2F5LCBJJ2xsIHVw
ZGF0ZSB3aXRoIHRoZSBjb25kaXRpb24gb2YgYmVmb3JlIC8gYWZ0ZXIuDQoNCj4gUmV2aWV3ZWQt
Ynk6IFVtYSBTaGFua2FyIDx1bWEuc2hhbmthckBpbnRlbC5jb20+DQo+IA0KPiA+IHYzOiBSZWJh
c2VkDQo+ID4gDQo+ID4gU2lnbmVkLW9mZi1ieTogR3dhbi1neWVvbmcgTXVuIDxnd2FuLWd5ZW9u
Zy5tdW5AaW50ZWwuY29tPg0KPiA+IC0tLQ0KPiA+ICBkcml2ZXJzL2dwdS9kcm0vaTkxNS9kaXNw
bGF5L2ludGVsX2RkaS5jIHwgICAzICstDQo+ID4gIGRyaXZlcnMvZ3B1L2RybS9pOTE1L2Rpc3Bs
YXkvaW50ZWxfZHAuYyAgfCAyMjYgLS0tLS0tLS0tLS0tLS0tLS0NCj4gPiAtLS0tLS0NCj4gPiAg
ZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9kcC5oICB8ICAgNiAtDQo+ID4gIDMg
ZmlsZXMgY2hhbmdlZCwgMSBpbnNlcnRpb24oKyksIDIzNCBkZWxldGlvbnMoLSkNCj4gPiANCj4g
PiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9kZGkuYw0K
PiA+IGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9kZGkuYw0KPiA+IGluZGV4
IGM5NmY2MjljZGRjMy4uMzc0YWI2YTM3NTdjIDEwMDY0NA0KPiA+IC0tLSBhL2RyaXZlcnMvZ3B1
L2RybS9pOTE1L2Rpc3BsYXkvaW50ZWxfZGRpLmMNCj4gPiArKysgYi9kcml2ZXJzL2dwdS9kcm0v
aTkxNS9kaXNwbGF5L2ludGVsX2RkaS5jDQo+ID4gQEAgLTM5MDAsOCArMzkwMCw3IEBAIHN0YXRp
YyB2b2lkIGludGVsX2VuYWJsZV9kZGlfZHAoc3RydWN0DQo+ID4gaW50ZWxfZW5jb2Rlcg0KPiA+
ICplbmNvZGVyLA0KPiA+IA0KPiA+ICAJaW50ZWxfZWRwX2JhY2tsaWdodF9vbihjcnRjX3N0YXRl
LCBjb25uX3N0YXRlKTsNCj4gPiAgCWludGVsX3Bzcl9lbmFibGUoaW50ZWxfZHAsIGNydGNfc3Rh
dGUpOw0KPiA+IC0JaW50ZWxfZHBfdnNjX2VuYWJsZShpbnRlbF9kcCwgY3J0Y19zdGF0ZSwgY29u
bl9zdGF0ZSk7DQo+ID4gLQlpbnRlbF9kcF9oZHJfbWV0YWRhdGFfZW5hYmxlKGludGVsX2RwLCBj
cnRjX3N0YXRlLCBjb25uX3N0YXRlKTsNCj4gPiArCWludGVsX2RwX3NldF9pbmZvZnJhbWVzKGVu
Y29kZXIsIHRydWUsIGNydGNfc3RhdGUsIGNvbm5fc3RhdGUpOw0KPiA+ICAJaW50ZWxfZWRwX2Ry
cnNfZW5hYmxlKGludGVsX2RwLCBjcnRjX3N0YXRlKTsNCj4gPiANCj4gPiAgCWlmIChjcnRjX3N0
YXRlLT5oYXNfYXVkaW8pDQo+ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2Rp
c3BsYXkvaW50ZWxfZHAuYw0KPiA+IGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRl
bF9kcC5jDQo+ID4gaW5kZXggZDRlY2UwYTgyNGMwLi5jZmZiNzdkYWVjOTYgMTAwNjQ0DQo+ID4g
LS0tIGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9kcC5jDQo+ID4gKysrIGIv
ZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9kcC5jDQo+ID4gQEAgLTUwOTUsMjMy
ICs1MDk1LDYgQEAgdm9pZCBpbnRlbF9yZWFkX2RwX3NkcChzdHJ1Y3QgaW50ZWxfZW5jb2Rlcg0K
PiA+ICplbmNvZGVyLA0KPiA+ICAJfQ0KPiA+ICB9DQo+ID4gDQo+ID4gLXN0YXRpYyB2b2lkDQo+
ID4gLWludGVsX2RwX3NldHVwX3ZzY19zZHAoc3RydWN0IGludGVsX2RwICppbnRlbF9kcCwNCj4g
PiAtCQkgICAgICAgY29uc3Qgc3RydWN0IGludGVsX2NydGNfc3RhdGUgKmNydGNfc3RhdGUsDQo+
ID4gLQkJICAgICAgIGNvbnN0IHN0cnVjdCBkcm1fY29ubmVjdG9yX3N0YXRlICpjb25uX3N0YXRl
KQ0KPiA+IC17DQo+ID4gLQlzdHJ1Y3QgaW50ZWxfZGlnaXRhbF9wb3J0ICppbnRlbF9kaWdfcG9y
dCA9DQo+ID4gZHBfdG9fZGlnX3BvcnQoaW50ZWxfZHApOw0KPiA+IC0Jc3RydWN0IGRwX3NkcCB2
c2Nfc2RwID0ge307DQo+ID4gLQ0KPiA+IC0JLyogUHJlcGFyZSBWU0MgSGVhZGVyIGZvciBTVSBh
cyBwZXIgRFAgMS40YSBzcGVjLCBUYWJsZSAyLTExOQ0KPiA+ICovDQo+ID4gLQl2c2Nfc2RwLnNk
cF9oZWFkZXIuSEIwID0gMDsNCj4gPiAtCXZzY19zZHAuc2RwX2hlYWRlci5IQjEgPSAweDc7DQo+
ID4gLQ0KPiA+IC0JLyoNCj4gPiAtCSAqIFZTQyBTRFAgc3VwcG9ydGluZyAzRCBzdGVyZW8sIFBT
UjIsIGFuZCBQaXhlbCBFbmNvZGluZy8NCj4gPiAtCSAqIENvbG9yaW1ldHJ5IEZvcm1hdCBpbmRp
Y2F0aW9uLg0KPiA+IC0JICovDQo+ID4gLQl2c2Nfc2RwLnNkcF9oZWFkZXIuSEIyID0gMHg1Ow0K
PiA+IC0NCj4gPiAtCS8qDQo+ID4gLQkgKiBWU0MgU0RQIHN1cHBvcnRpbmcgM0Qgc3RlcmVvLCAr
IFBTUjIsICsgUGl4ZWwgRW5jb2RpbmcvDQo+ID4gLQkgKiBDb2xvcmltZXRyeSBGb3JtYXQgaW5k
aWNhdGlvbiAoSEIyID0gMDVoKS4NCj4gPiAtCSAqLw0KPiA+IC0JdnNjX3NkcC5zZHBfaGVhZGVy
LkhCMyA9IDB4MTM7DQo+ID4gLQ0KPiA+IC0JLyogRFAgMS40YSBzcGVjLCBUYWJsZSAyLTEyMCAq
Lw0KPiA+IC0Jc3dpdGNoIChjcnRjX3N0YXRlLT5vdXRwdXRfZm9ybWF0KSB7DQo+ID4gLQljYXNl
IElOVEVMX09VVFBVVF9GT1JNQVRfWUNCQ1I0NDQ6DQo+ID4gLQkJdnNjX3NkcC5kYlsxNl0gPSAw
eDEgPDwgNDsgLyogWUNiQ3IgNDQ0IDogREIxNls3OjRdID0NCj4gPiAxaCAqLw0KPiA+IC0JCWJy
ZWFrOw0KPiA+IC0JY2FzZSBJTlRFTF9PVVRQVVRfRk9STUFUX1lDQkNSNDIwOg0KPiA+IC0JCXZz
Y19zZHAuZGJbMTZdID0gMHgzIDw8IDQ7IC8qIFlDYkNyIDQyMCA6IERCMTZbNzo0XSA9DQo+ID4g
M2ggKi8NCj4gPiAtCQlicmVhazsNCj4gPiAtCWNhc2UgSU5URUxfT1VUUFVUX0ZPUk1BVF9SR0I6
DQo+ID4gLQlkZWZhdWx0Og0KPiA+IC0JCS8qIFJHQjogREIxNls3OjRdID0gMGggKi8NCj4gPiAt
CQlicmVhazsNCj4gPiAtCX0NCj4gPiAtDQo+ID4gLQlzd2l0Y2ggKGNvbm5fc3RhdGUtPmNvbG9y
c3BhY2UpIHsNCj4gPiAtCWNhc2UgRFJNX01PREVfQ09MT1JJTUVUUllfQlQ3MDlfWUNDOg0KPiA+
IC0JCXZzY19zZHAuZGJbMTZdIHw9IDB4MTsNCj4gPiAtCQlicmVhazsNCj4gPiAtCWNhc2UgRFJN
X01PREVfQ09MT1JJTUVUUllfWFZZQ0NfNjAxOg0KPiA+IC0JCXZzY19zZHAuZGJbMTZdIHw9IDB4
MjsNCj4gPiAtCQlicmVhazsNCj4gPiAtCWNhc2UgRFJNX01PREVfQ09MT1JJTUVUUllfWFZZQ0Nf
NzA5Og0KPiA+IC0JCXZzY19zZHAuZGJbMTZdIHw9IDB4MzsNCj4gPiAtCQlicmVhazsNCj4gPiAt
CWNhc2UgRFJNX01PREVfQ09MT1JJTUVUUllfU1lDQ182MDE6DQo+ID4gLQkJdnNjX3NkcC5kYlsx
Nl0gfD0gMHg0Ow0KPiA+IC0JCWJyZWFrOw0KPiA+IC0JY2FzZSBEUk1fTU9ERV9DT0xPUklNRVRS
WV9PUFlDQ182MDE6DQo+ID4gLQkJdnNjX3NkcC5kYlsxNl0gfD0gMHg1Ow0KPiA+IC0JCWJyZWFr
Ow0KPiA+IC0JY2FzZSBEUk1fTU9ERV9DT0xPUklNRVRSWV9CVDIwMjBfQ1lDQzoNCj4gPiAtCWNh
c2UgRFJNX01PREVfQ09MT1JJTUVUUllfQlQyMDIwX1JHQjoNCj4gPiAtCQl2c2Nfc2RwLmRiWzE2
XSB8PSAweDY7DQo+ID4gLQkJYnJlYWs7DQo+ID4gLQljYXNlIERSTV9NT0RFX0NPTE9SSU1FVFJZ
X0JUMjAyMF9ZQ0M6DQo+ID4gLQkJdnNjX3NkcC5kYlsxNl0gfD0gMHg3Ow0KPiA+IC0JCWJyZWFr
Ow0KPiA+IC0JY2FzZSBEUk1fTU9ERV9DT0xPUklNRVRSWV9EQ0lfUDNfUkdCX0Q2NToNCj4gPiAt
CWNhc2UgRFJNX01PREVfQ09MT1JJTUVUUllfRENJX1AzX1JHQl9USEVBVEVSOg0KPiA+IC0JCXZz
Y19zZHAuZGJbMTZdIHw9IDB4NDsgLyogRENJLVAzIChTTVBURSBSUCA0MzEtMikgKi8NCj4gPiAt
CQlicmVhazsNCj4gPiAtCWRlZmF1bHQ6DQo+ID4gLQkJLyogc1JHQiAoSUVDIDYxOTY2LTItMSkg
LyBJVFUtUiBCVC42MDE6IERCMTZbMDozXSA9IDBoDQo+ID4gKi8NCj4gPiAtDQo+ID4gLQkJLyog
UkdCLT5ZQ0JDUiBjb2xvciBjb252ZXJzaW9uIHVzZXMgdGhlIEJULjcwOSBjb2xvcg0KPiA+IHNw
YWNlLiAqLw0KPiA+IC0JCWlmIChjcnRjX3N0YXRlLT5vdXRwdXRfZm9ybWF0ID09DQo+ID4gSU5U
RUxfT1VUUFVUX0ZPUk1BVF9ZQ0JDUjQyMCkNCj4gPiAtCQkJdnNjX3NkcC5kYlsxNl0gfD0gMHgx
OyAvKiAweDEsIElUVS1SIEJULjcwOSAqLw0KPiA+IC0JCWJyZWFrOw0KPiA+IC0JfQ0KPiA+IC0N
Cj4gPiAtCS8qDQo+ID4gLQkgKiBGb3IgcGl4ZWwgZW5jb2RpbmcgZm9ybWF0cyBZQ2JDcjQ0NCwg
WUNiQ3I0MjIsIFlDYkNyNDIwLCBhbmQNCj4gPiBZIE9ubHksDQo+ID4gLQkgKiB0aGUgZm9sbG93
aW5nIENvbXBvbmVudCBCaXQgRGVwdGggdmFsdWVzIGFyZSBkZWZpbmVkOg0KPiA+IC0JICogMDAx
YiA9IDhicGMuDQo+ID4gLQkgKiAwMTBiID0gMTBicGMuDQo+ID4gLQkgKiAwMTFiID0gMTJicGMu
DQo+ID4gLQkgKiAxMDBiID0gMTZicGMuDQo+ID4gLQkgKi8NCj4gPiAtCXN3aXRjaCAoY3J0Y19z
dGF0ZS0+cGlwZV9icHApIHsNCj4gPiAtCWNhc2UgMjQ6IC8qIDhicGMgKi8NCj4gPiAtCQl2c2Nf
c2RwLmRiWzE3XSA9IDB4MTsNCj4gPiAtCQlicmVhazsNCj4gPiAtCWNhc2UgMzA6IC8qIDEwYnBj
ICovDQo+ID4gLQkJdnNjX3NkcC5kYlsxN10gPSAweDI7DQo+ID4gLQkJYnJlYWs7DQo+ID4gLQlj
YXNlIDM2OiAvKiAxMmJwYyAqLw0KPiA+IC0JCXZzY19zZHAuZGJbMTddID0gMHgzOw0KPiA+IC0J
CWJyZWFrOw0KPiA+IC0JY2FzZSA0ODogLyogMTZicGMgKi8NCj4gPiAtCQl2c2Nfc2RwLmRiWzE3
XSA9IDB4NDsNCj4gPiAtCQlicmVhazsNCj4gPiAtCWRlZmF1bHQ6DQo+ID4gLQkJTUlTU0lOR19D
QVNFKGNydGNfc3RhdGUtPnBpcGVfYnBwKTsNCj4gPiAtCQlicmVhazsNCj4gPiAtCX0NCj4gPiAt
DQo+ID4gLQkvKg0KPiA+IC0JICogRHluYW1pYyBSYW5nZSAoQml0IDcpDQo+ID4gLQkgKiAwID0g
VkVTQSByYW5nZSwgMSA9IENUQSByYW5nZS4NCj4gPiAtCSAqIGFsbCBZQ2JDciBhcmUgYWx3YXlz
IGxpbWl0ZWQgcmFuZ2UNCj4gPiAtCSAqLw0KPiA+IC0JdnNjX3NkcC5kYlsxN10gfD0gMHg4MDsN
Cj4gPiAtDQo+ID4gLQkvKg0KPiA+IC0JICogQ29udGVudCBUeXBlIChCaXRzIDI6MCkNCj4gPiAt
CSAqIDAwMGIgPSBOb3QgZGVmaW5lZC4NCj4gPiAtCSAqIDAwMWIgPSBHcmFwaGljcy4NCj4gPiAt
CSAqIDAxMGIgPSBQaG90by4NCj4gPiAtCSAqIDAxMWIgPSBWaWRlby4NCj4gPiAtCSAqIDEwMGIg
PSBHYW1lDQo+ID4gLQkgKiBBbGwgb3RoZXIgdmFsdWVzIGFyZSBSRVNFUlZFRC4NCj4gPiAtCSAq
IE5vdGU6IFNlZSBDVEEtODYxLUcgZm9yIHRoZSBkZWZpbml0aW9uIGFuZCBleHBlY3RlZA0KPiA+
IC0JICogcHJvY2Vzc2luZyBieSBhIHN0cmVhbSBzaW5rIGZvciB0aGUgYWJvdmUgY29udGVjdCB0
eXBlcy4NCj4gPiAtCSAqLw0KPiA+IC0JdnNjX3NkcC5kYlsxOF0gPSAwOw0KPiA+IC0NCj4gPiAt
CWludGVsX2RpZ19wb3J0LT53cml0ZV9pbmZvZnJhbWUoJmludGVsX2RpZ19wb3J0LT5iYXNlLA0K
PiA+IC0JCQljcnRjX3N0YXRlLCBEUF9TRFBfVlNDLCAmdnNjX3NkcCwNCj4gPiBzaXplb2YodnNj
X3NkcCkpOw0KPiA+IC19DQo+ID4gLQ0KPiA+IC1zdGF0aWMgdm9pZA0KPiA+IC1pbnRlbF9kcF9z
ZXR1cF9oZHJfbWV0YWRhdGFfaW5mb2ZyYW1lX3NkcChzdHJ1Y3QgaW50ZWxfZHANCj4gPiAqaW50
ZWxfZHAsDQo+ID4gLQkJCQkJICBjb25zdCBzdHJ1Y3QgaW50ZWxfY3J0Y19zdGF0ZQ0KPiA+ICpj
cnRjX3N0YXRlLA0KPiA+IC0JCQkJCSAgY29uc3Qgc3RydWN0DQo+ID4gZHJtX2Nvbm5lY3Rvcl9z
dGF0ZQ0KPiA+ICpjb25uX3N0YXRlKQ0KPiA+IC17DQo+ID4gLQlzdHJ1Y3QgaW50ZWxfZGlnaXRh
bF9wb3J0ICppbnRlbF9kaWdfcG9ydCA9DQo+ID4gZHBfdG9fZGlnX3BvcnQoaW50ZWxfZHApOw0K
PiA+IC0Jc3RydWN0IGRwX3NkcCBpbmZvZnJhbWVfc2RwID0ge307DQo+ID4gLQlzdHJ1Y3QgaGRt
aV9kcm1faW5mb2ZyYW1lIGRybV9pbmZvZnJhbWUgPSB7fTsNCj4gPiAtCWNvbnN0IGludCBpbmZv
ZnJhbWVfc2l6ZSA9IEhETUlfSU5GT0ZSQU1FX0hFQURFUl9TSVpFICsNCj4gPiBIRE1JX0RSTV9J
TkZPRlJBTUVfU0laRTsNCj4gPiAtCXVuc2lnbmVkIGNoYXIgYnVmW0hETUlfSU5GT0ZSQU1FX0hF
QURFUl9TSVpFICsNCj4gPiBIRE1JX0RSTV9JTkZPRlJBTUVfU0laRV07DQo+ID4gLQlzc2l6ZV90
IGxlbjsNCj4gPiAtCWludCByZXQ7DQo+ID4gLQ0KPiA+IC0JcmV0ID0gZHJtX2hkbWlfaW5mb2Zy
YW1lX3NldF9oZHJfbWV0YWRhdGEoJmRybV9pbmZvZnJhbWUsDQo+ID4gY29ubl9zdGF0ZSk7DQo+
ID4gLQlpZiAocmV0KSB7DQo+ID4gLQkJRFJNX0RFQlVHX0tNUygiY291bGRuJ3Qgc2V0IEhEUiBt
ZXRhZGF0YSBpbg0KPiA+IGluZm9mcmFtZVxuIik7DQo+ID4gLQkJcmV0dXJuOw0KPiA+IC0JfQ0K
PiA+IC0NCj4gPiAtCWxlbiA9IGhkbWlfZHJtX2luZm9mcmFtZV9wYWNrX29ubHkoJmRybV9pbmZv
ZnJhbWUsIGJ1ZiwNCj4gPiBzaXplb2YoYnVmKSk7DQo+ID4gLQlpZiAobGVuIDwgMCkgew0KPiA+
IC0JCURSTV9ERUJVR19LTVMoImJ1ZmZlciBzaXplIGlzIHNtYWxsZXIgdGhhbiBoZHIgbWV0YWRh
dGENCj4gPiBpbmZvZnJhbWVcbiIpOw0KPiA+IC0JCXJldHVybjsNCj4gPiAtCX0NCj4gPiAtDQo+
ID4gLQlpZiAobGVuICE9IGluZm9mcmFtZV9zaXplKSB7DQo+ID4gLQkJRFJNX0RFQlVHX0tNUygi
d3Jvbmcgc3RhdGljIGhkciBtZXRhZGF0YSBzaXplXG4iKTsNCj4gPiAtCQlyZXR1cm47DQo+ID4g
LQl9DQo+ID4gLQ0KPiA+IC0JLyoNCj4gPiAtCSAqIFNldCB1cCB0aGUgaW5mb2ZyYW1lIHNkcCBw
YWNrZXQgZm9yIEhEUiBzdGF0aWMgbWV0YWRhdGEuDQo+ID4gLQkgKiBQcmVwYXJlIFZTQyBIZWFk
ZXIgZm9yIFNVIGFzIHBlciBEUCAxLjRhIHNwZWMsDQo+ID4gLQkgKiBUYWJsZSAyLTEwMCBhbmQg
VGFibGUgMi0xMDENCj4gPiAtCSAqLw0KPiA+IC0NCj4gPiAtCS8qIFBhY2tldCBJRCwgMDBoIGZv
ciBub24tQXVkaW8gSU5GT0ZSQU1FICovDQo+ID4gLQlpbmZvZnJhbWVfc2RwLnNkcF9oZWFkZXIu
SEIwID0gMDsNCj4gPiAtCS8qDQo+ID4gLQkgKiBQYWNrZXQgVHlwZSA4MGggKyBOb24tYXVkaW8g
SU5GT0ZSQU1FIFR5cGUgdmFsdWUNCj4gPiAtCSAqIEhETUlfSU5GT0ZSQU1FX1RZUEVfRFJNOiAw
eDg3LA0KPiA+IC0JICovDQo+ID4gLQlpbmZvZnJhbWVfc2RwLnNkcF9oZWFkZXIuSEIxID0gZHJt
X2luZm9mcmFtZS50eXBlOw0KPiA+IC0JLyoNCj4gPiAtCSAqIExlYXN0IFNpZ25pZmljYW50IEVp
Z2h0IEJpdHMgb2YgKERhdGEgQnl0ZSBDb3VudCDigJMgMSkNCj4gPiAtCSAqIGluZm9mcmFtZV9z
aXplIC0gMSwNCj4gPiAtCSAqLw0KPiA+IC0JaW5mb2ZyYW1lX3NkcC5zZHBfaGVhZGVyLkhCMiA9
IDB4MUQ7DQo+ID4gLQkvKiBJTkZPRlJBTUUgU0RQIFZlcnNpb24gTnVtYmVyICovDQo+ID4gLQlp
bmZvZnJhbWVfc2RwLnNkcF9oZWFkZXIuSEIzID0gKDB4MTMgPDwgMik7DQo+ID4gLQkvKiBDVEEg
SGVhZGVyIEJ5dGUgMiAoSU5GT0ZSQU1FIFZlcnNpb24gTnVtYmVyKSAqLw0KPiA+IC0JaW5mb2Zy
YW1lX3NkcC5kYlswXSA9IGRybV9pbmZvZnJhbWUudmVyc2lvbjsNCj4gPiAtCS8qIENUQSBIZWFk
ZXIgQnl0ZSAzIChMZW5ndGggb2YgSU5GT0ZSQU1FKToNCj4gPiBIRE1JX0RSTV9JTkZPRlJBTUVf
U0laRSAqLw0KPiA+IC0JaW5mb2ZyYW1lX3NkcC5kYlsxXSA9IGRybV9pbmZvZnJhbWUubGVuZ3Ro
Ow0KPiA+IC0JLyoNCj4gPiAtCSAqIENvcHkgSERNSV9EUk1fSU5GT0ZSQU1FX1NJWkUgc2l6ZSBm
cm9tIGEgYnVmZmVyIGFmdGVyDQo+ID4gLQkgKiBIRE1JX0lORk9GUkFNRV9IRUFERVJfU0laRQ0K
PiA+IC0JICovDQo+ID4gLQlCVUlMRF9CVUdfT04oc2l6ZW9mKGluZm9mcmFtZV9zZHAuZGIpIDwg
SERNSV9EUk1fSU5GT0ZSQU1FX1NJWkUNCj4gPiArIDIpOw0KPiA+IC0JbWVtY3B5KCZpbmZvZnJh
bWVfc2RwLmRiWzJdLCAmYnVmW0hETUlfSU5GT0ZSQU1FX0hFQURFUl9TSVpFXSwNCj4gPiAtCSAg
ICAgICBIRE1JX0RSTV9JTkZPRlJBTUVfU0laRSk7DQo+ID4gLQ0KPiA+IC0JLyoNCj4gPiAtCSAq
IFNpemUgb2YgRFAgaW5mb2ZyYW1lIHNkcCBwYWNrZXQgZm9yIEhEUiBzdGF0aWMgbWV0YWRhdGEg
aXMNCj4gPiBjb25zaXN0IG9mDQo+ID4gLQkgKiAtIERQIFNEUCBIZWFkZXIoc3RydWN0IGRwX3Nk
cF9oZWFkZXIpOiA0IGJ5dGVzDQo+ID4gLQkgKiAtIFR3byBEYXRhIEJsb2NrczogMiBieXRlcw0K
PiA+IC0JICogICAgQ1RBIEhlYWRlciBCeXRlMiAoSU5GT0ZSQU1FIFZlcnNpb24gTnVtYmVyKQ0K
PiA+IC0JICogICAgQ1RBIEhlYWRlciBCeXRlMyAoTGVuZ3RoIG9mIElORk9GUkFNRSkNCj4gPiAt
CSAqIC0gSERNSV9EUk1fSU5GT0ZSQU1FX1NJWkU6IDI2IGJ5dGVzDQo+ID4gLQkgKg0KPiA+IC0J
ICogUHJpb3IgdG8gR0VOMTEncyBHTVAgcmVnaXN0ZXIgc2l6ZSBpcyBpZGVudGljYWwgdG8gRFAg
SERSDQo+ID4gc3RhdGljIG1ldGFkYXRhDQo+ID4gLQkgKiBpbmZvZnJhbWUgc2l6ZS4gQnV0IEdF
TjExKyBoYXMgbGFyZ2VyIHRoYW4gdGhhdCBzaXplLA0KPiA+IHdyaXRlX2luZm9mcmFtZQ0KPiA+
IC0JICogd2lsbCBwYWQgcmVzdCBvZiB0aGUgc2l6ZS4NCj4gPiAtCSAqLw0KPiA+IC0JaW50ZWxf
ZGlnX3BvcnQtPndyaXRlX2luZm9mcmFtZSgmaW50ZWxfZGlnX3BvcnQtPmJhc2UsDQo+ID4gY3J0
Y19zdGF0ZSwNCj4gPiAtCQkJCQlIRE1JX1BBQ0tFVF9UWVBFX0dBTVVUX01FVEFEQVRBDQo+ID4g
LA0KPiA+IC0JCQkJCSZpbmZvZnJhbWVfc2RwLA0KPiA+IC0JCQkJCXNpemVvZihzdHJ1Y3QgZHBf
c2RwX2hlYWRlcikgKw0KPiA+IDIgKw0KPiA+IEhETUlfRFJNX0lORk9GUkFNRV9TSVpFKTsNCj4g
PiAtfQ0KPiA+IC0NCj4gPiAtdm9pZCBpbnRlbF9kcF92c2NfZW5hYmxlKHN0cnVjdCBpbnRlbF9k
cCAqaW50ZWxfZHAsDQo+ID4gLQkJCSBjb25zdCBzdHJ1Y3QgaW50ZWxfY3J0Y19zdGF0ZSAqY3J0
Y19zdGF0ZSwNCj4gPiAtCQkJIGNvbnN0IHN0cnVjdCBkcm1fY29ubmVjdG9yX3N0YXRlICpjb25u
X3N0YXRlKQ0KPiA+IC17DQo+ID4gLQlpZiAoIWludGVsX2RwX25lZWRzX3ZzY19zZHAoY3J0Y19z
dGF0ZSwgY29ubl9zdGF0ZSkpDQo+ID4gLQkJcmV0dXJuOw0KPiA+IC0NCj4gPiAtCWludGVsX2Rw
X3NldHVwX3ZzY19zZHAoaW50ZWxfZHAsIGNydGNfc3RhdGUsIGNvbm5fc3RhdGUpOw0KPiA+IC19
DQo+ID4gLQ0KPiA+IC12b2lkIGludGVsX2RwX2hkcl9tZXRhZGF0YV9lbmFibGUoc3RydWN0IGlu
dGVsX2RwICppbnRlbF9kcCwNCj4gPiAtCQkJCSAgY29uc3Qgc3RydWN0IGludGVsX2NydGNfc3Rh
dGUNCj4gPiAqY3J0Y19zdGF0ZSwNCj4gPiAtCQkJCSAgY29uc3Qgc3RydWN0IGRybV9jb25uZWN0
b3Jfc3RhdGUNCj4gPiAqY29ubl9zdGF0ZSkNCj4gPiAtew0KPiA+IC0JaWYgKCFjb25uX3N0YXRl
LT5oZHJfb3V0cHV0X21ldGFkYXRhKQ0KPiA+IC0JCXJldHVybjsNCj4gPiAtDQo+ID4gLQlpbnRl
bF9kcF9zZXR1cF9oZHJfbWV0YWRhdGFfaW5mb2ZyYW1lX3NkcChpbnRlbF9kcCwNCj4gPiAtCQkJ
CQkJICBjcnRjX3N0YXRlLA0KPiA+IC0JCQkJCQkgIGNvbm5fc3RhdGUpOw0KPiA+IC19DQo+ID4g
LQ0KPiA+ICBzdGF0aWMgdTggaW50ZWxfZHBfYXV0b3Rlc3RfbGlua190cmFpbmluZyhzdHJ1Y3Qg
aW50ZWxfZHANCj4gPiAqaW50ZWxfZHApICB7DQo+ID4gIAlpbnQgc3RhdHVzID0gMDsNCj4gPiBk
aWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9kcC5oDQo+ID4g
Yi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9kaXNwbGF5L2ludGVsX2RwLmgNCj4gPiBpbmRleCBlOGY5
YmE5NjJkMDkuLjY1NjJiYjhlZGViYSAxMDA2NDQNCj4gPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0v
aTkxNS9kaXNwbGF5L2ludGVsX2RwLmgNCj4gPiArKysgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9k
aXNwbGF5L2ludGVsX2RwLmgNCj4gPiBAQCAtMTEwLDEyICsxMTAsNiBAQCBpbnQgaW50ZWxfZHBf
bGlua19yZXF1aXJlZChpbnQgcGl4ZWxfY2xvY2ssDQo+ID4gaW50IGJwcCk7ICBpbnQNCj4gPiBp
bnRlbF9kcF9tYXhfZGF0YV9yYXRlKGludCBtYXhfbGlua19jbG9jaywgaW50IG1heF9sYW5lcyk7
ICBib29sDQo+ID4gaW50ZWxfZHBfbmVlZHNfdnNjX3NkcChjb25zdCBzdHJ1Y3QgaW50ZWxfY3J0
Y19zdGF0ZSAqY3J0Y19zdGF0ZSwNCj4gPiAgCQkJICAgIGNvbnN0IHN0cnVjdCBkcm1fY29ubmVj
dG9yX3N0YXRlDQo+ID4gKmNvbm5fc3RhdGUpOyAtdm9pZA0KPiA+IGludGVsX2RwX3ZzY19lbmFi
bGUoc3RydWN0IGludGVsX2RwICppbnRlbF9kcCwNCj4gPiAtCQkJIGNvbnN0IHN0cnVjdCBpbnRl
bF9jcnRjX3N0YXRlICpjcnRjX3N0YXRlLA0KPiA+IC0JCQkgY29uc3Qgc3RydWN0IGRybV9jb25u
ZWN0b3Jfc3RhdGUgKmNvbm5fc3RhdGUpOw0KPiA+IC12b2lkIGludGVsX2RwX2hkcl9tZXRhZGF0
YV9lbmFibGUoc3RydWN0IGludGVsX2RwICppbnRlbF9kcCwNCj4gPiAtCQkJCSAgY29uc3Qgc3Ry
dWN0IGludGVsX2NydGNfc3RhdGUNCj4gPiAqY3J0Y19zdGF0ZSwNCj4gPiAtCQkJCSAgY29uc3Qg
c3RydWN0IGRybV9jb25uZWN0b3Jfc3RhdGUNCj4gPiAqY29ubl9zdGF0ZSk7DQo+ID4gIHZvaWQg
aW50ZWxfZHBfc2V0X2luZm9mcmFtZXMoc3RydWN0IGludGVsX2VuY29kZXIgKmVuY29kZXIsIGJv
b2wNCj4gPiBlbmFibGUsDQo+ID4gIAkJCSAgICAgY29uc3Qgc3RydWN0IGludGVsX2NydGNfc3Rh
dGUgKmNydGNfc3RhdGUsDQo+ID4gIAkJCSAgICAgY29uc3Qgc3RydWN0IGRybV9jb25uZWN0b3Jf
c3RhdGUNCj4gPiAqY29ubl9zdGF0ZSk7DQo+ID4gLS0NCj4gPiAyLjI0LjENCj4gPiANCj4gPiBf
X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXw0KPiA+IEludGVs
LWdmeCBtYWlsaW5nIGxpc3QNCj4gPiBJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnDQo+
ID4gaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9pbnRlbC1n
ZngNCg=

Re: [Intel-gfx] [PATCH v3 11/17] drm/i915: Program DP SDPs with computed configs

[Mun, Gwan-gyeong]

On Wed, 2020-02-05 at 22:21 +0530, Shankar, Uma wrote:
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
> > Of Gwan-
> > gyeong Mun
> > Sent: Tuesday, February 4, 2020 4:50 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> > Subject: [Intel-gfx] [PATCH v3 11/17] drm/i915: Program DP SDPs
> > with computed
> > configs
> > 
> > In order to use computed config for DP SDPs (DP VSC SDP and DP HDR
> > Metadata
> > Infoframe SDP), it replaces intel_dp_vsc_enable() function and
> > intel_dp_hdr_metadata_enable() function to
> > intel_dp_set_infoframes() function.
> > 
> > Before applying it, routines of program SDP always calculated
> > configs when they
> > called. And it removes unused functions.
> 
> Fix the sentence, seems unclear.
> With that fixed,
Okay, I'll update with the condition of before / after.

> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> 
> > v3: Rebased
> > 
> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c |   3 +-
> >  drivers/gpu/drm/i915/display/intel_dp.c  | 226 -----------------
> > ------
> >  drivers/gpu/drm/i915/display/intel_dp.h  |   6 -
> >  3 files changed, 1 insertion(+), 234 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index c96f629cddc3..374ab6a3757c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -3900,8 +3900,7 @@ static void intel_enable_ddi_dp(struct
> > intel_encoder
> > *encoder,
> > 
> >  	intel_edp_backlight_on(crtc_state, conn_state);
> >  	intel_psr_enable(intel_dp, crtc_state);
> > -	intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
> > -	intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
> > +	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
> >  	intel_edp_drrs_enable(intel_dp, crtc_state);
> > 
> >  	if (crtc_state->has_audio)
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index d4ece0a824c0..cffb77daec96 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -5095,232 +5095,6 @@ void intel_read_dp_sdp(struct intel_encoder
> > *encoder,
> >  	}
> >  }
> > 
> > -static void
> > -intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
> > -		       const struct intel_crtc_state *crtc_state,
> > -		       const struct drm_connector_state *conn_state)
> > -{
> > -	struct intel_digital_port *intel_dig_port =
> > dp_to_dig_port(intel_dp);
> > -	struct dp_sdp vsc_sdp = {};
> > -
> > -	/* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
> > */
> > -	vsc_sdp.sdp_header.HB0 = 0;
> > -	vsc_sdp.sdp_header.HB1 = 0x7;
> > -
> > -	/*
> > -	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > -	 * Colorimetry Format indication.
> > -	 */
> > -	vsc_sdp.sdp_header.HB2 = 0x5;
> > -
> > -	/*
> > -	 * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
> > -	 * Colorimetry Format indication (HB2 = 05h).
> > -	 */
> > -	vsc_sdp.sdp_header.HB3 = 0x13;
> > -
> > -	/* DP 1.4a spec, Table 2-120 */
> > -	switch (crtc_state->output_format) {
> > -	case INTEL_OUTPUT_FORMAT_YCBCR444:
> > -		vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] =
> > 1h */
> > -		break;
> > -	case INTEL_OUTPUT_FORMAT_YCBCR420:
> > -		vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] =
> > 3h */
> > -		break;
> > -	case INTEL_OUTPUT_FORMAT_RGB:
> > -	default:
> > -		/* RGB: DB16[7:4] = 0h */
> > -		break;
> > -	}
> > -
> > -	switch (conn_state->colorspace) {
> > -	case DRM_MODE_COLORIMETRY_BT709_YCC:
> > -		vsc_sdp.db[16] |= 0x1;
> > -		break;
> > -	case DRM_MODE_COLORIMETRY_XVYCC_601:
> > -		vsc_sdp.db[16] |= 0x2;
> > -		break;
> > -	case DRM_MODE_COLORIMETRY_XVYCC_709:
> > -		vsc_sdp.db[16] |= 0x3;
> > -		break;
> > -	case DRM_MODE_COLORIMETRY_SYCC_601:
> > -		vsc_sdp.db[16] |= 0x4;
> > -		break;
> > -	case DRM_MODE_COLORIMETRY_OPYCC_601:
> > -		vsc_sdp.db[16] |= 0x5;
> > -		break;
> > -	case DRM_MODE_COLORIMETRY_BT2020_CYCC:
> > -	case DRM_MODE_COLORIMETRY_BT2020_RGB:
> > -		vsc_sdp.db[16] |= 0x6;
> > -		break;
> > -	case DRM_MODE_COLORIMETRY_BT2020_YCC:
> > -		vsc_sdp.db[16] |= 0x7;
> > -		break;
> > -	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
> > -	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
> > -		vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */
> > -		break;
> > -	default:
> > -		/* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h
> > */
> > -
> > -		/* RGB->YCBCR color conversion uses the BT.709 color
> > space. */
> > -		if (crtc_state->output_format ==
> > INTEL_OUTPUT_FORMAT_YCBCR420)
> > -			vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
> > -		break;
> > -	}
> > -
> > -	/*
> > -	 * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and
> > Y Only,
> > -	 * the following Component Bit Depth values are defined:
> > -	 * 001b = 8bpc.
> > -	 * 010b = 10bpc.
> > -	 * 011b = 12bpc.
> > -	 * 100b = 16bpc.
> > -	 */
> > -	switch (crtc_state->pipe_bpp) {
> > -	case 24: /* 8bpc */
> > -		vsc_sdp.db[17] = 0x1;
> > -		break;
> > -	case 30: /* 10bpc */
> > -		vsc_sdp.db[17] = 0x2;
> > -		break;
> > -	case 36: /* 12bpc */
> > -		vsc_sdp.db[17] = 0x3;
> > -		break;
> > -	case 48: /* 16bpc */
> > -		vsc_sdp.db[17] = 0x4;
> > -		break;
> > -	default:
> > -		MISSING_CASE(crtc_state->pipe_bpp);
> > -		break;
> > -	}
> > -
> > -	/*
> > -	 * Dynamic Range (Bit 7)
> > -	 * 0 = VESA range, 1 = CTA range.
> > -	 * all YCbCr are always limited range
> > -	 */
> > -	vsc_sdp.db[17] |= 0x80;
> > -
> > -	/*
> > -	 * Content Type (Bits 2:0)
> > -	 * 000b = Not defined.
> > -	 * 001b = Graphics.
> > -	 * 010b = Photo.
> > -	 * 011b = Video.
> > -	 * 100b = Game
> > -	 * All other values are RESERVED.
> > -	 * Note: See CTA-861-G for the definition and expected
> > -	 * processing by a stream sink for the above contect types.
> > -	 */
> > -	vsc_sdp.db[18] = 0;
> > -
> > -	intel_dig_port->write_infoframe(&intel_dig_port->base,
> > -			crtc_state, DP_SDP_VSC, &vsc_sdp,
> > sizeof(vsc_sdp));
> > -}
> > -
> > -static void
> > -intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp
> > *intel_dp,
> > -					  const struct intel_crtc_state
> > *crtc_state,
> > -					  const struct
> > drm_connector_state
> > *conn_state)
> > -{
> > -	struct intel_digital_port *intel_dig_port =
> > dp_to_dig_port(intel_dp);
> > -	struct dp_sdp infoframe_sdp = {};
> > -	struct hdmi_drm_infoframe drm_infoframe = {};
> > -	const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE +
> > HDMI_DRM_INFOFRAME_SIZE;
> > -	unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE +
> > HDMI_DRM_INFOFRAME_SIZE];
> > -	ssize_t len;
> > -	int ret;
> > -
> > -	ret = drm_hdmi_infoframe_set_hdr_metadata(&drm_infoframe,
> > conn_state);
> > -	if (ret) {
> > -		DRM_DEBUG_KMS("couldn't set HDR metadata in
> > infoframe\n");
> > -		return;
> > -	}
> > -
> > -	len = hdmi_drm_infoframe_pack_only(&drm_infoframe, buf,
> > sizeof(buf));
> > -	if (len < 0) {
> > -		DRM_DEBUG_KMS("buffer size is smaller than hdr metadata
> > infoframe\n");
> > -		return;
> > -	}
> > -
> > -	if (len != infoframe_size) {
> > -		DRM_DEBUG_KMS("wrong static hdr metadata size\n");
> > -		return;
> > -	}
> > -
> > -	/*
> > -	 * Set up the infoframe sdp packet for HDR static metadata.
> > -	 * Prepare VSC Header for SU as per DP 1.4a spec,
> > -	 * Table 2-100 and Table 2-101
> > -	 */
> > -
> > -	/* Packet ID, 00h for non-Audio INFOFRAME */
> > -	infoframe_sdp.sdp_header.HB0 = 0;
> > -	/*
> > -	 * Packet Type 80h + Non-audio INFOFRAME Type value
> > -	 * HDMI_INFOFRAME_TYPE_DRM: 0x87,
> > -	 */
> > -	infoframe_sdp.sdp_header.HB1 = drm_infoframe.type;
> > -	/*
> > -	 * Least Significant Eight Bits of (Data Byte Count – 1)
> > -	 * infoframe_size - 1,
> > -	 */
> > -	infoframe_sdp.sdp_header.HB2 = 0x1D;
> > -	/* INFOFRAME SDP Version Number */
> > -	infoframe_sdp.sdp_header.HB3 = (0x13 << 2);
> > -	/* CTA Header Byte 2 (INFOFRAME Version Number) */
> > -	infoframe_sdp.db[0] = drm_infoframe.version;
> > -	/* CTA Header Byte 3 (Length of INFOFRAME):
> > HDMI_DRM_INFOFRAME_SIZE */
> > -	infoframe_sdp.db[1] = drm_infoframe.length;
> > -	/*
> > -	 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
> > -	 * HDMI_INFOFRAME_HEADER_SIZE
> > -	 */
> > -	BUILD_BUG_ON(sizeof(infoframe_sdp.db) < HDMI_DRM_INFOFRAME_SIZE
> > + 2);
> > -	memcpy(&infoframe_sdp.db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
> > -	       HDMI_DRM_INFOFRAME_SIZE);
> > -
> > -	/*
> > -	 * Size of DP infoframe sdp packet for HDR static metadata is
> > consist of
> > -	 * - DP SDP Header(struct dp_sdp_header): 4 bytes
> > -	 * - Two Data Blocks: 2 bytes
> > -	 *    CTA Header Byte2 (INFOFRAME Version Number)
> > -	 *    CTA Header Byte3 (Length of INFOFRAME)
> > -	 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
> > -	 *
> > -	 * Prior to GEN11's GMP register size is identical to DP HDR
> > static metadata
> > -	 * infoframe size. But GEN11+ has larger than that size,
> > write_infoframe
> > -	 * will pad rest of the size.
> > -	 */
> > -	intel_dig_port->write_infoframe(&intel_dig_port->base,
> > crtc_state,
> > -					HDMI_PACKET_TYPE_GAMUT_METADATA
> > ,
> > -					&infoframe_sdp,
> > -					sizeof(struct dp_sdp_header) +
> > 2 +
> > HDMI_DRM_INFOFRAME_SIZE);
> > -}
> > -
> > -void intel_dp_vsc_enable(struct intel_dp *intel_dp,
> > -			 const struct intel_crtc_state *crtc_state,
> > -			 const struct drm_connector_state *conn_state)
> > -{
> > -	if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
> > -		return;
> > -
> > -	intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);
> > -}
> > -
> > -void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
> > -				  const struct intel_crtc_state
> > *crtc_state,
> > -				  const struct drm_connector_state
> > *conn_state)
> > -{
> > -	if (!conn_state->hdr_output_metadata)
> > -		return;
> > -
> > -	intel_dp_setup_hdr_metadata_infoframe_sdp(intel_dp,
> > -						  crtc_state,
> > -						  conn_state);
> > -}
> > -
> >  static u8 intel_dp_autotest_link_training(struct intel_dp
> > *intel_dp)  {
> >  	int status = 0;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> > b/drivers/gpu/drm/i915/display/intel_dp.h
> > index e8f9ba962d09..6562bb8edeba 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > @@ -110,12 +110,6 @@ int intel_dp_link_required(int pixel_clock,
> > int bpp);  int
> > intel_dp_max_data_rate(int max_link_clock, int max_lanes);  bool
> > intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
> >  			    const struct drm_connector_state
> > *conn_state); -void
> > intel_dp_vsc_enable(struct intel_dp *intel_dp,
> > -			 const struct intel_crtc_state *crtc_state,
> > -			 const struct drm_connector_state *conn_state);
> > -void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
> > -				  const struct intel_crtc_state
> > *crtc_state,
> > -				  const struct drm_connector_state
> > *conn_state);
> >  void intel_dp_set_infoframes(struct intel_encoder *encoder, bool
> > enable,
> >  			     const struct intel_crtc_state *crtc_state,
> >  			     const struct drm_connector_state
> > *conn_state);
> > --
> > 2.24.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Intel-gfx] [PATCH v3 11/17] drm/i915: Program DP SDPs with computed configs

[Mun, Gwan-gyeong]

On Wed, 2020-02-05 at 22:21 +0530, Shankar, Uma wrote:
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
> > Of Gwan-
> > gyeong Mun
> > Sent: Tuesday, February 4, 2020 4:50 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> > Subject: [Intel-gfx] [PATCH v3 11/17] drm/i915: Program DP SDPs
> > with computed
> > configs
> > 
> > In order to use computed config for DP SDPs (DP VSC SDP and DP HDR
> > Metadata
> > Infoframe SDP), it replaces intel_dp_vsc_enable() function and
> > intel_dp_hdr_metadata_enable() function to
> > intel_dp_set_infoframes() function.
> > 
> > Before applying it, routines of program SDP always calculated
> > configs when they
> > called. And it removes unused functions.
> 
> Fix the sentence, seems unclear.
> With that fixed,
Okay, I'll update with the condition of before / after.

> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> 
> > v3: Rebased
> > 
> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c |   3 +-
> >  drivers/gpu/drm/i915/display/intel_dp.c  | 226 -----------------
> > ------
> >  drivers/gpu/drm/i915/display/intel_dp.h  |   6 -
> >  3 files changed, 1 insertion(+), 234 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index c96f629cddc3..374ab6a3757c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -3900,8 +3900,7 @@ static void intel_enable_ddi_dp(struct
> > intel_encoder
> > *encoder,
> > 
> >  	intel_edp_backlight_on(crtc_state, conn_state);
> >  	intel_psr_enable(intel_dp, crtc_state);
> > -	intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
> > -	intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
> > +	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
> >  	intel_edp_drrs_enable(intel_dp, crtc_state);
> > 
> >  	if (crtc_state->has_audio)
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index d4ece0a824c0..cffb77daec96 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -5095,232 +5095,6 @@ void intel_read_dp_sdp(struct intel_encoder
> > *encoder,
> >  	}
> >  }
> > 
> > -static void
> > -intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
> > -		       const struct intel_crtc_state *crtc_state,
> > -		       const struct drm_connector_state *conn_state)
> > -{
> > -	struct intel_digital_port *intel_dig_port =
> > dp_to_dig_port(intel_dp);
> > -	struct dp_sdp vsc_sdp = {};
> > -
> > -	/* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
> > */
> > -	vsc_sdp.sdp_header.HB0 = 0;
> > -	vsc_sdp.sdp_header.HB1 = 0x7;
> > -
> > -	/*
> > -	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > -	 * Colorimetry Format indication.
> > -	 */
> > -	vsc_sdp.sdp_header.HB2 = 0x5;
> > -
> > -	/*
> > -	 * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
> > -	 * Colorimetry Format indication (HB2 = 05h).
> > -	 */
> > -	vsc_sdp.sdp_header.HB3 = 0x13;
> > -
> > -	/* DP 1.4a spec, Table 2-120 */
> > -	switch (crtc_state->output_format) {
> > -	case INTEL_OUTPUT_FORMAT_YCBCR444:
> > -		vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] =
> > 1h */
> > -		break;
> > -	case INTEL_OUTPUT_FORMAT_YCBCR420:
> > -		vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] =
> > 3h */
> > -		break;
> > -	case INTEL_OUTPUT_FORMAT_RGB:
> > -	default:
> > -		/* RGB: DB16[7:4] = 0h */
> > -		break;
> > -	}
> > -
> > -	switch (conn_state->colorspace) {
> > -	case DRM_MODE_COLORIMETRY_BT709_YCC:
> > -		vsc_sdp.db[16] |= 0x1;
> > -		break;
> > -	case DRM_MODE_COLORIMETRY_XVYCC_601:
> > -		vsc_sdp.db[16] |= 0x2;
> > -		break;
> > -	case DRM_MODE_COLORIMETRY_XVYCC_709:
> > -		vsc_sdp.db[16] |= 0x3;
> > -		break;
> > -	case DRM_MODE_COLORIMETRY_SYCC_601:
> > -		vsc_sdp.db[16] |= 0x4;
> > -		break;
> > -	case DRM_MODE_COLORIMETRY_OPYCC_601:
> > -		vsc_sdp.db[16] |= 0x5;
> > -		break;
> > -	case DRM_MODE_COLORIMETRY_BT2020_CYCC:
> > -	case DRM_MODE_COLORIMETRY_BT2020_RGB:
> > -		vsc_sdp.db[16] |= 0x6;
> > -		break;
> > -	case DRM_MODE_COLORIMETRY_BT2020_YCC:
> > -		vsc_sdp.db[16] |= 0x7;
> > -		break;
> > -	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
> > -	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
> > -		vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */
> > -		break;
> > -	default:
> > -		/* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h
> > */
> > -
> > -		/* RGB->YCBCR color conversion uses the BT.709 color
> > space. */
> > -		if (crtc_state->output_format ==
> > INTEL_OUTPUT_FORMAT_YCBCR420)
> > -			vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
> > -		break;
> > -	}
> > -
> > -	/*
> > -	 * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and
> > Y Only,
> > -	 * the following Component Bit Depth values are defined:
> > -	 * 001b = 8bpc.
> > -	 * 010b = 10bpc.
> > -	 * 011b = 12bpc.
> > -	 * 100b = 16bpc.
> > -	 */
> > -	switch (crtc_state->pipe_bpp) {
> > -	case 24: /* 8bpc */
> > -		vsc_sdp.db[17] = 0x1;
> > -		break;
> > -	case 30: /* 10bpc */
> > -		vsc_sdp.db[17] = 0x2;
> > -		break;
> > -	case 36: /* 12bpc */
> > -		vsc_sdp.db[17] = 0x3;
> > -		break;
> > -	case 48: /* 16bpc */
> > -		vsc_sdp.db[17] = 0x4;
> > -		break;
> > -	default:
> > -		MISSING_CASE(crtc_state->pipe_bpp);
> > -		break;
> > -	}
> > -
> > -	/*
> > -	 * Dynamic Range (Bit 7)
> > -	 * 0 = VESA range, 1 = CTA range.
> > -	 * all YCbCr are always limited range
> > -	 */
> > -	vsc_sdp.db[17] |= 0x80;
> > -
> > -	/*
> > -	 * Content Type (Bits 2:0)
> > -	 * 000b = Not defined.
> > -	 * 001b = Graphics.
> > -	 * 010b = Photo.
> > -	 * 011b = Video.
> > -	 * 100b = Game
> > -	 * All other values are RESERVED.
> > -	 * Note: See CTA-861-G for the definition and expected
> > -	 * processing by a stream sink for the above contect types.
> > -	 */
> > -	vsc_sdp.db[18] = 0;
> > -
> > -	intel_dig_port->write_infoframe(&intel_dig_port->base,
> > -			crtc_state, DP_SDP_VSC, &vsc_sdp,
> > sizeof(vsc_sdp));
> > -}
> > -
> > -static void
> > -intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp
> > *intel_dp,
> > -					  const struct intel_crtc_state
> > *crtc_state,
> > -					  const struct
> > drm_connector_state
> > *conn_state)
> > -{
> > -	struct intel_digital_port *intel_dig_port =
> > dp_to_dig_port(intel_dp);
> > -	struct dp_sdp infoframe_sdp = {};
> > -	struct hdmi_drm_infoframe drm_infoframe = {};
> > -	const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE +
> > HDMI_DRM_INFOFRAME_SIZE;
> > -	unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE +
> > HDMI_DRM_INFOFRAME_SIZE];
> > -	ssize_t len;
> > -	int ret;
> > -
> > -	ret = drm_hdmi_infoframe_set_hdr_metadata(&drm_infoframe,
> > conn_state);
> > -	if (ret) {
> > -		DRM_DEBUG_KMS("couldn't set HDR metadata in
> > infoframe\n");
> > -		return;
> > -	}
> > -
> > -	len = hdmi_drm_infoframe_pack_only(&drm_infoframe, buf,
> > sizeof(buf));
> > -	if (len < 0) {
> > -		DRM_DEBUG_KMS("buffer size is smaller than hdr metadata
> > infoframe\n");
> > -		return;
> > -	}
> > -
> > -	if (len != infoframe_size) {
> > -		DRM_DEBUG_KMS("wrong static hdr metadata size\n");
> > -		return;
> > -	}
> > -
> > -	/*
> > -	 * Set up the infoframe sdp packet for HDR static metadata.
> > -	 * Prepare VSC Header for SU as per DP 1.4a spec,
> > -	 * Table 2-100 and Table 2-101
> > -	 */
> > -
> > -	/* Packet ID, 00h for non-Audio INFOFRAME */
> > -	infoframe_sdp.sdp_header.HB0 = 0;
> > -	/*
> > -	 * Packet Type 80h + Non-audio INFOFRAME Type value
> > -	 * HDMI_INFOFRAME_TYPE_DRM: 0x87,
> > -	 */
> > -	infoframe_sdp.sdp_header.HB1 = drm_infoframe.type;
> > -	/*
> > -	 * Least Significant Eight Bits of (Data Byte Count – 1)
> > -	 * infoframe_size - 1,
> > -	 */
> > -	infoframe_sdp.sdp_header.HB2 = 0x1D;
> > -	/* INFOFRAME SDP Version Number */
> > -	infoframe_sdp.sdp_header.HB3 = (0x13 << 2);
> > -	/* CTA Header Byte 2 (INFOFRAME Version Number) */
> > -	infoframe_sdp.db[0] = drm_infoframe.version;
> > -	/* CTA Header Byte 3 (Length of INFOFRAME):
> > HDMI_DRM_INFOFRAME_SIZE */
> > -	infoframe_sdp.db[1] = drm_infoframe.length;
> > -	/*
> > -	 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
> > -	 * HDMI_INFOFRAME_HEADER_SIZE
> > -	 */
> > -	BUILD_BUG_ON(sizeof(infoframe_sdp.db) < HDMI_DRM_INFOFRAME_SIZE
> > + 2);
> > -	memcpy(&infoframe_sdp.db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
> > -	       HDMI_DRM_INFOFRAME_SIZE);
> > -
> > -	/*
> > -	 * Size of DP infoframe sdp packet for HDR static metadata is
> > consist of
> > -	 * - DP SDP Header(struct dp_sdp_header): 4 bytes
> > -	 * - Two Data Blocks: 2 bytes
> > -	 *    CTA Header Byte2 (INFOFRAME Version Number)
> > -	 *    CTA Header Byte3 (Length of INFOFRAME)
> > -	 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
> > -	 *
> > -	 * Prior to GEN11's GMP register size is identical to DP HDR
> > static metadata
> > -	 * infoframe size. But GEN11+ has larger than that size,
> > write_infoframe
> > -	 * will pad rest of the size.
> > -	 */
> > -	intel_dig_port->write_infoframe(&intel_dig_port->base,
> > crtc_state,
> > -					HDMI_PACKET_TYPE_GAMUT_METADATA
> > ,
> > -					&infoframe_sdp,
> > -					sizeof(struct dp_sdp_header) +
> > 2 +
> > HDMI_DRM_INFOFRAME_SIZE);
> > -}
> > -
> > -void intel_dp_vsc_enable(struct intel_dp *intel_dp,
> > -			 const struct intel_crtc_state *crtc_state,
> > -			 const struct drm_connector_state *conn_state)
> > -{
> > -	if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
> > -		return;
> > -
> > -	intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);
> > -}
> > -
> > -void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
> > -				  const struct intel_crtc_state
> > *crtc_state,
> > -				  const struct drm_connector_state
> > *conn_state)
> > -{
> > -	if (!conn_state->hdr_output_metadata)
> > -		return;
> > -
> > -	intel_dp_setup_hdr_metadata_infoframe_sdp(intel_dp,
> > -						  crtc_state,
> > -						  conn_state);
> > -}
> > -
> >  static u8 intel_dp_autotest_link_training(struct intel_dp
> > *intel_dp)  {
> >  	int status = 0;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> > b/drivers/gpu/drm/i915/display/intel_dp.h
> > index e8f9ba962d09..6562bb8edeba 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > @@ -110,12 +110,6 @@ int intel_dp_link_required(int pixel_clock,
> > int bpp);  int
> > intel_dp_max_data_rate(int max_link_clock, int max_lanes);  bool
> > intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
> >  			    const struct drm_connector_state
> > *conn_state); -void
> > intel_dp_vsc_enable(struct intel_dp *intel_dp,
> > -			 const struct intel_crtc_state *crtc_state,
> > -			 const struct drm_connector_state *conn_state);
> > -void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
> > -				  const struct intel_crtc_state
> > *crtc_state,
> > -				  const struct drm_connector_state
> > *conn_state);
> >  void intel_dp_set_infoframes(struct intel_encoder *encoder, bool
> > enable,
> >  			     const struct intel_crtc_state *crtc_state,
> >  			     const struct drm_connector_state
> > *conn_state);
> > --
> > 2.24.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

RE: [PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs (Secondary Data Packet)

[Shankar, Uma]

DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogTXVuLCBHd2FuLWd5ZW9u
ZyA8Z3dhbi1neWVvbmcubXVuQGludGVsLmNvbT4NCj4gU2VudDogU3VuZGF5LCBGZWJydWFyeSA5
LCAyMDIwIDk6MDUgQU0NCj4gVG86IFNoYW5rYXIsIFVtYSA8dW1hLnNoYW5rYXJAaW50ZWwuY29t
PjsgaW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZw0KPiBDYzogZHJpLWRldmVsQGxpc3Rz
LmZyZWVkZXNrdG9wLm9yZzsgbGludXgtZmJkZXZAdmdlci5rZXJuZWwub3JnDQo+IFN1YmplY3Q6
IFJlOiBbUEFUQ0ggdjMgMDQvMTddIGRybS9pOTE1L2RwOiBBZGQgd3JpdGluZyBvZiBEUCBTRFBz
IChTZWNvbmRhcnkgRGF0YQ0KPiBQYWNrZXQpDQo+IA0KPiBPbiBXZWQsIDIwMjAtMDItMDUgYXQg
MjE6MzkgKzA1MzAsIFNoYW5rYXIsIFVtYSB3cm90ZToNCj4gPiA+IC0tLS0tT3JpZ2luYWwgTWVz
c2FnZS0tLS0tDQo+ID4gPiBGcm9tOiBkcmktZGV2ZWwgPGRyaS1kZXZlbC1ib3VuY2VzQGxpc3Rz
LmZyZWVkZXNrdG9wLm9yZz4gT24gQmVoYWxmDQo+ID4gPiBPZiBHd2FuLSBneWVvbmcgTXVuDQo+
ID4gPiBTZW50OiBUdWVzZGF5LCBGZWJydWFyeSA0LCAyMDIwIDQ6NTAgQU0NCj4gPiA+IFRvOiBp
bnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnDQo+ID4gPiBDYzogbGludXgtZmJkZXZAdmdl
ci5rZXJuZWwub3JnOyBkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnDQo+ID4gPiBTdWJq
ZWN0OiBbUEFUQ0ggdjMgMDQvMTddIGRybS9pOTE1L2RwOiBBZGQgd3JpdGluZyBvZiBEUCBTRFBz
DQo+ID4gPiAoU2Vjb25kYXJ5IERhdGENCj4gPiA+IFBhY2tldCkNCj4gPg0KPiA+IERyb3AgdGhp
bmdzIGluICgpLCBub3QgbmVlZGVkLg0KPiA+DQo+ID4gPiBJdCBhZGRzIHJvdXRpbmVzIHRoYXQg
d3JpdGUgRFAgVlNDIFNEUCBhbmQgRFAgSERSIE1ldGFkYXRhIEluZm9mcmFtZQ0KPiA+ID4gU0RQ
Lg0KPiA+ID4gSW4gb3JkZXIgdG8gcGFjayBEUCBWU0MgU0RQLCBpdCBhZGRzIGludGVsX2RwX3Zz
Y19zZHBfcGFjaygpDQo+ID4gPiBmdW5jdGlvbi4NCj4gPiA+IEl0IGZvbGxvd3MgRFAgMS40YSBz
cGVjLiBbVGFibGUgMi0xMTY6IFZTQyBTRFAgSGVhZGVyIEJ5dGVzXSBhbmQNCj4gPiA+IFtUYWJs
ZSAyLTExNzogVlNDIFNEUCBQYXlsb2FkIGZvciBEQjE2IHRocm91Z2ggREIxOF0NCj4gPiA+DQo+
ID4gPiBJbiBvcmRlciB0byBwYWNrIERQIEhEUiBNZXRhZGF0YSBJbmZvZnJhbWUgU0RQLCBpdCBh
ZGRzDQo+ID4gPiBpbnRlbF9kcF9oZHJfbWV0YWRhdGFfaW5mb2ZyYW1lX3NkcF9wYWNrKCkgZnVu
Y3Rpb24uDQo+ID4gPiBBbmQgaXQgZm9sbG93cyBEUCAxLjRhIHNwZWMuDQo+ID4gPiAoW1RhYmxl
IDItMTI1OiBJTkZPRlJBTUUgU0RQIHYxLjIgSGVhZGVyIEJ5dGVzXSBhbmQgW1RhYmxlIDItMTI2
Og0KPiA+ID4gSU5GT0ZSQU1FDQo+ID4gPiBTRFAgdjEuMiBQYXlsb2FkIERhdGEgQnl0ZXMgLSBE
QjAgdGhyb3VnaCBEQjMxXSkgYW5kIENUQS04NjEtRyBzcGVjLg0KPiA+ID4gW1RhYmxlLTQyIER5
bmFtaWMgUmFuZ2UgYW5kIE1hc3RlcmluZyBJbmZvRnJhbWVdLg0KPiA+ID4NCj4gPiA+IEEgbWFj
aGFuaXNtIGFuZCBhIG5hbWluZyBydWxlIG9mIGludGVsX2RwX3NldF9pbmZvZnJhbWVzKCkgZnVu
Y3Rpb24NCj4gPiA+IHJlZmVyZW5jZXMNCj4gPg0KPiA+IFR5cG8gaW4gbWVjaGFuaXNtLg0KPiA+
DQo+ID4gPiBpbnRlbF9lbmNvZGVyLT5zZXRfaW5mb2ZyYW1lcygpIG9mIGludGVsX2hkbWkuYyAu
DQo+ID4gPiBWU0MgU0RQIGlzIHVzZWQgZm9yIFBTUiBhbmQgUGl4ZWwgRW5jb2RpbmcgYW5kIENv
bG9yaW1ldHJ5IEZvcm1hdHMNCj4gPiA+IGNhc2VzLg0KPiA+ID4gQmVjYXVzZSBQU1Igcm91dGlu
ZSBoYXMgaXRzIG93biByb3V0aW5lIG9mIHdyaXRpbmcgYSBWU0MgU0RQLCB3aGVuDQo+ID4gPiB0
aGUgUFNSIGlzIGVuYWJsZWQsIGludGVsX2RwX3NldF9pbmZvZnJhbWVzKCkgZG9lcyBub3Qgd3Jp
dGUgYSBWU0MNCj4gPiA+IFNEUC4NCj4gPiA+DQo+ID4gPiB2MzoNCj4gPiA+ICAgLSBFeHBsaWNp
dGx5IGRpc2FibGUgdW51c2VkIERJUHMgKEFWSSwgR0NQLCBWUywgU1BELCBEUk0uIFRoZXkNCj4g
PiA+IHdpbGwgYmUNCj4gPiA+ICAgICB1c2VkIGZvciBIRE1JKSwgd2hlbiBpbnRlbF9kcF9zZXRf
aW5mb2ZyYW1lcygpIGZ1bmN0aW9uIHdpbGwgYmUNCj4gPiA+IGNhbGxlZC4NCj4gPiA+ICAgLSBS
ZXBsYWNlIGEgc3RydWN0dXJlIG5hbWUgdG8gZHJtX2RwX3ZzY19zZHAgZnJvbQ0KPiA+ID4gaW50
ZWxfZHBfdnNjX3NkcC4NCj4gPiA+DQo+ID4gPiBTaWduZWQtb2ZmLWJ5OiBHd2FuLWd5ZW9uZyBN
dW4gPGd3YW4tZ3llb25nLm11bkBpbnRlbC5jb20+DQo+ID4gPiAtLS0NCj4gPiA+ICBkcml2ZXJz
L2dwdS9kcm0vaTkxNS9kaXNwbGF5L2ludGVsX2RwLmMgfCAxOTQNCj4gPiA+ICsrKysrKysrKysr
KysrKysrKysrKysrKw0KPiA+ID4gIGRyaXZlcnMvZ3B1L2RybS9pOTE1L2Rpc3BsYXkvaW50ZWxf
ZHAuaCB8ICAgMyArDQo+ID4gPiAgMiBmaWxlcyBjaGFuZ2VkLCAxOTcgaW5zZXJ0aW9ucygrKQ0K
PiA+ID4NCj4gPiA+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9kaXNwbGF5L2lu
dGVsX2RwLmMNCj4gPiA+IGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9kcC5j
DQo+ID4gPiBpbmRleCBiMjY1YjVjNTk5ZjIuLmRkN2U1NTg4MDAxZSAxMDA2NDQNCj4gPiA+IC0t
LSBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2Rpc3BsYXkvaW50ZWxfZHAuYw0KPiA+ID4gKysrIGIv
ZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9kcC5jDQo+ID4gPiBAQCAtNDczMSw2
ICs0NzMxLDIwMCBAQCBpbnRlbF9kcF9uZWVkc192c2Nfc2RwKGNvbnN0IHN0cnVjdA0KPiA+ID4g
aW50ZWxfY3J0Y19zdGF0ZSAqY3J0Y19zdGF0ZSwNCj4gPiA+ICAJcmV0dXJuIGZhbHNlOw0KPiA+
ID4gIH0NCj4gPiA+DQo+ID4gPiArc3RhdGljIHNzaXplX3QgaW50ZWxfZHBfdnNjX3NkcF9wYWNr
KGNvbnN0IHN0cnVjdCBkcm1fZHBfdnNjX3NkcA0KPiA+ID4gKnZzYywNCj4gPiA+ICsJCQkJICAg
ICBzdHJ1Y3QgZHBfc2RwICpzZHAsIHNpemVfdCBzaXplKSB7DQo+ID4gPiArCXNpemVfdCBsZW5n
dGggPSBzaXplb2Yoc3RydWN0IGRwX3NkcCk7DQo+ID4gPiArDQo+ID4gPiArCWlmIChzaXplIDwg
bGVuZ3RoKQ0KPiA+ID4gKwkJcmV0dXJuIC1FTk9TUEM7DQo+ID4gPiArDQo+ID4gPiArCW1lbXNl
dChzZHAsIDAsIHNpemUpOw0KPiA+ID4gKw0KPiA+ID4gKwkvKg0KPiA+ID4gKwkgKiBQcmVwYXJl
IFZTQyBIZWFkZXIgZm9yIFNVIGFzIHBlciBEUCAxLjRhIHNwZWMsIFRhYmxlIDItMTE5DQo+ID4g
PiArCSAqIFZTQyBTRFAgSGVhZGVyIEJ5dGVzDQo+ID4gPiArCSAqLw0KPiA+ID4gKwlzZHAtPnNk
cF9oZWFkZXIuSEIwID0gMDsgLyogU2Vjb25kYXJ5LURhdGEgUGFja2V0IElEID0gMCAqLw0KPiA+
ID4gKwlzZHAtPnNkcF9oZWFkZXIuSEIxID0gdnNjLT5zZHBfdHlwZTsgLyogU2Vjb25kYXJ5LWRh
dGEgUGFja2V0DQo+ID4gPiBUeXBlICovDQo+ID4gPiArCXNkcC0+c2RwX2hlYWRlci5IQjIgPSB2
c2MtPnJldmlzaW9uOyAvKiBSZXZpc2lvbiBOdW1iZXIgKi8NCj4gPiA+ICsJc2RwLT5zZHBfaGVh
ZGVyLkhCMyA9IHZzYy0+bGVuZ3RoOyAvKiBOdW1iZXIgb2YgVmFsaWQgRGF0YQ0KPiA+ID4gQnl0
ZXMgKi8NCj4gPiA+ICsNCj4gPiA+ICsJLyogVlNDIFNEUCBQYXlsb2FkIGZvciBEQjE2IHRocm91
Z2ggREIxOCAqLw0KPiA+ID4gKwkvKiBQaXhlbCBFbmNvZGluZyBhbmQgQ29sb3JpbWV0cnkgRm9y
bWF0cyAgKi8NCj4gPiA+ICsJc2RwLT5kYlsxNl0gPSAodnNjLT5jb2xvcnNwYWNlICYgMHhmKSA8
PCA0OyAvKiBEQjE2Wzc6NF0gKi8NCj4gPiA+ICsJc2RwLT5kYlsxNl0gfD0gdnNjLT5jb2xvcmlt
ZXRyeSAmIDB4ZjsgLyogREIxNlszOjBdICovDQo+ID4gPiArDQo+ID4gPiArCXN3aXRjaCAodnNj
LT5icGMpIHsNCj4gPiA+ICsJY2FzZSA4Og0KPiA+ID4gKwkJc2RwLT5kYlsxN10gPSAweDE7IC8q
IERCMTdbMzowXSAqLw0KPiA+ID4gKwkJYnJlYWs7DQo+ID4gPiArCWNhc2UgMTA6DQo+ID4gPiAr
CQlzZHAtPmRiWzE3XSA9IDB4MjsNCj4gPiA+ICsJCWJyZWFrOw0KPiA+ID4gKwljYXNlIDEyOg0K
PiA+ID4gKwkJc2RwLT5kYlsxN10gPSAweDM7DQo+ID4gPiArCQlicmVhazsNCj4gPiA+ICsJY2Fz
ZSAxNjoNCj4gPiA+ICsJCXNkcC0+ZGJbMTddID0gMHg0Ow0KPiA+ID4gKwkJYnJlYWs7DQo+ID4g
PiArCWRlZmF1bHQ6DQo+ID4gPiArCQlNSVNTSU5HX0NBU0UodnNjLT5icGMpOw0KPiA+DQo+ID4g
NmJwYyBpcyBub3QgaGFuZGxlZCBoZXJlLCBhZGQgdGhhdCBhcyB3ZWxsLg0KPiA+DQo+IFllcywg
SSBtaXNzZWQgNmJwYyBjYXNlLCBJJ2xsIHVwZGF0ZSBpdC4NCj4gPiA+ICsJCWJyZWFrOw0KPiA+
ID4gKwl9DQo+ID4gPiArCS8qIER5bmFtaWMgUmFuZ2UgYW5kIENvbXBvbmVudCBCaXQgRGVwdGgg
Ki8NCj4gPiA+ICsJaWYgKHZzYy0+ZHluYW1pY19yYW5nZSA9PSBEUF9EWU5BTUlDX1JBTkdFX0NU
QSkNCj4gPiA+ICsJCXNkcC0+ZGJbMTddIHw9IDB4ODA7ICAvKiBEQjE3WzddICovDQo+ID4gPiAr
DQo+ID4gPiArCS8qIENvbnRlbnQgVHlwZSAqLw0KPiA+ID4gKwlzZHAtPmRiWzE4XSA9IHZzYy0+
Y29udGVudF90eXBlICYgMHg3Ow0KPiA+ID4gKw0KPiA+ID4gKwlyZXR1cm4gbGVuZ3RoOw0KPiA+
ID4gK30NCj4gPiA+ICsNCj4gPiA+ICtzdGF0aWMgc3NpemVfdA0KPiA+ID4gK2ludGVsX2RwX2hk
cl9tZXRhZGF0YV9pbmZvZnJhbWVfc2RwX3BhY2soY29uc3Qgc3RydWN0DQo+ID4gPiBoZG1pX2Ry
bV9pbmZvZnJhbWUNCj4gPiA+ICpkcm1faW5mb2ZyYW1lLA0KPiA+ID4gKwkJCQkJIHN0cnVjdCBk
cF9zZHAgKnNkcCwNCj4gPiA+ICsJCQkJCSBzaXplX3Qgc2l6ZSkNCj4gPiA+ICt7DQo+ID4gPiAr
CXNpemVfdCBsZW5ndGggPSBzaXplb2Yoc3RydWN0IGRwX3NkcCk7DQo+ID4gPiArCWNvbnN0IGlu
dCBpbmZvZnJhbWVfc2l6ZSA9IEhETUlfSU5GT0ZSQU1FX0hFQURFUl9TSVpFICsNCj4gPiA+IEhE
TUlfRFJNX0lORk9GUkFNRV9TSVpFOw0KPiA+ID4gKwl1bnNpZ25lZCBjaGFyIGJ1ZltIRE1JX0lO
Rk9GUkFNRV9IRUFERVJfU0laRSArDQo+ID4gPiBIRE1JX0RSTV9JTkZPRlJBTUVfU0laRV07DQo+
ID4gPiArCXNzaXplX3QgbGVuOw0KPiA+ID4gKw0KPiA+ID4gKwlpZiAoc2l6ZSA8IGxlbmd0aCkN
Cj4gPiA+ICsJCXJldHVybiAtRU5PU1BDOw0KPiA+ID4gKw0KPiA+ID4gKwltZW1zZXQoc2RwLCAw
LCBzaXplKTsNCj4gPiA+ICsNCj4gPiA+ICsJbGVuID0gaGRtaV9kcm1faW5mb2ZyYW1lX3BhY2tf
b25seShkcm1faW5mb2ZyYW1lLCBidWYsDQo+ID4gPiBzaXplb2YoYnVmKSk7DQo+ID4gPiArCWlm
IChsZW4gPCAwKSB7DQo+ID4gPiArCQlEUk1fREVCVUdfS01TKCJidWZmZXIgc2l6ZSBpcyBzbWFs
bGVyIHRoYW4gaGRyIG1ldGFkYXRhDQo+ID4gPiBpbmZvZnJhbWVcbiIpOw0KPiA+ID4gKwkJcmV0
dXJuIC1FTk9TUEM7DQo+ID4gPiArCX0NCj4gPiA+ICsNCj4gPiA+ICsJaWYgKGxlbiAhPSBpbmZv
ZnJhbWVfc2l6ZSkgew0KPiA+ID4gKwkJRFJNX0RFQlVHX0tNUygid3Jvbmcgc3RhdGljIGhkciBt
ZXRhZGF0YSBzaXplXG4iKTsNCj4gPiA+ICsJCXJldHVybiAtRU5PU1BDOw0KPiA+ID4gKwl9DQo+
ID4gPiArDQo+ID4gPiArCS8qDQo+ID4gPiArCSAqIFNldCB1cCB0aGUgaW5mb2ZyYW1lIHNkcCBw
YWNrZXQgZm9yIEhEUiBzdGF0aWMgbWV0YWRhdGEuDQo+ID4gPiArCSAqIFByZXBhcmUgVlNDIEhl
YWRlciBmb3IgU1UgYXMgcGVyIERQIDEuNGEgc3BlYywNCj4gPiA+ICsJICogVGFibGUgMi0xMDAg
YW5kIFRhYmxlIDItMTAxDQo+ID4gPiArCSAqLw0KPiA+ID4gKw0KPiA+ID4gKwkvKiBTZWNvbmRh
cnktRGF0YSBQYWNrZXQgSUQsIDAwaCBmb3Igbm9uLUF1ZGlvIElORk9GUkFNRSAqLw0KPiA+ID4g
KwlzZHAtPnNkcF9oZWFkZXIuSEIwID0gMDsNCj4gPiA+ICsJLyoNCj4gPiA+ICsJICogUGFja2V0
IFR5cGUgODBoICsgTm9uLWF1ZGlvIElORk9GUkFNRSBUeXBlIHZhbHVlDQo+ID4gPiArCSAqIEhE
TUlfSU5GT0ZSQU1FX1RZUEVfRFJNOiAweDg3DQo+ID4gPiArCSAqIC0gODBoICsgTm9uLWF1ZGlv
IElORk9GUkFNRSBUeXBlIHZhbHVlDQo+ID4gPiArCSAqIC0gSW5mb0ZyYW1lIFR5cGU6IDB4MDcN
Cj4gPiA+ICsJICogICAgW0NUQS04NjEtRyBUYWJsZS00MiBEeW5hbWljIFJhbmdlIGFuZCBNYXN0
ZXJpbmcNCj4gPiA+IEluZm9GcmFtZV0NCj4gPiA+ICsJICovDQo+ID4gPiArCXNkcC0+c2RwX2hl
YWRlci5IQjEgPSBkcm1faW5mb2ZyYW1lLT50eXBlOw0KPiA+ID4gKwkvKg0KPiA+ID4gKwkgKiBM
ZWFzdCBTaWduaWZpY2FudCBFaWdodCBCaXRzIG9mIChEYXRhIEJ5dGUgQ291bnQg4oCTIDEpDQo+
ID4gPiArCSAqIGluZm9mcmFtZV9zaXplIC0gMQ0KPiA+ID4gKwkgKi8NCj4gPiA+ICsJc2RwLT5z
ZHBfaGVhZGVyLkhCMiA9IDB4MUQ7DQo+ID4gPiArCS8qIElORk9GUkFNRSBTRFAgVmVyc2lvbiBO
dW1iZXIgKi8NCj4gPiA+ICsJc2RwLT5zZHBfaGVhZGVyLkhCMyA9ICgweDEzIDw8IDIpOw0KPiA+
ID4gKwkvKiBDVEEgSGVhZGVyIEJ5dGUgMiAoSU5GT0ZSQU1FIFZlcnNpb24gTnVtYmVyKSAqLw0K
PiA+ID4gKwlzZHAtPmRiWzBdID0gZHJtX2luZm9mcmFtZS0+dmVyc2lvbjsNCj4gPiA+ICsJLyog
Q1RBIEhlYWRlciBCeXRlIDMgKExlbmd0aCBvZiBJTkZPRlJBTUUpOg0KPiA+ID4gSERNSV9EUk1f
SU5GT0ZSQU1FX1NJWkUgKi8NCj4gPiA+ICsJc2RwLT5kYlsxXSA9IGRybV9pbmZvZnJhbWUtPmxl
bmd0aDsNCj4gPiA+ICsJLyoNCj4gPiA+ICsJICogQ29weSBIRE1JX0RSTV9JTkZPRlJBTUVfU0la
RSBzaXplIGZyb20gYSBidWZmZXIgYWZ0ZXINCj4gPg0KPiA+IENvbW1lbnQgTG9va3MgaW5jb21w
bGV0ZS4NCj4gPg0KPiBJIG1pc3NlZCBzb21lIGNvbW1lbnRzLCBJJ2xsIHVwZGF0ZSBpdC4NCj4g
PiA+ICsJICovDQo+ID4gPiArCUJVSUxEX0JVR19PTihzaXplb2Yoc2RwLT5kYikgPCBIRE1JX0RS
TV9JTkZPRlJBTUVfU0laRSArIDIpOw0KPiA+ID4gKwltZW1jcHkoJnNkcC0+ZGJbMl0sICZidWZb
SERNSV9JTkZPRlJBTUVfSEVBREVSX1NJWkVdLA0KPiA+ID4gKwkgICAgICAgSERNSV9EUk1fSU5G
T0ZSQU1FX1NJWkUpOw0KPiA+ID4gKw0KPiA+ID4gKwkvKg0KPiA+ID4gKwkgKiBTaXplIG9mIERQ
IGluZm9mcmFtZSBzZHAgcGFja2V0IGZvciBIRFIgc3RhdGljIG1ldGFkYXRhIGlzDQo+ID4gPiBj
b25zaXN0IG9mDQo+ID4NCj4gPiBEcm9wICJpcyINCj4gPg0KPiBJbmNsdWRlcyB0aGlzLCBJJ2xs
IHBvbGlzaCBwb2xpc2ggY29tbWl0IG1lc3NhZ2UgYW5kIGNvbW1lbnRzLg0KPiANCj4gPiA+ICsJ
ICogLSBEUCBTRFAgSGVhZGVyKHN0cnVjdCBkcF9zZHBfaGVhZGVyKTogNCBieXRlcw0KPiA+ID4g
KwkgKiAtIFR3byBEYXRhIEJsb2NrczogMiBieXRlcw0KPiA+ID4gKwkgKiAgICBDVEEgSGVhZGVy
IEJ5dGUyIChJTkZPRlJBTUUgVmVyc2lvbiBOdW1iZXIpDQo+ID4gPiArCSAqICAgIENUQSBIZWFk
ZXIgQnl0ZTMgKExlbmd0aCBvZiBJTkZPRlJBTUUpDQo+ID4gPiArCSAqIC0gSERNSV9EUk1fSU5G
T0ZSQU1FX1NJWkU6IDI2IGJ5dGVzDQo+ID4gPiArCSAqDQo+ID4gPiArCSAqIFByaW9yIHRvIEdF
TjExJ3MgR01QIHJlZ2lzdGVyIHNpemUgaXMgaWRlbnRpY2FsIHRvIERQIEhEUg0KPiA+ID4gc3Rh
dGljIG1ldGFkYXRhDQo+ID4gPiArCSAqIGluZm9mcmFtZSBzaXplLiBCdXQgR0VOMTErIGhhcyBs
YXJnZXIgdGhhbiB0aGF0IHNpemUsDQo+ID4gPiB3cml0ZV9pbmZvZnJhbWUNCj4gPiA+ICsJICog
d2lsbCBwYWQgcmVzdCBvZiB0aGUgc2l6ZS4NCj4gPiA+ICsJICovDQo+ID4gPiArCXJldHVybiBz
aXplb2Yoc3RydWN0IGRwX3NkcF9oZWFkZXIpICsgMiArDQo+ID4gPiBIRE1JX0RSTV9JTkZPRlJB
TUVfU0laRTsgfQ0KPiA+ID4gKw0KPiA+ID4gK3N0YXRpYyB2b2lkIGludGVsX3dyaXRlX2RwX3Nk
cChzdHJ1Y3QgaW50ZWxfZW5jb2RlciAqZW5jb2RlciwNCj4gPiA+ICsJCQkgICAgICAgY29uc3Qg
c3RydWN0IGludGVsX2NydGNfc3RhdGUNCj4gPiA+ICpjcnRjX3N0YXRlLA0KPiA+ID4gKwkJCSAg
ICAgICB1bnNpZ25lZCBpbnQgdHlwZSkNCj4gPiA+ICt7DQo+ID4gPiArCXN0cnVjdCBpbnRlbF9k
aWdpdGFsX3BvcnQgKmludGVsX2RpZ19wb3J0ID0NCj4gPiA+IGVuY190b19kaWdfcG9ydChlbmNv
ZGVyKTsNCj4gPiA+ICsJc3RydWN0IGRwX3NkcCBzZHAgPSB7fTsNCj4gPiA+ICsJc3NpemVfdCBs
ZW47DQo+ID4gPiArDQo+ID4gPiArCWlmICgoY3J0Y19zdGF0ZS0+aW5mb2ZyYW1lcy5lbmFibGUg
Jg0KPiA+ID4gKwkgICAgIGludGVsX2hkbWlfaW5mb2ZyYW1lX2VuYWJsZSh0eXBlKSkgPT0gMCkN
Cj4gPiA+ICsJCXJldHVybjsNCj4gPiA+ICsNCj4gPiA+ICsJc3dpdGNoICh0eXBlKSB7DQo+ID4g
PiArCWNhc2UgRFBfU0RQX1ZTQzoNCj4gPiA+ICsJCWxlbiA9IGludGVsX2RwX3ZzY19zZHBfcGFj
aygmY3J0Y19zdGF0ZS0NCj4gPiA+ID5pbmZvZnJhbWVzLnZzYywgJnNkcCwNCj4gPiA+ICsJCQkJ
CSAgICBzaXplb2Yoc2RwKSk7DQo+ID4gPiArCQlicmVhazsNCj4gPiA+ICsJY2FzZSBIRE1JX1BB
Q0tFVF9UWVBFX0dBTVVUX01FVEFEQVRBOg0KPiA+ID4gKwkJbGVuID0NCj4gPiA+IGludGVsX2Rw
X2hkcl9tZXRhZGF0YV9pbmZvZnJhbWVfc2RwX3BhY2soJmNydGNfc3RhdGUtDQo+ID4gPiA+IGlu
Zm9mcmFtZXMuZHJtLmRybSwNCj4gPiA+ICsJCQkJCQkJICAgICAgICZzZHAsDQo+ID4gPiBzaXpl
b2Yoc2RwKSk7DQo+ID4gPiArCQlicmVhazsNCj4gPiA+ICsJZGVmYXVsdDoNCj4gPiA+ICsJCU1J
U1NJTkdfQ0FTRSh0eXBlKTsNCj4gPiA+ICsJCWJyZWFrOw0KPiA+ID4gKwl9DQo+ID4gPiArDQo+
ID4gPiArCWlmIChXQVJOX09OKGxlbiA8IDApKQ0KPiA+ID4gKwkJcmV0dXJuOw0KPiA+ID4gKw0K
PiA+ID4gKwlpbnRlbF9kaWdfcG9ydC0+d3JpdGVfaW5mb2ZyYW1lKGVuY29kZXIsIGNydGNfc3Rh
dGUsIHR5cGUsDQo+ID4gPiAmc2RwLCBsZW4pOw0KPiA+ID4gK30NCj4gPiA+ICsNCj4gPiA+ICt2
b2lkIGludGVsX2RwX3NldF9pbmZvZnJhbWVzKHN0cnVjdCBpbnRlbF9lbmNvZGVyICplbmNvZGVy
LA0KPiA+ID4gKwkJCSAgICAgYm9vbCBlbmFibGUsDQo+ID4gPiArCQkJICAgICBjb25zdCBzdHJ1
Y3QgaW50ZWxfY3J0Y19zdGF0ZSAqY3J0Y19zdGF0ZSwNCj4gPiA+ICsJCQkgICAgIGNvbnN0IHN0
cnVjdCBkcm1fY29ubmVjdG9yX3N0YXRlDQo+ID4gPiAqY29ubl9zdGF0ZSkgew0KPiA+ID4gKwlz
dHJ1Y3QgZHJtX2k5MTVfcHJpdmF0ZSAqZGV2X3ByaXYgPSB0b19pOTE1KGVuY29kZXItPmJhc2Uu
ZGV2KTsNCj4gPiA+ICsJc3RydWN0IGludGVsX2RwICppbnRlbF9kcCA9IGVuY190b19pbnRlbF9k
cChlbmNvZGVyKTsNCj4gPiA+ICsJaTkxNV9yZWdfdCByZWcgPSBIU1dfVFZJREVPX0RJUF9DVEwo
Y3J0Y19zdGF0ZS0NCj4gPiA+ID5jcHVfdHJhbnNjb2Rlcik7DQo+ID4gPiArCXUzMiBkaXBfZW5h
YmxlID0gVklERU9fRElQX0VOQUJMRV9BVklfSFNXIHwNCj4gPiA+IFZJREVPX0RJUF9FTkFCTEVf
R0NQX0hTVyB8DQo+ID4gPiArCQkJIFZJREVPX0RJUF9FTkFCTEVfVlNfSFNXIHwNCj4gPiA+IFZJ
REVPX0RJUF9FTkFCTEVfR01QX0hTVyB8DQo+ID4gPiArCQkJIFZJREVPX0RJUF9FTkFCTEVfU1BE
X0hTVyB8DQo+ID4gPiBWSURFT19ESVBfRU5BQkxFX0RSTV9HTEs7DQo+ID4gPiArCXUzMiB2YWwg
PSBJOTE1X1JFQUQocmVnKTsNCj4gPiA+ICsNCj4gPiA+ICsJLyogVE9ETzogQWRkIERTQyBjYXNl
IChESVBfRU5BQkxFX1BQUykgKi8NCj4gPiA+ICsJLyogV2hlbiBQU1IgaXMgZW5hYmxlZCwgdGhp
cyByb3V0aW5lIGRvZXNuJ3QgZGlzYWJsZSBWU0MgRElQICovDQo+ID4gPiArCWlmIChpbnRlbF9w
c3JfZW5hYmxlZChpbnRlbF9kcCkpDQo+ID4gPiArCQl2YWwgJj0gfmRpcF9lbmFibGU7DQo+ID4g
PiArCWVsc2UNCj4gPiA+ICsJCXZhbCAmPSB+KGRpcF9lbmFibGUgfCBWSURFT19ESVBfRU5BQkxF
X1ZTQ19IU1cpOw0KPiA+DQo+ID4gZGlwX2VuYWJsZSBoYXMgVklERU9fRElQX0VOQUJMRV9WU0Nf
SFNXIGFscmVhZHkgaW4gaXQuIFBsZWFzZSBmaXgNCj4gPiB0aGlzLg0KPiA+DQo+IERlY2xhcmlu
ZyBvZiBkaXBfZW5hYmxlIGRvZXMgbm90IGluY2x1ZGUgVklERU9fRElQX0VOQUJMRV9WU0NfSFNX
Lg0KPiB0aGVyZWZvcmUgd2UgbmVlZCBpdCBoZXJlIHRvIGRpc2FibGUgVlNDIFNEUCBESVAuDQoN
Ck9oIG9rLCBUb29rIFZTIGZvciBWU0MuIFNjcmF0Y2ggbXkgZWFybGllciBjb21tZW50LCBjaGFu
Z2UgaXMgY29ycmVjdC4NCg0KPiA+ID4gKw0KPiA+ID4gKwlpZiAoIWVuYWJsZSkgew0KPiA+ID4g
KwkJSTkxNV9XUklURShyZWcsIHZhbCk7DQo+ID4gPiArCQlQT1NUSU5HX1JFQUQocmVnKTsNCj4g
PiA+ICsJCXJldHVybjsNCj4gPiA+ICsJfQ0KPiA+ID4gKw0KPiA+ID4gKwlJOTE1X1dSSVRFKHJl
ZywgdmFsKTsNCj4gPiA+ICsJUE9TVElOR19SRUFEKHJlZyk7DQo+ID4gPiArDQo+ID4gPiArCS8q
IFdoZW4gUFNSIGlzIGVuYWJsZWQsIFZTQyBTRFAgaXMgaGFuZGxlZCBieSBQU1Igcm91dGluZSAq
Lw0KPiA+ID4gKwlpZiAoIWludGVsX3Bzcl9lbmFibGVkKGludGVsX2RwKSkNCj4gPiA+ICsJCWlu
dGVsX3dyaXRlX2RwX3NkcChlbmNvZGVyLCBjcnRjX3N0YXRlLCBEUF9TRFBfVlNDKTsNCj4gPiA+
ICsNCj4gPiA+ICsJaW50ZWxfd3JpdGVfZHBfc2RwKGVuY29kZXIsIGNydGNfc3RhdGUsDQo+ID4g
PiArSERNSV9QQUNLRVRfVFlQRV9HQU1VVF9NRVRBREFUQSk7IH0NCj4gPiA+ICsNCj4gPiA+ICBz
dGF0aWMgdm9pZA0KPiA+ID4gIGludGVsX2RwX3NldHVwX3ZzY19zZHAoc3RydWN0IGludGVsX2Rw
ICppbnRlbF9kcCwNCj4gPiA+ICAJCSAgICAgICBjb25zdCBzdHJ1Y3QgaW50ZWxfY3J0Y19zdGF0
ZSAqY3J0Y19zdGF0ZSwgZGlmZiAtLWdpdA0KPiA+ID4gYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9k
aXNwbGF5L2ludGVsX2RwLmgNCj4gPiA+IGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9p
bnRlbF9kcC5oDQo+ID4gPiBpbmRleCAzZGExNjYwNTQ3ODguLjBkYzA5YTQ2M2VlMSAxMDA2NDQN
Cj4gPiA+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2Rpc3BsYXkvaW50ZWxfZHAuaA0KPiA+
ID4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9kcC5oDQo+ID4gPiBA
QCAtMTE2LDYgKzExNiw5IEBAIHZvaWQgaW50ZWxfZHBfdnNjX2VuYWJsZShzdHJ1Y3QgaW50ZWxf
ZHANCj4gPiA+ICppbnRlbF9kcCwgIHZvaWQgaW50ZWxfZHBfaGRyX21ldGFkYXRhX2VuYWJsZShz
dHJ1Y3QgaW50ZWxfZHANCj4gPiA+ICppbnRlbF9kcCwNCj4gPiA+ICAJCQkJICBjb25zdCBzdHJ1
Y3QgaW50ZWxfY3J0Y19zdGF0ZSAqY3J0Y19zdGF0ZSwNCj4gPiA+ICAJCQkJICBjb25zdCBzdHJ1
Y3QgZHJtX2Nvbm5lY3Rvcl9zdGF0ZSAqY29ubl9zdGF0ZSk7DQo+ID4gPiArdm9pZCBpbnRlbF9k
cF9zZXRfaW5mb2ZyYW1lcyhzdHJ1Y3QgaW50ZWxfZW5jb2RlciAqZW5jb2RlciwgYm9vbA0KPiA+
ID4gZW5hYmxlLA0KPiA+ID4gKwkJCSAgICAgY29uc3Qgc3RydWN0IGludGVsX2NydGNfc3RhdGUg
KmNydGNfc3RhdGUsDQo+ID4gPiArCQkJICAgICBjb25zdCBzdHJ1Y3QgZHJtX2Nvbm5lY3Rvcl9z
dGF0ZQ0KPiA+ID4gKmNvbm5fc3RhdGUpOw0KPiA+ID4gIGJvb2wgaW50ZWxfZGlnaXRhbF9wb3J0
X2Nvbm5lY3RlZChzdHJ1Y3QgaW50ZWxfZW5jb2RlciAqZW5jb2Rlcik7DQo+ID4gPg0KPiA+ID4g
IHN0YXRpYyBpbmxpbmUgdW5zaWduZWQgaW50IGludGVsX2RwX3VudXNlZF9sYW5lX21hc2soaW50
DQo+ID4gPiBsYW5lX2NvdW50KQ0KPiA+ID4gLS0NCj4gPiA+IDIuMjQuMQ0KPiA+ID4NCj4gPiA+
IF9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fDQo+ID4gPiBk
cmktZGV2ZWwgbWFpbGluZyBsaXN0DQo+ID4gPiBkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Au
b3JnDQo+ID4gPiBodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZv
L2RyaS1kZXZlbA0K

RE: [PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs (Secondary Data Packet)

[Shankar, Uma]

> -----Original Message-----
> From: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>
> Sent: Sunday, February 9, 2020 9:05 AM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; linux-fbdev@vger.kernel.org
> Subject: Re: [PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs (Secondary Data
> Packet)
> 
> On Wed, 2020-02-05 at 21:39 +0530, Shankar, Uma wrote:
> > > -----Original Message-----
> > > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf
> > > Of Gwan- gyeong Mun
> > > Sent: Tuesday, February 4, 2020 4:50 AM
> > > To: intel-gfx@lists.freedesktop.org
> > > Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> > > Subject: [PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs
> > > (Secondary Data
> > > Packet)
> >
> > Drop things in (), not needed.
> >
> > > It adds routines that write DP VSC SDP and DP HDR Metadata Infoframe
> > > SDP.
> > > In order to pack DP VSC SDP, it adds intel_dp_vsc_sdp_pack()
> > > function.
> > > It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and
> > > [Table 2-117: VSC SDP Payload for DB16 through DB18]
> > >
> > > In order to pack DP HDR Metadata Infoframe SDP, it adds
> > > intel_dp_hdr_metadata_infoframe_sdp_pack() function.
> > > And it follows DP 1.4a spec.
> > > ([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and [Table 2-126:
> > > INFOFRAME
> > > SDP v1.2 Payload Data Bytes - DB0 through DB31]) and CTA-861-G spec.
> > > [Table-42 Dynamic Range and Mastering InfoFrame].
> > >
> > > A machanism and a naming rule of intel_dp_set_infoframes() function
> > > references
> >
> > Typo in mechanism.
> >
> > > intel_encoder->set_infoframes() of intel_hdmi.c .
> > > VSC SDP is used for PSR and Pixel Encoding and Colorimetry Formats
> > > cases.
> > > Because PSR routine has its own routine of writing a VSC SDP, when
> > > the PSR is enabled, intel_dp_set_infoframes() does not write a VSC
> > > SDP.
> > >
> > > v3:
> > >   - Explicitly disable unused DIPs (AVI, GCP, VS, SPD, DRM. They
> > > will be
> > >     used for HDMI), when intel_dp_set_infoframes() function will be
> > > called.
> > >   - Replace a structure name to drm_dp_vsc_sdp from
> > > intel_dp_vsc_sdp.
> > >
> > > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_dp.c | 194
> > > ++++++++++++++++++++++++
> > >  drivers/gpu/drm/i915/display/intel_dp.h |   3 +
> > >  2 files changed, 197 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index b265b5c599f2..dd7e5588001e 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -4731,6 +4731,200 @@ intel_dp_needs_vsc_sdp(const struct
> > > intel_crtc_state *crtc_state,
> > >  	return false;
> > >  }
> > >
> > > +static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp
> > > *vsc,
> > > +				     struct dp_sdp *sdp, size_t size) {
> > > +	size_t length = sizeof(struct dp_sdp);
> > > +
> > > +	if (size < length)
> > > +		return -ENOSPC;
> > > +
> > > +	memset(sdp, 0, size);
> > > +
> > > +	/*
> > > +	 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
> > > +	 * VSC SDP Header Bytes
> > > +	 */
> > > +	sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
> > > +	sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet
> > > Type */
> > > +	sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
> > > +	sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data
> > > Bytes */
> > > +
> > > +	/* VSC SDP Payload for DB16 through DB18 */
> > > +	/* Pixel Encoding and Colorimetry Formats  */
> > > +	sdp->db[16] = (vsc->colorspace & 0xf) << 4; /* DB16[7:4] */
> > > +	sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
> > > +
> > > +	switch (vsc->bpc) {
> > > +	case 8:
> > > +		sdp->db[17] = 0x1; /* DB17[3:0] */
> > > +		break;
> > > +	case 10:
> > > +		sdp->db[17] = 0x2;
> > > +		break;
> > > +	case 12:
> > > +		sdp->db[17] = 0x3;
> > > +		break;
> > > +	case 16:
> > > +		sdp->db[17] = 0x4;
> > > +		break;
> > > +	default:
> > > +		MISSING_CASE(vsc->bpc);
> >
> > 6bpc is not handled here, add that as well.
> >
> Yes, I missed 6bpc case, I'll update it.
> > > +		break;
> > > +	}
> > > +	/* Dynamic Range and Component Bit Depth */
> > > +	if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
> > > +		sdp->db[17] |= 0x80;  /* DB17[7] */
> > > +
> > > +	/* Content Type */
> > > +	sdp->db[18] = vsc->content_type & 0x7;
> > > +
> > > +	return length;
> > > +}
> > > +
> > > +static ssize_t
> > > +intel_dp_hdr_metadata_infoframe_sdp_pack(const struct
> > > hdmi_drm_infoframe
> > > *drm_infoframe,
> > > +					 struct dp_sdp *sdp,
> > > +					 size_t size)
> > > +{
> > > +	size_t length = sizeof(struct dp_sdp);
> > > +	const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE +
> > > HDMI_DRM_INFOFRAME_SIZE;
> > > +	unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE +
> > > HDMI_DRM_INFOFRAME_SIZE];
> > > +	ssize_t len;
> > > +
> > > +	if (size < length)
> > > +		return -ENOSPC;
> > > +
> > > +	memset(sdp, 0, size);
> > > +
> > > +	len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf,
> > > sizeof(buf));
> > > +	if (len < 0) {
> > > +		DRM_DEBUG_KMS("buffer size is smaller than hdr metadata
> > > infoframe\n");
> > > +		return -ENOSPC;
> > > +	}
> > > +
> > > +	if (len != infoframe_size) {
> > > +		DRM_DEBUG_KMS("wrong static hdr metadata size\n");
> > > +		return -ENOSPC;
> > > +	}
> > > +
> > > +	/*
> > > +	 * Set up the infoframe sdp packet for HDR static metadata.
> > > +	 * Prepare VSC Header for SU as per DP 1.4a spec,
> > > +	 * Table 2-100 and Table 2-101
> > > +	 */
> > > +
> > > +	/* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
> > > +	sdp->sdp_header.HB0 = 0;
> > > +	/*
> > > +	 * Packet Type 80h + Non-audio INFOFRAME Type value
> > > +	 * HDMI_INFOFRAME_TYPE_DRM: 0x87
> > > +	 * - 80h + Non-audio INFOFRAME Type value
> > > +	 * - InfoFrame Type: 0x07
> > > +	 *    [CTA-861-G Table-42 Dynamic Range and Mastering
> > > InfoFrame]
> > > +	 */
> > > +	sdp->sdp_header.HB1 = drm_infoframe->type;
> > > +	/*
> > > +	 * Least Significant Eight Bits of (Data Byte Count – 1)
> > > +	 * infoframe_size - 1
> > > +	 */
> > > +	sdp->sdp_header.HB2 = 0x1D;
> > > +	/* INFOFRAME SDP Version Number */
> > > +	sdp->sdp_header.HB3 = (0x13 << 2);
> > > +	/* CTA Header Byte 2 (INFOFRAME Version Number) */
> > > +	sdp->db[0] = drm_infoframe->version;
> > > +	/* CTA Header Byte 3 (Length of INFOFRAME):
> > > HDMI_DRM_INFOFRAME_SIZE */
> > > +	sdp->db[1] = drm_infoframe->length;
> > > +	/*
> > > +	 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
> >
> > Comment Looks incomplete.
> >
> I missed some comments, I'll update it.
> > > +	 */
> > > +	BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
> > > +	memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
> > > +	       HDMI_DRM_INFOFRAME_SIZE);
> > > +
> > > +	/*
> > > +	 * Size of DP infoframe sdp packet for HDR static metadata is
> > > consist of
> >
> > Drop "is"
> >
> Includes this, I'll polish polish commit message and comments.
> 
> > > +	 * - DP SDP Header(struct dp_sdp_header): 4 bytes
> > > +	 * - Two Data Blocks: 2 bytes
> > > +	 *    CTA Header Byte2 (INFOFRAME Version Number)
> > > +	 *    CTA Header Byte3 (Length of INFOFRAME)
> > > +	 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
> > > +	 *
> > > +	 * Prior to GEN11's GMP register size is identical to DP HDR
> > > static metadata
> > > +	 * infoframe size. But GEN11+ has larger than that size,
> > > write_infoframe
> > > +	 * will pad rest of the size.
> > > +	 */
> > > +	return sizeof(struct dp_sdp_header) + 2 +
> > > HDMI_DRM_INFOFRAME_SIZE; }
> > > +
> > > +static void intel_write_dp_sdp(struct intel_encoder *encoder,
> > > +			       const struct intel_crtc_state
> > > *crtc_state,
> > > +			       unsigned int type)
> > > +{
> > > +	struct intel_digital_port *intel_dig_port =
> > > enc_to_dig_port(encoder);
> > > +	struct dp_sdp sdp = {};
> > > +	ssize_t len;
> > > +
> > > +	if ((crtc_state->infoframes.enable &
> > > +	     intel_hdmi_infoframe_enable(type)) == 0)
> > > +		return;
> > > +
> > > +	switch (type) {
> > > +	case DP_SDP_VSC:
> > > +		len = intel_dp_vsc_sdp_pack(&crtc_state-
> > > >infoframes.vsc, &sdp,
> > > +					    sizeof(sdp));
> > > +		break;
> > > +	case HDMI_PACKET_TYPE_GAMUT_METADATA:
> > > +		len =
> > > intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state-
> > > > infoframes.drm.drm,
> > > +							       &sdp,
> > > sizeof(sdp));
> > > +		break;
> > > +	default:
> > > +		MISSING_CASE(type);
> > > +		break;
> > > +	}
> > > +
> > > +	if (WARN_ON(len < 0))
> > > +		return;
> > > +
> > > +	intel_dig_port->write_infoframe(encoder, crtc_state, type,
> > > &sdp, len);
> > > +}
> > > +
> > > +void intel_dp_set_infoframes(struct intel_encoder *encoder,
> > > +			     bool enable,
> > > +			     const struct intel_crtc_state *crtc_state,
> > > +			     const struct drm_connector_state
> > > *conn_state) {
> > > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > > +	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state-
> > > >cpu_transcoder);
> > > +	u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW |
> > > VIDEO_DIP_ENABLE_GCP_HSW |
> > > +			 VIDEO_DIP_ENABLE_VS_HSW |
> > > VIDEO_DIP_ENABLE_GMP_HSW |
> > > +			 VIDEO_DIP_ENABLE_SPD_HSW |
> > > VIDEO_DIP_ENABLE_DRM_GLK;
> > > +	u32 val = I915_READ(reg);
> > > +
> > > +	/* TODO: Add DSC case (DIP_ENABLE_PPS) */
> > > +	/* When PSR is enabled, this routine doesn't disable VSC DIP */
> > > +	if (intel_psr_enabled(intel_dp))
> > > +		val &= ~dip_enable;
> > > +	else
> > > +		val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
> >
> > dip_enable has VIDEO_DIP_ENABLE_VSC_HSW already in it. Please fix
> > this.
> >
> Declaring of dip_enable does not include VIDEO_DIP_ENABLE_VSC_HSW.
> therefore we need it here to disable VSC SDP DIP.

Oh ok, Took VS for VSC. Scratch my earlier comment, change is correct.

> > > +
> > > +	if (!enable) {
> > > +		I915_WRITE(reg, val);
> > > +		POSTING_READ(reg);
> > > +		return;
> > > +	}
> > > +
> > > +	I915_WRITE(reg, val);
> > > +	POSTING_READ(reg);
> > > +
> > > +	/* When PSR is enabled, VSC SDP is handled by PSR routine */
> > > +	if (!intel_psr_enabled(intel_dp))
> > > +		intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
> > > +
> > > +	intel_write_dp_sdp(encoder, crtc_state,
> > > +HDMI_PACKET_TYPE_GAMUT_METADATA); }
> > > +
> > >  static void
> > >  intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
> > >  		       const struct intel_crtc_state *crtc_state, diff --git
> > > a/drivers/gpu/drm/i915/display/intel_dp.h
> > > b/drivers/gpu/drm/i915/display/intel_dp.h
> > > index 3da166054788..0dc09a463ee1 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > > @@ -116,6 +116,9 @@ void intel_dp_vsc_enable(struct intel_dp
> > > *intel_dp,  void intel_dp_hdr_metadata_enable(struct intel_dp
> > > *intel_dp,
> > >  				  const struct intel_crtc_state *crtc_state,
> > >  				  const struct drm_connector_state *conn_state);
> > > +void intel_dp_set_infoframes(struct intel_encoder *encoder, bool
> > > enable,
> > > +			     const struct intel_crtc_state *crtc_state,
> > > +			     const struct drm_connector_state
> > > *conn_state);
> > >  bool intel_digital_port_connected(struct intel_encoder *encoder);
> > >
> > >  static inline unsigned int intel_dp_unused_lane_mask(int
> > > lane_count)
> > > --
> > > 2.24.1
> > >
> > > _______________________________________________
> > > dri-devel mailing list
> > > dri-devel@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Intel-gfx] [PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs (Secondary Data Packet)

[Shankar, Uma]

> -----Original Message-----
> From: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>
> Sent: Sunday, February 9, 2020 9:05 AM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; linux-fbdev@vger.kernel.org
> Subject: Re: [PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs (Secondary Data
> Packet)
> 
> On Wed, 2020-02-05 at 21:39 +0530, Shankar, Uma wrote:
> > > -----Original Message-----
> > > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf
> > > Of Gwan- gyeong Mun
> > > Sent: Tuesday, February 4, 2020 4:50 AM
> > > To: intel-gfx@lists.freedesktop.org
> > > Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
> > > Subject: [PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs
> > > (Secondary Data
> > > Packet)
> >
> > Drop things in (), not needed.
> >
> > > It adds routines that write DP VSC SDP and DP HDR Metadata Infoframe
> > > SDP.
> > > In order to pack DP VSC SDP, it adds intel_dp_vsc_sdp_pack()
> > > function.
> > > It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and
> > > [Table 2-117: VSC SDP Payload for DB16 through DB18]
> > >
> > > In order to pack DP HDR Metadata Infoframe SDP, it adds
> > > intel_dp_hdr_metadata_infoframe_sdp_pack() function.
> > > And it follows DP 1.4a spec.
> > > ([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and [Table 2-126:
> > > INFOFRAME
> > > SDP v1.2 Payload Data Bytes - DB0 through DB31]) and CTA-861-G spec.
> > > [Table-42 Dynamic Range and Mastering InfoFrame].
> > >
> > > A machanism and a naming rule of intel_dp_set_infoframes() function
> > > references
> >
> > Typo in mechanism.
> >
> > > intel_encoder->set_infoframes() of intel_hdmi.c .
> > > VSC SDP is used for PSR and Pixel Encoding and Colorimetry Formats
> > > cases.
> > > Because PSR routine has its own routine of writing a VSC SDP, when
> > > the PSR is enabled, intel_dp_set_infoframes() does not write a VSC
> > > SDP.
> > >
> > > v3:
> > >   - Explicitly disable unused DIPs (AVI, GCP, VS, SPD, DRM. They
> > > will be
> > >     used for HDMI), when intel_dp_set_infoframes() function will be
> > > called.
> > >   - Replace a structure name to drm_dp_vsc_sdp from
> > > intel_dp_vsc_sdp.
> > >
> > > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_dp.c | 194
> > > ++++++++++++++++++++++++
> > >  drivers/gpu/drm/i915/display/intel_dp.h |   3 +
> > >  2 files changed, 197 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index b265b5c599f2..dd7e5588001e 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -4731,6 +4731,200 @@ intel_dp_needs_vsc_sdp(const struct
> > > intel_crtc_state *crtc_state,
> > >  	return false;
> > >  }
> > >
> > > +static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp
> > > *vsc,
> > > +				     struct dp_sdp *sdp, size_t size) {
> > > +	size_t length = sizeof(struct dp_sdp);
> > > +
> > > +	if (size < length)
> > > +		return -ENOSPC;
> > > +
> > > +	memset(sdp, 0, size);
> > > +
> > > +	/*
> > > +	 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
> > > +	 * VSC SDP Header Bytes
> > > +	 */
> > > +	sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
> > > +	sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet
> > > Type */
> > > +	sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
> > > +	sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data
> > > Bytes */
> > > +
> > > +	/* VSC SDP Payload for DB16 through DB18 */
> > > +	/* Pixel Encoding and Colorimetry Formats  */
> > > +	sdp->db[16] = (vsc->colorspace & 0xf) << 4; /* DB16[7:4] */
> > > +	sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
> > > +
> > > +	switch (vsc->bpc) {
> > > +	case 8:
> > > +		sdp->db[17] = 0x1; /* DB17[3:0] */
> > > +		break;
> > > +	case 10:
> > > +		sdp->db[17] = 0x2;
> > > +		break;
> > > +	case 12:
> > > +		sdp->db[17] = 0x3;
> > > +		break;
> > > +	case 16:
> > > +		sdp->db[17] = 0x4;
> > > +		break;
> > > +	default:
> > > +		MISSING_CASE(vsc->bpc);
> >
> > 6bpc is not handled here, add that as well.
> >
> Yes, I missed 6bpc case, I'll update it.
> > > +		break;
> > > +	}
> > > +	/* Dynamic Range and Component Bit Depth */
> > > +	if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
> > > +		sdp->db[17] |= 0x80;  /* DB17[7] */
> > > +
> > > +	/* Content Type */
> > > +	sdp->db[18] = vsc->content_type & 0x7;
> > > +
> > > +	return length;
> > > +}
> > > +
> > > +static ssize_t
> > > +intel_dp_hdr_metadata_infoframe_sdp_pack(const struct
> > > hdmi_drm_infoframe
> > > *drm_infoframe,
> > > +					 struct dp_sdp *sdp,
> > > +					 size_t size)
> > > +{
> > > +	size_t length = sizeof(struct dp_sdp);
> > > +	const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE +
> > > HDMI_DRM_INFOFRAME_SIZE;
> > > +	unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE +
> > > HDMI_DRM_INFOFRAME_SIZE];
> > > +	ssize_t len;
> > > +
> > > +	if (size < length)
> > > +		return -ENOSPC;
> > > +
> > > +	memset(sdp, 0, size);
> > > +
> > > +	len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf,
> > > sizeof(buf));
> > > +	if (len < 0) {
> > > +		DRM_DEBUG_KMS("buffer size is smaller than hdr metadata
> > > infoframe\n");
> > > +		return -ENOSPC;
> > > +	}
> > > +
> > > +	if (len != infoframe_size) {
> > > +		DRM_DEBUG_KMS("wrong static hdr metadata size\n");
> > > +		return -ENOSPC;
> > > +	}
> > > +
> > > +	/*
> > > +	 * Set up the infoframe sdp packet for HDR static metadata.
> > > +	 * Prepare VSC Header for SU as per DP 1.4a spec,
> > > +	 * Table 2-100 and Table 2-101
> > > +	 */
> > > +
> > > +	/* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
> > > +	sdp->sdp_header.HB0 = 0;
> > > +	/*
> > > +	 * Packet Type 80h + Non-audio INFOFRAME Type value
> > > +	 * HDMI_INFOFRAME_TYPE_DRM: 0x87
> > > +	 * - 80h + Non-audio INFOFRAME Type value
> > > +	 * - InfoFrame Type: 0x07
> > > +	 *    [CTA-861-G Table-42 Dynamic Range and Mastering
> > > InfoFrame]
> > > +	 */
> > > +	sdp->sdp_header.HB1 = drm_infoframe->type;
> > > +	/*
> > > +	 * Least Significant Eight Bits of (Data Byte Count – 1)
> > > +	 * infoframe_size - 1
> > > +	 */
> > > +	sdp->sdp_header.HB2 = 0x1D;
> > > +	/* INFOFRAME SDP Version Number */
> > > +	sdp->sdp_header.HB3 = (0x13 << 2);
> > > +	/* CTA Header Byte 2 (INFOFRAME Version Number) */
> > > +	sdp->db[0] = drm_infoframe->version;
> > > +	/* CTA Header Byte 3 (Length of INFOFRAME):
> > > HDMI_DRM_INFOFRAME_SIZE */
> > > +	sdp->db[1] = drm_infoframe->length;
> > > +	/*
> > > +	 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
> >
> > Comment Looks incomplete.
> >
> I missed some comments, I'll update it.
> > > +	 */
> > > +	BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
> > > +	memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
> > > +	       HDMI_DRM_INFOFRAME_SIZE);
> > > +
> > > +	/*
> > > +	 * Size of DP infoframe sdp packet for HDR static metadata is
> > > consist of
> >
> > Drop "is"
> >
> Includes this, I'll polish polish commit message and comments.
> 
> > > +	 * - DP SDP Header(struct dp_sdp_header): 4 bytes
> > > +	 * - Two Data Blocks: 2 bytes
> > > +	 *    CTA Header Byte2 (INFOFRAME Version Number)
> > > +	 *    CTA Header Byte3 (Length of INFOFRAME)
> > > +	 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
> > > +	 *
> > > +	 * Prior to GEN11's GMP register size is identical to DP HDR
> > > static metadata
> > > +	 * infoframe size. But GEN11+ has larger than that size,
> > > write_infoframe
> > > +	 * will pad rest of the size.
> > > +	 */
> > > +	return sizeof(struct dp_sdp_header) + 2 +
> > > HDMI_DRM_INFOFRAME_SIZE; }
> > > +
> > > +static void intel_write_dp_sdp(struct intel_encoder *encoder,
> > > +			       const struct intel_crtc_state
> > > *crtc_state,
> > > +			       unsigned int type)
> > > +{
> > > +	struct intel_digital_port *intel_dig_port =
> > > enc_to_dig_port(encoder);
> > > +	struct dp_sdp sdp = {};
> > > +	ssize_t len;
> > > +
> > > +	if ((crtc_state->infoframes.enable &
> > > +	     intel_hdmi_infoframe_enable(type)) == 0)
> > > +		return;
> > > +
> > > +	switch (type) {
> > > +	case DP_SDP_VSC:
> > > +		len = intel_dp_vsc_sdp_pack(&crtc_state-
> > > >infoframes.vsc, &sdp,
> > > +					    sizeof(sdp));
> > > +		break;
> > > +	case HDMI_PACKET_TYPE_GAMUT_METADATA:
> > > +		len =
> > > intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state-
> > > > infoframes.drm.drm,
> > > +							       &sdp,
> > > sizeof(sdp));
> > > +		break;
> > > +	default:
> > > +		MISSING_CASE(type);
> > > +		break;
> > > +	}
> > > +
> > > +	if (WARN_ON(len < 0))
> > > +		return;
> > > +
> > > +	intel_dig_port->write_infoframe(encoder, crtc_state, type,
> > > &sdp, len);
> > > +}
> > > +
> > > +void intel_dp_set_infoframes(struct intel_encoder *encoder,
> > > +			     bool enable,
> > > +			     const struct intel_crtc_state *crtc_state,
> > > +			     const struct drm_connector_state
> > > *conn_state) {
> > > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > > +	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state-
> > > >cpu_transcoder);
> > > +	u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW |
> > > VIDEO_DIP_ENABLE_GCP_HSW |
> > > +			 VIDEO_DIP_ENABLE_VS_HSW |
> > > VIDEO_DIP_ENABLE_GMP_HSW |
> > > +			 VIDEO_DIP_ENABLE_SPD_HSW |
> > > VIDEO_DIP_ENABLE_DRM_GLK;
> > > +	u32 val = I915_READ(reg);
> > > +
> > > +	/* TODO: Add DSC case (DIP_ENABLE_PPS) */
> > > +	/* When PSR is enabled, this routine doesn't disable VSC DIP */
> > > +	if (intel_psr_enabled(intel_dp))
> > > +		val &= ~dip_enable;
> > > +	else
> > > +		val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
> >
> > dip_enable has VIDEO_DIP_ENABLE_VSC_HSW already in it. Please fix
> > this.
> >
> Declaring of dip_enable does not include VIDEO_DIP_ENABLE_VSC_HSW.
> therefore we need it here to disable VSC SDP DIP.

Oh ok, Took VS for VSC. Scratch my earlier comment, change is correct.

> > > +
> > > +	if (!enable) {
> > > +		I915_WRITE(reg, val);
> > > +		POSTING_READ(reg);
> > > +		return;
> > > +	}
> > > +
> > > +	I915_WRITE(reg, val);
> > > +	POSTING_READ(reg);
> > > +
> > > +	/* When PSR is enabled, VSC SDP is handled by PSR routine */
> > > +	if (!intel_psr_enabled(intel_dp))
> > > +		intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
> > > +
> > > +	intel_write_dp_sdp(encoder, crtc_state,
> > > +HDMI_PACKET_TYPE_GAMUT_METADATA); }
> > > +
> > >  static void
> > >  intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
> > >  		       const struct intel_crtc_state *crtc_state, diff --git
> > > a/drivers/gpu/drm/i915/display/intel_dp.h
> > > b/drivers/gpu/drm/i915/display/intel_dp.h
> > > index 3da166054788..0dc09a463ee1 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > > @@ -116,6 +116,9 @@ void intel_dp_vsc_enable(struct intel_dp
> > > *intel_dp,  void intel_dp_hdr_metadata_enable(struct intel_dp
> > > *intel_dp,
> > >  				  const struct intel_crtc_state *crtc_state,
> > >  				  const struct drm_connector_state *conn_state);
> > > +void intel_dp_set_infoframes(struct intel_encoder *encoder, bool
> > > enable,
> > > +			     const struct intel_crtc_state *crtc_state,
> > > +			     const struct drm_connector_state
> > > *conn_state);
> > >  bool intel_digital_port_connected(struct intel_encoder *encoder);
> > >
> > >  static inline unsigned int intel_dp_unused_lane_mask(int
> > > lane_count)
> > > --
> > > 2.24.1
> > >
> > > _______________________________________________
> > > dri-devel mailing list
> > > dri-devel@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx