[PATCH V2 00/10] clk: imx: fixes and improve for i.MX8M

[PATCH V2 00/10] clk: imx: fixes and improve for i.MX8M

[peng.fan]

From: Peng Fan <peng.fan@nxp.com>

Patches based on for-next

V2:
 Patch 7, drop wait after write, add one line comment for write twice

V1:
Patch 1,2 is to fix the lockdep warning reported by Leonard
Patch 3 is to fix pll mux bit
Patch 4 is align with other i.MX8M using gate
Patch 5 is to simplify i.MX8MP clk root using composite

Patch 3~5 is actually https://patchwork.kernel.org/patch/11402761/
with a minimal change to patch 5 here.

Patch 6 is to use composite core clk for A53 clk root
Patch 7,8,9 is actually to fix CORE/BUS clk slice issue.
 This issue is triggerred after we update U-Boot to include
 the A53 clk fixes to sources from PLL, not from A53 root clk,
 because of the signoff timing is 1GHz. U-Boot set the A53 root
 mux to 2, sys pll2 500MHz. Kernel will set the A53 root mux to
 4, sys pll1 800MHz, then gate off sys pll2 500MHz. Then kernel
 will gate off A53 root because clk_ignore_unsed, A53 directly sources
 PLL, so it is ok to gate off A53 root. However when gate off A53
 root clk, system hang, because the original mux sys pll2 500MHz
 gated off with CLK_OPS_PARENT_ENABLE flag.

 It is lucky that we not met issue for other core/bus clk slice
 except A53 ROOT core slice. But it is always triggerred after
 U-Boot and Linux both switch to use ARM PLL for A53 core, but
 have different mux settings for A53 root clk slice.

 So the three patches is to address this issue.

Patch 10 is make memrepair as critical.

Peng Fan (10):
  arm64: dts: imx8m: assign clocks for A53
  clk: imx8m: drop clk_hw_set_parent for A53
  clk: imx: imx8mp: fix pll mux bit
  clk: imx8mp: Define gates for pll1/2 fixed dividers
  clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code
  clk: imx8m: migrate A53 clk root to use composite core
  clk: imx: add mux ops for i.MX8M composite clk
  clk: imx: add imx8m_clk_hw_composite_bus
  clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice
  clk: imx8mp: mark memrepair clock as critical

 arch/arm64/boot/dts/freescale/imx8mm.dtsi |  10 +-
 arch/arm64/boot/dts/freescale/imx8mn.dtsi |  10 +-
 arch/arm64/boot/dts/freescale/imx8mp.dtsi |  11 ++-
 arch/arm64/boot/dts/freescale/imx8mq.dtsi |   9 +-
 drivers/clk/imx/clk-composite-8m.c        |  67 ++++++++++++-
 drivers/clk/imx/clk-imx8mm.c              |  27 +++---
 drivers/clk/imx/clk-imx8mn.c              |  25 +++--
 drivers/clk/imx/clk-imx8mp.c              | 150 +++++++++++++++---------------
 drivers/clk/imx/clk-imx8mq.c              |  29 +++---
 drivers/clk/imx/clk.h                     |   7 ++
 include/dt-bindings/clock/imx8mp-clock.h  |  28 +++++-
 11 files changed, 240 insertions(+), 133 deletions(-)

-- 
2.16.4

[PATCH V2 00/10] clk: imx: fixes and improve for i.MX8M

[peng.fan]

From: Peng Fan <peng.fan@nxp.com>

Patches based on for-next

V2:
 Patch 7, drop wait after write, add one line comment for write twice

V1:
Patch 1,2 is to fix the lockdep warning reported by Leonard
Patch 3 is to fix pll mux bit
Patch 4 is align with other i.MX8M using gate
Patch 5 is to simplify i.MX8MP clk root using composite

Patch 3~5 is actually https://patchwork.kernel.org/patch/11402761/
with a minimal change to patch 5 here.

Patch 6 is to use composite core clk for A53 clk root
Patch 7,8,9 is actually to fix CORE/BUS clk slice issue.
 This issue is triggerred after we update U-Boot to include
 the A53 clk fixes to sources from PLL, not from A53 root clk,
 because of the signoff timing is 1GHz. U-Boot set the A53 root
 mux to 2, sys pll2 500MHz. Kernel will set the A53 root mux to
 4, sys pll1 800MHz, then gate off sys pll2 500MHz. Then kernel
 will gate off A53 root because clk_ignore_unsed, A53 directly sources
 PLL, so it is ok to gate off A53 root. However when gate off A53
 root clk, system hang, because the original mux sys pll2 500MHz
 gated off with CLK_OPS_PARENT_ENABLE flag.

 It is lucky that we not met issue for other core/bus clk slice
 except A53 ROOT core slice. But it is always triggerred after
 U-Boot and Linux both switch to use ARM PLL for A53 core, but
 have different mux settings for A53 root clk slice.

 So the three patches is to address this issue.

Patch 10 is make memrepair as critical.

Peng Fan (10):
  arm64: dts: imx8m: assign clocks for A53
  clk: imx8m: drop clk_hw_set_parent for A53
  clk: imx: imx8mp: fix pll mux bit
  clk: imx8mp: Define gates for pll1/2 fixed dividers
  clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code
  clk: imx8m: migrate A53 clk root to use composite core
  clk: imx: add mux ops for i.MX8M composite clk
  clk: imx: add imx8m_clk_hw_composite_bus
  clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice
  clk: imx8mp: mark memrepair clock as critical

 arch/arm64/boot/dts/freescale/imx8mm.dtsi |  10 +-
 arch/arm64/boot/dts/freescale/imx8mn.dtsi |  10 +-
 arch/arm64/boot/dts/freescale/imx8mp.dtsi |  11 ++-
 arch/arm64/boot/dts/freescale/imx8mq.dtsi |   9 +-
 drivers/clk/imx/clk-composite-8m.c        |  67 ++++++++++++-
 drivers/clk/imx/clk-imx8mm.c              |  27 +++---
 drivers/clk/imx/clk-imx8mn.c              |  25 +++--
 drivers/clk/imx/clk-imx8mp.c              | 150 +++++++++++++++---------------
 drivers/clk/imx/clk-imx8mq.c              |  29 +++---
 drivers/clk/imx/clk.h                     |   7 ++
 include/dt-bindings/clock/imx8mp-clock.h  |  28 +++++-
 11 files changed, 240 insertions(+), 133 deletions(-)

-- 
2.16.4


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH V2 01/10] arm64: dts: imx8m: assign clocks for A53

[peng.fan]

From: Peng Fan <peng.fan@nxp.com>

Assign IMX8M*_CLK_A53_SRC's parent to system pll1 and
assign IMX8M*_CLK_A53_CORE's parent to arm pll out as what
is done in drivers/clk/imx/clk-imx8m*.c, then we could remove
the settings in driver which triggers lockdep warning.

Reported-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 10 +++++++---
 arch/arm64/boot/dts/freescale/imx8mn.dtsi | 10 +++++++---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 11 ++++++++---
 arch/arm64/boot/dts/freescale/imx8mq.dtsi |  9 +++++++--
 4 files changed, 29 insertions(+), 11 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 2e5e7c4457db..8d2200224db4 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -471,16 +471,20 @@
 					 <&clk_ext3>, <&clk_ext4>;
 				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
 					      "clk_ext3", "clk_ext4";
-				assigned-clocks = <&clk IMX8MM_CLK_NOC>,
+				assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
+						<&clk IMX8MM_CLK_A53_CORE>,
+						<&clk IMX8MM_CLK_NOC>,
 						<&clk IMX8MM_CLK_AUDIO_AHB>,
 						<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
 						<&clk IMX8MM_SYS_PLL3>,
 						<&clk IMX8MM_VIDEO_PLL1>,
 						<&clk IMX8MM_AUDIO_PLL1>,
 						<&clk IMX8MM_AUDIO_PLL2>;
-				assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
+				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
+							 <&clk IMX8MM_ARM_PLL_OUT>,
+							 <&clk IMX8MM_SYS_PLL3_OUT>,
 							 <&clk IMX8MM_SYS_PLL1_800M>;
-				assigned-clock-rates = <0>,
+				assigned-clock-rates = <0>, <0>, <0>,
 							<400000000>,
 							<400000000>,
 							<750000000>,
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index ff9c1ea38130..ad88ba3bf28c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -380,13 +380,17 @@
 					 <&clk_ext3>, <&clk_ext4>;
 				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
 					      "clk_ext3", "clk_ext4";
-				assigned-clocks = <&clk IMX8MN_CLK_NOC>,
+				assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
+						<&clk IMX8MN_CLK_A53_CORE>,
+						<&clk IMX8MN_CLK_NOC>,
 						<&clk IMX8MN_CLK_AUDIO_AHB>,
 						<&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
 						<&clk IMX8MN_SYS_PLL3>;
-				assigned-clock-parents = <&clk IMX8MN_SYS_PLL3_OUT>,
+				assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
+							 <&clk IMX8MN_ARM_PLL_OUT>,
+							 <&clk IMX8MN_SYS_PLL3_OUT>,
 							 <&clk IMX8MN_SYS_PLL1_800M>;
-				assigned-clock-rates = <0>,
+				assigned-clock-rates = <0>, <0>, <0>,
 							<400000000>,
 							<400000000>,
 							<600000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index d92199bf6635..3a96082e8717 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -284,7 +284,9 @@
 					 <&clk_ext3>, <&clk_ext4>;
 				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
 					      "clk_ext3", "clk_ext4";
-				assigned-clocks = <&clk IMX8MP_CLK_NOC>,
+				assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
+						  <&clk IMX8MP_CLK_A53_CORE>,
+						  <&clk IMX8MP_CLK_NOC>,
 						  <&clk IMX8MP_CLK_NOC_IO>,
 						  <&clk IMX8MP_CLK_GIC>,
 						  <&clk IMX8MP_CLK_AUDIO_AHB>,
@@ -292,12 +294,15 @@
 						  <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
 						  <&clk IMX8MP_AUDIO_PLL1>,
 						  <&clk IMX8MP_AUDIO_PLL2>;
-				assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
+				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
+							 <&clk IMX8MP_ARM_PLL_OUT>,
+							 <&clk IMX8MP_SYS_PLL2_1000M>,
 							 <&clk IMX8MP_SYS_PLL1_800M>,
 							 <&clk IMX8MP_SYS_PLL2_500M>,
 							 <&clk IMX8MP_SYS_PLL1_800M>,
 							 <&clk IMX8MP_SYS_PLL1_800M>;
-				assigned-clock-rates = <1000000000>,
+				assigned-clock-rates = <0>, <0>,
+						       <1000000000>,
 						       <800000000>,
 						       <500000000>,
 						       <400000000>,
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 9bbdaf2d6e34..1f3ffc8c8a78 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -594,8 +594,13 @@
 				clock-names = "ckil", "osc_25m", "osc_27m",
 				              "clk_ext1", "clk_ext2",
 				              "clk_ext3", "clk_ext4";
-				assigned-clocks = <&clk IMX8MQ_CLK_NOC>;
-				assigned-clock-rates = <800000000>;
+				assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,
+						  <&clk IMX8MQ_CLK_A53_CORE>,
+						  <&clk IMX8MQ_CLK_NOC>;
+				assigned-clock-rates = <0>, <0>,
+						       <800000000>;
+				assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
+							 <&clk IMX8MQ_ARM_PLL_OUT>;
 			};
 
 			src: reset-controller@30390000 {
-- 
2.16.4

[PATCH V2 01/10] arm64: dts: imx8m: assign clocks for A53

[peng.fan]

From: Peng Fan <peng.fan@nxp.com>

Assign IMX8M*_CLK_A53_SRC's parent to system pll1 and
assign IMX8M*_CLK_A53_CORE's parent to arm pll out as what
is done in drivers/clk/imx/clk-imx8m*.c, then we could remove
the settings in driver which triggers lockdep warning.

Reported-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 10 +++++++---
 arch/arm64/boot/dts/freescale/imx8mn.dtsi | 10 +++++++---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 11 ++++++++---
 arch/arm64/boot/dts/freescale/imx8mq.dtsi |  9 +++++++--
 4 files changed, 29 insertions(+), 11 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 2e5e7c4457db..8d2200224db4 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -471,16 +471,20 @@
 					 <&clk_ext3>, <&clk_ext4>;
 				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
 					      "clk_ext3", "clk_ext4";
-				assigned-clocks = <&clk IMX8MM_CLK_NOC>,
+				assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
+						<&clk IMX8MM_CLK_A53_CORE>,
+						<&clk IMX8MM_CLK_NOC>,
 						<&clk IMX8MM_CLK_AUDIO_AHB>,
 						<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
 						<&clk IMX8MM_SYS_PLL3>,
 						<&clk IMX8MM_VIDEO_PLL1>,
 						<&clk IMX8MM_AUDIO_PLL1>,
 						<&clk IMX8MM_AUDIO_PLL2>;
-				assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
+				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
+							 <&clk IMX8MM_ARM_PLL_OUT>,
+							 <&clk IMX8MM_SYS_PLL3_OUT>,
 							 <&clk IMX8MM_SYS_PLL1_800M>;
-				assigned-clock-rates = <0>,
+				assigned-clock-rates = <0>, <0>, <0>,
 							<400000000>,
 							<400000000>,
 							<750000000>,
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index ff9c1ea38130..ad88ba3bf28c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -380,13 +380,17 @@
 					 <&clk_ext3>, <&clk_ext4>;
 				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
 					      "clk_ext3", "clk_ext4";
-				assigned-clocks = <&clk IMX8MN_CLK_NOC>,
+				assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
+						<&clk IMX8MN_CLK_A53_CORE>,
+						<&clk IMX8MN_CLK_NOC>,
 						<&clk IMX8MN_CLK_AUDIO_AHB>,
 						<&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
 						<&clk IMX8MN_SYS_PLL3>;
-				assigned-clock-parents = <&clk IMX8MN_SYS_PLL3_OUT>,
+				assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
+							 <&clk IMX8MN_ARM_PLL_OUT>,
+							 <&clk IMX8MN_SYS_PLL3_OUT>,
 							 <&clk IMX8MN_SYS_PLL1_800M>;
-				assigned-clock-rates = <0>,
+				assigned-clock-rates = <0>, <0>, <0>,
 							<400000000>,
 							<400000000>,
 							<600000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index d92199bf6635..3a96082e8717 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -284,7 +284,9 @@
 					 <&clk_ext3>, <&clk_ext4>;
 				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
 					      "clk_ext3", "clk_ext4";
-				assigned-clocks = <&clk IMX8MP_CLK_NOC>,
+				assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
+						  <&clk IMX8MP_CLK_A53_CORE>,
+						  <&clk IMX8MP_CLK_NOC>,
 						  <&clk IMX8MP_CLK_NOC_IO>,
 						  <&clk IMX8MP_CLK_GIC>,
 						  <&clk IMX8MP_CLK_AUDIO_AHB>,
@@ -292,12 +294,15 @@
 						  <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
 						  <&clk IMX8MP_AUDIO_PLL1>,
 						  <&clk IMX8MP_AUDIO_PLL2>;
-				assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
+				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
+							 <&clk IMX8MP_ARM_PLL_OUT>,
+							 <&clk IMX8MP_SYS_PLL2_1000M>,
 							 <&clk IMX8MP_SYS_PLL1_800M>,
 							 <&clk IMX8MP_SYS_PLL2_500M>,
 							 <&clk IMX8MP_SYS_PLL1_800M>,
 							 <&clk IMX8MP_SYS_PLL1_800M>;
-				assigned-clock-rates = <1000000000>,
+				assigned-clock-rates = <0>, <0>,
+						       <1000000000>,
 						       <800000000>,
 						       <500000000>,
 						       <400000000>,
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 9bbdaf2d6e34..1f3ffc8c8a78 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -594,8 +594,13 @@
 				clock-names = "ckil", "osc_25m", "osc_27m",
 				              "clk_ext1", "clk_ext2",
 				              "clk_ext3", "clk_ext4";
-				assigned-clocks = <&clk IMX8MQ_CLK_NOC>;
-				assigned-clock-rates = <800000000>;
+				assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,
+						  <&clk IMX8MQ_CLK_A53_CORE>,
+						  <&clk IMX8MQ_CLK_NOC>;
+				assigned-clock-rates = <0>, <0>,
+						       <800000000>;
+				assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
+							 <&clk IMX8MQ_ARM_PLL_OUT>;
 			};
 
 			src: reset-controller@30390000 {
-- 
2.16.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH V2 02/10] clk: imx8m: drop clk_hw_set_parent for A53

[peng.fan]

From: Peng Fan <peng.fan@nxp.com>

The parent settings have been moved to dtsi, we no need to
set parent here. And clk_hw_set_parent will trigger lockdep warning,
because this api not have prepare_lock.

Reported-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx8mm.c | 3 ---
 drivers/clk/imx/clk-imx8mn.c | 3 ---
 drivers/clk/imx/clk-imx8mp.c | 3 ---
 drivers/clk/imx/clk-imx8mq.c | 3 ---
 4 files changed, 12 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 925670438f23..5435042a06e3 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -614,9 +614,6 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
 					   hws[IMX8MM_ARM_PLL_OUT]->clk,
 					   hws[IMX8MM_CLK_A53_DIV]->clk);
 
-	clk_hw_set_parent(hws[IMX8MM_CLK_A53_SRC], hws[IMX8MM_SYS_PLL1_800M]);
-	clk_hw_set_parent(hws[IMX8MM_CLK_A53_CORE], hws[IMX8MM_ARM_PLL_OUT]);
-
 	imx_check_clk_hws(hws, IMX8MM_CLK_END);
 
 	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 0bc7070235bd..6cac6ca03e12 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -565,9 +565,6 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
 					   hws[IMX8MN_ARM_PLL_OUT]->clk,
 					   hws[IMX8MN_CLK_A53_DIV]->clk);
 
-	clk_hw_set_parent(hws[IMX8MN_CLK_A53_SRC], hws[IMX8MN_SYS_PLL1_800M]);
-	clk_hw_set_parent(hws[IMX8MN_CLK_A53_CORE], hws[IMX8MN_ARM_PLL_OUT]);
-
 	imx_check_clk_hws(hws, IMX8MN_CLK_END);
 
 	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 41469e2cc3de..e05ec56df285 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -735,9 +735,6 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
 					     hws[IMX8MP_ARM_PLL_OUT]->clk,
 					     hws[IMX8MP_CLK_A53_DIV]->clk);
 
-	clk_hw_set_parent(hws[IMX8MP_CLK_A53_SRC], hws[IMX8MP_SYS_PLL1_800M]);
-	clk_hw_set_parent(hws[IMX8MP_CLK_A53_CORE], hws[IMX8MP_ARM_PLL_OUT]);
-
 	imx_check_clk_hws(hws, IMX8MP_CLK_END);
 
 	of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index fdc68db68de5..201c7bbb201f 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -599,9 +599,6 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
 					   hws[IMX8MQ_ARM_PLL_OUT]->clk,
 					   hws[IMX8MQ_CLK_A53_DIV]->clk);
 
-	clk_hw_set_parent(hws[IMX8MQ_CLK_A53_SRC], hws[IMX8MQ_SYS1_PLL_800M]);
-	clk_hw_set_parent(hws[IMX8MQ_CLK_A53_CORE], hws[IMX8MQ_ARM_PLL_OUT]);
-
 	imx_check_clk_hws(hws, IMX8MQ_CLK_END);
 
 	err = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
-- 
2.16.4

[PATCH V2 02/10] clk: imx8m: drop clk_hw_set_parent for A53

[peng.fan]

From: Peng Fan <peng.fan@nxp.com>

The parent settings have been moved to dtsi, we no need to
set parent here. And clk_hw_set_parent will trigger lockdep warning,
because this api not have prepare_lock.

Reported-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx8mm.c | 3 ---
 drivers/clk/imx/clk-imx8mn.c | 3 ---
 drivers/clk/imx/clk-imx8mp.c | 3 ---
 drivers/clk/imx/clk-imx8mq.c | 3 ---
 4 files changed, 12 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 925670438f23..5435042a06e3 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -614,9 +614,6 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
 					   hws[IMX8MM_ARM_PLL_OUT]->clk,
 					   hws[IMX8MM_CLK_A53_DIV]->clk);
 
-	clk_hw_set_parent(hws[IMX8MM_CLK_A53_SRC], hws[IMX8MM_SYS_PLL1_800M]);
-	clk_hw_set_parent(hws[IMX8MM_CLK_A53_CORE], hws[IMX8MM_ARM_PLL_OUT]);
-
 	imx_check_clk_hws(hws, IMX8MM_CLK_END);
 
 	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 0bc7070235bd..6cac6ca03e12 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -565,9 +565,6 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
 					   hws[IMX8MN_ARM_PLL_OUT]->clk,
 					   hws[IMX8MN_CLK_A53_DIV]->clk);
 
-	clk_hw_set_parent(hws[IMX8MN_CLK_A53_SRC], hws[IMX8MN_SYS_PLL1_800M]);
-	clk_hw_set_parent(hws[IMX8MN_CLK_A53_CORE], hws[IMX8MN_ARM_PLL_OUT]);
-
 	imx_check_clk_hws(hws, IMX8MN_CLK_END);
 
 	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 41469e2cc3de..e05ec56df285 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -735,9 +735,6 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
 					     hws[IMX8MP_ARM_PLL_OUT]->clk,
 					     hws[IMX8MP_CLK_A53_DIV]->clk);
 
-	clk_hw_set_parent(hws[IMX8MP_CLK_A53_SRC], hws[IMX8MP_SYS_PLL1_800M]);
-	clk_hw_set_parent(hws[IMX8MP_CLK_A53_CORE], hws[IMX8MP_ARM_PLL_OUT]);
-
 	imx_check_clk_hws(hws, IMX8MP_CLK_END);
 
 	of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index fdc68db68de5..201c7bbb201f 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -599,9 +599,6 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
 					   hws[IMX8MQ_ARM_PLL_OUT]->clk,
 					   hws[IMX8MQ_CLK_A53_DIV]->clk);
 
-	clk_hw_set_parent(hws[IMX8MQ_CLK_A53_SRC], hws[IMX8MQ_SYS1_PLL_800M]);
-	clk_hw_set_parent(hws[IMX8MQ_CLK_A53_CORE], hws[IMX8MQ_ARM_PLL_OUT]);
-
 	imx_check_clk_hws(hws, IMX8MQ_CLK_END);
 
 	err = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
-- 
2.16.4


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[PATCH V2 03/10] clk: imx: imx8mp: fix pll mux bit

[peng.fan]

From: Peng Fan <peng.fan@nxp.com>

Same to i.MX8MN/i.MX8MM, pll BYPASS bit should be kept inside pll
driver for glitchless freq setting following spec. If exposing the
bit, that means pll driver and clk driver has two paths to touch
this bit, which is wrong.

So use EXT_BYPASS bit here.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx8mp.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index e05ec56df285..e9ed8a188031 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -486,16 +486,16 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MP_SYS_PLL2] = imx_clk_hw_pll14xx("sys_pll2", "sys_pll2_ref_sel", anatop_base + 0x104, &imx_1416x_pll);
 	hws[IMX8MP_SYS_PLL3] = imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", anatop_base + 0x114, &imx_1416x_pll);
 
-	hws[IMX8MP_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", anatop_base, 4, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
-	hws[IMX8MP_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", anatop_base + 0x14, 4, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
-	hws[IMX8MP_VIDEO_PLL1_BYPASS] = imx_clk_hw_mux_flags("video_pll1_bypass", anatop_base + 0x28, 4, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT);
-	hws[IMX8MP_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", anatop_base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
-	hws[IMX8MP_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", anatop_base + 0x64, 4, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
-	hws[IMX8MP_VPU_PLL_BYPASS] = imx_clk_hw_mux_flags("vpu_pll_bypass", anatop_base + 0x74, 4, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
-	hws[IMX8MP_ARM_PLL_BYPASS] = imx_clk_hw_mux_flags("arm_pll_bypass", anatop_base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
-	hws[IMX8MP_SYS_PLL1_BYPASS] = imx_clk_hw_mux_flags("sys_pll1_bypass", anatop_base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT);
-	hws[IMX8MP_SYS_PLL2_BYPASS] = imx_clk_hw_mux_flags("sys_pll2_bypass", anatop_base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT);
-	hws[IMX8MP_SYS_PLL3_BYPASS] = imx_clk_hw_mux_flags("sys_pll3_bypass", anatop_base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
+	hws[IMX8MP_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", anatop_base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
+	hws[IMX8MP_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", anatop_base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
+	hws[IMX8MP_VIDEO_PLL1_BYPASS] = imx_clk_hw_mux_flags("video_pll1_bypass", anatop_base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT);
+	hws[IMX8MP_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", anatop_base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
+	hws[IMX8MP_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", anatop_base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
+	hws[IMX8MP_VPU_PLL_BYPASS] = imx_clk_hw_mux_flags("vpu_pll_bypass", anatop_base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
+	hws[IMX8MP_ARM_PLL_BYPASS] = imx_clk_hw_mux_flags("arm_pll_bypass", anatop_base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
+	hws[IMX8MP_SYS_PLL1_BYPASS] = imx_clk_hw_mux_flags("sys_pll1_bypass", anatop_base + 0x94, 28, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT);
+	hws[IMX8MP_SYS_PLL2_BYPASS] = imx_clk_hw_mux_flags("sys_pll2_bypass", anatop_base + 0x104, 28, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT);
+	hws[IMX8MP_SYS_PLL3_BYPASS] = imx_clk_hw_mux_flags("sys_pll3_bypass", anatop_base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
 
 	hws[IMX8MP_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", anatop_base, 13);
 	hws[IMX8MP_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", anatop_base + 0x14, 13);
-- 
2.16.4

[PATCH V2 03/10] clk: imx: imx8mp: fix pll mux bit

[peng.fan]

From: Peng Fan <peng.fan@nxp.com>

Same to i.MX8MN/i.MX8MM, pll BYPASS bit should be kept inside pll
driver for glitchless freq setting following spec. If exposing the
bit, that means pll driver and clk driver has two paths to touch
this bit, which is wrong.

So use EXT_BYPASS bit here.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx8mp.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index e05ec56df285..e9ed8a188031 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -486,16 +486,16 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MP_SYS_PLL2] = imx_clk_hw_pll14xx("sys_pll2", "sys_pll2_ref_sel", anatop_base + 0x104, &imx_1416x_pll);
 	hws[IMX8MP_SYS_PLL3] = imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", anatop_base + 0x114, &imx_1416x_pll);
 
-	hws[IMX8MP_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", anatop_base, 4, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
-	hws[IMX8MP_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", anatop_base + 0x14, 4, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
-	hws[IMX8MP_VIDEO_PLL1_BYPASS] = imx_clk_hw_mux_flags("video_pll1_bypass", anatop_base + 0x28, 4, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT);
-	hws[IMX8MP_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", anatop_base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
-	hws[IMX8MP_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", anatop_base + 0x64, 4, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
-	hws[IMX8MP_VPU_PLL_BYPASS] = imx_clk_hw_mux_flags("vpu_pll_bypass", anatop_base + 0x74, 4, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
-	hws[IMX8MP_ARM_PLL_BYPASS] = imx_clk_hw_mux_flags("arm_pll_bypass", anatop_base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
-	hws[IMX8MP_SYS_PLL1_BYPASS] = imx_clk_hw_mux_flags("sys_pll1_bypass", anatop_base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT);
-	hws[IMX8MP_SYS_PLL2_BYPASS] = imx_clk_hw_mux_flags("sys_pll2_bypass", anatop_base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT);
-	hws[IMX8MP_SYS_PLL3_BYPASS] = imx_clk_hw_mux_flags("sys_pll3_bypass", anatop_base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
+	hws[IMX8MP_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", anatop_base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
+	hws[IMX8MP_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", anatop_base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
+	hws[IMX8MP_VIDEO_PLL1_BYPASS] = imx_clk_hw_mux_flags("video_pll1_bypass", anatop_base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT);
+	hws[IMX8MP_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", anatop_base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
+	hws[IMX8MP_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", anatop_base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
+	hws[IMX8MP_VPU_PLL_BYPASS] = imx_clk_hw_mux_flags("vpu_pll_bypass", anatop_base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
+	hws[IMX8MP_ARM_PLL_BYPASS] = imx_clk_hw_mux_flags("arm_pll_bypass", anatop_base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
+	hws[IMX8MP_SYS_PLL1_BYPASS] = imx_clk_hw_mux_flags("sys_pll1_bypass", anatop_base + 0x94, 28, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT);
+	hws[IMX8MP_SYS_PLL2_BYPASS] = imx_clk_hw_mux_flags("sys_pll2_bypass", anatop_base + 0x104, 28, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT);
+	hws[IMX8MP_SYS_PLL3_BYPASS] = imx_clk_hw_mux_flags("sys_pll3_bypass", anatop_base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
 
 	hws[IMX8MP_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", anatop_base, 13);
 	hws[IMX8MP_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", anatop_base + 0x14, 13);
-- 
2.16.4


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[PATCH V2 04/10] clk: imx8mp: Define gates for pll1/2 fixed dividers

[peng.fan]

From: Peng Fan <peng.fan@nxp.com>

Inspried from
commit e8688fe8df7d ("clk: imx8mn: Define gates for pll1/2 fixed dividers")

On imx8mp there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2
each with their own gate. Only one of these gates (the one "dividing" by
one) is currently defined and it's incorrectly set as the parent of all
the fixed-factor dividers.

Add the other 8 gates to the clock tree between sys_pll1/2_bypass and
the fixed dividers.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx8mp.c             | 54 +++++++++++++++++++++-----------
 include/dt-bindings/clock/imx8mp-clock.h | 19 ++++++++++-
 2 files changed, 54 insertions(+), 19 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index e9ed8a188031..a7613c7355c8 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -504,28 +504,46 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MP_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", anatop_base + 0x64, 11);
 	hws[IMX8MP_VPU_PLL_OUT] = imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass", anatop_base + 0x74, 11);
 	hws[IMX8MP_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", anatop_base + 0x84, 11);
-	hws[IMX8MP_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1_bypass", anatop_base + 0x94, 11);
-	hws[IMX8MP_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2_bypass", anatop_base + 0x104, 11);
 	hws[IMX8MP_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", anatop_base + 0x114, 11);
 
-	hws[IMX8MP_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
-	hws[IMX8MP_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10);
-	hws[IMX8MP_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8);
-	hws[IMX8MP_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6);
-	hws[IMX8MP_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5);
-	hws[IMX8MP_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4);
-	hws[IMX8MP_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3);
-	hws[IMX8MP_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2);
+	hws[IMX8MP_SYS_PLL1_40M_CG] = imx_clk_hw_gate("sys_pll1_40m_cg", "sys_pll1_bypass", anatop_base + 0x94, 27);
+	hws[IMX8MP_SYS_PLL1_80M_CG] = imx_clk_hw_gate("sys_pll1_80m_cg", "sys_pll1_bypass", anatop_base + 0x94, 25);
+	hws[IMX8MP_SYS_PLL1_100M_CG] = imx_clk_hw_gate("sys_pll1_100m_cg", "sys_pll1_bypass", anatop_base + 0x94, 23);
+	hws[IMX8MP_SYS_PLL1_133M_CG] = imx_clk_hw_gate("sys_pll1_133m_cg", "sys_pll1_bypass", anatop_base + 0x94, 21);
+	hws[IMX8MP_SYS_PLL1_160M_CG] = imx_clk_hw_gate("sys_pll1_160m_cg", "sys_pll1_bypass", anatop_base + 0x94, 19);
+	hws[IMX8MP_SYS_PLL1_200M_CG] = imx_clk_hw_gate("sys_pll1_200m_cg", "sys_pll1_bypass", anatop_base + 0x94, 17);
+	hws[IMX8MP_SYS_PLL1_266M_CG] = imx_clk_hw_gate("sys_pll1_266m_cg", "sys_pll1_bypass", anatop_base + 0x94, 15);
+	hws[IMX8MP_SYS_PLL1_400M_CG] = imx_clk_hw_gate("sys_pll1_400m_cg", "sys_pll1_bypass", anatop_base + 0x94, 13);
+	hws[IMX8MP_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1_bypass", anatop_base + 0x94, 11);
+
+	hws[IMX8MP_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_40m_cg", 1, 20);
+	hws[IMX8MP_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_80m_cg", 1, 10);
+	hws[IMX8MP_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_100m_cg", 1, 8);
+	hws[IMX8MP_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_133m_cg", 1, 6);
+	hws[IMX8MP_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_160m_cg", 1, 5);
+	hws[IMX8MP_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_200m_cg", 1, 4);
+	hws[IMX8MP_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_266m_cg", 1, 3);
+	hws[IMX8MP_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_400m_cg", 1, 2);
 	hws[IMX8MP_SYS_PLL1_800M] = imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
 
-	hws[IMX8MP_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
-	hws[IMX8MP_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
-	hws[IMX8MP_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
-	hws[IMX8MP_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6);
-	hws[IMX8MP_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5);
-	hws[IMX8MP_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4);
-	hws[IMX8MP_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3);
-	hws[IMX8MP_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
+	hws[IMX8MP_SYS_PLL2_50M_CG] = imx_clk_hw_gate("sys_pll2_50m_cg", "sys_pll2_bypass", anatop_base + 0x104, 27);
+	hws[IMX8MP_SYS_PLL2_100M_CG] = imx_clk_hw_gate("sys_pll2_100m_cg", "sys_pll2_bypass", anatop_base + 0x104, 25);
+	hws[IMX8MP_SYS_PLL2_125M_CG] = imx_clk_hw_gate("sys_pll2_125m_cg", "sys_pll2_bypass", anatop_base + 0x104, 23);
+	hws[IMX8MP_SYS_PLL2_166M_CG] = imx_clk_hw_gate("sys_pll2_166m_cg", "sys_pll2_bypass", anatop_base + 0x104, 21);
+	hws[IMX8MP_SYS_PLL2_200M_CG] = imx_clk_hw_gate("sys_pll2_200m_cg", "sys_pll2_bypass", anatop_base + 0x104, 19);
+	hws[IMX8MP_SYS_PLL2_250M_CG] = imx_clk_hw_gate("sys_pll2_250m_cg", "sys_pll2_bypass", anatop_base + 0x104, 17);
+	hws[IMX8MP_SYS_PLL2_333M_CG] = imx_clk_hw_gate("sys_pll2_333m_cg", "sys_pll2_bypass", anatop_base + 0x104, 15);
+	hws[IMX8MP_SYS_PLL2_500M_CG] = imx_clk_hw_gate("sys_pll2_500m_cg", "sys_pll2_bypass", anatop_base + 0x104, 13);
+	hws[IMX8MP_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2_bypass", anatop_base + 0x104, 11);
+
+	hws[IMX8MP_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_50m_cg", 1, 20);
+	hws[IMX8MP_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_100m_cg", 1, 10);
+	hws[IMX8MP_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_125m_cg", 1, 8);
+	hws[IMX8MP_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_166m_cg", 1, 6);
+	hws[IMX8MP_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_200m_cg", 1, 5);
+	hws[IMX8MP_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_250m_cg", 1, 4);
+	hws[IMX8MP_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_333m_cg", 1, 3);
+	hws[IMX8MP_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
 	hws[IMX8MP_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
 
 	hws[IMX8MP_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", ccm_base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels));
diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h
index 47ab082238b4..46c69cd66c62 100644
--- a/include/dt-bindings/clock/imx8mp-clock.h
+++ b/include/dt-bindings/clock/imx8mp-clock.h
@@ -296,6 +296,23 @@
 #define IMX8MP_CLK_ARM				287
 #define IMX8MP_CLK_A53_CORE			288
 
-#define IMX8MP_CLK_END				289
+#define IMX8MP_SYS_PLL1_40M_CG			289
+#define IMX8MP_SYS_PLL1_80M_CG			290
+#define IMX8MP_SYS_PLL1_100M_CG			291
+#define IMX8MP_SYS_PLL1_133M_CG			292
+#define IMX8MP_SYS_PLL1_160M_CG			293
+#define IMX8MP_SYS_PLL1_200M_CG			294
+#define IMX8MP_SYS_PLL1_266M_CG			295
+#define IMX8MP_SYS_PLL1_400M_CG			296
+#define IMX8MP_SYS_PLL2_50M_CG			297
+#define IMX8MP_SYS_PLL2_100M_CG			298
+#define IMX8MP_SYS_PLL2_125M_CG			299
+#define IMX8MP_SYS_PLL2_166M_CG			300
+#define IMX8MP_SYS_PLL2_200M_CG			301
+#define IMX8MP_SYS_PLL2_250M_CG			302
+#define IMX8MP_SYS_PLL2_333M_CG			303
+#define IMX8MP_SYS_PLL2_500M_CG			304
+
+#define IMX8MP_CLK_END				305
 
 #endif
-- 
2.16.4

[PATCH V2 04/10] clk: imx8mp: Define gates for pll1/2 fixed dividers

[peng.fan]

From: Peng Fan <peng.fan@nxp.com>

Inspried from
commit e8688fe8df7d ("clk: imx8mn: Define gates for pll1/2 fixed dividers")

On imx8mp there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2
each with their own gate. Only one of these gates (the one "dividing" by
one) is currently defined and it's incorrectly set as the parent of all
the fixed-factor dividers.

Add the other 8 gates to the clock tree between sys_pll1/2_bypass and
the fixed dividers.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx8mp.c             | 54 +++++++++++++++++++++-----------
 include/dt-bindings/clock/imx8mp-clock.h | 19 ++++++++++-
 2 files changed, 54 insertions(+), 19 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index e9ed8a188031..a7613c7355c8 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -504,28 +504,46 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MP_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", anatop_base + 0x64, 11);
 	hws[IMX8MP_VPU_PLL_OUT] = imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass", anatop_base + 0x74, 11);
 	hws[IMX8MP_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", anatop_base + 0x84, 11);
-	hws[IMX8MP_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1_bypass", anatop_base + 0x94, 11);
-	hws[IMX8MP_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2_bypass", anatop_base + 0x104, 11);
 	hws[IMX8MP_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", anatop_base + 0x114, 11);
 
-	hws[IMX8MP_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
-	hws[IMX8MP_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10);
-	hws[IMX8MP_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8);
-	hws[IMX8MP_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6);
-	hws[IMX8MP_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5);
-	hws[IMX8MP_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4);
-	hws[IMX8MP_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3);
-	hws[IMX8MP_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2);
+	hws[IMX8MP_SYS_PLL1_40M_CG] = imx_clk_hw_gate("sys_pll1_40m_cg", "sys_pll1_bypass", anatop_base + 0x94, 27);
+	hws[IMX8MP_SYS_PLL1_80M_CG] = imx_clk_hw_gate("sys_pll1_80m_cg", "sys_pll1_bypass", anatop_base + 0x94, 25);
+	hws[IMX8MP_SYS_PLL1_100M_CG] = imx_clk_hw_gate("sys_pll1_100m_cg", "sys_pll1_bypass", anatop_base + 0x94, 23);
+	hws[IMX8MP_SYS_PLL1_133M_CG] = imx_clk_hw_gate("sys_pll1_133m_cg", "sys_pll1_bypass", anatop_base + 0x94, 21);
+	hws[IMX8MP_SYS_PLL1_160M_CG] = imx_clk_hw_gate("sys_pll1_160m_cg", "sys_pll1_bypass", anatop_base + 0x94, 19);
+	hws[IMX8MP_SYS_PLL1_200M_CG] = imx_clk_hw_gate("sys_pll1_200m_cg", "sys_pll1_bypass", anatop_base + 0x94, 17);
+	hws[IMX8MP_SYS_PLL1_266M_CG] = imx_clk_hw_gate("sys_pll1_266m_cg", "sys_pll1_bypass", anatop_base + 0x94, 15);
+	hws[IMX8MP_SYS_PLL1_400M_CG] = imx_clk_hw_gate("sys_pll1_400m_cg", "sys_pll1_bypass", anatop_base + 0x94, 13);
+	hws[IMX8MP_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1_bypass", anatop_base + 0x94, 11);
+
+	hws[IMX8MP_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_40m_cg", 1, 20);
+	hws[IMX8MP_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_80m_cg", 1, 10);
+	hws[IMX8MP_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_100m_cg", 1, 8);
+	hws[IMX8MP_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_133m_cg", 1, 6);
+	hws[IMX8MP_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_160m_cg", 1, 5);
+	hws[IMX8MP_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_200m_cg", 1, 4);
+	hws[IMX8MP_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_266m_cg", 1, 3);
+	hws[IMX8MP_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_400m_cg", 1, 2);
 	hws[IMX8MP_SYS_PLL1_800M] = imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
 
-	hws[IMX8MP_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
-	hws[IMX8MP_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
-	hws[IMX8MP_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
-	hws[IMX8MP_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6);
-	hws[IMX8MP_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5);
-	hws[IMX8MP_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4);
-	hws[IMX8MP_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3);
-	hws[IMX8MP_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
+	hws[IMX8MP_SYS_PLL2_50M_CG] = imx_clk_hw_gate("sys_pll2_50m_cg", "sys_pll2_bypass", anatop_base + 0x104, 27);
+	hws[IMX8MP_SYS_PLL2_100M_CG] = imx_clk_hw_gate("sys_pll2_100m_cg", "sys_pll2_bypass", anatop_base + 0x104, 25);
+	hws[IMX8MP_SYS_PLL2_125M_CG] = imx_clk_hw_gate("sys_pll2_125m_cg", "sys_pll2_bypass", anatop_base + 0x104, 23);
+	hws[IMX8MP_SYS_PLL2_166M_CG] = imx_clk_hw_gate("sys_pll2_166m_cg", "sys_pll2_bypass", anatop_base + 0x104, 21);
+	hws[IMX8MP_SYS_PLL2_200M_CG] = imx_clk_hw_gate("sys_pll2_200m_cg", "sys_pll2_bypass", anatop_base + 0x104, 19);
+	hws[IMX8MP_SYS_PLL2_250M_CG] = imx_clk_hw_gate("sys_pll2_250m_cg", "sys_pll2_bypass", anatop_base + 0x104, 17);
+	hws[IMX8MP_SYS_PLL2_333M_CG] = imx_clk_hw_gate("sys_pll2_333m_cg", "sys_pll2_bypass", anatop_base + 0x104, 15);
+	hws[IMX8MP_SYS_PLL2_500M_CG] = imx_clk_hw_gate("sys_pll2_500m_cg", "sys_pll2_bypass", anatop_base + 0x104, 13);
+	hws[IMX8MP_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2_bypass", anatop_base + 0x104, 11);
+
+	hws[IMX8MP_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_50m_cg", 1, 20);
+	hws[IMX8MP_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_100m_cg", 1, 10);
+	hws[IMX8MP_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_125m_cg", 1, 8);
+	hws[IMX8MP_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_166m_cg", 1, 6);
+	hws[IMX8MP_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_200m_cg", 1, 5);
+	hws[IMX8MP_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_250m_cg", 1, 4);
+	hws[IMX8MP_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_333m_cg", 1, 3);
+	hws[IMX8MP_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
 	hws[IMX8MP_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
 
 	hws[IMX8MP_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", ccm_base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels));
diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h
index 47ab082238b4..46c69cd66c62 100644
--- a/include/dt-bindings/clock/imx8mp-clock.h
+++ b/include/dt-bindings/clock/imx8mp-clock.h
@@ -296,6 +296,23 @@
 #define IMX8MP_CLK_ARM				287
 #define IMX8MP_CLK_A53_CORE			288
 
-#define IMX8MP_CLK_END				289
+#define IMX8MP_SYS_PLL1_40M_CG			289
+#define IMX8MP_SYS_PLL1_80M_CG			290
+#define IMX8MP_SYS_PLL1_100M_CG			291
+#define IMX8MP_SYS_PLL1_133M_CG			292
+#define IMX8MP_SYS_PLL1_160M_CG			293
+#define IMX8MP_SYS_PLL1_200M_CG			294
+#define IMX8MP_SYS_PLL1_266M_CG			295
+#define IMX8MP_SYS_PLL1_400M_CG			296
+#define IMX8MP_SYS_PLL2_50M_CG			297
+#define IMX8MP_SYS_PLL2_100M_CG			298
+#define IMX8MP_SYS_PLL2_125M_CG			299
+#define IMX8MP_SYS_PLL2_166M_CG			300
+#define IMX8MP_SYS_PLL2_200M_CG			301
+#define IMX8MP_SYS_PLL2_250M_CG			302
+#define IMX8MP_SYS_PLL2_333M_CG			303
+#define IMX8MP_SYS_PLL2_500M_CG			304
+
+#define IMX8MP_CLK_END				305
 
 #endif
-- 
2.16.4


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[PATCH V2 05/10] clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code

[peng.fan]

From: Peng Fan <peng.fan@nxp.com>

Use imx8m_clk_hw_composite_core to simpliy clks that belong to
core clk slice.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx8mp.c             | 47 +++++++++++---------------------
 include/dt-bindings/clock/imx8mp-clock.h | 11 +++++++-
 2 files changed, 26 insertions(+), 32 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index a7613c7355c8..998e9e63f831 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -546,33 +546,18 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MP_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
 	hws[IMX8MP_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
 
-	hws[IMX8MP_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", ccm_base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels));
-	hws[IMX8MP_CLK_M7_SRC] = imx_clk_hw_mux2("arm_m7_src", ccm_base + 0x8080, 24, 3, imx8mp_m7_sels, ARRAY_SIZE(imx8mp_m7_sels));
-	hws[IMX8MP_CLK_ML_SRC] = imx_clk_hw_mux2("ml_src", ccm_base + 0x8100, 24, 3, imx8mp_ml_sels, ARRAY_SIZE(imx8mp_ml_sels));
-	hws[IMX8MP_CLK_GPU3D_CORE_SRC] = imx_clk_hw_mux2("gpu3d_core_src", ccm_base + 0x8180, 24, 3,  imx8mp_gpu3d_core_sels, ARRAY_SIZE(imx8mp_gpu3d_core_sels));
-	hws[IMX8MP_CLK_GPU3D_SHADER_SRC] = imx_clk_hw_mux2("gpu3d_shader_src", ccm_base + 0x8200, 24, 3, imx8mp_gpu3d_shader_sels, ARRAY_SIZE(imx8mp_gpu3d_shader_sels));
-	hws[IMX8MP_CLK_GPU2D_SRC] = imx_clk_hw_mux2("gpu2d_src", ccm_base + 0x8280, 24, 3, imx8mp_gpu2d_sels, ARRAY_SIZE(imx8mp_gpu2d_sels));
-	hws[IMX8MP_CLK_AUDIO_AXI_SRC] = imx_clk_hw_mux2("audio_axi_src", ccm_base + 0x8300, 24, 3, imx8mp_audio_axi_sels, ARRAY_SIZE(imx8mp_audio_axi_sels));
-	hws[IMX8MP_CLK_HSIO_AXI_SRC] = imx_clk_hw_mux2("hsio_axi_src", ccm_base + 0x8380, 24, 3, imx8mp_hsio_axi_sels, ARRAY_SIZE(imx8mp_hsio_axi_sels));
-	hws[IMX8MP_CLK_MEDIA_ISP_SRC] = imx_clk_hw_mux2("media_isp_src", ccm_base + 0x8400, 24, 3, imx8mp_media_isp_sels, ARRAY_SIZE(imx8mp_media_isp_sels));
-	hws[IMX8MP_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg", "arm_a53_src", ccm_base + 0x8000, 28);
-	hws[IMX8MP_CLK_M4_CG] = imx_clk_hw_gate3("arm_m7_cg", "arm_m7_src", ccm_base + 0x8080, 28);
-	hws[IMX8MP_CLK_ML_CG] = imx_clk_hw_gate3("ml_cg", "ml_src", ccm_base + 0x8100, 28);
-	hws[IMX8MP_CLK_GPU3D_CORE_CG] = imx_clk_hw_gate3("gpu3d_core_cg", "gpu3d_core_src", ccm_base + 0x8180, 28);
-	hws[IMX8MP_CLK_GPU3D_SHADER_CG] = imx_clk_hw_gate3("gpu3d_shader_cg", "gpu3d_shader_src", ccm_base + 0x8200, 28);
-	hws[IMX8MP_CLK_GPU2D_CG] = imx_clk_hw_gate3("gpu2d_cg", "gpu2d_src", ccm_base + 0x8280, 28);
-	hws[IMX8MP_CLK_AUDIO_AXI_CG] = imx_clk_hw_gate3("audio_axi_cg", "audio_axi_src", ccm_base + 0x8300, 28);
-	hws[IMX8MP_CLK_HSIO_AXI_CG] = imx_clk_hw_gate3("hsio_axi_cg", "hsio_axi_src", ccm_base + 0x8380, 28);
-	hws[IMX8MP_CLK_MEDIA_ISP_CG] = imx_clk_hw_gate3("media_isp_cg", "media_isp_src", ccm_base + 0x8400, 28);
-	hws[IMX8MP_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div", "arm_a53_cg", ccm_base + 0x8000, 0, 3);
-	hws[IMX8MP_CLK_M7_DIV] = imx_clk_hw_divider2("arm_m7_div", "arm_m7_cg", ccm_base + 0x8080, 0, 3);
-	hws[IMX8MP_CLK_ML_DIV] = imx_clk_hw_divider2("ml_div", "ml_cg", ccm_base + 0x8100, 0, 3);
-	hws[IMX8MP_CLK_GPU3D_CORE_DIV] = imx_clk_hw_divider2("gpu3d_core_div", "gpu3d_core_cg", ccm_base + 0x8180, 0, 3);
-	hws[IMX8MP_CLK_GPU3D_SHADER_DIV] = imx_clk_hw_divider2("gpu3d_shader_div", "gpu3d_shader_cg", ccm_base + 0x8200, 0, 3);
-	hws[IMX8MP_CLK_GPU2D_DIV] = imx_clk_hw_divider2("gpu2d_div", "gpu2d_cg", ccm_base + 0x8280, 0, 3);
-	hws[IMX8MP_CLK_AUDIO_AXI_DIV] = imx_clk_hw_divider2("audio_axi_div", "audio_axi_cg", ccm_base + 0x8300, 0, 3);
-	hws[IMX8MP_CLK_HSIO_AXI_DIV] = imx_clk_hw_divider2("hsio_axi_div", "hsio_axi_cg", ccm_base + 0x8380, 0, 3);
-	hws[IMX8MP_CLK_MEDIA_ISP_DIV] = imx_clk_hw_divider2("media_isp_div", "media_isp_cg", ccm_base + 0x8400, 0, 3);
+	hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, ccm_base + 0x8000);
+	hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV];
+	hws[IMX8MP_CLK_A53_CG] = hws[IMX8MP_CLK_A53_DIV];
+	hws[IMX8MP_CLK_M7_CORE] = imx8m_clk_hw_composite_core("m7_core", imx8mp_m7_sels, ccm_base + 0x8080);
+	hws[IMX8MP_CLK_ML_CORE] = imx8m_clk_hw_composite_core("ml_core", imx8mp_ml_sels, ccm_base + 0x8100);
+	hws[IMX8MP_CLK_GPU3D_CORE] = imx8m_clk_hw_composite_core("gpu3d_core", imx8mp_gpu3d_core_sels, ccm_base + 0x8180);
+	hws[IMX8MP_CLK_GPU3D_SHADER_CORE] = imx8m_clk_hw_composite("gpu3d_shader_core", imx8mp_gpu3d_shader_sels, ccm_base + 0x8200);
+	hws[IMX8MP_CLK_GPU2D_CORE] = imx8m_clk_hw_composite("gpu2d_core", imx8mp_gpu2d_sels, ccm_base + 0x8280);
+	hws[IMX8MP_CLK_AUDIO_AXI] = imx8m_clk_hw_composite("audio_axi", imx8mp_audio_axi_sels, ccm_base + 0x8300);
+	hws[IMX8MP_CLK_AUDIO_AXI_SRC] = hws[IMX8MP_CLK_AUDIO_AXI];
+	hws[IMX8MP_CLK_HSIO_AXI] = imx8m_clk_hw_composite("hsio_axi", imx8mp_hsio_axi_sels, ccm_base + 0x8380);
+	hws[IMX8MP_CLK_MEDIA_ISP] = imx8m_clk_hw_composite("media_isp", imx8mp_media_isp_sels, ccm_base + 0x8400);
 
 	/* CORE SEL */
 	hws[IMX8MP_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core", ccm_base + 0x9880, 24, 1, imx8mp_a53_core_sels, ARRAY_SIZE(imx8mp_a53_core_sels));
@@ -713,8 +698,8 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MP_CLK_SDMA1_ROOT] = imx_clk_hw_gate4("sdma1_root_clk", "ipg_root", ccm_base + 0x43a0, 0);
 	hws[IMX8MP_CLK_ENET_QOS_ROOT] = imx_clk_hw_gate4("enet_qos_root_clk", "sim_enet_root_clk", ccm_base + 0x43b0, 0);
 	hws[IMX8MP_CLK_SIM_ENET_ROOT] = imx_clk_hw_gate4("sim_enet_root_clk", "enet_axi", ccm_base + 0x4400, 0);
-	hws[IMX8MP_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk", "gpu2d_div", ccm_base + 0x4450, 0);
-	hws[IMX8MP_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk", "gpu3d_core_div", ccm_base + 0x4460, 0);
+	hws[IMX8MP_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk", "gpu2d_core", ccm_base + 0x4450, 0);
+	hws[IMX8MP_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk", "gpu3d_core", ccm_base + 0x4460, 0);
 	hws[IMX8MP_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk", "ipg_root", ccm_base + 0x4470, 0);
 	hws[IMX8MP_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk", "uart1", ccm_base + 0x4490, 0);
 	hws[IMX8MP_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", ccm_base + 0x44a0, 0);
@@ -731,7 +716,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MP_CLK_GPU_ROOT] = imx_clk_hw_gate4("gpu_root_clk", "gpu_axi", ccm_base + 0x4570, 0);
 	hws[IMX8MP_CLK_VPU_VC8KE_ROOT] = imx_clk_hw_gate4("vpu_vc8ke_root_clk", "vpu_vc8000e", ccm_base + 0x4590, 0);
 	hws[IMX8MP_CLK_VPU_G2_ROOT] = imx_clk_hw_gate4("vpu_g2_root_clk", "vpu_g2", ccm_base + 0x45a0, 0);
-	hws[IMX8MP_CLK_NPU_ROOT] = imx_clk_hw_gate4("npu_root_clk", "ml_div", ccm_base + 0x45b0, 0);
+	hws[IMX8MP_CLK_NPU_ROOT] = imx_clk_hw_gate4("npu_root_clk", "ml_core", ccm_base + 0x45b0, 0);
 	hws[IMX8MP_CLK_HSIO_ROOT] = imx_clk_hw_gate4("hsio_root_clk", "ipg_root", ccm_base + 0x45c0, 0);
 	hws[IMX8MP_CLK_MEDIA_APB_ROOT] = imx_clk_hw_gate2_shared2("media_apb_root_clk", "media_apb", ccm_base + 0x45d0, 0, &share_count_media);
 	hws[IMX8MP_CLK_MEDIA_AXI_ROOT] = imx_clk_hw_gate2_shared2("media_axi_root_clk", "media_axi", ccm_base + 0x45d0, 0, &share_count_media);
@@ -739,7 +724,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_cam2_pix_root_clk", "media_cam2_pix", ccm_base + 0x45d0, 0, &share_count_media);
 	hws[IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_disp1_pix_root_clk", "media_disp1_pix", ccm_base + 0x45d0, 0, &share_count_media);
 	hws[IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_disp2_pix_root_clk", "media_disp2_pix", ccm_base + 0x45d0, 0, &share_count_media);
-	hws[IMX8MP_CLK_MEDIA_ISP_ROOT] = imx_clk_hw_gate2_shared2("media_isp_root_clk", "media_isp_div", ccm_base + 0x45d0, 0, &share_count_media);
+	hws[IMX8MP_CLK_MEDIA_ISP_ROOT] = imx_clk_hw_gate2_shared2("media_isp_root_clk", "media_isp", ccm_base + 0x45d0, 0, &share_count_media);
 
 	hws[IMX8MP_CLK_USDHC3_ROOT] = imx_clk_hw_gate4("usdhc3_root_clk", "usdhc3", ccm_base + 0x45e0, 0);
 	hws[IMX8MP_CLK_HDMI_ROOT] = imx_clk_hw_gate4("hdmi_root_clk", "hdmi_axi", ccm_base + 0x45f0, 0);
diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h
index 46c69cd66c62..8430bc4fd182 100644
--- a/include/dt-bindings/clock/imx8mp-clock.h
+++ b/include/dt-bindings/clock/imx8mp-clock.h
@@ -313,6 +313,15 @@
 #define IMX8MP_SYS_PLL2_333M_CG			303
 #define IMX8MP_SYS_PLL2_500M_CG			304
 
-#define IMX8MP_CLK_END				305
+#define IMX8MP_CLK_M7_CORE			305
+#define IMX8MP_CLK_ML_CORE			306
+#define IMX8MP_CLK_GPU3D_CORE			307
+#define IMX8MP_CLK_GPU3D_SHADER_CORE		308
+#define IMX8MP_CLK_GPU2D_CORE			309
+#define IMX8MP_CLK_AUDIO_AXI			310
+#define IMX8MP_CLK_HSIO_AXI			311
+#define IMX8MP_CLK_MEDIA_ISP			312
+
+#define IMX8MP_CLK_END				313
 
 #endif
-- 
2.16.4

[PATCH V2 05/10] clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code

[peng.fan]

From: Peng Fan <peng.fan@nxp.com>

Use imx8m_clk_hw_composite_core to simpliy clks that belong to
core clk slice.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx8mp.c             | 47 +++++++++++---------------------
 include/dt-bindings/clock/imx8mp-clock.h | 11 +++++++-
 2 files changed, 26 insertions(+), 32 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index a7613c7355c8..998e9e63f831 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -546,33 +546,18 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MP_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
 	hws[IMX8MP_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
 
-	hws[IMX8MP_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", ccm_base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels));
-	hws[IMX8MP_CLK_M7_SRC] = imx_clk_hw_mux2("arm_m7_src", ccm_base + 0x8080, 24, 3, imx8mp_m7_sels, ARRAY_SIZE(imx8mp_m7_sels));
-	hws[IMX8MP_CLK_ML_SRC] = imx_clk_hw_mux2("ml_src", ccm_base + 0x8100, 24, 3, imx8mp_ml_sels, ARRAY_SIZE(imx8mp_ml_sels));
-	hws[IMX8MP_CLK_GPU3D_CORE_SRC] = imx_clk_hw_mux2("gpu3d_core_src", ccm_base + 0x8180, 24, 3,  imx8mp_gpu3d_core_sels, ARRAY_SIZE(imx8mp_gpu3d_core_sels));
-	hws[IMX8MP_CLK_GPU3D_SHADER_SRC] = imx_clk_hw_mux2("gpu3d_shader_src", ccm_base + 0x8200, 24, 3, imx8mp_gpu3d_shader_sels, ARRAY_SIZE(imx8mp_gpu3d_shader_sels));
-	hws[IMX8MP_CLK_GPU2D_SRC] = imx_clk_hw_mux2("gpu2d_src", ccm_base + 0x8280, 24, 3, imx8mp_gpu2d_sels, ARRAY_SIZE(imx8mp_gpu2d_sels));
-	hws[IMX8MP_CLK_AUDIO_AXI_SRC] = imx_clk_hw_mux2("audio_axi_src", ccm_base + 0x8300, 24, 3, imx8mp_audio_axi_sels, ARRAY_SIZE(imx8mp_audio_axi_sels));
-	hws[IMX8MP_CLK_HSIO_AXI_SRC] = imx_clk_hw_mux2("hsio_axi_src", ccm_base + 0x8380, 24, 3, imx8mp_hsio_axi_sels, ARRAY_SIZE(imx8mp_hsio_axi_sels));
-	hws[IMX8MP_CLK_MEDIA_ISP_SRC] = imx_clk_hw_mux2("media_isp_src", ccm_base + 0x8400, 24, 3, imx8mp_media_isp_sels, ARRAY_SIZE(imx8mp_media_isp_sels));
-	hws[IMX8MP_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg", "arm_a53_src", ccm_base + 0x8000, 28);
-	hws[IMX8MP_CLK_M4_CG] = imx_clk_hw_gate3("arm_m7_cg", "arm_m7_src", ccm_base + 0x8080, 28);
-	hws[IMX8MP_CLK_ML_CG] = imx_clk_hw_gate3("ml_cg", "ml_src", ccm_base + 0x8100, 28);
-	hws[IMX8MP_CLK_GPU3D_CORE_CG] = imx_clk_hw_gate3("gpu3d_core_cg", "gpu3d_core_src", ccm_base + 0x8180, 28);
-	hws[IMX8MP_CLK_GPU3D_SHADER_CG] = imx_clk_hw_gate3("gpu3d_shader_cg", "gpu3d_shader_src", ccm_base + 0x8200, 28);
-	hws[IMX8MP_CLK_GPU2D_CG] = imx_clk_hw_gate3("gpu2d_cg", "gpu2d_src", ccm_base + 0x8280, 28);
-	hws[IMX8MP_CLK_AUDIO_AXI_CG] = imx_clk_hw_gate3("audio_axi_cg", "audio_axi_src", ccm_base + 0x8300, 28);
-	hws[IMX8MP_CLK_HSIO_AXI_CG] = imx_clk_hw_gate3("hsio_axi_cg", "hsio_axi_src", ccm_base + 0x8380, 28);
-	hws[IMX8MP_CLK_MEDIA_ISP_CG] = imx_clk_hw_gate3("media_isp_cg", "media_isp_src", ccm_base + 0x8400, 28);
-	hws[IMX8MP_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div", "arm_a53_cg", ccm_base + 0x8000, 0, 3);
-	hws[IMX8MP_CLK_M7_DIV] = imx_clk_hw_divider2("arm_m7_div", "arm_m7_cg", ccm_base + 0x8080, 0, 3);
-	hws[IMX8MP_CLK_ML_DIV] = imx_clk_hw_divider2("ml_div", "ml_cg", ccm_base + 0x8100, 0, 3);
-	hws[IMX8MP_CLK_GPU3D_CORE_DIV] = imx_clk_hw_divider2("gpu3d_core_div", "gpu3d_core_cg", ccm_base + 0x8180, 0, 3);
-	hws[IMX8MP_CLK_GPU3D_SHADER_DIV] = imx_clk_hw_divider2("gpu3d_shader_div", "gpu3d_shader_cg", ccm_base + 0x8200, 0, 3);
-	hws[IMX8MP_CLK_GPU2D_DIV] = imx_clk_hw_divider2("gpu2d_div", "gpu2d_cg", ccm_base + 0x8280, 0, 3);
-	hws[IMX8MP_CLK_AUDIO_AXI_DIV] = imx_clk_hw_divider2("audio_axi_div", "audio_axi_cg", ccm_base + 0x8300, 0, 3);
-	hws[IMX8MP_CLK_HSIO_AXI_DIV] = imx_clk_hw_divider2("hsio_axi_div", "hsio_axi_cg", ccm_base + 0x8380, 0, 3);
-	hws[IMX8MP_CLK_MEDIA_ISP_DIV] = imx_clk_hw_divider2("media_isp_div", "media_isp_cg", ccm_base + 0x8400, 0, 3);
+	hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, ccm_base + 0x8000);
+	hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV];
+	hws[IMX8MP_CLK_A53_CG] = hws[IMX8MP_CLK_A53_DIV];
+	hws[IMX8MP_CLK_M7_CORE] = imx8m_clk_hw_composite_core("m7_core", imx8mp_m7_sels, ccm_base + 0x8080);
+	hws[IMX8MP_CLK_ML_CORE] = imx8m_clk_hw_composite_core("ml_core", imx8mp_ml_sels, ccm_base + 0x8100);
+	hws[IMX8MP_CLK_GPU3D_CORE] = imx8m_clk_hw_composite_core("gpu3d_core", imx8mp_gpu3d_core_sels, ccm_base + 0x8180);
+	hws[IMX8MP_CLK_GPU3D_SHADER_CORE] = imx8m_clk_hw_composite("gpu3d_shader_core", imx8mp_gpu3d_shader_sels, ccm_base + 0x8200);
+	hws[IMX8MP_CLK_GPU2D_CORE] = imx8m_clk_hw_composite("gpu2d_core", imx8mp_gpu2d_sels, ccm_base + 0x8280);
+	hws[IMX8MP_CLK_AUDIO_AXI] = imx8m_clk_hw_composite("audio_axi", imx8mp_audio_axi_sels, ccm_base + 0x8300);
+	hws[IMX8MP_CLK_AUDIO_AXI_SRC] = hws[IMX8MP_CLK_AUDIO_AXI];
+	hws[IMX8MP_CLK_HSIO_AXI] = imx8m_clk_hw_composite("hsio_axi", imx8mp_hsio_axi_sels, ccm_base + 0x8380);
+	hws[IMX8MP_CLK_MEDIA_ISP] = imx8m_clk_hw_composite("media_isp", imx8mp_media_isp_sels, ccm_base + 0x8400);
 
 	/* CORE SEL */
 	hws[IMX8MP_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core", ccm_base + 0x9880, 24, 1, imx8mp_a53_core_sels, ARRAY_SIZE(imx8mp_a53_core_sels));
@@ -713,8 +698,8 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MP_CLK_SDMA1_ROOT] = imx_clk_hw_gate4("sdma1_root_clk", "ipg_root", ccm_base + 0x43a0, 0);
 	hws[IMX8MP_CLK_ENET_QOS_ROOT] = imx_clk_hw_gate4("enet_qos_root_clk", "sim_enet_root_clk", ccm_base + 0x43b0, 0);
 	hws[IMX8MP_CLK_SIM_ENET_ROOT] = imx_clk_hw_gate4("sim_enet_root_clk", "enet_axi", ccm_base + 0x4400, 0);
-	hws[IMX8MP_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk", "gpu2d_div", ccm_base + 0x4450, 0);
-	hws[IMX8MP_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk", "gpu3d_core_div", ccm_base + 0x4460, 0);
+	hws[IMX8MP_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk", "gpu2d_core", ccm_base + 0x4450, 0);
+	hws[IMX8MP_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk", "gpu3d_core", ccm_base + 0x4460, 0);
 	hws[IMX8MP_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk", "ipg_root", ccm_base + 0x4470, 0);
 	hws[IMX8MP_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk", "uart1", ccm_base + 0x4490, 0);
 	hws[IMX8MP_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", ccm_base + 0x44a0, 0);
@@ -731,7 +716,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MP_CLK_GPU_ROOT] = imx_clk_hw_gate4("gpu_root_clk", "gpu_axi", ccm_base + 0x4570, 0);
 	hws[IMX8MP_CLK_VPU_VC8KE_ROOT] = imx_clk_hw_gate4("vpu_vc8ke_root_clk", "vpu_vc8000e", ccm_base + 0x4590, 0);
 	hws[IMX8MP_CLK_VPU_G2_ROOT] = imx_clk_hw_gate4("vpu_g2_root_clk", "vpu_g2", ccm_base + 0x45a0, 0);
-	hws[IMX8MP_CLK_NPU_ROOT] = imx_clk_hw_gate4("npu_root_clk", "ml_div", ccm_base + 0x45b0, 0);
+	hws[IMX8MP_CLK_NPU_ROOT] = imx_clk_hw_gate4("npu_root_clk", "ml_core", ccm_base + 0x45b0, 0);
 	hws[IMX8MP_CLK_HSIO_ROOT] = imx_clk_hw_gate4("hsio_root_clk", "ipg_root", ccm_base + 0x45c0, 0);
 	hws[IMX8MP_CLK_MEDIA_APB_ROOT] = imx_clk_hw_gate2_shared2("media_apb_root_clk", "media_apb", ccm_base + 0x45d0, 0, &share_count_media);
 	hws[IMX8MP_CLK_MEDIA_AXI_ROOT] = imx_clk_hw_gate2_shared2("media_axi_root_clk", "media_axi", ccm_base + 0x45d0, 0, &share_count_media);
@@ -739,7 +724,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_cam2_pix_root_clk", "media_cam2_pix", ccm_base + 0x45d0, 0, &share_count_media);
 	hws[IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_disp1_pix_root_clk", "media_disp1_pix", ccm_base + 0x45d0, 0, &share_count_media);
 	hws[IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_disp2_pix_root_clk", "media_disp2_pix", ccm_base + 0x45d0, 0, &share_count_media);
-	hws[IMX8MP_CLK_MEDIA_ISP_ROOT] = imx_clk_hw_gate2_shared2("media_isp_root_clk", "media_isp_div", ccm_base + 0x45d0, 0, &share_count_media);
+	hws[IMX8MP_CLK_MEDIA_ISP_ROOT] = imx_clk_hw_gate2_shared2("media_isp_root_clk", "media_isp", ccm_base + 0x45d0, 0, &share_count_media);
 
 	hws[IMX8MP_CLK_USDHC3_ROOT] = imx_clk_hw_gate4("usdhc3_root_clk", "usdhc3", ccm_base + 0x45e0, 0);
 	hws[IMX8MP_CLK_HDMI_ROOT] = imx_clk_hw_gate4("hdmi_root_clk", "hdmi_axi", ccm_base + 0x45f0, 0);
diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h
index 46c69cd66c62..8430bc4fd182 100644
--- a/include/dt-bindings/clock/imx8mp-clock.h
+++ b/include/dt-bindings/clock/imx8mp-clock.h
@@ -313,6 +313,15 @@
 #define IMX8MP_SYS_PLL2_333M_CG			303
 #define IMX8MP_SYS_PLL2_500M_CG			304
 
-#define IMX8MP_CLK_END				305
+#define IMX8MP_CLK_M7_CORE			305
+#define IMX8MP_CLK_ML_CORE			306
+#define IMX8MP_CLK_GPU3D_CORE			307
+#define IMX8MP_CLK_GPU3D_SHADER_CORE		308
+#define IMX8MP_CLK_GPU2D_CORE			309
+#define IMX8MP_CLK_AUDIO_AXI			310
+#define IMX8MP_CLK_HSIO_AXI			311
+#define IMX8MP_CLK_MEDIA_ISP			312
+
+#define IMX8MP_CLK_END				313
 
 #endif
-- 
2.16.4


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[PATCH V2 06/10] clk: imx8m: migrate A53 clk root to use composite core

[peng.fan]

From: Peng Fan <peng.fan@nxp.com>

Migrate A53 clk root to use composite core clk type. It
will simplify code and make it easy to use composite
specific mux operation.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx8mm.c | 6 +++---
 drivers/clk/imx/clk-imx8mn.c | 6 +++---
 drivers/clk/imx/clk-imx8mq.c | 6 +++---
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 5435042a06e3..12443e06f329 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -416,9 +416,9 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
 		return PTR_ERR(base);
 
 	/* Core Slice */
-	hws[IMX8MM_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels));
-	hws[IMX8MM_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28);
-	hws[IMX8MM_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
+	hws[IMX8MM_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mm_a53_sels, base + 0x8000);
+	hws[IMX8MM_CLK_A53_CG] = hws[IMX8MM_CLK_A53_DIV];
+	hws[IMX8MM_CLK_A53_SRC] = hws[IMX8MM_CLK_A53_DIV];
 
 	hws[IMX8MM_CLK_M4_CORE] = imx8m_clk_hw_composite_core("arm_m4_core", imx8mm_m4_sels, base + 0x8080);
 	hws[IMX8MM_CLK_VPU_CORE] = imx8m_clk_hw_composite_core("vpu_core", imx8mm_vpu_sels, base + 0x8100);
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 6cac6ca03e12..bd3759b4afd0 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -413,9 +413,9 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
 	}
 
 	/* CORE */
-	hws[IMX8MN_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels));
-	hws[IMX8MN_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28);
-	hws[IMX8MN_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
+	hws[IMX8MN_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mn_a53_sels, base + 0x8000);
+	hws[IMX8MN_CLK_A53_SRC] = hws[IMX8MN_CLK_A53_DIV];
+	hws[IMX8MN_CLK_A53_CG] = hws[IMX8MN_CLK_A53_DIV];
 
 	hws[IMX8MN_CLK_GPU_CORE] = imx8m_clk_hw_composite_core("gpu_core", imx8mn_gpu_core_sels, base + 0x8180);
 	hws[IMX8MN_CLK_GPU_SHADER] = imx8m_clk_hw_composite_core("gpu_shader", imx8mn_gpu_shader_sels, base + 0x8200);
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 201c7bbb201f..91309ff65441 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -405,9 +405,9 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
 		return PTR_ERR(base);
 
 	/* CORE */
-	hws[IMX8MQ_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels));
-	hws[IMX8MQ_CLK_A53_CG] = imx_clk_hw_gate3_flags("arm_a53_cg", "arm_a53_src", base + 0x8000, 28, CLK_IS_CRITICAL);
-	hws[IMX8MQ_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
+	hws[IMX8MQ_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mq_a53_sels, base + 0x8000);
+	hws[IMX8MQ_CLK_A53_CG] = hws[IMX8MQ_CLK_A53_DIV];
+	hws[IMX8MQ_CLK_A53_SRC] = hws[IMX8MQ_CLK_A53_DIV];
 
 	hws[IMX8MQ_CLK_M4_CORE] = imx8m_clk_hw_composite_core("arm_m4_core", imx8mq_arm_m4_sels, base + 0x8080);
 	hws[IMX8MQ_CLK_VPU_CORE] = imx8m_clk_hw_composite_core("vpu_core", imx8mq_vpu_sels, base + 0x8100);
-- 
2.16.4

[PATCH V2 06/10] clk: imx8m: migrate A53 clk root to use composite core

[peng.fan]

From: Peng Fan <peng.fan@nxp.com>

Migrate A53 clk root to use composite core clk type. It
will simplify code and make it easy to use composite
specific mux operation.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx8mm.c | 6 +++---
 drivers/clk/imx/clk-imx8mn.c | 6 +++---
 drivers/clk/imx/clk-imx8mq.c | 6 +++---
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 5435042a06e3..12443e06f329 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -416,9 +416,9 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
 		return PTR_ERR(base);
 
 	/* Core Slice */
-	hws[IMX8MM_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels));
-	hws[IMX8MM_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28);
-	hws[IMX8MM_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
+	hws[IMX8MM_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mm_a53_sels, base + 0x8000);
+	hws[IMX8MM_CLK_A53_CG] = hws[IMX8MM_CLK_A53_DIV];
+	hws[IMX8MM_CLK_A53_SRC] = hws[IMX8MM_CLK_A53_DIV];
 
 	hws[IMX8MM_CLK_M4_CORE] = imx8m_clk_hw_composite_core("arm_m4_core", imx8mm_m4_sels, base + 0x8080);
 	hws[IMX8MM_CLK_VPU_CORE] = imx8m_clk_hw_composite_core("vpu_core", imx8mm_vpu_sels, base + 0x8100);
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 6cac6ca03e12..bd3759b4afd0 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -413,9 +413,9 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
 	}
 
 	/* CORE */
-	hws[IMX8MN_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels));
-	hws[IMX8MN_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28);
-	hws[IMX8MN_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
+	hws[IMX8MN_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mn_a53_sels, base + 0x8000);
+	hws[IMX8MN_CLK_A53_SRC] = hws[IMX8MN_CLK_A53_DIV];
+	hws[IMX8MN_CLK_A53_CG] = hws[IMX8MN_CLK_A53_DIV];
 
 	hws[IMX8MN_CLK_GPU_CORE] = imx8m_clk_hw_composite_core("gpu_core", imx8mn_gpu_core_sels, base + 0x8180);
 	hws[IMX8MN_CLK_GPU_SHADER] = imx8m_clk_hw_composite_core("gpu_shader", imx8mn_gpu_shader_sels, base + 0x8200);
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 201c7bbb201f..91309ff65441 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -405,9 +405,9 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
 		return PTR_ERR(base);
 
 	/* CORE */
-	hws[IMX8MQ_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels));
-	hws[IMX8MQ_CLK_A53_CG] = imx_clk_hw_gate3_flags("arm_a53_cg", "arm_a53_src", base + 0x8000, 28, CLK_IS_CRITICAL);
-	hws[IMX8MQ_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
+	hws[IMX8MQ_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mq_a53_sels, base + 0x8000);
+	hws[IMX8MQ_CLK_A53_CG] = hws[IMX8MQ_CLK_A53_DIV];
+	hws[IMX8MQ_CLK_A53_SRC] = hws[IMX8MQ_CLK_A53_DIV];
 
 	hws[IMX8MQ_CLK_M4_CORE] = imx8m_clk_hw_composite_core("arm_m4_core", imx8mq_arm_m4_sels, base + 0x8080);
 	hws[IMX8MQ_CLK_VPU_CORE] = imx8m_clk_hw_composite_core("vpu_core", imx8mq_vpu_sels, base + 0x8100);
-- 
2.16.4


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[PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk

[peng.fan]

From: Peng Fan <peng.fan@nxp.com>

The CORE/BUS root slice has following design, simplied graph:
The difference is core not have pre_div block.
A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7].

            SEL_A  GA
            +--+  +-+
            |  +->+ +------+
CLK[0-7]--->+  |  +-+      |
       |    |  |      +----v---+    +----+
       |    +--+      |pre_diva+---->    |  +---------+
       |              +--------+    |mux +--+post_div |
       |    +--+      |pre_divb+--->+    |  +---------+
       |    |  |      +----^---+    +----+
       +--->+  |  +-+      |
            |  +->+ +------+
            +--+  +-+
            SEL_B  GB

There will be system hang, when doing the following steps:
1. switch mux from clk0 to clk1
2. gate off clk0
3. swtich from clk1 to clk2, or gate off clk1

Step 3 triggers system hang.

If we skip step2, keep clk0 on, step 3 will not trigger system hang.
However we have CLK_OPS_PARENT_ENABLE flag, which will unprepare disable
the clk0 which will not be used.

To address this issue, we could use following simplied software flow:
After the first target register set
wait the target register set finished
set the target register set again
wait the target register set finished

The upper flow will make sure SEL_A and SEL_B both set the new mux,
but with only one path gate on.

And there will be no system hang anymore with step3.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---

V2:
 Drop wait after write, add one line comment for write twice.

 drivers/clk/imx/clk-composite-8m.c | 62 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 61 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
index 99773519b5a5..eae02c151ced 100644
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -24,6 +24,12 @@
 
 #define PCG_CGC_SHIFT		28
 
+#define PRE_REG_OFF		0x30
+#define PRE_MUXA_SHIFT		24
+#define PRE_MUXA_MASK		0x7
+#define PRE_MUXB_SHIFT		8
+#define PRE_MUXB_MASK		0x7
+
 static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk_hw *hw,
 						unsigned long parent_rate)
 {
@@ -124,6 +130,57 @@ static const struct clk_ops imx8m_clk_composite_divider_ops = {
 	.set_rate = imx8m_clk_composite_divider_set_rate,
 };
 
+static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw)
+{
+	struct clk_mux *mux = to_clk_mux(hw);
+	u32 val;
+
+	val = readl(mux->reg) >> mux->shift;
+	val &= mux->mask;
+
+	return clk_mux_val_to_index(hw, mux->table, mux->flags, val);
+}
+
+static int imx8m_clk_composite_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+	struct clk_mux *mux = to_clk_mux(hw);
+	u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
+	unsigned long flags = 0;
+	u32 reg;
+
+	if (mux->lock)
+		spin_lock_irqsave(mux->lock, flags);
+
+	reg = readl(mux->reg);
+	reg &= ~(mux->mask << mux->shift);
+	val = val << mux->shift;
+	reg |= val;
+	/* write twice to make sure SEL_A/B point the same mux */
+	writel(reg, mux->reg);
+	writel(reg, mux->reg);
+
+	if (mux->lock)
+		spin_unlock_irqrestore(mux->lock, flags);
+
+	return 0;
+}
+
+static int
+imx8m_clk_composite_mux_determine_rate(struct clk_hw *hw,
+				       struct clk_rate_request *req)
+{
+	struct clk_mux *mux = to_clk_mux(hw);
+
+	return clk_mux_determine_rate_flags(hw, req, mux->flags);
+}
+
+
+const struct clk_ops imx8m_clk_composite_mux_ops = {
+	.get_parent = imx8m_clk_composite_mux_get_parent,
+	.set_parent = imx8m_clk_composite_mux_set_parent,
+	.determine_rate = imx8m_clk_composite_mux_determine_rate,
+};
+
 struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
 					const char * const *parent_names,
 					int num_parents, void __iomem *reg,
@@ -136,6 +193,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
 	struct clk_gate *gate = NULL;
 	struct clk_mux *mux = NULL;
 	const struct clk_ops *divider_ops;
+	const struct clk_ops *mux_ops;
 
 	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
 	if (!mux)
@@ -157,10 +215,12 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
 		div->shift = PCG_DIV_SHIFT;
 		div->width = PCG_CORE_DIV_WIDTH;
 		divider_ops = &clk_divider_ops;
+		mux_ops = &imx8m_clk_composite_mux_ops;
 	} else {
 		div->shift = PCG_PREDIV_SHIFT;
 		div->width = PCG_PREDIV_WIDTH;
 		divider_ops = &imx8m_clk_composite_divider_ops;
+		mux_ops = &clk_mux_ops;
 	}
 
 	div->lock = &imx_ccm_lock;
@@ -176,7 +236,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
 	gate->lock = &imx_ccm_lock;
 
 	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
-			mux_hw, &clk_mux_ops, div_hw,
+			mux_hw, mux_ops, div_hw,
 			divider_ops, gate_hw, &clk_gate_ops, flags);
 	if (IS_ERR(hw))
 		goto fail;
-- 
2.16.4

[PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk

[peng.fan]

From: Peng Fan <peng.fan@nxp.com>

The CORE/BUS root slice has following design, simplied graph:
The difference is core not have pre_div block.
A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7].

            SEL_A  GA
            +--+  +-+
            |  +->+ +------+
CLK[0-7]--->+  |  +-+      |
       |    |  |      +----v---+    +----+
       |    +--+      |pre_diva+---->    |  +---------+
       |              +--------+    |mux +--+post_div |
       |    +--+      |pre_divb+--->+    |  +---------+
       |    |  |      +----^---+    +----+
       +--->+  |  +-+      |
            |  +->+ +------+
            +--+  +-+
            SEL_B  GB

There will be system hang, when doing the following steps:
1. switch mux from clk0 to clk1
2. gate off clk0
3. swtich from clk1 to clk2, or gate off clk1

Step 3 triggers system hang.

If we skip step2, keep clk0 on, step 3 will not trigger system hang.
However we have CLK_OPS_PARENT_ENABLE flag, which will unprepare disable
the clk0 which will not be used.

To address this issue, we could use following simplied software flow:
After the first target register set
wait the target register set finished
set the target register set again
wait the target register set finished

The upper flow will make sure SEL_A and SEL_B both set the new mux,
but with only one path gate on.

And there will be no system hang anymore with step3.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---

V2:
 Drop wait after write, add one line comment for write twice.

 drivers/clk/imx/clk-composite-8m.c | 62 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 61 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
index 99773519b5a5..eae02c151ced 100644
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -24,6 +24,12 @@
 
 #define PCG_CGC_SHIFT		28
 
+#define PRE_REG_OFF		0x30
+#define PRE_MUXA_SHIFT		24
+#define PRE_MUXA_MASK		0x7
+#define PRE_MUXB_SHIFT		8
+#define PRE_MUXB_MASK		0x7
+
 static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk_hw *hw,
 						unsigned long parent_rate)
 {
@@ -124,6 +130,57 @@ static const struct clk_ops imx8m_clk_composite_divider_ops = {
 	.set_rate = imx8m_clk_composite_divider_set_rate,
 };
 
+static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw)
+{
+	struct clk_mux *mux = to_clk_mux(hw);
+	u32 val;
+
+	val = readl(mux->reg) >> mux->shift;
+	val &= mux->mask;
+
+	return clk_mux_val_to_index(hw, mux->table, mux->flags, val);
+}
+
+static int imx8m_clk_composite_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+	struct clk_mux *mux = to_clk_mux(hw);
+	u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
+	unsigned long flags = 0;
+	u32 reg;
+
+	if (mux->lock)
+		spin_lock_irqsave(mux->lock, flags);
+
+	reg = readl(mux->reg);
+	reg &= ~(mux->mask << mux->shift);
+	val = val << mux->shift;
+	reg |= val;
+	/* write twice to make sure SEL_A/B point the same mux */
+	writel(reg, mux->reg);
+	writel(reg, mux->reg);
+
+	if (mux->lock)
+		spin_unlock_irqrestore(mux->lock, flags);
+
+	return 0;
+}
+
+static int
+imx8m_clk_composite_mux_determine_rate(struct clk_hw *hw,
+				       struct clk_rate_request *req)
+{
+	struct clk_mux *mux = to_clk_mux(hw);
+
+	return clk_mux_determine_rate_flags(hw, req, mux->flags);
+}
+
+
+const struct clk_ops imx8m_clk_composite_mux_ops = {
+	.get_parent = imx8m_clk_composite_mux_get_parent,
+	.set_parent = imx8m_clk_composite_mux_set_parent,
+	.determine_rate = imx8m_clk_composite_mux_determine_rate,
+};
+
 struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
 					const char * const *parent_names,
 					int num_parents, void __iomem *reg,
@@ -136,6 +193,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
 	struct clk_gate *gate = NULL;
 	struct clk_mux *mux = NULL;
 	const struct clk_ops *divider_ops;
+	const struct clk_ops *mux_ops;
 
 	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
 	if (!mux)
@@ -157,10 +215,12 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
 		div->shift = PCG_DIV_SHIFT;
 		div->width = PCG_CORE_DIV_WIDTH;
 		divider_ops = &clk_divider_ops;
+		mux_ops = &imx8m_clk_composite_mux_ops;
 	} else {
 		div->shift = PCG_PREDIV_SHIFT;
 		div->width = PCG_PREDIV_WIDTH;
 		divider_ops = &imx8m_clk_composite_divider_ops;
+		mux_ops = &clk_mux_ops;
 	}
 
 	div->lock = &imx_ccm_lock;
@@ -176,7 +236,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
 	gate->lock = &imx_ccm_lock;
 
 	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
-			mux_hw, &clk_mux_ops, div_hw,
+			mux_hw, mux_ops, div_hw,
 			divider_ops, gate_hw, &clk_gate_ops, flags);
 	if (IS_ERR(hw))
 		goto fail;
-- 
2.16.4


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[PATCH V2 08/10] clk: imx: add imx8m_clk_hw_composite_bus

[peng.fan]

From: Peng Fan <peng.fan@nxp.com>

Introduce imx8m_clk_hw_composite_bus api for bus clk root slice usage.
Because the mux switch sequence issue, we could not reuse Peripheral
Clock Slice code, need use composite specific mux operation.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-composite-8m.c | 5 +++++
 drivers/clk/imx/clk.h              | 7 +++++++
 2 files changed, 12 insertions(+)

diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
index eae02c151ced..ec28643426c2 100644
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -216,6 +216,11 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
 		div->width = PCG_CORE_DIV_WIDTH;
 		divider_ops = &clk_divider_ops;
 		mux_ops = &imx8m_clk_composite_mux_ops;
+	} else if (composite_flags & IMX_COMPOSITE_BUS) {
+		div->shift = PCG_PREDIV_SHIFT;
+		div->width = PCG_PREDIV_WIDTH;
+		divider_ops = &imx8m_clk_composite_divider_ops;
+		mux_ops = &imx8m_clk_composite_mux_ops;
 	} else {
 		div->shift = PCG_PREDIV_SHIFT;
 		div->width = PCG_PREDIV_WIDTH;
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index f074dd8ec42e..d4ea1609bcb7 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -478,6 +478,7 @@ struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
 		struct clk *step);
 
 #define IMX_COMPOSITE_CORE	BIT(0)
+#define IMX_COMPOSITE_BUS	BIT(1)
 
 struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
 					    const char * const *parent_names,
@@ -486,6 +487,12 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
 					    u32 composite_flags,
 					    unsigned long flags);
 
+#define imx8m_clk_hw_composite_bus(name, parent_names, reg)	\
+	imx8m_clk_hw_composite_flags(name, parent_names, \
+			ARRAY_SIZE(parent_names), reg, \
+			IMX_COMPOSITE_BUS, \
+			CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
+
 #define imx8m_clk_hw_composite_core(name, parent_names, reg)	\
 	imx8m_clk_hw_composite_flags(name, parent_names, \
 			ARRAY_SIZE(parent_names), reg, \
-- 
2.16.4

[PATCH V2 08/10] clk: imx: add imx8m_clk_hw_composite_bus

[peng.fan]

From: Peng Fan <peng.fan@nxp.com>

Introduce imx8m_clk_hw_composite_bus api for bus clk root slice usage.
Because the mux switch sequence issue, we could not reuse Peripheral
Clock Slice code, need use composite specific mux operation.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-composite-8m.c | 5 +++++
 drivers/clk/imx/clk.h              | 7 +++++++
 2 files changed, 12 insertions(+)

diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
index eae02c151ced..ec28643426c2 100644
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -216,6 +216,11 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
 		div->width = PCG_CORE_DIV_WIDTH;
 		divider_ops = &clk_divider_ops;
 		mux_ops = &imx8m_clk_composite_mux_ops;
+	} else if (composite_flags & IMX_COMPOSITE_BUS) {
+		div->shift = PCG_PREDIV_SHIFT;
+		div->width = PCG_PREDIV_WIDTH;
+		divider_ops = &imx8m_clk_composite_divider_ops;
+		mux_ops = &imx8m_clk_composite_mux_ops;
 	} else {
 		div->shift = PCG_PREDIV_SHIFT;
 		div->width = PCG_PREDIV_WIDTH;
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index f074dd8ec42e..d4ea1609bcb7 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -478,6 +478,7 @@ struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
 		struct clk *step);
 
 #define IMX_COMPOSITE_CORE	BIT(0)
+#define IMX_COMPOSITE_BUS	BIT(1)
 
 struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
 					    const char * const *parent_names,
@@ -486,6 +487,12 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
 					    u32 composite_flags,
 					    unsigned long flags);
 
+#define imx8m_clk_hw_composite_bus(name, parent_names, reg)	\
+	imx8m_clk_hw_composite_flags(name, parent_names, \
+			ARRAY_SIZE(parent_names), reg, \
+			IMX_COMPOSITE_BUS, \
+			CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
+
 #define imx8m_clk_hw_composite_core(name, parent_names, reg)	\
 	imx8m_clk_hw_composite_flags(name, parent_names, \
 			ARRAY_SIZE(parent_names), reg, \
-- 
2.16.4


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[PATCH V2 09/10] clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice

[peng.fan]

From: Peng Fan <peng.fan@nxp.com>

Switch the bus clk use imx8m_clk_hw_composite_bus, then
we could avoid possible issue when setting mux of the clk.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx8mm.c | 18 +++++++++---------
 drivers/clk/imx/clk-imx8mn.c | 16 ++++++++--------
 drivers/clk/imx/clk-imx8mp.c | 24 ++++++++++++------------
 drivers/clk/imx/clk-imx8mq.c | 20 ++++++++++----------
 4 files changed, 39 insertions(+), 39 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 12443e06f329..b793264c21c6 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -444,21 +444,21 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
 
 	/* BUS */
 	hws[IMX8MM_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi",  imx8mm_main_axi_sels, base + 0x8800);
-	hws[IMX8MM_CLK_ENET_AXI] = imx8m_clk_hw_composite("enet_axi", imx8mm_enet_axi_sels, base + 0x8880);
+	hws[IMX8MM_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi", imx8mm_enet_axi_sels, base + 0x8880);
 	hws[IMX8MM_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_critical("nand_usdhc_bus", imx8mm_nand_usdhc_sels, base + 0x8900);
-	hws[IMX8MM_CLK_VPU_BUS] = imx8m_clk_hw_composite("vpu_bus", imx8mm_vpu_bus_sels, base + 0x8980);
-	hws[IMX8MM_CLK_DISP_AXI] = imx8m_clk_hw_composite("disp_axi", imx8mm_disp_axi_sels, base + 0x8a00);
-	hws[IMX8MM_CLK_DISP_APB] = imx8m_clk_hw_composite("disp_apb", imx8mm_disp_apb_sels, base + 0x8a80);
-	hws[IMX8MM_CLK_DISP_RTRM] = imx8m_clk_hw_composite("disp_rtrm", imx8mm_disp_rtrm_sels, base + 0x8b00);
-	hws[IMX8MM_CLK_USB_BUS] = imx8m_clk_hw_composite("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80);
-	hws[IMX8MM_CLK_GPU_AXI] = imx8m_clk_hw_composite("gpu_axi", imx8mm_gpu_axi_sels, base + 0x8c00);
-	hws[IMX8MM_CLK_GPU_AHB] = imx8m_clk_hw_composite("gpu_ahb", imx8mm_gpu_ahb_sels, base + 0x8c80);
+	hws[IMX8MM_CLK_VPU_BUS] = imx8m_clk_hw_composite_bus("vpu_bus", imx8mm_vpu_bus_sels, base + 0x8980);
+	hws[IMX8MM_CLK_DISP_AXI] = imx8m_clk_hw_composite_bus("disp_axi", imx8mm_disp_axi_sels, base + 0x8a00);
+	hws[IMX8MM_CLK_DISP_APB] = imx8m_clk_hw_composite_bus("disp_apb", imx8mm_disp_apb_sels, base + 0x8a80);
+	hws[IMX8MM_CLK_DISP_RTRM] = imx8m_clk_hw_composite_bus("disp_rtrm", imx8mm_disp_rtrm_sels, base + 0x8b00);
+	hws[IMX8MM_CLK_USB_BUS] = imx8m_clk_hw_composite_bus("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80);
+	hws[IMX8MM_CLK_GPU_AXI] = imx8m_clk_hw_composite_bus("gpu_axi", imx8mm_gpu_axi_sels, base + 0x8c00);
+	hws[IMX8MM_CLK_GPU_AHB] = imx8m_clk_hw_composite_bus("gpu_ahb", imx8mm_gpu_ahb_sels, base + 0x8c80);
 	hws[IMX8MM_CLK_NOC] = imx8m_clk_hw_composite_critical("noc", imx8mm_noc_sels, base + 0x8d00);
 	hws[IMX8MM_CLK_NOC_APB] = imx8m_clk_hw_composite_critical("noc_apb", imx8mm_noc_apb_sels, base + 0x8d80);
 
 	/* AHB */
 	hws[IMX8MM_CLK_AHB] = imx8m_clk_hw_composite_critical("ahb", imx8mm_ahb_sels, base + 0x9000);
-	hws[IMX8MM_CLK_AUDIO_AHB] = imx8m_clk_hw_composite("audio_ahb", imx8mm_audio_ahb_sels, base + 0x9100);
+	hws[IMX8MM_CLK_AUDIO_AHB] = imx8m_clk_hw_composite_bus("audio_ahb", imx8mm_audio_ahb_sels, base + 0x9100);
 
 	/* IPG */
 	hws[IMX8MM_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb", base + 0x9080, 0, 1);
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index bd3759b4afd0..213cc37b3173 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -432,17 +432,17 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
 
 	/* BUS */
 	hws[IMX8MN_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi", imx8mn_main_axi_sels, base + 0x8800);
-	hws[IMX8MN_CLK_ENET_AXI] = imx8m_clk_hw_composite("enet_axi", imx8mn_enet_axi_sels, base + 0x8880);
-	hws[IMX8MN_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite("nand_usdhc_bus", imx8mn_nand_usdhc_sels, base + 0x8900);
-	hws[IMX8MN_CLK_DISP_AXI] = imx8m_clk_hw_composite("disp_axi", imx8mn_disp_axi_sels, base + 0x8a00);
-	hws[IMX8MN_CLK_DISP_APB] = imx8m_clk_hw_composite("disp_apb", imx8mn_disp_apb_sels, base + 0x8a80);
-	hws[IMX8MN_CLK_USB_BUS] = imx8m_clk_hw_composite("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80);
-	hws[IMX8MN_CLK_GPU_AXI] = imx8m_clk_hw_composite("gpu_axi", imx8mn_gpu_axi_sels, base + 0x8c00);
-	hws[IMX8MN_CLK_GPU_AHB] = imx8m_clk_hw_composite("gpu_ahb", imx8mn_gpu_ahb_sels, base + 0x8c80);
+	hws[IMX8MN_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi", imx8mn_enet_axi_sels, base + 0x8880);
+	hws[IMX8MN_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_bus("nand_usdhc_bus", imx8mn_nand_usdhc_sels, base + 0x8900);
+	hws[IMX8MN_CLK_DISP_AXI] = imx8m_clk_hw_composite_bus("disp_axi", imx8mn_disp_axi_sels, base + 0x8a00);
+	hws[IMX8MN_CLK_DISP_APB] = imx8m_clk_hw_composite_bus("disp_apb", imx8mn_disp_apb_sels, base + 0x8a80);
+	hws[IMX8MN_CLK_USB_BUS] = imx8m_clk_hw_composite_bus("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80);
+	hws[IMX8MN_CLK_GPU_AXI] = imx8m_clk_hw_composite_bus("gpu_axi", imx8mn_gpu_axi_sels, base + 0x8c00);
+	hws[IMX8MN_CLK_GPU_AHB] = imx8m_clk_hw_composite_bus("gpu_ahb", imx8mn_gpu_ahb_sels, base + 0x8c80);
 	hws[IMX8MN_CLK_NOC] = imx8m_clk_hw_composite_critical("noc", imx8mn_noc_sels, base + 0x8d00);
 
 	hws[IMX8MN_CLK_AHB] = imx8m_clk_hw_composite_critical("ahb", imx8mn_ahb_sels, base + 0x9000);
-	hws[IMX8MN_CLK_AUDIO_AHB] = imx8m_clk_hw_composite("audio_ahb", imx8mn_audio_ahb_sels, base + 0x9100);
+	hws[IMX8MN_CLK_AUDIO_AHB] = imx8m_clk_hw_composite_bus("audio_ahb", imx8mn_audio_ahb_sels, base + 0x9100);
 	hws[IMX8MN_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb", base + 0x9080, 0, 1);
 	hws[IMX8MN_CLK_IPG_AUDIO_ROOT] = imx_clk_hw_divider2("ipg_audio_root", "audio_ahb", base + 0x9180, 0, 1);
 	hws[IMX8MN_CLK_DRAM_CORE] = imx_clk_hw_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mn_dram_core_sels, ARRAY_SIZE(imx8mn_dram_core_sels), CLK_IS_CRITICAL);
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 998e9e63f831..b4d9db9d5bf1 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -563,23 +563,23 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MP_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core", ccm_base + 0x9880, 24, 1, imx8mp_a53_core_sels, ARRAY_SIZE(imx8mp_a53_core_sels));
 
 	hws[IMX8MP_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi", imx8mp_main_axi_sels, ccm_base + 0x8800);
-	hws[IMX8MP_CLK_ENET_AXI] = imx8m_clk_hw_composite("enet_axi", imx8mp_enet_axi_sels, ccm_base + 0x8880);
+	hws[IMX8MP_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi", imx8mp_enet_axi_sels, ccm_base + 0x8880);
 	hws[IMX8MP_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, ccm_base + 0x8900);
-	hws[IMX8MP_CLK_VPU_BUS] = imx8m_clk_hw_composite("vpu_bus", imx8mp_vpu_bus_sels, ccm_base + 0x8980);
-	hws[IMX8MP_CLK_MEDIA_AXI] = imx8m_clk_hw_composite("media_axi", imx8mp_media_axi_sels, ccm_base + 0x8a00);
-	hws[IMX8MP_CLK_MEDIA_APB] = imx8m_clk_hw_composite("media_apb", imx8mp_media_apb_sels, ccm_base + 0x8a80);
-	hws[IMX8MP_CLK_HDMI_APB] = imx8m_clk_hw_composite("hdmi_apb", imx8mp_media_apb_sels, ccm_base + 0x8b00);
-	hws[IMX8MP_CLK_HDMI_AXI] = imx8m_clk_hw_composite("hdmi_axi", imx8mp_media_axi_sels, ccm_base + 0x8b80);
-	hws[IMX8MP_CLK_GPU_AXI] = imx8m_clk_hw_composite("gpu_axi", imx8mp_gpu_axi_sels, ccm_base + 0x8c00);
-	hws[IMX8MP_CLK_GPU_AHB] = imx8m_clk_hw_composite("gpu_ahb", imx8mp_gpu_ahb_sels, ccm_base + 0x8c80);
+	hws[IMX8MP_CLK_VPU_BUS] = imx8m_clk_hw_composite_bus("vpu_bus", imx8mp_vpu_bus_sels, ccm_base + 0x8980);
+	hws[IMX8MP_CLK_MEDIA_AXI] = imx8m_clk_hw_composite_bus("media_axi", imx8mp_media_axi_sels, ccm_base + 0x8a00);
+	hws[IMX8MP_CLK_MEDIA_APB] = imx8m_clk_hw_composite_bus("media_apb", imx8mp_media_apb_sels, ccm_base + 0x8a80);
+	hws[IMX8MP_CLK_HDMI_APB] = imx8m_clk_hw_composite_bus("hdmi_apb", imx8mp_media_apb_sels, ccm_base + 0x8b00);
+	hws[IMX8MP_CLK_HDMI_AXI] = imx8m_clk_hw_composite_bus("hdmi_axi", imx8mp_media_axi_sels, ccm_base + 0x8b80);
+	hws[IMX8MP_CLK_GPU_AXI] = imx8m_clk_hw_composite_bus("gpu_axi", imx8mp_gpu_axi_sels, ccm_base + 0x8c00);
+	hws[IMX8MP_CLK_GPU_AHB] = imx8m_clk_hw_composite_bus("gpu_ahb", imx8mp_gpu_ahb_sels, ccm_base + 0x8c80);
 	hws[IMX8MP_CLK_NOC] = imx8m_clk_hw_composite_critical("noc", imx8mp_noc_sels, ccm_base + 0x8d00);
 	hws[IMX8MP_CLK_NOC_IO] = imx8m_clk_hw_composite_critical("noc_io", imx8mp_noc_io_sels, ccm_base + 0x8d80);
-	hws[IMX8MP_CLK_ML_AXI] = imx8m_clk_hw_composite("ml_axi", imx8mp_ml_axi_sels, ccm_base + 0x8e00);
-	hws[IMX8MP_CLK_ML_AHB] = imx8m_clk_hw_composite("ml_ahb", imx8mp_ml_ahb_sels, ccm_base + 0x8e80);
+	hws[IMX8MP_CLK_ML_AXI] = imx8m_clk_hw_composite_bus("ml_axi", imx8mp_ml_axi_sels, ccm_base + 0x8e00);
+	hws[IMX8MP_CLK_ML_AHB] = imx8m_clk_hw_composite_bus("ml_ahb", imx8mp_ml_ahb_sels, ccm_base + 0x8e80);
 
 	hws[IMX8MP_CLK_AHB] = imx8m_clk_hw_composite_critical("ahb_root", imx8mp_ahb_sels, ccm_base + 0x9000);
-	hws[IMX8MP_CLK_AUDIO_AHB] = imx8m_clk_hw_composite("audio_ahb", imx8mp_audio_ahb_sels, ccm_base + 0x9100);
-	hws[IMX8MP_CLK_MIPI_DSI_ESC_RX] = imx8m_clk_hw_composite("mipi_dsi_esc_rx", imx8mp_mipi_dsi_esc_rx_sels, ccm_base + 0x9200);
+	hws[IMX8MP_CLK_AUDIO_AHB] = imx8m_clk_hw_composite_bus("audio_ahb", imx8mp_audio_ahb_sels, ccm_base + 0x9100);
+	hws[IMX8MP_CLK_MIPI_DSI_ESC_RX] = imx8m_clk_hw_composite_bus("mipi_dsi_esc_rx", imx8mp_mipi_dsi_esc_rx_sels, ccm_base + 0x9200);
 
 	hws[IMX8MP_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb_root", ccm_base + 0x9080, 0, 1);
 	hws[IMX8MP_CLK_IPG_AUDIO_ROOT] = imx_clk_hw_divider2("ipg_audio_root", "audio_ahb", ccm_base + 0x9180, 0, 1);
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 91309ff65441..a64aace213c2 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -432,22 +432,22 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
 
 	/* BUS */
 	hws[IMX8MQ_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi", imx8mq_main_axi_sels, base + 0x8800);
-	hws[IMX8MQ_CLK_ENET_AXI] = imx8m_clk_hw_composite("enet_axi", imx8mq_enet_axi_sels, base + 0x8880);
-	hws[IMX8MQ_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite("nand_usdhc_bus", imx8mq_nand_usdhc_sels, base + 0x8900);
-	hws[IMX8MQ_CLK_VPU_BUS] = imx8m_clk_hw_composite("vpu_bus", imx8mq_vpu_bus_sels, base + 0x8980);
-	hws[IMX8MQ_CLK_DISP_AXI] = imx8m_clk_hw_composite("disp_axi", imx8mq_disp_axi_sels, base + 0x8a00);
-	hws[IMX8MQ_CLK_DISP_APB] = imx8m_clk_hw_composite("disp_apb", imx8mq_disp_apb_sels, base + 0x8a80);
-	hws[IMX8MQ_CLK_DISP_RTRM] = imx8m_clk_hw_composite("disp_rtrm", imx8mq_disp_rtrm_sels, base + 0x8b00);
-	hws[IMX8MQ_CLK_USB_BUS] = imx8m_clk_hw_composite("usb_bus", imx8mq_usb_bus_sels, base + 0x8b80);
-	hws[IMX8MQ_CLK_GPU_AXI] = imx8m_clk_hw_composite("gpu_axi", imx8mq_gpu_axi_sels, base + 0x8c00);
-	hws[IMX8MQ_CLK_GPU_AHB] = imx8m_clk_hw_composite("gpu_ahb", imx8mq_gpu_ahb_sels, base + 0x8c80);
+	hws[IMX8MQ_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi", imx8mq_enet_axi_sels, base + 0x8880);
+	hws[IMX8MQ_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_bus("nand_usdhc_bus", imx8mq_nand_usdhc_sels, base + 0x8900);
+	hws[IMX8MQ_CLK_VPU_BUS] = imx8m_clk_hw_composite_bus("vpu_bus", imx8mq_vpu_bus_sels, base + 0x8980);
+	hws[IMX8MQ_CLK_DISP_AXI] = imx8m_clk_hw_composite_bus("disp_axi", imx8mq_disp_axi_sels, base + 0x8a00);
+	hws[IMX8MQ_CLK_DISP_APB] = imx8m_clk_hw_composite_bus("disp_apb", imx8mq_disp_apb_sels, base + 0x8a80);
+	hws[IMX8MQ_CLK_DISP_RTRM] = imx8m_clk_hw_composite_bus("disp_rtrm", imx8mq_disp_rtrm_sels, base + 0x8b00);
+	hws[IMX8MQ_CLK_USB_BUS] = imx8m_clk_hw_composite_bus("usb_bus", imx8mq_usb_bus_sels, base + 0x8b80);
+	hws[IMX8MQ_CLK_GPU_AXI] = imx8m_clk_hw_composite_bus("gpu_axi", imx8mq_gpu_axi_sels, base + 0x8c00);
+	hws[IMX8MQ_CLK_GPU_AHB] = imx8m_clk_hw_composite_bus("gpu_ahb", imx8mq_gpu_ahb_sels, base + 0x8c80);
 	hws[IMX8MQ_CLK_NOC] = imx8m_clk_hw_composite_critical("noc", imx8mq_noc_sels, base + 0x8d00);
 	hws[IMX8MQ_CLK_NOC_APB] = imx8m_clk_hw_composite_critical("noc_apb", imx8mq_noc_apb_sels, base + 0x8d80);
 
 	/* AHB */
 	/* AHB clock is used by the AHB bus therefore marked as critical */
 	hws[IMX8MQ_CLK_AHB] = imx8m_clk_hw_composite_critical("ahb", imx8mq_ahb_sels, base + 0x9000);
-	hws[IMX8MQ_CLK_AUDIO_AHB] = imx8m_clk_hw_composite("audio_ahb", imx8mq_audio_ahb_sels, base + 0x9100);
+	hws[IMX8MQ_CLK_AUDIO_AHB] = imx8m_clk_hw_composite_bus("audio_ahb", imx8mq_audio_ahb_sels, base + 0x9100);
 
 	/* IPG */
 	hws[IMX8MQ_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb", base + 0x9080, 0, 1);
-- 
2.16.4

[PATCH V2 09/10] clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice

[peng.fan]

From: Peng Fan <peng.fan@nxp.com>

Switch the bus clk use imx8m_clk_hw_composite_bus, then
we could avoid possible issue when setting mux of the clk.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx8mm.c | 18 +++++++++---------
 drivers/clk/imx/clk-imx8mn.c | 16 ++++++++--------
 drivers/clk/imx/clk-imx8mp.c | 24 ++++++++++++------------
 drivers/clk/imx/clk-imx8mq.c | 20 ++++++++++----------
 4 files changed, 39 insertions(+), 39 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 12443e06f329..b793264c21c6 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -444,21 +444,21 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
 
 	/* BUS */
 	hws[IMX8MM_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi",  imx8mm_main_axi_sels, base + 0x8800);
-	hws[IMX8MM_CLK_ENET_AXI] = imx8m_clk_hw_composite("enet_axi", imx8mm_enet_axi_sels, base + 0x8880);
+	hws[IMX8MM_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi", imx8mm_enet_axi_sels, base + 0x8880);
 	hws[IMX8MM_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_critical("nand_usdhc_bus", imx8mm_nand_usdhc_sels, base + 0x8900);
-	hws[IMX8MM_CLK_VPU_BUS] = imx8m_clk_hw_composite("vpu_bus", imx8mm_vpu_bus_sels, base + 0x8980);
-	hws[IMX8MM_CLK_DISP_AXI] = imx8m_clk_hw_composite("disp_axi", imx8mm_disp_axi_sels, base + 0x8a00);
-	hws[IMX8MM_CLK_DISP_APB] = imx8m_clk_hw_composite("disp_apb", imx8mm_disp_apb_sels, base + 0x8a80);
-	hws[IMX8MM_CLK_DISP_RTRM] = imx8m_clk_hw_composite("disp_rtrm", imx8mm_disp_rtrm_sels, base + 0x8b00);
-	hws[IMX8MM_CLK_USB_BUS] = imx8m_clk_hw_composite("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80);
-	hws[IMX8MM_CLK_GPU_AXI] = imx8m_clk_hw_composite("gpu_axi", imx8mm_gpu_axi_sels, base + 0x8c00);
-	hws[IMX8MM_CLK_GPU_AHB] = imx8m_clk_hw_composite("gpu_ahb", imx8mm_gpu_ahb_sels, base + 0x8c80);
+	hws[IMX8MM_CLK_VPU_BUS] = imx8m_clk_hw_composite_bus("vpu_bus", imx8mm_vpu_bus_sels, base + 0x8980);
+	hws[IMX8MM_CLK_DISP_AXI] = imx8m_clk_hw_composite_bus("disp_axi", imx8mm_disp_axi_sels, base + 0x8a00);
+	hws[IMX8MM_CLK_DISP_APB] = imx8m_clk_hw_composite_bus("disp_apb", imx8mm_disp_apb_sels, base + 0x8a80);
+	hws[IMX8MM_CLK_DISP_RTRM] = imx8m_clk_hw_composite_bus("disp_rtrm", imx8mm_disp_rtrm_sels, base + 0x8b00);
+	hws[IMX8MM_CLK_USB_BUS] = imx8m_clk_hw_composite_bus("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80);
+	hws[IMX8MM_CLK_GPU_AXI] = imx8m_clk_hw_composite_bus("gpu_axi", imx8mm_gpu_axi_sels, base + 0x8c00);
+	hws[IMX8MM_CLK_GPU_AHB] = imx8m_clk_hw_composite_bus("gpu_ahb", imx8mm_gpu_ahb_sels, base + 0x8c80);
 	hws[IMX8MM_CLK_NOC] = imx8m_clk_hw_composite_critical("noc", imx8mm_noc_sels, base + 0x8d00);
 	hws[IMX8MM_CLK_NOC_APB] = imx8m_clk_hw_composite_critical("noc_apb", imx8mm_noc_apb_sels, base + 0x8d80);
 
 	/* AHB */
 	hws[IMX8MM_CLK_AHB] = imx8m_clk_hw_composite_critical("ahb", imx8mm_ahb_sels, base + 0x9000);
-	hws[IMX8MM_CLK_AUDIO_AHB] = imx8m_clk_hw_composite("audio_ahb", imx8mm_audio_ahb_sels, base + 0x9100);
+	hws[IMX8MM_CLK_AUDIO_AHB] = imx8m_clk_hw_composite_bus("audio_ahb", imx8mm_audio_ahb_sels, base + 0x9100);
 
 	/* IPG */
 	hws[IMX8MM_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb", base + 0x9080, 0, 1);
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index bd3759b4afd0..213cc37b3173 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -432,17 +432,17 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
 
 	/* BUS */
 	hws[IMX8MN_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi", imx8mn_main_axi_sels, base + 0x8800);
-	hws[IMX8MN_CLK_ENET_AXI] = imx8m_clk_hw_composite("enet_axi", imx8mn_enet_axi_sels, base + 0x8880);
-	hws[IMX8MN_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite("nand_usdhc_bus", imx8mn_nand_usdhc_sels, base + 0x8900);
-	hws[IMX8MN_CLK_DISP_AXI] = imx8m_clk_hw_composite("disp_axi", imx8mn_disp_axi_sels, base + 0x8a00);
-	hws[IMX8MN_CLK_DISP_APB] = imx8m_clk_hw_composite("disp_apb", imx8mn_disp_apb_sels, base + 0x8a80);
-	hws[IMX8MN_CLK_USB_BUS] = imx8m_clk_hw_composite("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80);
-	hws[IMX8MN_CLK_GPU_AXI] = imx8m_clk_hw_composite("gpu_axi", imx8mn_gpu_axi_sels, base + 0x8c00);
-	hws[IMX8MN_CLK_GPU_AHB] = imx8m_clk_hw_composite("gpu_ahb", imx8mn_gpu_ahb_sels, base + 0x8c80);
+	hws[IMX8MN_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi", imx8mn_enet_axi_sels, base + 0x8880);
+	hws[IMX8MN_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_bus("nand_usdhc_bus", imx8mn_nand_usdhc_sels, base + 0x8900);
+	hws[IMX8MN_CLK_DISP_AXI] = imx8m_clk_hw_composite_bus("disp_axi", imx8mn_disp_axi_sels, base + 0x8a00);
+	hws[IMX8MN_CLK_DISP_APB] = imx8m_clk_hw_composite_bus("disp_apb", imx8mn_disp_apb_sels, base + 0x8a80);
+	hws[IMX8MN_CLK_USB_BUS] = imx8m_clk_hw_composite_bus("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80);
+	hws[IMX8MN_CLK_GPU_AXI] = imx8m_clk_hw_composite_bus("gpu_axi", imx8mn_gpu_axi_sels, base + 0x8c00);
+	hws[IMX8MN_CLK_GPU_AHB] = imx8m_clk_hw_composite_bus("gpu_ahb", imx8mn_gpu_ahb_sels, base + 0x8c80);
 	hws[IMX8MN_CLK_NOC] = imx8m_clk_hw_composite_critical("noc", imx8mn_noc_sels, base + 0x8d00);
 
 	hws[IMX8MN_CLK_AHB] = imx8m_clk_hw_composite_critical("ahb", imx8mn_ahb_sels, base + 0x9000);
-	hws[IMX8MN_CLK_AUDIO_AHB] = imx8m_clk_hw_composite("audio_ahb", imx8mn_audio_ahb_sels, base + 0x9100);
+	hws[IMX8MN_CLK_AUDIO_AHB] = imx8m_clk_hw_composite_bus("audio_ahb", imx8mn_audio_ahb_sels, base + 0x9100);
 	hws[IMX8MN_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb", base + 0x9080, 0, 1);
 	hws[IMX8MN_CLK_IPG_AUDIO_ROOT] = imx_clk_hw_divider2("ipg_audio_root", "audio_ahb", base + 0x9180, 0, 1);
 	hws[IMX8MN_CLK_DRAM_CORE] = imx_clk_hw_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mn_dram_core_sels, ARRAY_SIZE(imx8mn_dram_core_sels), CLK_IS_CRITICAL);
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 998e9e63f831..b4d9db9d5bf1 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -563,23 +563,23 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MP_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core", ccm_base + 0x9880, 24, 1, imx8mp_a53_core_sels, ARRAY_SIZE(imx8mp_a53_core_sels));
 
 	hws[IMX8MP_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi", imx8mp_main_axi_sels, ccm_base + 0x8800);
-	hws[IMX8MP_CLK_ENET_AXI] = imx8m_clk_hw_composite("enet_axi", imx8mp_enet_axi_sels, ccm_base + 0x8880);
+	hws[IMX8MP_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi", imx8mp_enet_axi_sels, ccm_base + 0x8880);
 	hws[IMX8MP_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, ccm_base + 0x8900);
-	hws[IMX8MP_CLK_VPU_BUS] = imx8m_clk_hw_composite("vpu_bus", imx8mp_vpu_bus_sels, ccm_base + 0x8980);
-	hws[IMX8MP_CLK_MEDIA_AXI] = imx8m_clk_hw_composite("media_axi", imx8mp_media_axi_sels, ccm_base + 0x8a00);
-	hws[IMX8MP_CLK_MEDIA_APB] = imx8m_clk_hw_composite("media_apb", imx8mp_media_apb_sels, ccm_base + 0x8a80);
-	hws[IMX8MP_CLK_HDMI_APB] = imx8m_clk_hw_composite("hdmi_apb", imx8mp_media_apb_sels, ccm_base + 0x8b00);
-	hws[IMX8MP_CLK_HDMI_AXI] = imx8m_clk_hw_composite("hdmi_axi", imx8mp_media_axi_sels, ccm_base + 0x8b80);
-	hws[IMX8MP_CLK_GPU_AXI] = imx8m_clk_hw_composite("gpu_axi", imx8mp_gpu_axi_sels, ccm_base + 0x8c00);
-	hws[IMX8MP_CLK_GPU_AHB] = imx8m_clk_hw_composite("gpu_ahb", imx8mp_gpu_ahb_sels, ccm_base + 0x8c80);
+	hws[IMX8MP_CLK_VPU_BUS] = imx8m_clk_hw_composite_bus("vpu_bus", imx8mp_vpu_bus_sels, ccm_base + 0x8980);
+	hws[IMX8MP_CLK_MEDIA_AXI] = imx8m_clk_hw_composite_bus("media_axi", imx8mp_media_axi_sels, ccm_base + 0x8a00);
+	hws[IMX8MP_CLK_MEDIA_APB] = imx8m_clk_hw_composite_bus("media_apb", imx8mp_media_apb_sels, ccm_base + 0x8a80);
+	hws[IMX8MP_CLK_HDMI_APB] = imx8m_clk_hw_composite_bus("hdmi_apb", imx8mp_media_apb_sels, ccm_base + 0x8b00);
+	hws[IMX8MP_CLK_HDMI_AXI] = imx8m_clk_hw_composite_bus("hdmi_axi", imx8mp_media_axi_sels, ccm_base + 0x8b80);
+	hws[IMX8MP_CLK_GPU_AXI] = imx8m_clk_hw_composite_bus("gpu_axi", imx8mp_gpu_axi_sels, ccm_base + 0x8c00);
+	hws[IMX8MP_CLK_GPU_AHB] = imx8m_clk_hw_composite_bus("gpu_ahb", imx8mp_gpu_ahb_sels, ccm_base + 0x8c80);
 	hws[IMX8MP_CLK_NOC] = imx8m_clk_hw_composite_critical("noc", imx8mp_noc_sels, ccm_base + 0x8d00);
 	hws[IMX8MP_CLK_NOC_IO] = imx8m_clk_hw_composite_critical("noc_io", imx8mp_noc_io_sels, ccm_base + 0x8d80);
-	hws[IMX8MP_CLK_ML_AXI] = imx8m_clk_hw_composite("ml_axi", imx8mp_ml_axi_sels, ccm_base + 0x8e00);
-	hws[IMX8MP_CLK_ML_AHB] = imx8m_clk_hw_composite("ml_ahb", imx8mp_ml_ahb_sels, ccm_base + 0x8e80);
+	hws[IMX8MP_CLK_ML_AXI] = imx8m_clk_hw_composite_bus("ml_axi", imx8mp_ml_axi_sels, ccm_base + 0x8e00);
+	hws[IMX8MP_CLK_ML_AHB] = imx8m_clk_hw_composite_bus("ml_ahb", imx8mp_ml_ahb_sels, ccm_base + 0x8e80);
 
 	hws[IMX8MP_CLK_AHB] = imx8m_clk_hw_composite_critical("ahb_root", imx8mp_ahb_sels, ccm_base + 0x9000);
-	hws[IMX8MP_CLK_AUDIO_AHB] = imx8m_clk_hw_composite("audio_ahb", imx8mp_audio_ahb_sels, ccm_base + 0x9100);
-	hws[IMX8MP_CLK_MIPI_DSI_ESC_RX] = imx8m_clk_hw_composite("mipi_dsi_esc_rx", imx8mp_mipi_dsi_esc_rx_sels, ccm_base + 0x9200);
+	hws[IMX8MP_CLK_AUDIO_AHB] = imx8m_clk_hw_composite_bus("audio_ahb", imx8mp_audio_ahb_sels, ccm_base + 0x9100);
+	hws[IMX8MP_CLK_MIPI_DSI_ESC_RX] = imx8m_clk_hw_composite_bus("mipi_dsi_esc_rx", imx8mp_mipi_dsi_esc_rx_sels, ccm_base + 0x9200);
 
 	hws[IMX8MP_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb_root", ccm_base + 0x9080, 0, 1);
 	hws[IMX8MP_CLK_IPG_AUDIO_ROOT] = imx_clk_hw_divider2("ipg_audio_root", "audio_ahb", ccm_base + 0x9180, 0, 1);
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 91309ff65441..a64aace213c2 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -432,22 +432,22 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
 
 	/* BUS */
 	hws[IMX8MQ_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi", imx8mq_main_axi_sels, base + 0x8800);
-	hws[IMX8MQ_CLK_ENET_AXI] = imx8m_clk_hw_composite("enet_axi", imx8mq_enet_axi_sels, base + 0x8880);
-	hws[IMX8MQ_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite("nand_usdhc_bus", imx8mq_nand_usdhc_sels, base + 0x8900);
-	hws[IMX8MQ_CLK_VPU_BUS] = imx8m_clk_hw_composite("vpu_bus", imx8mq_vpu_bus_sels, base + 0x8980);
-	hws[IMX8MQ_CLK_DISP_AXI] = imx8m_clk_hw_composite("disp_axi", imx8mq_disp_axi_sels, base + 0x8a00);
-	hws[IMX8MQ_CLK_DISP_APB] = imx8m_clk_hw_composite("disp_apb", imx8mq_disp_apb_sels, base + 0x8a80);
-	hws[IMX8MQ_CLK_DISP_RTRM] = imx8m_clk_hw_composite("disp_rtrm", imx8mq_disp_rtrm_sels, base + 0x8b00);
-	hws[IMX8MQ_CLK_USB_BUS] = imx8m_clk_hw_composite("usb_bus", imx8mq_usb_bus_sels, base + 0x8b80);
-	hws[IMX8MQ_CLK_GPU_AXI] = imx8m_clk_hw_composite("gpu_axi", imx8mq_gpu_axi_sels, base + 0x8c00);
-	hws[IMX8MQ_CLK_GPU_AHB] = imx8m_clk_hw_composite("gpu_ahb", imx8mq_gpu_ahb_sels, base + 0x8c80);
+	hws[IMX8MQ_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi", imx8mq_enet_axi_sels, base + 0x8880);
+	hws[IMX8MQ_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_bus("nand_usdhc_bus", imx8mq_nand_usdhc_sels, base + 0x8900);
+	hws[IMX8MQ_CLK_VPU_BUS] = imx8m_clk_hw_composite_bus("vpu_bus", imx8mq_vpu_bus_sels, base + 0x8980);
+	hws[IMX8MQ_CLK_DISP_AXI] = imx8m_clk_hw_composite_bus("disp_axi", imx8mq_disp_axi_sels, base + 0x8a00);
+	hws[IMX8MQ_CLK_DISP_APB] = imx8m_clk_hw_composite_bus("disp_apb", imx8mq_disp_apb_sels, base + 0x8a80);
+	hws[IMX8MQ_CLK_DISP_RTRM] = imx8m_clk_hw_composite_bus("disp_rtrm", imx8mq_disp_rtrm_sels, base + 0x8b00);
+	hws[IMX8MQ_CLK_USB_BUS] = imx8m_clk_hw_composite_bus("usb_bus", imx8mq_usb_bus_sels, base + 0x8b80);
+	hws[IMX8MQ_CLK_GPU_AXI] = imx8m_clk_hw_composite_bus("gpu_axi", imx8mq_gpu_axi_sels, base + 0x8c00);
+	hws[IMX8MQ_CLK_GPU_AHB] = imx8m_clk_hw_composite_bus("gpu_ahb", imx8mq_gpu_ahb_sels, base + 0x8c80);
 	hws[IMX8MQ_CLK_NOC] = imx8m_clk_hw_composite_critical("noc", imx8mq_noc_sels, base + 0x8d00);
 	hws[IMX8MQ_CLK_NOC_APB] = imx8m_clk_hw_composite_critical("noc_apb", imx8mq_noc_apb_sels, base + 0x8d80);
 
 	/* AHB */
 	/* AHB clock is used by the AHB bus therefore marked as critical */
 	hws[IMX8MQ_CLK_AHB] = imx8m_clk_hw_composite_critical("ahb", imx8mq_ahb_sels, base + 0x9000);
-	hws[IMX8MQ_CLK_AUDIO_AHB] = imx8m_clk_hw_composite("audio_ahb", imx8mq_audio_ahb_sels, base + 0x9100);
+	hws[IMX8MQ_CLK_AUDIO_AHB] = imx8m_clk_hw_composite_bus("audio_ahb", imx8mq_audio_ahb_sels, base + 0x9100);
 
 	/* IPG */
 	hws[IMX8MQ_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb", base + 0x9080, 0, 1);
-- 
2.16.4


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[PATCH V2 10/10] clk: imx8mp: mark memrepair clock as critical

[peng.fan]

From: Peng Fan <peng.fan@nxp.com>

If memrepair root clock in CCM is disabled, the memory repair logic
in HDMIMIX can’t work. So let's mark it as critical clock.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx8mp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index b4d9db9d5bf1..a7c59d7a40de 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -590,7 +590,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MP_CLK_VPU_G2] = imx8m_clk_hw_composite("vpu_g2", imx8mp_vpu_g2_sels, ccm_base + 0xa180);
 	hws[IMX8MP_CLK_CAN1] = imx8m_clk_hw_composite("can1", imx8mp_can1_sels, ccm_base + 0xa200);
 	hws[IMX8MP_CLK_CAN2] = imx8m_clk_hw_composite("can2", imx8mp_can2_sels, ccm_base + 0xa280);
-	hws[IMX8MP_CLK_MEMREPAIR] = imx8m_clk_hw_composite("memrepair", imx8mp_memrepair_sels, ccm_base + 0xa300);
+	hws[IMX8MP_CLK_MEMREPAIR] = imx8m_clk_hw_composite_critical("memrepair", imx8mp_memrepair_sels, ccm_base + 0xa300);
 	hws[IMX8MP_CLK_PCIE_PHY] = imx8m_clk_hw_composite("pcie_phy", imx8mp_pcie_phy_sels, ccm_base + 0xa380);
 	hws[IMX8MP_CLK_PCIE_AUX] = imx8m_clk_hw_composite("pcie_aux", imx8mp_pcie_aux_sels, ccm_base + 0xa400);
 	hws[IMX8MP_CLK_I2C5] = imx8m_clk_hw_composite("i2c5", imx8mp_i2c5_sels, ccm_base + 0xa480);
-- 
2.16.4

[PATCH V2 10/10] clk: imx8mp: mark memrepair clock as critical

[peng.fan]

From: Peng Fan <peng.fan@nxp.com>

If memrepair root clock in CCM is disabled, the memory repair logic
in HDMIMIX can’t work. So let's mark it as critical clock.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx8mp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index b4d9db9d5bf1..a7c59d7a40de 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -590,7 +590,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MP_CLK_VPU_G2] = imx8m_clk_hw_composite("vpu_g2", imx8mp_vpu_g2_sels, ccm_base + 0xa180);
 	hws[IMX8MP_CLK_CAN1] = imx8m_clk_hw_composite("can1", imx8mp_can1_sels, ccm_base + 0xa200);
 	hws[IMX8MP_CLK_CAN2] = imx8m_clk_hw_composite("can2", imx8mp_can2_sels, ccm_base + 0xa280);
-	hws[IMX8MP_CLK_MEMREPAIR] = imx8m_clk_hw_composite("memrepair", imx8mp_memrepair_sels, ccm_base + 0xa300);
+	hws[IMX8MP_CLK_MEMREPAIR] = imx8m_clk_hw_composite_critical("memrepair", imx8mp_memrepair_sels, ccm_base + 0xa300);
 	hws[IMX8MP_CLK_PCIE_PHY] = imx8m_clk_hw_composite("pcie_phy", imx8mp_pcie_phy_sels, ccm_base + 0xa380);
 	hws[IMX8MP_CLK_PCIE_AUX] = imx8m_clk_hw_composite("pcie_aux", imx8mp_pcie_aux_sels, ccm_base + 0xa400);
 	hws[IMX8MP_CLK_I2C5] = imx8m_clk_hw_composite("i2c5", imx8mp_i2c5_sels, ccm_base + 0xa480);
-- 
2.16.4


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RE: [PATCH V2 00/10] clk: imx: fixes and improve for i.MX8M

[Peng Fan]

Hi Shawn,

> Subject: [PATCH V2 00/10] clk: imx: fixes and improve for i.MX8M

Is it possible for you to take this patchset for 5.7?

Currently the i.MX8M cpu clock has some dependency on U-Boot settings,
When uboot has different settings, the kernel will hang.
With this patchset, it will not, at least I tested on i.MX8MM-EVK with your
lastest for-next branch.

Thanks,
Peng.

> 
> From: Peng Fan <peng.fan@nxp.com>
> 
> Patches based on for-next
> 
> V2:
>  Patch 7, drop wait after write, add one line comment for write twice
> 
> V1:
> Patch 1,2 is to fix the lockdep warning reported by Leonard Patch 3 is to fix pll
> mux bit Patch 4 is align with other i.MX8M using gate Patch 5 is to simplify
> i.MX8MP clk root using composite
> 
> Patch 3~5 is actually https://patchwork.kernel.org/patch/11402761/
> with a minimal change to patch 5 here.
> 
> Patch 6 is to use composite core clk for A53 clk root Patch 7,8,9 is actually to
> fix CORE/BUS clk slice issue.
>  This issue is triggerred after we update U-Boot to include  the A53 clk fixes
> to sources from PLL, not from A53 root clk,  because of the signoff timing is
> 1GHz. U-Boot set the A53 root  mux to 2, sys pll2 500MHz. Kernel will set
> the A53 root mux to  4, sys pll1 800MHz, then gate off sys pll2 500MHz. Then
> kernel  will gate off A53 root because clk_ignore_unsed, A53 directly sources
> PLL, so it is ok to gate off A53 root. However when gate off A53  root clk,
> system hang, because the original mux sys pll2 500MHz  gated off with
> CLK_OPS_PARENT_ENABLE flag.
> 
>  It is lucky that we not met issue for other core/bus clk slice  except A53
> ROOT core slice. But it is always triggerred after  U-Boot and Linux both
> switch to use ARM PLL for A53 core, but  have different mux settings for A53
> root clk slice.
> 
>  So the three patches is to address this issue.
> 
> Patch 10 is make memrepair as critical.
> 
> Peng Fan (10):
>   arm64: dts: imx8m: assign clocks for A53
>   clk: imx8m: drop clk_hw_set_parent for A53
>   clk: imx: imx8mp: fix pll mux bit
>   clk: imx8mp: Define gates for pll1/2 fixed dividers
>   clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code
>   clk: imx8m: migrate A53 clk root to use composite core
>   clk: imx: add mux ops for i.MX8M composite clk
>   clk: imx: add imx8m_clk_hw_composite_bus
>   clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice
>   clk: imx8mp: mark memrepair clock as critical
> 
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi |  10 +-
> arch/arm64/boot/dts/freescale/imx8mn.dtsi |  10 +-
> arch/arm64/boot/dts/freescale/imx8mp.dtsi |  11 ++-
>  arch/arm64/boot/dts/freescale/imx8mq.dtsi |   9 +-
>  drivers/clk/imx/clk-composite-8m.c        |  67 ++++++++++++-
>  drivers/clk/imx/clk-imx8mm.c              |  27 +++---
>  drivers/clk/imx/clk-imx8mn.c              |  25 +++--
>  drivers/clk/imx/clk-imx8mp.c              | 150
> +++++++++++++++---------------
>  drivers/clk/imx/clk-imx8mq.c              |  29 +++---
>  drivers/clk/imx/clk.h                     |   7 ++
>  include/dt-bindings/clock/imx8mp-clock.h  |  28 +++++-
>  11 files changed, 240 insertions(+), 133 deletions(-)
> 
> --
> 2.16.4

RE: [PATCH V2 00/10] clk: imx: fixes and improve for i.MX8M

[Peng Fan]

Hi Shawn,

> Subject: [PATCH V2 00/10] clk: imx: fixes and improve for i.MX8M

Is it possible for you to take this patchset for 5.7?

Currently the i.MX8M cpu clock has some dependency on U-Boot settings,
When uboot has different settings, the kernel will hang.
With this patchset, it will not, at least I tested on i.MX8MM-EVK with your
lastest for-next branch.

Thanks,
Peng.

> 
> From: Peng Fan <peng.fan@nxp.com>
> 
> Patches based on for-next
> 
> V2:
>  Patch 7, drop wait after write, add one line comment for write twice
> 
> V1:
> Patch 1,2 is to fix the lockdep warning reported by Leonard Patch 3 is to fix pll
> mux bit Patch 4 is align with other i.MX8M using gate Patch 5 is to simplify
> i.MX8MP clk root using composite
> 
> Patch 3~5 is actually https://patchwork.kernel.org/patch/11402761/
> with a minimal change to patch 5 here.
> 
> Patch 6 is to use composite core clk for A53 clk root Patch 7,8,9 is actually to
> fix CORE/BUS clk slice issue.
>  This issue is triggerred after we update U-Boot to include  the A53 clk fixes
> to sources from PLL, not from A53 root clk,  because of the signoff timing is
> 1GHz. U-Boot set the A53 root  mux to 2, sys pll2 500MHz. Kernel will set
> the A53 root mux to  4, sys pll1 800MHz, then gate off sys pll2 500MHz. Then
> kernel  will gate off A53 root because clk_ignore_unsed, A53 directly sources
> PLL, so it is ok to gate off A53 root. However when gate off A53  root clk,
> system hang, because the original mux sys pll2 500MHz  gated off with
> CLK_OPS_PARENT_ENABLE flag.
> 
>  It is lucky that we not met issue for other core/bus clk slice  except A53
> ROOT core slice. But it is always triggerred after  U-Boot and Linux both
> switch to use ARM PLL for A53 core, but  have different mux settings for A53
> root clk slice.
> 
>  So the three patches is to address this issue.
> 
> Patch 10 is make memrepair as critical.
> 
> Peng Fan (10):
>   arm64: dts: imx8m: assign clocks for A53
>   clk: imx8m: drop clk_hw_set_parent for A53
>   clk: imx: imx8mp: fix pll mux bit
>   clk: imx8mp: Define gates for pll1/2 fixed dividers
>   clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code
>   clk: imx8m: migrate A53 clk root to use composite core
>   clk: imx: add mux ops for i.MX8M composite clk
>   clk: imx: add imx8m_clk_hw_composite_bus
>   clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice
>   clk: imx8mp: mark memrepair clock as critical
> 
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi |  10 +-
> arch/arm64/boot/dts/freescale/imx8mn.dtsi |  10 +-
> arch/arm64/boot/dts/freescale/imx8mp.dtsi |  11 ++-
>  arch/arm64/boot/dts/freescale/imx8mq.dtsi |   9 +-
>  drivers/clk/imx/clk-composite-8m.c        |  67 ++++++++++++-
>  drivers/clk/imx/clk-imx8mm.c              |  27 +++---
>  drivers/clk/imx/clk-imx8mn.c              |  25 +++--
>  drivers/clk/imx/clk-imx8mp.c              | 150
> +++++++++++++++---------------
>  drivers/clk/imx/clk-imx8mq.c              |  29 +++---
>  drivers/clk/imx/clk.h                     |   7 ++
>  include/dt-bindings/clock/imx8mp-clock.h  |  28 +++++-
>  11 files changed, 240 insertions(+), 133 deletions(-)
> 
> --
> 2.16.4

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RE: [PATCH V2 00/10] clk: imx: fixes and improve for i.MX8M

[Peng Fan]

> Subject: [PATCH V2 00/10] clk: imx: fixes and improve for i.MX8M

Ping...

Thanks,
Peng.

> 
> From: Peng Fan <peng.fan@nxp.com>
> 
> Patches based on for-next
> 
> V2:
>  Patch 7, drop wait after write, add one line comment for write twice
> 
> V1:
> Patch 1,2 is to fix the lockdep warning reported by Leonard Patch 3 is to fix pll
> mux bit Patch 4 is align with other i.MX8M using gate Patch 5 is to simplify
> i.MX8MP clk root using composite
> 
> Patch 3~5 is actually https://patchwork.kernel.org/patch/11402761/
> with a minimal change to patch 5 here.
> 
> Patch 6 is to use composite core clk for A53 clk root Patch 7,8,9 is actually to
> fix CORE/BUS clk slice issue.
>  This issue is triggerred after we update U-Boot to include  the A53 clk fixes
> to sources from PLL, not from A53 root clk,  because of the signoff timing is
> 1GHz. U-Boot set the A53 root  mux to 2, sys pll2 500MHz. Kernel will set
> the A53 root mux to  4, sys pll1 800MHz, then gate off sys pll2 500MHz. Then
> kernel  will gate off A53 root because clk_ignore_unsed, A53 directly sources
> PLL, so it is ok to gate off A53 root. However when gate off A53  root clk,
> system hang, because the original mux sys pll2 500MHz  gated off with
> CLK_OPS_PARENT_ENABLE flag.
> 
>  It is lucky that we not met issue for other core/bus clk slice  except A53
> ROOT core slice. But it is always triggerred after  U-Boot and Linux both
> switch to use ARM PLL for A53 core, but  have different mux settings for A53
> root clk slice.
> 
>  So the three patches is to address this issue.
> 
> Patch 10 is make memrepair as critical.
> 
> Peng Fan (10):
>   arm64: dts: imx8m: assign clocks for A53
>   clk: imx8m: drop clk_hw_set_parent for A53
>   clk: imx: imx8mp: fix pll mux bit
>   clk: imx8mp: Define gates for pll1/2 fixed dividers
>   clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code
>   clk: imx8m: migrate A53 clk root to use composite core
>   clk: imx: add mux ops for i.MX8M composite clk
>   clk: imx: add imx8m_clk_hw_composite_bus
>   clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice
>   clk: imx8mp: mark memrepair clock as critical
> 
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi |  10 +-
> arch/arm64/boot/dts/freescale/imx8mn.dtsi |  10 +-
> arch/arm64/boot/dts/freescale/imx8mp.dtsi |  11 ++-
>  arch/arm64/boot/dts/freescale/imx8mq.dtsi |   9 +-
>  drivers/clk/imx/clk-composite-8m.c        |  67 ++++++++++++-
>  drivers/clk/imx/clk-imx8mm.c              |  27 +++---
>  drivers/clk/imx/clk-imx8mn.c              |  25 +++--
>  drivers/clk/imx/clk-imx8mp.c              | 150
> +++++++++++++++---------------
>  drivers/clk/imx/clk-imx8mq.c              |  29 +++---
>  drivers/clk/imx/clk.h                     |   7 ++
>  include/dt-bindings/clock/imx8mp-clock.h  |  28 +++++-
>  11 files changed, 240 insertions(+), 133 deletions(-)
> 
> --
> 2.16.4

RE: [PATCH V2 00/10] clk: imx: fixes and improve for i.MX8M

[Peng Fan]

> Subject: [PATCH V2 00/10] clk: imx: fixes and improve for i.MX8M

Ping...

Thanks,
Peng.

> 
> From: Peng Fan <peng.fan@nxp.com>
> 
> Patches based on for-next
> 
> V2:
>  Patch 7, drop wait after write, add one line comment for write twice
> 
> V1:
> Patch 1,2 is to fix the lockdep warning reported by Leonard Patch 3 is to fix pll
> mux bit Patch 4 is align with other i.MX8M using gate Patch 5 is to simplify
> i.MX8MP clk root using composite
> 
> Patch 3~5 is actually https://patchwork.kernel.org/patch/11402761/
> with a minimal change to patch 5 here.
> 
> Patch 6 is to use composite core clk for A53 clk root Patch 7,8,9 is actually to
> fix CORE/BUS clk slice issue.
>  This issue is triggerred after we update U-Boot to include  the A53 clk fixes
> to sources from PLL, not from A53 root clk,  because of the signoff timing is
> 1GHz. U-Boot set the A53 root  mux to 2, sys pll2 500MHz. Kernel will set
> the A53 root mux to  4, sys pll1 800MHz, then gate off sys pll2 500MHz. Then
> kernel  will gate off A53 root because clk_ignore_unsed, A53 directly sources
> PLL, so it is ok to gate off A53 root. However when gate off A53  root clk,
> system hang, because the original mux sys pll2 500MHz  gated off with
> CLK_OPS_PARENT_ENABLE flag.
> 
>  It is lucky that we not met issue for other core/bus clk slice  except A53
> ROOT core slice. But it is always triggerred after  U-Boot and Linux both
> switch to use ARM PLL for A53 core, but  have different mux settings for A53
> root clk slice.
> 
>  So the three patches is to address this issue.
> 
> Patch 10 is make memrepair as critical.
> 
> Peng Fan (10):
>   arm64: dts: imx8m: assign clocks for A53
>   clk: imx8m: drop clk_hw_set_parent for A53
>   clk: imx: imx8mp: fix pll mux bit
>   clk: imx8mp: Define gates for pll1/2 fixed dividers
>   clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code
>   clk: imx8m: migrate A53 clk root to use composite core
>   clk: imx: add mux ops for i.MX8M composite clk
>   clk: imx: add imx8m_clk_hw_composite_bus
>   clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice
>   clk: imx8mp: mark memrepair clock as critical
> 
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi |  10 +-
> arch/arm64/boot/dts/freescale/imx8mn.dtsi |  10 +-
> arch/arm64/boot/dts/freescale/imx8mp.dtsi |  11 ++-
>  arch/arm64/boot/dts/freescale/imx8mq.dtsi |   9 +-
>  drivers/clk/imx/clk-composite-8m.c        |  67 ++++++++++++-
>  drivers/clk/imx/clk-imx8mm.c              |  27 +++---
>  drivers/clk/imx/clk-imx8mn.c              |  25 +++--
>  drivers/clk/imx/clk-imx8mp.c              | 150
> +++++++++++++++---------------
>  drivers/clk/imx/clk-imx8mq.c              |  29 +++---
>  drivers/clk/imx/clk.h                     |   7 ++
>  include/dt-bindings/clock/imx8mp-clock.h  |  28 +++++-
>  11 files changed, 240 insertions(+), 133 deletions(-)
> 
> --
> 2.16.4

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Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk

[Leonard Crestez]

On 2020-03-12 12:27 PM, Peng Fan wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> The CORE/BUS root slice has following design, simplied graph:
> The difference is core not have pre_div block.
> A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7].
> 
>              SEL_A  GA
>              +--+  +-+
>              |  +->+ +------+
> CLK[0-7]--->+  |  +-+      |
>         |    |  |      +----v---+    +----+
>         |    +--+      |pre_diva+---->    |  +---------+
>         |              +--------+    |mux +--+post_div |
>         |    +--+      |pre_divb+--->+    |  +---------+
>         |    |  |      +----^---+    +----+
>         +--->+  |  +-+      |
>              |  +->+ +------+
>              +--+  +-+
>              SEL_B  GB
> 
> There will be system hang, when doing the following steps:
> 1. switch mux from clk0 to clk1
> 2. gate off clk0
> 3. swtich from clk1 to clk2, or gate off clk1
> 
> Step 3 triggers system hang.
> 
> If we skip step2, keep clk0 on, step 3 will not trigger system hang.
> However we have CLK_OPS_PARENT_ENABLE flag, which will unprepare disable
> the clk0 which will not be used.

As far as I understand when switching from clk1 to clk2 this is done by 
temporarily switching the rightmost SELECT mux to whatever was in the 
spare SEL, which is essentially arbitrary from linux POV.

This is quite unexpected but in theory it might be desirable to use a 
third parent as a fallback.

> 
> To address this issue, we could use following simplied software flow:
> After the first target register set
> wait the target register set finished
> set the target register set again
> wait the target register set finished
> 
> The upper flow will make sure SEL_A and SEL_B both set the new mux,
> but with only one path gate on.
> And there will be no system hang anymore with step3.

Your fix tries to work around this scenario by always setting the mux 
value in SEL_A and SEL_B to the same value after each set_parent operation.

But what if SEL_A and SEL_B are different at linux boot time and the 
first reparenting is done *after* disabling unused clocks? This doesn't 
happen for A53 because it's reparented during clock provider probe but 
maybe this scenario could be contrived if bootloader touches one of the 
other bus slices.

It might be extra safe to assign the parent of the spare mux at the 
start of each set_parent call. This could even be done on probe and this 
way wouldn't have to duplicate mux_ops just to do a double write.

> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> 
> V2:
>   Drop wait after write, add one line comment for write twice.
> 
>   drivers/clk/imx/clk-composite-8m.c | 62 +++++++++++++++++++++++++++++++++++++-
>   1 file changed, 61 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
> index 99773519b5a5..eae02c151ced 100644
> --- a/drivers/clk/imx/clk-composite-8m.c
> +++ b/drivers/clk/imx/clk-composite-8m.c
> @@ -24,6 +24,12 @@
>   
>   #define PCG_CGC_SHIFT		28
>   
> +#define PRE_REG_OFF		0x30
> +#define PRE_MUXA_SHIFT		24
> +#define PRE_MUXA_MASK		0x7
> +#define PRE_MUXB_SHIFT		8
> +#define PRE_MUXB_MASK		0x7

These are unused.

> +
>   static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk_hw *hw,
>   						unsigned long parent_rate)
>   {
> @@ -124,6 +130,57 @@ static const struct clk_ops imx8m_clk_composite_divider_ops = {
>   	.set_rate = imx8m_clk_composite_divider_set_rate,
>   };
>   
> +static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw)
> +{
> +	struct clk_mux *mux = to_clk_mux(hw);
> +	u32 val;
> +
> +	val = readl(mux->reg) >> mux->shift;
> +	val &= mux->mask;
> +
> +	return clk_mux_val_to_index(hw, mux->table, mux->flags, val);
> +}
> +
> +static int imx8m_clk_composite_mux_set_parent(struct clk_hw *hw, u8 index)
> +{
> +	struct clk_mux *mux = to_clk_mux(hw);
> +	u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
> +	unsigned long flags = 0;
> +	u32 reg;
> +
> +	if (mux->lock)
> +		spin_lock_irqsave(mux->lock, flags);
> +
> +	reg = readl(mux->reg);
> +	reg &= ~(mux->mask << mux->shift);
> +	val = val << mux->shift;
> +	reg |= val;
> +	/* write twice to make sure SEL_A/B point the same mux */
> +	writel(reg, mux->reg);
> +	writel(reg, mux->reg);
> +
> +	if (mux->lock)
> +		spin_unlock_irqrestore(mux->lock, flags);
> +
> +	return 0;
> +}
> +
> +static int
> +imx8m_clk_composite_mux_determine_rate(struct clk_hw *hw,
> +				       struct clk_rate_request *req)
> +{
> +	struct clk_mux *mux = to_clk_mux(hw);
> +
> +	return clk_mux_determine_rate_flags(hw, req, mux->flags);
> +}
> +
> +
> +const struct clk_ops imx8m_clk_composite_mux_ops = {
> +	.get_parent = imx8m_clk_composite_mux_get_parent,
> +	.set_parent = imx8m_clk_composite_mux_set_parent,
> +	.determine_rate = imx8m_clk_composite_mux_determine_rate,
> +};
> +
>   struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
>   					const char * const *parent_names,
>   					int num_parents, void __iomem *reg,
> @@ -136,6 +193,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
>   	struct clk_gate *gate = NULL;
>   	struct clk_mux *mux = NULL;
>   	const struct clk_ops *divider_ops;
> +	const struct clk_ops *mux_ops;
>   
>   	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
>   	if (!mux)
> @@ -157,10 +215,12 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
>   		div->shift = PCG_DIV_SHIFT;
>   		div->width = PCG_CORE_DIV_WIDTH;
>   		divider_ops = &clk_divider_ops;
> +		mux_ops = &imx8m_clk_composite_mux_ops;
>   	} else {
>   		div->shift = PCG_PREDIV_SHIFT;
>   		div->width = PCG_PREDIV_WIDTH;
>   		divider_ops = &imx8m_clk_composite_divider_ops;
> +		mux_ops = &clk_mux_ops;
>   	}
>   
>   	div->lock = &imx_ccm_lock;
> @@ -176,7 +236,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
>   	gate->lock = &imx_ccm_lock;
>   
>   	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
> -			mux_hw, &clk_mux_ops, div_hw,
> +			mux_hw, mux_ops, div_hw,
>   			divider_ops, gate_hw, &clk_gate_ops, flags);
>   	if (IS_ERR(hw))
>   		goto fail;
> 

Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk

[Leonard Crestez]

On 2020-03-12 12:27 PM, Peng Fan wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> The CORE/BUS root slice has following design, simplied graph:
> The difference is core not have pre_div block.
> A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7].
> 
>              SEL_A  GA
>              +--+  +-+
>              |  +->+ +------+
> CLK[0-7]--->+  |  +-+      |
>         |    |  |      +----v---+    +----+
>         |    +--+      |pre_diva+---->    |  +---------+
>         |              +--------+    |mux +--+post_div |
>         |    +--+      |pre_divb+--->+    |  +---------+
>         |    |  |      +----^---+    +----+
>         +--->+  |  +-+      |
>              |  +->+ +------+
>              +--+  +-+
>              SEL_B  GB
> 
> There will be system hang, when doing the following steps:
> 1. switch mux from clk0 to clk1
> 2. gate off clk0
> 3. swtich from clk1 to clk2, or gate off clk1
> 
> Step 3 triggers system hang.
> 
> If we skip step2, keep clk0 on, step 3 will not trigger system hang.
> However we have CLK_OPS_PARENT_ENABLE flag, which will unprepare disable
> the clk0 which will not be used.

As far as I understand when switching from clk1 to clk2 this is done by 
temporarily switching the rightmost SELECT mux to whatever was in the 
spare SEL, which is essentially arbitrary from linux POV.

This is quite unexpected but in theory it might be desirable to use a 
third parent as a fallback.

> 
> To address this issue, we could use following simplied software flow:
> After the first target register set
> wait the target register set finished
> set the target register set again
> wait the target register set finished
> 
> The upper flow will make sure SEL_A and SEL_B both set the new mux,
> but with only one path gate on.
> And there will be no system hang anymore with step3.

Your fix tries to work around this scenario by always setting the mux 
value in SEL_A and SEL_B to the same value after each set_parent operation.

But what if SEL_A and SEL_B are different at linux boot time and the 
first reparenting is done *after* disabling unused clocks? This doesn't 
happen for A53 because it's reparented during clock provider probe but 
maybe this scenario could be contrived if bootloader touches one of the 
other bus slices.

It might be extra safe to assign the parent of the spare mux at the 
start of each set_parent call. This could even be done on probe and this 
way wouldn't have to duplicate mux_ops just to do a double write.

> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> 
> V2:
>   Drop wait after write, add one line comment for write twice.
> 
>   drivers/clk/imx/clk-composite-8m.c | 62 +++++++++++++++++++++++++++++++++++++-
>   1 file changed, 61 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
> index 99773519b5a5..eae02c151ced 100644
> --- a/drivers/clk/imx/clk-composite-8m.c
> +++ b/drivers/clk/imx/clk-composite-8m.c
> @@ -24,6 +24,12 @@
>   
>   #define PCG_CGC_SHIFT		28
>   
> +#define PRE_REG_OFF		0x30
> +#define PRE_MUXA_SHIFT		24
> +#define PRE_MUXA_MASK		0x7
> +#define PRE_MUXB_SHIFT		8
> +#define PRE_MUXB_MASK		0x7

These are unused.

> +
>   static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk_hw *hw,
>   						unsigned long parent_rate)
>   {
> @@ -124,6 +130,57 @@ static const struct clk_ops imx8m_clk_composite_divider_ops = {
>   	.set_rate = imx8m_clk_composite_divider_set_rate,
>   };
>   
> +static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw)
> +{
> +	struct clk_mux *mux = to_clk_mux(hw);
> +	u32 val;
> +
> +	val = readl(mux->reg) >> mux->shift;
> +	val &= mux->mask;
> +
> +	return clk_mux_val_to_index(hw, mux->table, mux->flags, val);
> +}
> +
> +static int imx8m_clk_composite_mux_set_parent(struct clk_hw *hw, u8 index)
> +{
> +	struct clk_mux *mux = to_clk_mux(hw);
> +	u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
> +	unsigned long flags = 0;
> +	u32 reg;
> +
> +	if (mux->lock)
> +		spin_lock_irqsave(mux->lock, flags);
> +
> +	reg = readl(mux->reg);
> +	reg &= ~(mux->mask << mux->shift);
> +	val = val << mux->shift;
> +	reg |= val;
> +	/* write twice to make sure SEL_A/B point the same mux */
> +	writel(reg, mux->reg);
> +	writel(reg, mux->reg);
> +
> +	if (mux->lock)
> +		spin_unlock_irqrestore(mux->lock, flags);
> +
> +	return 0;
> +}
> +
> +static int
> +imx8m_clk_composite_mux_determine_rate(struct clk_hw *hw,
> +				       struct clk_rate_request *req)
> +{
> +	struct clk_mux *mux = to_clk_mux(hw);
> +
> +	return clk_mux_determine_rate_flags(hw, req, mux->flags);
> +}
> +
> +
> +const struct clk_ops imx8m_clk_composite_mux_ops = {
> +	.get_parent = imx8m_clk_composite_mux_get_parent,
> +	.set_parent = imx8m_clk_composite_mux_set_parent,
> +	.determine_rate = imx8m_clk_composite_mux_determine_rate,
> +};
> +
>   struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
>   					const char * const *parent_names,
>   					int num_parents, void __iomem *reg,
> @@ -136,6 +193,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
>   	struct clk_gate *gate = NULL;
>   	struct clk_mux *mux = NULL;
>   	const struct clk_ops *divider_ops;
> +	const struct clk_ops *mux_ops;
>   
>   	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
>   	if (!mux)
> @@ -157,10 +215,12 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
>   		div->shift = PCG_DIV_SHIFT;
>   		div->width = PCG_CORE_DIV_WIDTH;
>   		divider_ops = &clk_divider_ops;
> +		mux_ops = &imx8m_clk_composite_mux_ops;
>   	} else {
>   		div->shift = PCG_PREDIV_SHIFT;
>   		div->width = PCG_PREDIV_WIDTH;
>   		divider_ops = &imx8m_clk_composite_divider_ops;
> +		mux_ops = &clk_mux_ops;
>   	}
>   
>   	div->lock = &imx_ccm_lock;
> @@ -176,7 +236,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
>   	gate->lock = &imx_ccm_lock;
>   
>   	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
> -			mux_hw, &clk_mux_ops, div_hw,
> +			mux_hw, mux_ops, div_hw,
>   			divider_ops, gate_hw, &clk_gate_ops, flags);
>   	if (IS_ERR(hw))
>   		goto fail;
> 


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Re: [PATCH V2 00/10] clk: imx: fixes and improve for i.MX8M

[Leonard Crestez]

On 2020-04-18 4:45 PM, Peng Fan wrote:
>> Subject: [PATCH V2 00/10] clk: imx: fixes and improve for i.MX8M
> 
> Ping...
> 
> Thanks,
> Peng.
> 
>>
>> From: Peng Fan <peng.fan@nxp.com>
>>
>> Patches based on for-next
>>
>> V2:
>>   Patch 7, drop wait after write, add one line comment for write twice
>>
>> V1:
>> Patch 1,2 is to fix the lockdep warning reported by Leonard Patch 3 is to fix pll
>> mux bit Patch 4 is align with other i.MX8M using gate Patch 5 is to simplify
>> i.MX8MP clk root using composite
>>
>> Patch 3~5 is actually https://patchwork.kernel.org/patch/11402761/
>> with a minimal change to patch 5 here.
>>
>> Patch 6 is to use composite core clk for A53 clk root Patch 7,8,9 is actually to
>> fix CORE/BUS clk slice issue.
>>   This issue is triggerred after we update U-Boot to include  the A53 clk fixes
>> to sources from PLL, not from A53 root clk,  because of the signoff timing is
>> 1GHz. U-Boot set the A53 root  mux to 2, sys pll2 500MHz. Kernel will set
>> the A53 root mux to  4, sys pll1 800MHz, then gate off sys pll2 500MHz. Then
>> kernel  will gate off A53 root because clk_ignore_unsed, A53 directly sources
>> PLL, so it is ok to gate off A53 root. However when gate off A53  root clk,
>> system hang, because the original mux sys pll2 500MHz  gated off with
>> CLK_OPS_PARENT_ENABLE flag.
>>
>>   It is lucky that we not met issue for other core/bus clk slice  except A53
>> ROOT core slice. But it is always triggerred after  U-Boot and Linux both
>> switch to use ARM PLL for A53 core, but  have different mux settings for A53
>> root clk slice.
>>
>>   So the three patches is to address this issue.
>>
>> Patch 10 is make memrepair as critical.
>>
>> Peng Fan (10):
>>    arm64: dts: imx8m: assign clocks for A53
>>    clk: imx8m: drop clk_hw_set_parent for A53
>>    clk: imx: imx8mp: fix pll mux bit
>>    clk: imx8mp: Define gates for pll1/2 fixed dividers
>>    clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code
>>    clk: imx8m: migrate A53 clk root to use composite core
>>    clk: imx: add mux ops for i.MX8M composite clk
>>    clk: imx: add imx8m_clk_hw_composite_bus
>>    clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice
>>    clk: imx8mp: mark memrepair clock as critical
>>
>>   arch/arm64/boot/dts/freescale/imx8mm.dtsi |  10 +-
>> arch/arm64/boot/dts/freescale/imx8mn.dtsi |  10 +-
>> arch/arm64/boot/dts/freescale/imx8mp.dtsi |  11 ++-
>>   arch/arm64/boot/dts/freescale/imx8mq.dtsi |   9 +-
>>   drivers/clk/imx/clk-composite-8m.c        |  67 ++++++++++++-
>>   drivers/clk/imx/clk-imx8mm.c              |  27 +++---
>>   drivers/clk/imx/clk-imx8mn.c              |  25 +++--
>>   drivers/clk/imx/clk-imx8mp.c              | 150
>> +++++++++++++++---------------
>>   drivers/clk/imx/clk-imx8mq.c              |  29 +++---
>>   drivers/clk/imx/clk.h                     |   7 ++
>>   include/dt-bindings/clock/imx8mp-clock.h  |  28 +++++-
>>   11 files changed, 240 insertions(+), 133 deletions(-)

For 1-6 and 10:

Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>

Re: [PATCH V2 00/10] clk: imx: fixes and improve for i.MX8M

[Leonard Crestez]

On 2020-04-18 4:45 PM, Peng Fan wrote:
>> Subject: [PATCH V2 00/10] clk: imx: fixes and improve for i.MX8M
> 
> Ping...
> 
> Thanks,
> Peng.
> 
>>
>> From: Peng Fan <peng.fan@nxp.com>
>>
>> Patches based on for-next
>>
>> V2:
>>   Patch 7, drop wait after write, add one line comment for write twice
>>
>> V1:
>> Patch 1,2 is to fix the lockdep warning reported by Leonard Patch 3 is to fix pll
>> mux bit Patch 4 is align with other i.MX8M using gate Patch 5 is to simplify
>> i.MX8MP clk root using composite
>>
>> Patch 3~5 is actually https://patchwork.kernel.org/patch/11402761/
>> with a minimal change to patch 5 here.
>>
>> Patch 6 is to use composite core clk for A53 clk root Patch 7,8,9 is actually to
>> fix CORE/BUS clk slice issue.
>>   This issue is triggerred after we update U-Boot to include  the A53 clk fixes
>> to sources from PLL, not from A53 root clk,  because of the signoff timing is
>> 1GHz. U-Boot set the A53 root  mux to 2, sys pll2 500MHz. Kernel will set
>> the A53 root mux to  4, sys pll1 800MHz, then gate off sys pll2 500MHz. Then
>> kernel  will gate off A53 root because clk_ignore_unsed, A53 directly sources
>> PLL, so it is ok to gate off A53 root. However when gate off A53  root clk,
>> system hang, because the original mux sys pll2 500MHz  gated off with
>> CLK_OPS_PARENT_ENABLE flag.
>>
>>   It is lucky that we not met issue for other core/bus clk slice  except A53
>> ROOT core slice. But it is always triggerred after  U-Boot and Linux both
>> switch to use ARM PLL for A53 core, but  have different mux settings for A53
>> root clk slice.
>>
>>   So the three patches is to address this issue.
>>
>> Patch 10 is make memrepair as critical.
>>
>> Peng Fan (10):
>>    arm64: dts: imx8m: assign clocks for A53
>>    clk: imx8m: drop clk_hw_set_parent for A53
>>    clk: imx: imx8mp: fix pll mux bit
>>    clk: imx8mp: Define gates for pll1/2 fixed dividers
>>    clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code
>>    clk: imx8m: migrate A53 clk root to use composite core
>>    clk: imx: add mux ops for i.MX8M composite clk
>>    clk: imx: add imx8m_clk_hw_composite_bus
>>    clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice
>>    clk: imx8mp: mark memrepair clock as critical
>>
>>   arch/arm64/boot/dts/freescale/imx8mm.dtsi |  10 +-
>> arch/arm64/boot/dts/freescale/imx8mn.dtsi |  10 +-
>> arch/arm64/boot/dts/freescale/imx8mp.dtsi |  11 ++-
>>   arch/arm64/boot/dts/freescale/imx8mq.dtsi |   9 +-
>>   drivers/clk/imx/clk-composite-8m.c        |  67 ++++++++++++-
>>   drivers/clk/imx/clk-imx8mm.c              |  27 +++---
>>   drivers/clk/imx/clk-imx8mn.c              |  25 +++--
>>   drivers/clk/imx/clk-imx8mp.c              | 150
>> +++++++++++++++---------------
>>   drivers/clk/imx/clk-imx8mq.c              |  29 +++---
>>   drivers/clk/imx/clk.h                     |   7 ++
>>   include/dt-bindings/clock/imx8mp-clock.h  |  28 +++++-
>>   11 files changed, 240 insertions(+), 133 deletions(-)

For 1-6 and 10:

Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>

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RE: [PATCH V2 01/10] arm64: dts: imx8m: assign clocks for A53

[Aisheng Dong]

> From: Peng Fan <peng.fan@nxp.com>
> Sent: Thursday, March 12, 2020 6:20 PM
> 
> Assign IMX8M*_CLK_A53_SRC's parent to system pll1 and assign
> IMX8M*_CLK_A53_CORE's parent to arm pll out as what is done in
> drivers/clk/imx/clk-imx8m*.c, then we could remove the settings in driver which
> triggers lockdep warning.
> 
> Reported-by: Leonard Crestez <leonard.crestez@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

Regards
Aisheng

> ---
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi | 10 +++++++---
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 10 +++++++---
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 11 ++++++++---
> arch/arm64/boot/dts/freescale/imx8mq.dtsi |  9 +++++++--
>  4 files changed, 29 insertions(+), 11 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 2e5e7c4457db..8d2200224db4 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -471,16 +471,20 @@
>  					 <&clk_ext3>, <&clk_ext4>;
>  				clock-names = "osc_32k", "osc_24m", "clk_ext1",
> "clk_ext2",
>  					      "clk_ext3", "clk_ext4";
> -				assigned-clocks = <&clk IMX8MM_CLK_NOC>,
> +				assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
> +						<&clk IMX8MM_CLK_A53_CORE>,
> +						<&clk IMX8MM_CLK_NOC>,
>  						<&clk IMX8MM_CLK_AUDIO_AHB>,
>  						<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
>  						<&clk IMX8MM_SYS_PLL3>,
>  						<&clk IMX8MM_VIDEO_PLL1>,
>  						<&clk IMX8MM_AUDIO_PLL1>,
>  						<&clk IMX8MM_AUDIO_PLL2>;
> -				assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
> +				assigned-clock-parents = <&clk
> IMX8MM_SYS_PLL1_800M>,
> +							 <&clk IMX8MM_ARM_PLL_OUT>,
> +							 <&clk IMX8MM_SYS_PLL3_OUT>,
>  							 <&clk IMX8MM_SYS_PLL1_800M>;
> -				assigned-clock-rates = <0>,
> +				assigned-clock-rates = <0>, <0>, <0>,
>  							<400000000>,
>  							<400000000>,
>  							<750000000>,
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index ff9c1ea38130..ad88ba3bf28c 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -380,13 +380,17 @@
>  					 <&clk_ext3>, <&clk_ext4>;
>  				clock-names = "osc_32k", "osc_24m", "clk_ext1",
> "clk_ext2",
>  					      "clk_ext3", "clk_ext4";
> -				assigned-clocks = <&clk IMX8MN_CLK_NOC>,
> +				assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
> +						<&clk IMX8MN_CLK_A53_CORE>,
> +						<&clk IMX8MN_CLK_NOC>,
>  						<&clk IMX8MN_CLK_AUDIO_AHB>,
>  						<&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
>  						<&clk IMX8MN_SYS_PLL3>;
> -				assigned-clock-parents = <&clk IMX8MN_SYS_PLL3_OUT>,
> +				assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
> +							 <&clk IMX8MN_ARM_PLL_OUT>,
> +							 <&clk IMX8MN_SYS_PLL3_OUT>,
>  							 <&clk IMX8MN_SYS_PLL1_800M>;
> -				assigned-clock-rates = <0>,
> +				assigned-clock-rates = <0>, <0>, <0>,
>  							<400000000>,
>  							<400000000>,
>  							<600000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index d92199bf6635..3a96082e8717 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -284,7 +284,9 @@
>  					 <&clk_ext3>, <&clk_ext4>;
>  				clock-names = "osc_32k", "osc_24m", "clk_ext1",
> "clk_ext2",
>  					      "clk_ext3", "clk_ext4";
> -				assigned-clocks = <&clk IMX8MP_CLK_NOC>,
> +				assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
> +						  <&clk IMX8MP_CLK_A53_CORE>,
> +						  <&clk IMX8MP_CLK_NOC>,
>  						  <&clk IMX8MP_CLK_NOC_IO>,
>  						  <&clk IMX8MP_CLK_GIC>,
>  						  <&clk IMX8MP_CLK_AUDIO_AHB>,
> @@ -292,12 +294,15 @@
>  						  <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
>  						  <&clk IMX8MP_AUDIO_PLL1>,
>  						  <&clk IMX8MP_AUDIO_PLL2>;
> -				assigned-clock-parents = <&clk
> IMX8MP_SYS_PLL2_1000M>,
> +				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
> +							 <&clk IMX8MP_ARM_PLL_OUT>,
> +							 <&clk IMX8MP_SYS_PLL2_1000M>,
>  							 <&clk IMX8MP_SYS_PLL1_800M>,
>  							 <&clk IMX8MP_SYS_PLL2_500M>,
>  							 <&clk IMX8MP_SYS_PLL1_800M>,
>  							 <&clk IMX8MP_SYS_PLL1_800M>;
> -				assigned-clock-rates = <1000000000>,
> +				assigned-clock-rates = <0>, <0>,
> +						       <1000000000>,
>  						       <800000000>,
>  						       <500000000>,
>  						       <400000000>,
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 9bbdaf2d6e34..1f3ffc8c8a78 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -594,8 +594,13 @@
>  				clock-names = "ckil", "osc_25m", "osc_27m",
>  				              "clk_ext1", "clk_ext2",
>  				              "clk_ext3", "clk_ext4";
> -				assigned-clocks = <&clk IMX8MQ_CLK_NOC>;
> -				assigned-clock-rates = <800000000>;
> +				assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,
> +						  <&clk IMX8MQ_CLK_A53_CORE>,
> +						  <&clk IMX8MQ_CLK_NOC>;
> +				assigned-clock-rates = <0>, <0>,
> +						       <800000000>;
> +				assigned-clock-parents = <&clk
> IMX8MQ_SYS1_PLL_800M>,
> +							 <&clk IMX8MQ_ARM_PLL_OUT>;
>  			};
> 
>  			src: reset-controller@30390000 {
> --
> 2.16.4

RE: [PATCH V2 01/10] arm64: dts: imx8m: assign clocks for A53

[Aisheng Dong]

> From: Peng Fan <peng.fan@nxp.com>
> Sent: Thursday, March 12, 2020 6:20 PM
> 
> Assign IMX8M*_CLK_A53_SRC's parent to system pll1 and assign
> IMX8M*_CLK_A53_CORE's parent to arm pll out as what is done in
> drivers/clk/imx/clk-imx8m*.c, then we could remove the settings in driver which
> triggers lockdep warning.
> 
> Reported-by: Leonard Crestez <leonard.crestez@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

Regards
Aisheng

> ---
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi | 10 +++++++---
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 10 +++++++---
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 11 ++++++++---
> arch/arm64/boot/dts/freescale/imx8mq.dtsi |  9 +++++++--
>  4 files changed, 29 insertions(+), 11 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 2e5e7c4457db..8d2200224db4 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -471,16 +471,20 @@
>  					 <&clk_ext3>, <&clk_ext4>;
>  				clock-names = "osc_32k", "osc_24m", "clk_ext1",
> "clk_ext2",
>  					      "clk_ext3", "clk_ext4";
> -				assigned-clocks = <&clk IMX8MM_CLK_NOC>,
> +				assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
> +						<&clk IMX8MM_CLK_A53_CORE>,
> +						<&clk IMX8MM_CLK_NOC>,
>  						<&clk IMX8MM_CLK_AUDIO_AHB>,
>  						<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
>  						<&clk IMX8MM_SYS_PLL3>,
>  						<&clk IMX8MM_VIDEO_PLL1>,
>  						<&clk IMX8MM_AUDIO_PLL1>,
>  						<&clk IMX8MM_AUDIO_PLL2>;
> -				assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
> +				assigned-clock-parents = <&clk
> IMX8MM_SYS_PLL1_800M>,
> +							 <&clk IMX8MM_ARM_PLL_OUT>,
> +							 <&clk IMX8MM_SYS_PLL3_OUT>,
>  							 <&clk IMX8MM_SYS_PLL1_800M>;
> -				assigned-clock-rates = <0>,
> +				assigned-clock-rates = <0>, <0>, <0>,
>  							<400000000>,
>  							<400000000>,
>  							<750000000>,
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index ff9c1ea38130..ad88ba3bf28c 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -380,13 +380,17 @@
>  					 <&clk_ext3>, <&clk_ext4>;
>  				clock-names = "osc_32k", "osc_24m", "clk_ext1",
> "clk_ext2",
>  					      "clk_ext3", "clk_ext4";
> -				assigned-clocks = <&clk IMX8MN_CLK_NOC>,
> +				assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
> +						<&clk IMX8MN_CLK_A53_CORE>,
> +						<&clk IMX8MN_CLK_NOC>,
>  						<&clk IMX8MN_CLK_AUDIO_AHB>,
>  						<&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
>  						<&clk IMX8MN_SYS_PLL3>;
> -				assigned-clock-parents = <&clk IMX8MN_SYS_PLL3_OUT>,
> +				assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
> +							 <&clk IMX8MN_ARM_PLL_OUT>,
> +							 <&clk IMX8MN_SYS_PLL3_OUT>,
>  							 <&clk IMX8MN_SYS_PLL1_800M>;
> -				assigned-clock-rates = <0>,
> +				assigned-clock-rates = <0>, <0>, <0>,
>  							<400000000>,
>  							<400000000>,
>  							<600000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index d92199bf6635..3a96082e8717 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -284,7 +284,9 @@
>  					 <&clk_ext3>, <&clk_ext4>;
>  				clock-names = "osc_32k", "osc_24m", "clk_ext1",
> "clk_ext2",
>  					      "clk_ext3", "clk_ext4";
> -				assigned-clocks = <&clk IMX8MP_CLK_NOC>,
> +				assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
> +						  <&clk IMX8MP_CLK_A53_CORE>,
> +						  <&clk IMX8MP_CLK_NOC>,
>  						  <&clk IMX8MP_CLK_NOC_IO>,
>  						  <&clk IMX8MP_CLK_GIC>,
>  						  <&clk IMX8MP_CLK_AUDIO_AHB>,
> @@ -292,12 +294,15 @@
>  						  <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
>  						  <&clk IMX8MP_AUDIO_PLL1>,
>  						  <&clk IMX8MP_AUDIO_PLL2>;
> -				assigned-clock-parents = <&clk
> IMX8MP_SYS_PLL2_1000M>,
> +				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
> +							 <&clk IMX8MP_ARM_PLL_OUT>,
> +							 <&clk IMX8MP_SYS_PLL2_1000M>,
>  							 <&clk IMX8MP_SYS_PLL1_800M>,
>  							 <&clk IMX8MP_SYS_PLL2_500M>,
>  							 <&clk IMX8MP_SYS_PLL1_800M>,
>  							 <&clk IMX8MP_SYS_PLL1_800M>;
> -				assigned-clock-rates = <1000000000>,
> +				assigned-clock-rates = <0>, <0>,
> +						       <1000000000>,
>  						       <800000000>,
>  						       <500000000>,
>  						       <400000000>,
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 9bbdaf2d6e34..1f3ffc8c8a78 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -594,8 +594,13 @@
>  				clock-names = "ckil", "osc_25m", "osc_27m",
>  				              "clk_ext1", "clk_ext2",
>  				              "clk_ext3", "clk_ext4";
> -				assigned-clocks = <&clk IMX8MQ_CLK_NOC>;
> -				assigned-clock-rates = <800000000>;
> +				assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,
> +						  <&clk IMX8MQ_CLK_A53_CORE>,
> +						  <&clk IMX8MQ_CLK_NOC>;
> +				assigned-clock-rates = <0>, <0>,
> +						       <800000000>;
> +				assigned-clock-parents = <&clk
> IMX8MQ_SYS1_PLL_800M>,
> +							 <&clk IMX8MQ_ARM_PLL_OUT>;
>  			};
> 
>  			src: reset-controller@30390000 {
> --
> 2.16.4

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RE: [PATCH V2 02/10] clk: imx8m: drop clk_hw_set_parent for A53

[Aisheng Dong]

> From: Peng Fan <peng.fan@nxp.com>
> Sent: Thursday, March 12, 2020 6:20 PM
> 
> The parent settings have been moved to dtsi, we no need to set parent here. And
> clk_hw_set_parent will trigger lockdep warning, because this api not have
> prepare_lock.
> 
> Reported-by: Leonard Crestez <leonard.crestez@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

For the patch:
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

BTW, What kind of lockdep warning? 
Do you mean it's generic issue that we can't use clk_hw_set_parent in clock driver?

Regards
Aisheng

> ---
>  drivers/clk/imx/clk-imx8mm.c | 3 ---
>  drivers/clk/imx/clk-imx8mn.c | 3 ---
>  drivers/clk/imx/clk-imx8mp.c | 3 ---
>  drivers/clk/imx/clk-imx8mq.c | 3 ---
>  4 files changed, 12 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index
> 925670438f23..5435042a06e3 100644
> --- a/drivers/clk/imx/clk-imx8mm.c
> +++ b/drivers/clk/imx/clk-imx8mm.c
> @@ -614,9 +614,6 @@ static int imx8mm_clocks_probe(struct
> platform_device *pdev)
>  					   hws[IMX8MM_ARM_PLL_OUT]->clk,
>  					   hws[IMX8MM_CLK_A53_DIV]->clk);
> 
> -	clk_hw_set_parent(hws[IMX8MM_CLK_A53_SRC],
> hws[IMX8MM_SYS_PLL1_800M]);
> -	clk_hw_set_parent(hws[IMX8MM_CLK_A53_CORE],
> hws[IMX8MM_ARM_PLL_OUT]);
> -
>  	imx_check_clk_hws(hws, IMX8MM_CLK_END);
> 
>  	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
> diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index
> 0bc7070235bd..6cac6ca03e12 100644
> --- a/drivers/clk/imx/clk-imx8mn.c
> +++ b/drivers/clk/imx/clk-imx8mn.c
> @@ -565,9 +565,6 @@ static int imx8mn_clocks_probe(struct platform_device
> *pdev)
>  					   hws[IMX8MN_ARM_PLL_OUT]->clk,
>  					   hws[IMX8MN_CLK_A53_DIV]->clk);
> 
> -	clk_hw_set_parent(hws[IMX8MN_CLK_A53_SRC],
> hws[IMX8MN_SYS_PLL1_800M]);
> -	clk_hw_set_parent(hws[IMX8MN_CLK_A53_CORE],
> hws[IMX8MN_ARM_PLL_OUT]);
> -
>  	imx_check_clk_hws(hws, IMX8MN_CLK_END);
> 
>  	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index
> 41469e2cc3de..e05ec56df285 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -735,9 +735,6 @@ static int imx8mp_clocks_probe(struct platform_device
> *pdev)
>  					     hws[IMX8MP_ARM_PLL_OUT]->clk,
>  					     hws[IMX8MP_CLK_A53_DIV]->clk);
> 
> -	clk_hw_set_parent(hws[IMX8MP_CLK_A53_SRC],
> hws[IMX8MP_SYS_PLL1_800M]);
> -	clk_hw_set_parent(hws[IMX8MP_CLK_A53_CORE],
> hws[IMX8MP_ARM_PLL_OUT]);
> -
>  	imx_check_clk_hws(hws, IMX8MP_CLK_END);
> 
>  	of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); diff
> --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index
> fdc68db68de5..201c7bbb201f 100644
> --- a/drivers/clk/imx/clk-imx8mq.c
> +++ b/drivers/clk/imx/clk-imx8mq.c
> @@ -599,9 +599,6 @@ static int imx8mq_clocks_probe(struct platform_device
> *pdev)
>  					   hws[IMX8MQ_ARM_PLL_OUT]->clk,
>  					   hws[IMX8MQ_CLK_A53_DIV]->clk);
> 
> -	clk_hw_set_parent(hws[IMX8MQ_CLK_A53_SRC],
> hws[IMX8MQ_SYS1_PLL_800M]);
> -	clk_hw_set_parent(hws[IMX8MQ_CLK_A53_CORE],
> hws[IMX8MQ_ARM_PLL_OUT]);
> -
>  	imx_check_clk_hws(hws, IMX8MQ_CLK_END);
> 
>  	err = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
> --
> 2.16.4

RE: [PATCH V2 02/10] clk: imx8m: drop clk_hw_set_parent for A53

[Aisheng Dong]

> From: Peng Fan <peng.fan@nxp.com>
> Sent: Thursday, March 12, 2020 6:20 PM
> 
> The parent settings have been moved to dtsi, we no need to set parent here. And
> clk_hw_set_parent will trigger lockdep warning, because this api not have
> prepare_lock.
> 
> Reported-by: Leonard Crestez <leonard.crestez@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

For the patch:
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

BTW, What kind of lockdep warning? 
Do you mean it's generic issue that we can't use clk_hw_set_parent in clock driver?

Regards
Aisheng

> ---
>  drivers/clk/imx/clk-imx8mm.c | 3 ---
>  drivers/clk/imx/clk-imx8mn.c | 3 ---
>  drivers/clk/imx/clk-imx8mp.c | 3 ---
>  drivers/clk/imx/clk-imx8mq.c | 3 ---
>  4 files changed, 12 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index
> 925670438f23..5435042a06e3 100644
> --- a/drivers/clk/imx/clk-imx8mm.c
> +++ b/drivers/clk/imx/clk-imx8mm.c
> @@ -614,9 +614,6 @@ static int imx8mm_clocks_probe(struct
> platform_device *pdev)
>  					   hws[IMX8MM_ARM_PLL_OUT]->clk,
>  					   hws[IMX8MM_CLK_A53_DIV]->clk);
> 
> -	clk_hw_set_parent(hws[IMX8MM_CLK_A53_SRC],
> hws[IMX8MM_SYS_PLL1_800M]);
> -	clk_hw_set_parent(hws[IMX8MM_CLK_A53_CORE],
> hws[IMX8MM_ARM_PLL_OUT]);
> -
>  	imx_check_clk_hws(hws, IMX8MM_CLK_END);
> 
>  	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
> diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index
> 0bc7070235bd..6cac6ca03e12 100644
> --- a/drivers/clk/imx/clk-imx8mn.c
> +++ b/drivers/clk/imx/clk-imx8mn.c
> @@ -565,9 +565,6 @@ static int imx8mn_clocks_probe(struct platform_device
> *pdev)
>  					   hws[IMX8MN_ARM_PLL_OUT]->clk,
>  					   hws[IMX8MN_CLK_A53_DIV]->clk);
> 
> -	clk_hw_set_parent(hws[IMX8MN_CLK_A53_SRC],
> hws[IMX8MN_SYS_PLL1_800M]);
> -	clk_hw_set_parent(hws[IMX8MN_CLK_A53_CORE],
> hws[IMX8MN_ARM_PLL_OUT]);
> -
>  	imx_check_clk_hws(hws, IMX8MN_CLK_END);
> 
>  	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index
> 41469e2cc3de..e05ec56df285 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -735,9 +735,6 @@ static int imx8mp_clocks_probe(struct platform_device
> *pdev)
>  					     hws[IMX8MP_ARM_PLL_OUT]->clk,
>  					     hws[IMX8MP_CLK_A53_DIV]->clk);
> 
> -	clk_hw_set_parent(hws[IMX8MP_CLK_A53_SRC],
> hws[IMX8MP_SYS_PLL1_800M]);
> -	clk_hw_set_parent(hws[IMX8MP_CLK_A53_CORE],
> hws[IMX8MP_ARM_PLL_OUT]);
> -
>  	imx_check_clk_hws(hws, IMX8MP_CLK_END);
> 
>  	of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); diff
> --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index
> fdc68db68de5..201c7bbb201f 100644
> --- a/drivers/clk/imx/clk-imx8mq.c
> +++ b/drivers/clk/imx/clk-imx8mq.c
> @@ -599,9 +599,6 @@ static int imx8mq_clocks_probe(struct platform_device
> *pdev)
>  					   hws[IMX8MQ_ARM_PLL_OUT]->clk,
>  					   hws[IMX8MQ_CLK_A53_DIV]->clk);
> 
> -	clk_hw_set_parent(hws[IMX8MQ_CLK_A53_SRC],
> hws[IMX8MQ_SYS1_PLL_800M]);
> -	clk_hw_set_parent(hws[IMX8MQ_CLK_A53_CORE],
> hws[IMX8MQ_ARM_PLL_OUT]);
> -
>  	imx_check_clk_hws(hws, IMX8MQ_CLK_END);
> 
>  	err = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
> --
> 2.16.4

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RE: [PATCH V2 03/10] clk: imx: imx8mp: fix pll mux bit

[Aisheng Dong]

> From: Peng Fan <peng.fan@nxp.com>
> Sent: Thursday, March 12, 2020 6:20 PM
> 
> Same to i.MX8MN/i.MX8MM, pll BYPASS bit should be kept inside pll driver for
> glitchless freq setting following spec. If exposing the bit, that means pll driver
> and clk driver has two paths to touch this bit, which is wrong.
> 
> So use EXT_BYPASS bit here.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

Regards
Aisheng

RE: [PATCH V2 03/10] clk: imx: imx8mp: fix pll mux bit

[Aisheng Dong]

> From: Peng Fan <peng.fan@nxp.com>
> Sent: Thursday, March 12, 2020 6:20 PM
> 
> Same to i.MX8MN/i.MX8MM, pll BYPASS bit should be kept inside pll driver for
> glitchless freq setting following spec. If exposing the bit, that means pll driver
> and clk driver has two paths to touch this bit, which is wrong.
> 
> So use EXT_BYPASS bit here.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

Regards
Aisheng
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RE: [PATCH V2 04/10] clk: imx8mp: Define gates for pll1/2 fixed dividers

[Aisheng Dong]

> From: Peng Fan <peng.fan@nxp.com>
> Sent: Thursday, March 12, 2020 6:20 PM
> 
> Inspried from
> commit e8688fe8df7d ("clk: imx8mn: Define gates for pll1/2 fixed dividers")
> 
> On imx8mp there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2 each
> with their own gate. Only one of these gates (the one "dividing" by
> one) is currently defined and it's incorrectly set as the parent of all the
> fixed-factor dividers.
> 
> Add the other 8 gates to the clock tree between sys_pll1/2_bypass and the fixed
> dividers.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

Regards
Aisheng

RE: [PATCH V2 04/10] clk: imx8mp: Define gates for pll1/2 fixed dividers

[Aisheng Dong]

> From: Peng Fan <peng.fan@nxp.com>
> Sent: Thursday, March 12, 2020 6:20 PM
> 
> Inspried from
> commit e8688fe8df7d ("clk: imx8mn: Define gates for pll1/2 fixed dividers")
> 
> On imx8mp there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2 each
> with their own gate. Only one of these gates (the one "dividing" by
> one) is currently defined and it's incorrectly set as the parent of all the
> fixed-factor dividers.
> 
> Add the other 8 gates to the clock tree between sys_pll1/2_bypass and the fixed
> dividers.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

Regards
Aisheng
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RE: [PATCH V2 05/10] clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code

[Aisheng Dong]

> From: Peng Fan <peng.fan@nxp.com>
> Sent: Thursday, March 12, 2020 6:20 PM
> 
> Use imx8m_clk_hw_composite_core to simpliy clks that belong to core clk slice.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Should we also deprecated the old clock ids which will not be supported by driver anymore?
Otherwise:
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

Regards
Aisheng

> ---
>  drivers/clk/imx/clk-imx8mp.c             | 47
> +++++++++++---------------------
>  include/dt-bindings/clock/imx8mp-clock.h | 11 +++++++-
>  2 files changed, 26 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index
> a7613c7355c8..998e9e63f831 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -546,33 +546,18 @@ static int imx8mp_clocks_probe(struct
> platform_device *pdev)
>  	hws[IMX8MP_SYS_PLL2_500M] =
> imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
>  	hws[IMX8MP_SYS_PLL2_1000M] =
> imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
> 
> -	hws[IMX8MP_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src",
> ccm_base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels));
> -	hws[IMX8MP_CLK_M7_SRC] = imx_clk_hw_mux2("arm_m7_src",
> ccm_base + 0x8080, 24, 3, imx8mp_m7_sels, ARRAY_SIZE(imx8mp_m7_sels));
> -	hws[IMX8MP_CLK_ML_SRC] = imx_clk_hw_mux2("ml_src", ccm_base +
> 0x8100, 24, 3, imx8mp_ml_sels, ARRAY_SIZE(imx8mp_ml_sels));
> -	hws[IMX8MP_CLK_GPU3D_CORE_SRC] =
> imx_clk_hw_mux2("gpu3d_core_src", ccm_base + 0x8180, 24, 3,
> imx8mp_gpu3d_core_sels, ARRAY_SIZE(imx8mp_gpu3d_core_sels));
> -	hws[IMX8MP_CLK_GPU3D_SHADER_SRC] =
> imx_clk_hw_mux2("gpu3d_shader_src", ccm_base + 0x8200, 24, 3,
> imx8mp_gpu3d_shader_sels, ARRAY_SIZE(imx8mp_gpu3d_shader_sels));
> -	hws[IMX8MP_CLK_GPU2D_SRC] = imx_clk_hw_mux2("gpu2d_src",
> ccm_base + 0x8280, 24, 3, imx8mp_gpu2d_sels,
> ARRAY_SIZE(imx8mp_gpu2d_sels));
> -	hws[IMX8MP_CLK_AUDIO_AXI_SRC] = imx_clk_hw_mux2("audio_axi_src",
> ccm_base + 0x8300, 24, 3, imx8mp_audio_axi_sels,
> ARRAY_SIZE(imx8mp_audio_axi_sels));
> -	hws[IMX8MP_CLK_HSIO_AXI_SRC] = imx_clk_hw_mux2("hsio_axi_src",
> ccm_base + 0x8380, 24, 3, imx8mp_hsio_axi_sels,
> ARRAY_SIZE(imx8mp_hsio_axi_sels));
> -	hws[IMX8MP_CLK_MEDIA_ISP_SRC] = imx_clk_hw_mux2("media_isp_src",
> ccm_base + 0x8400, 24, 3, imx8mp_media_isp_sels,
> ARRAY_SIZE(imx8mp_media_isp_sels));
> -	hws[IMX8MP_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg",
> "arm_a53_src", ccm_base + 0x8000, 28);
> -	hws[IMX8MP_CLK_M4_CG] = imx_clk_hw_gate3("arm_m7_cg",
> "arm_m7_src", ccm_base + 0x8080, 28);
> -	hws[IMX8MP_CLK_ML_CG] = imx_clk_hw_gate3("ml_cg", "ml_src",
> ccm_base + 0x8100, 28);
> -	hws[IMX8MP_CLK_GPU3D_CORE_CG] =
> imx_clk_hw_gate3("gpu3d_core_cg", "gpu3d_core_src", ccm_base + 0x8180,
> 28);
> -	hws[IMX8MP_CLK_GPU3D_SHADER_CG] =
> imx_clk_hw_gate3("gpu3d_shader_cg", "gpu3d_shader_src", ccm_base +
> 0x8200, 28);
> -	hws[IMX8MP_CLK_GPU2D_CG] = imx_clk_hw_gate3("gpu2d_cg",
> "gpu2d_src", ccm_base + 0x8280, 28);
> -	hws[IMX8MP_CLK_AUDIO_AXI_CG] = imx_clk_hw_gate3("audio_axi_cg",
> "audio_axi_src", ccm_base + 0x8300, 28);
> -	hws[IMX8MP_CLK_HSIO_AXI_CG] = imx_clk_hw_gate3("hsio_axi_cg",
> "hsio_axi_src", ccm_base + 0x8380, 28);
> -	hws[IMX8MP_CLK_MEDIA_ISP_CG] = imx_clk_hw_gate3("media_isp_cg",
> "media_isp_src", ccm_base + 0x8400, 28);
> -	hws[IMX8MP_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div",
> "arm_a53_cg", ccm_base + 0x8000, 0, 3);
> -	hws[IMX8MP_CLK_M7_DIV] = imx_clk_hw_divider2("arm_m7_div",
> "arm_m7_cg", ccm_base + 0x8080, 0, 3);
> -	hws[IMX8MP_CLK_ML_DIV] = imx_clk_hw_divider2("ml_div", "ml_cg",
> ccm_base + 0x8100, 0, 3);
> -	hws[IMX8MP_CLK_GPU3D_CORE_DIV] =
> imx_clk_hw_divider2("gpu3d_core_div", "gpu3d_core_cg", ccm_base + 0x8180,
> 0, 3);
> -	hws[IMX8MP_CLK_GPU3D_SHADER_DIV] =
> imx_clk_hw_divider2("gpu3d_shader_div", "gpu3d_shader_cg", ccm_base +
> 0x8200, 0, 3);
> -	hws[IMX8MP_CLK_GPU2D_DIV] = imx_clk_hw_divider2("gpu2d_div",
> "gpu2d_cg", ccm_base + 0x8280, 0, 3);
> -	hws[IMX8MP_CLK_AUDIO_AXI_DIV] =
> imx_clk_hw_divider2("audio_axi_div", "audio_axi_cg", ccm_base + 0x8300, 0,
> 3);
> -	hws[IMX8MP_CLK_HSIO_AXI_DIV] = imx_clk_hw_divider2("hsio_axi_div",
> "hsio_axi_cg", ccm_base + 0x8380, 0, 3);
> -	hws[IMX8MP_CLK_MEDIA_ISP_DIV] =
> imx_clk_hw_divider2("media_isp_div", "media_isp_cg", ccm_base + 0x8400, 0,
> 3);
> +	hws[IMX8MP_CLK_A53_DIV] =
> imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, ccm_base
> + 0x8000);
> +	hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV];
> +	hws[IMX8MP_CLK_A53_CG] = hws[IMX8MP_CLK_A53_DIV];
> +	hws[IMX8MP_CLK_M7_CORE] =
> imx8m_clk_hw_composite_core("m7_core", imx8mp_m7_sels, ccm_base +
> 0x8080);
> +	hws[IMX8MP_CLK_ML_CORE] =
> imx8m_clk_hw_composite_core("ml_core", imx8mp_ml_sels, ccm_base +
> 0x8100);
> +	hws[IMX8MP_CLK_GPU3D_CORE] =
> imx8m_clk_hw_composite_core("gpu3d_core", imx8mp_gpu3d_core_sels,
> ccm_base + 0x8180);
> +	hws[IMX8MP_CLK_GPU3D_SHADER_CORE] =
> imx8m_clk_hw_composite("gpu3d_shader_core", imx8mp_gpu3d_shader_sels,
> ccm_base + 0x8200);
> +	hws[IMX8MP_CLK_GPU2D_CORE] =
> imx8m_clk_hw_composite("gpu2d_core", imx8mp_gpu2d_sels, ccm_base +
> 0x8280);
> +	hws[IMX8MP_CLK_AUDIO_AXI] = imx8m_clk_hw_composite("audio_axi",
> imx8mp_audio_axi_sels, ccm_base + 0x8300);
> +	hws[IMX8MP_CLK_AUDIO_AXI_SRC] = hws[IMX8MP_CLK_AUDIO_AXI];
> +	hws[IMX8MP_CLK_HSIO_AXI] = imx8m_clk_hw_composite("hsio_axi",
> imx8mp_hsio_axi_sels, ccm_base + 0x8380);
> +	hws[IMX8MP_CLK_MEDIA_ISP] = imx8m_clk_hw_composite("media_isp",
> +imx8mp_media_isp_sels, ccm_base + 0x8400);
> 
>  	/* CORE SEL */
>  	hws[IMX8MP_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core",
> ccm_base + 0x9880, 24, 1, imx8mp_a53_core_sels,
> ARRAY_SIZE(imx8mp_a53_core_sels));
> @@ -713,8 +698,8 @@ static int imx8mp_clocks_probe(struct platform_device
> *pdev)
>  	hws[IMX8MP_CLK_SDMA1_ROOT] = imx_clk_hw_gate4("sdma1_root_clk",
> "ipg_root", ccm_base + 0x43a0, 0);
>  	hws[IMX8MP_CLK_ENET_QOS_ROOT] =
> imx_clk_hw_gate4("enet_qos_root_clk", "sim_enet_root_clk", ccm_base +
> 0x43b0, 0);
>  	hws[IMX8MP_CLK_SIM_ENET_ROOT] =
> imx_clk_hw_gate4("sim_enet_root_clk", "enet_axi", ccm_base + 0x4400, 0);
> -	hws[IMX8MP_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk",
> "gpu2d_div", ccm_base + 0x4450, 0);
> -	hws[IMX8MP_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk",
> "gpu3d_core_div", ccm_base + 0x4460, 0);
> +	hws[IMX8MP_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk",
> "gpu2d_core", ccm_base + 0x4450, 0);
> +	hws[IMX8MP_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk",
> +"gpu3d_core", ccm_base + 0x4460, 0);
>  	hws[IMX8MP_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk",
> "ipg_root", ccm_base + 0x4470, 0);
>  	hws[IMX8MP_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk",
> "uart1", ccm_base + 0x4490, 0);
>  	hws[IMX8MP_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk",
> "uart2", ccm_base + 0x44a0, 0); @@ -731,7 +716,7 @@ static int
> imx8mp_clocks_probe(struct platform_device *pdev)
>  	hws[IMX8MP_CLK_GPU_ROOT] = imx_clk_hw_gate4("gpu_root_clk",
> "gpu_axi", ccm_base + 0x4570, 0);
>  	hws[IMX8MP_CLK_VPU_VC8KE_ROOT] =
> imx_clk_hw_gate4("vpu_vc8ke_root_clk", "vpu_vc8000e", ccm_base + 0x4590,
> 0);
>  	hws[IMX8MP_CLK_VPU_G2_ROOT] =
> imx_clk_hw_gate4("vpu_g2_root_clk", "vpu_g2", ccm_base + 0x45a0, 0);
> -	hws[IMX8MP_CLK_NPU_ROOT] = imx_clk_hw_gate4("npu_root_clk",
> "ml_div", ccm_base + 0x45b0, 0);
> +	hws[IMX8MP_CLK_NPU_ROOT] = imx_clk_hw_gate4("npu_root_clk",
> "ml_core",
> +ccm_base + 0x45b0, 0);
>  	hws[IMX8MP_CLK_HSIO_ROOT] = imx_clk_hw_gate4("hsio_root_clk",
> "ipg_root", ccm_base + 0x45c0, 0);
>  	hws[IMX8MP_CLK_MEDIA_APB_ROOT] =
> imx_clk_hw_gate2_shared2("media_apb_root_clk", "media_apb", ccm_base +
> 0x45d0, 0, &share_count_media);
>  	hws[IMX8MP_CLK_MEDIA_AXI_ROOT] =
> imx_clk_hw_gate2_shared2("media_axi_root_clk", "media_axi", ccm_base +
> 0x45d0, 0, &share_count_media); @@ -739,7 +724,7 @@ static int
> imx8mp_clocks_probe(struct platform_device *pdev)
>  	hws[IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT] =
> imx_clk_hw_gate2_shared2("media_cam2_pix_root_clk", "media_cam2_pix",
> ccm_base + 0x45d0, 0, &share_count_media);
>  	hws[IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT] =
> imx_clk_hw_gate2_shared2("media_disp1_pix_root_clk", "media_disp1_pix",
> ccm_base + 0x45d0, 0, &share_count_media);
>  	hws[IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT] =
> imx_clk_hw_gate2_shared2("media_disp2_pix_root_clk", "media_disp2_pix",
> ccm_base + 0x45d0, 0, &share_count_media);
> -	hws[IMX8MP_CLK_MEDIA_ISP_ROOT] =
> imx_clk_hw_gate2_shared2("media_isp_root_clk", "media_isp_div", ccm_base
> + 0x45d0, 0, &share_count_media);
> +	hws[IMX8MP_CLK_MEDIA_ISP_ROOT] =
> +imx_clk_hw_gate2_shared2("media_isp_root_clk", "media_isp", ccm_base +
> +0x45d0, 0, &share_count_media);
> 
>  	hws[IMX8MP_CLK_USDHC3_ROOT] =
> imx_clk_hw_gate4("usdhc3_root_clk", "usdhc3", ccm_base + 0x45e0, 0);
>  	hws[IMX8MP_CLK_HDMI_ROOT] = imx_clk_hw_gate4("hdmi_root_clk",
> "hdmi_axi", ccm_base + 0x45f0, 0); diff --git
> a/include/dt-bindings/clock/imx8mp-clock.h
> b/include/dt-bindings/clock/imx8mp-clock.h
> index 46c69cd66c62..8430bc4fd182 100644
> --- a/include/dt-bindings/clock/imx8mp-clock.h
> +++ b/include/dt-bindings/clock/imx8mp-clock.h
> @@ -313,6 +313,15 @@
>  #define IMX8MP_SYS_PLL2_333M_CG			303
>  #define IMX8MP_SYS_PLL2_500M_CG			304
> 
> -#define IMX8MP_CLK_END				305
> +#define IMX8MP_CLK_M7_CORE			305
> +#define IMX8MP_CLK_ML_CORE			306
> +#define IMX8MP_CLK_GPU3D_CORE			307
> +#define IMX8MP_CLK_GPU3D_SHADER_CORE		308
> +#define IMX8MP_CLK_GPU2D_CORE			309
> +#define IMX8MP_CLK_AUDIO_AXI			310
> +#define IMX8MP_CLK_HSIO_AXI			311
> +#define IMX8MP_CLK_MEDIA_ISP			312
> +
> +#define IMX8MP_CLK_END				313
> 
>  #endif
> --
> 2.16.4

RE: [PATCH V2 05/10] clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code

[Aisheng Dong]

> From: Peng Fan <peng.fan@nxp.com>
> Sent: Thursday, March 12, 2020 6:20 PM
> 
> Use imx8m_clk_hw_composite_core to simpliy clks that belong to core clk slice.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Should we also deprecated the old clock ids which will not be supported by driver anymore?
Otherwise:
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

Regards
Aisheng

> ---
>  drivers/clk/imx/clk-imx8mp.c             | 47
> +++++++++++---------------------
>  include/dt-bindings/clock/imx8mp-clock.h | 11 +++++++-
>  2 files changed, 26 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index
> a7613c7355c8..998e9e63f831 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -546,33 +546,18 @@ static int imx8mp_clocks_probe(struct
> platform_device *pdev)
>  	hws[IMX8MP_SYS_PLL2_500M] =
> imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
>  	hws[IMX8MP_SYS_PLL2_1000M] =
> imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
> 
> -	hws[IMX8MP_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src",
> ccm_base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels));
> -	hws[IMX8MP_CLK_M7_SRC] = imx_clk_hw_mux2("arm_m7_src",
> ccm_base + 0x8080, 24, 3, imx8mp_m7_sels, ARRAY_SIZE(imx8mp_m7_sels));
> -	hws[IMX8MP_CLK_ML_SRC] = imx_clk_hw_mux2("ml_src", ccm_base +
> 0x8100, 24, 3, imx8mp_ml_sels, ARRAY_SIZE(imx8mp_ml_sels));
> -	hws[IMX8MP_CLK_GPU3D_CORE_SRC] =
> imx_clk_hw_mux2("gpu3d_core_src", ccm_base + 0x8180, 24, 3,
> imx8mp_gpu3d_core_sels, ARRAY_SIZE(imx8mp_gpu3d_core_sels));
> -	hws[IMX8MP_CLK_GPU3D_SHADER_SRC] =
> imx_clk_hw_mux2("gpu3d_shader_src", ccm_base + 0x8200, 24, 3,
> imx8mp_gpu3d_shader_sels, ARRAY_SIZE(imx8mp_gpu3d_shader_sels));
> -	hws[IMX8MP_CLK_GPU2D_SRC] = imx_clk_hw_mux2("gpu2d_src",
> ccm_base + 0x8280, 24, 3, imx8mp_gpu2d_sels,
> ARRAY_SIZE(imx8mp_gpu2d_sels));
> -	hws[IMX8MP_CLK_AUDIO_AXI_SRC] = imx_clk_hw_mux2("audio_axi_src",
> ccm_base + 0x8300, 24, 3, imx8mp_audio_axi_sels,
> ARRAY_SIZE(imx8mp_audio_axi_sels));
> -	hws[IMX8MP_CLK_HSIO_AXI_SRC] = imx_clk_hw_mux2("hsio_axi_src",
> ccm_base + 0x8380, 24, 3, imx8mp_hsio_axi_sels,
> ARRAY_SIZE(imx8mp_hsio_axi_sels));
> -	hws[IMX8MP_CLK_MEDIA_ISP_SRC] = imx_clk_hw_mux2("media_isp_src",
> ccm_base + 0x8400, 24, 3, imx8mp_media_isp_sels,
> ARRAY_SIZE(imx8mp_media_isp_sels));
> -	hws[IMX8MP_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg",
> "arm_a53_src", ccm_base + 0x8000, 28);
> -	hws[IMX8MP_CLK_M4_CG] = imx_clk_hw_gate3("arm_m7_cg",
> "arm_m7_src", ccm_base + 0x8080, 28);
> -	hws[IMX8MP_CLK_ML_CG] = imx_clk_hw_gate3("ml_cg", "ml_src",
> ccm_base + 0x8100, 28);
> -	hws[IMX8MP_CLK_GPU3D_CORE_CG] =
> imx_clk_hw_gate3("gpu3d_core_cg", "gpu3d_core_src", ccm_base + 0x8180,
> 28);
> -	hws[IMX8MP_CLK_GPU3D_SHADER_CG] =
> imx_clk_hw_gate3("gpu3d_shader_cg", "gpu3d_shader_src", ccm_base +
> 0x8200, 28);
> -	hws[IMX8MP_CLK_GPU2D_CG] = imx_clk_hw_gate3("gpu2d_cg",
> "gpu2d_src", ccm_base + 0x8280, 28);
> -	hws[IMX8MP_CLK_AUDIO_AXI_CG] = imx_clk_hw_gate3("audio_axi_cg",
> "audio_axi_src", ccm_base + 0x8300, 28);
> -	hws[IMX8MP_CLK_HSIO_AXI_CG] = imx_clk_hw_gate3("hsio_axi_cg",
> "hsio_axi_src", ccm_base + 0x8380, 28);
> -	hws[IMX8MP_CLK_MEDIA_ISP_CG] = imx_clk_hw_gate3("media_isp_cg",
> "media_isp_src", ccm_base + 0x8400, 28);
> -	hws[IMX8MP_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div",
> "arm_a53_cg", ccm_base + 0x8000, 0, 3);
> -	hws[IMX8MP_CLK_M7_DIV] = imx_clk_hw_divider2("arm_m7_div",
> "arm_m7_cg", ccm_base + 0x8080, 0, 3);
> -	hws[IMX8MP_CLK_ML_DIV] = imx_clk_hw_divider2("ml_div", "ml_cg",
> ccm_base + 0x8100, 0, 3);
> -	hws[IMX8MP_CLK_GPU3D_CORE_DIV] =
> imx_clk_hw_divider2("gpu3d_core_div", "gpu3d_core_cg", ccm_base + 0x8180,
> 0, 3);
> -	hws[IMX8MP_CLK_GPU3D_SHADER_DIV] =
> imx_clk_hw_divider2("gpu3d_shader_div", "gpu3d_shader_cg", ccm_base +
> 0x8200, 0, 3);
> -	hws[IMX8MP_CLK_GPU2D_DIV] = imx_clk_hw_divider2("gpu2d_div",
> "gpu2d_cg", ccm_base + 0x8280, 0, 3);
> -	hws[IMX8MP_CLK_AUDIO_AXI_DIV] =
> imx_clk_hw_divider2("audio_axi_div", "audio_axi_cg", ccm_base + 0x8300, 0,
> 3);
> -	hws[IMX8MP_CLK_HSIO_AXI_DIV] = imx_clk_hw_divider2("hsio_axi_div",
> "hsio_axi_cg", ccm_base + 0x8380, 0, 3);
> -	hws[IMX8MP_CLK_MEDIA_ISP_DIV] =
> imx_clk_hw_divider2("media_isp_div", "media_isp_cg", ccm_base + 0x8400, 0,
> 3);
> +	hws[IMX8MP_CLK_A53_DIV] =
> imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, ccm_base
> + 0x8000);
> +	hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV];
> +	hws[IMX8MP_CLK_A53_CG] = hws[IMX8MP_CLK_A53_DIV];
> +	hws[IMX8MP_CLK_M7_CORE] =
> imx8m_clk_hw_composite_core("m7_core", imx8mp_m7_sels, ccm_base +
> 0x8080);
> +	hws[IMX8MP_CLK_ML_CORE] =
> imx8m_clk_hw_composite_core("ml_core", imx8mp_ml_sels, ccm_base +
> 0x8100);
> +	hws[IMX8MP_CLK_GPU3D_CORE] =
> imx8m_clk_hw_composite_core("gpu3d_core", imx8mp_gpu3d_core_sels,
> ccm_base + 0x8180);
> +	hws[IMX8MP_CLK_GPU3D_SHADER_CORE] =
> imx8m_clk_hw_composite("gpu3d_shader_core", imx8mp_gpu3d_shader_sels,
> ccm_base + 0x8200);
> +	hws[IMX8MP_CLK_GPU2D_CORE] =
> imx8m_clk_hw_composite("gpu2d_core", imx8mp_gpu2d_sels, ccm_base +
> 0x8280);
> +	hws[IMX8MP_CLK_AUDIO_AXI] = imx8m_clk_hw_composite("audio_axi",
> imx8mp_audio_axi_sels, ccm_base + 0x8300);
> +	hws[IMX8MP_CLK_AUDIO_AXI_SRC] = hws[IMX8MP_CLK_AUDIO_AXI];
> +	hws[IMX8MP_CLK_HSIO_AXI] = imx8m_clk_hw_composite("hsio_axi",
> imx8mp_hsio_axi_sels, ccm_base + 0x8380);
> +	hws[IMX8MP_CLK_MEDIA_ISP] = imx8m_clk_hw_composite("media_isp",
> +imx8mp_media_isp_sels, ccm_base + 0x8400);
> 
>  	/* CORE SEL */
>  	hws[IMX8MP_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core",
> ccm_base + 0x9880, 24, 1, imx8mp_a53_core_sels,
> ARRAY_SIZE(imx8mp_a53_core_sels));
> @@ -713,8 +698,8 @@ static int imx8mp_clocks_probe(struct platform_device
> *pdev)
>  	hws[IMX8MP_CLK_SDMA1_ROOT] = imx_clk_hw_gate4("sdma1_root_clk",
> "ipg_root", ccm_base + 0x43a0, 0);
>  	hws[IMX8MP_CLK_ENET_QOS_ROOT] =
> imx_clk_hw_gate4("enet_qos_root_clk", "sim_enet_root_clk", ccm_base +
> 0x43b0, 0);
>  	hws[IMX8MP_CLK_SIM_ENET_ROOT] =
> imx_clk_hw_gate4("sim_enet_root_clk", "enet_axi", ccm_base + 0x4400, 0);
> -	hws[IMX8MP_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk",
> "gpu2d_div", ccm_base + 0x4450, 0);
> -	hws[IMX8MP_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk",
> "gpu3d_core_div", ccm_base + 0x4460, 0);
> +	hws[IMX8MP_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk",
> "gpu2d_core", ccm_base + 0x4450, 0);
> +	hws[IMX8MP_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk",
> +"gpu3d_core", ccm_base + 0x4460, 0);
>  	hws[IMX8MP_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk",
> "ipg_root", ccm_base + 0x4470, 0);
>  	hws[IMX8MP_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk",
> "uart1", ccm_base + 0x4490, 0);
>  	hws[IMX8MP_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk",
> "uart2", ccm_base + 0x44a0, 0); @@ -731,7 +716,7 @@ static int
> imx8mp_clocks_probe(struct platform_device *pdev)
>  	hws[IMX8MP_CLK_GPU_ROOT] = imx_clk_hw_gate4("gpu_root_clk",
> "gpu_axi", ccm_base + 0x4570, 0);
>  	hws[IMX8MP_CLK_VPU_VC8KE_ROOT] =
> imx_clk_hw_gate4("vpu_vc8ke_root_clk", "vpu_vc8000e", ccm_base + 0x4590,
> 0);
>  	hws[IMX8MP_CLK_VPU_G2_ROOT] =
> imx_clk_hw_gate4("vpu_g2_root_clk", "vpu_g2", ccm_base + 0x45a0, 0);
> -	hws[IMX8MP_CLK_NPU_ROOT] = imx_clk_hw_gate4("npu_root_clk",
> "ml_div", ccm_base + 0x45b0, 0);
> +	hws[IMX8MP_CLK_NPU_ROOT] = imx_clk_hw_gate4("npu_root_clk",
> "ml_core",
> +ccm_base + 0x45b0, 0);
>  	hws[IMX8MP_CLK_HSIO_ROOT] = imx_clk_hw_gate4("hsio_root_clk",
> "ipg_root", ccm_base + 0x45c0, 0);
>  	hws[IMX8MP_CLK_MEDIA_APB_ROOT] =
> imx_clk_hw_gate2_shared2("media_apb_root_clk", "media_apb", ccm_base +
> 0x45d0, 0, &share_count_media);
>  	hws[IMX8MP_CLK_MEDIA_AXI_ROOT] =
> imx_clk_hw_gate2_shared2("media_axi_root_clk", "media_axi", ccm_base +
> 0x45d0, 0, &share_count_media); @@ -739,7 +724,7 @@ static int
> imx8mp_clocks_probe(struct platform_device *pdev)
>  	hws[IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT] =
> imx_clk_hw_gate2_shared2("media_cam2_pix_root_clk", "media_cam2_pix",
> ccm_base + 0x45d0, 0, &share_count_media);
>  	hws[IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT] =
> imx_clk_hw_gate2_shared2("media_disp1_pix_root_clk", "media_disp1_pix",
> ccm_base + 0x45d0, 0, &share_count_media);
>  	hws[IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT] =
> imx_clk_hw_gate2_shared2("media_disp2_pix_root_clk", "media_disp2_pix",
> ccm_base + 0x45d0, 0, &share_count_media);
> -	hws[IMX8MP_CLK_MEDIA_ISP_ROOT] =
> imx_clk_hw_gate2_shared2("media_isp_root_clk", "media_isp_div", ccm_base
> + 0x45d0, 0, &share_count_media);
> +	hws[IMX8MP_CLK_MEDIA_ISP_ROOT] =
> +imx_clk_hw_gate2_shared2("media_isp_root_clk", "media_isp", ccm_base +
> +0x45d0, 0, &share_count_media);
> 
>  	hws[IMX8MP_CLK_USDHC3_ROOT] =
> imx_clk_hw_gate4("usdhc3_root_clk", "usdhc3", ccm_base + 0x45e0, 0);
>  	hws[IMX8MP_CLK_HDMI_ROOT] = imx_clk_hw_gate4("hdmi_root_clk",
> "hdmi_axi", ccm_base + 0x45f0, 0); diff --git
> a/include/dt-bindings/clock/imx8mp-clock.h
> b/include/dt-bindings/clock/imx8mp-clock.h
> index 46c69cd66c62..8430bc4fd182 100644
> --- a/include/dt-bindings/clock/imx8mp-clock.h
> +++ b/include/dt-bindings/clock/imx8mp-clock.h
> @@ -313,6 +313,15 @@
>  #define IMX8MP_SYS_PLL2_333M_CG			303
>  #define IMX8MP_SYS_PLL2_500M_CG			304
> 
> -#define IMX8MP_CLK_END				305
> +#define IMX8MP_CLK_M7_CORE			305
> +#define IMX8MP_CLK_ML_CORE			306
> +#define IMX8MP_CLK_GPU3D_CORE			307
> +#define IMX8MP_CLK_GPU3D_SHADER_CORE		308
> +#define IMX8MP_CLK_GPU2D_CORE			309
> +#define IMX8MP_CLK_AUDIO_AXI			310
> +#define IMX8MP_CLK_HSIO_AXI			311
> +#define IMX8MP_CLK_MEDIA_ISP			312
> +
> +#define IMX8MP_CLK_END				313
> 
>  #endif
> --
> 2.16.4

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RE: [PATCH V2 06/10] clk: imx8m: migrate A53 clk root to use composite core

[Aisheng Dong]

> From: Peng Fan <peng.fan@nxp.com>
> Sent: Thursday, March 12, 2020 6:20 PM
> 
> Migrate A53 clk root to use composite core clk type. It will simplify code and
> make it easy to use composite specific mux operation.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  drivers/clk/imx/clk-imx8mm.c | 6 +++---  drivers/clk/imx/clk-imx8mn.c | 6
> +++---  drivers/clk/imx/clk-imx8mq.c | 6 +++---
>  3 files changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index
> 5435042a06e3..12443e06f329 100644
> --- a/drivers/clk/imx/clk-imx8mm.c
> +++ b/drivers/clk/imx/clk-imx8mm.c
> @@ -416,9 +416,9 @@ static int imx8mm_clocks_probe(struct
> platform_device *pdev)
>  		return PTR_ERR(base);
> 
>  	/* Core Slice */
> -	hws[IMX8MM_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base +
> 0x8000, 24, 3, imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels));
> -	hws[IMX8MM_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg",
> "arm_a53_src", base + 0x8000, 28);
> -	hws[IMX8MM_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div",
> "arm_a53_cg", base + 0x8000, 0, 3);
> +	hws[IMX8MM_CLK_A53_DIV] =
> imx8m_clk_hw_composite_core("arm_a53_div", imx8mm_a53_sels, base +
> 0x8000);
> +	hws[IMX8MM_CLK_A53_CG] = hws[IMX8MM_CLK_A53_DIV];
> +	hws[IMX8MM_CLK_A53_SRC] = hws[IMX8MM_CLK_A53_DIV];

The former patch already breaks the compatibility.
Not sure if we really need keep it for only A53 clock here as we are still at very early enablement
Phase for MX8MP.  So we may just remove them IMHO.
Shawn, what's your suggestion?

Regards
Aisheng

> 
>  	hws[IMX8MM_CLK_M4_CORE] =
> imx8m_clk_hw_composite_core("arm_m4_core", imx8mm_m4_sels, base +
> 0x8080);
>  	hws[IMX8MM_CLK_VPU_CORE] =
> imx8m_clk_hw_composite_core("vpu_core", imx8mm_vpu_sels, base +
> 0x8100); diff --git a/drivers/clk/imx/clk-imx8mn.c
> b/drivers/clk/imx/clk-imx8mn.c index 6cac6ca03e12..bd3759b4afd0 100644
> --- a/drivers/clk/imx/clk-imx8mn.c
> +++ b/drivers/clk/imx/clk-imx8mn.c
> @@ -413,9 +413,9 @@ static int imx8mn_clocks_probe(struct platform_device
> *pdev)
>  	}
> 
>  	/* CORE */
> -	hws[IMX8MN_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base +
> 0x8000, 24, 3, imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels));
> -	hws[IMX8MN_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg",
> "arm_a53_src", base + 0x8000, 28);
> -	hws[IMX8MN_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div",
> "arm_a53_cg", base + 0x8000, 0, 3);
> +	hws[IMX8MN_CLK_A53_DIV] =
> imx8m_clk_hw_composite_core("arm_a53_div", imx8mn_a53_sels, base +
> 0x8000);
> +	hws[IMX8MN_CLK_A53_SRC] = hws[IMX8MN_CLK_A53_DIV];
> +	hws[IMX8MN_CLK_A53_CG] = hws[IMX8MN_CLK_A53_DIV];
> 
>  	hws[IMX8MN_CLK_GPU_CORE] =
> imx8m_clk_hw_composite_core("gpu_core", imx8mn_gpu_core_sels, base +
> 0x8180);
>  	hws[IMX8MN_CLK_GPU_SHADER] =
> imx8m_clk_hw_composite_core("gpu_shader", imx8mn_gpu_shader_sels, base
> + 0x8200); diff --git a/drivers/clk/imx/clk-imx8mq.c
> b/drivers/clk/imx/clk-imx8mq.c index 201c7bbb201f..91309ff65441 100644
> --- a/drivers/clk/imx/clk-imx8mq.c
> +++ b/drivers/clk/imx/clk-imx8mq.c
> @@ -405,9 +405,9 @@ static int imx8mq_clocks_probe(struct platform_device
> *pdev)
>  		return PTR_ERR(base);
> 
>  	/* CORE */
> -	hws[IMX8MQ_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base +
> 0x8000, 24, 3, imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels));
> -	hws[IMX8MQ_CLK_A53_CG] = imx_clk_hw_gate3_flags("arm_a53_cg",
> "arm_a53_src", base + 0x8000, 28, CLK_IS_CRITICAL);
> -	hws[IMX8MQ_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div",
> "arm_a53_cg", base + 0x8000, 0, 3);
> +	hws[IMX8MQ_CLK_A53_DIV] =
> imx8m_clk_hw_composite_core("arm_a53_div", imx8mq_a53_sels, base +
> 0x8000);
> +	hws[IMX8MQ_CLK_A53_CG] = hws[IMX8MQ_CLK_A53_DIV];
> +	hws[IMX8MQ_CLK_A53_SRC] = hws[IMX8MQ_CLK_A53_DIV];
> 
>  	hws[IMX8MQ_CLK_M4_CORE] =
> imx8m_clk_hw_composite_core("arm_m4_core", imx8mq_arm_m4_sels, base
> + 0x8080);
>  	hws[IMX8MQ_CLK_VPU_CORE] =
> imx8m_clk_hw_composite_core("vpu_core", imx8mq_vpu_sels, base +
> 0x8100);
> --
> 2.16.4

RE: [PATCH V2 06/10] clk: imx8m: migrate A53 clk root to use composite core

[Aisheng Dong]

> From: Peng Fan <peng.fan@nxp.com>
> Sent: Thursday, March 12, 2020 6:20 PM
> 
> Migrate A53 clk root to use composite core clk type. It will simplify code and
> make it easy to use composite specific mux operation.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  drivers/clk/imx/clk-imx8mm.c | 6 +++---  drivers/clk/imx/clk-imx8mn.c | 6
> +++---  drivers/clk/imx/clk-imx8mq.c | 6 +++---
>  3 files changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index
> 5435042a06e3..12443e06f329 100644
> --- a/drivers/clk/imx/clk-imx8mm.c
> +++ b/drivers/clk/imx/clk-imx8mm.c
> @@ -416,9 +416,9 @@ static int imx8mm_clocks_probe(struct
> platform_device *pdev)
>  		return PTR_ERR(base);
> 
>  	/* Core Slice */
> -	hws[IMX8MM_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base +
> 0x8000, 24, 3, imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels));
> -	hws[IMX8MM_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg",
> "arm_a53_src", base + 0x8000, 28);
> -	hws[IMX8MM_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div",
> "arm_a53_cg", base + 0x8000, 0, 3);
> +	hws[IMX8MM_CLK_A53_DIV] =
> imx8m_clk_hw_composite_core("arm_a53_div", imx8mm_a53_sels, base +
> 0x8000);
> +	hws[IMX8MM_CLK_A53_CG] = hws[IMX8MM_CLK_A53_DIV];
> +	hws[IMX8MM_CLK_A53_SRC] = hws[IMX8MM_CLK_A53_DIV];

The former patch already breaks the compatibility.
Not sure if we really need keep it for only A53 clock here as we are still at very early enablement
Phase for MX8MP.  So we may just remove them IMHO.
Shawn, what's your suggestion?

Regards
Aisheng

> 
>  	hws[IMX8MM_CLK_M4_CORE] =
> imx8m_clk_hw_composite_core("arm_m4_core", imx8mm_m4_sels, base +
> 0x8080);
>  	hws[IMX8MM_CLK_VPU_CORE] =
> imx8m_clk_hw_composite_core("vpu_core", imx8mm_vpu_sels, base +
> 0x8100); diff --git a/drivers/clk/imx/clk-imx8mn.c
> b/drivers/clk/imx/clk-imx8mn.c index 6cac6ca03e12..bd3759b4afd0 100644
> --- a/drivers/clk/imx/clk-imx8mn.c
> +++ b/drivers/clk/imx/clk-imx8mn.c
> @@ -413,9 +413,9 @@ static int imx8mn_clocks_probe(struct platform_device
> *pdev)
>  	}
> 
>  	/* CORE */
> -	hws[IMX8MN_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base +
> 0x8000, 24, 3, imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels));
> -	hws[IMX8MN_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg",
> "arm_a53_src", base + 0x8000, 28);
> -	hws[IMX8MN_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div",
> "arm_a53_cg", base + 0x8000, 0, 3);
> +	hws[IMX8MN_CLK_A53_DIV] =
> imx8m_clk_hw_composite_core("arm_a53_div", imx8mn_a53_sels, base +
> 0x8000);
> +	hws[IMX8MN_CLK_A53_SRC] = hws[IMX8MN_CLK_A53_DIV];
> +	hws[IMX8MN_CLK_A53_CG] = hws[IMX8MN_CLK_A53_DIV];
> 
>  	hws[IMX8MN_CLK_GPU_CORE] =
> imx8m_clk_hw_composite_core("gpu_core", imx8mn_gpu_core_sels, base +
> 0x8180);
>  	hws[IMX8MN_CLK_GPU_SHADER] =
> imx8m_clk_hw_composite_core("gpu_shader", imx8mn_gpu_shader_sels, base
> + 0x8200); diff --git a/drivers/clk/imx/clk-imx8mq.c
> b/drivers/clk/imx/clk-imx8mq.c index 201c7bbb201f..91309ff65441 100644
> --- a/drivers/clk/imx/clk-imx8mq.c
> +++ b/drivers/clk/imx/clk-imx8mq.c
> @@ -405,9 +405,9 @@ static int imx8mq_clocks_probe(struct platform_device
> *pdev)
>  		return PTR_ERR(base);
> 
>  	/* CORE */
> -	hws[IMX8MQ_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base +
> 0x8000, 24, 3, imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels));
> -	hws[IMX8MQ_CLK_A53_CG] = imx_clk_hw_gate3_flags("arm_a53_cg",
> "arm_a53_src", base + 0x8000, 28, CLK_IS_CRITICAL);
> -	hws[IMX8MQ_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div",
> "arm_a53_cg", base + 0x8000, 0, 3);
> +	hws[IMX8MQ_CLK_A53_DIV] =
> imx8m_clk_hw_composite_core("arm_a53_div", imx8mq_a53_sels, base +
> 0x8000);
> +	hws[IMX8MQ_CLK_A53_CG] = hws[IMX8MQ_CLK_A53_DIV];
> +	hws[IMX8MQ_CLK_A53_SRC] = hws[IMX8MQ_CLK_A53_DIV];
> 
>  	hws[IMX8MQ_CLK_M4_CORE] =
> imx8m_clk_hw_composite_core("arm_m4_core", imx8mq_arm_m4_sels, base
> + 0x8080);
>  	hws[IMX8MQ_CLK_VPU_CORE] =
> imx8m_clk_hw_composite_core("vpu_core", imx8mq_vpu_sels, base +
> 0x8100);
> --
> 2.16.4

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RE: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk

[Aisheng Dong]

> From: Peng Fan <peng.fan@nxp.com>
> Sent: Thursday, March 12, 2020 6:20 PM
> 
> The CORE/BUS root slice has following design, simplied graph:
> The difference is core not have pre_div block.
> A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7].
> 
>             SEL_A  GA
>             +--+  +-+
>             |  +->+ +------+
> CLK[0-7]--->+  |  +-+      |
>        |    |  |      +----v---+    +----+
>        |    +--+      |pre_diva+---->    |  +---------+
>        |              +--------+    |mux +--+post_div |
>        |    +--+      |pre_divb+--->+    |  +---------+
>        |    |  |      +----^---+    +----+
>        +--->+  |  +-+      |
>             |  +->+ +------+
>             +--+  +-+
>             SEL_B  GB
> 
> There will be system hang, when doing the following steps:
> 1. switch mux from clk0 to clk1
> 2. gate off clk0
> 3. swtich from clk1 to clk2, or gate off clk1
> 
> Step 3 triggers system hang.

Why Step 3 triggers system hang? Is this a HW limitation?

> 
> If we skip step2, keep clk0 on, step 3 will not trigger system hang.
> However we have CLK_OPS_PARENT_ENABLE flag, which will unprepare disable
> the clk0 which will not be used.
> 
> To address this issue, we could use following simplied software flow:
> After the first target register set
> wait the target register set finished
> set the target register set again
> wait the target register set finished
> 
> The upper flow will make sure SEL_A and SEL_B both set the new mux, but with
> only one path gate on.
> 
> And there will be no system hang anymore with step3.

Is this IC proposed solution?

> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> 
> V2:
>  Drop wait after write, add one line comment for write twice.
> 
>  drivers/clk/imx/clk-composite-8m.c | 62
> +++++++++++++++++++++++++++++++++++++-
>  1 file changed, 61 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/imx/clk-composite-8m.c
> b/drivers/clk/imx/clk-composite-8m.c
> index 99773519b5a5..eae02c151ced 100644
> --- a/drivers/clk/imx/clk-composite-8m.c
> +++ b/drivers/clk/imx/clk-composite-8m.c
> @@ -24,6 +24,12 @@
> 
>  #define PCG_CGC_SHIFT		28
> 
> +#define PRE_REG_OFF		0x30
> +#define PRE_MUXA_SHIFT		24
> +#define PRE_MUXA_MASK		0x7
> +#define PRE_MUXB_SHIFT		8
> +#define PRE_MUXB_MASK		0x7

Are those macros used somewhere?

> +
>  static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk_hw
> *hw,
>  						unsigned long parent_rate)
>  {
> @@ -124,6 +130,57 @@ static const struct clk_ops
> imx8m_clk_composite_divider_ops = {
>  	.set_rate = imx8m_clk_composite_divider_set_rate,
>  };
> 
> +static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw) {
> +	struct clk_mux *mux = to_clk_mux(hw);
> +	u32 val;
> +
> +	val = readl(mux->reg) >> mux->shift;
> +	val &= mux->mask;
> +
> +	return clk_mux_val_to_index(hw, mux->table, mux->flags, val); }

You don't have to redefinition them if they're the same as clk_mux_ops.
You have the access to clk_mux_ops.

> +
> +static int imx8m_clk_composite_mux_set_parent(struct clk_hw *hw, u8
> +index) {
> +	struct clk_mux *mux = to_clk_mux(hw);
> +	u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
> +	unsigned long flags = 0;
> +	u32 reg;
> +
> +	if (mux->lock)
> +		spin_lock_irqsave(mux->lock, flags);
> +
> +	reg = readl(mux->reg);
> +	reg &= ~(mux->mask << mux->shift);
> +	val = val << mux->shift;
> +	reg |= val;
> +	/* write twice to make sure SEL_A/B point the same mux */
> +	writel(reg, mux->reg);
> +	writel(reg, mux->reg);

Why this affects both SEL_A/B?
Very tricky and may worth more comments.

Besides that, I'd like to see Abel's comments on this patch.

Regards
Aisheng

> +
> +	if (mux->lock)
> +		spin_unlock_irqrestore(mux->lock, flags);
> +
> +	return 0;
> +}
> +
> +static int
> +imx8m_clk_composite_mux_determine_rate(struct clk_hw *hw,
> +				       struct clk_rate_request *req) {
> +	struct clk_mux *mux = to_clk_mux(hw);
> +
> +	return clk_mux_determine_rate_flags(hw, req, mux->flags); }

Same as bove.

> +
> +
> +const struct clk_ops imx8m_clk_composite_mux_ops = {
> +	.get_parent = imx8m_clk_composite_mux_get_parent,
> +	.set_parent = imx8m_clk_composite_mux_set_parent,
> +	.determine_rate = imx8m_clk_composite_mux_determine_rate,
> +};
> +
>  struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
>  					const char * const *parent_names,
>  					int num_parents, void __iomem *reg, @@ -136,6
> +193,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
>  	struct clk_gate *gate = NULL;
>  	struct clk_mux *mux = NULL;
>  	const struct clk_ops *divider_ops;
> +	const struct clk_ops *mux_ops;
> 
>  	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
>  	if (!mux)
> @@ -157,10 +215,12 @@ struct clk_hw
> *imx8m_clk_hw_composite_flags(const char *name,
>  		div->shift = PCG_DIV_SHIFT;
>  		div->width = PCG_CORE_DIV_WIDTH;
>  		divider_ops = &clk_divider_ops;
> +		mux_ops = &imx8m_clk_composite_mux_ops;
>  	} else {
>  		div->shift = PCG_PREDIV_SHIFT;
>  		div->width = PCG_PREDIV_WIDTH;
>  		divider_ops = &imx8m_clk_composite_divider_ops;
> +		mux_ops = &clk_mux_ops;
>  	}
> 
>  	div->lock = &imx_ccm_lock;
> @@ -176,7 +236,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const
> char *name,
>  	gate->lock = &imx_ccm_lock;
> 
>  	hw = clk_hw_register_composite(NULL, name, parent_names,
> num_parents,
> -			mux_hw, &clk_mux_ops, div_hw,
> +			mux_hw, mux_ops, div_hw,
>  			divider_ops, gate_hw, &clk_gate_ops, flags);
>  	if (IS_ERR(hw))
>  		goto fail;
> --
> 2.16.4

RE: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk

[Aisheng Dong]

> From: Peng Fan <peng.fan@nxp.com>
> Sent: Thursday, March 12, 2020 6:20 PM
> 
> The CORE/BUS root slice has following design, simplied graph:
> The difference is core not have pre_div block.
> A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7].
> 
>             SEL_A  GA
>             +--+  +-+
>             |  +->+ +------+
> CLK[0-7]--->+  |  +-+      |
>        |    |  |      +----v---+    +----+
>        |    +--+      |pre_diva+---->    |  +---------+
>        |              +--------+    |mux +--+post_div |
>        |    +--+      |pre_divb+--->+    |  +---------+
>        |    |  |      +----^---+    +----+
>        +--->+  |  +-+      |
>             |  +->+ +------+
>             +--+  +-+
>             SEL_B  GB
> 
> There will be system hang, when doing the following steps:
> 1. switch mux from clk0 to clk1
> 2. gate off clk0
> 3. swtich from clk1 to clk2, or gate off clk1
> 
> Step 3 triggers system hang.

Why Step 3 triggers system hang? Is this a HW limitation?

> 
> If we skip step2, keep clk0 on, step 3 will not trigger system hang.
> However we have CLK_OPS_PARENT_ENABLE flag, which will unprepare disable
> the clk0 which will not be used.
> 
> To address this issue, we could use following simplied software flow:
> After the first target register set
> wait the target register set finished
> set the target register set again
> wait the target register set finished
> 
> The upper flow will make sure SEL_A and SEL_B both set the new mux, but with
> only one path gate on.
> 
> And there will be no system hang anymore with step3.

Is this IC proposed solution?

> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> 
> V2:
>  Drop wait after write, add one line comment for write twice.
> 
>  drivers/clk/imx/clk-composite-8m.c | 62
> +++++++++++++++++++++++++++++++++++++-
>  1 file changed, 61 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/imx/clk-composite-8m.c
> b/drivers/clk/imx/clk-composite-8m.c
> index 99773519b5a5..eae02c151ced 100644
> --- a/drivers/clk/imx/clk-composite-8m.c
> +++ b/drivers/clk/imx/clk-composite-8m.c
> @@ -24,6 +24,12 @@
> 
>  #define PCG_CGC_SHIFT		28
> 
> +#define PRE_REG_OFF		0x30
> +#define PRE_MUXA_SHIFT		24
> +#define PRE_MUXA_MASK		0x7
> +#define PRE_MUXB_SHIFT		8
> +#define PRE_MUXB_MASK		0x7

Are those macros used somewhere?

> +
>  static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk_hw
> *hw,
>  						unsigned long parent_rate)
>  {
> @@ -124,6 +130,57 @@ static const struct clk_ops
> imx8m_clk_composite_divider_ops = {
>  	.set_rate = imx8m_clk_composite_divider_set_rate,
>  };
> 
> +static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw) {
> +	struct clk_mux *mux = to_clk_mux(hw);
> +	u32 val;
> +
> +	val = readl(mux->reg) >> mux->shift;
> +	val &= mux->mask;
> +
> +	return clk_mux_val_to_index(hw, mux->table, mux->flags, val); }

You don't have to redefinition them if they're the same as clk_mux_ops.
You have the access to clk_mux_ops.

> +
> +static int imx8m_clk_composite_mux_set_parent(struct clk_hw *hw, u8
> +index) {
> +	struct clk_mux *mux = to_clk_mux(hw);
> +	u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
> +	unsigned long flags = 0;
> +	u32 reg;
> +
> +	if (mux->lock)
> +		spin_lock_irqsave(mux->lock, flags);
> +
> +	reg = readl(mux->reg);
> +	reg &= ~(mux->mask << mux->shift);
> +	val = val << mux->shift;
> +	reg |= val;
> +	/* write twice to make sure SEL_A/B point the same mux */
> +	writel(reg, mux->reg);
> +	writel(reg, mux->reg);

Why this affects both SEL_A/B?
Very tricky and may worth more comments.

Besides that, I'd like to see Abel's comments on this patch.

Regards
Aisheng

> +
> +	if (mux->lock)
> +		spin_unlock_irqrestore(mux->lock, flags);
> +
> +	return 0;
> +}
> +
> +static int
> +imx8m_clk_composite_mux_determine_rate(struct clk_hw *hw,
> +				       struct clk_rate_request *req) {
> +	struct clk_mux *mux = to_clk_mux(hw);
> +
> +	return clk_mux_determine_rate_flags(hw, req, mux->flags); }

Same as bove.

> +
> +
> +const struct clk_ops imx8m_clk_composite_mux_ops = {
> +	.get_parent = imx8m_clk_composite_mux_get_parent,
> +	.set_parent = imx8m_clk_composite_mux_set_parent,
> +	.determine_rate = imx8m_clk_composite_mux_determine_rate,
> +};
> +
>  struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
>  					const char * const *parent_names,
>  					int num_parents, void __iomem *reg, @@ -136,6
> +193,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
>  	struct clk_gate *gate = NULL;
>  	struct clk_mux *mux = NULL;
>  	const struct clk_ops *divider_ops;
> +	const struct clk_ops *mux_ops;
> 
>  	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
>  	if (!mux)
> @@ -157,10 +215,12 @@ struct clk_hw
> *imx8m_clk_hw_composite_flags(const char *name,
>  		div->shift = PCG_DIV_SHIFT;
>  		div->width = PCG_CORE_DIV_WIDTH;
>  		divider_ops = &clk_divider_ops;
> +		mux_ops = &imx8m_clk_composite_mux_ops;
>  	} else {
>  		div->shift = PCG_PREDIV_SHIFT;
>  		div->width = PCG_PREDIV_WIDTH;
>  		divider_ops = &imx8m_clk_composite_divider_ops;
> +		mux_ops = &clk_mux_ops;
>  	}
> 
>  	div->lock = &imx_ccm_lock;
> @@ -176,7 +236,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const
> char *name,
>  	gate->lock = &imx_ccm_lock;
> 
>  	hw = clk_hw_register_composite(NULL, name, parent_names,
> num_parents,
> -			mux_hw, &clk_mux_ops, div_hw,
> +			mux_hw, mux_ops, div_hw,
>  			divider_ops, gate_hw, &clk_gate_ops, flags);
>  	if (IS_ERR(hw))
>  		goto fail;
> --
> 2.16.4

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RE: [PATCH V2 05/10] clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code

[Peng Fan]

> Subject: RE: [PATCH V2 05/10] clk: imx8mp: use
> imx8m_clk_hw_composite_core to simplify code
> 
> > From: Peng Fan <peng.fan@nxp.com>
> > Sent: Thursday, March 12, 2020 6:20 PM
> >
> > Use imx8m_clk_hw_composite_core to simpliy clks that belong to core clk
> slice.
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> 
> Should we also deprecated the old clock ids which will not be supported by
> driver anymore?

To keep dt backward compatible, those ids are kept as what we did for other
i.MX8M platform.

Thanks,
Peng.

> Otherwise:
> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
> 
> Regards
> Aisheng
> 
> > ---
> >  drivers/clk/imx/clk-imx8mp.c             | 47
> > +++++++++++---------------------
> >  include/dt-bindings/clock/imx8mp-clock.h | 11 +++++++-
> >  2 files changed, 26 insertions(+), 32 deletions(-)
> >
> > diff --git a/drivers/clk/imx/clk-imx8mp.c
> > b/drivers/clk/imx/clk-imx8mp.c index
> > a7613c7355c8..998e9e63f831 100644
> > --- a/drivers/clk/imx/clk-imx8mp.c
> > +++ b/drivers/clk/imx/clk-imx8mp.c
> > @@ -546,33 +546,18 @@ static int imx8mp_clocks_probe(struct
> > platform_device *pdev)
> >  	hws[IMX8MP_SYS_PLL2_500M] =
> > imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
> >  	hws[IMX8MP_SYS_PLL2_1000M] =
> > imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
> >
> > -	hws[IMX8MP_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src",
> > ccm_base + 0x8000, 24, 3, imx8mp_a53_sels,
> ARRAY_SIZE(imx8mp_a53_sels));
> > -	hws[IMX8MP_CLK_M7_SRC] = imx_clk_hw_mux2("arm_m7_src",
> > ccm_base + 0x8080, 24, 3, imx8mp_m7_sels,
> ARRAY_SIZE(imx8mp_m7_sels));
> > -	hws[IMX8MP_CLK_ML_SRC] = imx_clk_hw_mux2("ml_src", ccm_base +
> > 0x8100, 24, 3, imx8mp_ml_sels, ARRAY_SIZE(imx8mp_ml_sels));
> > -	hws[IMX8MP_CLK_GPU3D_CORE_SRC] =
> > imx_clk_hw_mux2("gpu3d_core_src", ccm_base + 0x8180, 24, 3,
> > imx8mp_gpu3d_core_sels, ARRAY_SIZE(imx8mp_gpu3d_core_sels));
> > -	hws[IMX8MP_CLK_GPU3D_SHADER_SRC] =
> > imx_clk_hw_mux2("gpu3d_shader_src", ccm_base + 0x8200, 24, 3,
> > imx8mp_gpu3d_shader_sels, ARRAY_SIZE(imx8mp_gpu3d_shader_sels));
> > -	hws[IMX8MP_CLK_GPU2D_SRC] = imx_clk_hw_mux2("gpu2d_src",
> > ccm_base + 0x8280, 24, 3, imx8mp_gpu2d_sels,
> > ARRAY_SIZE(imx8mp_gpu2d_sels));
> > -	hws[IMX8MP_CLK_AUDIO_AXI_SRC] =
> imx_clk_hw_mux2("audio_axi_src",
> > ccm_base + 0x8300, 24, 3, imx8mp_audio_axi_sels,
> > ARRAY_SIZE(imx8mp_audio_axi_sels));
> > -	hws[IMX8MP_CLK_HSIO_AXI_SRC] = imx_clk_hw_mux2("hsio_axi_src",
> > ccm_base + 0x8380, 24, 3, imx8mp_hsio_axi_sels,
> > ARRAY_SIZE(imx8mp_hsio_axi_sels));
> > -	hws[IMX8MP_CLK_MEDIA_ISP_SRC] =
> imx_clk_hw_mux2("media_isp_src",
> > ccm_base + 0x8400, 24, 3, imx8mp_media_isp_sels,
> > ARRAY_SIZE(imx8mp_media_isp_sels));
> > -	hws[IMX8MP_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg",
> > "arm_a53_src", ccm_base + 0x8000, 28);
> > -	hws[IMX8MP_CLK_M4_CG] = imx_clk_hw_gate3("arm_m7_cg",
> > "arm_m7_src", ccm_base + 0x8080, 28);
> > -	hws[IMX8MP_CLK_ML_CG] = imx_clk_hw_gate3("ml_cg", "ml_src",
> > ccm_base + 0x8100, 28);
> > -	hws[IMX8MP_CLK_GPU3D_CORE_CG] =
> > imx_clk_hw_gate3("gpu3d_core_cg", "gpu3d_core_src", ccm_base +
> 0x8180,
> > 28);
> > -	hws[IMX8MP_CLK_GPU3D_SHADER_CG] =
> > imx_clk_hw_gate3("gpu3d_shader_cg", "gpu3d_shader_src", ccm_base +
> > 0x8200, 28);
> > -	hws[IMX8MP_CLK_GPU2D_CG] = imx_clk_hw_gate3("gpu2d_cg",
> > "gpu2d_src", ccm_base + 0x8280, 28);
> > -	hws[IMX8MP_CLK_AUDIO_AXI_CG] =
> imx_clk_hw_gate3("audio_axi_cg",
> > "audio_axi_src", ccm_base + 0x8300, 28);
> > -	hws[IMX8MP_CLK_HSIO_AXI_CG] = imx_clk_hw_gate3("hsio_axi_cg",
> > "hsio_axi_src", ccm_base + 0x8380, 28);
> > -	hws[IMX8MP_CLK_MEDIA_ISP_CG] =
> imx_clk_hw_gate3("media_isp_cg",
> > "media_isp_src", ccm_base + 0x8400, 28);
> > -	hws[IMX8MP_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div",
> > "arm_a53_cg", ccm_base + 0x8000, 0, 3);
> > -	hws[IMX8MP_CLK_M7_DIV] = imx_clk_hw_divider2("arm_m7_div",
> > "arm_m7_cg", ccm_base + 0x8080, 0, 3);
> > -	hws[IMX8MP_CLK_ML_DIV] = imx_clk_hw_divider2("ml_div", "ml_cg",
> > ccm_base + 0x8100, 0, 3);
> > -	hws[IMX8MP_CLK_GPU3D_CORE_DIV] =
> > imx_clk_hw_divider2("gpu3d_core_div", "gpu3d_core_cg", ccm_base +
> > 0x8180, 0, 3);
> > -	hws[IMX8MP_CLK_GPU3D_SHADER_DIV] =
> > imx_clk_hw_divider2("gpu3d_shader_div", "gpu3d_shader_cg", ccm_base +
> > 0x8200, 0, 3);
> > -	hws[IMX8MP_CLK_GPU2D_DIV] = imx_clk_hw_divider2("gpu2d_div",
> > "gpu2d_cg", ccm_base + 0x8280, 0, 3);
> > -	hws[IMX8MP_CLK_AUDIO_AXI_DIV] =
> > imx_clk_hw_divider2("audio_axi_div", "audio_axi_cg", ccm_base +
> > 0x8300, 0, 3);
> > -	hws[IMX8MP_CLK_HSIO_AXI_DIV] =
> imx_clk_hw_divider2("hsio_axi_div",
> > "hsio_axi_cg", ccm_base + 0x8380, 0, 3);
> > -	hws[IMX8MP_CLK_MEDIA_ISP_DIV] =
> > imx_clk_hw_divider2("media_isp_div", "media_isp_cg", ccm_base +
> > 0x8400, 0, 3);
> > +	hws[IMX8MP_CLK_A53_DIV] =
> > imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels,
> ccm_base
> > + 0x8000);
> > +	hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV];
> > +	hws[IMX8MP_CLK_A53_CG] = hws[IMX8MP_CLK_A53_DIV];
> > +	hws[IMX8MP_CLK_M7_CORE] =
> > imx8m_clk_hw_composite_core("m7_core", imx8mp_m7_sels, ccm_base +
> > 0x8080);
> > +	hws[IMX8MP_CLK_ML_CORE] =
> > imx8m_clk_hw_composite_core("ml_core", imx8mp_ml_sels, ccm_base +
> > 0x8100);
> > +	hws[IMX8MP_CLK_GPU3D_CORE] =
> > imx8m_clk_hw_composite_core("gpu3d_core", imx8mp_gpu3d_core_sels,
> > ccm_base + 0x8180);
> > +	hws[IMX8MP_CLK_GPU3D_SHADER_CORE] =
> > imx8m_clk_hw_composite("gpu3d_shader_core",
> imx8mp_gpu3d_shader_sels,
> > ccm_base + 0x8200);
> > +	hws[IMX8MP_CLK_GPU2D_CORE] =
> > imx8m_clk_hw_composite("gpu2d_core", imx8mp_gpu2d_sels, ccm_base +
> > 0x8280);
> > +	hws[IMX8MP_CLK_AUDIO_AXI] =
> imx8m_clk_hw_composite("audio_axi",
> > imx8mp_audio_axi_sels, ccm_base + 0x8300);
> > +	hws[IMX8MP_CLK_AUDIO_AXI_SRC] = hws[IMX8MP_CLK_AUDIO_AXI];
> > +	hws[IMX8MP_CLK_HSIO_AXI] = imx8m_clk_hw_composite("hsio_axi",
> > imx8mp_hsio_axi_sels, ccm_base + 0x8380);
> > +	hws[IMX8MP_CLK_MEDIA_ISP] =
> imx8m_clk_hw_composite("media_isp",
> > +imx8mp_media_isp_sels, ccm_base + 0x8400);
> >
> >  	/* CORE SEL */
> >  	hws[IMX8MP_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core",
> ccm_base
> > + 0x9880, 24, 1, imx8mp_a53_core_sels,
> > ARRAY_SIZE(imx8mp_a53_core_sels));
> > @@ -713,8 +698,8 @@ static int imx8mp_clocks_probe(struct
> > platform_device
> > *pdev)
> >  	hws[IMX8MP_CLK_SDMA1_ROOT] =
> imx_clk_hw_gate4("sdma1_root_clk",
> > "ipg_root", ccm_base + 0x43a0, 0);
> >  	hws[IMX8MP_CLK_ENET_QOS_ROOT] =
> > imx_clk_hw_gate4("enet_qos_root_clk", "sim_enet_root_clk", ccm_base +
> > 0x43b0, 0);
> >  	hws[IMX8MP_CLK_SIM_ENET_ROOT] =
> > imx_clk_hw_gate4("sim_enet_root_clk", "enet_axi", ccm_base + 0x4400,
> 0);
> > -	hws[IMX8MP_CLK_GPU2D_ROOT] =
> imx_clk_hw_gate4("gpu2d_root_clk",
> > "gpu2d_div", ccm_base + 0x4450, 0);
> > -	hws[IMX8MP_CLK_GPU3D_ROOT] =
> imx_clk_hw_gate4("gpu3d_root_clk",
> > "gpu3d_core_div", ccm_base + 0x4460, 0);
> > +	hws[IMX8MP_CLK_GPU2D_ROOT] =
> imx_clk_hw_gate4("gpu2d_root_clk",
> > "gpu2d_core", ccm_base + 0x4450, 0);
> > +	hws[IMX8MP_CLK_GPU3D_ROOT] =
> imx_clk_hw_gate4("gpu3d_root_clk",
> > +"gpu3d_core", ccm_base + 0x4460, 0);
> >  	hws[IMX8MP_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk",
> > "ipg_root", ccm_base + 0x4470, 0);
> >  	hws[IMX8MP_CLK_UART1_ROOT] =
> imx_clk_hw_gate4("uart1_root_clk",
> > "uart1", ccm_base + 0x4490, 0);
> >  	hws[IMX8MP_CLK_UART2_ROOT] =
> imx_clk_hw_gate4("uart2_root_clk",
> > "uart2", ccm_base + 0x44a0, 0); @@ -731,7 +716,7 @@ static int
> > imx8mp_clocks_probe(struct platform_device *pdev)
> >  	hws[IMX8MP_CLK_GPU_ROOT] = imx_clk_hw_gate4("gpu_root_clk",
> > "gpu_axi", ccm_base + 0x4570, 0);
> >  	hws[IMX8MP_CLK_VPU_VC8KE_ROOT] =
> > imx_clk_hw_gate4("vpu_vc8ke_root_clk", "vpu_vc8000e", ccm_base +
> > 0x4590, 0);
> >  	hws[IMX8MP_CLK_VPU_G2_ROOT] =
> > imx_clk_hw_gate4("vpu_g2_root_clk", "vpu_g2", ccm_base + 0x45a0, 0);
> > -	hws[IMX8MP_CLK_NPU_ROOT] = imx_clk_hw_gate4("npu_root_clk",
> > "ml_div", ccm_base + 0x45b0, 0);
> > +	hws[IMX8MP_CLK_NPU_ROOT] = imx_clk_hw_gate4("npu_root_clk",
> > "ml_core",
> > +ccm_base + 0x45b0, 0);
> >  	hws[IMX8MP_CLK_HSIO_ROOT] = imx_clk_hw_gate4("hsio_root_clk",
> > "ipg_root", ccm_base + 0x45c0, 0);
> >  	hws[IMX8MP_CLK_MEDIA_APB_ROOT] =
> > imx_clk_hw_gate2_shared2("media_apb_root_clk", "media_apb",
> ccm_base +
> > 0x45d0, 0, &share_count_media);
> >  	hws[IMX8MP_CLK_MEDIA_AXI_ROOT] =
> > imx_clk_hw_gate2_shared2("media_axi_root_clk", "media_axi", ccm_base
> +
> > 0x45d0, 0, &share_count_media); @@ -739,7 +724,7 @@ static int
> > imx8mp_clocks_probe(struct platform_device *pdev)
> >  	hws[IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT] =
> > imx_clk_hw_gate2_shared2("media_cam2_pix_root_clk",
> "media_cam2_pix",
> > ccm_base + 0x45d0, 0, &share_count_media);
> >  	hws[IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT] =
> > imx_clk_hw_gate2_shared2("media_disp1_pix_root_clk",
> > "media_disp1_pix", ccm_base + 0x45d0, 0, &share_count_media);
> >  	hws[IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT] =
> > imx_clk_hw_gate2_shared2("media_disp2_pix_root_clk",
> > "media_disp2_pix", ccm_base + 0x45d0, 0, &share_count_media);
> > -	hws[IMX8MP_CLK_MEDIA_ISP_ROOT] =
> > imx_clk_hw_gate2_shared2("media_isp_root_clk", "media_isp_div",
> > ccm_base
> > + 0x45d0, 0, &share_count_media);
> > +	hws[IMX8MP_CLK_MEDIA_ISP_ROOT] =
> > +imx_clk_hw_gate2_shared2("media_isp_root_clk", "media_isp",
> ccm_base
> > ++ 0x45d0, 0, &share_count_media);
> >
> >  	hws[IMX8MP_CLK_USDHC3_ROOT] =
> > imx_clk_hw_gate4("usdhc3_root_clk", "usdhc3", ccm_base + 0x45e0, 0);
> >  	hws[IMX8MP_CLK_HDMI_ROOT] = imx_clk_hw_gate4("hdmi_root_clk",
> > "hdmi_axi", ccm_base + 0x45f0, 0); diff --git
> > a/include/dt-bindings/clock/imx8mp-clock.h
> > b/include/dt-bindings/clock/imx8mp-clock.h
> > index 46c69cd66c62..8430bc4fd182 100644
> > --- a/include/dt-bindings/clock/imx8mp-clock.h
> > +++ b/include/dt-bindings/clock/imx8mp-clock.h
> > @@ -313,6 +313,15 @@
> >  #define IMX8MP_SYS_PLL2_333M_CG			303
> >  #define IMX8MP_SYS_PLL2_500M_CG			304
> >
> > -#define IMX8MP_CLK_END				305
> > +#define IMX8MP_CLK_M7_CORE			305
> > +#define IMX8MP_CLK_ML_CORE			306
> > +#define IMX8MP_CLK_GPU3D_CORE			307
> > +#define IMX8MP_CLK_GPU3D_SHADER_CORE		308
> > +#define IMX8MP_CLK_GPU2D_CORE			309
> > +#define IMX8MP_CLK_AUDIO_AXI			310
> > +#define IMX8MP_CLK_HSIO_AXI			311
> > +#define IMX8MP_CLK_MEDIA_ISP			312
> > +
> > +#define IMX8MP_CLK_END				313
> >
> >  #endif
> > --
> > 2.16.4

RE: [PATCH V2 05/10] clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code

[Peng Fan]

> Subject: RE: [PATCH V2 05/10] clk: imx8mp: use
> imx8m_clk_hw_composite_core to simplify code
> 
> > From: Peng Fan <peng.fan@nxp.com>
> > Sent: Thursday, March 12, 2020 6:20 PM
> >
> > Use imx8m_clk_hw_composite_core to simpliy clks that belong to core clk
> slice.
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> 
> Should we also deprecated the old clock ids which will not be supported by
> driver anymore?

To keep dt backward compatible, those ids are kept as what we did for other
i.MX8M platform.

Thanks,
Peng.

> Otherwise:
> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
> 
> Regards
> Aisheng
> 
> > ---
> >  drivers/clk/imx/clk-imx8mp.c             | 47
> > +++++++++++---------------------
> >  include/dt-bindings/clock/imx8mp-clock.h | 11 +++++++-
> >  2 files changed, 26 insertions(+), 32 deletions(-)
> >
> > diff --git a/drivers/clk/imx/clk-imx8mp.c
> > b/drivers/clk/imx/clk-imx8mp.c index
> > a7613c7355c8..998e9e63f831 100644
> > --- a/drivers/clk/imx/clk-imx8mp.c
> > +++ b/drivers/clk/imx/clk-imx8mp.c
> > @@ -546,33 +546,18 @@ static int imx8mp_clocks_probe(struct
> > platform_device *pdev)
> >  	hws[IMX8MP_SYS_PLL2_500M] =
> > imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
> >  	hws[IMX8MP_SYS_PLL2_1000M] =
> > imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
> >
> > -	hws[IMX8MP_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src",
> > ccm_base + 0x8000, 24, 3, imx8mp_a53_sels,
> ARRAY_SIZE(imx8mp_a53_sels));
> > -	hws[IMX8MP_CLK_M7_SRC] = imx_clk_hw_mux2("arm_m7_src",
> > ccm_base + 0x8080, 24, 3, imx8mp_m7_sels,
> ARRAY_SIZE(imx8mp_m7_sels));
> > -	hws[IMX8MP_CLK_ML_SRC] = imx_clk_hw_mux2("ml_src", ccm_base +
> > 0x8100, 24, 3, imx8mp_ml_sels, ARRAY_SIZE(imx8mp_ml_sels));
> > -	hws[IMX8MP_CLK_GPU3D_CORE_SRC] =
> > imx_clk_hw_mux2("gpu3d_core_src", ccm_base + 0x8180, 24, 3,
> > imx8mp_gpu3d_core_sels, ARRAY_SIZE(imx8mp_gpu3d_core_sels));
> > -	hws[IMX8MP_CLK_GPU3D_SHADER_SRC] =
> > imx_clk_hw_mux2("gpu3d_shader_src", ccm_base + 0x8200, 24, 3,
> > imx8mp_gpu3d_shader_sels, ARRAY_SIZE(imx8mp_gpu3d_shader_sels));
> > -	hws[IMX8MP_CLK_GPU2D_SRC] = imx_clk_hw_mux2("gpu2d_src",
> > ccm_base + 0x8280, 24, 3, imx8mp_gpu2d_sels,
> > ARRAY_SIZE(imx8mp_gpu2d_sels));
> > -	hws[IMX8MP_CLK_AUDIO_AXI_SRC] =
> imx_clk_hw_mux2("audio_axi_src",
> > ccm_base + 0x8300, 24, 3, imx8mp_audio_axi_sels,
> > ARRAY_SIZE(imx8mp_audio_axi_sels));
> > -	hws[IMX8MP_CLK_HSIO_AXI_SRC] = imx_clk_hw_mux2("hsio_axi_src",
> > ccm_base + 0x8380, 24, 3, imx8mp_hsio_axi_sels,
> > ARRAY_SIZE(imx8mp_hsio_axi_sels));
> > -	hws[IMX8MP_CLK_MEDIA_ISP_SRC] =
> imx_clk_hw_mux2("media_isp_src",
> > ccm_base + 0x8400, 24, 3, imx8mp_media_isp_sels,
> > ARRAY_SIZE(imx8mp_media_isp_sels));
> > -	hws[IMX8MP_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg",
> > "arm_a53_src", ccm_base + 0x8000, 28);
> > -	hws[IMX8MP_CLK_M4_CG] = imx_clk_hw_gate3("arm_m7_cg",
> > "arm_m7_src", ccm_base + 0x8080, 28);
> > -	hws[IMX8MP_CLK_ML_CG] = imx_clk_hw_gate3("ml_cg", "ml_src",
> > ccm_base + 0x8100, 28);
> > -	hws[IMX8MP_CLK_GPU3D_CORE_CG] =
> > imx_clk_hw_gate3("gpu3d_core_cg", "gpu3d_core_src", ccm_base +
> 0x8180,
> > 28);
> > -	hws[IMX8MP_CLK_GPU3D_SHADER_CG] =
> > imx_clk_hw_gate3("gpu3d_shader_cg", "gpu3d_shader_src", ccm_base +
> > 0x8200, 28);
> > -	hws[IMX8MP_CLK_GPU2D_CG] = imx_clk_hw_gate3("gpu2d_cg",
> > "gpu2d_src", ccm_base + 0x8280, 28);
> > -	hws[IMX8MP_CLK_AUDIO_AXI_CG] =
> imx_clk_hw_gate3("audio_axi_cg",
> > "audio_axi_src", ccm_base + 0x8300, 28);
> > -	hws[IMX8MP_CLK_HSIO_AXI_CG] = imx_clk_hw_gate3("hsio_axi_cg",
> > "hsio_axi_src", ccm_base + 0x8380, 28);
> > -	hws[IMX8MP_CLK_MEDIA_ISP_CG] =
> imx_clk_hw_gate3("media_isp_cg",
> > "media_isp_src", ccm_base + 0x8400, 28);
> > -	hws[IMX8MP_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div",
> > "arm_a53_cg", ccm_base + 0x8000, 0, 3);
> > -	hws[IMX8MP_CLK_M7_DIV] = imx_clk_hw_divider2("arm_m7_div",
> > "arm_m7_cg", ccm_base + 0x8080, 0, 3);
> > -	hws[IMX8MP_CLK_ML_DIV] = imx_clk_hw_divider2("ml_div", "ml_cg",
> > ccm_base + 0x8100, 0, 3);
> > -	hws[IMX8MP_CLK_GPU3D_CORE_DIV] =
> > imx_clk_hw_divider2("gpu3d_core_div", "gpu3d_core_cg", ccm_base +
> > 0x8180, 0, 3);
> > -	hws[IMX8MP_CLK_GPU3D_SHADER_DIV] =
> > imx_clk_hw_divider2("gpu3d_shader_div", "gpu3d_shader_cg", ccm_base +
> > 0x8200, 0, 3);
> > -	hws[IMX8MP_CLK_GPU2D_DIV] = imx_clk_hw_divider2("gpu2d_div",
> > "gpu2d_cg", ccm_base + 0x8280, 0, 3);
> > -	hws[IMX8MP_CLK_AUDIO_AXI_DIV] =
> > imx_clk_hw_divider2("audio_axi_div", "audio_axi_cg", ccm_base +
> > 0x8300, 0, 3);
> > -	hws[IMX8MP_CLK_HSIO_AXI_DIV] =
> imx_clk_hw_divider2("hsio_axi_div",
> > "hsio_axi_cg", ccm_base + 0x8380, 0, 3);
> > -	hws[IMX8MP_CLK_MEDIA_ISP_DIV] =
> > imx_clk_hw_divider2("media_isp_div", "media_isp_cg", ccm_base +
> > 0x8400, 0, 3);
> > +	hws[IMX8MP_CLK_A53_DIV] =
> > imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels,
> ccm_base
> > + 0x8000);
> > +	hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV];
> > +	hws[IMX8MP_CLK_A53_CG] = hws[IMX8MP_CLK_A53_DIV];
> > +	hws[IMX8MP_CLK_M7_CORE] =
> > imx8m_clk_hw_composite_core("m7_core", imx8mp_m7_sels, ccm_base +
> > 0x8080);
> > +	hws[IMX8MP_CLK_ML_CORE] =
> > imx8m_clk_hw_composite_core("ml_core", imx8mp_ml_sels, ccm_base +
> > 0x8100);
> > +	hws[IMX8MP_CLK_GPU3D_CORE] =
> > imx8m_clk_hw_composite_core("gpu3d_core", imx8mp_gpu3d_core_sels,
> > ccm_base + 0x8180);
> > +	hws[IMX8MP_CLK_GPU3D_SHADER_CORE] =
> > imx8m_clk_hw_composite("gpu3d_shader_core",
> imx8mp_gpu3d_shader_sels,
> > ccm_base + 0x8200);
> > +	hws[IMX8MP_CLK_GPU2D_CORE] =
> > imx8m_clk_hw_composite("gpu2d_core", imx8mp_gpu2d_sels, ccm_base +
> > 0x8280);
> > +	hws[IMX8MP_CLK_AUDIO_AXI] =
> imx8m_clk_hw_composite("audio_axi",
> > imx8mp_audio_axi_sels, ccm_base + 0x8300);
> > +	hws[IMX8MP_CLK_AUDIO_AXI_SRC] = hws[IMX8MP_CLK_AUDIO_AXI];
> > +	hws[IMX8MP_CLK_HSIO_AXI] = imx8m_clk_hw_composite("hsio_axi",
> > imx8mp_hsio_axi_sels, ccm_base + 0x8380);
> > +	hws[IMX8MP_CLK_MEDIA_ISP] =
> imx8m_clk_hw_composite("media_isp",
> > +imx8mp_media_isp_sels, ccm_base + 0x8400);
> >
> >  	/* CORE SEL */
> >  	hws[IMX8MP_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core",
> ccm_base
> > + 0x9880, 24, 1, imx8mp_a53_core_sels,
> > ARRAY_SIZE(imx8mp_a53_core_sels));
> > @@ -713,8 +698,8 @@ static int imx8mp_clocks_probe(struct
> > platform_device
> > *pdev)
> >  	hws[IMX8MP_CLK_SDMA1_ROOT] =
> imx_clk_hw_gate4("sdma1_root_clk",
> > "ipg_root", ccm_base + 0x43a0, 0);
> >  	hws[IMX8MP_CLK_ENET_QOS_ROOT] =
> > imx_clk_hw_gate4("enet_qos_root_clk", "sim_enet_root_clk", ccm_base +
> > 0x43b0, 0);
> >  	hws[IMX8MP_CLK_SIM_ENET_ROOT] =
> > imx_clk_hw_gate4("sim_enet_root_clk", "enet_axi", ccm_base + 0x4400,
> 0);
> > -	hws[IMX8MP_CLK_GPU2D_ROOT] =
> imx_clk_hw_gate4("gpu2d_root_clk",
> > "gpu2d_div", ccm_base + 0x4450, 0);
> > -	hws[IMX8MP_CLK_GPU3D_ROOT] =
> imx_clk_hw_gate4("gpu3d_root_clk",
> > "gpu3d_core_div", ccm_base + 0x4460, 0);
> > +	hws[IMX8MP_CLK_GPU2D_ROOT] =
> imx_clk_hw_gate4("gpu2d_root_clk",
> > "gpu2d_core", ccm_base + 0x4450, 0);
> > +	hws[IMX8MP_CLK_GPU3D_ROOT] =
> imx_clk_hw_gate4("gpu3d_root_clk",
> > +"gpu3d_core", ccm_base + 0x4460, 0);
> >  	hws[IMX8MP_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk",
> > "ipg_root", ccm_base + 0x4470, 0);
> >  	hws[IMX8MP_CLK_UART1_ROOT] =
> imx_clk_hw_gate4("uart1_root_clk",
> > "uart1", ccm_base + 0x4490, 0);
> >  	hws[IMX8MP_CLK_UART2_ROOT] =
> imx_clk_hw_gate4("uart2_root_clk",
> > "uart2", ccm_base + 0x44a0, 0); @@ -731,7 +716,7 @@ static int
> > imx8mp_clocks_probe(struct platform_device *pdev)
> >  	hws[IMX8MP_CLK_GPU_ROOT] = imx_clk_hw_gate4("gpu_root_clk",
> > "gpu_axi", ccm_base + 0x4570, 0);
> >  	hws[IMX8MP_CLK_VPU_VC8KE_ROOT] =
> > imx_clk_hw_gate4("vpu_vc8ke_root_clk", "vpu_vc8000e", ccm_base +
> > 0x4590, 0);
> >  	hws[IMX8MP_CLK_VPU_G2_ROOT] =
> > imx_clk_hw_gate4("vpu_g2_root_clk", "vpu_g2", ccm_base + 0x45a0, 0);
> > -	hws[IMX8MP_CLK_NPU_ROOT] = imx_clk_hw_gate4("npu_root_clk",
> > "ml_div", ccm_base + 0x45b0, 0);
> > +	hws[IMX8MP_CLK_NPU_ROOT] = imx_clk_hw_gate4("npu_root_clk",
> > "ml_core",
> > +ccm_base + 0x45b0, 0);
> >  	hws[IMX8MP_CLK_HSIO_ROOT] = imx_clk_hw_gate4("hsio_root_clk",
> > "ipg_root", ccm_base + 0x45c0, 0);
> >  	hws[IMX8MP_CLK_MEDIA_APB_ROOT] =
> > imx_clk_hw_gate2_shared2("media_apb_root_clk", "media_apb",
> ccm_base +
> > 0x45d0, 0, &share_count_media);
> >  	hws[IMX8MP_CLK_MEDIA_AXI_ROOT] =
> > imx_clk_hw_gate2_shared2("media_axi_root_clk", "media_axi", ccm_base
> +
> > 0x45d0, 0, &share_count_media); @@ -739,7 +724,7 @@ static int
> > imx8mp_clocks_probe(struct platform_device *pdev)
> >  	hws[IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT] =
> > imx_clk_hw_gate2_shared2("media_cam2_pix_root_clk",
> "media_cam2_pix",
> > ccm_base + 0x45d0, 0, &share_count_media);
> >  	hws[IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT] =
> > imx_clk_hw_gate2_shared2("media_disp1_pix_root_clk",
> > "media_disp1_pix", ccm_base + 0x45d0, 0, &share_count_media);
> >  	hws[IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT] =
> > imx_clk_hw_gate2_shared2("media_disp2_pix_root_clk",
> > "media_disp2_pix", ccm_base + 0x45d0, 0, &share_count_media);
> > -	hws[IMX8MP_CLK_MEDIA_ISP_ROOT] =
> > imx_clk_hw_gate2_shared2("media_isp_root_clk", "media_isp_div",
> > ccm_base
> > + 0x45d0, 0, &share_count_media);
> > +	hws[IMX8MP_CLK_MEDIA_ISP_ROOT] =
> > +imx_clk_hw_gate2_shared2("media_isp_root_clk", "media_isp",
> ccm_base
> > ++ 0x45d0, 0, &share_count_media);
> >
> >  	hws[IMX8MP_CLK_USDHC3_ROOT] =
> > imx_clk_hw_gate4("usdhc3_root_clk", "usdhc3", ccm_base + 0x45e0, 0);
> >  	hws[IMX8MP_CLK_HDMI_ROOT] = imx_clk_hw_gate4("hdmi_root_clk",
> > "hdmi_axi", ccm_base + 0x45f0, 0); diff --git
> > a/include/dt-bindings/clock/imx8mp-clock.h
> > b/include/dt-bindings/clock/imx8mp-clock.h
> > index 46c69cd66c62..8430bc4fd182 100644
> > --- a/include/dt-bindings/clock/imx8mp-clock.h
> > +++ b/include/dt-bindings/clock/imx8mp-clock.h
> > @@ -313,6 +313,15 @@
> >  #define IMX8MP_SYS_PLL2_333M_CG			303
> >  #define IMX8MP_SYS_PLL2_500M_CG			304
> >
> > -#define IMX8MP_CLK_END				305
> > +#define IMX8MP_CLK_M7_CORE			305
> > +#define IMX8MP_CLK_ML_CORE			306
> > +#define IMX8MP_CLK_GPU3D_CORE			307
> > +#define IMX8MP_CLK_GPU3D_SHADER_CORE		308
> > +#define IMX8MP_CLK_GPU2D_CORE			309
> > +#define IMX8MP_CLK_AUDIO_AXI			310
> > +#define IMX8MP_CLK_HSIO_AXI			311
> > +#define IMX8MP_CLK_MEDIA_ISP			312
> > +
> > +#define IMX8MP_CLK_END				313
> >
> >  #endif
> > --
> > 2.16.4

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RE: [PATCH V2 06/10] clk: imx8m: migrate A53 clk root to use composite core

[Peng Fan]

> Subject: RE: [PATCH V2 06/10] clk: imx8m: migrate A53 clk root to use
> composite core
> 
> > From: Peng Fan <peng.fan@nxp.com>
> > Sent: Thursday, March 12, 2020 6:20 PM
> >
> > Migrate A53 clk root to use composite core clk type. It will simplify
> > code and make it easy to use composite specific mux operation.
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >  drivers/clk/imx/clk-imx8mm.c | 6 +++---  drivers/clk/imx/clk-imx8mn.c
> > | 6
> > +++---  drivers/clk/imx/clk-imx8mq.c | 6 +++---
> >  3 files changed, 9 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/clk/imx/clk-imx8mm.c
> > b/drivers/clk/imx/clk-imx8mm.c index
> > 5435042a06e3..12443e06f329 100644
> > --- a/drivers/clk/imx/clk-imx8mm.c
> > +++ b/drivers/clk/imx/clk-imx8mm.c
> > @@ -416,9 +416,9 @@ static int imx8mm_clocks_probe(struct
> > platform_device *pdev)
> >  		return PTR_ERR(base);
> >
> >  	/* Core Slice */
> > -	hws[IMX8MM_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src",
> base +
> > 0x8000, 24, 3, imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels));
> > -	hws[IMX8MM_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg",
> > "arm_a53_src", base + 0x8000, 28);
> > -	hws[IMX8MM_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div",
> > "arm_a53_cg", base + 0x8000, 0, 3);
> > +	hws[IMX8MM_CLK_A53_DIV] =
> > imx8m_clk_hw_composite_core("arm_a53_div", imx8mm_a53_sels, base +
> > 0x8000);
> > +	hws[IMX8MM_CLK_A53_CG] = hws[IMX8MM_CLK_A53_DIV];
> > +	hws[IMX8MM_CLK_A53_SRC] = hws[IMX8MM_CLK_A53_DIV];
> 
> The former patch already breaks the compatibility.
> Not sure if we really need keep it for only A53 clock here as we are still at
> very early enablement Phase for MX8MP.  So we may just remove them
> IMHO.

i.MX8MM, not i.MX8MP.

Thanks,
Peng.

> Shawn, what's your suggestion?
> 
> Regards
> Aisheng
> 
> >
> >  	hws[IMX8MM_CLK_M4_CORE] =
> > imx8m_clk_hw_composite_core("arm_m4_core", imx8mm_m4_sels, base +
> > 0x8080);
> >  	hws[IMX8MM_CLK_VPU_CORE] =
> > imx8m_clk_hw_composite_core("vpu_core", imx8mm_vpu_sels, base +
> > 0x8100); diff --git a/drivers/clk/imx/clk-imx8mn.c
> > b/drivers/clk/imx/clk-imx8mn.c index 6cac6ca03e12..bd3759b4afd0
> 100644
> > --- a/drivers/clk/imx/clk-imx8mn.c
> > +++ b/drivers/clk/imx/clk-imx8mn.c
> > @@ -413,9 +413,9 @@ static int imx8mn_clocks_probe(struct
> > platform_device
> > *pdev)
> >  	}
> >
> >  	/* CORE */
> > -	hws[IMX8MN_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base
> +
> > 0x8000, 24, 3, imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels));
> > -	hws[IMX8MN_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg",
> > "arm_a53_src", base + 0x8000, 28);
> > -	hws[IMX8MN_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div",
> > "arm_a53_cg", base + 0x8000, 0, 3);
> > +	hws[IMX8MN_CLK_A53_DIV] =
> > imx8m_clk_hw_composite_core("arm_a53_div", imx8mn_a53_sels, base +
> > 0x8000);
> > +	hws[IMX8MN_CLK_A53_SRC] = hws[IMX8MN_CLK_A53_DIV];
> > +	hws[IMX8MN_CLK_A53_CG] = hws[IMX8MN_CLK_A53_DIV];
> >
> >  	hws[IMX8MN_CLK_GPU_CORE] =
> > imx8m_clk_hw_composite_core("gpu_core", imx8mn_gpu_core_sels, base
> +
> > 0x8180);
> >  	hws[IMX8MN_CLK_GPU_SHADER] =
> > imx8m_clk_hw_composite_core("gpu_shader", imx8mn_gpu_shader_sels,
> base
> > + 0x8200); diff --git a/drivers/clk/imx/clk-imx8mq.c
> > b/drivers/clk/imx/clk-imx8mq.c index 201c7bbb201f..91309ff65441 100644
> > --- a/drivers/clk/imx/clk-imx8mq.c
> > +++ b/drivers/clk/imx/clk-imx8mq.c
> > @@ -405,9 +405,9 @@ static int imx8mq_clocks_probe(struct
> > platform_device
> > *pdev)
> >  		return PTR_ERR(base);
> >
> >  	/* CORE */
> > -	hws[IMX8MQ_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base
> +
> > 0x8000, 24, 3, imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels));
> > -	hws[IMX8MQ_CLK_A53_CG] = imx_clk_hw_gate3_flags("arm_a53_cg",
> > "arm_a53_src", base + 0x8000, 28, CLK_IS_CRITICAL);
> > -	hws[IMX8MQ_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div",
> > "arm_a53_cg", base + 0x8000, 0, 3);
> > +	hws[IMX8MQ_CLK_A53_DIV] =
> > imx8m_clk_hw_composite_core("arm_a53_div", imx8mq_a53_sels, base +
> > 0x8000);
> > +	hws[IMX8MQ_CLK_A53_CG] = hws[IMX8MQ_CLK_A53_DIV];
> > +	hws[IMX8MQ_CLK_A53_SRC] = hws[IMX8MQ_CLK_A53_DIV];
> >
> >  	hws[IMX8MQ_CLK_M4_CORE] =
> > imx8m_clk_hw_composite_core("arm_m4_core", imx8mq_arm_m4_sels,
> base
> > + 0x8080);
> >  	hws[IMX8MQ_CLK_VPU_CORE] =
> > imx8m_clk_hw_composite_core("vpu_core", imx8mq_vpu_sels, base +
> > 0x8100);
> > --
> > 2.16.4

RE: [PATCH V2 06/10] clk: imx8m: migrate A53 clk root to use composite core

[Peng Fan]

> Subject: RE: [PATCH V2 06/10] clk: imx8m: migrate A53 clk root to use
> composite core
> 
> > From: Peng Fan <peng.fan@nxp.com>
> > Sent: Thursday, March 12, 2020 6:20 PM
> >
> > Migrate A53 clk root to use composite core clk type. It will simplify
> > code and make it easy to use composite specific mux operation.
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >  drivers/clk/imx/clk-imx8mm.c | 6 +++---  drivers/clk/imx/clk-imx8mn.c
> > | 6
> > +++---  drivers/clk/imx/clk-imx8mq.c | 6 +++---
> >  3 files changed, 9 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/clk/imx/clk-imx8mm.c
> > b/drivers/clk/imx/clk-imx8mm.c index
> > 5435042a06e3..12443e06f329 100644
> > --- a/drivers/clk/imx/clk-imx8mm.c
> > +++ b/drivers/clk/imx/clk-imx8mm.c
> > @@ -416,9 +416,9 @@ static int imx8mm_clocks_probe(struct
> > platform_device *pdev)
> >  		return PTR_ERR(base);
> >
> >  	/* Core Slice */
> > -	hws[IMX8MM_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src",
> base +
> > 0x8000, 24, 3, imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels));
> > -	hws[IMX8MM_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg",
> > "arm_a53_src", base + 0x8000, 28);
> > -	hws[IMX8MM_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div",
> > "arm_a53_cg", base + 0x8000, 0, 3);
> > +	hws[IMX8MM_CLK_A53_DIV] =
> > imx8m_clk_hw_composite_core("arm_a53_div", imx8mm_a53_sels, base +
> > 0x8000);
> > +	hws[IMX8MM_CLK_A53_CG] = hws[IMX8MM_CLK_A53_DIV];
> > +	hws[IMX8MM_CLK_A53_SRC] = hws[IMX8MM_CLK_A53_DIV];
> 
> The former patch already breaks the compatibility.
> Not sure if we really need keep it for only A53 clock here as we are still at
> very early enablement Phase for MX8MP.  So we may just remove them
> IMHO.

i.MX8MM, not i.MX8MP.

Thanks,
Peng.

> Shawn, what's your suggestion?
> 
> Regards
> Aisheng
> 
> >
> >  	hws[IMX8MM_CLK_M4_CORE] =
> > imx8m_clk_hw_composite_core("arm_m4_core", imx8mm_m4_sels, base +
> > 0x8080);
> >  	hws[IMX8MM_CLK_VPU_CORE] =
> > imx8m_clk_hw_composite_core("vpu_core", imx8mm_vpu_sels, base +
> > 0x8100); diff --git a/drivers/clk/imx/clk-imx8mn.c
> > b/drivers/clk/imx/clk-imx8mn.c index 6cac6ca03e12..bd3759b4afd0
> 100644
> > --- a/drivers/clk/imx/clk-imx8mn.c
> > +++ b/drivers/clk/imx/clk-imx8mn.c
> > @@ -413,9 +413,9 @@ static int imx8mn_clocks_probe(struct
> > platform_device
> > *pdev)
> >  	}
> >
> >  	/* CORE */
> > -	hws[IMX8MN_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base
> +
> > 0x8000, 24, 3, imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels));
> > -	hws[IMX8MN_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg",
> > "arm_a53_src", base + 0x8000, 28);
> > -	hws[IMX8MN_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div",
> > "arm_a53_cg", base + 0x8000, 0, 3);
> > +	hws[IMX8MN_CLK_A53_DIV] =
> > imx8m_clk_hw_composite_core("arm_a53_div", imx8mn_a53_sels, base +
> > 0x8000);
> > +	hws[IMX8MN_CLK_A53_SRC] = hws[IMX8MN_CLK_A53_DIV];
> > +	hws[IMX8MN_CLK_A53_CG] = hws[IMX8MN_CLK_A53_DIV];
> >
> >  	hws[IMX8MN_CLK_GPU_CORE] =
> > imx8m_clk_hw_composite_core("gpu_core", imx8mn_gpu_core_sels, base
> +
> > 0x8180);
> >  	hws[IMX8MN_CLK_GPU_SHADER] =
> > imx8m_clk_hw_composite_core("gpu_shader", imx8mn_gpu_shader_sels,
> base
> > + 0x8200); diff --git a/drivers/clk/imx/clk-imx8mq.c
> > b/drivers/clk/imx/clk-imx8mq.c index 201c7bbb201f..91309ff65441 100644
> > --- a/drivers/clk/imx/clk-imx8mq.c
> > +++ b/drivers/clk/imx/clk-imx8mq.c
> > @@ -405,9 +405,9 @@ static int imx8mq_clocks_probe(struct
> > platform_device
> > *pdev)
> >  		return PTR_ERR(base);
> >
> >  	/* CORE */
> > -	hws[IMX8MQ_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base
> +
> > 0x8000, 24, 3, imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels));
> > -	hws[IMX8MQ_CLK_A53_CG] = imx_clk_hw_gate3_flags("arm_a53_cg",
> > "arm_a53_src", base + 0x8000, 28, CLK_IS_CRITICAL);
> > -	hws[IMX8MQ_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div",
> > "arm_a53_cg", base + 0x8000, 0, 3);
> > +	hws[IMX8MQ_CLK_A53_DIV] =
> > imx8m_clk_hw_composite_core("arm_a53_div", imx8mq_a53_sels, base +
> > 0x8000);
> > +	hws[IMX8MQ_CLK_A53_CG] = hws[IMX8MQ_CLK_A53_DIV];
> > +	hws[IMX8MQ_CLK_A53_SRC] = hws[IMX8MQ_CLK_A53_DIV];
> >
> >  	hws[IMX8MQ_CLK_M4_CORE] =
> > imx8m_clk_hw_composite_core("arm_m4_core", imx8mq_arm_m4_sels,
> base
> > + 0x8080);
> >  	hws[IMX8MQ_CLK_VPU_CORE] =
> > imx8m_clk_hw_composite_core("vpu_core", imx8mq_vpu_sels, base +
> > 0x8100);
> > --
> > 2.16.4

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RE: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk

[Peng Fan]

> Subject: RE: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite
> clk
> 
> > From: Peng Fan <peng.fan@nxp.com>
> > Sent: Thursday, March 12, 2020 6:20 PM
> >
> > The CORE/BUS root slice has following design, simplied graph:
> > The difference is core not have pre_div block.
> > A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7].
> >
> >             SEL_A  GA
> >             +--+  +-+
> >             |  +->+ +------+
> > CLK[0-7]--->+  |  +-+      |
> >        |    |  |      +----v---+    +----+
> >        |    +--+      |pre_diva+---->    |  +---------+
> >        |              +--------+    |mux +--+post_div |
> >        |    +--+      |pre_divb+--->+    |  +---------+
> >        |    |  |      +----^---+    +----+
> >        +--->+  |  +-+      |
> >             |  +->+ +------+
> >             +--+  +-+
> >             SEL_B  GB
> >
> > There will be system hang, when doing the following steps:
> > 1. switch mux from clk0 to clk1
> > 2. gate off clk0
> > 3. swtich from clk1 to clk2, or gate off clk1
> >
> > Step 3 triggers system hang.
> 
> Why Step 3 triggers system hang? Is this a HW limitation?

It is what hardware designed.

There is a counter inside the clk root module to choose
SEL_A or SEL_B. If choose SEL_B, the parent of SEL_B must
be active, otherwise the change from SEL_A to SEL_B
will cause hang.

SEL_A and SEL_B is inside the clock root module,
It is not clk's software parentA/B. misunderstand
this will misunderstand the whole fix.

> 
> >
> > If we skip step2, keep clk0 on, step 3 will not trigger system hang.
> > However we have CLK_OPS_PARENT_ENABLE flag, which will unprepare
> > disable the clk0 which will not be used.
> >
> > To address this issue, we could use following simplied software flow:
> > After the first target register set
> > wait the target register set finished
> > set the target register set again
> > wait the target register set finished
> >
> > The upper flow will make sure SEL_A and SEL_B both set the new mux,
> > but with only one path gate on.
> >
> > And there will be no system hang anymore with step3.
> 
> Is this IC proposed solution?

This is what I proposed and IC team confirmed.

> 
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >
> > V2:
> >  Drop wait after write, add one line comment for write twice.
> >
> >  drivers/clk/imx/clk-composite-8m.c | 62
> > +++++++++++++++++++++++++++++++++++++-
> >  1 file changed, 61 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/imx/clk-composite-8m.c
> > b/drivers/clk/imx/clk-composite-8m.c
> > index 99773519b5a5..eae02c151ced 100644
> > --- a/drivers/clk/imx/clk-composite-8m.c
> > +++ b/drivers/clk/imx/clk-composite-8m.c
> > @@ -24,6 +24,12 @@
> >
> >  #define PCG_CGC_SHIFT		28
> >
> > +#define PRE_REG_OFF		0x30
> > +#define PRE_MUXA_SHIFT		24
> > +#define PRE_MUXA_MASK		0x7
> > +#define PRE_MUXB_SHIFT		8
> > +#define PRE_MUXB_MASK		0x7
> 
> Are those macros used somewhere?

Remove in v3.

> 
> > +
> >  static unsigned long imx8m_clk_composite_divider_recalc_rate(struct
> > clk_hw *hw,
> >  						unsigned long parent_rate)
> >  {
> > @@ -124,6 +130,57 @@ static const struct clk_ops
> > imx8m_clk_composite_divider_ops = {
> >  	.set_rate = imx8m_clk_composite_divider_set_rate,
> >  };
> >
> > +static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw) {
> > +	struct clk_mux *mux = to_clk_mux(hw);
> > +	u32 val;
> > +
> > +	val = readl(mux->reg) >> mux->shift;
> > +	val &= mux->mask;
> > +
> > +	return clk_mux_val_to_index(hw, mux->table, mux->flags, val); }
> 
> You don't have to redefinition them if they're the same as clk_mux_ops.
> You have the access to clk_mux_ops.

This will require export_symbol of clk_mux_ops callbacks.

> 
> > +
> > +static int imx8m_clk_composite_mux_set_parent(struct clk_hw *hw, u8
> > +index) {
> > +	struct clk_mux *mux = to_clk_mux(hw);
> > +	u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
> > +	unsigned long flags = 0;
> > +	u32 reg;
> > +
> > +	if (mux->lock)
> > +		spin_lock_irqsave(mux->lock, flags);
> > +
> > +	reg = readl(mux->reg);
> > +	reg &= ~(mux->mask << mux->shift);
> > +	val = val << mux->shift;
> > +	reg |= val;
> > +	/* write twice to make sure SEL_A/B point the same mux */
> > +	writel(reg, mux->reg);
> > +	writel(reg, mux->reg);
> 
> Why this affects both SEL_A/B?

The internal counter will make sure both SEL_A/B point
to the same mux.

> Very tricky and may worth more comments.

Ah, I think RM should be clear about the target interface
and non-target interface.

When you write once, saying use SEL_A, when
you write the 2nd, the hardware will use SEL_B,
when you write 3rd, the hardware will use SEL_A.
and ...

> 
> Besides that, I'd like to see Abel's comments on this patch.


Abel,

 Any comments?

Thanks,
Peng.

> 
> Regards
> Aisheng
> 
> > +
> > +	if (mux->lock)
> > +		spin_unlock_irqrestore(mux->lock, flags);
> > +
> > +	return 0;
> > +}
> > +
> > +static int
> > +imx8m_clk_composite_mux_determine_rate(struct clk_hw *hw,
> > +				       struct clk_rate_request *req) {
> > +	struct clk_mux *mux = to_clk_mux(hw);
> > +
> > +	return clk_mux_determine_rate_flags(hw, req, mux->flags); }
> 
> Same as bove.
> 
> > +
> > +
> > +const struct clk_ops imx8m_clk_composite_mux_ops = {
> > +	.get_parent = imx8m_clk_composite_mux_get_parent,
> > +	.set_parent = imx8m_clk_composite_mux_set_parent,
> > +	.determine_rate = imx8m_clk_composite_mux_determine_rate,
> > +};
> > +
> >  struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
> >  					const char * const *parent_names,
> >  					int num_parents, void __iomem *reg, @@ -136,6
> > +193,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char
> > +*name,
> >  	struct clk_gate *gate = NULL;
> >  	struct clk_mux *mux = NULL;
> >  	const struct clk_ops *divider_ops;
> > +	const struct clk_ops *mux_ops;
> >
> >  	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
> >  	if (!mux)
> > @@ -157,10 +215,12 @@ struct clk_hw
> > *imx8m_clk_hw_composite_flags(const char *name,
> >  		div->shift = PCG_DIV_SHIFT;
> >  		div->width = PCG_CORE_DIV_WIDTH;
> >  		divider_ops = &clk_divider_ops;
> > +		mux_ops = &imx8m_clk_composite_mux_ops;
> >  	} else {
> >  		div->shift = PCG_PREDIV_SHIFT;
> >  		div->width = PCG_PREDIV_WIDTH;
> >  		divider_ops = &imx8m_clk_composite_divider_ops;
> > +		mux_ops = &clk_mux_ops;
> >  	}
> >
> >  	div->lock = &imx_ccm_lock;
> > @@ -176,7 +236,7 @@ struct clk_hw
> *imx8m_clk_hw_composite_flags(const
> > char *name,
> >  	gate->lock = &imx_ccm_lock;
> >
> >  	hw = clk_hw_register_composite(NULL, name, parent_names,
> > num_parents,
> > -			mux_hw, &clk_mux_ops, div_hw,
> > +			mux_hw, mux_ops, div_hw,
> >  			divider_ops, gate_hw, &clk_gate_ops, flags);
> >  	if (IS_ERR(hw))
> >  		goto fail;
> > --
> > 2.16.4

RE: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk

[Peng Fan]

> Subject: RE: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite
> clk
> 
> > From: Peng Fan <peng.fan@nxp.com>
> > Sent: Thursday, March 12, 2020 6:20 PM
> >
> > The CORE/BUS root slice has following design, simplied graph:
> > The difference is core not have pre_div block.
> > A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7].
> >
> >             SEL_A  GA
> >             +--+  +-+
> >             |  +->+ +------+
> > CLK[0-7]--->+  |  +-+      |
> >        |    |  |      +----v---+    +----+
> >        |    +--+      |pre_diva+---->    |  +---------+
> >        |              +--------+    |mux +--+post_div |
> >        |    +--+      |pre_divb+--->+    |  +---------+
> >        |    |  |      +----^---+    +----+
> >        +--->+  |  +-+      |
> >             |  +->+ +------+
> >             +--+  +-+
> >             SEL_B  GB
> >
> > There will be system hang, when doing the following steps:
> > 1. switch mux from clk0 to clk1
> > 2. gate off clk0
> > 3. swtich from clk1 to clk2, or gate off clk1
> >
> > Step 3 triggers system hang.
> 
> Why Step 3 triggers system hang? Is this a HW limitation?

It is what hardware designed.

There is a counter inside the clk root module to choose
SEL_A or SEL_B. If choose SEL_B, the parent of SEL_B must
be active, otherwise the change from SEL_A to SEL_B
will cause hang.

SEL_A and SEL_B is inside the clock root module,
It is not clk's software parentA/B. misunderstand
this will misunderstand the whole fix.

> 
> >
> > If we skip step2, keep clk0 on, step 3 will not trigger system hang.
> > However we have CLK_OPS_PARENT_ENABLE flag, which will unprepare
> > disable the clk0 which will not be used.
> >
> > To address this issue, we could use following simplied software flow:
> > After the first target register set
> > wait the target register set finished
> > set the target register set again
> > wait the target register set finished
> >
> > The upper flow will make sure SEL_A and SEL_B both set the new mux,
> > but with only one path gate on.
> >
> > And there will be no system hang anymore with step3.
> 
> Is this IC proposed solution?

This is what I proposed and IC team confirmed.

> 
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >
> > V2:
> >  Drop wait after write, add one line comment for write twice.
> >
> >  drivers/clk/imx/clk-composite-8m.c | 62
> > +++++++++++++++++++++++++++++++++++++-
> >  1 file changed, 61 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/imx/clk-composite-8m.c
> > b/drivers/clk/imx/clk-composite-8m.c
> > index 99773519b5a5..eae02c151ced 100644
> > --- a/drivers/clk/imx/clk-composite-8m.c
> > +++ b/drivers/clk/imx/clk-composite-8m.c
> > @@ -24,6 +24,12 @@
> >
> >  #define PCG_CGC_SHIFT		28
> >
> > +#define PRE_REG_OFF		0x30
> > +#define PRE_MUXA_SHIFT		24
> > +#define PRE_MUXA_MASK		0x7
> > +#define PRE_MUXB_SHIFT		8
> > +#define PRE_MUXB_MASK		0x7
> 
> Are those macros used somewhere?

Remove in v3.

> 
> > +
> >  static unsigned long imx8m_clk_composite_divider_recalc_rate(struct
> > clk_hw *hw,
> >  						unsigned long parent_rate)
> >  {
> > @@ -124,6 +130,57 @@ static const struct clk_ops
> > imx8m_clk_composite_divider_ops = {
> >  	.set_rate = imx8m_clk_composite_divider_set_rate,
> >  };
> >
> > +static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw) {
> > +	struct clk_mux *mux = to_clk_mux(hw);
> > +	u32 val;
> > +
> > +	val = readl(mux->reg) >> mux->shift;
> > +	val &= mux->mask;
> > +
> > +	return clk_mux_val_to_index(hw, mux->table, mux->flags, val); }
> 
> You don't have to redefinition them if they're the same as clk_mux_ops.
> You have the access to clk_mux_ops.

This will require export_symbol of clk_mux_ops callbacks.

> 
> > +
> > +static int imx8m_clk_composite_mux_set_parent(struct clk_hw *hw, u8
> > +index) {
> > +	struct clk_mux *mux = to_clk_mux(hw);
> > +	u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
> > +	unsigned long flags = 0;
> > +	u32 reg;
> > +
> > +	if (mux->lock)
> > +		spin_lock_irqsave(mux->lock, flags);
> > +
> > +	reg = readl(mux->reg);
> > +	reg &= ~(mux->mask << mux->shift);
> > +	val = val << mux->shift;
> > +	reg |= val;
> > +	/* write twice to make sure SEL_A/B point the same mux */
> > +	writel(reg, mux->reg);
> > +	writel(reg, mux->reg);
> 
> Why this affects both SEL_A/B?

The internal counter will make sure both SEL_A/B point
to the same mux.

> Very tricky and may worth more comments.

Ah, I think RM should be clear about the target interface
and non-target interface.

When you write once, saying use SEL_A, when
you write the 2nd, the hardware will use SEL_B,
when you write 3rd, the hardware will use SEL_A.
and ...

> 
> Besides that, I'd like to see Abel's comments on this patch.


Abel,

 Any comments?

Thanks,
Peng.

> 
> Regards
> Aisheng
> 
> > +
> > +	if (mux->lock)
> > +		spin_unlock_irqrestore(mux->lock, flags);
> > +
> > +	return 0;
> > +}
> > +
> > +static int
> > +imx8m_clk_composite_mux_determine_rate(struct clk_hw *hw,
> > +				       struct clk_rate_request *req) {
> > +	struct clk_mux *mux = to_clk_mux(hw);
> > +
> > +	return clk_mux_determine_rate_flags(hw, req, mux->flags); }
> 
> Same as bove.
> 
> > +
> > +
> > +const struct clk_ops imx8m_clk_composite_mux_ops = {
> > +	.get_parent = imx8m_clk_composite_mux_get_parent,
> > +	.set_parent = imx8m_clk_composite_mux_set_parent,
> > +	.determine_rate = imx8m_clk_composite_mux_determine_rate,
> > +};
> > +
> >  struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
> >  					const char * const *parent_names,
> >  					int num_parents, void __iomem *reg, @@ -136,6
> > +193,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char
> > +*name,
> >  	struct clk_gate *gate = NULL;
> >  	struct clk_mux *mux = NULL;
> >  	const struct clk_ops *divider_ops;
> > +	const struct clk_ops *mux_ops;
> >
> >  	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
> >  	if (!mux)
> > @@ -157,10 +215,12 @@ struct clk_hw
> > *imx8m_clk_hw_composite_flags(const char *name,
> >  		div->shift = PCG_DIV_SHIFT;
> >  		div->width = PCG_CORE_DIV_WIDTH;
> >  		divider_ops = &clk_divider_ops;
> > +		mux_ops = &imx8m_clk_composite_mux_ops;
> >  	} else {
> >  		div->shift = PCG_PREDIV_SHIFT;
> >  		div->width = PCG_PREDIV_WIDTH;
> >  		divider_ops = &imx8m_clk_composite_divider_ops;
> > +		mux_ops = &clk_mux_ops;
> >  	}
> >
> >  	div->lock = &imx_ccm_lock;
> > @@ -176,7 +236,7 @@ struct clk_hw
> *imx8m_clk_hw_composite_flags(const
> > char *name,
> >  	gate->lock = &imx_ccm_lock;
> >
> >  	hw = clk_hw_register_composite(NULL, name, parent_names,
> > num_parents,
> > -			mux_hw, &clk_mux_ops, div_hw,
> > +			mux_hw, mux_ops, div_hw,
> >  			divider_ops, gate_hw, &clk_gate_ops, flags);
> >  	if (IS_ERR(hw))
> >  		goto fail;
> > --
> > 2.16.4

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RE: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk

[Peng Fan]

> Subject: Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite
> clk
> 
> On 2020-03-12 12:27 PM, Peng Fan wrote:
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > The CORE/BUS root slice has following design, simplied graph:
> > The difference is core not have pre_div block.
> > A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7].
> >
> >              SEL_A  GA
> >              +--+  +-+
> >              |  +->+ +------+
> > CLK[0-7]--->+  |  +-+      |
> >         |    |  |      +----v---+    +----+
> >         |    +--+      |pre_diva+---->    |  +---------+
> >         |              +--------+    |mux +--+post_div |
> >         |    +--+      |pre_divb+--->+    |  +---------+
> >         |    |  |      +----^---+    +----+
> >         +--->+  |  +-+      |
> >              |  +->+ +------+
> >              +--+  +-+
> >              SEL_B  GB
> >
> > There will be system hang, when doing the following steps:
> > 1. switch mux from clk0 to clk1
> > 2. gate off clk0
> > 3. swtich from clk1 to clk2, or gate off clk1
> >
> > Step 3 triggers system hang.
> >
> > If we skip step2, keep clk0 on, step 3 will not trigger system hang.
> > However we have CLK_OPS_PARENT_ENABLE flag, which will unprepare
> > disable the clk0 which will not be used.
> 
> As far as I understand when switching from clk1 to clk2 this is done by
> temporarily switching the rightmost SELECT mux to whatever was in the
> spare SEL, which is essentially arbitrary from linux POV.

No. The fixes in this patches has been confirmed by IC design owner

> 
> This is quite unexpected but in theory it might be desirable to use a third
> parent as a fallback.

No. this will make things complicated. To CCM SEL_A and SEL_B,
it is controlled by a hardware counter. Saying you write n times to
the target interface.

The mux will use n % 2 to choose SEL_A or SEL_B. write twice
to make sure SEL_A and SEL_B has the same value.

Thanks,
Peng.

> 
> >
> > To address this issue, we could use following simplied software flow:
> > After the first target register set
> > wait the target register set finished
> > set the target register set again
> > wait the target register set finished
> >
> > The upper flow will make sure SEL_A and SEL_B both set the new mux,
> > but with only one path gate on.
> > And there will be no system hang anymore with step3.
> 
> Your fix tries to work around this scenario by always setting the mux value in
> SEL_A and SEL_B to the same value after each set_parent operation.
> 
> But what if SEL_A and SEL_B are different at linux boot time and the first
> reparenting is done *after* disabling unused clocks? This doesn't happen for
> A53 because it's reparented during clock provider probe but maybe this
> scenario could be contrived if bootloader touches one of the other bus slices.
> 
> It might be extra safe to assign the parent of the spare mux at the start of
> each set_parent call. This could even be done on probe and this way wouldn't
> have to duplicate mux_ops just to do a double write.
> 
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >
> > V2:
> >   Drop wait after write, add one line comment for write twice.
> >
> >   drivers/clk/imx/clk-composite-8m.c | 62
> +++++++++++++++++++++++++++++++++++++-
> >   1 file changed, 61 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/imx/clk-composite-8m.c
> > b/drivers/clk/imx/clk-composite-8m.c
> > index 99773519b5a5..eae02c151ced 100644
> > --- a/drivers/clk/imx/clk-composite-8m.c
> > +++ b/drivers/clk/imx/clk-composite-8m.c
> > @@ -24,6 +24,12 @@
> >
> >   #define PCG_CGC_SHIFT		28
> >
> > +#define PRE_REG_OFF		0x30
> > +#define PRE_MUXA_SHIFT		24
> > +#define PRE_MUXA_MASK		0x7
> > +#define PRE_MUXB_SHIFT		8
> > +#define PRE_MUXB_MASK		0x7
> 
> These are unused.
> 
> > +
> >   static unsigned long imx8m_clk_composite_divider_recalc_rate(struct
> clk_hw *hw,
> >   						unsigned long parent_rate)
> >   {
> > @@ -124,6 +130,57 @@ static const struct clk_ops
> imx8m_clk_composite_divider_ops = {
> >   	.set_rate = imx8m_clk_composite_divider_set_rate,
> >   };
> >
> > +static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw) {
> > +	struct clk_mux *mux = to_clk_mux(hw);
> > +	u32 val;
> > +
> > +	val = readl(mux->reg) >> mux->shift;
> > +	val &= mux->mask;
> > +
> > +	return clk_mux_val_to_index(hw, mux->table, mux->flags, val); }
> > +
> > +static int imx8m_clk_composite_mux_set_parent(struct clk_hw *hw, u8
> > +index) {
> > +	struct clk_mux *mux = to_clk_mux(hw);
> > +	u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
> > +	unsigned long flags = 0;
> > +	u32 reg;
> > +
> > +	if (mux->lock)
> > +		spin_lock_irqsave(mux->lock, flags);
> > +
> > +	reg = readl(mux->reg);
> > +	reg &= ~(mux->mask << mux->shift);
> > +	val = val << mux->shift;
> > +	reg |= val;
> > +	/* write twice to make sure SEL_A/B point the same mux */
> > +	writel(reg, mux->reg);
> > +	writel(reg, mux->reg);
> > +
> > +	if (mux->lock)
> > +		spin_unlock_irqrestore(mux->lock, flags);
> > +
> > +	return 0;
> > +}
> > +
> > +static int
> > +imx8m_clk_composite_mux_determine_rate(struct clk_hw *hw,
> > +				       struct clk_rate_request *req) {
> > +	struct clk_mux *mux = to_clk_mux(hw);
> > +
> > +	return clk_mux_determine_rate_flags(hw, req, mux->flags); }
> > +
> > +
> > +const struct clk_ops imx8m_clk_composite_mux_ops = {
> > +	.get_parent = imx8m_clk_composite_mux_get_parent,
> > +	.set_parent = imx8m_clk_composite_mux_set_parent,
> > +	.determine_rate = imx8m_clk_composite_mux_determine_rate,
> > +};
> > +
> >   struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
> >   					const char * const *parent_names,
> >   					int num_parents, void __iomem *reg, @@
> -136,6 +193,7 @@ struct
> > clk_hw *imx8m_clk_hw_composite_flags(const char *name,
> >   	struct clk_gate *gate = NULL;
> >   	struct clk_mux *mux = NULL;
> >   	const struct clk_ops *divider_ops;
> > +	const struct clk_ops *mux_ops;
> >
> >   	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
> >   	if (!mux)
> > @@ -157,10 +215,12 @@ struct clk_hw
> *imx8m_clk_hw_composite_flags(const char *name,
> >   		div->shift = PCG_DIV_SHIFT;
> >   		div->width = PCG_CORE_DIV_WIDTH;
> >   		divider_ops = &clk_divider_ops;
> > +		mux_ops = &imx8m_clk_composite_mux_ops;
> >   	} else {
> >   		div->shift = PCG_PREDIV_SHIFT;
> >   		div->width = PCG_PREDIV_WIDTH;
> >   		divider_ops = &imx8m_clk_composite_divider_ops;
> > +		mux_ops = &clk_mux_ops;
> >   	}
> >
> >   	div->lock = &imx_ccm_lock;
> > @@ -176,7 +236,7 @@ struct clk_hw
> *imx8m_clk_hw_composite_flags(const char *name,
> >   	gate->lock = &imx_ccm_lock;
> >
> >   	hw = clk_hw_register_composite(NULL, name, parent_names,
> num_parents,
> > -			mux_hw, &clk_mux_ops, div_hw,
> > +			mux_hw, mux_ops, div_hw,
> >   			divider_ops, gate_hw, &clk_gate_ops, flags);
> >   	if (IS_ERR(hw))
> >   		goto fail;
> >

RE: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk

[Peng Fan]

> Subject: Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite
> clk
> 
> On 2020-03-12 12:27 PM, Peng Fan wrote:
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > The CORE/BUS root slice has following design, simplied graph:
> > The difference is core not have pre_div block.
> > A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7].
> >
> >              SEL_A  GA
> >              +--+  +-+
> >              |  +->+ +------+
> > CLK[0-7]--->+  |  +-+      |
> >         |    |  |      +----v---+    +----+
> >         |    +--+      |pre_diva+---->    |  +---------+
> >         |              +--------+    |mux +--+post_div |
> >         |    +--+      |pre_divb+--->+    |  +---------+
> >         |    |  |      +----^---+    +----+
> >         +--->+  |  +-+      |
> >              |  +->+ +------+
> >              +--+  +-+
> >              SEL_B  GB
> >
> > There will be system hang, when doing the following steps:
> > 1. switch mux from clk0 to clk1
> > 2. gate off clk0
> > 3. swtich from clk1 to clk2, or gate off clk1
> >
> > Step 3 triggers system hang.
> >
> > If we skip step2, keep clk0 on, step 3 will not trigger system hang.
> > However we have CLK_OPS_PARENT_ENABLE flag, which will unprepare
> > disable the clk0 which will not be used.
> 
> As far as I understand when switching from clk1 to clk2 this is done by
> temporarily switching the rightmost SELECT mux to whatever was in the
> spare SEL, which is essentially arbitrary from linux POV.

No. The fixes in this patches has been confirmed by IC design owner

> 
> This is quite unexpected but in theory it might be desirable to use a third
> parent as a fallback.

No. this will make things complicated. To CCM SEL_A and SEL_B,
it is controlled by a hardware counter. Saying you write n times to
the target interface.

The mux will use n % 2 to choose SEL_A or SEL_B. write twice
to make sure SEL_A and SEL_B has the same value.

Thanks,
Peng.

> 
> >
> > To address this issue, we could use following simplied software flow:
> > After the first target register set
> > wait the target register set finished
> > set the target register set again
> > wait the target register set finished
> >
> > The upper flow will make sure SEL_A and SEL_B both set the new mux,
> > but with only one path gate on.
> > And there will be no system hang anymore with step3.
> 
> Your fix tries to work around this scenario by always setting the mux value in
> SEL_A and SEL_B to the same value after each set_parent operation.
> 
> But what if SEL_A and SEL_B are different at linux boot time and the first
> reparenting is done *after* disabling unused clocks? This doesn't happen for
> A53 because it's reparented during clock provider probe but maybe this
> scenario could be contrived if bootloader touches one of the other bus slices.
> 
> It might be extra safe to assign the parent of the spare mux at the start of
> each set_parent call. This could even be done on probe and this way wouldn't
> have to duplicate mux_ops just to do a double write.
> 
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >
> > V2:
> >   Drop wait after write, add one line comment for write twice.
> >
> >   drivers/clk/imx/clk-composite-8m.c | 62
> +++++++++++++++++++++++++++++++++++++-
> >   1 file changed, 61 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/imx/clk-composite-8m.c
> > b/drivers/clk/imx/clk-composite-8m.c
> > index 99773519b5a5..eae02c151ced 100644
> > --- a/drivers/clk/imx/clk-composite-8m.c
> > +++ b/drivers/clk/imx/clk-composite-8m.c
> > @@ -24,6 +24,12 @@
> >
> >   #define PCG_CGC_SHIFT		28
> >
> > +#define PRE_REG_OFF		0x30
> > +#define PRE_MUXA_SHIFT		24
> > +#define PRE_MUXA_MASK		0x7
> > +#define PRE_MUXB_SHIFT		8
> > +#define PRE_MUXB_MASK		0x7
> 
> These are unused.
> 
> > +
> >   static unsigned long imx8m_clk_composite_divider_recalc_rate(struct
> clk_hw *hw,
> >   						unsigned long parent_rate)
> >   {
> > @@ -124,6 +130,57 @@ static const struct clk_ops
> imx8m_clk_composite_divider_ops = {
> >   	.set_rate = imx8m_clk_composite_divider_set_rate,
> >   };
> >
> > +static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw) {
> > +	struct clk_mux *mux = to_clk_mux(hw);
> > +	u32 val;
> > +
> > +	val = readl(mux->reg) >> mux->shift;
> > +	val &= mux->mask;
> > +
> > +	return clk_mux_val_to_index(hw, mux->table, mux->flags, val); }
> > +
> > +static int imx8m_clk_composite_mux_set_parent(struct clk_hw *hw, u8
> > +index) {
> > +	struct clk_mux *mux = to_clk_mux(hw);
> > +	u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
> > +	unsigned long flags = 0;
> > +	u32 reg;
> > +
> > +	if (mux->lock)
> > +		spin_lock_irqsave(mux->lock, flags);
> > +
> > +	reg = readl(mux->reg);
> > +	reg &= ~(mux->mask << mux->shift);
> > +	val = val << mux->shift;
> > +	reg |= val;
> > +	/* write twice to make sure SEL_A/B point the same mux */
> > +	writel(reg, mux->reg);
> > +	writel(reg, mux->reg);
> > +
> > +	if (mux->lock)
> > +		spin_unlock_irqrestore(mux->lock, flags);
> > +
> > +	return 0;
> > +}
> > +
> > +static int
> > +imx8m_clk_composite_mux_determine_rate(struct clk_hw *hw,
> > +				       struct clk_rate_request *req) {
> > +	struct clk_mux *mux = to_clk_mux(hw);
> > +
> > +	return clk_mux_determine_rate_flags(hw, req, mux->flags); }
> > +
> > +
> > +const struct clk_ops imx8m_clk_composite_mux_ops = {
> > +	.get_parent = imx8m_clk_composite_mux_get_parent,
> > +	.set_parent = imx8m_clk_composite_mux_set_parent,
> > +	.determine_rate = imx8m_clk_composite_mux_determine_rate,
> > +};
> > +
> >   struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
> >   					const char * const *parent_names,
> >   					int num_parents, void __iomem *reg, @@
> -136,6 +193,7 @@ struct
> > clk_hw *imx8m_clk_hw_composite_flags(const char *name,
> >   	struct clk_gate *gate = NULL;
> >   	struct clk_mux *mux = NULL;
> >   	const struct clk_ops *divider_ops;
> > +	const struct clk_ops *mux_ops;
> >
> >   	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
> >   	if (!mux)
> > @@ -157,10 +215,12 @@ struct clk_hw
> *imx8m_clk_hw_composite_flags(const char *name,
> >   		div->shift = PCG_DIV_SHIFT;
> >   		div->width = PCG_CORE_DIV_WIDTH;
> >   		divider_ops = &clk_divider_ops;
> > +		mux_ops = &imx8m_clk_composite_mux_ops;
> >   	} else {
> >   		div->shift = PCG_PREDIV_SHIFT;
> >   		div->width = PCG_PREDIV_WIDTH;
> >   		divider_ops = &imx8m_clk_composite_divider_ops;
> > +		mux_ops = &clk_mux_ops;
> >   	}
> >
> >   	div->lock = &imx_ccm_lock;
> > @@ -176,7 +236,7 @@ struct clk_hw
> *imx8m_clk_hw_composite_flags(const char *name,
> >   	gate->lock = &imx_ccm_lock;
> >
> >   	hw = clk_hw_register_composite(NULL, name, parent_names,
> num_parents,
> > -			mux_hw, &clk_mux_ops, div_hw,
> > +			mux_hw, mux_ops, div_hw,
> >   			divider_ops, gate_hw, &clk_gate_ops, flags);
> >   	if (IS_ERR(hw))
> >   		goto fail;
> >


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Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk

[Leonard Crestez]

On 2020-04-27 12:15 PM, Peng Fan wrote:
>> Subject: Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite
>> clk
>>
>> On 2020-03-12 12:27 PM, Peng Fan wrote:
>>> From: Peng Fan <peng.fan@nxp.com>
>>>
>>> The CORE/BUS root slice has following design, simplied graph:
>>> The difference is core not have pre_div block.
>>> A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7].
>>>
>>>               SEL_A  GA
>>>               +--+  +-+
>>>               |  +->+ +------+
>>> CLK[0-7]--->+  |  +-+      |
>>>          |    |  |      +----v---+    +----+
>>>          |    +--+      |pre_diva+---->    |  +---------+
>>>          |              +--------+    |mux +--+post_div |
>>>          |    +--+      |pre_divb+--->+    |  +---------+
>>>          |    |  |      +----^---+    +----+
>>>          +--->+  |  +-+      |
>>>               |  +->+ +------+
>>>               +--+  +-+
>>>               SEL_B  GB
>>>
>>> There will be system hang, when doing the following steps:
>>> 1. switch mux from clk0 to clk1
>>> 2. gate off clk0
>>> 3. swtich from clk1 to clk2, or gate off clk1
>>>
>>> Step 3 triggers system hang.
>>>
>>> If we skip step2, keep clk0 on, step 3 will not trigger system hang.
>>> However we have CLK_OPS_PARENT_ENABLE flag, which will unprepare
>>> disable the clk0 which will not be used.
>>
>> As far as I understand when switching from clk1 to clk2 this is done by
>> temporarily switching the rightmost SELECT mux to whatever was in the
>> spare SEL, which is essentially arbitrary from linux POV.
> 
> No. The fixes in this patches has been confirmed by IC design owner
> 
>>
>> This is quite unexpected but in theory it might be desirable to use a third
>> parent as a fallback.
> 
> No. this will make things complicated. To CCM SEL_A and SEL_B,
> it is controlled by a hardware counter. Saying you write n times to
> the target interface.
> 
> The mux will use n % 2 to choose SEL_A or SEL_B. write twice
> to make sure SEL_A and SEL_B has the same value.

What if SEL_A and SEL_B have different values on boot? The first time 
linux does set_parent it will switch to the other SEL_X which might be off.

Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk

[Leonard Crestez]

On 2020-04-27 12:15 PM, Peng Fan wrote:
>> Subject: Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite
>> clk
>>
>> On 2020-03-12 12:27 PM, Peng Fan wrote:
>>> From: Peng Fan <peng.fan@nxp.com>
>>>
>>> The CORE/BUS root slice has following design, simplied graph:
>>> The difference is core not have pre_div block.
>>> A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7].
>>>
>>>               SEL_A  GA
>>>               +--+  +-+
>>>               |  +->+ +------+
>>> CLK[0-7]--->+  |  +-+      |
>>>          |    |  |      +----v---+    +----+
>>>          |    +--+      |pre_diva+---->    |  +---------+
>>>          |              +--------+    |mux +--+post_div |
>>>          |    +--+      |pre_divb+--->+    |  +---------+
>>>          |    |  |      +----^---+    +----+
>>>          +--->+  |  +-+      |
>>>               |  +->+ +------+
>>>               +--+  +-+
>>>               SEL_B  GB
>>>
>>> There will be system hang, when doing the following steps:
>>> 1. switch mux from clk0 to clk1
>>> 2. gate off clk0
>>> 3. swtich from clk1 to clk2, or gate off clk1
>>>
>>> Step 3 triggers system hang.
>>>
>>> If we skip step2, keep clk0 on, step 3 will not trigger system hang.
>>> However we have CLK_OPS_PARENT_ENABLE flag, which will unprepare
>>> disable the clk0 which will not be used.
>>
>> As far as I understand when switching from clk1 to clk2 this is done by
>> temporarily switching the rightmost SELECT mux to whatever was in the
>> spare SEL, which is essentially arbitrary from linux POV.
> 
> No. The fixes in this patches has been confirmed by IC design owner
> 
>>
>> This is quite unexpected but in theory it might be desirable to use a third
>> parent as a fallback.
> 
> No. this will make things complicated. To CCM SEL_A and SEL_B,
> it is controlled by a hardware counter. Saying you write n times to
> the target interface.
> 
> The mux will use n % 2 to choose SEL_A or SEL_B. write twice
> to make sure SEL_A and SEL_B has the same value.

What if SEL_A and SEL_B have different values on boot? The first time 
linux does set_parent it will switch to the other SEL_X which might be off.

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RE: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk

[Peng Fan]

> Subject: Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite
> clk
> 
> On 2020-04-27 12:15 PM, Peng Fan wrote:
> >> Subject: Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M
> >> composite clk
> >>
> >> On 2020-03-12 12:27 PM, Peng Fan wrote:
> >>> From: Peng Fan <peng.fan@nxp.com>
> >>>
> >>> The CORE/BUS root slice has following design, simplied graph:
> >>> The difference is core not have pre_div block.
> >>> A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7].
> >>>
> >>>               SEL_A  GA
> >>>               +--+  +-+
> >>>               |  +->+ +------+
> >>> CLK[0-7]--->+  |  +-+      |
> >>>          |    |  |      +----v---+    +----+
> >>>          |    +--+      |pre_diva+---->    |  +---------+
> >>>          |              +--------+    |mux +--+post_div |
> >>>          |    +--+      |pre_divb+--->+    |  +---------+
> >>>          |    |  |      +----^---+    +----+
> >>>          +--->+  |  +-+      |
> >>>               |  +->+ +------+
> >>>               +--+  +-+
> >>>               SEL_B  GB
> >>>
> >>> There will be system hang, when doing the following steps:
> >>> 1. switch mux from clk0 to clk1
> >>> 2. gate off clk0
> >>> 3. swtich from clk1 to clk2, or gate off clk1
> >>>
> >>> Step 3 triggers system hang.
> >>>
> >>> If we skip step2, keep clk0 on, step 3 will not trigger system hang.
> >>> However we have CLK_OPS_PARENT_ENABLE flag, which will unprepare
> >>> disable the clk0 which will not be used.
> >>
> >> As far as I understand when switching from clk1 to clk2 this is done
> >> by temporarily switching the rightmost SELECT mux to whatever was in
> >> the spare SEL, which is essentially arbitrary from linux POV.
> >
> > No. The fixes in this patches has been confirmed by IC design owner
> >
> >>
> >> This is quite unexpected but in theory it might be desirable to use a
> >> third parent as a fallback.
> >
> > No. this will make things complicated. To CCM SEL_A and SEL_B, it is
> > controlled by a hardware counter. Saying you write n times to the
> > target interface.
> >
> > The mux will use n % 2 to choose SEL_A or SEL_B. write twice to make
> > sure SEL_A and SEL_B has the same value.
> 
> What if SEL_A and SEL_B have different values on boot? The first time linux
> does set_parent it will switch to the other SEL_X which might be off.

If SEL_A and SEL_B has different values on boot, SEL_A or SEL_B will
be effective according internal counter. There must be one
chosen for mux usage whether SEL_A or SEL_B.

The CCM ROOT slice only has SEL_A and SEL_B, no SEL_X. SEL_A and SEL_B
both have 7 mux inputs.

Thanks,
Peng.

RE: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk

[Peng Fan]

> Subject: Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite
> clk
> 
> On 2020-04-27 12:15 PM, Peng Fan wrote:
> >> Subject: Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M
> >> composite clk
> >>
> >> On 2020-03-12 12:27 PM, Peng Fan wrote:
> >>> From: Peng Fan <peng.fan@nxp.com>
> >>>
> >>> The CORE/BUS root slice has following design, simplied graph:
> >>> The difference is core not have pre_div block.
> >>> A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7].
> >>>
> >>>               SEL_A  GA
> >>>               +--+  +-+
> >>>               |  +->+ +------+
> >>> CLK[0-7]--->+  |  +-+      |
> >>>          |    |  |      +----v---+    +----+
> >>>          |    +--+      |pre_diva+---->    |  +---------+
> >>>          |              +--------+    |mux +--+post_div |
> >>>          |    +--+      |pre_divb+--->+    |  +---------+
> >>>          |    |  |      +----^---+    +----+
> >>>          +--->+  |  +-+      |
> >>>               |  +->+ +------+
> >>>               +--+  +-+
> >>>               SEL_B  GB
> >>>
> >>> There will be system hang, when doing the following steps:
> >>> 1. switch mux from clk0 to clk1
> >>> 2. gate off clk0
> >>> 3. swtich from clk1 to clk2, or gate off clk1
> >>>
> >>> Step 3 triggers system hang.
> >>>
> >>> If we skip step2, keep clk0 on, step 3 will not trigger system hang.
> >>> However we have CLK_OPS_PARENT_ENABLE flag, which will unprepare
> >>> disable the clk0 which will not be used.
> >>
> >> As far as I understand when switching from clk1 to clk2 this is done
> >> by temporarily switching the rightmost SELECT mux to whatever was in
> >> the spare SEL, which is essentially arbitrary from linux POV.
> >
> > No. The fixes in this patches has been confirmed by IC design owner
> >
> >>
> >> This is quite unexpected but in theory it might be desirable to use a
> >> third parent as a fallback.
> >
> > No. this will make things complicated. To CCM SEL_A and SEL_B, it is
> > controlled by a hardware counter. Saying you write n times to the
> > target interface.
> >
> > The mux will use n % 2 to choose SEL_A or SEL_B. write twice to make
> > sure SEL_A and SEL_B has the same value.
> 
> What if SEL_A and SEL_B have different values on boot? The first time linux
> does set_parent it will switch to the other SEL_X which might be off.

If SEL_A and SEL_B has different values on boot, SEL_A or SEL_B will
be effective according internal counter. There must be one
chosen for mux usage whether SEL_A or SEL_B.

The CCM ROOT slice only has SEL_A and SEL_B, no SEL_X. SEL_A and SEL_B
both have 7 mux inputs.

Thanks,
Peng.

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Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk

[Abel Vesa]

On 20-04-27 09:11:56, Peng Fan wrote:
> > Subject: RE: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite
> > clk
> > 
> > > From: Peng Fan <peng.fan@nxp.com>
> > > Sent: Thursday, March 12, 2020 6:20 PM
> > >
> > > The CORE/BUS root slice has following design, simplied graph:
> > > The difference is core not have pre_div block.
> > > A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7].
> > >
> > >             SEL_A  GA
> > >             +--+  +-+
> > >             |  +->+ +------+
> > > CLK[0-7]--->+  |  +-+      |
> > >        |    |  |      +----v---+    +----+
> > >        |    +--+      |pre_diva+---->    |  +---------+
> > >        |              +--------+    |mux +--+post_div |
> > >        |    +--+      |pre_divb+--->+    |  +---------+
> > >        |    |  |      +----^---+    +----+
> > >        +--->+  |  +-+      |
> > >             |  +->+ +------+
> > >             +--+  +-+
> > >             SEL_B  GB
> > >
> > > There will be system hang, when doing the following steps:
> > > 1. switch mux from clk0 to clk1
> > > 2. gate off clk0
> > > 3. swtich from clk1 to clk2, or gate off clk1
> > >
> > > Step 3 triggers system hang.
> > 
> > Why Step 3 triggers system hang? Is this a HW limitation?
> 
> It is what hardware designed.
> 
> There is a counter inside the clk root module to choose
> SEL_A or SEL_B. If choose SEL_B, the parent of SEL_B must
> be active, otherwise the change from SEL_A to SEL_B
> will cause hang.
> 
> SEL_A and SEL_B is inside the clock root module,
> It is not clk's software parentA/B. misunderstand
> this will misunderstand the whole fix.
> 
> > 
> > >
> > > If we skip step2, keep clk0 on, step 3 will not trigger system hang.
> > > However we have CLK_OPS_PARENT_ENABLE flag, which will unprepare
> > > disable the clk0 which will not be used.
> > >
> > > To address this issue, we could use following simplied software flow:
> > > After the first target register set
> > > wait the target register set finished
> > > set the target register set again
> > > wait the target register set finished
> > >
> > > The upper flow will make sure SEL_A and SEL_B both set the new mux,
> > > but with only one path gate on.
> > >
> > > And there will be no system hang anymore with step3.
> > 
> > Is this IC proposed solution?
> 
> This is what I proposed and IC team confirmed.
> 
> > 
> > >
> > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > ---
> > >
> > > V2:
> > >  Drop wait after write, add one line comment for write twice.
> > >
> > >  drivers/clk/imx/clk-composite-8m.c | 62
> > > +++++++++++++++++++++++++++++++++++++-
> > >  1 file changed, 61 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/clk/imx/clk-composite-8m.c
> > > b/drivers/clk/imx/clk-composite-8m.c
> > > index 99773519b5a5..eae02c151ced 100644
> > > --- a/drivers/clk/imx/clk-composite-8m.c
> > > +++ b/drivers/clk/imx/clk-composite-8m.c
> > > @@ -24,6 +24,12 @@
> > >
> > >  #define PCG_CGC_SHIFT		28
> > >
> > > +#define PRE_REG_OFF		0x30
> > > +#define PRE_MUXA_SHIFT		24
> > > +#define PRE_MUXA_MASK		0x7
> > > +#define PRE_MUXB_SHIFT		8
> > > +#define PRE_MUXB_MASK		0x7
> > 
> > Are those macros used somewhere?
> 
> Remove in v3.
> 
> > 
> > > +
> > >  static unsigned long imx8m_clk_composite_divider_recalc_rate(struct
> > > clk_hw *hw,
> > >  						unsigned long parent_rate)
> > >  {
> > > @@ -124,6 +130,57 @@ static const struct clk_ops
> > > imx8m_clk_composite_divider_ops = {
> > >  	.set_rate = imx8m_clk_composite_divider_set_rate,
> > >  };
> > >
> > > +static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw) {
> > > +	struct clk_mux *mux = to_clk_mux(hw);
> > > +	u32 val;
> > > +
> > > +	val = readl(mux->reg) >> mux->shift;
> > > +	val &= mux->mask;
> > > +
> > > +	return clk_mux_val_to_index(hw, mux->table, mux->flags, val); }
> > 
> > You don't have to redefinition them if they're the same as clk_mux_ops.
> > You have the access to clk_mux_ops.
> 
> This will require export_symbol of clk_mux_ops callbacks.
> 

Maybe you can do here:

return clk_mux_ops.get_parent(hw);

> > 
> > > +
> > > +static int imx8m_clk_composite_mux_set_parent(struct clk_hw *hw, u8
> > > +index) {
> > > +	struct clk_mux *mux = to_clk_mux(hw);
> > > +	u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
> > > +	unsigned long flags = 0;
> > > +	u32 reg;
> > > +
> > > +	if (mux->lock)
> > > +		spin_lock_irqsave(mux->lock, flags);
> > > +
> > > +	reg = readl(mux->reg);
> > > +	reg &= ~(mux->mask << mux->shift);
> > > +	val = val << mux->shift;
> > > +	reg |= val;
> > > +	/* write twice to make sure SEL_A/B point the same mux */
> > > +	writel(reg, mux->reg);
> > > +	writel(reg, mux->reg);
> > 
> > Why this affects both SEL_A/B?
> 
> The internal counter will make sure both SEL_A/B point
> to the same mux.
> 
> > Very tricky and may worth more comments.
> 
> Ah, I think RM should be clear about the target interface
> and non-target interface.
> 
> When you write once, saying use SEL_A, when
> you write the 2nd, the hardware will use SEL_B,
> when you write 3rd, the hardware will use SEL_A.
> and ...
> 

This is a very interesting behavior from HW point of view.
So every write changes the mux ? 

Unless there is an ERRATA for this, we'll get a lot of pushback from upstream.

> > 
> > Besides that, I'd like to see Abel's comments on this patch.
> 
> 
> Abel,
> 
>  Any comments?
> 
> Thanks,
> Peng.
> 
> > 
> > Regards
> > Aisheng
> > 
> > > +
> > > +	if (mux->lock)
> > > +		spin_unlock_irqrestore(mux->lock, flags);
> > > +
> > > +	return 0;
> > > +}
> > > +
> > > +static int
> > > +imx8m_clk_composite_mux_determine_rate(struct clk_hw *hw,
> > > +				       struct clk_rate_request *req) {
> > > +	struct clk_mux *mux = to_clk_mux(hw);
> > > +
> > > +	return clk_mux_determine_rate_flags(hw, req, mux->flags); }
> > 
> > Same as bove.
> > 
> > > +
> > > +
> > > +const struct clk_ops imx8m_clk_composite_mux_ops = {
> > > +	.get_parent = imx8m_clk_composite_mux_get_parent,
> > > +	.set_parent = imx8m_clk_composite_mux_set_parent,
> > > +	.determine_rate = imx8m_clk_composite_mux_determine_rate,
> > > +};
> > > +
> > >  struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
> > >  					const char * const *parent_names,
> > >  					int num_parents, void __iomem *reg, @@ -136,6
> > > +193,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char
> > > +*name,
> > >  	struct clk_gate *gate = NULL;
> > >  	struct clk_mux *mux = NULL;
> > >  	const struct clk_ops *divider_ops;
> > > +	const struct clk_ops *mux_ops;
> > >
> > >  	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
> > >  	if (!mux)
> > > @@ -157,10 +215,12 @@ struct clk_hw
> > > *imx8m_clk_hw_composite_flags(const char *name,
> > >  		div->shift = PCG_DIV_SHIFT;
> > >  		div->width = PCG_CORE_DIV_WIDTH;
> > >  		divider_ops = &clk_divider_ops;
> > > +		mux_ops = &imx8m_clk_composite_mux_ops;
> > >  	} else {
> > >  		div->shift = PCG_PREDIV_SHIFT;
> > >  		div->width = PCG_PREDIV_WIDTH;
> > >  		divider_ops = &imx8m_clk_composite_divider_ops;
> > > +		mux_ops = &clk_mux_ops;
> > >  	}
> > >
> > >  	div->lock = &imx_ccm_lock;
> > > @@ -176,7 +236,7 @@ struct clk_hw
> > *imx8m_clk_hw_composite_flags(const
> > > char *name,
> > >  	gate->lock = &imx_ccm_lock;
> > >
> > >  	hw = clk_hw_register_composite(NULL, name, parent_names,
> > > num_parents,
> > > -			mux_hw, &clk_mux_ops, div_hw,
> > > +			mux_hw, mux_ops, div_hw,
> > >  			divider_ops, gate_hw, &clk_gate_ops, flags);
> > >  	if (IS_ERR(hw))
> > >  		goto fail;
> > > --
> > > 2.16.4
> 

Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk

[Abel Vesa]

On 20-04-27 09:11:56, Peng Fan wrote:
> > Subject: RE: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite
> > clk
> > 
> > > From: Peng Fan <peng.fan@nxp.com>
> > > Sent: Thursday, March 12, 2020 6:20 PM
> > >
> > > The CORE/BUS root slice has following design, simplied graph:
> > > The difference is core not have pre_div block.
> > > A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7].
> > >
> > >             SEL_A  GA
> > >             +--+  +-+
> > >             |  +->+ +------+
> > > CLK[0-7]--->+  |  +-+      |
> > >        |    |  |      +----v---+    +----+
> > >        |    +--+      |pre_diva+---->    |  +---------+
> > >        |              +--------+    |mux +--+post_div |
> > >        |    +--+      |pre_divb+--->+    |  +---------+
> > >        |    |  |      +----^---+    +----+
> > >        +--->+  |  +-+      |
> > >             |  +->+ +------+
> > >             +--+  +-+
> > >             SEL_B  GB
> > >
> > > There will be system hang, when doing the following steps:
> > > 1. switch mux from clk0 to clk1
> > > 2. gate off clk0
> > > 3. swtich from clk1 to clk2, or gate off clk1
> > >
> > > Step 3 triggers system hang.
> > 
> > Why Step 3 triggers system hang? Is this a HW limitation?
> 
> It is what hardware designed.
> 
> There is a counter inside the clk root module to choose
> SEL_A or SEL_B. If choose SEL_B, the parent of SEL_B must
> be active, otherwise the change from SEL_A to SEL_B
> will cause hang.
> 
> SEL_A and SEL_B is inside the clock root module,
> It is not clk's software parentA/B. misunderstand
> this will misunderstand the whole fix.
> 
> > 
> > >
> > > If we skip step2, keep clk0 on, step 3 will not trigger system hang.
> > > However we have CLK_OPS_PARENT_ENABLE flag, which will unprepare
> > > disable the clk0 which will not be used.
> > >
> > > To address this issue, we could use following simplied software flow:
> > > After the first target register set
> > > wait the target register set finished
> > > set the target register set again
> > > wait the target register set finished
> > >
> > > The upper flow will make sure SEL_A and SEL_B both set the new mux,
> > > but with only one path gate on.
> > >
> > > And there will be no system hang anymore with step3.
> > 
> > Is this IC proposed solution?
> 
> This is what I proposed and IC team confirmed.
> 
> > 
> > >
> > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > ---
> > >
> > > V2:
> > >  Drop wait after write, add one line comment for write twice.
> > >
> > >  drivers/clk/imx/clk-composite-8m.c | 62
> > > +++++++++++++++++++++++++++++++++++++-
> > >  1 file changed, 61 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/clk/imx/clk-composite-8m.c
> > > b/drivers/clk/imx/clk-composite-8m.c
> > > index 99773519b5a5..eae02c151ced 100644
> > > --- a/drivers/clk/imx/clk-composite-8m.c
> > > +++ b/drivers/clk/imx/clk-composite-8m.c
> > > @@ -24,6 +24,12 @@
> > >
> > >  #define PCG_CGC_SHIFT		28
> > >
> > > +#define PRE_REG_OFF		0x30
> > > +#define PRE_MUXA_SHIFT		24
> > > +#define PRE_MUXA_MASK		0x7
> > > +#define PRE_MUXB_SHIFT		8
> > > +#define PRE_MUXB_MASK		0x7
> > 
> > Are those macros used somewhere?
> 
> Remove in v3.
> 
> > 
> > > +
> > >  static unsigned long imx8m_clk_composite_divider_recalc_rate(struct
> > > clk_hw *hw,
> > >  						unsigned long parent_rate)
> > >  {
> > > @@ -124,6 +130,57 @@ static const struct clk_ops
> > > imx8m_clk_composite_divider_ops = {
> > >  	.set_rate = imx8m_clk_composite_divider_set_rate,
> > >  };
> > >
> > > +static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw) {
> > > +	struct clk_mux *mux = to_clk_mux(hw);
> > > +	u32 val;
> > > +
> > > +	val = readl(mux->reg) >> mux->shift;
> > > +	val &= mux->mask;
> > > +
> > > +	return clk_mux_val_to_index(hw, mux->table, mux->flags, val); }
> > 
> > You don't have to redefinition them if they're the same as clk_mux_ops.
> > You have the access to clk_mux_ops.
> 
> This will require export_symbol of clk_mux_ops callbacks.
> 

Maybe you can do here:

return clk_mux_ops.get_parent(hw);

> > 
> > > +
> > > +static int imx8m_clk_composite_mux_set_parent(struct clk_hw *hw, u8
> > > +index) {
> > > +	struct clk_mux *mux = to_clk_mux(hw);
> > > +	u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
> > > +	unsigned long flags = 0;
> > > +	u32 reg;
> > > +
> > > +	if (mux->lock)
> > > +		spin_lock_irqsave(mux->lock, flags);
> > > +
> > > +	reg = readl(mux->reg);
> > > +	reg &= ~(mux->mask << mux->shift);
> > > +	val = val << mux->shift;
> > > +	reg |= val;
> > > +	/* write twice to make sure SEL_A/B point the same mux */
> > > +	writel(reg, mux->reg);
> > > +	writel(reg, mux->reg);
> > 
> > Why this affects both SEL_A/B?
> 
> The internal counter will make sure both SEL_A/B point
> to the same mux.
> 
> > Very tricky and may worth more comments.
> 
> Ah, I think RM should be clear about the target interface
> and non-target interface.
> 
> When you write once, saying use SEL_A, when
> you write the 2nd, the hardware will use SEL_B,
> when you write 3rd, the hardware will use SEL_A.
> and ...
> 

This is a very interesting behavior from HW point of view.
So every write changes the mux ? 

Unless there is an ERRATA for this, we'll get a lot of pushback from upstream.

> > 
> > Besides that, I'd like to see Abel's comments on this patch.
> 
> 
> Abel,
> 
>  Any comments?
> 
> Thanks,
> Peng.
> 
> > 
> > Regards
> > Aisheng
> > 
> > > +
> > > +	if (mux->lock)
> > > +		spin_unlock_irqrestore(mux->lock, flags);
> > > +
> > > +	return 0;
> > > +}
> > > +
> > > +static int
> > > +imx8m_clk_composite_mux_determine_rate(struct clk_hw *hw,
> > > +				       struct clk_rate_request *req) {
> > > +	struct clk_mux *mux = to_clk_mux(hw);
> > > +
> > > +	return clk_mux_determine_rate_flags(hw, req, mux->flags); }
> > 
> > Same as bove.
> > 
> > > +
> > > +
> > > +const struct clk_ops imx8m_clk_composite_mux_ops = {
> > > +	.get_parent = imx8m_clk_composite_mux_get_parent,
> > > +	.set_parent = imx8m_clk_composite_mux_set_parent,
> > > +	.determine_rate = imx8m_clk_composite_mux_determine_rate,
> > > +};
> > > +
> > >  struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
> > >  					const char * const *parent_names,
> > >  					int num_parents, void __iomem *reg, @@ -136,6
> > > +193,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char
> > > +*name,
> > >  	struct clk_gate *gate = NULL;
> > >  	struct clk_mux *mux = NULL;
> > >  	const struct clk_ops *divider_ops;
> > > +	const struct clk_ops *mux_ops;
> > >
> > >  	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
> > >  	if (!mux)
> > > @@ -157,10 +215,12 @@ struct clk_hw
> > > *imx8m_clk_hw_composite_flags(const char *name,
> > >  		div->shift = PCG_DIV_SHIFT;
> > >  		div->width = PCG_CORE_DIV_WIDTH;
> > >  		divider_ops = &clk_divider_ops;
> > > +		mux_ops = &imx8m_clk_composite_mux_ops;
> > >  	} else {
> > >  		div->shift = PCG_PREDIV_SHIFT;
> > >  		div->width = PCG_PREDIV_WIDTH;
> > >  		divider_ops = &imx8m_clk_composite_divider_ops;
> > > +		mux_ops = &clk_mux_ops;
> > >  	}
> > >
> > >  	div->lock = &imx_ccm_lock;
> > > @@ -176,7 +236,7 @@ struct clk_hw
> > *imx8m_clk_hw_composite_flags(const
> > > char *name,
> > >  	gate->lock = &imx_ccm_lock;
> > >
> > >  	hw = clk_hw_register_composite(NULL, name, parent_names,
> > > num_parents,
> > > -			mux_hw, &clk_mux_ops, div_hw,
> > > +			mux_hw, mux_ops, div_hw,
> > >  			divider_ops, gate_hw, &clk_gate_ops, flags);
> > >  	if (IS_ERR(hw))
> > >  		goto fail;
> > > --
> > > 2.16.4
> 

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RE: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk

[Peng Fan]

Hi Abel, Aisheng, Leonard and all

> Subject: Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite
> clk
> 
....
> > > > +
> > > > +	return clk_mux_val_to_index(hw, mux->table, mux->flags, val); }
> > >
> > > You don't have to redefinition them if they're the same as clk_mux_ops.
> > > You have the access to clk_mux_ops.
> >
> > This will require export_symbol of clk_mux_ops callbacks.
> >
> 
> Maybe you can do here:
> 
> return clk_mux_ops.get_parent(hw);

Ok, will try this.

> 
> > >
> > > > +
> > > > +static int imx8m_clk_composite_mux_set_parent(struct clk_hw *hw,
> > > > +u8
> > > > +index) {
> > > > +	struct clk_mux *mux = to_clk_mux(hw);
> > > > +	u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
> > > > +	unsigned long flags = 0;
> > > > +	u32 reg;
> > > > +
> > > > +	if (mux->lock)
> > > > +		spin_lock_irqsave(mux->lock, flags);
> > > > +
> > > > +	reg = readl(mux->reg);
> > > > +	reg &= ~(mux->mask << mux->shift);
> > > > +	val = val << mux->shift;
> > > > +	reg |= val;
> > > > +	/* write twice to make sure SEL_A/B point the same mux */
> > > > +	writel(reg, mux->reg);
> > > > +	writel(reg, mux->reg);
> > >
> > > Why this affects both SEL_A/B?
> >
> > The internal counter will make sure both SEL_A/B point to the same
> > mux.
> >
> > > Very tricky and may worth more comments.
> >
> > Ah, I think RM should be clear about the target interface and
> > non-target interface.
> >
> > When you write once, saying use SEL_A, when you write the 2nd, the
> > hardware will use SEL_B, when you write 3rd, the hardware will use
> > SEL_A.
> > and ...
> >
> 
> This is a very interesting behavior from HW point of view.
> So every write changes the mux ?
> 
> Unless there is an ERRATA for this, we'll get a lot of pushback from upstream.

Let me share more details about this. Then if ok, I'll put in commit log and post
V2.

There is no errata, this is the hardware designed as is and it exist since i.MX7D.
i.MX8M and i.MX7D using same CCM root design.

It support target(smart) interface and normal interface. Target interface is exported
for programmer easy to configure ccm root. Normal interface is also
exported, but we not use it in our driver, because it will introduce more
complexity compared with target interface.

From RM:
"
The Target Interface is optimized to simplify software operation. Using this interface, all
clock roots are in the same program model with the same register bit field mapping. The
software does not handle the details of the clock slice and clock slice types. Software
writes the desired settings to the register, and the internal hardware logic generates a
required sequence to achieve the desired settings.
"

From i.MX8MN RM:
"
A requirement of the Target Interface's software is that the
target clock source is active.
"

We touch target interface, but hardware logic actually also need configure normal interface.

I draw a simple normal interface for core clock slice pic:

CLK[0-7] --------->SEL_A ----->-----CG---->|
         |                        \
         |                          mux-->post_podf-->
         V                        /                   
         |------>SEL_B------>---CG---->| /


The mux in the upper pic is not the target interface MUX, target interface MUX is
hiding SEL_A and SEL_B. When you choose clk[0-7], you are actually writing
SEL_A or SEL_B depends on the internal counter which will also control the
internal "mux".

Whether the hardware touch SEL_A or SEL_B, it requires the clock input to
SEL_A or SEL_B must be active. However SEL_A and SEL_B could have
different value. Saying SEL_A is clk1, SEL_B is clk4, the internal counter
controlled automatically by hardware logic choose SEL_A, then Linux will
disable clk4 because of no user. Now we write target MUX to choose clk5,
the internal counter will configure SEL_B to clk5 and switch to SEL_B,
however the previous SEL_B input clk4 is off, system hang, the hardware
requires SEL_B input clk4 is on, then hardware could configure SEL_B to
clk5.

That's why write twice to make sure the internal counter could select
SEL_A and SEL_B to same active input clk.

Please see whether this clarify the issue or not. I could post the upper
into commit log in V3. The fixes needs to be into 5.7 to avoid system
boot hang.

Thanks,
Peng.

> 
> > >
> > > Besides that, I'd like to see Abel's comments on this patch.
> >
> >
> > Abel,
> >
> >  Any comments?
> >
> > Thanks,
> > Peng.
> >
> > >
> > > Regards
> > > Aisheng
> > >
> > > > +
> > > > +	if (mux->lock)
> > > > +		spin_unlock_irqrestore(mux->lock, flags);
> > > > +
> > > > +	return 0;
> > > > +}
> > > > +
> > > > +static int
> > > > +imx8m_clk_composite_mux_determine_rate(struct clk_hw *hw,
> > > > +				       struct clk_rate_request *req) {
> > > > +	struct clk_mux *mux = to_clk_mux(hw);
> > > > +
> > > > +	return clk_mux_determine_rate_flags(hw, req, mux->flags); }
> > >
> > > Same as bove.
> > >
> > > > +
> > > > +
> > > > +const struct clk_ops imx8m_clk_composite_mux_ops = {
> > > > +	.get_parent = imx8m_clk_composite_mux_get_parent,
> > > > +	.set_parent = imx8m_clk_composite_mux_set_parent,
> > > > +	.determine_rate = imx8m_clk_composite_mux_determine_rate,
> > > > +};
> > > > +
> > > >  struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
> > > >  					const char * const *parent_names,
> > > >  					int num_parents, void __iomem *reg, @@
> -136,6
> > > > +193,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char
> > > > +*name,
> > > >  	struct clk_gate *gate = NULL;
> > > >  	struct clk_mux *mux = NULL;
> > > >  	const struct clk_ops *divider_ops;
> > > > +	const struct clk_ops *mux_ops;
> > > >
> > > >  	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
> > > >  	if (!mux)
> > > > @@ -157,10 +215,12 @@ struct clk_hw
> > > > *imx8m_clk_hw_composite_flags(const char *name,
> > > >  		div->shift = PCG_DIV_SHIFT;
> > > >  		div->width = PCG_CORE_DIV_WIDTH;
> > > >  		divider_ops = &clk_divider_ops;
> > > > +		mux_ops = &imx8m_clk_composite_mux_ops;
> > > >  	} else {
> > > >  		div->shift = PCG_PREDIV_SHIFT;
> > > >  		div->width = PCG_PREDIV_WIDTH;
> > > >  		divider_ops = &imx8m_clk_composite_divider_ops;
> > > > +		mux_ops = &clk_mux_ops;
> > > >  	}
> > > >
> > > >  	div->lock = &imx_ccm_lock;
> > > > @@ -176,7 +236,7 @@ struct clk_hw
> > > *imx8m_clk_hw_composite_flags(const
> > > > char *name,
> > > >  	gate->lock = &imx_ccm_lock;
> > > >
> > > >  	hw = clk_hw_register_composite(NULL, name, parent_names,
> > > > num_parents,
> > > > -			mux_hw, &clk_mux_ops, div_hw,
> > > > +			mux_hw, mux_ops, div_hw,
> > > >  			divider_ops, gate_hw, &clk_gate_ops, flags);
> > > >  	if (IS_ERR(hw))
> > > >  		goto fail;
> > > > --
> > > > 2.16.4
> >

RE: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk

[Peng Fan]

Hi Abel, Aisheng, Leonard and all

> Subject: Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite
> clk
> 
....
> > > > +
> > > > +	return clk_mux_val_to_index(hw, mux->table, mux->flags, val); }
> > >
> > > You don't have to redefinition them if they're the same as clk_mux_ops.
> > > You have the access to clk_mux_ops.
> >
> > This will require export_symbol of clk_mux_ops callbacks.
> >
> 
> Maybe you can do here:
> 
> return clk_mux_ops.get_parent(hw);

Ok, will try this.

> 
> > >
> > > > +
> > > > +static int imx8m_clk_composite_mux_set_parent(struct clk_hw *hw,
> > > > +u8
> > > > +index) {
> > > > +	struct clk_mux *mux = to_clk_mux(hw);
> > > > +	u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
> > > > +	unsigned long flags = 0;
> > > > +	u32 reg;
> > > > +
> > > > +	if (mux->lock)
> > > > +		spin_lock_irqsave(mux->lock, flags);
> > > > +
> > > > +	reg = readl(mux->reg);
> > > > +	reg &= ~(mux->mask << mux->shift);
> > > > +	val = val << mux->shift;
> > > > +	reg |= val;
> > > > +	/* write twice to make sure SEL_A/B point the same mux */
> > > > +	writel(reg, mux->reg);
> > > > +	writel(reg, mux->reg);
> > >
> > > Why this affects both SEL_A/B?
> >
> > The internal counter will make sure both SEL_A/B point to the same
> > mux.
> >
> > > Very tricky and may worth more comments.
> >
> > Ah, I think RM should be clear about the target interface and
> > non-target interface.
> >
> > When you write once, saying use SEL_A, when you write the 2nd, the
> > hardware will use SEL_B, when you write 3rd, the hardware will use
> > SEL_A.
> > and ...
> >
> 
> This is a very interesting behavior from HW point of view.
> So every write changes the mux ?
> 
> Unless there is an ERRATA for this, we'll get a lot of pushback from upstream.

Let me share more details about this. Then if ok, I'll put in commit log and post
V2.

There is no errata, this is the hardware designed as is and it exist since i.MX7D.
i.MX8M and i.MX7D using same CCM root design.

It support target(smart) interface and normal interface. Target interface is exported
for programmer easy to configure ccm root. Normal interface is also
exported, but we not use it in our driver, because it will introduce more
complexity compared with target interface.

From RM:
"
The Target Interface is optimized to simplify software operation. Using this interface, all
clock roots are in the same program model with the same register bit field mapping. The
software does not handle the details of the clock slice and clock slice types. Software
writes the desired settings to the register, and the internal hardware logic generates a
required sequence to achieve the desired settings.
"

From i.MX8MN RM:
"
A requirement of the Target Interface's software is that the
target clock source is active.
"

We touch target interface, but hardware logic actually also need configure normal interface.

I draw a simple normal interface for core clock slice pic:

CLK[0-7] --------->SEL_A ----->-----CG---->|
         |                        \
         |                          mux-->post_podf-->
         V                        /                   
         |------>SEL_B------>---CG---->| /


The mux in the upper pic is not the target interface MUX, target interface MUX is
hiding SEL_A and SEL_B. When you choose clk[0-7], you are actually writing
SEL_A or SEL_B depends on the internal counter which will also control the
internal "mux".

Whether the hardware touch SEL_A or SEL_B, it requires the clock input to
SEL_A or SEL_B must be active. However SEL_A and SEL_B could have
different value. Saying SEL_A is clk1, SEL_B is clk4, the internal counter
controlled automatically by hardware logic choose SEL_A, then Linux will
disable clk4 because of no user. Now we write target MUX to choose clk5,
the internal counter will configure SEL_B to clk5 and switch to SEL_B,
however the previous SEL_B input clk4 is off, system hang, the hardware
requires SEL_B input clk4 is on, then hardware could configure SEL_B to
clk5.

That's why write twice to make sure the internal counter could select
SEL_A and SEL_B to same active input clk.

Please see whether this clarify the issue or not. I could post the upper
into commit log in V3. The fixes needs to be into 5.7 to avoid system
boot hang.

Thanks,
Peng.

> 
> > >
> > > Besides that, I'd like to see Abel's comments on this patch.
> >
> >
> > Abel,
> >
> >  Any comments?
> >
> > Thanks,
> > Peng.
> >
> > >
> > > Regards
> > > Aisheng
> > >
> > > > +
> > > > +	if (mux->lock)
> > > > +		spin_unlock_irqrestore(mux->lock, flags);
> > > > +
> > > > +	return 0;
> > > > +}
> > > > +
> > > > +static int
> > > > +imx8m_clk_composite_mux_determine_rate(struct clk_hw *hw,
> > > > +				       struct clk_rate_request *req) {
> > > > +	struct clk_mux *mux = to_clk_mux(hw);
> > > > +
> > > > +	return clk_mux_determine_rate_flags(hw, req, mux->flags); }
> > >
> > > Same as bove.
> > >
> > > > +
> > > > +
> > > > +const struct clk_ops imx8m_clk_composite_mux_ops = {
> > > > +	.get_parent = imx8m_clk_composite_mux_get_parent,
> > > > +	.set_parent = imx8m_clk_composite_mux_set_parent,
> > > > +	.determine_rate = imx8m_clk_composite_mux_determine_rate,
> > > > +};
> > > > +
> > > >  struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
> > > >  					const char * const *parent_names,
> > > >  					int num_parents, void __iomem *reg, @@
> -136,6
> > > > +193,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char
> > > > +*name,
> > > >  	struct clk_gate *gate = NULL;
> > > >  	struct clk_mux *mux = NULL;
> > > >  	const struct clk_ops *divider_ops;
> > > > +	const struct clk_ops *mux_ops;
> > > >
> > > >  	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
> > > >  	if (!mux)
> > > > @@ -157,10 +215,12 @@ struct clk_hw
> > > > *imx8m_clk_hw_composite_flags(const char *name,
> > > >  		div->shift = PCG_DIV_SHIFT;
> > > >  		div->width = PCG_CORE_DIV_WIDTH;
> > > >  		divider_ops = &clk_divider_ops;
> > > > +		mux_ops = &imx8m_clk_composite_mux_ops;
> > > >  	} else {
> > > >  		div->shift = PCG_PREDIV_SHIFT;
> > > >  		div->width = PCG_PREDIV_WIDTH;
> > > >  		divider_ops = &imx8m_clk_composite_divider_ops;
> > > > +		mux_ops = &clk_mux_ops;
> > > >  	}
> > > >
> > > >  	div->lock = &imx_ccm_lock;
> > > > @@ -176,7 +236,7 @@ struct clk_hw
> > > *imx8m_clk_hw_composite_flags(const
> > > > char *name,
> > > >  	gate->lock = &imx_ccm_lock;
> > > >
> > > >  	hw = clk_hw_register_composite(NULL, name, parent_names,
> > > > num_parents,
> > > > -			mux_hw, &clk_mux_ops, div_hw,
> > > > +			mux_hw, mux_ops, div_hw,
> > > >  			divider_ops, gate_hw, &clk_gate_ops, flags);
> > > >  	if (IS_ERR(hw))
> > > >  		goto fail;
> > > > --
> > > > 2.16.4
> >

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