* [Intel-gfx] [PATCH] drm/i915/tgl: Put HDC flush pipe_control bit in the right dword
@ 2020-05-05 0:01 D Scott Phillips
2020-05-05 0:09 ` D Scott Phillips
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: D Scott Phillips @ 2020-05-05 0:01 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Previously we set HDC_PIPELINE_FLUSH in dword 1 of gen12
pipe_control commands. HDC Pipeline flush actually resides in
dword 0, and the bit we were setting in dword 1 was Indirect State
Pointers Disable, which invalidates indirect state in the render
context. This causes failures for userspace, as things like push
constant state gets invalidated.
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: D Scott Phillips <d.scott.phillips@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine.h | 23 +++++++++++++++++------
drivers/gpu/drm/i915/gt/intel_lrc.c | 11 ++++++-----
2 files changed, 23 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 19d0b8830905..8338be338ec8 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -241,19 +241,24 @@ void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
void intel_engine_print_breadcrumbs(struct intel_engine_cs *engine,
struct drm_printer *p);
-static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
+static inline u32 *gen12_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset)
{
memset(batch, 0, 6 * sizeof(u32));
- batch[0] = GFX_OP_PIPE_CONTROL(6);
- batch[1] = flags;
+ batch[0] = GFX_OP_PIPE_CONTROL(6) | flags0;
+ batch[1] = flags1;
batch[2] = offset;
return batch + 6;
}
+static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
+{
+ return gen12_emit_pipe_control(batch, 0, flags, offset);
+}
+
static inline u32 *
-gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
+gen12_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32 flags1)
{
/* We're using qword write, offset should be aligned to 8 bytes. */
GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
@@ -262,8 +267,8 @@ gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
* need a prior CS_STALL, which is emitted by the flush
* following the batch.
*/
- *cs++ = GFX_OP_PIPE_CONTROL(6);
- *cs++ = flags | PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_GLOBAL_GTT_IVB;
+ *cs++ = GFX_OP_PIPE_CONTROL(6) | flags0;
+ *cs++ = flags1 | PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_GLOBAL_GTT_IVB;
*cs++ = gtt_offset;
*cs++ = 0;
*cs++ = value;
@@ -273,6 +278,12 @@ gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
return cs;
}
+static inline u32 *
+gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
+{
+ return gen12_emit_ggtt_write_rcs(cs, value, gtt_offset, 0, flags);
+}
+
static inline u32 *
gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index d4ef344657b0..af7790ac9f6a 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4549,6 +4549,7 @@ static int gen12_emit_flush_render(struct i915_request *request,
u32 mode)
{
if (mode & EMIT_FLUSH) {
+ u32 flags0 = 0;
u32 flags = 0;
u32 *cs;
@@ -4559,7 +4560,7 @@ static int gen12_emit_flush_render(struct i915_request *request,
flags |= PIPE_CONTROL_DEPTH_STALL;
flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
flags |= PIPE_CONTROL_FLUSH_ENABLE;
- flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
+ flags0 |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
flags |= PIPE_CONTROL_STORE_DATA_INDEX;
flags |= PIPE_CONTROL_QW_WRITE;
@@ -4570,7 +4571,7 @@ static int gen12_emit_flush_render(struct i915_request *request,
if (IS_ERR(cs))
return PTR_ERR(cs);
- cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
+ cs = gen12_emit_pipe_control(cs, flags0, flags, LRC_PPHWSP_SCRATCH_ADDR);
intel_ring_advance(request, cs);
}
@@ -4762,9 +4763,10 @@ static u32 *gen12_emit_fini_breadcrumb(struct i915_request *request, u32 *cs)
static u32 *
gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
{
- cs = gen8_emit_ggtt_write_rcs(cs,
+ cs = gen12_emit_ggtt_write_rcs(cs,
request->fence.seqno,
i915_request_active_timeline(request)->hwsp_offset,
+ PIPE_CONTROL_HDC_PIPELINE_FLUSH,
PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_TILE_CACHE_FLUSH |
PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
@@ -4772,8 +4774,7 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
/* Wa_1409600907:tgl */
PIPE_CONTROL_DEPTH_STALL |
PIPE_CONTROL_DC_FLUSH_ENABLE |
- PIPE_CONTROL_FLUSH_ENABLE |
- PIPE_CONTROL_HDC_PIPELINE_FLUSH);
+ PIPE_CONTROL_FLUSH_ENABLE);
return gen12_emit_fini_breadcrumb_footer(request, cs);
}
--
2.25.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/tgl: Put HDC flush pipe_control bit in the right dword
2020-05-05 0:01 [Intel-gfx] [PATCH] drm/i915/tgl: Put HDC flush pipe_control bit in the right dword D Scott Phillips
@ 2020-05-05 0:09 ` D Scott Phillips
2020-05-05 7:27 ` Lionel Landwerlin
2020-05-05 0:25 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (3 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: D Scott Phillips @ 2020-05-05 0:09 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
D Scott Phillips <d.scott.phillips@intel.com> writes:
> Previously we set HDC_PIPELINE_FLUSH in dword 1 of gen12
> pipe_control commands. HDC Pipeline flush actually resides in
> dword 0, and the bit we were setting in dword 1 was Indirect State
> Pointers Disable, which invalidates indirect state in the render
> context. This causes failures for userspace, as things like push
> constant state gets invalidated.
>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: D Scott Phillips <d.scott.phillips@intel.com>
also,
Fixes: 4aa0b5d457f5 ("drm/i915/tgl: Add HDC Pipeline Flush")
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: Put HDC flush pipe_control bit in the right dword
2020-05-05 0:01 [Intel-gfx] [PATCH] drm/i915/tgl: Put HDC flush pipe_control bit in the right dword D Scott Phillips
2020-05-05 0:09 ` D Scott Phillips
@ 2020-05-05 0:25 ` Patchwork
2020-05-05 0:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2020-05-05 0:25 UTC (permalink / raw)
To: D Scott Phillips; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: Put HDC flush pipe_control bit in the right dword
URL : https://patchwork.freedesktop.org/series/76925/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f3eb1ee5e0b9 drm/i915/tgl: Put HDC flush pipe_control bit in the right dword
-:112: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#112: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:4767:
+ cs = gen12_emit_ggtt_write_rcs(cs,
request->fence.seqno,
total: 0 errors, 0 warnings, 1 checks, 93 lines checked
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Put HDC flush pipe_control bit in the right dword
2020-05-05 0:01 [Intel-gfx] [PATCH] drm/i915/tgl: Put HDC flush pipe_control bit in the right dword D Scott Phillips
2020-05-05 0:09 ` D Scott Phillips
2020-05-05 0:25 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2020-05-05 0:48 ` Patchwork
2020-05-05 0:57 ` [Intel-gfx] [PATCH] " Kenneth Graunke
2020-05-05 14:17 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2020-05-05 0:48 UTC (permalink / raw)
To: D Scott Phillips; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: Put HDC flush pipe_control bit in the right dword
URL : https://patchwork.freedesktop.org/series/76925/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8424 -> Patchwork_17578
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/index.html
Known issues
------------
Here are the changes found in Patchwork_17578 that come from known issues:
### IGT changes ###
#### Warnings ####
* igt@i915_pm_rpm@module-reload:
- fi-kbl-x1275: [FAIL][1] ([i915#62]) -> [SKIP][2] ([fdo#109271])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
Participating hosts (51 -> 44)
------------------------------
Additional (1): fi-kbl-7560u
Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-tgl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8424 -> Patchwork_17578
CI-20190529: 20190529
CI_DRM_8424: 69ecf47ef1aabcdc8a4e070584d0a717bbabf4fe @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5628: 652a3fd8966345fa5498904ce80a2027a6782783 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17578: f3eb1ee5e0b9a5156d1253dc3dbf86049d9d4d69 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f3eb1ee5e0b9 drm/i915/tgl: Put HDC flush pipe_control bit in the right dword
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/index.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/tgl: Put HDC flush pipe_control bit in the right dword
2020-05-05 0:01 [Intel-gfx] [PATCH] drm/i915/tgl: Put HDC flush pipe_control bit in the right dword D Scott Phillips
` (2 preceding siblings ...)
2020-05-05 0:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-05-05 0:57 ` Kenneth Graunke
2020-05-05 14:17 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
4 siblings, 0 replies; 8+ messages in thread
From: Kenneth Graunke @ 2020-05-05 0:57 UTC (permalink / raw)
To: intel-gfx, D Scott Phillips; +Cc: Chris Wilson
[-- Attachment #1.1: Type: text/plain, Size: 1926 bytes --]
On Monday, May 4, 2020 5:01:46 PM PDT D Scott Phillips wrote:
> Previously we set HDC_PIPELINE_FLUSH in dword 1 of gen12
> pipe_control commands. HDC Pipeline flush actually resides in
> dword 0, and the bit we were setting in dword 1 was Indirect State
> Pointers Disable, which invalidates indirect state in the render
> context. This causes failures for userspace, as things like push
> constant state gets invalidated.
>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: D Scott Phillips <d.scott.phillips@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine.h | 23 +++++++++++++++++------
> drivers/gpu/drm/i915/gt/intel_lrc.c | 11 ++++++-----
> 2 files changed, 23 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
> index 19d0b8830905..8338be338ec8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -241,19 +241,24 @@ void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
> void intel_engine_print_breadcrumbs(struct intel_engine_cs *engine,
> struct drm_printer *p);
>
> -static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
> +static inline u32 *gen12_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset)
Great find! It looks like HDC_PIPELINE_FLUSH moved from bit 41 to bit 9
even on Icelake / Gen11 - so it might make sense to call this
gen11_emit_pipe_control() and use it on the Icelake functions.
That said, i915 never sets HDC_PIPELINE_FLUSH until Gen12, so we don't
actually have a bug to fix on Icelake today. But if someone started
trying to set it on Gen11, we would have a bug - hence the suggestion.
With or without any changes,
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
and thanks so much for tracking this down!
[-- Attachment #1.2: This is a digitally signed message part. --]
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[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/tgl: Put HDC flush pipe_control bit in the right dword
2020-05-05 0:09 ` D Scott Phillips
@ 2020-05-05 7:27 ` Lionel Landwerlin
2020-05-05 16:32 ` D Scott Phillips
0 siblings, 1 reply; 8+ messages in thread
From: Lionel Landwerlin @ 2020-05-05 7:27 UTC (permalink / raw)
To: D Scott Phillips, intel-gfx; +Cc: Chris Wilson
On 05/05/2020 03:09, D Scott Phillips wrote:
> D Scott Phillips <d.scott.phillips@intel.com> writes:
>
>> Previously we set HDC_PIPELINE_FLUSH in dword 1 of gen12
>> pipe_control commands. HDC Pipeline flush actually resides in
>> dword 0, and the bit we were setting in dword 1 was Indirect State
>> Pointers Disable, which invalidates indirect state in the render
>> context. This causes failures for userspace, as things like push
>> constant state gets invalidated.
>>
>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Signed-off-by: D Scott Phillips <d.scott.phillips@intel.com>
> also,
>
> Fixes: 4aa0b5d457f5 ("drm/i915/tgl: Add HDC Pipeline Flush")
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
I think Mika sent the same patch in "drm/i915/gen12: Fix HDC pipeline
flush".
-Lionel
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tgl: Put HDC flush pipe_control bit in the right dword
2020-05-05 0:01 [Intel-gfx] [PATCH] drm/i915/tgl: Put HDC flush pipe_control bit in the right dword D Scott Phillips
` (3 preceding siblings ...)
2020-05-05 0:57 ` [Intel-gfx] [PATCH] " Kenneth Graunke
@ 2020-05-05 14:17 ` Patchwork
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2020-05-05 14:17 UTC (permalink / raw)
To: D Scott Phillips; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: Put HDC flush pipe_control bit in the right dword
URL : https://patchwork.freedesktop.org/series/76925/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8424_full -> Patchwork_17578_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_17578_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@legacy-engines-mixed-process@render:
- shard-skl: [PASS][1] -> [FAIL][2] ([i915#1528])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-skl10/igt@gem_ctx_persistence@legacy-engines-mixed-process@render.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/shard-skl5/igt@gem_ctx_persistence@legacy-engines-mixed-process@render.html
* igt@gem_exec_fence@basic-await@vcs0:
- shard-skl: [PASS][3] -> [FAIL][4] ([i915#1472]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-skl8/igt@gem_exec_fence@basic-await@vcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/shard-skl1/igt@gem_exec_fence@basic-await@vcs0.html
* igt@gem_exec_params@invalid-bsd-ring:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-iclb4/igt@gem_exec_params@invalid-bsd-ring.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/shard-iclb7/igt@gem_exec_params@invalid-bsd-ring.html
* igt@i915_suspend@fence-restore-untiled:
- shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-kbl7/igt@i915_suspend@fence-restore-untiled.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/shard-kbl4/igt@i915_suspend@fence-restore-untiled.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-apl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge:
- shard-apl: [PASS][11] -> [FAIL][12] ([i915#70] / [i915#95])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-apl4/igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/shard-apl4/igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge.html
* igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled:
- shard-skl: [PASS][13] -> [FAIL][14] ([i915#177] / [i915#52] / [i915#54])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-skl1/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/shard-skl8/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled.html
* igt@kms_flip_tiling@flip-changes-tiling-y:
- shard-apl: [PASS][15] -> [FAIL][16] ([i915#95])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-apl6/igt@kms_flip_tiling@flip-changes-tiling-y.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/shard-apl3/igt@kms_flip_tiling@flip-changes-tiling-y.html
- shard-kbl: [PASS][17] -> [FAIL][18] ([i915#699] / [i915#93] / [i915#95])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-kbl2/igt@kms_flip_tiling@flip-changes-tiling-y.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/shard-kbl2/igt@kms_flip_tiling@flip-changes-tiling-y.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [PASS][19] -> [FAIL][20] ([i915#1188])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-skl1/igt@kms_hdr@bpc-switch.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/shard-skl8/igt@kms_hdr@bpc-switch.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +3 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/shard-iclb8/igt@kms_psr@psr2_sprite_mmap_gtt.html
#### Possible fixes ####
* igt@gem_ctx_persistence@legacy-engines-mixed-process@render:
- shard-apl: [FAIL][23] ([i915#1528]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-apl7/igt@gem_ctx_persistence@legacy-engines-mixed-process@render.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/shard-apl6/igt@gem_ctx_persistence@legacy-engines-mixed-process@render.html
* igt@gem_ctx_persistence@legacy-engines-mixed-process@vebox:
- shard-skl: [FAIL][25] ([i915#1528]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-skl10/igt@gem_ctx_persistence@legacy-engines-mixed-process@vebox.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/shard-skl5/igt@gem_ctx_persistence@legacy-engines-mixed-process@vebox.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [FAIL][27] ([IGT#5]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [SKIP][29] ([fdo#109349]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-iclb6/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_fence_pin_leak:
- shard-kbl: [DMESG-WARN][31] ([i915#165] / [i915#78]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-kbl2/igt@kms_fence_pin_leak.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/shard-kbl2/igt@kms_fence_pin_leak.html
* {igt@kms_flip@flip-vs-suspend-interruptible@c-dp1}:
- shard-apl: [DMESG-WARN][33] ([i915#180]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
- shard-kbl: [DMESG-WARN][35] ([i915#180]) -> [PASS][36] +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][37] ([fdo#108145] / [i915#265]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-none:
- shard-glk: [FAIL][39] ([i915#899]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-glk8/igt@kms_plane_lowres@pipe-a-tiling-none.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/shard-glk5/igt@kms_plane_lowres@pipe-a-tiling-none.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][41] ([fdo#109441]) -> [PASS][42] +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-iclb1/igt@kms_psr@psr2_no_drrs.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@kms_setmode@basic:
- shard-skl: [FAIL][43] ([i915#31]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-skl4/igt@kms_setmode@basic.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/shard-skl2/igt@kms_setmode@basic.html
- shard-kbl: [FAIL][45] ([i915#31]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-kbl4/igt@kms_setmode@basic.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/shard-kbl3/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
- shard-skl: [INCOMPLETE][47] ([i915#69]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-skl8/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/shard-skl9/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
#### Warnings ####
* igt@i915_pm_dc@dc6-psr:
- shard-tglb: [FAIL][49] ([i915#454]) -> [SKIP][50] ([i915#468])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-tglb6/igt@i915_pm_dc@dc6-psr.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/shard-tglb2/igt@i915_pm_dc@dc6-psr.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1472]: https://gitlab.freedesktop.org/drm/intel/issues/1472
[i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
[i915#177]: https://gitlab.freedesktop.org/drm/intel/issues/177
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
[i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#699]: https://gitlab.freedesktop.org/drm/intel/issues/699
[i915#70]: https://gitlab.freedesktop.org/drm/intel/issues/70
[i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78
[i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (11 -> 10)
------------------------------
Missing (1): pig-icl-1065g7
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8424 -> Patchwork_17578
CI-20190529: 20190529
CI_DRM_8424: 69ecf47ef1aabcdc8a4e070584d0a717bbabf4fe @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5628: 652a3fd8966345fa5498904ce80a2027a6782783 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17578: f3eb1ee5e0b9a5156d1253dc3dbf86049d9d4d69 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/tgl: Put HDC flush pipe_control bit in the right dword
2020-05-05 7:27 ` Lionel Landwerlin
@ 2020-05-05 16:32 ` D Scott Phillips
0 siblings, 0 replies; 8+ messages in thread
From: D Scott Phillips @ 2020-05-05 16:32 UTC (permalink / raw)
To: Lionel Landwerlin, intel-gfx; +Cc: Chris Wilson
Lionel Landwerlin <lionel.g.landwerlin@intel.com> writes:
> On 05/05/2020 03:09, D Scott Phillips wrote:
>> D Scott Phillips <d.scott.phillips@intel.com> writes:
>>
>>> Previously we set HDC_PIPELINE_FLUSH in dword 1 of gen12
>>> pipe_control commands. HDC Pipeline flush actually resides in
>>> dword 0, and the bit we were setting in dword 1 was Indirect State
>>> Pointers Disable, which invalidates indirect state in the render
>>> context. This causes failures for userspace, as things like push
>>> constant state gets invalidated.
>>>
>>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>>> Signed-off-by: D Scott Phillips <d.scott.phillips@intel.com>
>> also,
>>
>> Fixes: 4aa0b5d457f5 ("drm/i915/tgl: Add HDC Pipeline Flush")
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> I think Mika sent the same patch in "drm/i915/gen12: Fix HDC pipeline
> flush".
>
> -Lionel
Ah, quite right, I missed it. Ignore this.
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-05-05 16:34 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-05-05 0:01 [Intel-gfx] [PATCH] drm/i915/tgl: Put HDC flush pipe_control bit in the right dword D Scott Phillips
2020-05-05 0:09 ` D Scott Phillips
2020-05-05 7:27 ` Lionel Landwerlin
2020-05-05 16:32 ` D Scott Phillips
2020-05-05 0:25 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2020-05-05 0:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-05 0:57 ` [Intel-gfx] [PATCH] " Kenneth Graunke
2020-05-05 14:17 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
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