* Initial support for the Pine64 Pinephone
@ 2020-07-22 14:18 Peter Robinson
2020-07-22 14:18 ` [PATCH 1/8] dt-bindings: clk: sync sun50i-a64-ccu.h to linux 5.8-rc1 Peter Robinson
` (7 more replies)
0 siblings, 8 replies; 17+ messages in thread
From: Peter Robinson @ 2020-07-22 14:18 UTC (permalink / raw)
To: u-boot
Hi,
This is an initial patch set to support the PinePhone. The patches were tested
on the Braveheart Edition (1.1) of the phone with a serial console cable attached.
There's not currently U-Boot output on the screen, for starters the device tree
support for the panel hasn't landed upstream yet so I'll send that in a follow
up patch series, similarly I'll send a patch set to add support for the Consumer
Edition (1.2) once it lands upstream. For me this allows the phone to boot off
either eMMC or mSD card, USB-C for USB-2/display doesn't currently work as I
think there will need to be support for the ANX7688 USB-C bridge.
Peter
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 1/8] dt-bindings: clk: sync sun50i-a64-ccu.h to linux 5.8-rc1
2020-07-22 14:18 Initial support for the Pine64 Pinephone Peter Robinson
@ 2020-07-22 14:18 ` Peter Robinson
2020-07-22 14:18 ` [PATCH 2/8] dt-bindings: leds: sync leds common.h to linux from 5.8-rc1 Peter Robinson
` (6 subsequent siblings)
7 siblings, 0 replies; 17+ messages in thread
From: Peter Robinson @ 2020-07-22 14:18 UTC (permalink / raw)
To: u-boot
Sync the clock bindings for the Allwinner A64 to Linux
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
---
include/dt-bindings/clock/sun50i-a64-ccu.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h
index d66432c6e6..318eb15c41 100644
--- a/include/dt-bindings/clock/sun50i-a64-ccu.h
+++ b/include/dt-bindings/clock/sun50i-a64-ccu.h
@@ -43,8 +43,10 @@
#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_
#define _DT_BINDINGS_CLK_SUN50I_A64_H_
+#define CLK_PLL_VIDEO0 7
#define CLK_PLL_PERIPH0 11
+#define CLK_CPUX 21
#define CLK_BUS_MIPI_DSI 28
#define CLK_BUS_CE 29
#define CLK_BUS_DMA 30
@@ -129,7 +131,7 @@
#define CLK_AVS 109
#define CLK_HDMI 110
#define CLK_HDMI_DDC 111
-
+#define CLK_MBUS 112
#define CLK_DSI_DPHY 113
#define CLK_GPU 114
--
2.26.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 2/8] dt-bindings: leds: sync leds common.h to linux from 5.8-rc1
2020-07-22 14:18 Initial support for the Pine64 Pinephone Peter Robinson
2020-07-22 14:18 ` [PATCH 1/8] dt-bindings: clk: sync sun50i-a64-ccu.h to linux 5.8-rc1 Peter Robinson
@ 2020-07-22 14:18 ` Peter Robinson
2020-07-22 14:18 ` [PATCH 3/8] dt-bindings: clk/reset: sync updated bindings for Allwinner DE2 display engine Peter Robinson
` (5 subsequent siblings)
7 siblings, 0 replies; 17+ messages in thread
From: Peter Robinson @ 2020-07-22 14:18 UTC (permalink / raw)
To: u-boot
Sync the leds common.h to the latest Linux version.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
---
include/dt-bindings/leds/common.h | 36 ++++++++++++++++++++++---------
1 file changed, 26 insertions(+), 10 deletions(-)
diff --git a/include/dt-bindings/leds/common.h b/include/dt-bindings/leds/common.h
index 9e1256a7c1..0ce7dfc00d 100644
--- a/include/dt-bindings/leds/common.h
+++ b/include/dt-bindings/leds/common.h
@@ -6,6 +6,7 @@
* Author: Jacek Anaszewski <j.anaszewski@samsung.com>
*
* Copyright (C) 2019 Jacek Anaszewski <jacek.anaszewski@gmail.com>
+ * Copyright (C) 2020 Pavel Machek <pavel@ucw.cz>
*/
#ifndef __DT_BINDINGS_LEDS_H
@@ -32,16 +33,38 @@
#define LED_COLOR_ID_MAX 8
/* Standard LED functions */
+/* Keyboard LEDs, usually it would be input4::capslock etc. */
+/* Obsolete equivalent: "shift-key-light" */
+#define LED_FUNCTION_CAPSLOCK "capslock"
+#define LED_FUNCTION_SCROLLLOCK "scrolllock"
+#define LED_FUNCTION_NUMLOCK "numlock"
+/* Obsolete equivalents: "tpacpi::thinklight" (IBM/Lenovo Thinkpads),
+ "lp5523:kb{1,2,3,4,5,6}" (Nokia N900) */
+#define LED_FUNCTION_KBD_BACKLIGHT "kbd_backlight"
+
+/* System LEDs, usually found on system body.
+ platform::mute (etc) is sometimes seen, :mute would be better */
+#define LED_FUNCTION_POWER "power"
+#define LED_FUNCTION_DISK "disk"
+
+/* Obsolete: "platform:*:charging" (allwinner sun50i) */
+#define LED_FUNCTION_CHARGING "charging"
+/* Used RGB notification LEDs common on phones.
+ Obsolete equivalents: "status-led:{red,green,blue}" (Motorola Droid 4),
+ "lp5523:{r,g,b}" (Nokia N900) */
+#define LED_FUNCTION_STATUS "status"
+
+#define LED_FUNCTION_MICMUTE "micmute"
+#define LED_FUNCTION_MUTE "mute"
+
+/* Miscelleaus functions. Use functions above if you can. */
#define LED_FUNCTION_ACTIVITY "activity"
#define LED_FUNCTION_ALARM "alarm"
#define LED_FUNCTION_BACKLIGHT "backlight"
#define LED_FUNCTION_BLUETOOTH "bluetooth"
#define LED_FUNCTION_BOOT "boot"
#define LED_FUNCTION_CPU "cpu"
-#define LED_FUNCTION_CAPSLOCK "capslock"
-#define LED_FUNCTION_CHARGING "charging"
#define LED_FUNCTION_DEBUG "debug"
-#define LED_FUNCTION_DISK "disk"
#define LED_FUNCTION_DISK_ACTIVITY "disk-activity"
#define LED_FUNCTION_DISK_ERR "disk-err"
#define LED_FUNCTION_DISK_READ "disk-read"
@@ -50,21 +73,14 @@
#define LED_FUNCTION_FLASH "flash"
#define LED_FUNCTION_HEARTBEAT "heartbeat"
#define LED_FUNCTION_INDICATOR "indicator"
-#define LED_FUNCTION_KBD_BACKLIGHT "kbd_backlight"
#define LED_FUNCTION_LAN "lan"
#define LED_FUNCTION_MAIL "mail"
#define LED_FUNCTION_MTD "mtd"
-#define LED_FUNCTION_MICMUTE "micmute"
-#define LED_FUNCTION_MUTE "mute"
-#define LED_FUNCTION_NUMLOCK "numlock"
#define LED_FUNCTION_PANIC "panic"
#define LED_FUNCTION_PROGRAMMING "programming"
-#define LED_FUNCTION_POWER "power"
#define LED_FUNCTION_RX "rx"
#define LED_FUNCTION_SD "sd"
-#define LED_FUNCTION_SCROLLLOCK "scrolllock"
#define LED_FUNCTION_STANDBY "standby"
-#define LED_FUNCTION_STATUS "status"
#define LED_FUNCTION_TORCH "torch"
#define LED_FUNCTION_TX "tx"
#define LED_FUNCTION_USB "usb"
--
2.26.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 3/8] dt-bindings: clk/reset: sync updated bindings for Allwinner DE2 display engine
2020-07-22 14:18 Initial support for the Pine64 Pinephone Peter Robinson
2020-07-22 14:18 ` [PATCH 1/8] dt-bindings: clk: sync sun50i-a64-ccu.h to linux 5.8-rc1 Peter Robinson
2020-07-22 14:18 ` [PATCH 2/8] dt-bindings: leds: sync leds common.h to linux from 5.8-rc1 Peter Robinson
@ 2020-07-22 14:18 ` Peter Robinson
2020-07-22 14:18 ` [PATCH 4/8] arm: dts: sync axp803.dtsi from linux 5.8-rc1 Peter Robinson
` (4 subsequent siblings)
7 siblings, 0 replies; 17+ messages in thread
From: Peter Robinson @ 2020-07-22 14:18 UTC (permalink / raw)
To: u-boot
Sync the clock and reset bindings for the Allwinner DE2 display engine to Linux 5.8-rc1.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
---
include/dt-bindings/clock/sun8i-de2.h | 3 +++
include/dt-bindings/reset/sun8i-de2.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/include/dt-bindings/clock/sun8i-de2.h b/include/dt-bindings/clock/sun8i-de2.h
index 3bed63b524..7768f73b05 100644
--- a/include/dt-bindings/clock/sun8i-de2.h
+++ b/include/dt-bindings/clock/sun8i-de2.h
@@ -15,4 +15,7 @@
#define CLK_MIXER1 7
#define CLK_WB 8
+#define CLK_BUS_ROT 9
+#define CLK_ROT 10
+
#endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */
diff --git a/include/dt-bindings/reset/sun8i-de2.h b/include/dt-bindings/reset/sun8i-de2.h
index 9526017432..1c36a6ac86 100644
--- a/include/dt-bindings/reset/sun8i-de2.h
+++ b/include/dt-bindings/reset/sun8i-de2.h
@@ -10,5 +10,6 @@
#define RST_MIXER0 0
#define RST_MIXER1 1
#define RST_WB 2
+#define RST_ROT 3
#endif /* _DT_BINDINGS_RESET_SUN8I_DE2_H_ */
--
2.26.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 4/8] arm: dts: sync axp803.dtsi from linux 5.8-rc1
2020-07-22 14:18 Initial support for the Pine64 Pinephone Peter Robinson
` (2 preceding siblings ...)
2020-07-22 14:18 ` [PATCH 3/8] dt-bindings: clk/reset: sync updated bindings for Allwinner DE2 display engine Peter Robinson
@ 2020-07-22 14:18 ` Peter Robinson
2020-07-22 14:18 ` [PATCH 5/8] arm: dts: Add new sun50i-a64-cpu-opp.dtsi from Linux 5.8-rc1 Peter Robinson
` (3 subsequent siblings)
7 siblings, 0 replies; 17+ messages in thread
From: Peter Robinson @ 2020-07-22 14:18 UTC (permalink / raw)
To: u-boot
Sync the Allwinner axp803 device tree to the latest upstream Linux.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
---
arch/arm/dts/axp803.dtsi | 82 ++++++++++++++++++++--------------------
1 file changed, 41 insertions(+), 41 deletions(-)
diff --git a/arch/arm/dts/axp803.dtsi b/arch/arm/dts/axp803.dtsi
index e5eae8bafc..10e9186a76 100644
--- a/arch/arm/dts/axp803.dtsi
+++ b/arch/arm/dts/axp803.dtsi
@@ -1,44 +1,5 @@
-/*
- * Copyright 2017 Icenowy Zheng <icenowy@aosc.xyz>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright 2017 Icenowy Zheng <icenowy@aosc.xyz>
/*
* AXP803 Integrated Power Management Chip
@@ -49,6 +10,39 @@
interrupt-controller;
#interrupt-cells = <1>;
+ ac_power_supply: ac-power-supply {
+ compatible = "x-powers,axp803-ac-power-supply",
+ "x-powers,axp813-ac-power-supply";
+ status = "disabled";
+ };
+
+ axp_adc: adc {
+ compatible = "x-powers,axp803-adc", "x-powers,axp813-adc";
+ #io-channel-cells = <1>;
+ };
+
+ axp_gpio: gpio {
+ compatible = "x-powers,axp803-gpio", "x-powers,axp813-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio0_ldo: gpio0-ldo {
+ pins = "GPIO0";
+ function = "ldo";
+ };
+
+ gpio1_ldo: gpio1-ldo {
+ pins = "GPIO1";
+ function = "ldo";
+ };
+ };
+
+ battery_power_supply: battery-power-supply {
+ compatible = "x-powers,axp803-battery-power-supply",
+ "x-powers,axp813-battery-power-supply";
+ status = "disabled";
+ };
+
regulators {
/* Default work frequency for buck regulators */
x-powers,dcdc-freq = <3000>;
@@ -152,4 +146,10 @@
status = "disabled";
};
};
+
+ usb_power_supply: usb-power-supply {
+ compatible = "x-powers,axp803-usb-power-supply",
+ "x-powers,axp813-usb-power-supply";
+ status = "disabled";
+ };
};
--
2.26.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 5/8] arm: dts: Add new sun50i-a64-cpu-opp.dtsi from Linux 5.8-rc1
2020-07-22 14:18 Initial support for the Pine64 Pinephone Peter Robinson
` (3 preceding siblings ...)
2020-07-22 14:18 ` [PATCH 4/8] arm: dts: sync axp803.dtsi from linux 5.8-rc1 Peter Robinson
@ 2020-07-22 14:18 ` Peter Robinson
2020-07-22 14:18 ` [PATCH 6/8] arm: dts: Sync the sun50i-a64.dtsi " Peter Robinson
` (2 subsequent siblings)
7 siblings, 0 replies; 17+ messages in thread
From: Peter Robinson @ 2020-07-22 14:18 UTC (permalink / raw)
To: u-boot
Sync the Allwinner A64 CPU operating points dtsi from Linux.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
---
arch/arm/dts/sun50i-a64-cpu-opp.dtsi | 75 ++++++++++++++++++++++++++++
1 file changed, 75 insertions(+)
create mode 100644 arch/arm/dts/sun50i-a64-cpu-opp.dtsi
diff --git a/arch/arm/dts/sun50i-a64-cpu-opp.dtsi b/arch/arm/dts/sun50i-a64-cpu-opp.dtsi
new file mode 100644
index 0000000000..578c37490d
--- /dev/null
+++ b/arch/arm/dts/sun50i-a64-cpu-opp.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Vasily khoruzhick <anarsoul@gmail.com>
+ */
+
+/ {
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-648000000 {
+ opp-hz = /bits/ 64 <648000000>;
+ opp-microvolt = <1040000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-912000000 {
+ opp-hz = /bits/ 64 <912000000>;
+ opp-microvolt = <1120000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-960000000 {
+ opp-hz = /bits/ 64 <960000000>;
+ opp-microvolt = <1160000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1200000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-microvolt = <1240000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1104000000 {
+ opp-hz = /bits/ 64 <1104000000>;
+ opp-microvolt = <1260000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1152000000 {
+ opp-hz = /bits/ 64 <1152000000>;
+ opp-microvolt = <1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu0_opp_table>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu0_opp_table>;
+};
+
+&cpu2 {
+ operating-points-v2 = <&cpu0_opp_table>;
+};
+
+&cpu3 {
+ operating-points-v2 = <&cpu0_opp_table>;
+};
--
2.26.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 6/8] arm: dts: Sync the sun50i-a64.dtsi from Linux 5.8-rc1
2020-07-22 14:18 Initial support for the Pine64 Pinephone Peter Robinson
` (4 preceding siblings ...)
2020-07-22 14:18 ` [PATCH 5/8] arm: dts: Add new sun50i-a64-cpu-opp.dtsi from Linux 5.8-rc1 Peter Robinson
@ 2020-07-22 14:18 ` Peter Robinson
2020-07-22 23:14 ` André Przywara
2020-07-22 14:18 ` [PATCH 7/8] arm64: dts: allwinner: Add initial support for Pine64 PinePhone Peter Robinson
2020-07-22 14:18 ` [PATCH 8/8] Initial Pine64 Pinephone support Peter Robinson
7 siblings, 1 reply; 17+ messages in thread
From: Peter Robinson @ 2020-07-22 14:18 UTC (permalink / raw)
To: u-boot
Sync the Allwinner A64 sun50i-a64.dtsi from Linux.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
---
arch/arm/dts/sun50i-a64.dtsi | 532 ++++++++++++++++++++++++++++-------
1 file changed, 434 insertions(+), 98 deletions(-)
diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
index ff41abc96a..8dfbcd1440 100644
--- a/arch/arm/dts/sun50i-a64.dtsi
+++ b/arch/arm/dts/sun50i-a64.dtsi
@@ -1,46 +1,7 @@
-/*
- * Copyright (C) 2016 ARM Ltd.
- * based on the Allwinner H3 dtsi:
- * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2016 ARM Ltd.
+// based on the Allwinner H3 dtsi:
+// Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
#include <dt-bindings/clock/sun50i-a64-ccu.h>
#include <dt-bindings/clock/sun8i-de2.h>
@@ -49,6 +10,7 @@
#include <dt-bindings/reset/sun50i-a64-ccu.h>
#include <dt-bindings/reset/sun8i-de2.h>
#include <dt-bindings/reset/sun8i-r-ccu.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&gic>;
@@ -84,35 +46,47 @@
#size-cells = <0>;
cpu0: cpu at 0 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0>;
enable-method = "psci";
next-level-cache = <&L2>;
+ clocks = <&ccu 21>;
+ clock-names = "cpu";
+ #cooling-cells = <2>;
};
cpu1: cpu at 1 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <1>;
enable-method = "psci";
next-level-cache = <&L2>;
+ clocks = <&ccu 21>;
+ clock-names = "cpu";
+ #cooling-cells = <2>;
};
cpu2: cpu at 2 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <2>;
enable-method = "psci";
next-level-cache = <&L2>;
+ clocks = <&ccu 21>;
+ clock-names = "cpu";
+ #cooling-cells = <2>;
};
cpu3: cpu at 3 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <3>;
enable-method = "psci";
next-level-cache = <&L2>;
+ clocks = <&ccu 21>;
+ clock-names = "cpu";
+ #cooling-cells = <2>;
};
L2: l2-cache {
@@ -139,15 +113,16 @@
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
- clock-output-names = "osc32k";
+ clock-output-names = "ext-osc32k";
};
- iosc: internal-osc-clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <16000000>;
- clock-accuracy = <300000000>;
- clock-output-names = "iosc";
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
psci {
@@ -155,26 +130,33 @@
method = "smc";
};
- sound_spdif {
+ sound: sound {
compatible = "simple-audio-card";
- simple-audio-card,name = "On-board SPDIF";
+ simple-audio-card,name = "sun50i-a64-audio";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,frame-master = <&cpudai>;
+ simple-audio-card,bitclock-master = <&cpudai>;
+ simple-audio-card,mclk-fs = <128>;
+ simple-audio-card,aux-devs = <&codec_analog>;
+ simple-audio-card,routing =
+ "Left DAC", "AIF1 Slot 0 Left",
+ "Right DAC", "AIF1 Slot 0 Right",
+ "AIF1 Slot 0 Left ADC", "Left ADC",
+ "AIF1 Slot 0 Right ADC", "Right ADC";
+ status = "disabled";
- simple-audio-card,cpu {
- sound-dai = <&spdif>;
+ cpudai: simple-audio-card,cpu {
+ sound-dai = <&dai>;
};
- simple-audio-card,codec {
- sound-dai = <&spdif_out>;
+ link_codec: simple-audio-card,codec {
+ sound-dai = <&codec>;
};
};
- spdif_out: spdif-out {
- #sound-dai-cells = <0>;
- compatible = "linux,spdif-dit";
- };
-
timer {
compatible = "arm,armv8-timer";
+ allwinner,erratum-unknown1;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14
@@ -185,13 +167,76 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ thermal-zones {
+ cpu_thermal: cpu0-thermal {
+ /* milliseconds */
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&ths 0>;
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu_alert1>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
+ trips {
+ cpu_alert0: cpu_alert0 {
+ /* milliCelsius */
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_alert1: cpu_alert1 {
+ /* milliCelsius */
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cpu_crit: cpu_crit {
+ /* milliCelsius */
+ temperature = <110000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu0_thermal: gpu0-thermal {
+ /* milliseconds */
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&ths 1>;
+ };
+
+ gpu1_thermal: gpu1-thermal {
+ /* milliseconds */
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&ths 2>;
+ };
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
- de2 at 1000000 {
+ bus at 1000000 {
compatible = "allwinner,sun50i-a64-de2";
reg = <0x1000000 0x400000>;
allwinner,sram = <&de2_sram 1>;
@@ -201,16 +246,28 @@
display_clocks: clock at 0 {
compatible = "allwinner,sun50i-a64-de2-clk";
- reg = <0x0 0x100000>;
- clocks = <&ccu CLK_DE>,
- <&ccu CLK_BUS_DE>;
- clock-names = "mod",
- "bus";
+ reg = <0x0 0x10000>;
+ clocks = <&ccu CLK_BUS_DE>,
+ <&ccu CLK_DE>;
+ clock-names = "bus",
+ "mod";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
};
+ rotate: rotate at 20000 {
+ compatible = "allwinner,sun50i-a64-de2-rotate",
+ "allwinner,sun8i-a83t-de2-rotate";
+ reg = <0x20000 0x10000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&display_clocks CLK_BUS_ROT>,
+ <&display_clocks CLK_ROT>;
+ clock-names = "bus",
+ "mod";
+ resets = <&display_clocks RST_ROT>;
+ };
+
mixer0: mixer at 100000 {
compatible = "allwinner,sun50i-a64-de2-mixer-0";
reg = <0x100000 0x100000>;
@@ -225,11 +282,19 @@
#size-cells = <0>;
mixer0_out: port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <1>;
- mixer0_out_tcon0: endpoint {
+ mixer0_out_tcon0: endpoint at 0 {
+ reg = <0>;
remote-endpoint = <&tcon0_in_mixer0>;
};
+
+ mixer0_out_tcon1: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&tcon1_in_mixer0>;
+ };
};
};
};
@@ -248,9 +313,17 @@
#size-cells = <0>;
mixer1_out: port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <1>;
- mixer1_out_tcon1: endpoint {
+ mixer1_out_tcon0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_in_mixer1>;
+ };
+
+ mixer1_out_tcon1: endpoint at 1 {
+ reg = <1>;
remote-endpoint = <&tcon1_in_mixer1>;
};
};
@@ -259,8 +332,7 @@
};
syscon: syscon at 1c00000 {
- compatible = "allwinner,sun50i-a64-system-control",
- "syscon";
+ compatible = "allwinner,sun50i-a64-system-control";
reg = <0x01c00000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
@@ -278,6 +350,20 @@
reg = <0x0000 0x28000>;
};
};
+
+ sram_c1: sram at 1d00000 {
+ compatible = "mmio-sram";
+ reg = <0x01d00000 0x40000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x01d00000 0x40000>;
+
+ ve_sram: sram-section at 0 {
+ compatible = "allwinner,sun50i-a64-sram-c1",
+ "allwinner,sun4i-a10-sram-c1";
+ reg = <0x000000 0x40000>;
+ };
+ };
};
dma: dma-controller at 1c02000 {
@@ -299,6 +385,7 @@
clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
clock-names = "ahb", "tcon-ch0";
clock-output-names = "tcon-pixel-clock";
+ #clock-cells = <0>;
resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
reset-names = "lcd", "lvds";
@@ -315,12 +402,23 @@
reg = <0>;
remote-endpoint = <&mixer0_out_tcon0>;
};
+
+ tcon0_in_mixer1: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&mixer1_out_tcon0>;
+ };
};
tcon0_out: port at 1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
+
+ tcon0_out_dsi: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&dsi_in_tcon0>;
+ allwinner,tcon-channel = <1>;
+ };
};
};
};
@@ -340,9 +438,17 @@
#size-cells = <0>;
tcon1_in: port at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0>;
- tcon1_in_mixer1: endpoint {
+ tcon1_in_mixer0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&mixer0_out_tcon1>;
+ };
+
+ tcon1_in_mixer1: endpoint at 1 {
+ reg = <1>;
remote-endpoint = <&mixer1_out_tcon1>;
};
};
@@ -360,6 +466,17 @@
};
};
+ video-codec at 1c0e000 {
+ compatible = "allwinner,sun50i-a64-video-engine";
+ reg = <0x01c0e000 0x1000>;
+ clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
+ <&ccu CLK_DRAM_VE>;
+ clock-names = "ahb", "mod", "ram";
+ resets = <&ccu RST_BUS_VE>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ allwinner,sram = <&ve_sram 1>;
+ };
+
mmc0: mmc at 1c0f000 {
compatible = "allwinner,sun50i-a64-mmc";
reg = <0x01c0f000 0x1000>;
@@ -405,6 +522,31 @@
sid: eeprom at 1c14000 {
compatible = "allwinner,sun50i-a64-sid";
reg = <0x1c14000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ths_calibration: thermal-sensor-calibration at 34 {
+ reg = <0x34 0x8>;
+ };
+ };
+
+ crypto: crypto at 1c15000 {
+ compatible = "allwinner,sun50i-a64-crypto";
+ reg = <0x01c15000 0x1000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_CE>;
+ };
+
+ msgbox: mailbox at 1c17000 {
+ compatible = "allwinner,sun50i-a64-msgbox",
+ "allwinner,sun6i-a31-msgbox";
+ reg = <0x01c17000 0x1000>;
+ clocks = <&ccu CLK_BUS_MSGBOX>;
+ resets = <&ccu RST_BUS_MSGBOX>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
};
usb_otg: usb at 1c19000 {
@@ -417,6 +559,7 @@
phys = <&usbphy 0>;
phy-names = "usb";
extcon = <&usbphy 0>;
+ dr_mode = "otg";
status = "disabled";
};
@@ -491,7 +634,7 @@
ccu: clock at 1c20000 {
compatible = "allwinner,sun50i-a64-ccu";
reg = <0x01c20000 0x400>;
- clocks = <&osc24M>, <&osc32k>;
+ clocks = <&osc24M>, <&rtc 0>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
@@ -503,22 +646,50 @@
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu 58>;
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
+ clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
- i2c0_pins: i2c0_pins {
+ csi_pins: csi-pins {
+ pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
+ "PE7", "PE8", "PE9", "PE10", "PE11";
+ function = "csi";
+ };
+
+ /omit-if-no-ref/
+ csi_mclk_pin: csi-mclk-pin {
+ pins = "PE1";
+ function = "csi";
+ };
+
+ i2c0_pins: i2c0-pins {
pins = "PH0", "PH1";
function = "i2c0";
};
- i2c1_pins: i2c1_pins {
+ i2c1_pins: i2c1-pins {
pins = "PH2", "PH3";
function = "i2c1";
};
+ i2c2_pins: i2c2-pins {
+ pins = "PE14", "PE15";
+ function = "i2c2";
+ };
+
+ /omit-if-no-ref/
+ lcd_rgb666_pins: lcd-rgb666-pins {
+ pins = "PD0", "PD1", "PD2", "PD3", "PD4",
+ "PD5", "PD6", "PD7", "PD8", "PD9",
+ "PD10", "PD11", "PD12", "PD13",
+ "PD14", "PD15", "PD16", "PD17",
+ "PD18", "PD19", "PD20", "PD21";
+ function = "lcd0";
+ };
+
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2", "PF3",
"PF4", "PF5";
@@ -551,19 +722,19 @@
bias-pull-up;
};
- pwm_pin: pwm_pin {
+ pwm_pin: pwm-pin {
pins = "PD22";
function = "pwm";
};
- rmii_pins: rmii_pins {
+ rmii_pins: rmii-pins {
pins = "PD10", "PD11", "PD13", "PD14", "PD17",
"PD18", "PD19", "PD20", "PD22", "PD23";
function = "emac";
drive-strength = <40>;
};
- rgmii_pins: rgmii_pins {
+ rgmii_pins: rgmii-pins {
pins = "PD8", "PD9", "PD10", "PD11", "PD12",
"PD13", "PD15", "PD16", "PD17", "PD18",
"PD19", "PD20", "PD21", "PD22", "PD23";
@@ -571,17 +742,17 @@
drive-strength = <40>;
};
- spdif_tx_pin: spdif {
+ spdif_tx_pin: spdif-tx-pin {
pins = "PH8";
function = "spdif";
};
- spi0_pins: spi0 {
+ spi0_pins: spi0-pins {
pins = "PC0", "PC1", "PC2", "PC3";
function = "spi0";
};
- spi1_pins: spi1 {
+ spi1_pins: spi1-pins {
pins = "PD0", "PD1", "PD2", "PD3";
function = "spi1";
};
@@ -591,12 +762,12 @@
function = "uart0";
};
- uart1_pins: uart1_pins {
+ uart1_pins: uart1-pins {
pins = "PG6", "PG7";
function = "uart1";
};
- uart1_rts_cts_pins: uart1_rts_cts_pins {
+ uart1_rts_cts_pins: uart1-rts-cts-pins {
pins = "PG8", "PG9";
function = "uart1";
};
@@ -638,6 +809,14 @@
status = "disabled";
};
+ lradc: lradc at 1c21800 {
+ compatible = "allwinner,sun50i-a64-lradc",
+ "allwinner,sun8i-a83t-r-lradc";
+ reg = <0x01c21800 0x400>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
i2s0: i2s at 1c22000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun50i-a64-i2s",
@@ -666,6 +845,41 @@
status = "disabled";
};
+ dai: dai at 1c22c00 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun50i-a64-codec-i2s";
+ reg = <0x01c22c00 0x200>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
+ clock-names = "apb", "mod";
+ resets = <&ccu RST_BUS_CODEC>;
+ dmas = <&dma 15>, <&dma 15>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ codec: codec at 1c22e00 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-a33-codec";
+ reg = <0x01c22e00 0x600>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
+ clock-names = "bus", "mod";
+ status = "disabled";
+ };
+
+ ths: thermal-sensor at 1c25000 {
+ compatible = "allwinner,sun50i-a64-ths";
+ reg = <0x01c25000 0x100>;
+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
+ clock-names = "bus", "mod";
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ccu RST_BUS_THS>;
+ nvmem-cells = <&ths_calibration>;
+ nvmem-cell-names = "calibration";
+ #thermal-sensor-cells = <1>;
+ };
+
uart0: serial at 1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
@@ -727,6 +941,8 @@
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C0>;
resets = <&ccu RST_BUS_I2C0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -738,6 +954,8 @@
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C1>;
resets = <&ccu RST_BUS_I2C1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -749,12 +967,13 @@
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C2>;
resets = <&ccu RST_BUS_I2C2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
-
spi0: spi at 1c68000 {
compatible = "allwinner,sun8i-h3-spi";
reg = <0x01c68000 0x1000>;
@@ -808,6 +1027,28 @@
};
};
+ mali: gpu at 1c40000 {
+ compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
+ reg = <0x01c40000 0x10000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1",
+ "pmu";
+ clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
+ clock-names = "bus", "core";
+ resets = <&ccu RST_BUS_GPU>;
+ };
+
gic: interrupt-controller at 1c81000 {
compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,
@@ -830,6 +1071,75 @@
status = "disabled";
};
+ mbus: dram-controller at 1c62000 {
+ compatible = "allwinner,sun50i-a64-mbus";
+ reg = <0x01c62000 0x1000>;
+ clocks = <&ccu 112>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ dma-ranges = <0x00000000 0x40000000 0xc0000000>;
+ #interconnect-cells = <1>;
+ };
+
+ csi: csi at 1cb0000 {
+ compatible = "allwinner,sun50i-a64-csi";
+ reg = <0x01cb0000 0x1000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CSI>,
+ <&ccu CLK_CSI_SCLK>,
+ <&ccu CLK_DRAM_CSI>;
+ clock-names = "bus", "mod", "ram";
+ resets = <&ccu RST_BUS_CSI>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&csi_pins>;
+ status = "disabled";
+ };
+
+ dsi: dsi at 1ca0000 {
+ compatible = "allwinner,sun50i-a64-mipi-dsi";
+ reg = <0x01ca0000 0x1000>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_MIPI_DSI>;
+ resets = <&ccu RST_BUS_MIPI_DSI>;
+ phys = <&dphy>;
+ phy-names = "dphy";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port {
+ dsi_in_tcon0: endpoint {
+ remote-endpoint = <&tcon0_out_dsi>;
+ };
+ };
+ };
+
+ dphy: d-phy at 1ca1000 {
+ compatible = "allwinner,sun50i-a64-mipi-dphy",
+ "allwinner,sun6i-a31-mipi-dphy";
+ reg = <0x01ca1000 0x1000>;
+ clocks = <&ccu CLK_BUS_MIPI_DSI>,
+ <&ccu CLK_DSI_DPHY>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_MIPI_DSI>;
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+
+ deinterlace: deinterlace at 1e00000 {
+ compatible = "allwinner,sun50i-a64-deinterlace",
+ "allwinner,sun8i-h3-deinterlace";
+ reg = <0x01e00000 0x20000>;
+ clocks = <&ccu CLK_BUS_DEINTERLACE>,
+ <&ccu CLK_DEINTERLACE>,
+ <&ccu CLK_DRAM_DEINTERLACE>;
+ clock-names = "bus", "mod", "ram";
+ resets = <&ccu RST_BUS_DEINTERLACE>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&mbus 9>;
+ interconnect-names = "dma-mem";
+ };
+
hdmi: hdmi at 1ee0000 {
compatible = "allwinner,sun50i-a64-dw-hdmi",
"allwinner,sun8i-a83t-dw-hdmi";
@@ -842,7 +1152,7 @@
resets = <&ccu RST_BUS_HDMI1>;
reset-names = "ctrl";
phys = <&hdmi_phy>;
- phy-names = "hdmi-phy";
+ phy-names = "phy";
status = "disabled";
ports {
@@ -867,7 +1177,7 @@
compatible = "allwinner,sun50i-a64-hdmi-phy";
reg = <0x01ef0000 0x10000>;
clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
- <&ccu 7>;
+ <&ccu CLK_PLL_VIDEO0>;
clock-names = "bus", "mod", "pll-0";
resets = <&ccu RST_BUS_HDMI0>;
reset-names = "phy";
@@ -875,11 +1185,12 @@
};
rtc: rtc at 1f00000 {
- compatible = "allwinner,sun6i-a31-rtc";
- reg = <0x01f00000 0x54>;
+ compatible = "allwinner,sun50i-a64-rtc",
+ "allwinner,sun8i-h3-rtc";
+ reg = <0x01f00000 0x400>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- clock-output-names = "rtc-osc32k", "rtc-osc32k-out";
+ clock-output-names = "osc32k", "osc32k-out", "iosc";
clocks = <&osc32k>;
#clock-cells = <1>;
};
@@ -896,13 +1207,19 @@
r_ccu: clock at 1f01400 {
compatible = "allwinner,sun50i-a64-r-ccu";
reg = <0x01f01400 0x100>;
- clocks = <&osc24M>, <&osc32k>, <&iosc>,
- <&ccu 11>;
+ clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
+ <&ccu CLK_PLL_PERIPH0>;
clock-names = "hosc", "losc", "iosc", "pll-periph";
#clock-cells = <1>;
#reset-cells = <1>;
};
+ codec_analog: codec-analog at 1f015c0 {
+ compatible = "allwinner,sun50i-a64-codec-analog";
+ reg = <0x01f015c0 0x4>;
+ status = "disabled";
+ };
+
r_i2c: i2c at 1f02400 {
compatible = "allwinner,sun50i-a64-i2c",
"allwinner,sun6i-a31-i2c";
@@ -915,6 +1232,19 @@
#size-cells = <0>;
};
+ r_ir: ir at 1f02000 {
+ compatible = "allwinner,sun50i-a64-ir",
+ "allwinner,sun6i-a31-ir";
+ reg = <0x01f02000 0x400>;
+ clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
+ clock-names = "apb", "ir";
+ resets = <&r_ccu RST_APB0_IR>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";
+ };
+
r_pwm: pwm at 1f03800 {
compatible = "allwinner,sun50i-a64-pwm",
"allwinner,sun5i-a13-pwm";
@@ -942,12 +1272,17 @@
function = "s_i2c";
};
- r_pwm_pin: pwm {
+ r_ir_rx_pin: r-ir-rx-pin {
+ pins = "PL11";
+ function = "s_cir_rx";
+ };
+
+ r_pwm_pin: r-pwm-pin {
pins = "PL10";
function = "s_pwm";
};
- r_rsb_pins: rsb {
+ r_rsb_pins: r-rsb-pins {
pins = "PL0", "PL1";
function = "s_rsb";
};
@@ -972,6 +1307,7 @@
"allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
};
};
};
--
2.26.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 7/8] arm64: dts: allwinner: Add initial support for Pine64 PinePhone
2020-07-22 14:18 Initial support for the Pine64 Pinephone Peter Robinson
` (5 preceding siblings ...)
2020-07-22 14:18 ` [PATCH 6/8] arm: dts: Sync the sun50i-a64.dtsi " Peter Robinson
@ 2020-07-22 14:18 ` Peter Robinson
2020-07-22 14:18 ` [PATCH 8/8] Initial Pine64 Pinephone support Peter Robinson
7 siblings, 0 replies; 17+ messages in thread
From: Peter Robinson @ 2020-07-22 14:18 UTC (permalink / raw)
To: u-boot
At the moment PinePhone comes in two slightly incompatible variants:
- 1.0: Early Developer Batch
- 1.1: Braveheart Batch
This syncs the Pinephone DTs from Linux 5.8-rc1.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/sun50i-a64-pinephone-1.0.dts | 11 +
arch/arm/dts/sun50i-a64-pinephone-1.1.dts | 11 +
arch/arm/dts/sun50i-a64-pinephone.dtsi | 379 ++++++++++++++++++++++
4 files changed, 403 insertions(+)
create mode 100644 arch/arm/dts/sun50i-a64-pinephone-1.0.dts
create mode 100644 arch/arm/dts/sun50i-a64-pinephone-1.1.dts
create mode 100644 arch/arm/dts/sun50i-a64-pinephone.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cee10f533f..efaadeecf3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -597,6 +597,8 @@ dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-pine64-plus.dtb \
sun50i-a64-pine64.dtb \
sun50i-a64-pinebook.dtb \
+ sun50i-a64-pinephone-1.0.dtb \
+ sun50i-a64-pinephone-1.1.dtb \
sun50i-a64-sopine-baseboard.dtb \
sun50i-a64-teres-i.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
diff --git a/arch/arm/dts/sun50i-a64-pinephone-1.0.dts b/arch/arm/dts/sun50i-a64-pinephone-1.0.dts
new file mode 100644
index 0000000000..0c42272106
--- /dev/null
+++ b/arch/arm/dts/sun50i-a64-pinephone-1.0.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Ondrej Jirman <megous@megous.com>
+
+/dts-v1/;
+
+#include "sun50i-a64-pinephone.dtsi"
+
+/ {
+ model = "Pine64 PinePhone Developer Batch (1.0)";
+ compatible = "pine64,pinephone-1.0", "allwinner,sun50i-a64";
+};
diff --git a/arch/arm/dts/sun50i-a64-pinephone-1.1.dts b/arch/arm/dts/sun50i-a64-pinephone-1.1.dts
new file mode 100644
index 0000000000..06a775c416
--- /dev/null
+++ b/arch/arm/dts/sun50i-a64-pinephone-1.1.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Ondrej Jirman <megous@megous.com>
+
+/dts-v1/;
+
+#include "sun50i-a64-pinephone.dtsi"
+
+/ {
+ model = "Pine64 PinePhone Braveheart (1.1)";
+ compatible = "pine64,pinephone-1.1", "allwinner,sun50i-a64";
+};
diff --git a/arch/arm/dts/sun50i-a64-pinephone.dtsi b/arch/arm/dts/sun50i-a64-pinephone.dtsi
new file mode 100644
index 0000000000..cefda145c3
--- /dev/null
+++ b/arch/arm/dts/sun50i-a64-pinephone.dtsi
@@ -0,0 +1,379 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.xyz>
+// Copyright (C) 2020 Martijn Braam <martijn@brixit.nl>
+// Copyright (C) 2020 Ondrej Jirman <megous@megous.com>
+
+#include "sun50i-a64.dtsi"
+#include "sun50i-a64-cpu-opp.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ blue {
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
+ };
+
+ green {
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 3 18 GPIO_ACTIVE_HIGH>; /* PD18 */
+ };
+
+ red {
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
+ };
+ };
+
+ speaker_amp: audio-amplifier {
+ compatible = "simple-audio-amplifier";
+ enable-gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */
+ sound-name-prefix = "Speaker Amp";
+ };
+
+ vibrator {
+ compatible = "gpio-vibrator";
+ enable-gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */
+ vcc-supply = <®_dcdc1>;
+ };
+};
+
+&codec {
+ status = "okay";
+};
+
+&codec_analog {
+ cpvdd-supply = <®_eldo1>;
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu1 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu2 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu3 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&dai {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ /* Magnetometer */
+ lis3mdl at 1e {
+ compatible = "st,lis3mdl-magn";
+ reg = <0x1e>;
+ vdd-supply = <®_dldo1>;
+ vddio-supply = <®_dldo1>;
+ };
+
+ /* Accelerometer/gyroscope */
+ mpu6050 at 68 {
+ compatible = "invensense,mpu6050";
+ reg = <0x68>;
+ interrupt-parent = <&pio>;
+ interrupts = <7 5 IRQ_TYPE_EDGE_RISING>; /* PH5 */
+ vdd-supply = <®_dldo1>;
+ vddio-supply = <®_dldo1>;
+ };
+};
+
+/* Connected to pogo pins (external spring based pinheader for user addons) */
+&i2c2 {
+ status = "okay";
+};
+
+&lradc {
+ vref-supply = <®_aldo3>;
+ status = "okay";
+
+ button-200 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <200000>;
+ };
+
+ button-400 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <400000>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <®_dcdc1>;
+ vqmmc-supply = <®_dcdc1>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ disable-wp;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ vmmc-supply = <®_dcdc1>;
+ vqmmc-supply = <®_dcdc1>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ vcc-pb-supply = <®_dcdc1>;
+ vcc-pc-supply = <®_dcdc1>;
+ vcc-pd-supply = <®_dcdc1>;
+ vcc-pe-supply = <®_aldo1>;
+ vcc-pf-supply = <®_dcdc1>;
+ vcc-pg-supply = <®_dldo4>;
+ vcc-ph-supply = <®_dcdc1>;
+};
+
+&r_pio {
+ /*
+ * FIXME: We can't add that supply for now since it would
+ * create a circular dependency between pinctrl, the regulator
+ * and the RSB Bus.
+ *
+ * vcc-pl-supply = <®_aldo2>;
+ */
+};
+
+&r_rsb {
+ status = "okay";
+
+ axp803: pmic at 3a3 {
+ compatible = "x-powers,axp803";
+ reg = <0x3a3>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "axp803.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+&battery_power_supply {
+ status = "okay";
+};
+
+®_aldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "dovdd-csi";
+};
+
+®_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pl";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dcdc6 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-sys";
+};
+
+®_dldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-dsi-sensor";
+};
+
+®_dldo2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-mipi-io";
+};
+
+®_dldo3 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "avdd-csi";
+};
+
+®_dldo4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-io";
+};
+
+®_eldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-lpddr";
+};
+
+®_eldo3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "dvdd-1v8-csi";
+};
+
+®_fldo1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-1v2-hsic";
+};
+
+®_fldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpus";
+};
+
+®_ldo_io0 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-lcd-ctp-stk";
+ status = "okay";
+};
+
+®_ldo_io1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-1v8-typec";
+ status = "okay";
+};
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&sound {
+ status = "okay";
+ simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
+ simple-audio-card,widgets = "Microphone", "Headset Microphone",
+ "Microphone", "Internal Microphone",
+ "Headphone", "Headphone Jack",
+ "Speaker", "Internal Earpiece",
+ "Speaker", "Internal Speaker";
+ simple-audio-card,routing =
+ "Headphone Jack", "HP",
+ "Internal Earpiece", "EARPIECE",
+ "Internal Speaker", "Speaker Amp OUTL",
+ "Internal Speaker", "Speaker Amp OUTR",
+ "Speaker Amp INL", "LINEOUT",
+ "Speaker Amp INR", "LINEOUT",
+ "Left DAC", "AIF1 Slot 0 Left",
+ "Right DAC", "AIF1 Slot 0 Right",
+ "AIF1 Slot 0 Left ADC", "Left ADC",
+ "AIF1 Slot 0 Right ADC", "Right ADC",
+ "Internal Microphone", "MBIAS",
+ "MIC1", "Internal Microphone",
+ "Headset Microphone", "HBIAS",
+ "MIC2", "Headset Microphone";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pb_pins>;
+ status = "okay";
+};
+
+/* Connected to the modem (hardware flow control can't be used) */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usb_power_supply {
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
--
2.26.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 8/8] Initial Pine64 Pinephone support
2020-07-22 14:18 Initial support for the Pine64 Pinephone Peter Robinson
` (6 preceding siblings ...)
2020-07-22 14:18 ` [PATCH 7/8] arm64: dts: allwinner: Add initial support for Pine64 PinePhone Peter Robinson
@ 2020-07-22 14:18 ` Peter Robinson
2020-07-27 13:30 ` Maxime Ripard
7 siblings, 1 reply; 17+ messages in thread
From: Peter Robinson @ 2020-07-22 14:18 UTC (permalink / raw)
To: u-boot
The Pine64 Pinephone is a smartphone based on the AllWinner A64 SoC.
It has the following features:
* 2GB LPDDR3 SDRAM
* 5.95 inch 1440x720 HD IPS capacitive touchscreen
* 16GB eMMC, mSD slot
* Quectel EG25 LTE Modem
* Realtek RTL8723CS WiFi/BT
* Front and read cameras
* Accelerometer, gyro, proximity, ambient light, compass sensors
* A USB Type-C, USB Host, DisplayPort alt mode output, 15W 5V 3A Quick Charge, follows USB PD specification
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
---
arch/arm/Kconfig | 2 +-
configs/pinephone_defconfig | 38 +++++++++++++++++++++++++++++++++++++
2 files changed, 39 insertions(+), 1 deletion(-)
create mode 100644 configs/pinephone_defconfig
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e16fe03887..636ba26938 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1004,7 +1004,7 @@ config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
select BINMAN
select CMD_GPIO
- select CMD_MMC if MMC
+select CMD_MMC if MMC
select CMD_USB if DISTRO_DEFAULTS
select CLK
select DM
diff --git a/configs/pinephone_defconfig b/configs/pinephone_defconfig
new file mode 100644
index 0000000000..d5750aa954
--- /dev/null
+++ b/configs/pinephone_defconfig
@@ -0,0 +1,38 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SPL=y
+CONFIG_MACH_SUN50I=y
+CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
+CONFIG_DRAM_CLK=552
+CONFIG_DRAM_ZQ=3881949
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_R_I2C_ENABLE=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+# CONFIG_SPL_SPI_SUNXI is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinephone-1.1"
+CONFIG_OF_LIST="sun50i-a64-pinephone-1.1 sun50i-a64-pinephone-1.0"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_SUNXI=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_MII is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_DM_ETH is not set
+# CONFIG_PHY is not set
+# CONFIG_PHY_GIGE is not set
+# CONFIG_SUN8I_EMAC is not set
+# CONFIG_PHY_REALTEK is not set
+# CONFIG_CMD_SF is not set
+# CONFIG_SPI is not set
+# CONFIG_DM_SPI is not set
+# CONFIG_SPI_FLASH is not set
+# CONFIG_SPI_MEM is not set
+# CONFIG_DM_SPI_FLASH is not set
--
2.26.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 6/8] arm: dts: Sync the sun50i-a64.dtsi from Linux 5.8-rc1
2020-07-22 14:18 ` [PATCH 6/8] arm: dts: Sync the sun50i-a64.dtsi " Peter Robinson
@ 2020-07-22 23:14 ` André Przywara
2020-07-26 10:17 ` Peter Robinson
0 siblings, 1 reply; 17+ messages in thread
From: André Przywara @ 2020-07-22 23:14 UTC (permalink / raw)
To: u-boot
On 22/07/2020 15:18, Peter Robinson wrote:
> Sync the Allwinner A64 sun50i-a64.dtsi from Linux.
Hi Peter,
thanks for your series!
While this looks mostly straight-forward, the problem is that this patch
here affects all Allwinner boards. And for them it breaks older kernels,
which cannot cope with some of the changed bindings or nodes.
Your patches up until here are fine, since they only add nodes and
properties, but this update changes nodes, some in a non-compatible way.
Examples are dropping the "syscon" compatible (which requires 4.18 to
know about the new compatible string) and the dropping of
internal-osc-clk and the connected RTC change. This breaks any kernels
that don't know about the third RTC clock (<&rtc 2>) or the new
compatible string (introduced in 4.20). Similar effects show up in other
OSes.
I was experimenting with some small changes (compared to mainline) to
overcome those issues, mostly by *adding* compatible strings instead of
*replacing* them.
So I would like to ask for a few days so that I can do more testing with
various kernels. I would then post those changes, so that we can discuss
them.
Cheers,
Andre
>
> Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
> ---
> arch/arm/dts/sun50i-a64.dtsi | 532 ++++++++++++++++++++++++++++-------
> 1 file changed, 434 insertions(+), 98 deletions(-)
>
> diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
> index ff41abc96a..8dfbcd1440 100644
> --- a/arch/arm/dts/sun50i-a64.dtsi
> +++ b/arch/arm/dts/sun50i-a64.dtsi
> @@ -1,46 +1,7 @@
> -/*
> - * Copyright (C) 2016 ARM Ltd.
> - * based on the Allwinner H3 dtsi:
> - * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
> - *
> - * This file is dual-licensed: you can use it either under the terms
> - * of the GPL or the X11 license, at your option. Note that this dual
> - * licensing only applies to this file, and not this project as a
> - * whole.
> - *
> - * a) This file is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of the
> - * License, or (at your option) any later version.
> - *
> - * This file is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - * Or, alternatively,
> - *
> - * b) Permission is hereby granted, free of charge, to any person
> - * obtaining a copy of this software and associated documentation
> - * files (the "Software"), to deal in the Software without
> - * restriction, including without limitation the rights to use,
> - * copy, modify, merge, publish, distribute, sublicense, and/or
> - * sell copies of the Software, and to permit persons to whom the
> - * Software is furnished to do so, subject to the following
> - * conditions:
> - *
> - * The above copyright notice and this permission notice shall be
> - * included in all copies or substantial portions of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> - * OTHER DEALINGS IN THE SOFTWARE.
> - */
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (C) 2016 ARM Ltd.
> +// based on the Allwinner H3 dtsi:
> +// Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
>
> #include <dt-bindings/clock/sun50i-a64-ccu.h>
> #include <dt-bindings/clock/sun8i-de2.h>
> @@ -49,6 +10,7 @@
> #include <dt-bindings/reset/sun50i-a64-ccu.h>
> #include <dt-bindings/reset/sun8i-de2.h>
> #include <dt-bindings/reset/sun8i-r-ccu.h>
> +#include <dt-bindings/thermal/thermal.h>
>
> / {
> interrupt-parent = <&gic>;
> @@ -84,35 +46,47 @@
> #size-cells = <0>;
>
> cpu0: cpu at 0 {
> - compatible = "arm,cortex-a53", "arm,armv8";
> + compatible = "arm,cortex-a53";
> device_type = "cpu";
> reg = <0>;
> enable-method = "psci";
> next-level-cache = <&L2>;
> + clocks = <&ccu 21>;
> + clock-names = "cpu";
> + #cooling-cells = <2>;
> };
>
> cpu1: cpu at 1 {
> - compatible = "arm,cortex-a53", "arm,armv8";
> + compatible = "arm,cortex-a53";
> device_type = "cpu";
> reg = <1>;
> enable-method = "psci";
> next-level-cache = <&L2>;
> + clocks = <&ccu 21>;
> + clock-names = "cpu";
> + #cooling-cells = <2>;
> };
>
> cpu2: cpu at 2 {
> - compatible = "arm,cortex-a53", "arm,armv8";
> + compatible = "arm,cortex-a53";
> device_type = "cpu";
> reg = <2>;
> enable-method = "psci";
> next-level-cache = <&L2>;
> + clocks = <&ccu 21>;
> + clock-names = "cpu";
> + #cooling-cells = <2>;
> };
>
> cpu3: cpu at 3 {
> - compatible = "arm,cortex-a53", "arm,armv8";
> + compatible = "arm,cortex-a53";
> device_type = "cpu";
> reg = <3>;
> enable-method = "psci";
> next-level-cache = <&L2>;
> + clocks = <&ccu 21>;
> + clock-names = "cpu";
> + #cooling-cells = <2>;
> };
>
> L2: l2-cache {
> @@ -139,15 +113,16 @@
> #clock-cells = <0>;
> compatible = "fixed-clock";
> clock-frequency = <32768>;
> - clock-output-names = "osc32k";
> + clock-output-names = "ext-osc32k";
> };
>
> - iosc: internal-osc-clk {
> - #clock-cells = <0>;
> - compatible = "fixed-clock";
> - clock-frequency = <16000000>;
> - clock-accuracy = <300000000>;
> - clock-output-names = "iosc";
> + pmu {
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> };
>
> psci {
> @@ -155,26 +130,33 @@
> method = "smc";
> };
>
> - sound_spdif {
> + sound: sound {
> compatible = "simple-audio-card";
> - simple-audio-card,name = "On-board SPDIF";
> + simple-audio-card,name = "sun50i-a64-audio";
> + simple-audio-card,format = "i2s";
> + simple-audio-card,frame-master = <&cpudai>;
> + simple-audio-card,bitclock-master = <&cpudai>;
> + simple-audio-card,mclk-fs = <128>;
> + simple-audio-card,aux-devs = <&codec_analog>;
> + simple-audio-card,routing =
> + "Left DAC", "AIF1 Slot 0 Left",
> + "Right DAC", "AIF1 Slot 0 Right",
> + "AIF1 Slot 0 Left ADC", "Left ADC",
> + "AIF1 Slot 0 Right ADC", "Right ADC";
> + status = "disabled";
>
> - simple-audio-card,cpu {
> - sound-dai = <&spdif>;
> + cpudai: simple-audio-card,cpu {
> + sound-dai = <&dai>;
> };
>
> - simple-audio-card,codec {
> - sound-dai = <&spdif_out>;
> + link_codec: simple-audio-card,codec {
> + sound-dai = <&codec>;
> };
> };
>
> - spdif_out: spdif-out {
> - #sound-dai-cells = <0>;
> - compatible = "linux,spdif-dit";
> - };
> -
> timer {
> compatible = "arm,armv8-timer";
> + allwinner,erratum-unknown1;
> interrupts = <GIC_PPI 13
> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> <GIC_PPI 14
> @@ -185,13 +167,76 @@
> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> };
>
> + thermal-zones {
> + cpu_thermal: cpu0-thermal {
> + /* milliseconds */
> + polling-delay-passive = <0>;
> + polling-delay = <0>;
> + thermal-sensors = <&ths 0>;
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu_alert0>;
> + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + map1 {
> + trip = <&cpu_alert1>;
> + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> +
> + trips {
> + cpu_alert0: cpu_alert0 {
> + /* milliCelsius */
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_alert1: cpu_alert1 {
> + /* milliCelsius */
> + temperature = <90000>;
> + hysteresis = <2000>;
> + type = "hot";
> + };
> +
> + cpu_crit: cpu_crit {
> + /* milliCelsius */
> + temperature = <110000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + gpu0_thermal: gpu0-thermal {
> + /* milliseconds */
> + polling-delay-passive = <0>;
> + polling-delay = <0>;
> + thermal-sensors = <&ths 1>;
> + };
> +
> + gpu1_thermal: gpu1-thermal {
> + /* milliseconds */
> + polling-delay-passive = <0>;
> + polling-delay = <0>;
> + thermal-sensors = <&ths 2>;
> + };
> + };
> +
> soc {
> compatible = "simple-bus";
> #address-cells = <1>;
> #size-cells = <1>;
> ranges;
>
> - de2 at 1000000 {
> + bus at 1000000 {
> compatible = "allwinner,sun50i-a64-de2";
> reg = <0x1000000 0x400000>;
> allwinner,sram = <&de2_sram 1>;
> @@ -201,16 +246,28 @@
>
> display_clocks: clock at 0 {
> compatible = "allwinner,sun50i-a64-de2-clk";
> - reg = <0x0 0x100000>;
> - clocks = <&ccu CLK_DE>,
> - <&ccu CLK_BUS_DE>;
> - clock-names = "mod",
> - "bus";
> + reg = <0x0 0x10000>;
> + clocks = <&ccu CLK_BUS_DE>,
> + <&ccu CLK_DE>;
> + clock-names = "bus",
> + "mod";
> resets = <&ccu RST_BUS_DE>;
> #clock-cells = <1>;
> #reset-cells = <1>;
> };
>
> + rotate: rotate at 20000 {
> + compatible = "allwinner,sun50i-a64-de2-rotate",
> + "allwinner,sun8i-a83t-de2-rotate";
> + reg = <0x20000 0x10000>;
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&display_clocks CLK_BUS_ROT>,
> + <&display_clocks CLK_ROT>;
> + clock-names = "bus",
> + "mod";
> + resets = <&display_clocks RST_ROT>;
> + };
> +
> mixer0: mixer at 100000 {
> compatible = "allwinner,sun50i-a64-de2-mixer-0";
> reg = <0x100000 0x100000>;
> @@ -225,11 +282,19 @@
> #size-cells = <0>;
>
> mixer0_out: port at 1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> reg = <1>;
>
> - mixer0_out_tcon0: endpoint {
> + mixer0_out_tcon0: endpoint at 0 {
> + reg = <0>;
> remote-endpoint = <&tcon0_in_mixer0>;
> };
> +
> + mixer0_out_tcon1: endpoint at 1 {
> + reg = <1>;
> + remote-endpoint = <&tcon1_in_mixer0>;
> + };
> };
> };
> };
> @@ -248,9 +313,17 @@
> #size-cells = <0>;
>
> mixer1_out: port at 1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> reg = <1>;
>
> - mixer1_out_tcon1: endpoint {
> + mixer1_out_tcon0: endpoint at 0 {
> + reg = <0>;
> + remote-endpoint = <&tcon0_in_mixer1>;
> + };
> +
> + mixer1_out_tcon1: endpoint at 1 {
> + reg = <1>;
> remote-endpoint = <&tcon1_in_mixer1>;
> };
> };
> @@ -259,8 +332,7 @@
> };
>
> syscon: syscon at 1c00000 {
> - compatible = "allwinner,sun50i-a64-system-control",
> - "syscon";
> + compatible = "allwinner,sun50i-a64-system-control";
> reg = <0x01c00000 0x1000>;
> #address-cells = <1>;
> #size-cells = <1>;
> @@ -278,6 +350,20 @@
> reg = <0x0000 0x28000>;
> };
> };
> +
> + sram_c1: sram at 1d00000 {
> + compatible = "mmio-sram";
> + reg = <0x01d00000 0x40000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x01d00000 0x40000>;
> +
> + ve_sram: sram-section at 0 {
> + compatible = "allwinner,sun50i-a64-sram-c1",
> + "allwinner,sun4i-a10-sram-c1";
> + reg = <0x000000 0x40000>;
> + };
> + };
> };
>
> dma: dma-controller at 1c02000 {
> @@ -299,6 +385,7 @@
> clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
> clock-names = "ahb", "tcon-ch0";
> clock-output-names = "tcon-pixel-clock";
> + #clock-cells = <0>;
> resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
> reset-names = "lcd", "lvds";
>
> @@ -315,12 +402,23 @@
> reg = <0>;
> remote-endpoint = <&mixer0_out_tcon0>;
> };
> +
> + tcon0_in_mixer1: endpoint at 1 {
> + reg = <1>;
> + remote-endpoint = <&mixer1_out_tcon0>;
> + };
> };
>
> tcon0_out: port at 1 {
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <1>;
> +
> + tcon0_out_dsi: endpoint at 1 {
> + reg = <1>;
> + remote-endpoint = <&dsi_in_tcon0>;
> + allwinner,tcon-channel = <1>;
> + };
> };
> };
> };
> @@ -340,9 +438,17 @@
> #size-cells = <0>;
>
> tcon1_in: port at 0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> reg = <0>;
>
> - tcon1_in_mixer1: endpoint {
> + tcon1_in_mixer0: endpoint at 0 {
> + reg = <0>;
> + remote-endpoint = <&mixer0_out_tcon1>;
> + };
> +
> + tcon1_in_mixer1: endpoint at 1 {
> + reg = <1>;
> remote-endpoint = <&mixer1_out_tcon1>;
> };
> };
> @@ -360,6 +466,17 @@
> };
> };
>
> + video-codec at 1c0e000 {
> + compatible = "allwinner,sun50i-a64-video-engine";
> + reg = <0x01c0e000 0x1000>;
> + clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
> + <&ccu CLK_DRAM_VE>;
> + clock-names = "ahb", "mod", "ram";
> + resets = <&ccu RST_BUS_VE>;
> + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
> + allwinner,sram = <&ve_sram 1>;
> + };
> +
> mmc0: mmc at 1c0f000 {
> compatible = "allwinner,sun50i-a64-mmc";
> reg = <0x01c0f000 0x1000>;
> @@ -405,6 +522,31 @@
> sid: eeprom at 1c14000 {
> compatible = "allwinner,sun50i-a64-sid";
> reg = <0x1c14000 0x400>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + ths_calibration: thermal-sensor-calibration at 34 {
> + reg = <0x34 0x8>;
> + };
> + };
> +
> + crypto: crypto at 1c15000 {
> + compatible = "allwinner,sun50i-a64-crypto";
> + reg = <0x01c15000 0x1000>;
> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
> + clock-names = "bus", "mod";
> + resets = <&ccu RST_BUS_CE>;
> + };
> +
> + msgbox: mailbox at 1c17000 {
> + compatible = "allwinner,sun50i-a64-msgbox",
> + "allwinner,sun6i-a31-msgbox";
> + reg = <0x01c17000 0x1000>;
> + clocks = <&ccu CLK_BUS_MSGBOX>;
> + resets = <&ccu RST_BUS_MSGBOX>;
> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> + #mbox-cells = <1>;
> };
>
> usb_otg: usb at 1c19000 {
> @@ -417,6 +559,7 @@
> phys = <&usbphy 0>;
> phy-names = "usb";
> extcon = <&usbphy 0>;
> + dr_mode = "otg";
> status = "disabled";
> };
>
> @@ -491,7 +634,7 @@
> ccu: clock at 1c20000 {
> compatible = "allwinner,sun50i-a64-ccu";
> reg = <0x01c20000 0x400>;
> - clocks = <&osc24M>, <&osc32k>;
> + clocks = <&osc24M>, <&rtc 0>;
> clock-names = "hosc", "losc";
> #clock-cells = <1>;
> #reset-cells = <1>;
> @@ -503,22 +646,50 @@
> interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&ccu 58>;
> + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
> + clock-names = "apb", "hosc", "losc";
> gpio-controller;
> #gpio-cells = <3>;
> interrupt-controller;
> #interrupt-cells = <3>;
>
> - i2c0_pins: i2c0_pins {
> + csi_pins: csi-pins {
> + pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
> + "PE7", "PE8", "PE9", "PE10", "PE11";
> + function = "csi";
> + };
> +
> + /omit-if-no-ref/
> + csi_mclk_pin: csi-mclk-pin {
> + pins = "PE1";
> + function = "csi";
> + };
> +
> + i2c0_pins: i2c0-pins {
> pins = "PH0", "PH1";
> function = "i2c0";
> };
>
> - i2c1_pins: i2c1_pins {
> + i2c1_pins: i2c1-pins {
> pins = "PH2", "PH3";
> function = "i2c1";
> };
>
> + i2c2_pins: i2c2-pins {
> + pins = "PE14", "PE15";
> + function = "i2c2";
> + };
> +
> + /omit-if-no-ref/
> + lcd_rgb666_pins: lcd-rgb666-pins {
> + pins = "PD0", "PD1", "PD2", "PD3", "PD4",
> + "PD5", "PD6", "PD7", "PD8", "PD9",
> + "PD10", "PD11", "PD12", "PD13",
> + "PD14", "PD15", "PD16", "PD17",
> + "PD18", "PD19", "PD20", "PD21";
> + function = "lcd0";
> + };
> +
> mmc0_pins: mmc0-pins {
> pins = "PF0", "PF1", "PF2", "PF3",
> "PF4", "PF5";
> @@ -551,19 +722,19 @@
> bias-pull-up;
> };
>
> - pwm_pin: pwm_pin {
> + pwm_pin: pwm-pin {
> pins = "PD22";
> function = "pwm";
> };
>
> - rmii_pins: rmii_pins {
> + rmii_pins: rmii-pins {
> pins = "PD10", "PD11", "PD13", "PD14", "PD17",
> "PD18", "PD19", "PD20", "PD22", "PD23";
> function = "emac";
> drive-strength = <40>;
> };
>
> - rgmii_pins: rgmii_pins {
> + rgmii_pins: rgmii-pins {
> pins = "PD8", "PD9", "PD10", "PD11", "PD12",
> "PD13", "PD15", "PD16", "PD17", "PD18",
> "PD19", "PD20", "PD21", "PD22", "PD23";
> @@ -571,17 +742,17 @@
> drive-strength = <40>;
> };
>
> - spdif_tx_pin: spdif {
> + spdif_tx_pin: spdif-tx-pin {
> pins = "PH8";
> function = "spdif";
> };
>
> - spi0_pins: spi0 {
> + spi0_pins: spi0-pins {
> pins = "PC0", "PC1", "PC2", "PC3";
> function = "spi0";
> };
>
> - spi1_pins: spi1 {
> + spi1_pins: spi1-pins {
> pins = "PD0", "PD1", "PD2", "PD3";
> function = "spi1";
> };
> @@ -591,12 +762,12 @@
> function = "uart0";
> };
>
> - uart1_pins: uart1_pins {
> + uart1_pins: uart1-pins {
> pins = "PG6", "PG7";
> function = "uart1";
> };
>
> - uart1_rts_cts_pins: uart1_rts_cts_pins {
> + uart1_rts_cts_pins: uart1-rts-cts-pins {
> pins = "PG8", "PG9";
> function = "uart1";
> };
> @@ -638,6 +809,14 @@
> status = "disabled";
> };
>
> + lradc: lradc at 1c21800 {
> + compatible = "allwinner,sun50i-a64-lradc",
> + "allwinner,sun8i-a83t-r-lradc";
> + reg = <0x01c21800 0x400>;
> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> i2s0: i2s at 1c22000 {
> #sound-dai-cells = <0>;
> compatible = "allwinner,sun50i-a64-i2s",
> @@ -666,6 +845,41 @@
> status = "disabled";
> };
>
> + dai: dai at 1c22c00 {
> + #sound-dai-cells = <0>;
> + compatible = "allwinner,sun50i-a64-codec-i2s";
> + reg = <0x01c22c00 0x200>;
> + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
> + clock-names = "apb", "mod";
> + resets = <&ccu RST_BUS_CODEC>;
> + dmas = <&dma 15>, <&dma 15>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + codec: codec at 1c22e00 {
> + #sound-dai-cells = <0>;
> + compatible = "allwinner,sun8i-a33-codec";
> + reg = <0x01c22e00 0x600>;
> + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
> + clock-names = "bus", "mod";
> + status = "disabled";
> + };
> +
> + ths: thermal-sensor at 1c25000 {
> + compatible = "allwinner,sun50i-a64-ths";
> + reg = <0x01c25000 0x100>;
> + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
> + clock-names = "bus", "mod";
> + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> + resets = <&ccu RST_BUS_THS>;
> + nvmem-cells = <&ths_calibration>;
> + nvmem-cell-names = "calibration";
> + #thermal-sensor-cells = <1>;
> + };
> +
> uart0: serial at 1c28000 {
> compatible = "snps,dw-apb-uart";
> reg = <0x01c28000 0x400>;
> @@ -727,6 +941,8 @@
> interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&ccu CLK_BUS_I2C0>;
> resets = <&ccu RST_BUS_I2C0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c0_pins>;
> status = "disabled";
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -738,6 +954,8 @@
> interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&ccu CLK_BUS_I2C1>;
> resets = <&ccu RST_BUS_I2C1>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c1_pins>;
> status = "disabled";
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -749,12 +967,13 @@
> interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&ccu CLK_BUS_I2C2>;
> resets = <&ccu RST_BUS_I2C2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c2_pins>;
> status = "disabled";
> #address-cells = <1>;
> #size-cells = <0>;
> };
>
> -
> spi0: spi at 1c68000 {
> compatible = "allwinner,sun8i-h3-spi";
> reg = <0x01c68000 0x1000>;
> @@ -808,6 +1027,28 @@
> };
> };
>
> + mali: gpu at 1c40000 {
> + compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
> + reg = <0x01c40000 0x10000>;
> + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "gp",
> + "gpmmu",
> + "pp0",
> + "ppmmu0",
> + "pp1",
> + "ppmmu1",
> + "pmu";
> + clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
> + clock-names = "bus", "core";
> + resets = <&ccu RST_BUS_GPU>;
> + };
> +
> gic: interrupt-controller at 1c81000 {
> compatible = "arm,gic-400";
> reg = <0x01c81000 0x1000>,
> @@ -830,6 +1071,75 @@
> status = "disabled";
> };
>
> + mbus: dram-controller at 1c62000 {
> + compatible = "allwinner,sun50i-a64-mbus";
> + reg = <0x01c62000 0x1000>;
> + clocks = <&ccu 112>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + dma-ranges = <0x00000000 0x40000000 0xc0000000>;
> + #interconnect-cells = <1>;
> + };
> +
> + csi: csi at 1cb0000 {
> + compatible = "allwinner,sun50i-a64-csi";
> + reg = <0x01cb0000 0x1000>;
> + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_CSI>,
> + <&ccu CLK_CSI_SCLK>,
> + <&ccu CLK_DRAM_CSI>;
> + clock-names = "bus", "mod", "ram";
> + resets = <&ccu RST_BUS_CSI>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&csi_pins>;
> + status = "disabled";
> + };
> +
> + dsi: dsi at 1ca0000 {
> + compatible = "allwinner,sun50i-a64-mipi-dsi";
> + reg = <0x01ca0000 0x1000>;
> + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_MIPI_DSI>;
> + resets = <&ccu RST_BUS_MIPI_DSI>;
> + phys = <&dphy>;
> + phy-names = "dphy";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port {
> + dsi_in_tcon0: endpoint {
> + remote-endpoint = <&tcon0_out_dsi>;
> + };
> + };
> + };
> +
> + dphy: d-phy at 1ca1000 {
> + compatible = "allwinner,sun50i-a64-mipi-dphy",
> + "allwinner,sun6i-a31-mipi-dphy";
> + reg = <0x01ca1000 0x1000>;
> + clocks = <&ccu CLK_BUS_MIPI_DSI>,
> + <&ccu CLK_DSI_DPHY>;
> + clock-names = "bus", "mod";
> + resets = <&ccu RST_BUS_MIPI_DSI>;
> + status = "disabled";
> + #phy-cells = <0>;
> + };
> +
> + deinterlace: deinterlace at 1e00000 {
> + compatible = "allwinner,sun50i-a64-deinterlace",
> + "allwinner,sun8i-h3-deinterlace";
> + reg = <0x01e00000 0x20000>;
> + clocks = <&ccu CLK_BUS_DEINTERLACE>,
> + <&ccu CLK_DEINTERLACE>,
> + <&ccu CLK_DRAM_DEINTERLACE>;
> + clock-names = "bus", "mod", "ram";
> + resets = <&ccu RST_BUS_DEINTERLACE>;
> + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
> + interconnects = <&mbus 9>;
> + interconnect-names = "dma-mem";
> + };
> +
> hdmi: hdmi at 1ee0000 {
> compatible = "allwinner,sun50i-a64-dw-hdmi",
> "allwinner,sun8i-a83t-dw-hdmi";
> @@ -842,7 +1152,7 @@
> resets = <&ccu RST_BUS_HDMI1>;
> reset-names = "ctrl";
> phys = <&hdmi_phy>;
> - phy-names = "hdmi-phy";
> + phy-names = "phy";
> status = "disabled";
>
> ports {
> @@ -867,7 +1177,7 @@
> compatible = "allwinner,sun50i-a64-hdmi-phy";
> reg = <0x01ef0000 0x10000>;
> clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
> - <&ccu 7>;
> + <&ccu CLK_PLL_VIDEO0>;
> clock-names = "bus", "mod", "pll-0";
> resets = <&ccu RST_BUS_HDMI0>;
> reset-names = "phy";
> @@ -875,11 +1185,12 @@
> };
>
> rtc: rtc at 1f00000 {
> - compatible = "allwinner,sun6i-a31-rtc";
> - reg = <0x01f00000 0x54>;
> + compatible = "allwinner,sun50i-a64-rtc",
> + "allwinner,sun8i-h3-rtc";
> + reg = <0x01f00000 0x400>;
> interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> - clock-output-names = "rtc-osc32k", "rtc-osc32k-out";
> + clock-output-names = "osc32k", "osc32k-out", "iosc";
> clocks = <&osc32k>;
> #clock-cells = <1>;
> };
> @@ -896,13 +1207,19 @@
> r_ccu: clock at 1f01400 {
> compatible = "allwinner,sun50i-a64-r-ccu";
> reg = <0x01f01400 0x100>;
> - clocks = <&osc24M>, <&osc32k>, <&iosc>,
> - <&ccu 11>;
> + clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
> + <&ccu CLK_PLL_PERIPH0>;
> clock-names = "hosc", "losc", "iosc", "pll-periph";
> #clock-cells = <1>;
> #reset-cells = <1>;
> };
>
> + codec_analog: codec-analog at 1f015c0 {
> + compatible = "allwinner,sun50i-a64-codec-analog";
> + reg = <0x01f015c0 0x4>;
> + status = "disabled";
> + };
> +
> r_i2c: i2c at 1f02400 {
> compatible = "allwinner,sun50i-a64-i2c",
> "allwinner,sun6i-a31-i2c";
> @@ -915,6 +1232,19 @@
> #size-cells = <0>;
> };
>
> + r_ir: ir at 1f02000 {
> + compatible = "allwinner,sun50i-a64-ir",
> + "allwinner,sun6i-a31-ir";
> + reg = <0x01f02000 0x400>;
> + clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
> + clock-names = "apb", "ir";
> + resets = <&r_ccu RST_APB0_IR>;
> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&r_ir_rx_pin>;
> + status = "disabled";
> + };
> +
> r_pwm: pwm at 1f03800 {
> compatible = "allwinner,sun50i-a64-pwm",
> "allwinner,sun5i-a13-pwm";
> @@ -942,12 +1272,17 @@
> function = "s_i2c";
> };
>
> - r_pwm_pin: pwm {
> + r_ir_rx_pin: r-ir-rx-pin {
> + pins = "PL11";
> + function = "s_cir_rx";
> + };
> +
> + r_pwm_pin: r-pwm-pin {
> pins = "PL10";
> function = "s_pwm";
> };
>
> - r_rsb_pins: rsb {
> + r_rsb_pins: r-rsb-pins {
> pins = "PL0", "PL1";
> function = "s_rsb";
> };
> @@ -972,6 +1307,7 @@
> "allwinner,sun6i-a31-wdt";
> reg = <0x01c20ca0 0x20>;
> interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>;
> };
> };
> };
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 6/8] arm: dts: Sync the sun50i-a64.dtsi from Linux 5.8-rc1
2020-07-22 23:14 ` André Przywara
@ 2020-07-26 10:17 ` Peter Robinson
2020-07-27 13:16 ` Heinrich Schuchardt
0 siblings, 1 reply; 17+ messages in thread
From: Peter Robinson @ 2020-07-26 10:17 UTC (permalink / raw)
To: u-boot
On Thu, Jul 23, 2020 at 12:15 AM Andr? Przywara <andre.przywara@arm.com> wrote:
>
> On 22/07/2020 15:18, Peter Robinson wrote:
> > Sync the Allwinner A64 sun50i-a64.dtsi from Linux.
>
> Hi Peter,
>
> thanks for your series!
>
> While this looks mostly straight-forward, the problem is that this patch
> here affects all Allwinner boards. And for them it breaks older kernels,
> which cannot cope with some of the changed bindings or nodes.
> Your patches up until here are fine, since they only add nodes and
> properties, but this update changes nodes, some in a non-compatible way.
>
> Examples are dropping the "syscon" compatible (which requires 4.18 to
> know about the new compatible string) and the dropping of
> internal-osc-clk and the connected RTC change. This breaks any kernels
> that don't know about the third RTC clock (<&rtc 2>) or the new
> compatible string (introduced in 4.20). Similar effects show up in other
> OSes.
The 4.18 kernel is over 2 years old. How many users are going to
actively upgrade U-Boot to the latest and not the kernel all while
using the U-Boot provided DT and not just loading the matching kernel
DT supplied by what ever ancient kernel they happen to choose to use?
I feel this use case is quite a corner case and in those cases they're
probably not using a vanilla upstream U-Boot anyway.
> I was experimenting with some small changes (compared to mainline) to
> overcome those issues, mostly by *adding* compatible strings instead of
> *replacing* them.
Shouldn't they be added to a -u-boot.dtsi?
> So I would like to ask for a few days so that I can do more testing with
> various kernels. I would then post those changes, so that we can discuss
> them.
>
> Cheers,
> Andre
>
> >
> > Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
> > ---
> > arch/arm/dts/sun50i-a64.dtsi | 532 ++++++++++++++++++++++++++++-------
> > 1 file changed, 434 insertions(+), 98 deletions(-)
> >
> > diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
> > index ff41abc96a..8dfbcd1440 100644
> > --- a/arch/arm/dts/sun50i-a64.dtsi
> > +++ b/arch/arm/dts/sun50i-a64.dtsi
> > @@ -1,46 +1,7 @@
> > -/*
> > - * Copyright (C) 2016 ARM Ltd.
> > - * based on the Allwinner H3 dtsi:
> > - * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
> > - *
> > - * This file is dual-licensed: you can use it either under the terms
> > - * of the GPL or the X11 license, at your option. Note that this dual
> > - * licensing only applies to this file, and not this project as a
> > - * whole.
> > - *
> > - * a) This file is free software; you can redistribute it and/or
> > - * modify it under the terms of the GNU General Public License as
> > - * published by the Free Software Foundation; either version 2 of the
> > - * License, or (at your option) any later version.
> > - *
> > - * This file is distributed in the hope that it will be useful,
> > - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > - * GNU General Public License for more details.
> > - *
> > - * Or, alternatively,
> > - *
> > - * b) Permission is hereby granted, free of charge, to any person
> > - * obtaining a copy of this software and associated documentation
> > - * files (the "Software"), to deal in the Software without
> > - * restriction, including without limitation the rights to use,
> > - * copy, modify, merge, publish, distribute, sublicense, and/or
> > - * sell copies of the Software, and to permit persons to whom the
> > - * Software is furnished to do so, subject to the following
> > - * conditions:
> > - *
> > - * The above copyright notice and this permission notice shall be
> > - * included in all copies or substantial portions of the Software.
> > - *
> > - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> > - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> > - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> > - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> > - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > - * OTHER DEALINGS IN THE SOFTWARE.
> > - */
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +// Copyright (C) 2016 ARM Ltd.
> > +// based on the Allwinner H3 dtsi:
> > +// Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
> >
> > #include <dt-bindings/clock/sun50i-a64-ccu.h>
> > #include <dt-bindings/clock/sun8i-de2.h>
> > @@ -49,6 +10,7 @@
> > #include <dt-bindings/reset/sun50i-a64-ccu.h>
> > #include <dt-bindings/reset/sun8i-de2.h>
> > #include <dt-bindings/reset/sun8i-r-ccu.h>
> > +#include <dt-bindings/thermal/thermal.h>
> >
> > / {
> > interrupt-parent = <&gic>;
> > @@ -84,35 +46,47 @@
> > #size-cells = <0>;
> >
> > cpu0: cpu at 0 {
> > - compatible = "arm,cortex-a53", "arm,armv8";
> > + compatible = "arm,cortex-a53";
> > device_type = "cpu";
> > reg = <0>;
> > enable-method = "psci";
> > next-level-cache = <&L2>;
> > + clocks = <&ccu 21>;
> > + clock-names = "cpu";
> > + #cooling-cells = <2>;
> > };
> >
> > cpu1: cpu at 1 {
> > - compatible = "arm,cortex-a53", "arm,armv8";
> > + compatible = "arm,cortex-a53";
> > device_type = "cpu";
> > reg = <1>;
> > enable-method = "psci";
> > next-level-cache = <&L2>;
> > + clocks = <&ccu 21>;
> > + clock-names = "cpu";
> > + #cooling-cells = <2>;
> > };
> >
> > cpu2: cpu at 2 {
> > - compatible = "arm,cortex-a53", "arm,armv8";
> > + compatible = "arm,cortex-a53";
> > device_type = "cpu";
> > reg = <2>;
> > enable-method = "psci";
> > next-level-cache = <&L2>;
> > + clocks = <&ccu 21>;
> > + clock-names = "cpu";
> > + #cooling-cells = <2>;
> > };
> >
> > cpu3: cpu at 3 {
> > - compatible = "arm,cortex-a53", "arm,armv8";
> > + compatible = "arm,cortex-a53";
> > device_type = "cpu";
> > reg = <3>;
> > enable-method = "psci";
> > next-level-cache = <&L2>;
> > + clocks = <&ccu 21>;
> > + clock-names = "cpu";
> > + #cooling-cells = <2>;
> > };
> >
> > L2: l2-cache {
> > @@ -139,15 +113,16 @@
> > #clock-cells = <0>;
> > compatible = "fixed-clock";
> > clock-frequency = <32768>;
> > - clock-output-names = "osc32k";
> > + clock-output-names = "ext-osc32k";
> > };
> >
> > - iosc: internal-osc-clk {
> > - #clock-cells = <0>;
> > - compatible = "fixed-clock";
> > - clock-frequency = <16000000>;
> > - clock-accuracy = <300000000>;
> > - clock-output-names = "iosc";
> > + pmu {
> > + compatible = "arm,cortex-a53-pmu";
> > + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> > };
> >
> > psci {
> > @@ -155,26 +130,33 @@
> > method = "smc";
> > };
> >
> > - sound_spdif {
> > + sound: sound {
> > compatible = "simple-audio-card";
> > - simple-audio-card,name = "On-board SPDIF";
> > + simple-audio-card,name = "sun50i-a64-audio";
> > + simple-audio-card,format = "i2s";
> > + simple-audio-card,frame-master = <&cpudai>;
> > + simple-audio-card,bitclock-master = <&cpudai>;
> > + simple-audio-card,mclk-fs = <128>;
> > + simple-audio-card,aux-devs = <&codec_analog>;
> > + simple-audio-card,routing =
> > + "Left DAC", "AIF1 Slot 0 Left",
> > + "Right DAC", "AIF1 Slot 0 Right",
> > + "AIF1 Slot 0 Left ADC", "Left ADC",
> > + "AIF1 Slot 0 Right ADC", "Right ADC";
> > + status = "disabled";
> >
> > - simple-audio-card,cpu {
> > - sound-dai = <&spdif>;
> > + cpudai: simple-audio-card,cpu {
> > + sound-dai = <&dai>;
> > };
> >
> > - simple-audio-card,codec {
> > - sound-dai = <&spdif_out>;
> > + link_codec: simple-audio-card,codec {
> > + sound-dai = <&codec>;
> > };
> > };
> >
> > - spdif_out: spdif-out {
> > - #sound-dai-cells = <0>;
> > - compatible = "linux,spdif-dit";
> > - };
> > -
> > timer {
> > compatible = "arm,armv8-timer";
> > + allwinner,erratum-unknown1;
> > interrupts = <GIC_PPI 13
> > (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> > <GIC_PPI 14
> > @@ -185,13 +167,76 @@
> > (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> > };
> >
> > + thermal-zones {
> > + cpu_thermal: cpu0-thermal {
> > + /* milliseconds */
> > + polling-delay-passive = <0>;
> > + polling-delay = <0>;
> > + thermal-sensors = <&ths 0>;
> > +
> > + cooling-maps {
> > + map0 {
> > + trip = <&cpu_alert0>;
> > + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> > + };
> > + map1 {
> > + trip = <&cpu_alert1>;
> > + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> > + };
> > + };
> > +
> > + trips {
> > + cpu_alert0: cpu_alert0 {
> > + /* milliCelsius */
> > + temperature = <75000>;
> > + hysteresis = <2000>;
> > + type = "passive";
> > + };
> > +
> > + cpu_alert1: cpu_alert1 {
> > + /* milliCelsius */
> > + temperature = <90000>;
> > + hysteresis = <2000>;
> > + type = "hot";
> > + };
> > +
> > + cpu_crit: cpu_crit {
> > + /* milliCelsius */
> > + temperature = <110000>;
> > + hysteresis = <2000>;
> > + type = "critical";
> > + };
> > + };
> > + };
> > +
> > + gpu0_thermal: gpu0-thermal {
> > + /* milliseconds */
> > + polling-delay-passive = <0>;
> > + polling-delay = <0>;
> > + thermal-sensors = <&ths 1>;
> > + };
> > +
> > + gpu1_thermal: gpu1-thermal {
> > + /* milliseconds */
> > + polling-delay-passive = <0>;
> > + polling-delay = <0>;
> > + thermal-sensors = <&ths 2>;
> > + };
> > + };
> > +
> > soc {
> > compatible = "simple-bus";
> > #address-cells = <1>;
> > #size-cells = <1>;
> > ranges;
> >
> > - de2 at 1000000 {
> > + bus at 1000000 {
> > compatible = "allwinner,sun50i-a64-de2";
> > reg = <0x1000000 0x400000>;
> > allwinner,sram = <&de2_sram 1>;
> > @@ -201,16 +246,28 @@
> >
> > display_clocks: clock at 0 {
> > compatible = "allwinner,sun50i-a64-de2-clk";
> > - reg = <0x0 0x100000>;
> > - clocks = <&ccu CLK_DE>,
> > - <&ccu CLK_BUS_DE>;
> > - clock-names = "mod",
> > - "bus";
> > + reg = <0x0 0x10000>;
> > + clocks = <&ccu CLK_BUS_DE>,
> > + <&ccu CLK_DE>;
> > + clock-names = "bus",
> > + "mod";
> > resets = <&ccu RST_BUS_DE>;
> > #clock-cells = <1>;
> > #reset-cells = <1>;
> > };
> >
> > + rotate: rotate at 20000 {
> > + compatible = "allwinner,sun50i-a64-de2-rotate",
> > + "allwinner,sun8i-a83t-de2-rotate";
> > + reg = <0x20000 0x10000>;
> > + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&display_clocks CLK_BUS_ROT>,
> > + <&display_clocks CLK_ROT>;
> > + clock-names = "bus",
> > + "mod";
> > + resets = <&display_clocks RST_ROT>;
> > + };
> > +
> > mixer0: mixer at 100000 {
> > compatible = "allwinner,sun50i-a64-de2-mixer-0";
> > reg = <0x100000 0x100000>;
> > @@ -225,11 +282,19 @@
> > #size-cells = <0>;
> >
> > mixer0_out: port at 1 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > reg = <1>;
> >
> > - mixer0_out_tcon0: endpoint {
> > + mixer0_out_tcon0: endpoint at 0 {
> > + reg = <0>;
> > remote-endpoint = <&tcon0_in_mixer0>;
> > };
> > +
> > + mixer0_out_tcon1: endpoint at 1 {
> > + reg = <1>;
> > + remote-endpoint = <&tcon1_in_mixer0>;
> > + };
> > };
> > };
> > };
> > @@ -248,9 +313,17 @@
> > #size-cells = <0>;
> >
> > mixer1_out: port at 1 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > reg = <1>;
> >
> > - mixer1_out_tcon1: endpoint {
> > + mixer1_out_tcon0: endpoint at 0 {
> > + reg = <0>;
> > + remote-endpoint = <&tcon0_in_mixer1>;
> > + };
> > +
> > + mixer1_out_tcon1: endpoint at 1 {
> > + reg = <1>;
> > remote-endpoint = <&tcon1_in_mixer1>;
> > };
> > };
> > @@ -259,8 +332,7 @@
> > };
> >
> > syscon: syscon at 1c00000 {
> > - compatible = "allwinner,sun50i-a64-system-control",
> > - "syscon";
> > + compatible = "allwinner,sun50i-a64-system-control";
> > reg = <0x01c00000 0x1000>;
> > #address-cells = <1>;
> > #size-cells = <1>;
> > @@ -278,6 +350,20 @@
> > reg = <0x0000 0x28000>;
> > };
> > };
> > +
> > + sram_c1: sram at 1d00000 {
> > + compatible = "mmio-sram";
> > + reg = <0x01d00000 0x40000>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0 0x01d00000 0x40000>;
> > +
> > + ve_sram: sram-section at 0 {
> > + compatible = "allwinner,sun50i-a64-sram-c1",
> > + "allwinner,sun4i-a10-sram-c1";
> > + reg = <0x000000 0x40000>;
> > + };
> > + };
> > };
> >
> > dma: dma-controller at 1c02000 {
> > @@ -299,6 +385,7 @@
> > clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
> > clock-names = "ahb", "tcon-ch0";
> > clock-output-names = "tcon-pixel-clock";
> > + #clock-cells = <0>;
> > resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
> > reset-names = "lcd", "lvds";
> >
> > @@ -315,12 +402,23 @@
> > reg = <0>;
> > remote-endpoint = <&mixer0_out_tcon0>;
> > };
> > +
> > + tcon0_in_mixer1: endpoint at 1 {
> > + reg = <1>;
> > + remote-endpoint = <&mixer1_out_tcon0>;
> > + };
> > };
> >
> > tcon0_out: port at 1 {
> > #address-cells = <1>;
> > #size-cells = <0>;
> > reg = <1>;
> > +
> > + tcon0_out_dsi: endpoint at 1 {
> > + reg = <1>;
> > + remote-endpoint = <&dsi_in_tcon0>;
> > + allwinner,tcon-channel = <1>;
> > + };
> > };
> > };
> > };
> > @@ -340,9 +438,17 @@
> > #size-cells = <0>;
> >
> > tcon1_in: port at 0 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > reg = <0>;
> >
> > - tcon1_in_mixer1: endpoint {
> > + tcon1_in_mixer0: endpoint at 0 {
> > + reg = <0>;
> > + remote-endpoint = <&mixer0_out_tcon1>;
> > + };
> > +
> > + tcon1_in_mixer1: endpoint at 1 {
> > + reg = <1>;
> > remote-endpoint = <&mixer1_out_tcon1>;
> > };
> > };
> > @@ -360,6 +466,17 @@
> > };
> > };
> >
> > + video-codec at 1c0e000 {
> > + compatible = "allwinner,sun50i-a64-video-engine";
> > + reg = <0x01c0e000 0x1000>;
> > + clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
> > + <&ccu CLK_DRAM_VE>;
> > + clock-names = "ahb", "mod", "ram";
> > + resets = <&ccu RST_BUS_VE>;
> > + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
> > + allwinner,sram = <&ve_sram 1>;
> > + };
> > +
> > mmc0: mmc at 1c0f000 {
> > compatible = "allwinner,sun50i-a64-mmc";
> > reg = <0x01c0f000 0x1000>;
> > @@ -405,6 +522,31 @@
> > sid: eeprom at 1c14000 {
> > compatible = "allwinner,sun50i-a64-sid";
> > reg = <0x1c14000 0x400>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + ths_calibration: thermal-sensor-calibration at 34 {
> > + reg = <0x34 0x8>;
> > + };
> > + };
> > +
> > + crypto: crypto at 1c15000 {
> > + compatible = "allwinner,sun50i-a64-crypto";
> > + reg = <0x01c15000 0x1000>;
> > + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
> > + clock-names = "bus", "mod";
> > + resets = <&ccu RST_BUS_CE>;
> > + };
> > +
> > + msgbox: mailbox at 1c17000 {
> > + compatible = "allwinner,sun50i-a64-msgbox",
> > + "allwinner,sun6i-a31-msgbox";
> > + reg = <0x01c17000 0x1000>;
> > + clocks = <&ccu CLK_BUS_MSGBOX>;
> > + resets = <&ccu RST_BUS_MSGBOX>;
> > + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> > + #mbox-cells = <1>;
> > };
> >
> > usb_otg: usb at 1c19000 {
> > @@ -417,6 +559,7 @@
> > phys = <&usbphy 0>;
> > phy-names = "usb";
> > extcon = <&usbphy 0>;
> > + dr_mode = "otg";
> > status = "disabled";
> > };
> >
> > @@ -491,7 +634,7 @@
> > ccu: clock at 1c20000 {
> > compatible = "allwinner,sun50i-a64-ccu";
> > reg = <0x01c20000 0x400>;
> > - clocks = <&osc24M>, <&osc32k>;
> > + clocks = <&osc24M>, <&rtc 0>;
> > clock-names = "hosc", "losc";
> > #clock-cells = <1>;
> > #reset-cells = <1>;
> > @@ -503,22 +646,50 @@
> > interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> > <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> > <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> > - clocks = <&ccu 58>;
> > + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
> > + clock-names = "apb", "hosc", "losc";
> > gpio-controller;
> > #gpio-cells = <3>;
> > interrupt-controller;
> > #interrupt-cells = <3>;
> >
> > - i2c0_pins: i2c0_pins {
> > + csi_pins: csi-pins {
> > + pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
> > + "PE7", "PE8", "PE9", "PE10", "PE11";
> > + function = "csi";
> > + };
> > +
> > + /omit-if-no-ref/
> > + csi_mclk_pin: csi-mclk-pin {
> > + pins = "PE1";
> > + function = "csi";
> > + };
> > +
> > + i2c0_pins: i2c0-pins {
> > pins = "PH0", "PH1";
> > function = "i2c0";
> > };
> >
> > - i2c1_pins: i2c1_pins {
> > + i2c1_pins: i2c1-pins {
> > pins = "PH2", "PH3";
> > function = "i2c1";
> > };
> >
> > + i2c2_pins: i2c2-pins {
> > + pins = "PE14", "PE15";
> > + function = "i2c2";
> > + };
> > +
> > + /omit-if-no-ref/
> > + lcd_rgb666_pins: lcd-rgb666-pins {
> > + pins = "PD0", "PD1", "PD2", "PD3", "PD4",
> > + "PD5", "PD6", "PD7", "PD8", "PD9",
> > + "PD10", "PD11", "PD12", "PD13",
> > + "PD14", "PD15", "PD16", "PD17",
> > + "PD18", "PD19", "PD20", "PD21";
> > + function = "lcd0";
> > + };
> > +
> > mmc0_pins: mmc0-pins {
> > pins = "PF0", "PF1", "PF2", "PF3",
> > "PF4", "PF5";
> > @@ -551,19 +722,19 @@
> > bias-pull-up;
> > };
> >
> > - pwm_pin: pwm_pin {
> > + pwm_pin: pwm-pin {
> > pins = "PD22";
> > function = "pwm";
> > };
> >
> > - rmii_pins: rmii_pins {
> > + rmii_pins: rmii-pins {
> > pins = "PD10", "PD11", "PD13", "PD14", "PD17",
> > "PD18", "PD19", "PD20", "PD22", "PD23";
> > function = "emac";
> > drive-strength = <40>;
> > };
> >
> > - rgmii_pins: rgmii_pins {
> > + rgmii_pins: rgmii-pins {
> > pins = "PD8", "PD9", "PD10", "PD11", "PD12",
> > "PD13", "PD15", "PD16", "PD17", "PD18",
> > "PD19", "PD20", "PD21", "PD22", "PD23";
> > @@ -571,17 +742,17 @@
> > drive-strength = <40>;
> > };
> >
> > - spdif_tx_pin: spdif {
> > + spdif_tx_pin: spdif-tx-pin {
> > pins = "PH8";
> > function = "spdif";
> > };
> >
> > - spi0_pins: spi0 {
> > + spi0_pins: spi0-pins {
> > pins = "PC0", "PC1", "PC2", "PC3";
> > function = "spi0";
> > };
> >
> > - spi1_pins: spi1 {
> > + spi1_pins: spi1-pins {
> > pins = "PD0", "PD1", "PD2", "PD3";
> > function = "spi1";
> > };
> > @@ -591,12 +762,12 @@
> > function = "uart0";
> > };
> >
> > - uart1_pins: uart1_pins {
> > + uart1_pins: uart1-pins {
> > pins = "PG6", "PG7";
> > function = "uart1";
> > };
> >
> > - uart1_rts_cts_pins: uart1_rts_cts_pins {
> > + uart1_rts_cts_pins: uart1-rts-cts-pins {
> > pins = "PG8", "PG9";
> > function = "uart1";
> > };
> > @@ -638,6 +809,14 @@
> > status = "disabled";
> > };
> >
> > + lradc: lradc at 1c21800 {
> > + compatible = "allwinner,sun50i-a64-lradc",
> > + "allwinner,sun8i-a83t-r-lradc";
> > + reg = <0x01c21800 0x400>;
> > + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > + };
> > +
> > i2s0: i2s at 1c22000 {
> > #sound-dai-cells = <0>;
> > compatible = "allwinner,sun50i-a64-i2s",
> > @@ -666,6 +845,41 @@
> > status = "disabled";
> > };
> >
> > + dai: dai at 1c22c00 {
> > + #sound-dai-cells = <0>;
> > + compatible = "allwinner,sun50i-a64-codec-i2s";
> > + reg = <0x01c22c00 0x200>;
> > + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
> > + clock-names = "apb", "mod";
> > + resets = <&ccu RST_BUS_CODEC>;
> > + dmas = <&dma 15>, <&dma 15>;
> > + dma-names = "rx", "tx";
> > + status = "disabled";
> > + };
> > +
> > + codec: codec at 1c22e00 {
> > + #sound-dai-cells = <0>;
> > + compatible = "allwinner,sun8i-a33-codec";
> > + reg = <0x01c22e00 0x600>;
> > + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
> > + clock-names = "bus", "mod";
> > + status = "disabled";
> > + };
> > +
> > + ths: thermal-sensor at 1c25000 {
> > + compatible = "allwinner,sun50i-a64-ths";
> > + reg = <0x01c25000 0x100>;
> > + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
> > + clock-names = "bus", "mod";
> > + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> > + resets = <&ccu RST_BUS_THS>;
> > + nvmem-cells = <&ths_calibration>;
> > + nvmem-cell-names = "calibration";
> > + #thermal-sensor-cells = <1>;
> > + };
> > +
> > uart0: serial at 1c28000 {
> > compatible = "snps,dw-apb-uart";
> > reg = <0x01c28000 0x400>;
> > @@ -727,6 +941,8 @@
> > interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> > clocks = <&ccu CLK_BUS_I2C0>;
> > resets = <&ccu RST_BUS_I2C0>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&i2c0_pins>;
> > status = "disabled";
> > #address-cells = <1>;
> > #size-cells = <0>;
> > @@ -738,6 +954,8 @@
> > interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> > clocks = <&ccu CLK_BUS_I2C1>;
> > resets = <&ccu RST_BUS_I2C1>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&i2c1_pins>;
> > status = "disabled";
> > #address-cells = <1>;
> > #size-cells = <0>;
> > @@ -749,12 +967,13 @@
> > interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> > clocks = <&ccu CLK_BUS_I2C2>;
> > resets = <&ccu RST_BUS_I2C2>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&i2c2_pins>;
> > status = "disabled";
> > #address-cells = <1>;
> > #size-cells = <0>;
> > };
> >
> > -
> > spi0: spi at 1c68000 {
> > compatible = "allwinner,sun8i-h3-spi";
> > reg = <0x01c68000 0x1000>;
> > @@ -808,6 +1027,28 @@
> > };
> > };
> >
> > + mali: gpu at 1c40000 {
> > + compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
> > + reg = <0x01c40000 0x10000>;
> > + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "gp",
> > + "gpmmu",
> > + "pp0",
> > + "ppmmu0",
> > + "pp1",
> > + "ppmmu1",
> > + "pmu";
> > + clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
> > + clock-names = "bus", "core";
> > + resets = <&ccu RST_BUS_GPU>;
> > + };
> > +
> > gic: interrupt-controller at 1c81000 {
> > compatible = "arm,gic-400";
> > reg = <0x01c81000 0x1000>,
> > @@ -830,6 +1071,75 @@
> > status = "disabled";
> > };
> >
> > + mbus: dram-controller at 1c62000 {
> > + compatible = "allwinner,sun50i-a64-mbus";
> > + reg = <0x01c62000 0x1000>;
> > + clocks = <&ccu 112>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + dma-ranges = <0x00000000 0x40000000 0xc0000000>;
> > + #interconnect-cells = <1>;
> > + };
> > +
> > + csi: csi at 1cb0000 {
> > + compatible = "allwinner,sun50i-a64-csi";
> > + reg = <0x01cb0000 0x1000>;
> > + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ccu CLK_BUS_CSI>,
> > + <&ccu CLK_CSI_SCLK>,
> > + <&ccu CLK_DRAM_CSI>;
> > + clock-names = "bus", "mod", "ram";
> > + resets = <&ccu RST_BUS_CSI>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&csi_pins>;
> > + status = "disabled";
> > + };
> > +
> > + dsi: dsi at 1ca0000 {
> > + compatible = "allwinner,sun50i-a64-mipi-dsi";
> > + reg = <0x01ca0000 0x1000>;
> > + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ccu CLK_BUS_MIPI_DSI>;
> > + resets = <&ccu RST_BUS_MIPI_DSI>;
> > + phys = <&dphy>;
> > + phy-names = "dphy";
> > + status = "disabled";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port {
> > + dsi_in_tcon0: endpoint {
> > + remote-endpoint = <&tcon0_out_dsi>;
> > + };
> > + };
> > + };
> > +
> > + dphy: d-phy at 1ca1000 {
> > + compatible = "allwinner,sun50i-a64-mipi-dphy",
> > + "allwinner,sun6i-a31-mipi-dphy";
> > + reg = <0x01ca1000 0x1000>;
> > + clocks = <&ccu CLK_BUS_MIPI_DSI>,
> > + <&ccu CLK_DSI_DPHY>;
> > + clock-names = "bus", "mod";
> > + resets = <&ccu RST_BUS_MIPI_DSI>;
> > + status = "disabled";
> > + #phy-cells = <0>;
> > + };
> > +
> > + deinterlace: deinterlace at 1e00000 {
> > + compatible = "allwinner,sun50i-a64-deinterlace",
> > + "allwinner,sun8i-h3-deinterlace";
> > + reg = <0x01e00000 0x20000>;
> > + clocks = <&ccu CLK_BUS_DEINTERLACE>,
> > + <&ccu CLK_DEINTERLACE>,
> > + <&ccu CLK_DRAM_DEINTERLACE>;
> > + clock-names = "bus", "mod", "ram";
> > + resets = <&ccu RST_BUS_DEINTERLACE>;
> > + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
> > + interconnects = <&mbus 9>;
> > + interconnect-names = "dma-mem";
> > + };
> > +
> > hdmi: hdmi at 1ee0000 {
> > compatible = "allwinner,sun50i-a64-dw-hdmi",
> > "allwinner,sun8i-a83t-dw-hdmi";
> > @@ -842,7 +1152,7 @@
> > resets = <&ccu RST_BUS_HDMI1>;
> > reset-names = "ctrl";
> > phys = <&hdmi_phy>;
> > - phy-names = "hdmi-phy";
> > + phy-names = "phy";
> > status = "disabled";
> >
> > ports {
> > @@ -867,7 +1177,7 @@
> > compatible = "allwinner,sun50i-a64-hdmi-phy";
> > reg = <0x01ef0000 0x10000>;
> > clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
> > - <&ccu 7>;
> > + <&ccu CLK_PLL_VIDEO0>;
> > clock-names = "bus", "mod", "pll-0";
> > resets = <&ccu RST_BUS_HDMI0>;
> > reset-names = "phy";
> > @@ -875,11 +1185,12 @@
> > };
> >
> > rtc: rtc at 1f00000 {
> > - compatible = "allwinner,sun6i-a31-rtc";
> > - reg = <0x01f00000 0x54>;
> > + compatible = "allwinner,sun50i-a64-rtc",
> > + "allwinner,sun8i-h3-rtc";
> > + reg = <0x01f00000 0x400>;
> > interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> > <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> > - clock-output-names = "rtc-osc32k", "rtc-osc32k-out";
> > + clock-output-names = "osc32k", "osc32k-out", "iosc";
> > clocks = <&osc32k>;
> > #clock-cells = <1>;
> > };
> > @@ -896,13 +1207,19 @@
> > r_ccu: clock at 1f01400 {
> > compatible = "allwinner,sun50i-a64-r-ccu";
> > reg = <0x01f01400 0x100>;
> > - clocks = <&osc24M>, <&osc32k>, <&iosc>,
> > - <&ccu 11>;
> > + clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
> > + <&ccu CLK_PLL_PERIPH0>;
> > clock-names = "hosc", "losc", "iosc", "pll-periph";
> > #clock-cells = <1>;
> > #reset-cells = <1>;
> > };
> >
> > + codec_analog: codec-analog at 1f015c0 {
> > + compatible = "allwinner,sun50i-a64-codec-analog";
> > + reg = <0x01f015c0 0x4>;
> > + status = "disabled";
> > + };
> > +
> > r_i2c: i2c at 1f02400 {
> > compatible = "allwinner,sun50i-a64-i2c",
> > "allwinner,sun6i-a31-i2c";
> > @@ -915,6 +1232,19 @@
> > #size-cells = <0>;
> > };
> >
> > + r_ir: ir at 1f02000 {
> > + compatible = "allwinner,sun50i-a64-ir",
> > + "allwinner,sun6i-a31-ir";
> > + reg = <0x01f02000 0x400>;
> > + clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
> > + clock-names = "apb", "ir";
> > + resets = <&r_ccu RST_APB0_IR>;
> > + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&r_ir_rx_pin>;
> > + status = "disabled";
> > + };
> > +
> > r_pwm: pwm at 1f03800 {
> > compatible = "allwinner,sun50i-a64-pwm",
> > "allwinner,sun5i-a13-pwm";
> > @@ -942,12 +1272,17 @@
> > function = "s_i2c";
> > };
> >
> > - r_pwm_pin: pwm {
> > + r_ir_rx_pin: r-ir-rx-pin {
> > + pins = "PL11";
> > + function = "s_cir_rx";
> > + };
> > +
> > + r_pwm_pin: r-pwm-pin {
> > pins = "PL10";
> > function = "s_pwm";
> > };
> >
> > - r_rsb_pins: rsb {
> > + r_rsb_pins: r-rsb-pins {
> > pins = "PL0", "PL1";
> > function = "s_rsb";
> > };
> > @@ -972,6 +1307,7 @@
> > "allwinner,sun6i-a31-wdt";
> > reg = <0x01c20ca0 0x20>;
> > interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&osc24M>;
> > };
> > };
> > };
> >
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 6/8] arm: dts: Sync the sun50i-a64.dtsi from Linux 5.8-rc1
2020-07-26 10:17 ` Peter Robinson
@ 2020-07-27 13:16 ` Heinrich Schuchardt
2020-07-29 0:30 ` André Przywara
0 siblings, 1 reply; 17+ messages in thread
From: Heinrich Schuchardt @ 2020-07-27 13:16 UTC (permalink / raw)
To: u-boot
On 26.07.20 12:17, Peter Robinson wrote:
> On Thu, Jul 23, 2020 at 12:15 AM Andr? Przywara <andre.przywara@arm.com> wrote:
>>
>> On 22/07/2020 15:18, Peter Robinson wrote:
>>> Sync the Allwinner A64 sun50i-a64.dtsi from Linux.
>>
>> Hi Peter,
>>
>> thanks for your series!
>>
>> While this looks mostly straight-forward, the problem is that this patch
>> here affects all Allwinner boards. And for them it breaks older kernels,
>> which cannot cope with some of the changed bindings or nodes.
>> Your patches up until here are fine, since they only add nodes and
>> properties, but this update changes nodes, some in a non-compatible way.
>>
>> Examples are dropping the "syscon" compatible (which requires 4.18 to
>> know about the new compatible string) and the dropping of
>> internal-osc-clk and the connected RTC change. This breaks any kernels
>> that don't know about the third RTC clock (<&rtc 2>) or the new
>> compatible string (introduced in 4.20). Similar effects show up in other
>> OSes.
>
> The 4.18 kernel is over 2 years old. How many users are going to
> actively upgrade U-Boot to the latest and not the kernel all while
> using the U-Boot provided DT and not just loading the matching kernel
> DT supplied by what ever ancient kernel they happen to choose to use?
> I feel this use case is quite a corner case and in those cases they're
> probably not using a vanilla upstream U-Boot anyway.
Sure people using an old Linux distribution not providing an U-Boot
image may do so.
But here we are talking about the U-Boot device tree. As Linux device
trees are release specific you should not try to boot Linux using a
devicetree not provided by the exact same Linux version.
So incompatiblities between old Linux releases and U-Boot's device tree
should be irrelevant.
Best regards
Heinrich
>
>> I was experimenting with some small changes (compared to mainline) to
>> overcome those issues, mostly by *adding* compatible strings instead of
>> *replacing* them.
>
> Shouldn't they be added to a -u-boot.dtsi?
>
>> So I would like to ask for a few days so that I can do more testing with
>> various kernels. I would then post those changes, so that we can discuss
>> them.
>>
>> Cheers,
>> Andre
>>
>>>
>>> Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
>>> ---
>>> arch/arm/dts/sun50i-a64.dtsi | 532 ++++++++++++++++++++++++++++-------
>>> 1 file changed, 434 insertions(+), 98 deletions(-)
>>>
>>> diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
>>> index ff41abc96a..8dfbcd1440 100644
>>> --- a/arch/arm/dts/sun50i-a64.dtsi
>>> +++ b/arch/arm/dts/sun50i-a64.dtsi
>>> @@ -1,46 +1,7 @@
>>> -/*
>>> - * Copyright (C) 2016 ARM Ltd.
>>> - * based on the Allwinner H3 dtsi:
>>> - * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
>>> - *
>>> - * This file is dual-licensed: you can use it either under the terms
>>> - * of the GPL or the X11 license, at your option. Note that this dual
>>> - * licensing only applies to this file, and not this project as a
>>> - * whole.
>>> - *
>>> - * a) This file is free software; you can redistribute it and/or
>>> - * modify it under the terms of the GNU General Public License as
>>> - * published by the Free Software Foundation; either version 2 of the
>>> - * License, or (at your option) any later version.
>>> - *
>>> - * This file is distributed in the hope that it will be useful,
>>> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>>> - * GNU General Public License for more details.
>>> - *
>>> - * Or, alternatively,
>>> - *
>>> - * b) Permission is hereby granted, free of charge, to any person
>>> - * obtaining a copy of this software and associated documentation
>>> - * files (the "Software"), to deal in the Software without
>>> - * restriction, including without limitation the rights to use,
>>> - * copy, modify, merge, publish, distribute, sublicense, and/or
>>> - * sell copies of the Software, and to permit persons to whom the
>>> - * Software is furnished to do so, subject to the following
>>> - * conditions:
>>> - *
>>> - * The above copyright notice and this permission notice shall be
>>> - * included in all copies or substantial portions of the Software.
>>> - *
>>> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>> - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>>> - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>>> - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>>> - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>>> - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>> - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>>> - * OTHER DEALINGS IN THE SOFTWARE.
>>> - */
>>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>>> +// Copyright (C) 2016 ARM Ltd.
>>> +// based on the Allwinner H3 dtsi:
>>> +// Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
>>>
>>> #include <dt-bindings/clock/sun50i-a64-ccu.h>
>>> #include <dt-bindings/clock/sun8i-de2.h>
>>> @@ -49,6 +10,7 @@
>>> #include <dt-bindings/reset/sun50i-a64-ccu.h>
>>> #include <dt-bindings/reset/sun8i-de2.h>
>>> #include <dt-bindings/reset/sun8i-r-ccu.h>
>>> +#include <dt-bindings/thermal/thermal.h>
>>>
>>> / {
>>> interrupt-parent = <&gic>;
>>> @@ -84,35 +46,47 @@
>>> #size-cells = <0>;
>>>
>>> cpu0: cpu at 0 {
>>> - compatible = "arm,cortex-a53", "arm,armv8";
>>> + compatible = "arm,cortex-a53";
>>> device_type = "cpu";
>>> reg = <0>;
>>> enable-method = "psci";
>>> next-level-cache = <&L2>;
>>> + clocks = <&ccu 21>;
>>> + clock-names = "cpu";
>>> + #cooling-cells = <2>;
>>> };
>>>
>>> cpu1: cpu at 1 {
>>> - compatible = "arm,cortex-a53", "arm,armv8";
>>> + compatible = "arm,cortex-a53";
>>> device_type = "cpu";
>>> reg = <1>;
>>> enable-method = "psci";
>>> next-level-cache = <&L2>;
>>> + clocks = <&ccu 21>;
>>> + clock-names = "cpu";
>>> + #cooling-cells = <2>;
>>> };
>>>
>>> cpu2: cpu at 2 {
>>> - compatible = "arm,cortex-a53", "arm,armv8";
>>> + compatible = "arm,cortex-a53";
>>> device_type = "cpu";
>>> reg = <2>;
>>> enable-method = "psci";
>>> next-level-cache = <&L2>;
>>> + clocks = <&ccu 21>;
>>> + clock-names = "cpu";
>>> + #cooling-cells = <2>;
>>> };
>>>
>>> cpu3: cpu at 3 {
>>> - compatible = "arm,cortex-a53", "arm,armv8";
>>> + compatible = "arm,cortex-a53";
>>> device_type = "cpu";
>>> reg = <3>;
>>> enable-method = "psci";
>>> next-level-cache = <&L2>;
>>> + clocks = <&ccu 21>;
>>> + clock-names = "cpu";
>>> + #cooling-cells = <2>;
>>> };
>>>
>>> L2: l2-cache {
>>> @@ -139,15 +113,16 @@
>>> #clock-cells = <0>;
>>> compatible = "fixed-clock";
>>> clock-frequency = <32768>;
>>> - clock-output-names = "osc32k";
>>> + clock-output-names = "ext-osc32k";
>>> };
>>>
>>> - iosc: internal-osc-clk {
>>> - #clock-cells = <0>;
>>> - compatible = "fixed-clock";
>>> - clock-frequency = <16000000>;
>>> - clock-accuracy = <300000000>;
>>> - clock-output-names = "iosc";
>>> + pmu {
>>> + compatible = "arm,cortex-a53-pmu";
>>> + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
>>> + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
>>> };
>>>
>>> psci {
>>> @@ -155,26 +130,33 @@
>>> method = "smc";
>>> };
>>>
>>> - sound_spdif {
>>> + sound: sound {
>>> compatible = "simple-audio-card";
>>> - simple-audio-card,name = "On-board SPDIF";
>>> + simple-audio-card,name = "sun50i-a64-audio";
>>> + simple-audio-card,format = "i2s";
>>> + simple-audio-card,frame-master = <&cpudai>;
>>> + simple-audio-card,bitclock-master = <&cpudai>;
>>> + simple-audio-card,mclk-fs = <128>;
>>> + simple-audio-card,aux-devs = <&codec_analog>;
>>> + simple-audio-card,routing =
>>> + "Left DAC", "AIF1 Slot 0 Left",
>>> + "Right DAC", "AIF1 Slot 0 Right",
>>> + "AIF1 Slot 0 Left ADC", "Left ADC",
>>> + "AIF1 Slot 0 Right ADC", "Right ADC";
>>> + status = "disabled";
>>>
>>> - simple-audio-card,cpu {
>>> - sound-dai = <&spdif>;
>>> + cpudai: simple-audio-card,cpu {
>>> + sound-dai = <&dai>;
>>> };
>>>
>>> - simple-audio-card,codec {
>>> - sound-dai = <&spdif_out>;
>>> + link_codec: simple-audio-card,codec {
>>> + sound-dai = <&codec>;
>>> };
>>> };
>>>
>>> - spdif_out: spdif-out {
>>> - #sound-dai-cells = <0>;
>>> - compatible = "linux,spdif-dit";
>>> - };
>>> -
>>> timer {
>>> compatible = "arm,armv8-timer";
>>> + allwinner,erratum-unknown1;
>>> interrupts = <GIC_PPI 13
>>> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>>> <GIC_PPI 14
>>> @@ -185,13 +167,76 @@
>>> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>>> };
>>>
>>> + thermal-zones {
>>> + cpu_thermal: cpu0-thermal {
>>> + /* milliseconds */
>>> + polling-delay-passive = <0>;
>>> + polling-delay = <0>;
>>> + thermal-sensors = <&ths 0>;
>>> +
>>> + cooling-maps {
>>> + map0 {
>>> + trip = <&cpu_alert0>;
>>> + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>>> + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>>> + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>>> + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>>> + };
>>> + map1 {
>>> + trip = <&cpu_alert1>;
>>> + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>>> + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>>> + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>>> + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>>> + };
>>> + };
>>> +
>>> + trips {
>>> + cpu_alert0: cpu_alert0 {
>>> + /* milliCelsius */
>>> + temperature = <75000>;
>>> + hysteresis = <2000>;
>>> + type = "passive";
>>> + };
>>> +
>>> + cpu_alert1: cpu_alert1 {
>>> + /* milliCelsius */
>>> + temperature = <90000>;
>>> + hysteresis = <2000>;
>>> + type = "hot";
>>> + };
>>> +
>>> + cpu_crit: cpu_crit {
>>> + /* milliCelsius */
>>> + temperature = <110000>;
>>> + hysteresis = <2000>;
>>> + type = "critical";
>>> + };
>>> + };
>>> + };
>>> +
>>> + gpu0_thermal: gpu0-thermal {
>>> + /* milliseconds */
>>> + polling-delay-passive = <0>;
>>> + polling-delay = <0>;
>>> + thermal-sensors = <&ths 1>;
>>> + };
>>> +
>>> + gpu1_thermal: gpu1-thermal {
>>> + /* milliseconds */
>>> + polling-delay-passive = <0>;
>>> + polling-delay = <0>;
>>> + thermal-sensors = <&ths 2>;
>>> + };
>>> + };
>>> +
>>> soc {
>>> compatible = "simple-bus";
>>> #address-cells = <1>;
>>> #size-cells = <1>;
>>> ranges;
>>>
>>> - de2 at 1000000 {
>>> + bus at 1000000 {
>>> compatible = "allwinner,sun50i-a64-de2";
>>> reg = <0x1000000 0x400000>;
>>> allwinner,sram = <&de2_sram 1>;
>>> @@ -201,16 +246,28 @@
>>>
>>> display_clocks: clock at 0 {
>>> compatible = "allwinner,sun50i-a64-de2-clk";
>>> - reg = <0x0 0x100000>;
>>> - clocks = <&ccu CLK_DE>,
>>> - <&ccu CLK_BUS_DE>;
>>> - clock-names = "mod",
>>> - "bus";
>>> + reg = <0x0 0x10000>;
>>> + clocks = <&ccu CLK_BUS_DE>,
>>> + <&ccu CLK_DE>;
>>> + clock-names = "bus",
>>> + "mod";
>>> resets = <&ccu RST_BUS_DE>;
>>> #clock-cells = <1>;
>>> #reset-cells = <1>;
>>> };
>>>
>>> + rotate: rotate at 20000 {
>>> + compatible = "allwinner,sun50i-a64-de2-rotate",
>>> + "allwinner,sun8i-a83t-de2-rotate";
>>> + reg = <0x20000 0x10000>;
>>> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&display_clocks CLK_BUS_ROT>,
>>> + <&display_clocks CLK_ROT>;
>>> + clock-names = "bus",
>>> + "mod";
>>> + resets = <&display_clocks RST_ROT>;
>>> + };
>>> +
>>> mixer0: mixer at 100000 {
>>> compatible = "allwinner,sun50i-a64-de2-mixer-0";
>>> reg = <0x100000 0x100000>;
>>> @@ -225,11 +282,19 @@
>>> #size-cells = <0>;
>>>
>>> mixer0_out: port at 1 {
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> reg = <1>;
>>>
>>> - mixer0_out_tcon0: endpoint {
>>> + mixer0_out_tcon0: endpoint at 0 {
>>> + reg = <0>;
>>> remote-endpoint = <&tcon0_in_mixer0>;
>>> };
>>> +
>>> + mixer0_out_tcon1: endpoint at 1 {
>>> + reg = <1>;
>>> + remote-endpoint = <&tcon1_in_mixer0>;
>>> + };
>>> };
>>> };
>>> };
>>> @@ -248,9 +313,17 @@
>>> #size-cells = <0>;
>>>
>>> mixer1_out: port at 1 {
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> reg = <1>;
>>>
>>> - mixer1_out_tcon1: endpoint {
>>> + mixer1_out_tcon0: endpoint at 0 {
>>> + reg = <0>;
>>> + remote-endpoint = <&tcon0_in_mixer1>;
>>> + };
>>> +
>>> + mixer1_out_tcon1: endpoint at 1 {
>>> + reg = <1>;
>>> remote-endpoint = <&tcon1_in_mixer1>;
>>> };
>>> };
>>> @@ -259,8 +332,7 @@
>>> };
>>>
>>> syscon: syscon at 1c00000 {
>>> - compatible = "allwinner,sun50i-a64-system-control",
>>> - "syscon";
>>> + compatible = "allwinner,sun50i-a64-system-control";
>>> reg = <0x01c00000 0x1000>;
>>> #address-cells = <1>;
>>> #size-cells = <1>;
>>> @@ -278,6 +350,20 @@
>>> reg = <0x0000 0x28000>;
>>> };
>>> };
>>> +
>>> + sram_c1: sram at 1d00000 {
>>> + compatible = "mmio-sram";
>>> + reg = <0x01d00000 0x40000>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges = <0 0x01d00000 0x40000>;
>>> +
>>> + ve_sram: sram-section at 0 {
>>> + compatible = "allwinner,sun50i-a64-sram-c1",
>>> + "allwinner,sun4i-a10-sram-c1";
>>> + reg = <0x000000 0x40000>;
>>> + };
>>> + };
>>> };
>>>
>>> dma: dma-controller at 1c02000 {
>>> @@ -299,6 +385,7 @@
>>> clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
>>> clock-names = "ahb", "tcon-ch0";
>>> clock-output-names = "tcon-pixel-clock";
>>> + #clock-cells = <0>;
>>> resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
>>> reset-names = "lcd", "lvds";
>>>
>>> @@ -315,12 +402,23 @@
>>> reg = <0>;
>>> remote-endpoint = <&mixer0_out_tcon0>;
>>> };
>>> +
>>> + tcon0_in_mixer1: endpoint at 1 {
>>> + reg = <1>;
>>> + remote-endpoint = <&mixer1_out_tcon0>;
>>> + };
>>> };
>>>
>>> tcon0_out: port at 1 {
>>> #address-cells = <1>;
>>> #size-cells = <0>;
>>> reg = <1>;
>>> +
>>> + tcon0_out_dsi: endpoint at 1 {
>>> + reg = <1>;
>>> + remote-endpoint = <&dsi_in_tcon0>;
>>> + allwinner,tcon-channel = <1>;
>>> + };
>>> };
>>> };
>>> };
>>> @@ -340,9 +438,17 @@
>>> #size-cells = <0>;
>>>
>>> tcon1_in: port at 0 {
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> reg = <0>;
>>>
>>> - tcon1_in_mixer1: endpoint {
>>> + tcon1_in_mixer0: endpoint at 0 {
>>> + reg = <0>;
>>> + remote-endpoint = <&mixer0_out_tcon1>;
>>> + };
>>> +
>>> + tcon1_in_mixer1: endpoint at 1 {
>>> + reg = <1>;
>>> remote-endpoint = <&mixer1_out_tcon1>;
>>> };
>>> };
>>> @@ -360,6 +466,17 @@
>>> };
>>> };
>>>
>>> + video-codec at 1c0e000 {
>>> + compatible = "allwinner,sun50i-a64-video-engine";
>>> + reg = <0x01c0e000 0x1000>;
>>> + clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
>>> + <&ccu CLK_DRAM_VE>;
>>> + clock-names = "ahb", "mod", "ram";
>>> + resets = <&ccu RST_BUS_VE>;
>>> + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
>>> + allwinner,sram = <&ve_sram 1>;
>>> + };
>>> +
>>> mmc0: mmc at 1c0f000 {
>>> compatible = "allwinner,sun50i-a64-mmc";
>>> reg = <0x01c0f000 0x1000>;
>>> @@ -405,6 +522,31 @@
>>> sid: eeprom at 1c14000 {
>>> compatible = "allwinner,sun50i-a64-sid";
>>> reg = <0x1c14000 0x400>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> +
>>> + ths_calibration: thermal-sensor-calibration at 34 {
>>> + reg = <0x34 0x8>;
>>> + };
>>> + };
>>> +
>>> + crypto: crypto at 1c15000 {
>>> + compatible = "allwinner,sun50i-a64-crypto";
>>> + reg = <0x01c15000 0x1000>;
>>> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
>>> + clock-names = "bus", "mod";
>>> + resets = <&ccu RST_BUS_CE>;
>>> + };
>>> +
>>> + msgbox: mailbox at 1c17000 {
>>> + compatible = "allwinner,sun50i-a64-msgbox",
>>> + "allwinner,sun6i-a31-msgbox";
>>> + reg = <0x01c17000 0x1000>;
>>> + clocks = <&ccu CLK_BUS_MSGBOX>;
>>> + resets = <&ccu RST_BUS_MSGBOX>;
>>> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
>>> + #mbox-cells = <1>;
>>> };
>>>
>>> usb_otg: usb at 1c19000 {
>>> @@ -417,6 +559,7 @@
>>> phys = <&usbphy 0>;
>>> phy-names = "usb";
>>> extcon = <&usbphy 0>;
>>> + dr_mode = "otg";
>>> status = "disabled";
>>> };
>>>
>>> @@ -491,7 +634,7 @@
>>> ccu: clock at 1c20000 {
>>> compatible = "allwinner,sun50i-a64-ccu";
>>> reg = <0x01c20000 0x400>;
>>> - clocks = <&osc24M>, <&osc32k>;
>>> + clocks = <&osc24M>, <&rtc 0>;
>>> clock-names = "hosc", "losc";
>>> #clock-cells = <1>;
>>> #reset-cells = <1>;
>>> @@ -503,22 +646,50 @@
>>> interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
>>> <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
>>> <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
>>> - clocks = <&ccu 58>;
>>> + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
>>> + clock-names = "apb", "hosc", "losc";
>>> gpio-controller;
>>> #gpio-cells = <3>;
>>> interrupt-controller;
>>> #interrupt-cells = <3>;
>>>
>>> - i2c0_pins: i2c0_pins {
>>> + csi_pins: csi-pins {
>>> + pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
>>> + "PE7", "PE8", "PE9", "PE10", "PE11";
>>> + function = "csi";
>>> + };
>>> +
>>> + /omit-if-no-ref/
>>> + csi_mclk_pin: csi-mclk-pin {
>>> + pins = "PE1";
>>> + function = "csi";
>>> + };
>>> +
>>> + i2c0_pins: i2c0-pins {
>>> pins = "PH0", "PH1";
>>> function = "i2c0";
>>> };
>>>
>>> - i2c1_pins: i2c1_pins {
>>> + i2c1_pins: i2c1-pins {
>>> pins = "PH2", "PH3";
>>> function = "i2c1";
>>> };
>>>
>>> + i2c2_pins: i2c2-pins {
>>> + pins = "PE14", "PE15";
>>> + function = "i2c2";
>>> + };
>>> +
>>> + /omit-if-no-ref/
>>> + lcd_rgb666_pins: lcd-rgb666-pins {
>>> + pins = "PD0", "PD1", "PD2", "PD3", "PD4",
>>> + "PD5", "PD6", "PD7", "PD8", "PD9",
>>> + "PD10", "PD11", "PD12", "PD13",
>>> + "PD14", "PD15", "PD16", "PD17",
>>> + "PD18", "PD19", "PD20", "PD21";
>>> + function = "lcd0";
>>> + };
>>> +
>>> mmc0_pins: mmc0-pins {
>>> pins = "PF0", "PF1", "PF2", "PF3",
>>> "PF4", "PF5";
>>> @@ -551,19 +722,19 @@
>>> bias-pull-up;
>>> };
>>>
>>> - pwm_pin: pwm_pin {
>>> + pwm_pin: pwm-pin {
>>> pins = "PD22";
>>> function = "pwm";
>>> };
>>>
>>> - rmii_pins: rmii_pins {
>>> + rmii_pins: rmii-pins {
>>> pins = "PD10", "PD11", "PD13", "PD14", "PD17",
>>> "PD18", "PD19", "PD20", "PD22", "PD23";
>>> function = "emac";
>>> drive-strength = <40>;
>>> };
>>>
>>> - rgmii_pins: rgmii_pins {
>>> + rgmii_pins: rgmii-pins {
>>> pins = "PD8", "PD9", "PD10", "PD11", "PD12",
>>> "PD13", "PD15", "PD16", "PD17", "PD18",
>>> "PD19", "PD20", "PD21", "PD22", "PD23";
>>> @@ -571,17 +742,17 @@
>>> drive-strength = <40>;
>>> };
>>>
>>> - spdif_tx_pin: spdif {
>>> + spdif_tx_pin: spdif-tx-pin {
>>> pins = "PH8";
>>> function = "spdif";
>>> };
>>>
>>> - spi0_pins: spi0 {
>>> + spi0_pins: spi0-pins {
>>> pins = "PC0", "PC1", "PC2", "PC3";
>>> function = "spi0";
>>> };
>>>
>>> - spi1_pins: spi1 {
>>> + spi1_pins: spi1-pins {
>>> pins = "PD0", "PD1", "PD2", "PD3";
>>> function = "spi1";
>>> };
>>> @@ -591,12 +762,12 @@
>>> function = "uart0";
>>> };
>>>
>>> - uart1_pins: uart1_pins {
>>> + uart1_pins: uart1-pins {
>>> pins = "PG6", "PG7";
>>> function = "uart1";
>>> };
>>>
>>> - uart1_rts_cts_pins: uart1_rts_cts_pins {
>>> + uart1_rts_cts_pins: uart1-rts-cts-pins {
>>> pins = "PG8", "PG9";
>>> function = "uart1";
>>> };
>>> @@ -638,6 +809,14 @@
>>> status = "disabled";
>>> };
>>>
>>> + lradc: lradc at 1c21800 {
>>> + compatible = "allwinner,sun50i-a64-lradc",
>>> + "allwinner,sun8i-a83t-r-lradc";
>>> + reg = <0x01c21800 0x400>;
>>> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
>>> + status = "disabled";
>>> + };
>>> +
>>> i2s0: i2s at 1c22000 {
>>> #sound-dai-cells = <0>;
>>> compatible = "allwinner,sun50i-a64-i2s",
>>> @@ -666,6 +845,41 @@
>>> status = "disabled";
>>> };
>>>
>>> + dai: dai at 1c22c00 {
>>> + #sound-dai-cells = <0>;
>>> + compatible = "allwinner,sun50i-a64-codec-i2s";
>>> + reg = <0x01c22c00 0x200>;
>>> + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
>>> + clock-names = "apb", "mod";
>>> + resets = <&ccu RST_BUS_CODEC>;
>>> + dmas = <&dma 15>, <&dma 15>;
>>> + dma-names = "rx", "tx";
>>> + status = "disabled";
>>> + };
>>> +
>>> + codec: codec at 1c22e00 {
>>> + #sound-dai-cells = <0>;
>>> + compatible = "allwinner,sun8i-a33-codec";
>>> + reg = <0x01c22e00 0x600>;
>>> + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
>>> + clock-names = "bus", "mod";
>>> + status = "disabled";
>>> + };
>>> +
>>> + ths: thermal-sensor at 1c25000 {
>>> + compatible = "allwinner,sun50i-a64-ths";
>>> + reg = <0x01c25000 0x100>;
>>> + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
>>> + clock-names = "bus", "mod";
>>> + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
>>> + resets = <&ccu RST_BUS_THS>;
>>> + nvmem-cells = <&ths_calibration>;
>>> + nvmem-cell-names = "calibration";
>>> + #thermal-sensor-cells = <1>;
>>> + };
>>> +
>>> uart0: serial at 1c28000 {
>>> compatible = "snps,dw-apb-uart";
>>> reg = <0x01c28000 0x400>;
>>> @@ -727,6 +941,8 @@
>>> interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
>>> clocks = <&ccu CLK_BUS_I2C0>;
>>> resets = <&ccu RST_BUS_I2C0>;
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&i2c0_pins>;
>>> status = "disabled";
>>> #address-cells = <1>;
>>> #size-cells = <0>;
>>> @@ -738,6 +954,8 @@
>>> interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
>>> clocks = <&ccu CLK_BUS_I2C1>;
>>> resets = <&ccu RST_BUS_I2C1>;
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&i2c1_pins>;
>>> status = "disabled";
>>> #address-cells = <1>;
>>> #size-cells = <0>;
>>> @@ -749,12 +967,13 @@
>>> interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
>>> clocks = <&ccu CLK_BUS_I2C2>;
>>> resets = <&ccu RST_BUS_I2C2>;
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&i2c2_pins>;
>>> status = "disabled";
>>> #address-cells = <1>;
>>> #size-cells = <0>;
>>> };
>>>
>>> -
>>> spi0: spi at 1c68000 {
>>> compatible = "allwinner,sun8i-h3-spi";
>>> reg = <0x01c68000 0x1000>;
>>> @@ -808,6 +1027,28 @@
>>> };
>>> };
>>>
>>> + mali: gpu at 1c40000 {
>>> + compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
>>> + reg = <0x01c40000 0x10000>;
>>> + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
>>> + interrupt-names = "gp",
>>> + "gpmmu",
>>> + "pp0",
>>> + "ppmmu0",
>>> + "pp1",
>>> + "ppmmu1",
>>> + "pmu";
>>> + clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
>>> + clock-names = "bus", "core";
>>> + resets = <&ccu RST_BUS_GPU>;
>>> + };
>>> +
>>> gic: interrupt-controller at 1c81000 {
>>> compatible = "arm,gic-400";
>>> reg = <0x01c81000 0x1000>,
>>> @@ -830,6 +1071,75 @@
>>> status = "disabled";
>>> };
>>>
>>> + mbus: dram-controller at 1c62000 {
>>> + compatible = "allwinner,sun50i-a64-mbus";
>>> + reg = <0x01c62000 0x1000>;
>>> + clocks = <&ccu 112>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + dma-ranges = <0x00000000 0x40000000 0xc0000000>;
>>> + #interconnect-cells = <1>;
>>> + };
>>> +
>>> + csi: csi at 1cb0000 {
>>> + compatible = "allwinner,sun50i-a64-csi";
>>> + reg = <0x01cb0000 0x1000>;
>>> + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&ccu CLK_BUS_CSI>,
>>> + <&ccu CLK_CSI_SCLK>,
>>> + <&ccu CLK_DRAM_CSI>;
>>> + clock-names = "bus", "mod", "ram";
>>> + resets = <&ccu RST_BUS_CSI>;
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&csi_pins>;
>>> + status = "disabled";
>>> + };
>>> +
>>> + dsi: dsi at 1ca0000 {
>>> + compatible = "allwinner,sun50i-a64-mipi-dsi";
>>> + reg = <0x01ca0000 0x1000>;
>>> + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&ccu CLK_BUS_MIPI_DSI>;
>>> + resets = <&ccu RST_BUS_MIPI_DSI>;
>>> + phys = <&dphy>;
>>> + phy-names = "dphy";
>>> + status = "disabled";
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> +
>>> + port {
>>> + dsi_in_tcon0: endpoint {
>>> + remote-endpoint = <&tcon0_out_dsi>;
>>> + };
>>> + };
>>> + };
>>> +
>>> + dphy: d-phy at 1ca1000 {
>>> + compatible = "allwinner,sun50i-a64-mipi-dphy",
>>> + "allwinner,sun6i-a31-mipi-dphy";
>>> + reg = <0x01ca1000 0x1000>;
>>> + clocks = <&ccu CLK_BUS_MIPI_DSI>,
>>> + <&ccu CLK_DSI_DPHY>;
>>> + clock-names = "bus", "mod";
>>> + resets = <&ccu RST_BUS_MIPI_DSI>;
>>> + status = "disabled";
>>> + #phy-cells = <0>;
>>> + };
>>> +
>>> + deinterlace: deinterlace at 1e00000 {
>>> + compatible = "allwinner,sun50i-a64-deinterlace",
>>> + "allwinner,sun8i-h3-deinterlace";
>>> + reg = <0x01e00000 0x20000>;
>>> + clocks = <&ccu CLK_BUS_DEINTERLACE>,
>>> + <&ccu CLK_DEINTERLACE>,
>>> + <&ccu CLK_DRAM_DEINTERLACE>;
>>> + clock-names = "bus", "mod", "ram";
>>> + resets = <&ccu RST_BUS_DEINTERLACE>;
>>> + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
>>> + interconnects = <&mbus 9>;
>>> + interconnect-names = "dma-mem";
>>> + };
>>> +
>>> hdmi: hdmi at 1ee0000 {
>>> compatible = "allwinner,sun50i-a64-dw-hdmi",
>>> "allwinner,sun8i-a83t-dw-hdmi";
>>> @@ -842,7 +1152,7 @@
>>> resets = <&ccu RST_BUS_HDMI1>;
>>> reset-names = "ctrl";
>>> phys = <&hdmi_phy>;
>>> - phy-names = "hdmi-phy";
>>> + phy-names = "phy";
>>> status = "disabled";
>>>
>>> ports {
>>> @@ -867,7 +1177,7 @@
>>> compatible = "allwinner,sun50i-a64-hdmi-phy";
>>> reg = <0x01ef0000 0x10000>;
>>> clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
>>> - <&ccu 7>;
>>> + <&ccu CLK_PLL_VIDEO0>;
>>> clock-names = "bus", "mod", "pll-0";
>>> resets = <&ccu RST_BUS_HDMI0>;
>>> reset-names = "phy";
>>> @@ -875,11 +1185,12 @@
>>> };
>>>
>>> rtc: rtc at 1f00000 {
>>> - compatible = "allwinner,sun6i-a31-rtc";
>>> - reg = <0x01f00000 0x54>;
>>> + compatible = "allwinner,sun50i-a64-rtc",
>>> + "allwinner,sun8i-h3-rtc";
>>> + reg = <0x01f00000 0x400>;
>>> interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
>>> <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
>>> - clock-output-names = "rtc-osc32k", "rtc-osc32k-out";
>>> + clock-output-names = "osc32k", "osc32k-out", "iosc";
>>> clocks = <&osc32k>;
>>> #clock-cells = <1>;
>>> };
>>> @@ -896,13 +1207,19 @@
>>> r_ccu: clock at 1f01400 {
>>> compatible = "allwinner,sun50i-a64-r-ccu";
>>> reg = <0x01f01400 0x100>;
>>> - clocks = <&osc24M>, <&osc32k>, <&iosc>,
>>> - <&ccu 11>;
>>> + clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
>>> + <&ccu CLK_PLL_PERIPH0>;
>>> clock-names = "hosc", "losc", "iosc", "pll-periph";
>>> #clock-cells = <1>;
>>> #reset-cells = <1>;
>>> };
>>>
>>> + codec_analog: codec-analog at 1f015c0 {
>>> + compatible = "allwinner,sun50i-a64-codec-analog";
>>> + reg = <0x01f015c0 0x4>;
>>> + status = "disabled";
>>> + };
>>> +
>>> r_i2c: i2c at 1f02400 {
>>> compatible = "allwinner,sun50i-a64-i2c",
>>> "allwinner,sun6i-a31-i2c";
>>> @@ -915,6 +1232,19 @@
>>> #size-cells = <0>;
>>> };
>>>
>>> + r_ir: ir at 1f02000 {
>>> + compatible = "allwinner,sun50i-a64-ir",
>>> + "allwinner,sun6i-a31-ir";
>>> + reg = <0x01f02000 0x400>;
>>> + clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
>>> + clock-names = "apb", "ir";
>>> + resets = <&r_ccu RST_APB0_IR>;
>>> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&r_ir_rx_pin>;
>>> + status = "disabled";
>>> + };
>>> +
>>> r_pwm: pwm at 1f03800 {
>>> compatible = "allwinner,sun50i-a64-pwm",
>>> "allwinner,sun5i-a13-pwm";
>>> @@ -942,12 +1272,17 @@
>>> function = "s_i2c";
>>> };
>>>
>>> - r_pwm_pin: pwm {
>>> + r_ir_rx_pin: r-ir-rx-pin {
>>> + pins = "PL11";
>>> + function = "s_cir_rx";
>>> + };
>>> +
>>> + r_pwm_pin: r-pwm-pin {
>>> pins = "PL10";
>>> function = "s_pwm";
>>> };
>>>
>>> - r_rsb_pins: rsb {
>>> + r_rsb_pins: r-rsb-pins {
>>> pins = "PL0", "PL1";
>>> function = "s_rsb";
>>> };
>>> @@ -972,6 +1307,7 @@
>>> "allwinner,sun6i-a31-wdt";
>>> reg = <0x01c20ca0 0x20>;
>>> interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&osc24M>;
>>> };
>>> };
>>> };
>>>
>>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 8/8] Initial Pine64 Pinephone support
2020-07-22 14:18 ` [PATCH 8/8] Initial Pine64 Pinephone support Peter Robinson
@ 2020-07-27 13:30 ` Maxime Ripard
2020-07-27 13:49 ` Peter Robinson
0 siblings, 1 reply; 17+ messages in thread
From: Maxime Ripard @ 2020-07-27 13:30 UTC (permalink / raw)
To: u-boot
Hi,
On Wed, Jul 22, 2020 at 03:18:40PM +0100, Peter Robinson wrote:
> The Pine64 Pinephone is a smartphone based on the AllWinner A64 SoC.
> It has the following features:
> * 2GB LPDDR3 SDRAM
> * 5.95 inch 1440x720 HD IPS capacitive touchscreen
> * 16GB eMMC, mSD slot
> * Quectel EG25 LTE Modem
> * Realtek RTL8723CS WiFi/BT
> * Front and read cameras
> * Accelerometer, gyro, proximity, ambient light, compass sensors
> * A USB Type-C, USB Host, DisplayPort alt mode output, 15W 5V 3A Quick Charge, follows USB PD specification
>
> Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
> ---
> arch/arm/Kconfig | 2 +-
> configs/pinephone_defconfig | 38 +++++++++++++++++++++++++++++++++++++
> 2 files changed, 39 insertions(+), 1 deletion(-)
> create mode 100644 configs/pinephone_defconfig
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index e16fe03887..636ba26938 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1004,7 +1004,7 @@ config ARCH_SUNXI
> bool "Support sunxi (Allwinner) SoCs"
> select BINMAN
> select CMD_GPIO
> - select CMD_MMC if MMC
> +select CMD_MMC if MMC
That looks like a typo?
> select CMD_USB if DISTRO_DEFAULTS
> select CLK
> select DM
> diff --git a/configs/pinephone_defconfig b/configs/pinephone_defconfig
> new file mode 100644
> index 0000000000..d5750aa954
> --- /dev/null
> +++ b/configs/pinephone_defconfig
> @@ -0,0 +1,38 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_SUNXI=y
> +CONFIG_SPL=y
> +CONFIG_MACH_SUN50I=y
> +CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
> +CONFIG_DRAM_CLK=552
> +CONFIG_DRAM_ZQ=3881949
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> +CONFIG_R_I2C_ENABLE=y
> +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> +# CONFIG_SPL_SPI_SUNXI is not set
> +# CONFIG_SPL_DOS_PARTITION is not set
> +# CONFIG_SPL_EFI_PARTITION is not set
> +CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinephone-1.1"
> +CONFIG_OF_LIST="sun50i-a64-pinephone-1.1 sun50i-a64-pinephone-1.0"
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_DM_PWM=y
> +CONFIG_PWM_SUNXI=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_GPT=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +# CONFIG_CMD_MII is not set
> +# CONFIG_CMD_NFS is not set
> +# CONFIG_DM_ETH is not set
> +# CONFIG_PHY is not set
> +# CONFIG_PHY_GIGE is not set
> +# CONFIG_SUN8I_EMAC is not set
> +# CONFIG_PHY_REALTEK is not set
> +# CONFIG_CMD_SF is not set
> +# CONFIG_SPI is not set
> +# CONFIG_DM_SPI is not set
> +# CONFIG_SPI_FLASH is not set
> +# CONFIG_SPI_MEM is not set
> +# CONFIG_DM_SPI_FLASH is not set
I'm not entirely sure why we need to deviate from the default that much
here. Some options should definitely be disabled (like SUN8I_EMAC), but
I'm not really sure why it's enabled in the first place, and why we need
to disable the other network related options (PHY, PHY_GIGE,
PHY_REALTEK). They shouldn't even be enabled in the first place.
Similarly, CMD_GPIO, CMD_GPT should be enabled by default.
(and I'm not sure why PWM_SUNXI is here in the first place?)
Maxime
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 8/8] Initial Pine64 Pinephone support
2020-07-27 13:30 ` Maxime Ripard
@ 2020-07-27 13:49 ` Peter Robinson
2020-07-27 20:08 ` André Przywara
0 siblings, 1 reply; 17+ messages in thread
From: Peter Robinson @ 2020-07-27 13:49 UTC (permalink / raw)
To: u-boot
> On Wed, Jul 22, 2020 at 03:18:40PM +0100, Peter Robinson wrote:
> > The Pine64 Pinephone is a smartphone based on the AllWinner A64 SoC.
> > It has the following features:
> > * 2GB LPDDR3 SDRAM
> > * 5.95 inch 1440x720 HD IPS capacitive touchscreen
> > * 16GB eMMC, mSD slot
> > * Quectel EG25 LTE Modem
> > * Realtek RTL8723CS WiFi/BT
> > * Front and read cameras
> > * Accelerometer, gyro, proximity, ambient light, compass sensors
> > * A USB Type-C, USB Host, DisplayPort alt mode output, 15W 5V 3A Quick Charge, follows USB PD specification
> >
> > Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
> > ---
> > arch/arm/Kconfig | 2 +-
> > configs/pinephone_defconfig | 38 +++++++++++++++++++++++++++++++++++++
> > 2 files changed, 39 insertions(+), 1 deletion(-)
> > create mode 100644 configs/pinephone_defconfig
> >
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index e16fe03887..636ba26938 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -1004,7 +1004,7 @@ config ARCH_SUNXI
> > bool "Support sunxi (Allwinner) SoCs"
> > select BINMAN
> > select CMD_GPIO
> > - select CMD_MMC if MMC
> > +select CMD_MMC if MMC
>
> That looks like a typo?
Yes, it is.
> > select CMD_USB if DISTRO_DEFAULTS
> > select CLK
> > select DM
> > diff --git a/configs/pinephone_defconfig b/configs/pinephone_defconfig
> > new file mode 100644
> > index 0000000000..d5750aa954
> > --- /dev/null
> > +++ b/configs/pinephone_defconfig
> > @@ -0,0 +1,38 @@
> > +CONFIG_ARM=y
> > +CONFIG_ARCH_SUNXI=y
> > +CONFIG_SPL=y
> > +CONFIG_MACH_SUN50I=y
> > +CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
> > +CONFIG_DRAM_CLK=552
> > +CONFIG_DRAM_ZQ=3881949
> > +CONFIG_NR_DRAM_BANKS=1
> > +CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> > +CONFIG_R_I2C_ENABLE=y
> > +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> > +# CONFIG_SPL_SPI_SUNXI is not set
> > +# CONFIG_SPL_DOS_PARTITION is not set
> > +# CONFIG_SPL_EFI_PARTITION is not set
> > +CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinephone-1.1"
> > +CONFIG_OF_LIST="sun50i-a64-pinephone-1.1 sun50i-a64-pinephone-1.0"
> > +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> > +CONFIG_DM_REGULATOR=y
> > +CONFIG_DM_REGULATOR_FIXED=y
> > +CONFIG_DM_PWM=y
> > +CONFIG_PWM_SUNXI=y
> > +CONFIG_CMD_GPIO=y
> > +CONFIG_CMD_GPT=y
> > +CONFIG_CMD_I2C=y
> > +CONFIG_CMD_MMC=y
> > +# CONFIG_CMD_MII is not set
> > +# CONFIG_CMD_NFS is not set
> > +# CONFIG_DM_ETH is not set
> > +# CONFIG_PHY is not set
> > +# CONFIG_PHY_GIGE is not set
> > +# CONFIG_SUN8I_EMAC is not set
> > +# CONFIG_PHY_REALTEK is not set
> > +# CONFIG_CMD_SF is not set
> > +# CONFIG_SPI is not set
> > +# CONFIG_DM_SPI is not set
> > +# CONFIG_SPI_FLASH is not set
> > +# CONFIG_SPI_MEM is not set
> > +# CONFIG_DM_SPI_FLASH is not set
>
> I'm not entirely sure why we need to deviate from the default that much
> here. Some options should definitely be disabled (like SUN8I_EMAC), but
> I'm not really sure why it's enabled in the first place, and why we need
Because it's selected by default for the SoC, I suspect that's because
it was assumed that everything would be a dev board and have a wired
ethernet port but there's more and more devices that don't so it
probably makes sense to review that but I didn't want to do that as
part of enabling a device.
> to disable the other network related options (PHY, PHY_GIGE,
> PHY_REALTEK). They shouldn't even be enabled in the first place.
That would be my guess but I suspect it's the same as the SUN8I_EMAC above.
> Similarly, CMD_GPIO, CMD_GPT should be enabled by default.
>
> (and I'm not sure why PWM_SUNXI is here in the first place?)
It's used by the backlight, it shouldn't have made it into this patch,
as the DT bits aren't upstream yet and as I mentioned in my overview
the screen side of things is still a WiP, I must have missed it as I
sliced up my patch set between bits that worked with upstream and bits
that still need some work before they go upstream.
Peter
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 8/8] Initial Pine64 Pinephone support
2020-07-27 13:49 ` Peter Robinson
@ 2020-07-27 20:08 ` André Przywara
2020-07-27 20:43 ` Tom Rini
0 siblings, 1 reply; 17+ messages in thread
From: André Przywara @ 2020-07-27 20:08 UTC (permalink / raw)
To: u-boot
On 27/07/2020 14:49, Peter Robinson wrote:
Hi,
thanks for piecing this together. As Maxime mentioned, many options are
not necessary (see below).
Some options are now set by ARCH_SUNXI, since 48313fe51008.
>> On Wed, Jul 22, 2020 at 03:18:40PM +0100, Peter Robinson wrote:
>>> The Pine64 Pinephone is a smartphone based on the AllWinner A64 SoC.
>>> It has the following features:
>>> * 2GB LPDDR3 SDRAM
>>> * 5.95 inch 1440x720 HD IPS capacitive touchscreen
>>> * 16GB eMMC, mSD slot
>>> * Quectel EG25 LTE Modem
>>> * Realtek RTL8723CS WiFi/BT
>>> * Front and read cameras
>>> * Accelerometer, gyro, proximity, ambient light, compass sensors
>>> * A USB Type-C, USB Host, DisplayPort alt mode output, 15W 5V 3A Quick Charge, follows USB PD specification
>>>
>>> Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
>>> ---
>>> arch/arm/Kconfig | 2 +-
>>> configs/pinephone_defconfig | 38 +++++++++++++++++++++++++++++++++++++
>>> 2 files changed, 39 insertions(+), 1 deletion(-)
>>> create mode 100644 configs/pinephone_defconfig
>>>
>>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>>> index e16fe03887..636ba26938 100644
>>> --- a/arch/arm/Kconfig
>>> +++ b/arch/arm/Kconfig
>>> @@ -1004,7 +1004,7 @@ config ARCH_SUNXI
>>> bool "Support sunxi (Allwinner) SoCs"
>>> select BINMAN
>>> select CMD_GPIO
>>> - select CMD_MMC if MMC
>>> +select CMD_MMC if MMC
>>
>> That looks like a typo?
>
> Yes, it is.
>
>>> select CMD_USB if DISTRO_DEFAULTS
>>> select CLK
>>> select DM
>>> diff --git a/configs/pinephone_defconfig b/configs/pinephone_defconfig
>>> new file mode 100644
>>> index 0000000000..d5750aa954
>>> --- /dev/null
>>> +++ b/configs/pinephone_defconfig
>>> @@ -0,0 +1,38 @@
>>> +CONFIG_ARM=y
>>> +CONFIG_ARCH_SUNXI=y
>>> +CONFIG_SPL=y
>>> +CONFIG_MACH_SUN50I=y
>>> +CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
>>> +CONFIG_DRAM_CLK=552
>>> +CONFIG_DRAM_ZQ=3881949
>>> +CONFIG_NR_DRAM_BANKS=1
defaults to 1 now for ARCH_SUNXI
>>> +CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>>> +CONFIG_R_I2C_ENABLE=y
>>> +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>>> +# CONFIG_SPL_SPI_SUNXI is not set
defaults to n
>>> +# CONFIG_SPL_DOS_PARTITION is not set
>>> +# CONFIG_SPL_EFI_PARTITION is not set
those two default to "n" now for ARCH_SUNXI
>>> +CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinephone-1.1"
>>> +CONFIG_OF_LIST="sun50i-a64-pinephone-1.1 sun50i-a64-pinephone-1.0"
>>> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
defaults to y now for ARCH_SUNXI
>>> +CONFIG_DM_REGULATOR=y
>>> +CONFIG_DM_REGULATOR_FIXED=y
>>> +CONFIG_DM_PWM=y
>>> +CONFIG_PWM_SUNXI=y
>>> +CONFIG_CMD_GPIO=y
>>> +CONFIG_CMD_GPT=y
those two are already y be default
>>> +CONFIG_CMD_I2C=y
>>> +CONFIG_CMD_MMC=y
already y by default
>>> +# CONFIG_CMD_MII is not set
>>> +# CONFIG_CMD_NFS is not set
>>> +# CONFIG_DM_ETH is not set
>>> +# CONFIG_PHY is not set
>>> +# CONFIG_PHY_GIGE is not set
>>> +# CONFIG_SUN8I_EMAC is not set
>>> +# CONFIG_PHY_REALTEK is not set
>>> +# CONFIG_CMD_SF is not set
>>> +# CONFIG_SPI is not set
>>> +# CONFIG_DM_SPI is not set
Those two sounds like a good idea, but don't do anything, because
ARCH_SUNXI selects them. Sounds weird, and looks like not the right
thing, tbh.
>>> +# CONFIG_SPI_FLASH is not set
>>> +# CONFIG_SPI_MEM is not set
>>> +# CONFIG_DM_SPI_FLASH is not set
>>
>> I'm not entirely sure why we need to deviate from the default that much
>> here. Some options should definitely be disabled (like SUN8I_EMAC), but
>> I'm not really sure why it's enabled in the first place, and why we need
>
> Because it's selected by default for the SoC,
Mmmh, really? I don't see that in Kconfig, and in fact removing that
"#CONFIG_SUN8I_EMAC is not set" line results in the exact same .config
created.
> I suspect that's because
> it was assumed that everything would be a dev board and have a wired
> ethernet port but there's more and more devices that don't so it
> probably makes sense to review that but I didn't want to do that as
> part of enabling a device.
Explicitly un-setting just CONFIG_NET should disable all network related
options. This disables even more commands and features than your
version, which is fine, unless we want USB Ethernet support. Doesn't
seem to be enabled with your config, and I don't know what's the USB
story on the Pinephone in general, and in U-Boot in particular.
What are the expectations in this regard?
Cheers,
Andre
>> to disable the other network related options (PHY, PHY_GIGE,
>> PHY_REALTEK). They shouldn't even be enabled in the first place.
>
> That would be my guess but I suspect it's the same as the SUN8I_EMAC above.
>
>> Similarly, CMD_GPIO, CMD_GPT should be enabled by default.
>>
>> (and I'm not sure why PWM_SUNXI is here in the first place?)
>
> It's used by the backlight, it shouldn't have made it into this patch,
> as the DT bits aren't upstream yet and as I mentioned in my overview
> the screen side of things is still a WiP, I must have missed it as I
> sliced up my patch set between bits that worked with upstream and bits
> that still need some work before they go upstream.
>
> Peter
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 8/8] Initial Pine64 Pinephone support
2020-07-27 20:08 ` André Przywara
@ 2020-07-27 20:43 ` Tom Rini
0 siblings, 0 replies; 17+ messages in thread
From: Tom Rini @ 2020-07-27 20:43 UTC (permalink / raw)
To: u-boot
On Mon, Jul 27, 2020 at 09:08:40PM +0100, Andr? Przywara wrote:
> On 27/07/2020 14:49, Peter Robinson wrote:
>
> Hi,
>
> thanks for piecing this together. As Maxime mentioned, many options are
> not necessary (see below).
>
> Some options are now set by ARCH_SUNXI, since 48313fe51008.
>
> >> On Wed, Jul 22, 2020 at 03:18:40PM +0100, Peter Robinson wrote:
> >>> The Pine64 Pinephone is a smartphone based on the AllWinner A64 SoC.
> >>> It has the following features:
> >>> * 2GB LPDDR3 SDRAM
> >>> * 5.95 inch 1440x720 HD IPS capacitive touchscreen
> >>> * 16GB eMMC, mSD slot
> >>> * Quectel EG25 LTE Modem
> >>> * Realtek RTL8723CS WiFi/BT
> >>> * Front and read cameras
> >>> * Accelerometer, gyro, proximity, ambient light, compass sensors
> >>> * A USB Type-C, USB Host, DisplayPort alt mode output, 15W 5V 3A Quick Charge, follows USB PD specification
> >>>
> >>> Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
> >>> ---
> >>> arch/arm/Kconfig | 2 +-
> >>> configs/pinephone_defconfig | 38 +++++++++++++++++++++++++++++++++++++
> >>> 2 files changed, 39 insertions(+), 1 deletion(-)
> >>> create mode 100644 configs/pinephone_defconfig
> >>>
> >>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> >>> index e16fe03887..636ba26938 100644
> >>> --- a/arch/arm/Kconfig
> >>> +++ b/arch/arm/Kconfig
> >>> @@ -1004,7 +1004,7 @@ config ARCH_SUNXI
> >>> bool "Support sunxi (Allwinner) SoCs"
> >>> select BINMAN
> >>> select CMD_GPIO
> >>> - select CMD_MMC if MMC
> >>> +select CMD_MMC if MMC
> >>
> >> That looks like a typo?
> >
> > Yes, it is.
> >
> >>> select CMD_USB if DISTRO_DEFAULTS
> >>> select CLK
> >>> select DM
> >>> diff --git a/configs/pinephone_defconfig b/configs/pinephone_defconfig
> >>> new file mode 100644
> >>> index 0000000000..d5750aa954
> >>> --- /dev/null
> >>> +++ b/configs/pinephone_defconfig
> >>> @@ -0,0 +1,38 @@
> >>> +CONFIG_ARM=y
> >>> +CONFIG_ARCH_SUNXI=y
> >>> +CONFIG_SPL=y
> >>> +CONFIG_MACH_SUN50I=y
> >>> +CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
> >>> +CONFIG_DRAM_CLK=552
> >>> +CONFIG_DRAM_ZQ=3881949
> >>> +CONFIG_NR_DRAM_BANKS=1
>
> defaults to 1 now for ARCH_SUNXI
So really, one needs to run `make savedefconfig`, copy defconfig to
configs/foo_defconfig and then see if there's some changes / settings
there that are unexpected. Because if you put a change in there, and
then run `make foo_defconfig` and don't see what you want in the new
.config file, there's a missing dependency or similar. Thanks!
--
Tom
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 6/8] arm: dts: Sync the sun50i-a64.dtsi from Linux 5.8-rc1
2020-07-27 13:16 ` Heinrich Schuchardt
@ 2020-07-29 0:30 ` André Przywara
0 siblings, 0 replies; 17+ messages in thread
From: André Przywara @ 2020-07-29 0:30 UTC (permalink / raw)
To: u-boot
On 27/07/2020 14:16, Heinrich Schuchardt wrote:
Hi Peter, Heinrich,
> On 26.07.20 12:17, Peter Robinson wrote:
>> On Thu, Jul 23, 2020 at 12:15 AM Andr? Przywara <andre.przywara@arm.com> wrote:
>>>
>>> On 22/07/2020 15:18, Peter Robinson wrote:
>>>> Sync the Allwinner A64 sun50i-a64.dtsi from Linux.
>>>
>>> Hi Peter,
>>>
>>> thanks for your series!
>>>
>>> While this looks mostly straight-forward, the problem is that this patch
>>> here affects all Allwinner boards. And for them it breaks older kernels,
>>> which cannot cope with some of the changed bindings or nodes.
>>> Your patches up until here are fine, since they only add nodes and
>>> properties, but this update changes nodes, some in a non-compatible way.
>>>
>>> Examples are dropping the "syscon" compatible (which requires 4.18 to
>>> know about the new compatible string) and the dropping of
>>> internal-osc-clk and the connected RTC change. This breaks any kernels
>>> that don't know about the third RTC clock (<&rtc 2>) or the new
>>> compatible string (introduced in 4.20). Similar effects show up in other
>>> OSes.
>>
>> The 4.18 kernel is over 2 years old. How many users are going to
>> actively upgrade U-Boot to the latest and not the kernel all while
>> using the U-Boot provided DT and not just loading the matching kernel
>> DT supplied by what ever ancient kernel they happen to choose to use?
Everyone who wants to boot the UEFI/distro way, using the DT as a
hardware description, provided by the firmware. Yes, for years people
got used to somehow get some matching revision of the right DT loaded
together with the kernel, but the UEFI boot flow makes this rather hard
to do.
And with the availability of $fdtcontroladdr (which is actually
implicit if bootefi is just called with one argument) this would all fit
so nicely: You have your device specific firmware build (firmware in the
classis sense, not the Android meaning), and the rest (kernel, userland,
secondary bootloaders) is generic and everything falls in place.
>> I feel this use case is quite a corner case and in those cases they're
>> probably not using a vanilla upstream U-Boot anyway.
>
> Sure people using an old Linux distribution not providing an U-Boot
> image may do so.
>
> But here we are talking about the U-Boot device tree.
What is a "U-Boot device tree"? The device tree describes the hardware,
so how would that be different between Linux, U-Boot, FreeBSD or Zephyr?
For practical reasons (no on-board storage, for instance) the DT is
shipped with some software/firmware, but the concept is still that of a
kernel-agnostic description.
Actually U-Boot's own DT needs are very minimal: we could get away with
a VERY basic DT, barely containing a clock node, and MMC, EMAC and USB
nodes with just reg and clocks properties.
But since a U-Boot build is per-board, it sounds natural to make this
the only place which holds the respective devicetree, so any user would
just consume it and doesn't need to have any further board specific
information.
> As Linux device
> trees are release specific you should not try to boot Linux using a
> devicetree not provided by the exact same Linux version.
Where does this statement come from? Definitely you can boot Linux with
DTs from a previous version, but conceptually DTs are independent from
any software consumer. It's just very hard to get that right if you
don't have all the documentation upfront, to create DT nodes which
describe everything you need. That's why some platform maintainers
decided to not guarantee forward compatibility for their platform.
Which doesn't mean we should not still aim at this, hence my request to
tweak some compatible string to restore compatibility across various
Linux kernel releases (used by distributions as their official kernel).
> So incompatiblities between old Linux releases and U-Boot's device tree
> should be irrelevant.
>
> Best regards
>
> Heinrich
>
>>
>>> I was experimenting with some small changes (compared to mainline) to
>>> overcome those issues, mostly by *adding* compatible strings instead of
>>> *replacing* them.
>>
>> Shouldn't they be added to a -u-boot.dtsi?
This might be a possible way to implement this, although the idea of
those files is to accommodate U-Boot specific nodes or properties.
Cheers,
Andre
>>> So I would like to ask for a few days so that I can do more testing with
>>> various kernels. I would then post those changes, so that we can discuss
>>> them.
>>>
>>> Cheers,
>>> Andre
>>>
>>>>
>>>> Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
>>>> ---
>>>> arch/arm/dts/sun50i-a64.dtsi | 532 ++++++++++++++++++++++++++++-------
>>>> 1 file changed, 434 insertions(+), 98 deletions(-)
>>>>
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2020-07-29 0:30 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-22 14:18 Initial support for the Pine64 Pinephone Peter Robinson
2020-07-22 14:18 ` [PATCH 1/8] dt-bindings: clk: sync sun50i-a64-ccu.h to linux 5.8-rc1 Peter Robinson
2020-07-22 14:18 ` [PATCH 2/8] dt-bindings: leds: sync leds common.h to linux from 5.8-rc1 Peter Robinson
2020-07-22 14:18 ` [PATCH 3/8] dt-bindings: clk/reset: sync updated bindings for Allwinner DE2 display engine Peter Robinson
2020-07-22 14:18 ` [PATCH 4/8] arm: dts: sync axp803.dtsi from linux 5.8-rc1 Peter Robinson
2020-07-22 14:18 ` [PATCH 5/8] arm: dts: Add new sun50i-a64-cpu-opp.dtsi from Linux 5.8-rc1 Peter Robinson
2020-07-22 14:18 ` [PATCH 6/8] arm: dts: Sync the sun50i-a64.dtsi " Peter Robinson
2020-07-22 23:14 ` André Przywara
2020-07-26 10:17 ` Peter Robinson
2020-07-27 13:16 ` Heinrich Schuchardt
2020-07-29 0:30 ` André Przywara
2020-07-22 14:18 ` [PATCH 7/8] arm64: dts: allwinner: Add initial support for Pine64 PinePhone Peter Robinson
2020-07-22 14:18 ` [PATCH 8/8] Initial Pine64 Pinephone support Peter Robinson
2020-07-27 13:30 ` Maxime Ripard
2020-07-27 13:49 ` Peter Robinson
2020-07-27 20:08 ` André Przywara
2020-07-27 20:43 ` Tom Rini
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