* [Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock
@ 2020-10-03 0:18 Imre Deak
2020-10-03 0:18 ` [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming Imre Deak
` (16 more replies)
0 siblings, 17 replies; 47+ messages in thread
From: Imre Deak @ 2020-10-03 0:18 UTC (permalink / raw)
To: intel-gfx
This patchset replaces [1]. That version's solution to work around
broken TGL A BIOSes turned out to be papering over something. The real
root cause was the lack of a full encoder recompute/modeset during the
initial commit and leaking the incorrect link rate into the PLL
frequency calculation code. So instead of making the PLL code aware of
incorrect link rates, this patchset forces a full modeset which will
recompute the correct link rate.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
[1] https://patchwork.freedesktop.org/series/82173/
Imre Deak (5):
drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
drm/i915: Move the initial fastset commit check to encoder hooks
drm/i915: Check for unsupported DP link rates during initial commit
drm/i915: Add an encoder hook to sanitize its state during init/resume
drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref
clock
drivers/gpu/drm/i915/display/icl_dsi.c | 14 ++++
drivers/gpu/drm/i915/display/intel_ddi.c | 18 +++++
drivers/gpu/drm/i915/display/intel_display.c | 33 +++++-----
.../drm/i915/display/intel_display_types.h | 15 +++++
drivers/gpu/drm/i915/display/intel_dp.c | 65 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 5 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 20 ++++++
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 55 +++++++++++-----
drivers/gpu/drm/i915/i915_reg.h | 1 +
9 files changed, 194 insertions(+), 32 deletions(-)
--
2.25.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
2020-10-03 0:18 [Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
@ 2020-10-03 0:18 ` Imre Deak
2020-10-05 20:08 ` Ville Syrjälä
2020-10-06 1:35 ` [Intel-gfx] [PATCH v3 " Imre Deak
2020-10-03 0:18 ` [Intel-gfx] [PATCH 2/5] drm/i915: Move the initial fastset commit check to encoder hooks Imre Deak
` (15 subsequent siblings)
16 siblings, 2 replies; 47+ messages in thread
From: Imre Deak @ 2020-10-03 0:18 UTC (permalink / raw)
To: intel-gfx
The BIOS of at least one ASUS-Z170M system with an SKL I have programs
the 101b WRPLL PDIV divider value, which is the encoding for PDIV=7 with
bit#0 incorrectly set.
This happens with the
"3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9
HDMI mode (scaled from a 1024x768 src fb) set by BIOS and the
ref_clock=24000, dco_integer=383, dco_fraction=5802, pdiv=7, qdiv=1, kdiv=1
WRPLL parameters (assuming PDIV=7 was the intended setting). This
corresponds to 262749 PLL frequency/port clock.
Later the driver sets the same mode for which it calculates the same
dco_int/dco_frac/div WRPLL parameters (with the correct PDIV=7 encoding).
Based on the above, let's assume that PDIV=7 was intended and the HW
just ignores bit#0 in the PDIV register field for this setting, treating
100b and 101b encodings the same way.
While at it add the MISSING_CASE() for the p0,p2 divider decodings.
v2: (Ville)
- Add a define for the incorrect divider value.
- Emit only a debug message when detecting the incorrect divider value.
- Use fallthrough from the incorrect divider value case.
- Add the MISSING_CASE()s.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 14 ++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index e08684e34078..61cb558c60d1 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -1602,12 +1602,26 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
case DPLL_CFGCR2_PDIV_3:
p0 = 3;
break;
+ default:
+ if (p0 == DPLL_CFGCR2_PDIV_7_INVALID)
+ /*
+ * Incorrect ASUS-Z170M BIOS setting, the HW seems to ignore bit#0,
+ * handling it the same way as PDIV_7.
+ */
+ drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n");
+ else
+ MISSING_CASE(p0);
+
+ fallthrough;
case DPLL_CFGCR2_PDIV_7:
p0 = 7;
break;
}
switch (p2) {
+ default:
+ MISSING_CASE(p2);
+ fallthrough;
case DPLL_CFGCR2_KDIV_5:
p2 = 5;
break;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 88c215cf97d4..d911583526db 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10261,6 +10261,7 @@ enum skl_power_gate {
#define DPLL_CFGCR2_PDIV_2 (1 << 2)
#define DPLL_CFGCR2_PDIV_3 (2 << 2)
#define DPLL_CFGCR2_PDIV_7 (4 << 2)
+#define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2)
#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
--
2.25.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 2/5] drm/i915: Move the initial fastset commit check to encoder hooks
2020-10-03 0:18 [Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
2020-10-03 0:18 ` [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming Imre Deak
@ 2020-10-03 0:18 ` Imre Deak
2020-10-03 1:07 ` [Intel-gfx] [PATCH v2 " Imre Deak
2020-10-03 0:18 ` [Intel-gfx] [PATCH 3/5] drm/i915: Check for unsupported DP link rates during initial commit Imre Deak
` (14 subsequent siblings)
16 siblings, 1 reply; 47+ messages in thread
From: Imre Deak @ 2020-10-03 0:18 UTC (permalink / raw)
To: intel-gfx
Move the checks to decide whether a fastset is possible during the
initial commit to an encoder hook. This check is really encoder specific
and the next patch will also require this adding a DP encoder specific
check.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 14 +++++++++
drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++++++
drivers/gpu/drm/i915/display/intel_display.c | 29 +++++++++----------
.../drm/i915/display/intel_display_types.h | 8 +++++
drivers/gpu/drm/i915/display/intel_dp.c | 22 ++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 3 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 +++++++
7 files changed, 80 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index fe946a2e2082..6c7220506410 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1668,6 +1668,19 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
return ret;
}
+static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ if (!crtc_state->dsc.compression_enable) {
+ drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n");
+ crtc_state->uapi.mode_changed = true;
+
+ return false;
+ }
+
+ return true;
+}
+
static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
{
intel_encoder_destroy(encoder);
@@ -1923,6 +1936,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
encoder->update_pipe = intel_panel_update_backlight;
encoder->compute_config = gen11_dsi_compute_config;
encoder->get_hw_state = gen11_dsi_get_hw_state;
+ encoder->initial_fastset_check = gen11_dsi_initial_fastset_check;
encoder->type = INTEL_OUTPUT_DSI;
encoder->cloneable = 0;
encoder->pipe_mask = ~0;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b4c520348b3b..4e54c55ec99f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4564,6 +4564,15 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
}
+static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ if (intel_crtc_has_dp_encoder(crtc_state))
+ return intel_dp_initial_fastset_check(encoder, crtc_state);
+
+ return true;
+}
+
static enum intel_output_type
intel_ddi_compute_output_type(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
@@ -5173,6 +5182,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder->update_pipe = intel_ddi_update_pipe;
encoder->get_hw_state = intel_ddi_get_hw_state;
encoder->get_config = intel_ddi_get_config;
+ encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
encoder->suspend = intel_dp_encoder_suspend;
encoder->get_power_domains = intel_ddi_get_power_domains;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 753f202ef6a0..31be63225b10 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17951,6 +17951,8 @@ static int intel_initial_commit(struct drm_device *dev)
}
if (crtc_state->hw.active) {
+ struct intel_encoder *encoder;
+
/*
* We've not yet detected sink capabilities
* (audio,infoframes,etc.) and thus we don't want to
@@ -17972,22 +17974,17 @@ static int intel_initial_commit(struct drm_device *dev)
*/
crtc_state->uapi.color_mgmt_changed = true;
- /*
- * FIXME hack to force full modeset when DSC is being
- * used.
- *
- * As long as we do not have full state readout and
- * config comparison of crtc_state->dsc, we have no way
- * to ensure reliable fastset. Remove once we have
- * readout for DSC.
- */
- if (crtc_state->dsc.compression_enable) {
- ret = drm_atomic_add_affected_connectors(state,
- &crtc->base);
- if (ret)
- goto out;
- crtc_state->uapi.mode_changed = true;
- drm_dbg_kms(dev, "Force full modeset for DSC\n");
+ for_each_intel_encoder_mask(dev, encoder,
+ crtc_state->uapi.encoder_mask) {
+ if (encoder->initial_fastset_check &&
+ !encoder->initial_fastset_check(encoder, crtc_state)) {
+ ret = drm_atomic_add_affected_connectors(state,
+ &crtc->base);
+ if (ret)
+ goto out;
+
+ break;
+ }
}
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index d5dc18cb8c39..5297b2f08ff9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -187,6 +187,14 @@ struct intel_encoder {
* be set correctly before calling this function. */
void (*get_config)(struct intel_encoder *,
struct intel_crtc_state *pipe_config);
+
+ /*
+ * Optional hook, returning true if this encoder allows a fastset
+ * during the initial commit, false otherwise.
+ */
+ bool (*initial_fastset_check)(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state);
+
/*
* Acquires the power domains needed for an active encoder during
* hardware state readout.
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7429597b57be..d33a3d9fdc3a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3703,6 +3703,27 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
}
}
+bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+ /*
+ * FIXME hack to force full modeset when DSC is being used.
+ *
+ * As long as we do not have full state readout and config comparison
+ * of crtc_state->dsc, we have no way to ensure reliable fastset.
+ * Remove once we have readout for DSC.
+ */
+ if (crtc_state->dsc.compression_enable) {
+ drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
+ crtc_state->uapi.mode_changed = true;
+ return false;
+ }
+
+ return true;
+}
+
static void intel_disable_dp(struct intel_atomic_state *state,
struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state,
@@ -8057,6 +8078,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
intel_encoder->compute_config = intel_dp_compute_config;
intel_encoder->get_hw_state = intel_dp_get_hw_state;
intel_encoder->get_config = intel_dp_get_config;
+ intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
intel_encoder->update_pipe = intel_panel_update_backlight;
intel_encoder->suspend = intel_dp_encoder_suspend;
if (IS_CHERRYVIEW(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 66854aab9887..977585aea3c8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -141,4 +141,7 @@ void intel_ddi_update_pipe(struct intel_atomic_state *state,
int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
struct intel_connector *intel_connector);
+bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state);
+
#endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 82f38c386dbd..e948aacbd4ab 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -591,6 +591,15 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
intel_ddi_get_config(&dig_port->base, pipe_config);
}
+static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
+ struct intel_digital_port *dig_port = intel_mst->primary;
+
+ return intel_dp_initial_fastset_check(&dig_port->base, crtc_state);
+}
+
static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector)
{
struct intel_connector *intel_connector = to_intel_connector(connector);
@@ -897,6 +906,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe
intel_encoder->enable = intel_mst_enable_dp;
intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
intel_encoder->get_config = intel_dp_mst_enc_get_config;
+ intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;
return intel_mst;
--
2.25.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 3/5] drm/i915: Check for unsupported DP link rates during initial commit
2020-10-03 0:18 [Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
2020-10-03 0:18 ` [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming Imre Deak
2020-10-03 0:18 ` [Intel-gfx] [PATCH 2/5] drm/i915: Move the initial fastset commit check to encoder hooks Imre Deak
@ 2020-10-03 0:18 ` Imre Deak
2020-10-05 20:25 ` Ville Syrjälä
2020-10-03 0:18 ` [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume Imre Deak
` (13 subsequent siblings)
16 siblings, 1 reply; 47+ messages in thread
From: Imre Deak @ 2020-10-03 0:18 UTC (permalink / raw)
To: intel-gfx
Some BIOSes set an unsupported/imprecise DP link rate (for instance on
TGL A stepping). Make sure that we do an encoder recompute and a modeset
in this case.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d33a3d9fdc3a..df5277c2b9ba 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3707,6 +3707,18 @@ bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ /*
+ * If BIOS has set an unsupported or non-standard link rate for some
+ * reason force an encoder recompute and full modeset.
+ */
+ if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
+ crtc_state->port_clock) < 0) {
+ drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n");
+ crtc_state->uapi.connectors_changed = true;
+ return false;
+ }
/*
* FIXME hack to force full modeset when DSC is being used.
--
2.25.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume
2020-10-03 0:18 [Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
` (2 preceding siblings ...)
2020-10-03 0:18 ` [Intel-gfx] [PATCH 3/5] drm/i915: Check for unsupported DP link rates during initial commit Imre Deak
@ 2020-10-03 0:18 ` Imre Deak
2020-10-05 20:30 ` Ville Syrjälä
` (3 more replies)
2020-10-03 0:18 ` [Intel-gfx] [PATCH 5/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
` (12 subsequent siblings)
16 siblings, 4 replies; 47+ messages in thread
From: Imre Deak @ 2020-10-03 0:18 UTC (permalink / raw)
To: intel-gfx
Atm, if a full modeset is performed during the initial modeset the link
training will happen with uninitialized max DP rate and lane count. Make
sure the corresponding encoder state is initialized by adding an encoder
hook called during driver init and system resume.
A better alternative would be to store all states in the CRTC state and
make this state available for the link re-training code. Also instead of
the DPCD read in the hook there should be really a proper sink HW
readout in place. Both of these require a bigger rework, so for now opting
for this minimal fix to make at least full initial modesets work.
The patch is based on
https://patchwork.freedesktop.org/patch/101473/?series=10354&rev=3
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 8 +++++
drivers/gpu/drm/i915/display/intel_display.c | 4 +++
.../drm/i915/display/intel_display_types.h | 7 +++++
drivers/gpu/drm/i915/display/intel_dp.c | 31 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++++++
6 files changed, 62 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4e54c55ec99f..a0805260b224 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4564,6 +4564,13 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
}
+static void intel_ddi_sanitize_state(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ if (crtc_state && intel_crtc_has_dp_encoder(crtc_state))
+ intel_dp_sanitize_state(encoder, crtc_state);
+}
+
static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
@@ -5182,6 +5189,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder->update_pipe = intel_ddi_update_pipe;
encoder->get_hw_state = intel_ddi_get_hw_state;
encoder->get_config = intel_ddi_get_config;
+ encoder->sanitize_state = intel_ddi_sanitize_state;
encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
encoder->suspend = intel_dp_encoder_suspend;
encoder->get_power_domains = intel_ddi_get_power_domains;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 31be63225b10..e61311ee8b8c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -18725,8 +18725,12 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
encoder->base.crtc = &crtc->base;
encoder->get_config(encoder, crtc_state);
+ if (encoder->sanitize_state)
+ encoder->sanitize_state(encoder, crtc_state);
} else {
encoder->base.crtc = NULL;
+ if (encoder->sanitize_state)
+ encoder->sanitize_state(encoder, NULL);
}
drm_dbg_kms(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 5297b2f08ff9..b2b458144f5a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -188,6 +188,13 @@ struct intel_encoder {
void (*get_config)(struct intel_encoder *,
struct intel_crtc_state *pipe_config);
+ /*
+ * Optional hook called during init/resume to sanitize any state
+ * stored in the encoder (eg. DP link parameters).
+ */
+ void (*sanitize_state)(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
+
/*
* Optional hook, returning true if this encoder allows a fastset
* during the initial commit, false otherwise.
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index df5277c2b9ba..9b6fe3b3b5b2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3703,6 +3703,36 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
}
}
+static bool
+intel_dp_get_dpcd(struct intel_dp *intel_dp);
+
+/**
+ * intel_dp_sanitize_state - sanitize the encoder state during init/resume
+ * @encoder: intel encoder to sanitize
+ * @crtc_state: state for the CRTC connected to the encoder
+ *
+ * Sanitize any state stored in the encoder during driver init and system
+ * resume.
+ */
+void intel_dp_sanitize_state(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ if (!crtc_state)
+ return;
+
+ /*
+ * Don't clobber DPCD if it's been already read out during output
+ * setup (eDP) or detect.
+ */
+ if (!memchr_inv(intel_dp->dpcd, 0, sizeof(intel_dp->dpcd)))
+ intel_dp_get_dpcd(intel_dp);
+
+ intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
+ intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
+}
+
bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
@@ -8090,6 +8120,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
intel_encoder->compute_config = intel_dp_compute_config;
intel_encoder->get_hw_state = intel_dp_get_hw_state;
intel_encoder->get_config = intel_dp_get_config;
+ intel_encoder->sanitize_state = intel_dp_sanitize_state;
intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
intel_encoder->update_pipe = intel_panel_update_backlight;
intel_encoder->suspend = intel_dp_encoder_suspend;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 977585aea3c8..1ab741e0be67 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -143,5 +143,7 @@ int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state);
+void intel_dp_sanitize_state(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
#endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index e948aacbd4ab..0831d1ee7978 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -591,6 +591,15 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
intel_ddi_get_config(&dig_port->base, pipe_config);
}
+static void intel_dp_mst_sync_state(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
+ struct intel_digital_port *dig_port = intel_mst->primary;
+
+ return intel_dp_sanitize_state(&dig_port->base, crtc_state);
+}
+
static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
@@ -906,6 +915,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe
intel_encoder->enable = intel_mst_enable_dp;
intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
intel_encoder->get_config = intel_dp_mst_enc_get_config;
+ intel_encoder->sanitize_state = intel_dp_mst_sync_state;
intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;
return intel_mst;
--
2.25.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH 5/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock
2020-10-03 0:18 [Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
` (3 preceding siblings ...)
2020-10-03 0:18 ` [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume Imre Deak
@ 2020-10-03 0:18 ` Imre Deak
2020-10-03 0:40 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev2) Patchwork
` (11 subsequent siblings)
16 siblings, 0 replies; 47+ messages in thread
From: Imre Deak @ 2020-10-03 0:18 UTC (permalink / raw)
To: intel-gfx
Apply Display WA #22010492432 for combo PHY PLLs too. This should fix a
problem where the PLL output frequency is slightly off with the current
PLL fractional divider value.
I haven't seen an actual case where this causes a problem, but let's
follow the spec. It's also needed on some EHL platforms, but for that we
also need a way to distinguish the affected EHL SKUs, so I leave that
for a follow-up.
v2:
- Apply the WA at one place when calculating the PLL dividers from the
frequency and the frequency from the dividers for all the combo PLL
use cases (DP, HDMI, TBT). (Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 41 +++++++++++--------
1 file changed, 25 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 61cb558c60d1..421176de5cfb 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2636,11 +2636,22 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
return true;
}
+/*
+ * Display WA #22010492432: tgl
+ * Program half of the nominal DCO divider fraction value.
+ */
+static bool
+tgl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
+{
+ return IS_TIGERLAKE(i915) && i915->dpll.ref_clks.nssc == 38400;
+}
+
static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
const struct intel_shared_dpll *pll,
int ref_clock)
{
const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
+ u32 dco_fraction;
u32 p0, p1, p2, dco_freq;
p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
@@ -2683,8 +2694,13 @@ static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) *
ref_clock;
- dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
- DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
+ dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
+ DPLL_CFGCR0_DCO_FRACTION_SHIFT;
+
+ if (tgl_combo_pll_div_frac_wa_needed(dev_priv))
+ dco_fraction *= 2;
+
+ dco_freq += (dco_fraction * ref_clock) / 0x8000;
if (drm_WARN_ON(&dev_priv->drm, p0 == 0 || p1 == 0 || p2 == 0))
return 0;
@@ -2962,16 +2978,6 @@ static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = {
/* the following params are unused */
};
-/*
- * Display WA #22010492432: tgl
- * Divide the nominal .dco_fraction value by 2.
- */
-static const struct skl_wrpll_params tgl_tbt_pll_38_4MHz_values = {
- .dco_integer = 0x54, .dco_fraction = 0x1800,
- /* the following params are unused */
- .pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0,
-};
-
static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
struct skl_wrpll_params *pll_params)
{
@@ -3005,14 +3011,12 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
MISSING_CASE(dev_priv->dpll.ref_clks.nssc);
fallthrough;
case 19200:
+ case 38400:
*pll_params = tgl_tbt_pll_19_2MHz_values;
break;
case 24000:
*pll_params = tgl_tbt_pll_24MHz_values;
break;
- case 38400:
- *pll_params = tgl_tbt_pll_38_4MHz_values;
- break;
}
} else {
switch (dev_priv->dpll.ref_clks.nssc) {
@@ -3079,9 +3083,14 @@ static void icl_calc_dpll_state(struct drm_i915_private *i915,
const struct skl_wrpll_params *pll_params,
struct intel_dpll_hw_state *pll_state)
{
+ u32 dco_fraction = pll_params->dco_fraction;
+
memset(pll_state, 0, sizeof(*pll_state));
- pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params->dco_fraction) |
+ if (tgl_combo_pll_div_frac_wa_needed(i915))
+ dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2);
+
+ pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) |
pll_params->dco_integer;
pll_state->cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params->qdiv_ratio) |
--
2.25.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev2)
2020-10-03 0:18 [Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
` (4 preceding siblings ...)
2020-10-03 0:18 ` [Intel-gfx] [PATCH 5/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
@ 2020-10-03 0:40 ` Patchwork
2020-10-03 0:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (10 subsequent siblings)
16 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2020-10-03 0:40 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev2)
URL : https://patchwork.freedesktop.org/series/82173/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216
+./include/linux/seqlock.h:752:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:778:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev2)
2020-10-03 0:18 [Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
` (5 preceding siblings ...)
2020-10-03 0:40 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev2) Patchwork
@ 2020-10-03 0:58 ` Patchwork
2020-10-03 1:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3) Patchwork
` (9 subsequent siblings)
16 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2020-10-03 0:58 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 4628 bytes --]
== Series Details ==
Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev2)
URL : https://patchwork.freedesktop.org/series/82173/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9093 -> Patchwork_18619
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18619/index.html
Known issues
------------
Here are the changes found in Patchwork_18619 that come from known issues:
### CI changes ###
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload:
- fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/fi-byt-j1900/igt@i915_module_load@reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18619/fi-byt-j1900/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18619/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18619/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
#### Warnings ####
* igt@i915_pm_rpm@basic-rte:
- fi-kbl-guc: [DMESG-FAIL][7] ([i915#2203]) -> [SKIP][8] ([fdo#109271])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18619/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
* igt@kms_force_connector_basic@prune-stale-modes:
- fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92]) -> [DMESG-WARN][10] ([i915#62] / [i915#92] / [i915#95]) +6 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/fi-kbl-x1275/igt@kms_force_connector_basic@prune-stale-modes.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18619/fi-kbl-x1275/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@prime_vgem@basic-fence-flip:
- fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/fi-kbl-x1275/igt@prime_vgem@basic-fence-flip.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18619/fi-kbl-x1275/igt@prime_vgem@basic-fence-flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#2448]: https://gitlab.freedesktop.org/drm/intel/issues/2448
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (45 -> 39)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9093 -> Patchwork_18619
CI-20190529: 20190529
CI_DRM_9093: 827ebff930c6340ed1c1c274909717525951c496 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5798: 430bad5a53c08125fbd48978ed6a66f61a33a40b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18619: 1f86980be6c9f250cace3c634b8f62a9fcc4d57b @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
1f86980be6c9 drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock
57989410859f drm/i915: Add an encoder hook to sanitize its state during init/resume
a5fbed9f3baa drm/i915: Check for unsupported DP link rates during initial commit
275ab3d8d970 drm/i915: Move the initial fastset commit check to encoder hooks
056e9d5d8a88 drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18619/index.html
[-- Attachment #1.2: Type: text/html, Size: 5915 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH v2 2/5] drm/i915: Move the initial fastset commit check to encoder hooks
2020-10-03 0:18 ` [Intel-gfx] [PATCH 2/5] drm/i915: Move the initial fastset commit check to encoder hooks Imre Deak
@ 2020-10-03 1:07 ` Imre Deak
2020-10-05 20:24 ` Ville Syrjälä
2020-10-05 21:53 ` [Intel-gfx] [PATCH v3 " Imre Deak
0 siblings, 2 replies; 47+ messages in thread
From: Imre Deak @ 2020-10-03 1:07 UTC (permalink / raw)
To: intel-gfx
Move the checks to decide whether a fastset is possible during the
initial commit to an encoder hook. This check is really encoder specific
and the next patch will also require this adding a DP encoder specific
check.
v2: Fix negated condition in gen11_dsi_initial_fastset_check().
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 14 +++++++++
drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++++++
drivers/gpu/drm/i915/display/intel_display.c | 29 +++++++++----------
.../drm/i915/display/intel_display_types.h | 8 +++++
drivers/gpu/drm/i915/display/intel_dp.c | 22 ++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 3 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 +++++++
7 files changed, 80 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index fe946a2e2082..4400e83f783f 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1668,6 +1668,19 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
return ret;
}
+static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ if (crtc_state->dsc.compression_enable) {
+ drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n");
+ crtc_state->uapi.mode_changed = true;
+
+ return false;
+ }
+
+ return true;
+}
+
static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
{
intel_encoder_destroy(encoder);
@@ -1923,6 +1936,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
encoder->update_pipe = intel_panel_update_backlight;
encoder->compute_config = gen11_dsi_compute_config;
encoder->get_hw_state = gen11_dsi_get_hw_state;
+ encoder->initial_fastset_check = gen11_dsi_initial_fastset_check;
encoder->type = INTEL_OUTPUT_DSI;
encoder->cloneable = 0;
encoder->pipe_mask = ~0;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b4c520348b3b..4e54c55ec99f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4564,6 +4564,15 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
}
+static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ if (intel_crtc_has_dp_encoder(crtc_state))
+ return intel_dp_initial_fastset_check(encoder, crtc_state);
+
+ return true;
+}
+
static enum intel_output_type
intel_ddi_compute_output_type(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
@@ -5173,6 +5182,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder->update_pipe = intel_ddi_update_pipe;
encoder->get_hw_state = intel_ddi_get_hw_state;
encoder->get_config = intel_ddi_get_config;
+ encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
encoder->suspend = intel_dp_encoder_suspend;
encoder->get_power_domains = intel_ddi_get_power_domains;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 753f202ef6a0..31be63225b10 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17951,6 +17951,8 @@ static int intel_initial_commit(struct drm_device *dev)
}
if (crtc_state->hw.active) {
+ struct intel_encoder *encoder;
+
/*
* We've not yet detected sink capabilities
* (audio,infoframes,etc.) and thus we don't want to
@@ -17972,22 +17974,17 @@ static int intel_initial_commit(struct drm_device *dev)
*/
crtc_state->uapi.color_mgmt_changed = true;
- /*
- * FIXME hack to force full modeset when DSC is being
- * used.
- *
- * As long as we do not have full state readout and
- * config comparison of crtc_state->dsc, we have no way
- * to ensure reliable fastset. Remove once we have
- * readout for DSC.
- */
- if (crtc_state->dsc.compression_enable) {
- ret = drm_atomic_add_affected_connectors(state,
- &crtc->base);
- if (ret)
- goto out;
- crtc_state->uapi.mode_changed = true;
- drm_dbg_kms(dev, "Force full modeset for DSC\n");
+ for_each_intel_encoder_mask(dev, encoder,
+ crtc_state->uapi.encoder_mask) {
+ if (encoder->initial_fastset_check &&
+ !encoder->initial_fastset_check(encoder, crtc_state)) {
+ ret = drm_atomic_add_affected_connectors(state,
+ &crtc->base);
+ if (ret)
+ goto out;
+
+ break;
+ }
}
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index d5dc18cb8c39..5297b2f08ff9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -187,6 +187,14 @@ struct intel_encoder {
* be set correctly before calling this function. */
void (*get_config)(struct intel_encoder *,
struct intel_crtc_state *pipe_config);
+
+ /*
+ * Optional hook, returning true if this encoder allows a fastset
+ * during the initial commit, false otherwise.
+ */
+ bool (*initial_fastset_check)(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state);
+
/*
* Acquires the power domains needed for an active encoder during
* hardware state readout.
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7429597b57be..d33a3d9fdc3a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3703,6 +3703,27 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
}
}
+bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+ /*
+ * FIXME hack to force full modeset when DSC is being used.
+ *
+ * As long as we do not have full state readout and config comparison
+ * of crtc_state->dsc, we have no way to ensure reliable fastset.
+ * Remove once we have readout for DSC.
+ */
+ if (crtc_state->dsc.compression_enable) {
+ drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
+ crtc_state->uapi.mode_changed = true;
+ return false;
+ }
+
+ return true;
+}
+
static void intel_disable_dp(struct intel_atomic_state *state,
struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state,
@@ -8057,6 +8078,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
intel_encoder->compute_config = intel_dp_compute_config;
intel_encoder->get_hw_state = intel_dp_get_hw_state;
intel_encoder->get_config = intel_dp_get_config;
+ intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
intel_encoder->update_pipe = intel_panel_update_backlight;
intel_encoder->suspend = intel_dp_encoder_suspend;
if (IS_CHERRYVIEW(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 66854aab9887..977585aea3c8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -141,4 +141,7 @@ void intel_ddi_update_pipe(struct intel_atomic_state *state,
int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
struct intel_connector *intel_connector);
+bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state);
+
#endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 82f38c386dbd..e948aacbd4ab 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -591,6 +591,15 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
intel_ddi_get_config(&dig_port->base, pipe_config);
}
+static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
+ struct intel_digital_port *dig_port = intel_mst->primary;
+
+ return intel_dp_initial_fastset_check(&dig_port->base, crtc_state);
+}
+
static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector)
{
struct intel_connector *intel_connector = to_intel_connector(connector);
@@ -897,6 +906,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe
intel_encoder->enable = intel_mst_enable_dp;
intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
intel_encoder->get_config = intel_dp_mst_enc_get_config;
+ intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;
return intel_mst;
--
2.25.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3)
2020-10-03 0:18 [Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
` (6 preceding siblings ...)
2020-10-03 0:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-10-03 1:31 ` Patchwork
2020-10-03 1:52 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (8 subsequent siblings)
16 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2020-10-03 1:31 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3)
URL : https://patchwork.freedesktop.org/series/82173/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216
+./include/linux/seqlock.h:752:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:778:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3)
2020-10-03 0:18 [Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
` (7 preceding siblings ...)
2020-10-03 1:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3) Patchwork
@ 2020-10-03 1:52 ` Patchwork
2020-10-03 3:56 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
` (7 subsequent siblings)
16 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2020-10-03 1:52 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 5144 bytes --]
== Series Details ==
Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3)
URL : https://patchwork.freedesktop.org/series/82173/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9093 -> Patchwork_18620
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/index.html
Known issues
------------
Here are the changes found in Patchwork_18620 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_pm_rpm@module-reload:
- fi-apl-guc: [PASS][3] -> [DMESG-WARN][4] ([i915#1635] / [i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/fi-apl-guc/igt@i915_pm_rpm@module-reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/fi-apl-guc/igt@i915_pm_rpm@module-reload.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
#### Possible fixes ####
* igt@i915_module_load@reload:
- {fi-tgl-dsi}: [DMESG-WARN][7] ([i915#1982] / [k.org#205379]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/fi-tgl-dsi/igt@i915_module_load@reload.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/fi-tgl-dsi/igt@i915_module_load@reload.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s0:
- fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][10] ([i915#62] / [i915#92]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
* igt@i915_pm_rpm@basic-rte:
- fi-kbl-guc: [DMESG-FAIL][11] ([i915#2203]) -> [SKIP][12] ([fdo#109271])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
* igt@kms_force_connector_basic@prune-stale-modes:
- fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/fi-kbl-x1275/igt@kms_force_connector_basic@prune-stale-modes.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/fi-kbl-x1275/igt@kms_force_connector_basic@prune-stale-modes.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (45 -> 39)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9093 -> Patchwork_18620
CI-20190529: 20190529
CI_DRM_9093: 827ebff930c6340ed1c1c274909717525951c496 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5798: 430bad5a53c08125fbd48978ed6a66f61a33a40b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18620: 77fe9153f15371efa976b7ebdb10e9a1df31054e @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
77fe9153f153 drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock
5eca404d0060 drm/i915: Add an encoder hook to sanitize its state during init/resume
99999f4fedb1 drm/i915: Check for unsupported DP link rates during initial commit
94f36ee39ef6 drm/i915: Move the initial fastset commit check to encoder hooks
f0622b209712 drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/index.html
[-- Attachment #1.2: Type: text/html, Size: 6513 bytes --]
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3)
2020-10-03 0:18 [Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
` (8 preceding siblings ...)
2020-10-03 1:52 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-10-03 3:56 ` Patchwork
2020-10-03 13:48 ` Imre Deak
2020-10-04 5:47 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
` (6 subsequent siblings)
16 siblings, 1 reply; 47+ messages in thread
From: Patchwork @ 2020-10-03 3:56 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 14125 bytes --]
== Series Details ==
Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3)
URL : https://patchwork.freedesktop.org/series/82173/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9093_full -> Patchwork_18620_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18620_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18620_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18620_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-skl: [PASS][1] -> [TIMEOUT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl6/igt@gem_userptr_blits@unsync-unmap-cycles.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl4/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@kms_flip@flip-vs-suspend@c-edp1:
- shard-iclb: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-iclb3/igt@kms_flip@flip-vs-suspend@c-edp1.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-iclb3/igt@kms_flip@flip-vs-suspend@c-edp1.html
Known issues
------------
Here are the changes found in Patchwork_18620_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#198])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl1/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl1/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-skl: [PASS][7] -> [TIMEOUT][8] ([i915#2424])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl10/igt@gem_userptr_blits@sync-unmap-cycles.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl2/igt@gem_userptr_blits@sync-unmap-cycles.html
* igt@kms_big_fb@linear-8bpp-rotate-0:
- shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-kbl6/igt@kms_big_fb@linear-8bpp-rotate-0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-kbl4/igt@kms_big_fb@linear-8bpp-rotate-0.html
* igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge:
- shard-glk: [PASS][11] -> [DMESG-WARN][12] ([i915#1982])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-glk4/igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-glk5/igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled:
- shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#1635] / [i915#1982]) +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-apl7/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-apl1/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled.html
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled:
- shard-skl: [PASS][15] -> [FAIL][16] ([i915#177] / [i915#52] / [i915#54])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl7/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl7/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1:
- shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +9 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl8/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl1/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html
* igt@kms_flip@plain-flip-ts-check@c-edp1:
- shard-skl: [PASS][19] -> [FAIL][20] ([i915#2122])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl9/igt@kms_flip@plain-flip-ts-check@c-edp1.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl8/igt@kms_flip@plain-flip-ts-check@c-edp1.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt:
- shard-tglb: [PASS][21] -> [DMESG-WARN][22] ([i915#1982])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-tglb1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-tglb2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-skl: [PASS][23] -> [INCOMPLETE][24] ([i915#123])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl6/igt@kms_frontbuffer_tracking@psr-suspend.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl4/igt@kms_frontbuffer_tracking@psr-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [PASS][25] -> [DMESG-WARN][26] ([i915#180]) +3 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][27] -> [FAIL][28] ([fdo#108145] / [i915#265]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_scaling@pipe-c-scaler-with-clipping-clamping:
- shard-iclb: [PASS][29] -> [DMESG-WARN][30] ([i915#1982])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-iclb1/igt@kms_plane_scaling@pipe-c-scaler-with-clipping-clamping.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-iclb3/igt@kms_plane_scaling@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109441]) +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-iclb8/igt@kms_psr@psr2_no_drrs.html
#### Possible fixes ####
* igt@gem_exec_reloc@basic-many-active@vecs0:
- shard-glk: [FAIL][33] ([i915#2389]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-glk2/igt@gem_exec_reloc@basic-many-active@vecs0.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-glk3/igt@gem_exec_reloc@basic-many-active@vecs0.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [DMESG-WARN][35] ([i915#1436] / [i915#716]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl7/igt@gen9_exec_parse@allowed-single.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl1/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@bb-start-param:
- shard-skl: [DMESG-WARN][37] ([i915#1982]) -> [PASS][38] +2 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl1/igt@gen9_exec_parse@bb-start-param.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl1/igt@gen9_exec_parse@bb-start-param.html
* {igt@kms_async_flips@async-flip-with-page-flip-events}:
- shard-kbl: [FAIL][39] ([i915#2521]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-kbl1/igt@kms_async_flips@async-flip-with-page-flip-events.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-kbl1/igt@kms_async_flips@async-flip-with-page-flip-events.html
* igt@kms_flip@plain-flip-fb-recreate@b-edp1:
- shard-skl: [FAIL][41] ([i915#2122]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl2/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl9/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
* igt@kms_flip_tiling@flip-changes-tiling-yf:
- shard-kbl: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-kbl1/igt@kms_flip_tiling@flip-changes-tiling-yf.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-kbl1/igt@kms_flip_tiling@flip-changes-tiling-yf.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][45] ([fdo#108145] / [i915#265]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [SKIP][47] ([fdo#109441]) -> [PASS][48] +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-iclb8/igt@kms_psr@psr2_cursor_blt.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
* igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
- shard-kbl: [INCOMPLETE][49] ([i915#155]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-kbl2/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [FAIL][51] ([i915#1515]) -> [WARN][52] ([i915#1515])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-iclb6/igt@i915_pm_rc6_residency@rc6-idle.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-iclb7/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-skl: [DMESG-FAIL][53] ([i915#1982]) -> [DMESG-WARN][54] ([i915#1982])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [DMESG-WARN][55] ([i915#1982]) -> [DMESG-FAIL][56] ([i915#1982])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl3/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-skl: [INCOMPLETE][57] ([i915#198]) -> [DMESG-WARN][58] ([i915#1982])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl8/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl5/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#177]: https://gitlab.freedesktop.org/drm/intel/issues/177
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2424]: https://gitlab.freedesktop.org/drm/intel/issues/2424
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9093 -> Patchwork_18620
CI-20190529: 20190529
CI_DRM_9093: 827ebff930c6340ed1c1c274909717525951c496 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5798: 430bad5a53c08125fbd48978ed6a66f61a33a40b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18620: 77fe9153f15371efa976b7ebdb10e9a1df31054e @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/index.html
[-- Attachment #1.2: Type: text/html, Size: 16672 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3)
2020-10-03 3:56 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-10-03 13:48 ` Imre Deak
2020-10-04 6:12 ` Vudum, Lakshminarayana
0 siblings, 1 reply; 47+ messages in thread
From: Imre Deak @ 2020-10-03 13:48 UTC (permalink / raw)
To: intel-gfx, Lakshminarayana Vudum, Tomi P Sarvela
Hi Lakshmi, Tomi,
On Sat, Oct 03, 2020 at 03:56:00AM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3)
> URL : https://patchwork.freedesktop.org/series/82173/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_9093_full -> Patchwork_18620_full
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_18620_full absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_18620_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_18620_full:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@gem_userptr_blits@unsync-unmap-cycles:
> - shard-skl: [PASS][1] -> [TIMEOUT][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl6/igt@gem_userptr_blits@unsync-unmap-cycles.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl4/igt@gem_userptr_blits@unsync-unmap-cycles.html
This looks like
https://gitlab.freedesktop.org/drm/intel/-/issues/2424
still happening at
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9090/shard-skl5/igt@gem_userptr_blits@sync-unmap-cycles.html
Could you update the filter to include sync-unmap-cycles as well?
> * igt@kms_flip@flip-vs-suspend@c-edp1:
> - shard-iclb: [PASS][3] -> [INCOMPLETE][4]
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-iclb3/igt@kms_flip@flip-vs-suspend@c-edp1.html
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-iclb3/igt@kms_flip@flip-vs-suspend@c-edp1.html
Looks like shard-iclb3 has a file system corruption, or just broken
storage device/host:
<3>[ 240.012780] blk_update_request: I/O error, dev sda, sector 76863120 op 0x1:(WRITE) flags 0x800 phys_seg 10 prio class 0
This has been consistently happening now for a while on the shard-iclb3
machine leading to the same hang, see for instance
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9063/shard-iclb3/pstore7-1601302770_Panic_1.txt
Similar sporadic filesystem errors have been also happening on
shard-iclb4.
I haven't seen any recent I/O errors on any of the other 7 shard-icl
machines.
shard-iclb3/4 would probably need reinstall/new storage device/new host.
--Imre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3)
2020-10-03 0:18 [Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
` (9 preceding siblings ...)
2020-10-03 3:56 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-10-04 5:47 ` Patchwork
2020-10-06 0:01 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6) Patchwork
` (5 subsequent siblings)
16 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2020-10-04 5:47 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 13388 bytes --]
== Series Details ==
Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3)
URL : https://patchwork.freedesktop.org/series/82173/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9093_full -> Patchwork_18620_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_18620_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-skl: [PASS][1] -> [INCOMPLETE][2] ([i915#198])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl1/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl1/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-skl: [PASS][3] -> [TIMEOUT][4] ([i915#2424]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl6/igt@gem_userptr_blits@unsync-unmap-cycles.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl4/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@kms_big_fb@linear-8bpp-rotate-0:
- shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-kbl6/igt@kms_big_fb@linear-8bpp-rotate-0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-kbl4/igt@kms_big_fb@linear-8bpp-rotate-0.html
* igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge:
- shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-glk4/igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-glk5/igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled:
- shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#1635] / [i915#1982]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-apl7/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-apl1/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled.html
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled:
- shard-skl: [PASS][11] -> [FAIL][12] ([i915#177] / [i915#52] / [i915#54])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl7/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl7/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1:
- shard-skl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +9 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl8/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl1/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend@c-edp1:
- shard-iclb: [PASS][15] -> [INCOMPLETE][16] ([i915#2536])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-iclb3/igt@kms_flip@flip-vs-suspend@c-edp1.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-iclb3/igt@kms_flip@flip-vs-suspend@c-edp1.html
* igt@kms_flip@plain-flip-ts-check@c-edp1:
- shard-skl: [PASS][17] -> [FAIL][18] ([i915#2122])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl9/igt@kms_flip@plain-flip-ts-check@c-edp1.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl8/igt@kms_flip@plain-flip-ts-check@c-edp1.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt:
- shard-tglb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-tglb1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-tglb2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-skl: [PASS][21] -> [INCOMPLETE][22] ([i915#123])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl6/igt@kms_frontbuffer_tracking@psr-suspend.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl4/igt@kms_frontbuffer_tracking@psr-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +3 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145] / [i915#265]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_scaling@pipe-c-scaler-with-clipping-clamping:
- shard-iclb: [PASS][27] -> [DMESG-WARN][28] ([i915#1982])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-iclb1/igt@kms_plane_scaling@pipe-c-scaler-with-clipping-clamping.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-iclb3/igt@kms_plane_scaling@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) +2 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-iclb8/igt@kms_psr@psr2_no_drrs.html
#### Possible fixes ####
* igt@gem_exec_reloc@basic-many-active@vecs0:
- shard-glk: [FAIL][31] ([i915#2389]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-glk2/igt@gem_exec_reloc@basic-many-active@vecs0.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-glk3/igt@gem_exec_reloc@basic-many-active@vecs0.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [DMESG-WARN][33] ([i915#1436] / [i915#716]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl7/igt@gen9_exec_parse@allowed-single.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl1/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@bb-start-param:
- shard-skl: [DMESG-WARN][35] ([i915#1982]) -> [PASS][36] +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl1/igt@gen9_exec_parse@bb-start-param.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl1/igt@gen9_exec_parse@bb-start-param.html
* {igt@kms_async_flips@async-flip-with-page-flip-events}:
- shard-kbl: [FAIL][37] ([i915#2521]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-kbl1/igt@kms_async_flips@async-flip-with-page-flip-events.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-kbl1/igt@kms_async_flips@async-flip-with-page-flip-events.html
* igt@kms_flip@plain-flip-fb-recreate@b-edp1:
- shard-skl: [FAIL][39] ([i915#2122]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl2/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl9/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
* igt@kms_flip_tiling@flip-changes-tiling-yf:
- shard-kbl: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-kbl1/igt@kms_flip_tiling@flip-changes-tiling-yf.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-kbl1/igt@kms_flip_tiling@flip-changes-tiling-yf.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][43] ([fdo#108145] / [i915#265]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [SKIP][45] ([fdo#109441]) -> [PASS][46] +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-iclb8/igt@kms_psr@psr2_cursor_blt.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
* igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
- shard-kbl: [INCOMPLETE][47] ([i915#155]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-kbl2/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [FAIL][49] ([i915#1515]) -> [WARN][50] ([i915#1515])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-iclb6/igt@i915_pm_rc6_residency@rc6-idle.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-iclb7/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-skl: [DMESG-FAIL][51] ([i915#1982]) -> [DMESG-WARN][52] ([i915#1982])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [DMESG-WARN][53] ([i915#1982]) -> [DMESG-FAIL][54] ([i915#1982])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl3/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-skl: [INCOMPLETE][55] ([i915#198]) -> [DMESG-WARN][56] ([i915#1982])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl8/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl5/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#177]: https://gitlab.freedesktop.org/drm/intel/issues/177
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2424]: https://gitlab.freedesktop.org/drm/intel/issues/2424
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2536]: https://gitlab.freedesktop.org/drm/intel/issues/2536
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9093 -> Patchwork_18620
CI-20190529: 20190529
CI_DRM_9093: 827ebff930c6340ed1c1c274909717525951c496 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5798: 430bad5a53c08125fbd48978ed6a66f61a33a40b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18620: 77fe9153f15371efa976b7ebdb10e9a1df31054e @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/index.html
[-- Attachment #1.2: Type: text/html, Size: 15886 bytes --]
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3)
2020-10-03 13:48 ` Imre Deak
@ 2020-10-04 6:12 ` Vudum, Lakshminarayana
0 siblings, 0 replies; 47+ messages in thread
From: Vudum, Lakshminarayana @ 2020-10-04 6:12 UTC (permalink / raw)
To: Deak, Imre, intel-gfx, Sarvela, Tomi P
Thanks for the pointers Imre. I have re-reported the results.
Lakshmi.
-----Original Message-----
From: Imre Deak <imre.deak@intel.com>
Sent: Saturday, October 3, 2020 6:49 AM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>; Sarvela, Tomi P <tomi.p.sarvela@intel.com>
Subject: Re: ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3)
Hi Lakshmi, Tomi,
On Sat, Oct 03, 2020 at 03:56:00AM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3)
> URL : https://patchwork.freedesktop.org/series/82173/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_9093_full -> Patchwork_18620_full
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_18620_full absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_18620_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_18620_full:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@gem_userptr_blits@unsync-unmap-cycles:
> - shard-skl: [PASS][1] -> [TIMEOUT][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl6/igt@gem_userptr_blits@unsync-unmap-cycles.html
> [2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl4/ig
> t@gem_userptr_blits@unsync-unmap-cycles.html
This looks like
https://gitlab.freedesktop.org/drm/intel/-/issues/2424
still happening at
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9090/shard-skl5/igt@gem_userptr_blits@sync-unmap-cycles.html
Could you update the filter to include sync-unmap-cycles as well?
> * igt@kms_flip@flip-vs-suspend@c-edp1:
> - shard-iclb: [PASS][3] -> [INCOMPLETE][4]
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-iclb3/igt@kms_flip@flip-vs-suspend@c-edp1.html
> [4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-iclb3/i
> gt@kms_flip@flip-vs-suspend@c-edp1.html
Looks like shard-iclb3 has a file system corruption, or just broken storage device/host:
<3>[ 240.012780] blk_update_request: I/O error, dev sda, sector 76863120 op 0x1:(WRITE) flags 0x800 phys_seg 10 prio class 0
This has been consistently happening now for a while on the shard-iclb3 machine leading to the same hang, see for instance https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9063/shard-iclb3/pstore7-1601302770_Panic_1.txt
Similar sporadic filesystem errors have been also happening on shard-iclb4.
I haven't seen any recent I/O errors on any of the other 7 shard-icl machines.
shard-iclb3/4 would probably need reinstall/new storage device/new host.
--Imre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
2020-10-03 0:18 ` [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming Imre Deak
@ 2020-10-05 20:08 ` Ville Syrjälä
2020-10-05 20:26 ` Imre Deak
2020-10-06 1:35 ` [Intel-gfx] [PATCH v3 " Imre Deak
1 sibling, 1 reply; 47+ messages in thread
From: Ville Syrjälä @ 2020-10-05 20:08 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Sat, Oct 03, 2020 at 03:18:42AM +0300, Imre Deak wrote:
> The BIOS of at least one ASUS-Z170M system with an SKL I have programs
> the 101b WRPLL PDIV divider value, which is the encoding for PDIV=7 with
> bit#0 incorrectly set.
>
> This happens with the
>
> "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9
>
> HDMI mode (scaled from a 1024x768 src fb) set by BIOS and the
>
> ref_clock=24000, dco_integer=383, dco_fraction=5802, pdiv=7, qdiv=1, kdiv=1
>
> WRPLL parameters (assuming PDIV=7 was the intended setting). This
> corresponds to 262749 PLL frequency/port clock.
>
> Later the driver sets the same mode for which it calculates the same
> dco_int/dco_frac/div WRPLL parameters (with the correct PDIV=7 encoding).
>
> Based on the above, let's assume that PDIV=7 was intended and the HW
> just ignores bit#0 in the PDIV register field for this setting, treating
> 100b and 101b encodings the same way.
>
> While at it add the MISSING_CASE() for the p0,p2 divider decodings.
>
> v2: (Ville)
> - Add a define for the incorrect divider value.
> - Emit only a debug message when detecting the incorrect divider value.
> - Use fallthrough from the incorrect divider value case.
> - Add the MISSING_CASE()s.
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 14 ++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index e08684e34078..61cb558c60d1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -1602,12 +1602,26 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
> case DPLL_CFGCR2_PDIV_3:
> p0 = 3;
> break;
> + default:
> + if (p0 == DPLL_CFGCR2_PDIV_7_INVALID)
Why not just 'case DPLL_CFGCR2_PDIV_7_INVALID:' ?
> + /*
> + * Incorrect ASUS-Z170M BIOS setting, the HW seems to ignore bit#0,
> + * handling it the same way as PDIV_7.
> + */
> + drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n");
> + else
> + MISSING_CASE(p0);
> +
> + fallthrough;
> case DPLL_CFGCR2_PDIV_7:
> p0 = 7;
> break;
> }
>
> switch (p2) {
> + default:
> + MISSING_CASE(p2);
> + fallthrough;
Is there a specific reason we fall through to the 5 and 7 cases for
bogus values?
> case DPLL_CFGCR2_KDIV_5:
> p2 = 5;
> break;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 88c215cf97d4..d911583526db 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10261,6 +10261,7 @@ enum skl_power_gate {
> #define DPLL_CFGCR2_PDIV_2 (1 << 2)
> #define DPLL_CFGCR2_PDIV_3 (2 << 2)
> #define DPLL_CFGCR2_PDIV_7 (4 << 2)
> +#define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2)
> #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
>
> #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
> --
> 2.25.1
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/5] drm/i915: Move the initial fastset commit check to encoder hooks
2020-10-03 1:07 ` [Intel-gfx] [PATCH v2 " Imre Deak
@ 2020-10-05 20:24 ` Ville Syrjälä
2020-10-05 20:34 ` Imre Deak
2020-10-05 21:53 ` [Intel-gfx] [PATCH v3 " Imre Deak
1 sibling, 1 reply; 47+ messages in thread
From: Ville Syrjälä @ 2020-10-05 20:24 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Sat, Oct 03, 2020 at 04:07:08AM +0300, Imre Deak wrote:
> Move the checks to decide whether a fastset is possible during the
> initial commit to an encoder hook. This check is really encoder specific
> and the next patch will also require this adding a DP encoder specific
> check.
>
> v2: Fix negated condition in gen11_dsi_initial_fastset_check().
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 14 +++++++++
> drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++++++
> drivers/gpu/drm/i915/display/intel_display.c | 29 +++++++++----------
> .../drm/i915/display/intel_display_types.h | 8 +++++
> drivers/gpu/drm/i915/display/intel_dp.c | 22 ++++++++++++++
> drivers/gpu/drm/i915/display/intel_dp.h | 3 ++
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 +++++++
> 7 files changed, 80 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index fe946a2e2082..4400e83f783f 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1668,6 +1668,19 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
> return ret;
> }
>
> +static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state)
> +{
> + if (crtc_state->dsc.compression_enable) {
> + drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n");
> + crtc_state->uapi.mode_changed = true;
> +
> + return false;
> + }
> +
> + return true;
> +}
> +
> static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
> {
> intel_encoder_destroy(encoder);
> @@ -1923,6 +1936,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
> encoder->update_pipe = intel_panel_update_backlight;
> encoder->compute_config = gen11_dsi_compute_config;
> encoder->get_hw_state = gen11_dsi_get_hw_state;
> + encoder->initial_fastset_check = gen11_dsi_initial_fastset_check;
> encoder->type = INTEL_OUTPUT_DSI;
> encoder->cloneable = 0;
> encoder->pipe_mask = ~0;
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index b4c520348b3b..4e54c55ec99f 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4564,6 +4564,15 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
> }
>
> +static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state)
> +{
> + if (intel_crtc_has_dp_encoder(crtc_state))
> + return intel_dp_initial_fastset_check(encoder, crtc_state);
> +
> + return true;
> +}
> +
> static enum intel_output_type
> intel_ddi_compute_output_type(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state,
> @@ -5173,6 +5182,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> encoder->update_pipe = intel_ddi_update_pipe;
> encoder->get_hw_state = intel_ddi_get_hw_state;
> encoder->get_config = intel_ddi_get_config;
> + encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
> encoder->suspend = intel_dp_encoder_suspend;
> encoder->get_power_domains = intel_ddi_get_power_domains;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 753f202ef6a0..31be63225b10 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -17951,6 +17951,8 @@ static int intel_initial_commit(struct drm_device *dev)
> }
>
> if (crtc_state->hw.active) {
> + struct intel_encoder *encoder;
> +
> /*
> * We've not yet detected sink capabilities
> * (audio,infoframes,etc.) and thus we don't want to
> @@ -17972,22 +17974,17 @@ static int intel_initial_commit(struct drm_device *dev)
> */
> crtc_state->uapi.color_mgmt_changed = true;
>
> - /*
> - * FIXME hack to force full modeset when DSC is being
> - * used.
> - *
> - * As long as we do not have full state readout and
> - * config comparison of crtc_state->dsc, we have no way
> - * to ensure reliable fastset. Remove once we have
> - * readout for DSC.
> - */
> - if (crtc_state->dsc.compression_enable) {
> - ret = drm_atomic_add_affected_connectors(state,
> - &crtc->base);
> - if (ret)
> - goto out;
> - crtc_state->uapi.mode_changed = true;
> - drm_dbg_kms(dev, "Force full modeset for DSC\n");
> + for_each_intel_encoder_mask(dev, encoder,
> + crtc_state->uapi.encoder_mask) {
> + if (encoder->initial_fastset_check &&
> + !encoder->initial_fastset_check(encoder, crtc_state)) {
> + ret = drm_atomic_add_affected_connectors(state,
> + &crtc->base);
I'd probably have stuffed that into the hook as well, but
I guess it can stay here too.
> + if (ret)
> + goto out;
> +
> + break;
The break seems wrong. Why wouldn't we want to check all encoders?
Not that there should be cloning with DP/DSI where we need the check,
but don't see what the point of the break is either way.
Otherwise
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> + }
> }
> }
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index d5dc18cb8c39..5297b2f08ff9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -187,6 +187,14 @@ struct intel_encoder {
> * be set correctly before calling this function. */
> void (*get_config)(struct intel_encoder *,
> struct intel_crtc_state *pipe_config);
> +
> + /*
> + * Optional hook, returning true if this encoder allows a fastset
> + * during the initial commit, false otherwise.
> + */
> + bool (*initial_fastset_check)(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state);
> +
> /*
> * Acquires the power domains needed for an active encoder during
> * hardware state readout.
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 7429597b57be..d33a3d9fdc3a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3703,6 +3703,27 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
> }
> }
>
> +bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> +
> + /*
> + * FIXME hack to force full modeset when DSC is being used.
> + *
> + * As long as we do not have full state readout and config comparison
> + * of crtc_state->dsc, we have no way to ensure reliable fastset.
> + * Remove once we have readout for DSC.
> + */
> + if (crtc_state->dsc.compression_enable) {
> + drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
> + crtc_state->uapi.mode_changed = true;
> + return false;
> + }
> +
> + return true;
> +}
> +
> static void intel_disable_dp(struct intel_atomic_state *state,
> struct intel_encoder *encoder,
> const struct intel_crtc_state *old_crtc_state,
> @@ -8057,6 +8078,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
> intel_encoder->compute_config = intel_dp_compute_config;
> intel_encoder->get_hw_state = intel_dp_get_hw_state;
> intel_encoder->get_config = intel_dp_get_config;
> + intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
> intel_encoder->update_pipe = intel_panel_update_backlight;
> intel_encoder->suspend = intel_dp_encoder_suspend;
> if (IS_CHERRYVIEW(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 66854aab9887..977585aea3c8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -141,4 +141,7 @@ void intel_ddi_update_pipe(struct intel_atomic_state *state,
> int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
> struct intel_connector *intel_connector);
>
> +bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state);
> +
> #endif /* __INTEL_DP_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 82f38c386dbd..e948aacbd4ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -591,6 +591,15 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
> intel_ddi_get_config(&dig_port->base, pipe_config);
> }
>
> +static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state)
> +{
> + struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
> + struct intel_digital_port *dig_port = intel_mst->primary;
> +
> + return intel_dp_initial_fastset_check(&dig_port->base, crtc_state);
> +}
> +
> static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector)
> {
> struct intel_connector *intel_connector = to_intel_connector(connector);
> @@ -897,6 +906,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe
> intel_encoder->enable = intel_mst_enable_dp;
> intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
> intel_encoder->get_config = intel_dp_mst_enc_get_config;
> + intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;
>
> return intel_mst;
>
> --
> 2.25.1
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH 3/5] drm/i915: Check for unsupported DP link rates during initial commit
2020-10-03 0:18 ` [Intel-gfx] [PATCH 3/5] drm/i915: Check for unsupported DP link rates during initial commit Imre Deak
@ 2020-10-05 20:25 ` Ville Syrjälä
0 siblings, 0 replies; 47+ messages in thread
From: Ville Syrjälä @ 2020-10-05 20:25 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Sat, Oct 03, 2020 at 03:18:44AM +0300, Imre Deak wrote:
> Some BIOSes set an unsupported/imprecise DP link rate (for instance on
> TGL A stepping). Make sure that we do an encoder recompute and a modeset
> in this case.
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index d33a3d9fdc3a..df5277c2b9ba 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3707,6 +3707,18 @@ bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + /*
> + * If BIOS has set an unsupported or non-standard link rate for some
> + * reason force an encoder recompute and full modeset.
> + */
> + if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
> + crtc_state->port_clock) < 0) {
> + drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n");
> + crtc_state->uapi.connectors_changed = true;
> + return false;
> + }
>
> /*
> * FIXME hack to force full modeset when DSC is being used.
> --
> 2.25.1
--
Ville Syrjälä
Intel
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
2020-10-05 20:08 ` Ville Syrjälä
@ 2020-10-05 20:26 ` Imre Deak
2020-10-05 23:37 ` Ville Syrjälä
0 siblings, 1 reply; 47+ messages in thread
From: Imre Deak @ 2020-10-05 20:26 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Oct 05, 2020 at 11:08:19PM +0300, Ville Syrjälä wrote:
> On Sat, Oct 03, 2020 at 03:18:42AM +0300, Imre Deak wrote:
> > The BIOS of at least one ASUS-Z170M system with an SKL I have programs
> > the 101b WRPLL PDIV divider value, which is the encoding for PDIV=7 with
> > bit#0 incorrectly set.
> >
> > This happens with the
> >
> > "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9
> >
> > HDMI mode (scaled from a 1024x768 src fb) set by BIOS and the
> >
> > ref_clock=24000, dco_integer=383, dco_fraction=5802, pdiv=7, qdiv=1, kdiv=1
> >
> > WRPLL parameters (assuming PDIV=7 was the intended setting). This
> > corresponds to 262749 PLL frequency/port clock.
> >
> > Later the driver sets the same mode for which it calculates the same
> > dco_int/dco_frac/div WRPLL parameters (with the correct PDIV=7 encoding).
> >
> > Based on the above, let's assume that PDIV=7 was intended and the HW
> > just ignores bit#0 in the PDIV register field for this setting, treating
> > 100b and 101b encodings the same way.
> >
> > While at it add the MISSING_CASE() for the p0,p2 divider decodings.
> >
> > v2: (Ville)
> > - Add a define for the incorrect divider value.
> > - Emit only a debug message when detecting the incorrect divider value.
> > - Use fallthrough from the incorrect divider value case.
> > - Add the MISSING_CASE()s.
> >
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 14 ++++++++++++++
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 2 files changed, 15 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index e08684e34078..61cb558c60d1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -1602,12 +1602,26 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
> > case DPLL_CFGCR2_PDIV_3:
> > p0 = 3;
> > break;
> > + default:
> > + if (p0 == DPLL_CFGCR2_PDIV_7_INVALID)
>
> Why not just 'case DPLL_CFGCR2_PDIV_7_INVALID:' ?
So we can use fallthrough for both this one and the default case.
>
> > + /*
> > + * Incorrect ASUS-Z170M BIOS setting, the HW seems to ignore bit#0,
> > + * handling it the same way as PDIV_7.
> > + */
> > + drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n");
> > + else
> > + MISSING_CASE(p0);
> > +
> > + fallthrough;
> > case DPLL_CFGCR2_PDIV_7:
> > p0 = 7;
> > break;
> > }
> >
> > switch (p2) {
> > + default:
> > + MISSING_CASE(p2);
> > + fallthrough;
>
> Is there a specific reason we fall through to the 5 and 7 cases for
> bogus values?
Just to default to dividers that result in the minimum PLL freq.
>
> > case DPLL_CFGCR2_KDIV_5:
> > p2 = 5;
> > break;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 88c215cf97d4..d911583526db 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -10261,6 +10261,7 @@ enum skl_power_gate {
> > #define DPLL_CFGCR2_PDIV_2 (1 << 2)
> > #define DPLL_CFGCR2_PDIV_3 (2 << 2)
> > #define DPLL_CFGCR2_PDIV_7 (4 << 2)
> > +#define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2)
> > #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
> >
> > #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
> > --
> > 2.25.1
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume
2020-10-03 0:18 ` [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume Imre Deak
@ 2020-10-05 20:30 ` Ville Syrjälä
2020-10-05 20:46 ` Imre Deak
2020-10-05 20:40 ` Ville Syrjälä
` (2 subsequent siblings)
3 siblings, 1 reply; 47+ messages in thread
From: Ville Syrjälä @ 2020-10-05 20:30 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Sat, Oct 03, 2020 at 03:18:45AM +0300, Imre Deak wrote:
> Atm, if a full modeset is performed during the initial modeset the link
> training will happen with uninitialized max DP rate and lane count. Make
> sure the corresponding encoder state is initialized by adding an encoder
> hook called during driver init and system resume.
>
> A better alternative would be to store all states in the CRTC state and
> make this state available for the link re-training code. Also instead of
> the DPCD read in the hook there should be really a proper sink HW
> readout in place. Both of these require a bigger rework, so for now opting
> for this minimal fix to make at least full initial modesets work.
>
> The patch is based on
> https://patchwork.freedesktop.org/patch/101473/?series=10354&rev=3
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 8 +++++
> drivers/gpu/drm/i915/display/intel_display.c | 4 +++
> .../drm/i915/display/intel_display_types.h | 7 +++++
> drivers/gpu/drm/i915/display/intel_dp.c | 31 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++++++
> 6 files changed, 62 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4e54c55ec99f..a0805260b224 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4564,6 +4564,13 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
> }
>
> +static void intel_ddi_sanitize_state(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + if (crtc_state && intel_crtc_has_dp_encoder(crtc_state))
> + intel_dp_sanitize_state(encoder, crtc_state);
> +}
I think we usually use 'sanitize' to mean "hw state is garbage -> must
take steps to sanitize it". This one is just filling in our intel_dp
sidechannel state. So the name isn't super consistnet with existing
practies.
> +
> static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state)
> {
> @@ -5182,6 +5189,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> encoder->update_pipe = intel_ddi_update_pipe;
> encoder->get_hw_state = intel_ddi_get_hw_state;
> encoder->get_config = intel_ddi_get_config;
> + encoder->sanitize_state = intel_ddi_sanitize_state;
> encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
> encoder->suspend = intel_dp_encoder_suspend;
> encoder->get_power_domains = intel_ddi_get_power_domains;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 31be63225b10..e61311ee8b8c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -18725,8 +18725,12 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
>
> encoder->base.crtc = &crtc->base;
> encoder->get_config(encoder, crtc_state);
> + if (encoder->sanitize_state)
> + encoder->sanitize_state(encoder, crtc_state);
> } else {
> encoder->base.crtc = NULL;
> + if (encoder->sanitize_state)
> + encoder->sanitize_state(encoder, NULL);
I wonder if we should even bother calling it in this case.
> }
>
> drm_dbg_kms(&dev_priv->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 5297b2f08ff9..b2b458144f5a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -188,6 +188,13 @@ struct intel_encoder {
> void (*get_config)(struct intel_encoder *,
> struct intel_crtc_state *pipe_config);
>
> + /*
> + * Optional hook called during init/resume to sanitize any state
> + * stored in the encoder (eg. DP link parameters).
> + */
> + void (*sanitize_state)(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state);
> +
> /*
> * Optional hook, returning true if this encoder allows a fastset
> * during the initial commit, false otherwise.
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index df5277c2b9ba..9b6fe3b3b5b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3703,6 +3703,36 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
> }
> }
>
> +static bool
> +intel_dp_get_dpcd(struct intel_dp *intel_dp);
> +
> +/**
> + * intel_dp_sanitize_state - sanitize the encoder state during init/resume
> + * @encoder: intel encoder to sanitize
> + * @crtc_state: state for the CRTC connected to the encoder
> + *
> + * Sanitize any state stored in the encoder during driver init and system
> + * resume.
> + */
> +void intel_dp_sanitize_state(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + if (!crtc_state)
> + return;
> +
> + /*
> + * Don't clobber DPCD if it's been already read out during output
> + * setup (eDP) or detect.
> + */
> + if (!memchr_inv(intel_dp->dpcd, 0, sizeof(intel_dp->dpcd)))
> + intel_dp_get_dpcd(intel_dp);
> +
> + intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
> + intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
> +}
> +
> bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state)
> {
> @@ -8090,6 +8120,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
> intel_encoder->compute_config = intel_dp_compute_config;
> intel_encoder->get_hw_state = intel_dp_get_hw_state;
> intel_encoder->get_config = intel_dp_get_config;
> + intel_encoder->sanitize_state = intel_dp_sanitize_state;
> intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
> intel_encoder->update_pipe = intel_panel_update_backlight;
> intel_encoder->suspend = intel_dp_encoder_suspend;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 977585aea3c8..1ab741e0be67 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -143,5 +143,7 @@ int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
>
> bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state);
> +void intel_dp_sanitize_state(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state);
>
> #endif /* __INTEL_DP_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index e948aacbd4ab..0831d1ee7978 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -591,6 +591,15 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
> intel_ddi_get_config(&dig_port->base, pipe_config);
> }
>
> +static void intel_dp_mst_sync_state(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
> + struct intel_digital_port *dig_port = intel_mst->primary;
> +
> + return intel_dp_sanitize_state(&dig_port->base, crtc_state);
> +}
> +
> static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state)
> {
> @@ -906,6 +915,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe
> intel_encoder->enable = intel_mst_enable_dp;
> intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
> intel_encoder->get_config = intel_dp_mst_enc_get_config;
> + intel_encoder->sanitize_state = intel_dp_mst_sync_state;
> intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;
>
> return intel_mst;
> --
> 2.25.1
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/5] drm/i915: Move the initial fastset commit check to encoder hooks
2020-10-05 20:24 ` Ville Syrjälä
@ 2020-10-05 20:34 ` Imre Deak
0 siblings, 0 replies; 47+ messages in thread
From: Imre Deak @ 2020-10-05 20:34 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Oct 05, 2020 at 11:24:56PM +0300, Ville Syrjälä wrote:
> On Sat, Oct 03, 2020 at 04:07:08AM +0300, Imre Deak wrote:
> > Move the checks to decide whether a fastset is possible during the
> > initial commit to an encoder hook. This check is really encoder specific
> > and the next patch will also require this adding a DP encoder specific
> > check.
> >
> > v2: Fix negated condition in gen11_dsi_initial_fastset_check().
> >
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/icl_dsi.c | 14 +++++++++
> > drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++++++
> > drivers/gpu/drm/i915/display/intel_display.c | 29 +++++++++----------
> > .../drm/i915/display/intel_display_types.h | 8 +++++
> > drivers/gpu/drm/i915/display/intel_dp.c | 22 ++++++++++++++
> > drivers/gpu/drm/i915/display/intel_dp.h | 3 ++
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 +++++++
> > 7 files changed, 80 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index fe946a2e2082..4400e83f783f 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -1668,6 +1668,19 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
> > return ret;
> > }
> >
> > +static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder,
> > + struct intel_crtc_state *crtc_state)
> > +{
> > + if (crtc_state->dsc.compression_enable) {
> > + drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n");
> > + crtc_state->uapi.mode_changed = true;
> > +
> > + return false;
> > + }
> > +
> > + return true;
> > +}
> > +
> > static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
> > {
> > intel_encoder_destroy(encoder);
> > @@ -1923,6 +1936,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
> > encoder->update_pipe = intel_panel_update_backlight;
> > encoder->compute_config = gen11_dsi_compute_config;
> > encoder->get_hw_state = gen11_dsi_get_hw_state;
> > + encoder->initial_fastset_check = gen11_dsi_initial_fastset_check;
> > encoder->type = INTEL_OUTPUT_DSI;
> > encoder->cloneable = 0;
> > encoder->pipe_mask = ~0;
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index b4c520348b3b..4e54c55ec99f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -4564,6 +4564,15 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> > intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
> > }
> >
> > +static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
> > + struct intel_crtc_state *crtc_state)
> > +{
> > + if (intel_crtc_has_dp_encoder(crtc_state))
> > + return intel_dp_initial_fastset_check(encoder, crtc_state);
> > +
> > + return true;
> > +}
> > +
> > static enum intel_output_type
> > intel_ddi_compute_output_type(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state,
> > @@ -5173,6 +5182,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> > encoder->update_pipe = intel_ddi_update_pipe;
> > encoder->get_hw_state = intel_ddi_get_hw_state;
> > encoder->get_config = intel_ddi_get_config;
> > + encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
> > encoder->suspend = intel_dp_encoder_suspend;
> > encoder->get_power_domains = intel_ddi_get_power_domains;
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 753f202ef6a0..31be63225b10 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -17951,6 +17951,8 @@ static int intel_initial_commit(struct drm_device *dev)
> > }
> >
> > if (crtc_state->hw.active) {
> > + struct intel_encoder *encoder;
> > +
> > /*
> > * We've not yet detected sink capabilities
> > * (audio,infoframes,etc.) and thus we don't want to
> > @@ -17972,22 +17974,17 @@ static int intel_initial_commit(struct drm_device *dev)
> > */
> > crtc_state->uapi.color_mgmt_changed = true;
> >
> > - /*
> > - * FIXME hack to force full modeset when DSC is being
> > - * used.
> > - *
> > - * As long as we do not have full state readout and
> > - * config comparison of crtc_state->dsc, we have no way
> > - * to ensure reliable fastset. Remove once we have
> > - * readout for DSC.
> > - */
> > - if (crtc_state->dsc.compression_enable) {
> > - ret = drm_atomic_add_affected_connectors(state,
> > - &crtc->base);
> > - if (ret)
> > - goto out;
> > - crtc_state->uapi.mode_changed = true;
> > - drm_dbg_kms(dev, "Force full modeset for DSC\n");
> > + for_each_intel_encoder_mask(dev, encoder,
> > + crtc_state->uapi.encoder_mask) {
> > + if (encoder->initial_fastset_check &&
> > + !encoder->initial_fastset_check(encoder, crtc_state)) {
> > + ret = drm_atomic_add_affected_connectors(state,
> > + &crtc->base);
>
> I'd probably have stuffed that into the hook as well, but
> I guess it can stay here too.
>
> > + if (ret)
> > + goto out;
> > +
> > + break;
>
> The break seems wrong. Why wouldn't we want to check all encoders?
> Not that there should be cloning with DP/DSI where we need the check,
> but don't see what the point of the break is either way.
Thought the only purpose would be to add all connectors to the state if
any encoder disallows fastset. But since an encoder can change
crtc_state, (probably setting either connector_changed or mode_changed)
agreed that the above break is bogus, will remove it.
>
> Otherwise
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> > + }
> > }
> > }
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index d5dc18cb8c39..5297b2f08ff9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -187,6 +187,14 @@ struct intel_encoder {
> > * be set correctly before calling this function. */
> > void (*get_config)(struct intel_encoder *,
> > struct intel_crtc_state *pipe_config);
> > +
> > + /*
> > + * Optional hook, returning true if this encoder allows a fastset
> > + * during the initial commit, false otherwise.
> > + */
> > + bool (*initial_fastset_check)(struct intel_encoder *encoder,
> > + struct intel_crtc_state *crtc_state);
> > +
> > /*
> > * Acquires the power domains needed for an active encoder during
> > * hardware state readout.
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 7429597b57be..d33a3d9fdc3a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -3703,6 +3703,27 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
> > }
> > }
> >
> > +bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> > + struct intel_crtc_state *crtc_state)
> > +{
> > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > +
> > + /*
> > + * FIXME hack to force full modeset when DSC is being used.
> > + *
> > + * As long as we do not have full state readout and config comparison
> > + * of crtc_state->dsc, we have no way to ensure reliable fastset.
> > + * Remove once we have readout for DSC.
> > + */
> > + if (crtc_state->dsc.compression_enable) {
> > + drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
> > + crtc_state->uapi.mode_changed = true;
> > + return false;
> > + }
> > +
> > + return true;
> > +}
> > +
> > static void intel_disable_dp(struct intel_atomic_state *state,
> > struct intel_encoder *encoder,
> > const struct intel_crtc_state *old_crtc_state,
> > @@ -8057,6 +8078,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
> > intel_encoder->compute_config = intel_dp_compute_config;
> > intel_encoder->get_hw_state = intel_dp_get_hw_state;
> > intel_encoder->get_config = intel_dp_get_config;
> > + intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
> > intel_encoder->update_pipe = intel_panel_update_backlight;
> > intel_encoder->suspend = intel_dp_encoder_suspend;
> > if (IS_CHERRYVIEW(dev_priv)) {
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> > index 66854aab9887..977585aea3c8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > @@ -141,4 +141,7 @@ void intel_ddi_update_pipe(struct intel_atomic_state *state,
> > int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
> > struct intel_connector *intel_connector);
> >
> > +bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> > + struct intel_crtc_state *crtc_state);
> > +
> > #endif /* __INTEL_DP_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index 82f38c386dbd..e948aacbd4ab 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -591,6 +591,15 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
> > intel_ddi_get_config(&dig_port->base, pipe_config);
> > }
> >
> > +static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,
> > + struct intel_crtc_state *crtc_state)
> > +{
> > + struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
> > + struct intel_digital_port *dig_port = intel_mst->primary;
> > +
> > + return intel_dp_initial_fastset_check(&dig_port->base, crtc_state);
> > +}
> > +
> > static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector)
> > {
> > struct intel_connector *intel_connector = to_intel_connector(connector);
> > @@ -897,6 +906,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe
> > intel_encoder->enable = intel_mst_enable_dp;
> > intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
> > intel_encoder->get_config = intel_dp_mst_enc_get_config;
> > + intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;
> >
> > return intel_mst;
> >
> > --
> > 2.25.1
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume
2020-10-03 0:18 ` [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume Imre Deak
2020-10-05 20:30 ` Ville Syrjälä
@ 2020-10-05 20:40 ` Ville Syrjälä
2020-10-05 20:57 ` Imre Deak
2020-10-05 20:51 ` Ville Syrjälä
2020-10-05 21:53 ` [Intel-gfx] [PATCH v2 " Imre Deak
3 siblings, 1 reply; 47+ messages in thread
From: Ville Syrjälä @ 2020-10-05 20:40 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Sat, Oct 03, 2020 at 03:18:45AM +0300, Imre Deak wrote:
> Atm, if a full modeset is performed during the initial modeset the link
> training will happen with uninitialized max DP rate and lane count. Make
> sure the corresponding encoder state is initialized by adding an encoder
> hook called during driver init and system resume.
>
> A better alternative would be to store all states in the CRTC state and
> make this state available for the link re-training code. Also instead of
> the DPCD read in the hook there should be really a proper sink HW
> readout in place. Both of these require a bigger rework, so for now opting
> for this minimal fix to make at least full initial modesets work.
>
> The patch is based on
> https://patchwork.freedesktop.org/patch/101473/?series=10354&rev=3
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 8 +++++
> drivers/gpu/drm/i915/display/intel_display.c | 4 +++
> .../drm/i915/display/intel_display_types.h | 7 +++++
> drivers/gpu/drm/i915/display/intel_dp.c | 31 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++++++
> 6 files changed, 62 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4e54c55ec99f..a0805260b224 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4564,6 +4564,13 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
> }
>
> +static void intel_ddi_sanitize_state(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + if (crtc_state && intel_crtc_has_dp_encoder(crtc_state))
> + intel_dp_sanitize_state(encoder, crtc_state);
> +}
> +
> static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state)
> {
> @@ -5182,6 +5189,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> encoder->update_pipe = intel_ddi_update_pipe;
> encoder->get_hw_state = intel_ddi_get_hw_state;
> encoder->get_config = intel_ddi_get_config;
> + encoder->sanitize_state = intel_ddi_sanitize_state;
> encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
> encoder->suspend = intel_dp_encoder_suspend;
> encoder->get_power_domains = intel_ddi_get_power_domains;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 31be63225b10..e61311ee8b8c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -18725,8 +18725,12 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
>
> encoder->base.crtc = &crtc->base;
> encoder->get_config(encoder, crtc_state);
> + if (encoder->sanitize_state)
> + encoder->sanitize_state(encoder, crtc_state);
> } else {
> encoder->base.crtc = NULL;
> + if (encoder->sanitize_state)
> + encoder->sanitize_state(encoder, NULL);
> }
>
> drm_dbg_kms(&dev_priv->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 5297b2f08ff9..b2b458144f5a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -188,6 +188,13 @@ struct intel_encoder {
> void (*get_config)(struct intel_encoder *,
> struct intel_crtc_state *pipe_config);
>
> + /*
> + * Optional hook called during init/resume to sanitize any state
> + * stored in the encoder (eg. DP link parameters).
> + */
> + void (*sanitize_state)(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state);
> +
> /*
> * Optional hook, returning true if this encoder allows a fastset
> * during the initial commit, false otherwise.
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index df5277c2b9ba..9b6fe3b3b5b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3703,6 +3703,36 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
> }
> }
>
> +static bool
> +intel_dp_get_dpcd(struct intel_dp *intel_dp);
> +
> +/**
> + * intel_dp_sanitize_state - sanitize the encoder state during init/resume
> + * @encoder: intel encoder to sanitize
> + * @crtc_state: state for the CRTC connected to the encoder
> + *
> + * Sanitize any state stored in the encoder during driver init and system
> + * resume.
> + */
> +void intel_dp_sanitize_state(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + if (!crtc_state)
> + return;
> +
> + /*
> + * Don't clobber DPCD if it's been already read out during output
> + * setup (eDP) or detect.
> + */
> + if (!memchr_inv(intel_dp->dpcd, 0, sizeof(intel_dp->dpcd)))
> + intel_dp_get_dpcd(intel_dp);
> +
> + intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
> + intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
> +}
> +
> bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state)
> {
> @@ -8090,6 +8120,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
> intel_encoder->compute_config = intel_dp_compute_config;
> intel_encoder->get_hw_state = intel_dp_get_hw_state;
> intel_encoder->get_config = intel_dp_get_config;
> + intel_encoder->sanitize_state = intel_dp_sanitize_state;
> intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
> intel_encoder->update_pipe = intel_panel_update_backlight;
> intel_encoder->suspend = intel_dp_encoder_suspend;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 977585aea3c8..1ab741e0be67 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -143,5 +143,7 @@ int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
>
> bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state);
> +void intel_dp_sanitize_state(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state);
>
> #endif /* __INTEL_DP_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index e948aacbd4ab..0831d1ee7978 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -591,6 +591,15 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
> intel_ddi_get_config(&dig_port->base, pipe_config);
> }
>
> +static void intel_dp_mst_sync_state(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
> + struct intel_digital_port *dig_port = intel_mst->primary;
> +
> + return intel_dp_sanitize_state(&dig_port->base, crtc_state);
> +}
MST readout is still totally missing, so not sure this part can
make any practical difference ever.
> +
> static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state)
> {
> @@ -906,6 +915,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe
> intel_encoder->enable = intel_mst_enable_dp;
> intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
> intel_encoder->get_config = intel_dp_mst_enc_get_config;
> + intel_encoder->sanitize_state = intel_dp_mst_sync_state;
> intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;
>
> return intel_mst;
> --
> 2.25.1
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume
2020-10-05 20:30 ` Ville Syrjälä
@ 2020-10-05 20:46 ` Imre Deak
2020-10-05 23:39 ` Ville Syrjälä
0 siblings, 1 reply; 47+ messages in thread
From: Imre Deak @ 2020-10-05 20:46 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Oct 05, 2020 at 11:30:55PM +0300, Ville Syrjälä wrote:
> On Sat, Oct 03, 2020 at 03:18:45AM +0300, Imre Deak wrote:
> > Atm, if a full modeset is performed during the initial modeset the link
> > training will happen with uninitialized max DP rate and lane count. Make
> > sure the corresponding encoder state is initialized by adding an encoder
> > hook called during driver init and system resume.
> >
> > A better alternative would be to store all states in the CRTC state and
> > make this state available for the link re-training code. Also instead of
> > the DPCD read in the hook there should be really a proper sink HW
> > readout in place. Both of these require a bigger rework, so for now opting
> > for this minimal fix to make at least full initial modesets work.
> >
> > The patch is based on
> > https://patchwork.freedesktop.org/patch/101473/?series=10354&rev=3
> >
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 8 +++++
> > drivers/gpu/drm/i915/display/intel_display.c | 4 +++
> > .../drm/i915/display/intel_display_types.h | 7 +++++
> > drivers/gpu/drm/i915/display/intel_dp.c | 31 +++++++++++++++++++
> > drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++++++
> > 6 files changed, 62 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 4e54c55ec99f..a0805260b224 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -4564,6 +4564,13 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> > intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
> > }
> >
> > +static void intel_ddi_sanitize_state(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state)
> > +{
> > + if (crtc_state && intel_crtc_has_dp_encoder(crtc_state))
> > + intel_dp_sanitize_state(encoder, crtc_state);
> > +}
>
> I think we usually use 'sanitize' to mean "hw state is garbage -> must
> take steps to sanitize it". This one is just filling in our intel_dp
> sidechannel state. So the name isn't super consistnet with existing
> practies.
It is called during init/resume time when encoders are sanitized as
well, but yea it's a separate step from HW readout. So I can rename it
for instance (back) to sync_state, or any better idea?
>
> > +
> > static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state)
> > {
> > @@ -5182,6 +5189,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> > encoder->update_pipe = intel_ddi_update_pipe;
> > encoder->get_hw_state = intel_ddi_get_hw_state;
> > encoder->get_config = intel_ddi_get_config;
> > + encoder->sanitize_state = intel_ddi_sanitize_state;
> > encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
> > encoder->suspend = intel_dp_encoder_suspend;
> > encoder->get_power_domains = intel_ddi_get_power_domains;
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 31be63225b10..e61311ee8b8c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -18725,8 +18725,12 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> >
> > encoder->base.crtc = &crtc->base;
> > encoder->get_config(encoder, crtc_state);
> > + if (encoder->sanitize_state)
> > + encoder->sanitize_state(encoder, crtc_state);
> > } else {
> > encoder->base.crtc = NULL;
> > + if (encoder->sanitize_state)
> > + encoder->sanitize_state(encoder, NULL);
>
> I wonder if we should even bother calling it in this case.
Yes, it would be just a nop atm, and can't think what state would need
to be updated, so will remove it.
>
> > }
> >
> > drm_dbg_kms(&dev_priv->drm,
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 5297b2f08ff9..b2b458144f5a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -188,6 +188,13 @@ struct intel_encoder {
> > void (*get_config)(struct intel_encoder *,
> > struct intel_crtc_state *pipe_config);
> >
> > + /*
> > + * Optional hook called during init/resume to sanitize any state
> > + * stored in the encoder (eg. DP link parameters).
> > + */
> > + void (*sanitize_state)(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state);
> > +
> > /*
> > * Optional hook, returning true if this encoder allows a fastset
> > * during the initial commit, false otherwise.
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index df5277c2b9ba..9b6fe3b3b5b2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -3703,6 +3703,36 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
> > }
> > }
> >
> > +static bool
> > +intel_dp_get_dpcd(struct intel_dp *intel_dp);
> > +
> > +/**
> > + * intel_dp_sanitize_state - sanitize the encoder state during init/resume
> > + * @encoder: intel encoder to sanitize
> > + * @crtc_state: state for the CRTC connected to the encoder
> > + *
> > + * Sanitize any state stored in the encoder during driver init and system
> > + * resume.
> > + */
> > +void intel_dp_sanitize_state(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state)
> > +{
> > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > +
> > + if (!crtc_state)
> > + return;
> > +
> > + /*
> > + * Don't clobber DPCD if it's been already read out during output
> > + * setup (eDP) or detect.
> > + */
> > + if (!memchr_inv(intel_dp->dpcd, 0, sizeof(intel_dp->dpcd)))
> > + intel_dp_get_dpcd(intel_dp);
> > +
> > + intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
> > + intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
> > +}
> > +
> > bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state)
> > {
> > @@ -8090,6 +8120,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
> > intel_encoder->compute_config = intel_dp_compute_config;
> > intel_encoder->get_hw_state = intel_dp_get_hw_state;
> > intel_encoder->get_config = intel_dp_get_config;
> > + intel_encoder->sanitize_state = intel_dp_sanitize_state;
> > intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
> > intel_encoder->update_pipe = intel_panel_update_backlight;
> > intel_encoder->suspend = intel_dp_encoder_suspend;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> > index 977585aea3c8..1ab741e0be67 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > @@ -143,5 +143,7 @@ int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
> >
> > bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state);
> > +void intel_dp_sanitize_state(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state);
> >
> > #endif /* __INTEL_DP_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index e948aacbd4ab..0831d1ee7978 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -591,6 +591,15 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
> > intel_ddi_get_config(&dig_port->base, pipe_config);
> > }
> >
> > +static void intel_dp_mst_sync_state(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state)
> > +{
> > + struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
> > + struct intel_digital_port *dig_port = intel_mst->primary;
> > +
> > + return intel_dp_sanitize_state(&dig_port->base, crtc_state);
> > +}
> > +
> > static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state)
> > {
> > @@ -906,6 +915,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe
> > intel_encoder->enable = intel_mst_enable_dp;
> > intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
> > intel_encoder->get_config = intel_dp_mst_enc_get_config;
> > + intel_encoder->sanitize_state = intel_dp_mst_sync_state;
> > intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;
> >
> > return intel_mst;
> > --
> > 2.25.1
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume
2020-10-03 0:18 ` [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume Imre Deak
2020-10-05 20:30 ` Ville Syrjälä
2020-10-05 20:40 ` Ville Syrjälä
@ 2020-10-05 20:51 ` Ville Syrjälä
2020-10-05 23:00 ` Imre Deak
2020-10-05 21:53 ` [Intel-gfx] [PATCH v2 " Imre Deak
3 siblings, 1 reply; 47+ messages in thread
From: Ville Syrjälä @ 2020-10-05 20:51 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Sat, Oct 03, 2020 at 03:18:45AM +0300, Imre Deak wrote:
> Atm, if a full modeset is performed during the initial modeset the link
> training will happen with uninitialized max DP rate and lane count. Make
> sure the corresponding encoder state is initialized by adding an encoder
> hook called during driver init and system resume.
>
> A better alternative would be to store all states in the CRTC state and
> make this state available for the link re-training code. Also instead of
> the DPCD read in the hook there should be really a proper sink HW
> readout in place. Both of these require a bigger rework, so for now opting
> for this minimal fix to make at least full initial modesets work.
>
> The patch is based on
> https://patchwork.freedesktop.org/patch/101473/?series=10354&rev=3
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 8 +++++
> drivers/gpu/drm/i915/display/intel_display.c | 4 +++
> .../drm/i915/display/intel_display_types.h | 7 +++++
> drivers/gpu/drm/i915/display/intel_dp.c | 31 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++++++
> 6 files changed, 62 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4e54c55ec99f..a0805260b224 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4564,6 +4564,13 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
> }
>
> +static void intel_ddi_sanitize_state(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + if (crtc_state && intel_crtc_has_dp_encoder(crtc_state))
> + intel_dp_sanitize_state(encoder, crtc_state);
> +}
> +
> static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state)
> {
> @@ -5182,6 +5189,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> encoder->update_pipe = intel_ddi_update_pipe;
> encoder->get_hw_state = intel_ddi_get_hw_state;
> encoder->get_config = intel_ddi_get_config;
> + encoder->sanitize_state = intel_ddi_sanitize_state;
> encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
> encoder->suspend = intel_dp_encoder_suspend;
> encoder->get_power_domains = intel_ddi_get_power_domains;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 31be63225b10..e61311ee8b8c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -18725,8 +18725,12 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
>
> encoder->base.crtc = &crtc->base;
> encoder->get_config(encoder, crtc_state);
> + if (encoder->sanitize_state)
> + encoder->sanitize_state(encoder, crtc_state);
> } else {
> encoder->base.crtc = NULL;
> + if (encoder->sanitize_state)
> + encoder->sanitize_state(encoder, NULL);
> }
>
> drm_dbg_kms(&dev_priv->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 5297b2f08ff9..b2b458144f5a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -188,6 +188,13 @@ struct intel_encoder {
> void (*get_config)(struct intel_encoder *,
> struct intel_crtc_state *pipe_config);
>
> + /*
> + * Optional hook called during init/resume to sanitize any state
> + * stored in the encoder (eg. DP link parameters).
> + */
> + void (*sanitize_state)(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state);
> +
> /*
> * Optional hook, returning true if this encoder allows a fastset
> * during the initial commit, false otherwise.
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index df5277c2b9ba..9b6fe3b3b5b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3703,6 +3703,36 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
> }
> }
>
> +static bool
> +intel_dp_get_dpcd(struct intel_dp *intel_dp);
> +
> +/**
> + * intel_dp_sanitize_state - sanitize the encoder state during init/resume
> + * @encoder: intel encoder to sanitize
> + * @crtc_state: state for the CRTC connected to the encoder
> + *
> + * Sanitize any state stored in the encoder during driver init and system
> + * resume.
> + */
> +void intel_dp_sanitize_state(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + if (!crtc_state)
> + return;
> +
> + /*
> + * Don't clobber DPCD if it's been already read out during output
> + * setup (eDP) or detect.
> + */
> + if (!memchr_inv(intel_dp->dpcd, 0, sizeof(intel_dp->dpcd)))
> + intel_dp_get_dpcd(intel_dp);
Oh, and I'd probably just have checked DPCD_REV !=0 here. That's what we
already do somewhere else IIRC.
> +
> + intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
> + intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
> +}
> +
> bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state)
> {
> @@ -8090,6 +8120,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
> intel_encoder->compute_config = intel_dp_compute_config;
> intel_encoder->get_hw_state = intel_dp_get_hw_state;
> intel_encoder->get_config = intel_dp_get_config;
> + intel_encoder->sanitize_state = intel_dp_sanitize_state;
> intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
> intel_encoder->update_pipe = intel_panel_update_backlight;
> intel_encoder->suspend = intel_dp_encoder_suspend;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 977585aea3c8..1ab741e0be67 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -143,5 +143,7 @@ int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
>
> bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state);
> +void intel_dp_sanitize_state(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state);
>
> #endif /* __INTEL_DP_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index e948aacbd4ab..0831d1ee7978 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -591,6 +591,15 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
> intel_ddi_get_config(&dig_port->base, pipe_config);
> }
>
> +static void intel_dp_mst_sync_state(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
> + struct intel_digital_port *dig_port = intel_mst->primary;
> +
> + return intel_dp_sanitize_state(&dig_port->base, crtc_state);
> +}
> +
> static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state)
> {
> @@ -906,6 +915,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe
> intel_encoder->enable = intel_mst_enable_dp;
> intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
> intel_encoder->get_config = intel_dp_mst_enc_get_config;
> + intel_encoder->sanitize_state = intel_dp_mst_sync_state;
> intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;
>
> return intel_mst;
> --
> 2.25.1
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume
2020-10-05 20:40 ` Ville Syrjälä
@ 2020-10-05 20:57 ` Imre Deak
0 siblings, 0 replies; 47+ messages in thread
From: Imre Deak @ 2020-10-05 20:57 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Oct 05, 2020 at 11:40:44PM +0300, Ville Syrjälä wrote:
> On Sat, Oct 03, 2020 at 03:18:45AM +0300, Imre Deak wrote:
> > Atm, if a full modeset is performed during the initial modeset the link
> > training will happen with uninitialized max DP rate and lane count. Make
> > sure the corresponding encoder state is initialized by adding an encoder
> > hook called during driver init and system resume.
> >
> > A better alternative would be to store all states in the CRTC state and
> > make this state available for the link re-training code. Also instead of
> > the DPCD read in the hook there should be really a proper sink HW
> > readout in place. Both of these require a bigger rework, so for now opting
> > for this minimal fix to make at least full initial modesets work.
> >
> > The patch is based on
> > https://patchwork.freedesktop.org/patch/101473/?series=10354&rev=3
> >
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 8 +++++
> > drivers/gpu/drm/i915/display/intel_display.c | 4 +++
> > .../drm/i915/display/intel_display_types.h | 7 +++++
> > drivers/gpu/drm/i915/display/intel_dp.c | 31 +++++++++++++++++++
> > drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++++++
> > 6 files changed, 62 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 4e54c55ec99f..a0805260b224 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -4564,6 +4564,13 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> > intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
> > }
> >
> > +static void intel_ddi_sanitize_state(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state)
> > +{
> > + if (crtc_state && intel_crtc_has_dp_encoder(crtc_state))
> > + intel_dp_sanitize_state(encoder, crtc_state);
> > +}
> > +
> > static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state)
> > {
> > @@ -5182,6 +5189,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> > encoder->update_pipe = intel_ddi_update_pipe;
> > encoder->get_hw_state = intel_ddi_get_hw_state;
> > encoder->get_config = intel_ddi_get_config;
> > + encoder->sanitize_state = intel_ddi_sanitize_state;
> > encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
> > encoder->suspend = intel_dp_encoder_suspend;
> > encoder->get_power_domains = intel_ddi_get_power_domains;
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 31be63225b10..e61311ee8b8c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -18725,8 +18725,12 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> >
> > encoder->base.crtc = &crtc->base;
> > encoder->get_config(encoder, crtc_state);
> > + if (encoder->sanitize_state)
> > + encoder->sanitize_state(encoder, crtc_state);
> > } else {
> > encoder->base.crtc = NULL;
> > + if (encoder->sanitize_state)
> > + encoder->sanitize_state(encoder, NULL);
> > }
> >
> > drm_dbg_kms(&dev_priv->drm,
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 5297b2f08ff9..b2b458144f5a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -188,6 +188,13 @@ struct intel_encoder {
> > void (*get_config)(struct intel_encoder *,
> > struct intel_crtc_state *pipe_config);
> >
> > + /*
> > + * Optional hook called during init/resume to sanitize any state
> > + * stored in the encoder (eg. DP link parameters).
> > + */
> > + void (*sanitize_state)(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state);
> > +
> > /*
> > * Optional hook, returning true if this encoder allows a fastset
> > * during the initial commit, false otherwise.
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index df5277c2b9ba..9b6fe3b3b5b2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -3703,6 +3703,36 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
> > }
> > }
> >
> > +static bool
> > +intel_dp_get_dpcd(struct intel_dp *intel_dp);
> > +
> > +/**
> > + * intel_dp_sanitize_state - sanitize the encoder state during init/resume
> > + * @encoder: intel encoder to sanitize
> > + * @crtc_state: state for the CRTC connected to the encoder
> > + *
> > + * Sanitize any state stored in the encoder during driver init and system
> > + * resume.
> > + */
> > +void intel_dp_sanitize_state(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state)
> > +{
> > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > +
> > + if (!crtc_state)
> > + return;
> > +
> > + /*
> > + * Don't clobber DPCD if it's been already read out during output
> > + * setup (eDP) or detect.
> > + */
> > + if (!memchr_inv(intel_dp->dpcd, 0, sizeof(intel_dp->dpcd)))
> > + intel_dp_get_dpcd(intel_dp);
> > +
> > + intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
> > + intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
> > +}
> > +
> > bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state)
> > {
> > @@ -8090,6 +8120,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
> > intel_encoder->compute_config = intel_dp_compute_config;
> > intel_encoder->get_hw_state = intel_dp_get_hw_state;
> > intel_encoder->get_config = intel_dp_get_config;
> > + intel_encoder->sanitize_state = intel_dp_sanitize_state;
> > intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
> > intel_encoder->update_pipe = intel_panel_update_backlight;
> > intel_encoder->suspend = intel_dp_encoder_suspend;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> > index 977585aea3c8..1ab741e0be67 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > @@ -143,5 +143,7 @@ int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
> >
> > bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state);
> > +void intel_dp_sanitize_state(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state);
> >
> > #endif /* __INTEL_DP_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index e948aacbd4ab..0831d1ee7978 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -591,6 +591,15 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
> > intel_ddi_get_config(&dig_port->base, pipe_config);
> > }
> >
> > +static void intel_dp_mst_sync_state(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state)
> > +{
> > + struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
> > + struct intel_digital_port *dig_port = intel_mst->primary;
> > +
> > + return intel_dp_sanitize_state(&dig_port->base, crtc_state);
> > +}
>
> MST readout is still totally missing, so not sure this part can
> make any practical difference ever.
No actual use case atm, I added this only for consistency since BIOS
could misconfigure port_clock on an MST port as well, which would need
at least the link params to be inited correctly. But I realize now we
would not run these hooks during driver init, so can drop it for MST.
> >
> > return intel_mst;
> > --
> > 2.25.1
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH v3 2/5] drm/i915: Move the initial fastset commit check to encoder hooks
2020-10-03 1:07 ` [Intel-gfx] [PATCH v2 " Imre Deak
2020-10-05 20:24 ` Ville Syrjälä
@ 2020-10-05 21:53 ` Imre Deak
2020-10-06 9:42 ` Jani Nikula
1 sibling, 1 reply; 47+ messages in thread
From: Imre Deak @ 2020-10-05 21:53 UTC (permalink / raw)
To: intel-gfx
Move the checks to decide whether a fastset is possible during the
initial commit to an encoder hook. This check is really encoder specific
and the next patch will also require this adding a DP encoder specific
check.
v2: Fix negated condition in gen11_dsi_initial_fastset_check().
v3: Make sure to call the hook for all encoders on the crtc. (Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 14 ++++++++++
drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++++++
drivers/gpu/drm/i915/display/intel_display.c | 27 ++++++++-----------
.../drm/i915/display/intel_display_types.h | 8 ++++++
drivers/gpu/drm/i915/display/intel_dp.c | 22 +++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 3 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 +++++++
7 files changed, 78 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index fe946a2e2082..4400e83f783f 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1668,6 +1668,19 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
return ret;
}
+static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ if (crtc_state->dsc.compression_enable) {
+ drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n");
+ crtc_state->uapi.mode_changed = true;
+
+ return false;
+ }
+
+ return true;
+}
+
static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
{
intel_encoder_destroy(encoder);
@@ -1923,6 +1936,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
encoder->update_pipe = intel_panel_update_backlight;
encoder->compute_config = gen11_dsi_compute_config;
encoder->get_hw_state = gen11_dsi_get_hw_state;
+ encoder->initial_fastset_check = gen11_dsi_initial_fastset_check;
encoder->type = INTEL_OUTPUT_DSI;
encoder->cloneable = 0;
encoder->pipe_mask = ~0;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b4c520348b3b..4e54c55ec99f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4564,6 +4564,15 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
}
+static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ if (intel_crtc_has_dp_encoder(crtc_state))
+ return intel_dp_initial_fastset_check(encoder, crtc_state);
+
+ return true;
+}
+
static enum intel_output_type
intel_ddi_compute_output_type(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
@@ -5173,6 +5182,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder->update_pipe = intel_ddi_update_pipe;
encoder->get_hw_state = intel_ddi_get_hw_state;
encoder->get_config = intel_ddi_get_config;
+ encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
encoder->suspend = intel_dp_encoder_suspend;
encoder->get_power_domains = intel_ddi_get_power_domains;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 753f202ef6a0..755b83d47f9c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17951,6 +17951,8 @@ static int intel_initial_commit(struct drm_device *dev)
}
if (crtc_state->hw.active) {
+ struct intel_encoder *encoder;
+
/*
* We've not yet detected sink capabilities
* (audio,infoframes,etc.) and thus we don't want to
@@ -17972,22 +17974,15 @@ static int intel_initial_commit(struct drm_device *dev)
*/
crtc_state->uapi.color_mgmt_changed = true;
- /*
- * FIXME hack to force full modeset when DSC is being
- * used.
- *
- * As long as we do not have full state readout and
- * config comparison of crtc_state->dsc, we have no way
- * to ensure reliable fastset. Remove once we have
- * readout for DSC.
- */
- if (crtc_state->dsc.compression_enable) {
- ret = drm_atomic_add_affected_connectors(state,
- &crtc->base);
- if (ret)
- goto out;
- crtc_state->uapi.mode_changed = true;
- drm_dbg_kms(dev, "Force full modeset for DSC\n");
+ for_each_intel_encoder_mask(dev, encoder,
+ crtc_state->uapi.encoder_mask) {
+ if (encoder->initial_fastset_check &&
+ !encoder->initial_fastset_check(encoder, crtc_state)) {
+ ret = drm_atomic_add_affected_connectors(state,
+ &crtc->base);
+ if (ret)
+ goto out;
+ }
}
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index d5dc18cb8c39..5297b2f08ff9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -187,6 +187,14 @@ struct intel_encoder {
* be set correctly before calling this function. */
void (*get_config)(struct intel_encoder *,
struct intel_crtc_state *pipe_config);
+
+ /*
+ * Optional hook, returning true if this encoder allows a fastset
+ * during the initial commit, false otherwise.
+ */
+ bool (*initial_fastset_check)(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state);
+
/*
* Acquires the power domains needed for an active encoder during
* hardware state readout.
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7429597b57be..d33a3d9fdc3a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3703,6 +3703,27 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
}
}
+bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+ /*
+ * FIXME hack to force full modeset when DSC is being used.
+ *
+ * As long as we do not have full state readout and config comparison
+ * of crtc_state->dsc, we have no way to ensure reliable fastset.
+ * Remove once we have readout for DSC.
+ */
+ if (crtc_state->dsc.compression_enable) {
+ drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
+ crtc_state->uapi.mode_changed = true;
+ return false;
+ }
+
+ return true;
+}
+
static void intel_disable_dp(struct intel_atomic_state *state,
struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state,
@@ -8057,6 +8078,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
intel_encoder->compute_config = intel_dp_compute_config;
intel_encoder->get_hw_state = intel_dp_get_hw_state;
intel_encoder->get_config = intel_dp_get_config;
+ intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
intel_encoder->update_pipe = intel_panel_update_backlight;
intel_encoder->suspend = intel_dp_encoder_suspend;
if (IS_CHERRYVIEW(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 66854aab9887..977585aea3c8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -141,4 +141,7 @@ void intel_ddi_update_pipe(struct intel_atomic_state *state,
int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
struct intel_connector *intel_connector);
+bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state);
+
#endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 82f38c386dbd..e948aacbd4ab 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -591,6 +591,15 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
intel_ddi_get_config(&dig_port->base, pipe_config);
}
+static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
+ struct intel_digital_port *dig_port = intel_mst->primary;
+
+ return intel_dp_initial_fastset_check(&dig_port->base, crtc_state);
+}
+
static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector)
{
struct intel_connector *intel_connector = to_intel_connector(connector);
@@ -897,6 +906,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe
intel_encoder->enable = intel_mst_enable_dp;
intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
intel_encoder->get_config = intel_dp_mst_enc_get_config;
+ intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;
return intel_mst;
--
2.25.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH v2 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume
2020-10-03 0:18 ` [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume Imre Deak
` (2 preceding siblings ...)
2020-10-05 20:51 ` Ville Syrjälä
@ 2020-10-05 21:53 ` Imre Deak
2020-10-05 23:01 ` [Intel-gfx] [PATCH v3 " Imre Deak
3 siblings, 1 reply; 47+ messages in thread
From: Imre Deak @ 2020-10-05 21:53 UTC (permalink / raw)
To: intel-gfx
Atm, if a full modeset is performed during the initial modeset the link
training will happen with uninitialized max DP rate and lane count. Make
sure the corresponding encoder state is initialized by adding an encoder
hook called during driver init and system resume.
A better alternative would be to store all states in the CRTC state and
make this state available for the link re-training code. Also instead of
the DPCD read in the hook there should be really a proper sink HW
readout in place. Both of these require a bigger rework, so for now opting
for this minimal fix to make at least full initial modesets work.
The patch is based on
https://patchwork.freedesktop.org/patch/101473/?series=10354&rev=3
v2: (Ville)
- s/sanitize_state/sync_state/
- No point in calling the hook when CRTC is disabled, remove the call.
- No point in calling the hook for MST, remove it.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++++
drivers/gpu/drm/i915/display/intel_display.c | 2 ++
.../drm/i915/display/intel_display_types.h | 7 +++++
drivers/gpu/drm/i915/display/intel_dp.c | 28 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
5 files changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4e54c55ec99f..6f7bd67732f2 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4564,6 +4564,13 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
}
+static void intel_ddi_sync_state(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ if (intel_crtc_has_dp_encoder(crtc_state))
+ intel_dp_sync_state(encoder, crtc_state);
+}
+
static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
@@ -5182,6 +5189,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder->update_pipe = intel_ddi_update_pipe;
encoder->get_hw_state = intel_ddi_get_hw_state;
encoder->get_config = intel_ddi_get_config;
+ encoder->sync_state = intel_ddi_sync_state;
encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
encoder->suspend = intel_dp_encoder_suspend;
encoder->get_power_domains = intel_ddi_get_power_domains;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 755b83d47f9c..907e1d155443 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -18723,6 +18723,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
encoder->base.crtc = &crtc->base;
encoder->get_config(encoder, crtc_state);
+ if (encoder->sync_state)
+ encoder->sync_state(encoder, crtc_state);
} else {
encoder->base.crtc = NULL;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 5297b2f08ff9..65ae2070576f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -188,6 +188,13 @@ struct intel_encoder {
void (*get_config)(struct intel_encoder *,
struct intel_crtc_state *pipe_config);
+ /*
+ * Optional hook called during init/resume to sync any state
+ * stored in the encoder (eg. DP link parameters) wrt. the HW state.
+ */
+ void (*sync_state)(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
+
/*
* Optional hook, returning true if this encoder allows a fastset
* during the initial commit, false otherwise.
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index df5277c2b9ba..54328eba473c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3703,6 +3703,33 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
}
}
+static bool
+intel_dp_get_dpcd(struct intel_dp *intel_dp);
+
+/**
+ * intel_dp_sync_state - sync the encoder state during init/resume
+ * @encoder: intel encoder to sync
+ * @crtc_state: state for the CRTC connected to the encoder
+ *
+ * Sync any state stored in the encoder wrt. HW state during driver init
+ * and system resume.
+ */
+void intel_dp_sync_state(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ /*
+ * Don't clobber DPCD if it's been already read out during output
+ * setup (eDP) or detect.
+ */
+ if (!memchr_inv(intel_dp->dpcd, 0, sizeof(intel_dp->dpcd)))
+ intel_dp_get_dpcd(intel_dp);
+
+ intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
+ intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
+}
+
bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
@@ -8090,6 +8117,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
intel_encoder->compute_config = intel_dp_compute_config;
intel_encoder->get_hw_state = intel_dp_get_hw_state;
intel_encoder->get_config = intel_dp_get_config;
+ intel_encoder->sync_state = intel_dp_sync_state;
intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
intel_encoder->update_pipe = intel_panel_update_backlight;
intel_encoder->suspend = intel_dp_encoder_suspend;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 977585aea3c8..6c201377fdc0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -143,5 +143,7 @@ int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state);
+void intel_dp_sync_state(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
#endif /* __INTEL_DP_H__ */
--
2.25.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume
2020-10-05 20:51 ` Ville Syrjälä
@ 2020-10-05 23:00 ` Imre Deak
0 siblings, 0 replies; 47+ messages in thread
From: Imre Deak @ 2020-10-05 23:00 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Oct 05, 2020 at 11:51:02PM +0300, Ville Syrjälä wrote:
> On Sat, Oct 03, 2020 at 03:18:45AM +0300, Imre Deak wrote:
> > Atm, if a full modeset is performed during the initial modeset the link
> > training will happen with uninitialized max DP rate and lane count. Make
> > sure the corresponding encoder state is initialized by adding an encoder
> > hook called during driver init and system resume.
> >
> > A better alternative would be to store all states in the CRTC state and
> > make this state available for the link re-training code. Also instead of
> > the DPCD read in the hook there should be really a proper sink HW
> > readout in place. Both of these require a bigger rework, so for now opting
> > for this minimal fix to make at least full initial modesets work.
> >
> > The patch is based on
> > https://patchwork.freedesktop.org/patch/101473/?series=10354&rev=3
> >
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 8 +++++
> > drivers/gpu/drm/i915/display/intel_display.c | 4 +++
> > .../drm/i915/display/intel_display_types.h | 7 +++++
> > drivers/gpu/drm/i915/display/intel_dp.c | 31 +++++++++++++++++++
> > drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++++++
> > 6 files changed, 62 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 4e54c55ec99f..a0805260b224 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -4564,6 +4564,13 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> > intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
> > }
> >
> > +static void intel_ddi_sanitize_state(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state)
> > +{
> > + if (crtc_state && intel_crtc_has_dp_encoder(crtc_state))
> > + intel_dp_sanitize_state(encoder, crtc_state);
> > +}
> > +
> > static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state)
> > {
> > @@ -5182,6 +5189,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> > encoder->update_pipe = intel_ddi_update_pipe;
> > encoder->get_hw_state = intel_ddi_get_hw_state;
> > encoder->get_config = intel_ddi_get_config;
> > + encoder->sanitize_state = intel_ddi_sanitize_state;
> > encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
> > encoder->suspend = intel_dp_encoder_suspend;
> > encoder->get_power_domains = intel_ddi_get_power_domains;
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 31be63225b10..e61311ee8b8c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -18725,8 +18725,12 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> >
> > encoder->base.crtc = &crtc->base;
> > encoder->get_config(encoder, crtc_state);
> > + if (encoder->sanitize_state)
> > + encoder->sanitize_state(encoder, crtc_state);
> > } else {
> > encoder->base.crtc = NULL;
> > + if (encoder->sanitize_state)
> > + encoder->sanitize_state(encoder, NULL);
> > }
> >
> > drm_dbg_kms(&dev_priv->drm,
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 5297b2f08ff9..b2b458144f5a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -188,6 +188,13 @@ struct intel_encoder {
> > void (*get_config)(struct intel_encoder *,
> > struct intel_crtc_state *pipe_config);
> >
> > + /*
> > + * Optional hook called during init/resume to sanitize any state
> > + * stored in the encoder (eg. DP link parameters).
> > + */
> > + void (*sanitize_state)(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state);
> > +
> > /*
> > * Optional hook, returning true if this encoder allows a fastset
> > * during the initial commit, false otherwise.
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index df5277c2b9ba..9b6fe3b3b5b2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -3703,6 +3703,36 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
> > }
> > }
> >
> > +static bool
> > +intel_dp_get_dpcd(struct intel_dp *intel_dp);
> > +
> > +/**
> > + * intel_dp_sanitize_state - sanitize the encoder state during init/resume
> > + * @encoder: intel encoder to sanitize
> > + * @crtc_state: state for the CRTC connected to the encoder
> > + *
> > + * Sanitize any state stored in the encoder during driver init and system
> > + * resume.
> > + */
> > +void intel_dp_sanitize_state(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state)
> > +{
> > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > +
> > + if (!crtc_state)
> > + return;
> > +
> > + /*
> > + * Don't clobber DPCD if it's been already read out during output
> > + * setup (eDP) or detect.
> > + */
> > + if (!memchr_inv(intel_dp->dpcd, 0, sizeof(intel_dp->dpcd)))
> > + intel_dp_get_dpcd(intel_dp);
>
> Oh, and I'd probably just have checked DPCD_REV !=0 here. That's what we
> already do somewhere else IIRC.
Ok.
>
> > +
> > + intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
> > + intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
> > +}
> > +
> > bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state)
> > {
> > @@ -8090,6 +8120,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
> > intel_encoder->compute_config = intel_dp_compute_config;
> > intel_encoder->get_hw_state = intel_dp_get_hw_state;
> > intel_encoder->get_config = intel_dp_get_config;
> > + intel_encoder->sanitize_state = intel_dp_sanitize_state;
> > intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
> > intel_encoder->update_pipe = intel_panel_update_backlight;
> > intel_encoder->suspend = intel_dp_encoder_suspend;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> > index 977585aea3c8..1ab741e0be67 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > @@ -143,5 +143,7 @@ int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
> >
> > bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state);
> > +void intel_dp_sanitize_state(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state);
> >
> > #endif /* __INTEL_DP_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index e948aacbd4ab..0831d1ee7978 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -591,6 +591,15 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
> > intel_ddi_get_config(&dig_port->base, pipe_config);
> > }
> >
> > +static void intel_dp_mst_sync_state(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state)
> > +{
> > + struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
> > + struct intel_digital_port *dig_port = intel_mst->primary;
> > +
> > + return intel_dp_sanitize_state(&dig_port->base, crtc_state);
> > +}
> > +
> > static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state)
> > {
> > @@ -906,6 +915,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe
> > intel_encoder->enable = intel_mst_enable_dp;
> > intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
> > intel_encoder->get_config = intel_dp_mst_enc_get_config;
> > + intel_encoder->sanitize_state = intel_dp_mst_sync_state;
> > intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;
> >
> > return intel_mst;
> > --
> > 2.25.1
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH v3 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume
2020-10-05 21:53 ` [Intel-gfx] [PATCH v2 " Imre Deak
@ 2020-10-05 23:01 ` Imre Deak
2020-10-06 8:58 ` Ville Syrjälä
0 siblings, 1 reply; 47+ messages in thread
From: Imre Deak @ 2020-10-05 23:01 UTC (permalink / raw)
To: intel-gfx
Atm, if a full modeset is performed during the initial modeset the link
training will happen with uninitialized max DP rate and lane count. Make
sure the corresponding encoder state is initialized by adding an encoder
hook called during driver init and system resume.
A better alternative would be to store all states in the CRTC state and
make this state available for the link re-training code. Also instead of
the DPCD read in the hook there should be really a proper sink HW
readout in place. Both of these require a bigger rework, so for now opting
for this minimal fix to make at least full initial modesets work.
The patch is based on
https://patchwork.freedesktop.org/patch/101473/?series=10354&rev=3
v2: (Ville)
- s/sanitize_state/sync_state/
- No point in calling the hook when CRTC is disabled, remove the call.
- No point in calling the hook for MST, remove it.
v3: Check only DPCD_REV to avoid clobbering intel_dp->dpcd. (Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++++
drivers/gpu/drm/i915/display/intel_display.c | 2 ++
.../drm/i915/display/intel_display_types.h | 7 +++++
drivers/gpu/drm/i915/display/intel_dp.c | 28 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
5 files changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4e54c55ec99f..6f7bd67732f2 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4564,6 +4564,13 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
}
+static void intel_ddi_sync_state(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ if (intel_crtc_has_dp_encoder(crtc_state))
+ intel_dp_sync_state(encoder, crtc_state);
+}
+
static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
@@ -5182,6 +5189,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder->update_pipe = intel_ddi_update_pipe;
encoder->get_hw_state = intel_ddi_get_hw_state;
encoder->get_config = intel_ddi_get_config;
+ encoder->sync_state = intel_ddi_sync_state;
encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
encoder->suspend = intel_dp_encoder_suspend;
encoder->get_power_domains = intel_ddi_get_power_domains;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 755b83d47f9c..907e1d155443 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -18723,6 +18723,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
encoder->base.crtc = &crtc->base;
encoder->get_config(encoder, crtc_state);
+ if (encoder->sync_state)
+ encoder->sync_state(encoder, crtc_state);
} else {
encoder->base.crtc = NULL;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 5297b2f08ff9..65ae2070576f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -188,6 +188,13 @@ struct intel_encoder {
void (*get_config)(struct intel_encoder *,
struct intel_crtc_state *pipe_config);
+ /*
+ * Optional hook called during init/resume to sync any state
+ * stored in the encoder (eg. DP link parameters) wrt. the HW state.
+ */
+ void (*sync_state)(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
+
/*
* Optional hook, returning true if this encoder allows a fastset
* during the initial commit, false otherwise.
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index df5277c2b9ba..239016dcd544 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3703,6 +3703,33 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
}
}
+static bool
+intel_dp_get_dpcd(struct intel_dp *intel_dp);
+
+/**
+ * intel_dp_sync_state - sync the encoder state during init/resume
+ * @encoder: intel encoder to sync
+ * @crtc_state: state for the CRTC connected to the encoder
+ *
+ * Sync any state stored in the encoder wrt. HW state during driver init
+ * and system resume.
+ */
+void intel_dp_sync_state(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ /*
+ * Don't clobber DPCD if it's been already read out during output
+ * setup (eDP) or detect.
+ */
+ if (intel_dp->dpcd[DP_DPCD_REV] == 0)
+ intel_dp_get_dpcd(intel_dp);
+
+ intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
+ intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
+}
+
bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
@@ -8090,6 +8117,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
intel_encoder->compute_config = intel_dp_compute_config;
intel_encoder->get_hw_state = intel_dp_get_hw_state;
intel_encoder->get_config = intel_dp_get_config;
+ intel_encoder->sync_state = intel_dp_sync_state;
intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
intel_encoder->update_pipe = intel_panel_update_backlight;
intel_encoder->suspend = intel_dp_encoder_suspend;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 977585aea3c8..6c201377fdc0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -143,5 +143,7 @@ int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state);
+void intel_dp_sync_state(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
#endif /* __INTEL_DP_H__ */
--
2.25.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
2020-10-05 20:26 ` Imre Deak
@ 2020-10-05 23:37 ` Ville Syrjälä
2020-10-06 1:24 ` Imre Deak
0 siblings, 1 reply; 47+ messages in thread
From: Ville Syrjälä @ 2020-10-05 23:37 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Mon, Oct 05, 2020 at 11:26:05PM +0300, Imre Deak wrote:
> On Mon, Oct 05, 2020 at 11:08:19PM +0300, Ville Syrjälä wrote:
> > On Sat, Oct 03, 2020 at 03:18:42AM +0300, Imre Deak wrote:
> > > The BIOS of at least one ASUS-Z170M system with an SKL I have programs
> > > the 101b WRPLL PDIV divider value, which is the encoding for PDIV=7 with
> > > bit#0 incorrectly set.
> > >
> > > This happens with the
> > >
> > > "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9
> > >
> > > HDMI mode (scaled from a 1024x768 src fb) set by BIOS and the
> > >
> > > ref_clock=24000, dco_integer=383, dco_fraction=5802, pdiv=7, qdiv=1, kdiv=1
> > >
> > > WRPLL parameters (assuming PDIV=7 was the intended setting). This
> > > corresponds to 262749 PLL frequency/port clock.
> > >
> > > Later the driver sets the same mode for which it calculates the same
> > > dco_int/dco_frac/div WRPLL parameters (with the correct PDIV=7 encoding).
> > >
> > > Based on the above, let's assume that PDIV=7 was intended and the HW
> > > just ignores bit#0 in the PDIV register field for this setting, treating
> > > 100b and 101b encodings the same way.
> > >
> > > While at it add the MISSING_CASE() for the p0,p2 divider decodings.
> > >
> > > v2: (Ville)
> > > - Add a define for the incorrect divider value.
> > > - Emit only a debug message when detecting the incorrect divider value.
> > > - Use fallthrough from the incorrect divider value case.
> > > - Add the MISSING_CASE()s.
> > >
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 14 ++++++++++++++
> > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > 2 files changed, 15 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > index e08684e34078..61cb558c60d1 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > @@ -1602,12 +1602,26 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
> > > case DPLL_CFGCR2_PDIV_3:
> > > p0 = 3;
> > > break;
> > > + default:
> > > + if (p0 == DPLL_CFGCR2_PDIV_7_INVALID)
> >
> > Why not just 'case DPLL_CFGCR2_PDIV_7_INVALID:' ?
>
> So we can use fallthrough for both this one and the default case.
IMO trying to be fancy just makes the code harder to read.
>
> >
> > > + /*
> > > + * Incorrect ASUS-Z170M BIOS setting, the HW seems to ignore bit#0,
> > > + * handling it the same way as PDIV_7.
> > > + */
> > > + drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n");
> > > + else
> > > + MISSING_CASE(p0);
> > > +
> > > + fallthrough;
> > > case DPLL_CFGCR2_PDIV_7:
> > > p0 = 7;
> > > break;
> > > }
> > >
> > > switch (p2) {
> > > + default:
> > > + MISSING_CASE(p2);
> > > + fallthrough;
> >
> > Is there a specific reason we fall through to the 5 and 7 cases for
> > bogus values?
>
> Just to default to dividers that result in the minimum PLL freq.
I'd probably just set them to zero if they're bogus. Looks like
that should already give us warn and just return zero as the freq.
>
> >
> > > case DPLL_CFGCR2_KDIV_5:
> > > p2 = 5;
> > > break;
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 88c215cf97d4..d911583526db 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -10261,6 +10261,7 @@ enum skl_power_gate {
> > > #define DPLL_CFGCR2_PDIV_2 (1 << 2)
> > > #define DPLL_CFGCR2_PDIV_3 (2 << 2)
> > > #define DPLL_CFGCR2_PDIV_7 (4 << 2)
> > > +#define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2)
> > > #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
> > >
> > > #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
> > > --
> > > 2.25.1
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume
2020-10-05 20:46 ` Imre Deak
@ 2020-10-05 23:39 ` Ville Syrjälä
0 siblings, 0 replies; 47+ messages in thread
From: Ville Syrjälä @ 2020-10-05 23:39 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Mon, Oct 05, 2020 at 11:46:17PM +0300, Imre Deak wrote:
> On Mon, Oct 05, 2020 at 11:30:55PM +0300, Ville Syrjälä wrote:
> > On Sat, Oct 03, 2020 at 03:18:45AM +0300, Imre Deak wrote:
> > > Atm, if a full modeset is performed during the initial modeset the link
> > > training will happen with uninitialized max DP rate and lane count. Make
> > > sure the corresponding encoder state is initialized by adding an encoder
> > > hook called during driver init and system resume.
> > >
> > > A better alternative would be to store all states in the CRTC state and
> > > make this state available for the link re-training code. Also instead of
> > > the DPCD read in the hook there should be really a proper sink HW
> > > readout in place. Both of these require a bigger rework, so for now opting
> > > for this minimal fix to make at least full initial modesets work.
> > >
> > > The patch is based on
> > > https://patchwork.freedesktop.org/patch/101473/?series=10354&rev=3
> > >
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_ddi.c | 8 +++++
> > > drivers/gpu/drm/i915/display/intel_display.c | 4 +++
> > > .../drm/i915/display/intel_display_types.h | 7 +++++
> > > drivers/gpu/drm/i915/display/intel_dp.c | 31 +++++++++++++++++++
> > > drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
> > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++++++
> > > 6 files changed, 62 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index 4e54c55ec99f..a0805260b224 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -4564,6 +4564,13 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> > > intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
> > > }
> > >
> > > +static void intel_ddi_sanitize_state(struct intel_encoder *encoder,
> > > + const struct intel_crtc_state *crtc_state)
> > > +{
> > > + if (crtc_state && intel_crtc_has_dp_encoder(crtc_state))
> > > + intel_dp_sanitize_state(encoder, crtc_state);
> > > +}
> >
> > I think we usually use 'sanitize' to mean "hw state is garbage -> must
> > take steps to sanitize it". This one is just filling in our intel_dp
> > sidechannel state. So the name isn't super consistnet with existing
> > practies.
>
> It is called during init/resume time when encoders are sanitized as
> well, but yea it's a separate step from HW readout. So I can rename it
> for instance (back) to sync_state, or any better idea?
All I know is that I suck at naming things.
>
> >
> > > +
> > > static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
> > > struct intel_crtc_state *crtc_state)
> > > {
> > > @@ -5182,6 +5189,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> > > encoder->update_pipe = intel_ddi_update_pipe;
> > > encoder->get_hw_state = intel_ddi_get_hw_state;
> > > encoder->get_config = intel_ddi_get_config;
> > > + encoder->sanitize_state = intel_ddi_sanitize_state;
> > > encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
> > > encoder->suspend = intel_dp_encoder_suspend;
> > > encoder->get_power_domains = intel_ddi_get_power_domains;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 31be63225b10..e61311ee8b8c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -18725,8 +18725,12 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> > >
> > > encoder->base.crtc = &crtc->base;
> > > encoder->get_config(encoder, crtc_state);
> > > + if (encoder->sanitize_state)
> > > + encoder->sanitize_state(encoder, crtc_state);
> > > } else {
> > > encoder->base.crtc = NULL;
> > > + if (encoder->sanitize_state)
> > > + encoder->sanitize_state(encoder, NULL);
> >
> > I wonder if we should even bother calling it in this case.
>
> Yes, it would be just a nop atm, and can't think what state would need
> to be updated, so will remove it.
>
> >
> > > }
> > >
> > > drm_dbg_kms(&dev_priv->drm,
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 5297b2f08ff9..b2b458144f5a 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -188,6 +188,13 @@ struct intel_encoder {
> > > void (*get_config)(struct intel_encoder *,
> > > struct intel_crtc_state *pipe_config);
> > >
> > > + /*
> > > + * Optional hook called during init/resume to sanitize any state
> > > + * stored in the encoder (eg. DP link parameters).
> > > + */
> > > + void (*sanitize_state)(struct intel_encoder *encoder,
> > > + const struct intel_crtc_state *crtc_state);
> > > +
> > > /*
> > > * Optional hook, returning true if this encoder allows a fastset
> > > * during the initial commit, false otherwise.
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index df5277c2b9ba..9b6fe3b3b5b2 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -3703,6 +3703,36 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
> > > }
> > > }
> > >
> > > +static bool
> > > +intel_dp_get_dpcd(struct intel_dp *intel_dp);
> > > +
> > > +/**
> > > + * intel_dp_sanitize_state - sanitize the encoder state during init/resume
> > > + * @encoder: intel encoder to sanitize
> > > + * @crtc_state: state for the CRTC connected to the encoder
> > > + *
> > > + * Sanitize any state stored in the encoder during driver init and system
> > > + * resume.
> > > + */
> > > +void intel_dp_sanitize_state(struct intel_encoder *encoder,
> > > + const struct intel_crtc_state *crtc_state)
> > > +{
> > > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > > +
> > > + if (!crtc_state)
> > > + return;
> > > +
> > > + /*
> > > + * Don't clobber DPCD if it's been already read out during output
> > > + * setup (eDP) or detect.
> > > + */
> > > + if (!memchr_inv(intel_dp->dpcd, 0, sizeof(intel_dp->dpcd)))
> > > + intel_dp_get_dpcd(intel_dp);
> > > +
> > > + intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
> > > + intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
> > > +}
> > > +
> > > bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> > > struct intel_crtc_state *crtc_state)
> > > {
> > > @@ -8090,6 +8120,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
> > > intel_encoder->compute_config = intel_dp_compute_config;
> > > intel_encoder->get_hw_state = intel_dp_get_hw_state;
> > > intel_encoder->get_config = intel_dp_get_config;
> > > + intel_encoder->sanitize_state = intel_dp_sanitize_state;
> > > intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
> > > intel_encoder->update_pipe = intel_panel_update_backlight;
> > > intel_encoder->suspend = intel_dp_encoder_suspend;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> > > index 977585aea3c8..1ab741e0be67 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > > @@ -143,5 +143,7 @@ int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
> > >
> > > bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> > > struct intel_crtc_state *crtc_state);
> > > +void intel_dp_sanitize_state(struct intel_encoder *encoder,
> > > + const struct intel_crtc_state *crtc_state);
> > >
> > > #endif /* __INTEL_DP_H__ */
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > > index e948aacbd4ab..0831d1ee7978 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > > @@ -591,6 +591,15 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
> > > intel_ddi_get_config(&dig_port->base, pipe_config);
> > > }
> > >
> > > +static void intel_dp_mst_sync_state(struct intel_encoder *encoder,
> > > + const struct intel_crtc_state *crtc_state)
> > > +{
> > > + struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
> > > + struct intel_digital_port *dig_port = intel_mst->primary;
> > > +
> > > + return intel_dp_sanitize_state(&dig_port->base, crtc_state);
> > > +}
> > > +
> > > static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,
> > > struct intel_crtc_state *crtc_state)
> > > {
> > > @@ -906,6 +915,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe
> > > intel_encoder->enable = intel_mst_enable_dp;
> > > intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
> > > intel_encoder->get_config = intel_dp_mst_enc_get_config;
> > > + intel_encoder->sanitize_state = intel_dp_mst_sync_state;
> > > intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;
> > >
> > > return intel_mst;
> > > --
> > > 2.25.1
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6)
2020-10-03 0:18 [Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
` (10 preceding siblings ...)
2020-10-04 5:47 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
@ 2020-10-06 0:01 ` Patchwork
2020-10-06 0:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (4 subsequent siblings)
16 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2020-10-06 0:01 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6)
URL : https://patchwork.freedesktop.org/series/82173/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216
+./include/linux/seqlock.h:752:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:778:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6)
2020-10-03 0:18 [Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
` (11 preceding siblings ...)
2020-10-06 0:01 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6) Patchwork
@ 2020-10-06 0:22 ` Patchwork
2020-10-06 1:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7) Patchwork
` (3 subsequent siblings)
16 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2020-10-06 0:22 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 5818 bytes --]
== Series Details ==
Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6)
URL : https://patchwork.freedesktop.org/series/82173/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9098 -> Patchwork_18629
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/index.html
Known issues
------------
Here are the changes found in Patchwork_18629 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-kefka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
#### Possible fixes ####
* {igt@core_hotunplug@unbind-rebind}:
- {fi-tgl-dsi}: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/fi-tgl-dsi/igt@core_hotunplug@unbind-rebind.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/fi-tgl-dsi/igt@core_hotunplug@unbind-rebind.html
* igt@i915_module_load@reload:
- {fi-tgl-dsi}: [DMESG-WARN][7] ([i915#1982] / [k.org#205379]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/fi-tgl-dsi/igt@i915_module_load@reload.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/fi-tgl-dsi/igt@i915_module_load@reload.html
- fi-apl-guc: [DMESG-WARN][9] ([i915#1635] / [i915#1982]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/fi-apl-guc/igt@i915_module_load@reload.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/fi-apl-guc/igt@i915_module_load@reload.html
* igt@vgem_basic@unload:
- fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/fi-kbl-x1275/igt@vgem_basic@unload.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/fi-kbl-x1275/igt@vgem_basic@unload.html
#### Warnings ####
* igt@debugfs_test@read_all_entries:
- fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#62] / [i915#92]) +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/fi-kbl-x1275/igt@debugfs_test@read_all_entries.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/fi-kbl-x1275/igt@debugfs_test@read_all_entries.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/fi-kbl-x1275/igt@kms_force_connector_basic@force-connector-state.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/fi-kbl-x1275/igt@kms_force_connector_basic@force-connector-state.html
* igt@runner@aborted:
- fi-bdw-5557u: [FAIL][17] ([i915#2029] / [i915#2439]) -> [FAIL][18] ([i915#2029])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/fi-bdw-5557u/igt@runner@aborted.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/fi-bdw-5557u/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
[i915#289]: https://gitlab.freedesktop.org/drm/intel/issues/289
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (44 -> 38)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9098 -> Patchwork_18629
CI-20190529: 20190529
CI_DRM_9098: 877045337ceb241797ac16226a1f2f76b3553d1d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5800: 982ca4122fd4f04ad3dfa80c6246f190b36e0c72 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18629: f3685bccf1c82e3f7abefc8732655b3ee9395c39 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f3685bccf1c8 drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock
c7c321023c54 drm/i915: Add an encoder hook to sanitize its state during init/resume
e5d2d7a31511 drm/i915: Check for unsupported DP link rates during initial commit
7b668d3b7773 drm/i915: Move the initial fastset commit check to encoder hooks
169bac923784 drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/index.html
[-- Attachment #1.2: Type: text/html, Size: 7568 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
2020-10-05 23:37 ` Ville Syrjälä
@ 2020-10-06 1:24 ` Imre Deak
0 siblings, 0 replies; 47+ messages in thread
From: Imre Deak @ 2020-10-06 1:24 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tue, Oct 06, 2020 at 02:37:58AM +0300, Ville Syrjälä wrote:
> On Mon, Oct 05, 2020 at 11:26:05PM +0300, Imre Deak wrote:
> > On Mon, Oct 05, 2020 at 11:08:19PM +0300, Ville Syrjälä wrote:
> > > On Sat, Oct 03, 2020 at 03:18:42AM +0300, Imre Deak wrote:
> > > > The BIOS of at least one ASUS-Z170M system with an SKL I have programs
> > > > the 101b WRPLL PDIV divider value, which is the encoding for PDIV=7 with
> > > > bit#0 incorrectly set.
> > > >
> > > > This happens with the
> > > >
> > > > "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9
> > > >
> > > > HDMI mode (scaled from a 1024x768 src fb) set by BIOS and the
> > > >
> > > > ref_clock=24000, dco_integer=383, dco_fraction=5802, pdiv=7, qdiv=1, kdiv=1
> > > >
> > > > WRPLL parameters (assuming PDIV=7 was the intended setting). This
> > > > corresponds to 262749 PLL frequency/port clock.
> > > >
> > > > Later the driver sets the same mode for which it calculates the same
> > > > dco_int/dco_frac/div WRPLL parameters (with the correct PDIV=7 encoding).
> > > >
> > > > Based on the above, let's assume that PDIV=7 was intended and the HW
> > > > just ignores bit#0 in the PDIV register field for this setting, treating
> > > > 100b and 101b encodings the same way.
> > > >
> > > > While at it add the MISSING_CASE() for the p0,p2 divider decodings.
> > > >
> > > > v2: (Ville)
> > > > - Add a define for the incorrect divider value.
> > > > - Emit only a debug message when detecting the incorrect divider value.
> > > > - Use fallthrough from the incorrect divider value case.
> > > > - Add the MISSING_CASE()s.
> > > >
> > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 14 ++++++++++++++
> > > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > > 2 files changed, 15 insertions(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > > index e08684e34078..61cb558c60d1 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > > @@ -1602,12 +1602,26 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
> > > > case DPLL_CFGCR2_PDIV_3:
> > > > p0 = 3;
> > > > break;
> > > > + default:
> > > > + if (p0 == DPLL_CFGCR2_PDIV_7_INVALID)
> > >
> > > Why not just 'case DPLL_CFGCR2_PDIV_7_INVALID:' ?
> >
> > So we can use fallthrough for both this one and the default case.
>
> IMO trying to be fancy just makes the code harder to read.
>
> > > > + /*
> > > > + * Incorrect ASUS-Z170M BIOS setting, the HW seems to ignore bit#0,
> > > > + * handling it the same way as PDIV_7.
> > > > + */
> > > > + drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n");
> > > > + else
> > > > + MISSING_CASE(p0);
> > > > +
> > > > + fallthrough;
> > > > case DPLL_CFGCR2_PDIV_7:
> > > > p0 = 7;
> > > > break;
> > > > }
> > > >
> > > > switch (p2) {
> > > > + default:
> > > > + MISSING_CASE(p2);
> > > > + fallthrough;
> > >
> > > Is there a specific reason we fall through to the 5 and 7 cases for
> > > bogus values?
> >
> > Just to default to dividers that result in the minimum PLL freq.
>
> I'd probably just set them to zero if they're bogus. Looks like
> that should already give us warn and just return zero as the freq.
Ok.
> > > > case DPLL_CFGCR2_KDIV_5:
> > > > p2 = 5;
> > > > break;
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > > index 88c215cf97d4..d911583526db 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -10261,6 +10261,7 @@ enum skl_power_gate {
> > > > #define DPLL_CFGCR2_PDIV_2 (1 << 2)
> > > > #define DPLL_CFGCR2_PDIV_3 (2 << 2)
> > > > #define DPLL_CFGCR2_PDIV_7 (4 << 2)
> > > > +#define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2)
> > > > #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
> > > >
> > > > #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
> > > > --
> > > > 2.25.1
> > >
> > > --
> > > Ville Syrjälä
> > > Intel
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH v3 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
2020-10-03 0:18 ` [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming Imre Deak
2020-10-05 20:08 ` Ville Syrjälä
@ 2020-10-06 1:35 ` Imre Deak
2020-10-06 8:59 ` Ville Syrjälä
1 sibling, 1 reply; 47+ messages in thread
From: Imre Deak @ 2020-10-06 1:35 UTC (permalink / raw)
To: intel-gfx
The BIOS of at least one ASUS-Z170M system with an SKL I have programs
the 101b WRPLL PDIV divider value, which is the encoding for PDIV=7 with
bit#0 incorrectly set.
This happens with the
"3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9
HDMI mode (scaled from a 1024x768 src fb) set by BIOS and the
ref_clock=24000, dco_integer=383, dco_fraction=5802, pdiv=7, qdiv=1, kdiv=1
WRPLL parameters (assuming PDIV=7 was the intended setting). This
corresponds to 262749 PLL frequency/port clock.
Later the driver sets the same mode for which it calculates the same
dco_int/dco_frac/div WRPLL parameters (with the correct PDIV=7 encoding).
Based on the above, let's assume that PDIV=7 was intended and the HW
just ignores bit#0 in the PDIV register field for this setting, treating
100b and 101b encodings the same way.
While at it add the MISSING_CASE() for the p0,p2 divider decodings.
v2: (Ville)
- Add a define for the incorrect divider value.
- Emit only a debug message when detecting the incorrect divider value.
- Use fallthrough from the incorrect divider value case.
- Add the MISSING_CASE()s.
v3: Return 0 freq for incorrect divider values. (Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 +++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index e08684e34078..fff4e154b391 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -1602,9 +1602,19 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
case DPLL_CFGCR2_PDIV_3:
p0 = 3;
break;
+ case DPLL_CFGCR2_PDIV_7_INVALID:
+ /*
+ * Incorrect ASUS-Z170M BIOS setting, the HW seems to ignore bit#0,
+ * handling it the same way as PDIV_7.
+ */
+ drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n");
+ fallthrough;
case DPLL_CFGCR2_PDIV_7:
p0 = 7;
break;
+ default:
+ MISSING_CASE(p0);
+ return 0;
}
switch (p2) {
@@ -1620,6 +1630,9 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
case DPLL_CFGCR2_KDIV_1:
p2 = 1;
break;
+ default:
+ MISSING_CASE(p2);
+ return 0;
}
dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) *
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 88c215cf97d4..d911583526db 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10261,6 +10261,7 @@ enum skl_power_gate {
#define DPLL_CFGCR2_PDIV_2 (1 << 2)
#define DPLL_CFGCR2_PDIV_3 (2 << 2)
#define DPLL_CFGCR2_PDIV_7 (4 << 2)
+#define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2)
#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
--
2.25.1
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7)
2020-10-03 0:18 [Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
` (12 preceding siblings ...)
2020-10-06 0:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-10-06 1:46 ` Patchwork
2020-10-06 2:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
16 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2020-10-06 1:46 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7)
URL : https://patchwork.freedesktop.org/series/82173/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216
+./include/linux/seqlock.h:752:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:778:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7)
2020-10-03 0:18 [Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
` (13 preceding siblings ...)
2020-10-06 1:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7) Patchwork
@ 2020-10-06 2:09 ` Patchwork
2020-10-06 2:39 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6) Patchwork
2020-10-06 5:39 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7) Patchwork
16 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2020-10-06 2:09 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 4931 bytes --]
== Series Details ==
Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7)
URL : https://patchwork.freedesktop.org/series/82173/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9100 -> Patchwork_18630
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/index.html
Known issues
------------
Here are the changes found in Patchwork_18630 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_busy@basic@flip:
- fi-kbl-x1275: [PASS][1] -> [DMESG-WARN][2] ([i915#62] / [i915#92] / [i915#95])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/fi-kbl-x1275/igt@kms_busy@basic@flip.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/fi-kbl-x1275/igt@kms_busy@basic@flip.html
#### Possible fixes ####
* igt@kms_busy@basic@flip:
- {fi-tgl-dsi}: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/fi-tgl-dsi/igt@kms_busy@basic@flip.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/fi-tgl-dsi/igt@kms_busy@basic@flip.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-n3050: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- fi-byt-j1900: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@vgem_basic@unload:
- fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/fi-kbl-x1275/igt@vgem_basic@unload.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/fi-kbl-x1275/igt@vgem_basic@unload.html
#### Warnings ####
* igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
- fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92]) -> [DMESG-WARN][12] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#62] / [i915#92]) +5 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/fi-kbl-x1275/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/fi-kbl-x1275/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2268]: https://gitlab.freedesktop.org/drm/intel/issues/2268
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (44 -> 38)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9100 -> Patchwork_18630
CI-20190529: 20190529
CI_DRM_9100: 62e000a556587d80f5c23b863195a30c073c7741 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5800: 982ca4122fd4f04ad3dfa80c6246f190b36e0c72 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18630: c9218b4e5fb4b047c75911a798897ab663fe158f @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c9218b4e5fb4 drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock
c2ee2fe22455 drm/i915: Add an encoder hook to sanitize its state during init/resume
cf94f1fd7110 drm/i915: Check for unsupported DP link rates during initial commit
76cfbbbf6aa9 drm/i915: Move the initial fastset commit check to encoder hooks
479da4d9f49e drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/index.html
[-- Attachment #1.2: Type: text/html, Size: 6623 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6)
2020-10-03 0:18 [Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
` (14 preceding siblings ...)
2020-10-06 2:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-10-06 2:39 ` Patchwork
2020-10-06 10:32 ` Imre Deak
2020-10-06 5:39 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7) Patchwork
16 siblings, 1 reply; 47+ messages in thread
From: Patchwork @ 2020-10-06 2:39 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 12523 bytes --]
== Series Details ==
Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6)
URL : https://patchwork.freedesktop.org/series/82173/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9098_full -> Patchwork_18629_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18629_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18629_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18629_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_softpin@softpin:
- shard-iclb: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-iclb6/igt@gem_softpin@softpin.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-iclb1/igt@gem_softpin@softpin.html
Known issues
------------
Here are the changes found in Patchwork_18629_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_reloc@basic-many-active@vecs0:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2389])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-glk4/igt@gem_exec_reloc@basic-many-active@vecs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-glk6/igt@gem_exec_reloc@basic-many-active@vecs0.html
* igt@kms_cursor_legacy@all-pipes-torture-bo:
- shard-tglb: [PASS][5] -> [DMESG-WARN][6] ([i915#128])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-tglb3/igt@kms_cursor_legacy@all-pipes-torture-bo.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-tglb7/igt@kms_cursor_legacy@all-pipes-torture-bo.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#79])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [PASS][9] -> [FAIL][10] ([i915#79]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +3 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-kbl6/igt@kms_flip@flip-vs-suspend@c-dp1.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-kbl4/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render:
- shard-tglb: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][15] -> [FAIL][16] ([i915#1188])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl10/igt@kms_hdr@bpc-switch-suspend.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl1/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-skl: [PASS][17] -> [INCOMPLETE][18] ([i915#198])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl9/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [i915#265])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-iclb5/igt@kms_psr@psr2_cursor_plane_move.html
* igt@kms_setmode@basic:
- shard-glk: [PASS][23] -> [FAIL][24] ([i915#31])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-glk4/igt@kms_setmode@basic.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-glk1/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-a-ts-continuation-dpms-rpm:
- shard-skl: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) +11 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl5/igt@kms_vblank@pipe-a-ts-continuation-dpms-rpm.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl4/igt@kms_vblank@pipe-a-ts-continuation-dpms-rpm.html
* igt@kms_vblank@pipe-b-wait-forked-busy:
- shard-apl: [PASS][27] -> [DMESG-WARN][28] ([i915#1635] / [i915#1982]) +2 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-apl4/igt@kms_vblank@pipe-b-wait-forked-busy.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-apl3/igt@kms_vblank@pipe-b-wait-forked-busy.html
#### Possible fixes ####
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-skl: [TIMEOUT][29] ([i915#2424]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl1/igt@gem_userptr_blits@unsync-unmap-cycles.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl9/igt@gem_userptr_blits@unsync-unmap-cycles.html
* {igt@kms_async_flips@async-flip-with-page-flip-events}:
- shard-glk: [FAIL][31] ([i915#2521]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-glk9/igt@kms_async_flips@async-flip-with-page-flip-events.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-glk7/igt@kms_async_flips@async-flip-with-page-flip-events.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
- shard-glk: [FAIL][33] ([i915#72]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-glk9/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-glk7/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled:
- shard-glk: [DMESG-WARN][35] ([i915#1982]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-glk9/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-glk7/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1:
- shard-glk: [FAIL][37] ([i915#2122]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-glk7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][39] ([i915#180]) -> [PASS][40] +6 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
- shard-tglb: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-skl: [INCOMPLETE][43] ([i915#198]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl10/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [FAIL][45] ([fdo#108145] / [i915#265]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [SKIP][47] ([fdo#109441]) -> [PASS][48] +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-iclb1/igt@kms_psr@psr2_basic.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-iclb2/igt@kms_psr@psr2_basic.html
* igt@perf_pmu@module-unload:
- shard-apl: [DMESG-WARN][49] ([i915#1635] / [i915#1982]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-apl1/igt@perf_pmu@module-unload.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-apl4/igt@perf_pmu@module-unload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2424]: https://gitlab.freedesktop.org/drm/intel/issues/2424
[i915#2469]: https://gitlab.freedesktop.org/drm/intel/issues/2469
[i915#2476]: https://gitlab.freedesktop.org/drm/intel/issues/2476
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Participating hosts (11 -> 12)
------------------------------
Additional (1): pig-snb-2600
Build changes
-------------
* Linux: CI_DRM_9098 -> Patchwork_18629
CI-20190529: 20190529
CI_DRM_9098: 877045337ceb241797ac16226a1f2f76b3553d1d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5800: 982ca4122fd4f04ad3dfa80c6246f190b36e0c72 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18629: f3685bccf1c82e3f7abefc8732655b3ee9395c39 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/index.html
[-- Attachment #1.2: Type: text/html, Size: 14422 bytes --]
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7)
2020-10-03 0:18 [Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
` (15 preceding siblings ...)
2020-10-06 2:39 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6) Patchwork
@ 2020-10-06 5:39 ` Patchwork
16 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2020-10-06 5:39 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 19484 bytes --]
== Series Details ==
Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7)
URL : https://patchwork.freedesktop.org/series/82173/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9100_full -> Patchwork_18630_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18630_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18630_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18630_full:
### Piglit changes ###
#### Possible regressions ####
* spec@!opengl 1.3@gl-1.3-texture-env:
- pig-snb-2600: NOTRUN -> [INCOMPLETE][1] +7 similar issues
[1]: None
* spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-int_ivec3_array3-position-double_dvec2 (NEW):
- {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][2] +7 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/pig-icl-1065g7/spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-int_ivec3_array3-position-double_dvec2.html
* spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-double_dmat4x3-float_mat3 (NEW):
- {pig-icl-1065g7}: NOTRUN -> [CRASH][3] +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/pig-icl-1065g7/spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-double_dmat4x3-float_mat3.html
New tests
---------
New tests have been introduced between CI_DRM_9100_full and Patchwork_18630_full:
### New Piglit tests (11) ###
* spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-double_dmat4x2-float_float_array3-position:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-float_mat2x3_array3-position-double_dvec3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-int_ivec3_array3-double_dvec4-position:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-int_ivec3_array3-position-double_dvec2:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-double_dmat4-double_dmat4x2_array2:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-double_dmat4-double_dvec3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-double_dmat4x3-float_mat3:
- Statuses : 1 crash(s)
- Exec time: [0.75] s
* spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-double_dmat4x3-int_ivec2_array3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-float_vec3_array3-double_dmat4x2:
- Statuses : 1 crash(s)
- Exec time: [1.14] s
* spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-ubyte_uvec2-short_ivec3-double_dmat3x2-position:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@nv_vertex_program2_option@vp-clipdistance-01:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18630_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-kbl: [PASS][4] -> [DMESG-WARN][5] ([i915#180]) +7 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-kbl6/igt@gem_ctx_isolation@preservation-s3@vecs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@vecs0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][6] -> [SKIP][7] ([i915#2190])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-tglb8/igt@gem_huc_copy@huc-copy.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-tglb6/igt@gem_huc_copy@huc-copy.html
* igt@kms_cursor_edge_walk@pipe-c-128x128-right-edge:
- shard-glk: [PASS][8] -> [DMESG-WARN][9] ([i915#1982])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-glk6/igt@kms_cursor_edge_walk@pipe-c-128x128-right-edge.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-glk4/igt@kms_cursor_edge_walk@pipe-c-128x128-right-edge.html
* igt@kms_cursor_legacy@cursora-vs-flipa-varying-size:
- shard-skl: [PASS][10] -> [DMESG-WARN][11] ([i915#1982]) +8 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-skl4/igt@kms_cursor_legacy@cursora-vs-flipa-varying-size.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-skl9/igt@kms_cursor_legacy@cursora-vs-flipa-varying-size.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@a-dp1:
- shard-kbl: [PASS][12] -> [DMESG-WARN][13] ([i915#1982]) +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-kbl4/igt@kms_flip@flip-vs-blocking-wf-vblank@a-dp1.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-kbl4/igt@kms_flip@flip-vs-blocking-wf-vblank@a-dp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-skl: [PASS][14] -> [FAIL][15] ([i915#2122])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt:
- shard-tglb: [PASS][16] -> [DMESG-WARN][17] ([i915#1982])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][18] -> [FAIL][19] ([i915#1188])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-skl5/igt@kms_hdr@bpc-switch-suspend.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-skl7/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-iclb: [PASS][20] -> [DMESG-WARN][21] ([i915#1982]) +1 similar issue
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-iclb5/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-iclb3/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][22] -> [FAIL][23] ([fdo#108145] / [i915#265]) +2 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][24] -> [SKIP][25] ([fdo#109642] / [fdo#111068])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-iclb8/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][26] -> [SKIP][27] ([fdo#109441])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-iclb1/igt@kms_psr@psr2_cursor_render.html
* igt@kms_setmode@basic:
- shard-glk: [PASS][28] -> [FAIL][29] ([i915#31])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-glk5/igt@kms_setmode@basic.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-glk6/igt@kms_setmode@basic.html
#### Possible fixes ####
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-skl: [TIMEOUT][30] ([i915#2424]) -> [PASS][31]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-skl7/igt@gem_userptr_blits@unsync-unmap-cycles.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-skl4/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gen9_exec_parse@allowed-all:
- shard-skl: [DMESG-WARN][32] ([i915#1436] / [i915#716]) -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-skl6/igt@gen9_exec_parse@allowed-all.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-skl4/igt@gen9_exec_parse@allowed-all.html
* igt@i915_module_load@reload:
- shard-iclb: [DMESG-WARN][34] ([i915#1982]) -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-iclb4/igt@i915_module_load@reload.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-iclb6/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@i2c:
- shard-glk: [FAIL][36] ([i915#68]) -> [PASS][37]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-glk1/igt@i915_pm_rpm@i2c.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-glk3/igt@i915_pm_rpm@i2c.html
* {igt@kms_async_flips@async-flip-with-page-flip-events}:
- shard-kbl: [FAIL][38] ([i915#2521]) -> [PASS][39] +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-kbl1/igt@kms_async_flips@async-flip-with-page-flip-events.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-kbl1/igt@kms_async_flips@async-flip-with-page-flip-events.html
- shard-glk: [FAIL][40] ([i915#2521]) -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-glk7/igt@kms_async_flips@async-flip-with-page-flip-events.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-glk1/igt@kms_async_flips@async-flip-with-page-flip-events.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [DMESG-WARN][42] ([i915#180]) -> [PASS][43] +2 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: [FAIL][44] ([i915#96]) -> [PASS][45]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-hsw1/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@cursora-vs-flipa-toggle:
- shard-skl: [DMESG-WARN][46] ([i915#1982]) -> [PASS][47] +4 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-skl10/igt@kms_cursor_legacy@cursora-vs-flipa-toggle.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-skl5/igt@kms_cursor_legacy@cursora-vs-flipa-toggle.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-skl: [FAIL][48] ([i915#2346]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][50] ([i915#79]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [FAIL][52] ([i915#79]) -> [PASS][53]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-skl9/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
- shard-tglb: [DMESG-WARN][54] ([i915#1982]) -> [PASS][55] +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][56] ([i915#1188]) -> [PASS][57] +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-skl6/igt@kms_hdr@bpc-switch-dpms.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-skl4/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][58] ([fdo#108145] / [i915#265]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][60] ([fdo#109441]) -> [PASS][61] +3 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-iclb6/igt@kms_psr@psr2_primary_mmap_cpu.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_vblank@pipe-b-wait-forked-busy:
- shard-apl: [DMESG-WARN][62] ([i915#1635] / [i915#1982]) -> [PASS][63] +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-apl3/igt@kms_vblank@pipe-b-wait-forked-busy.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-apl3/igt@kms_vblank@pipe-b-wait-forked-busy.html
* igt@perf@polling-parameterized:
- shard-tglb: [FAIL][64] ([i915#1542]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-tglb8/igt@perf@polling-parameterized.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-tglb6/igt@perf@polling-parameterized.html
* igt@perf@polling-small-buf:
- shard-skl: [FAIL][66] ([i915#1722]) -> [PASS][67]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-skl3/igt@perf@polling-small-buf.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-skl6/igt@perf@polling-small-buf.html
* igt@sysfs_timeslice_duration@timeout@vecs0:
- shard-glk: [FAIL][68] ([i915#1755]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-glk5/igt@sysfs_timeslice_duration@timeout@vecs0.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-glk2/igt@sysfs_timeslice_duration@timeout@vecs0.html
- shard-skl: [FAIL][70] ([i915#1755]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-skl5/igt@sysfs_timeslice_duration@timeout@vecs0.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-skl7/igt@sysfs_timeslice_duration@timeout@vecs0.html
#### Warnings ####
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [SKIP][72] ([fdo#109349]) -> [DMESG-WARN][73] ([i915#1226])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-iclb6/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-tglb: [DMESG-WARN][74] ([i915#2411]) -> [DMESG-WARN][75] ([i915#1982] / [i915#2411])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-suspend.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2424]: https://gitlab.freedesktop.org/drm/intel/issues/2424
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#68]: https://gitlab.freedesktop.org/drm/intel/issues/68
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96
Participating hosts (11 -> 12)
------------------------------
Additional (1): pig-snb-2600
Build changes
-------------
* Linux: CI_DRM_9100 -> Patchwork_18630
CI-20190529: 20190529
CI_DRM_9100: 62e000a556587d80f5c23b863195a30c073c7741 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5800: 982ca4122fd4f04ad3dfa80c6246f190b36e0c72 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18630: c9218b4e5fb4b047c75911a798897ab663fe158f @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/index.html
[-- Attachment #1.2: Type: text/html, Size: 22615 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH v3 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume
2020-10-05 23:01 ` [Intel-gfx] [PATCH v3 " Imre Deak
@ 2020-10-06 8:58 ` Ville Syrjälä
0 siblings, 0 replies; 47+ messages in thread
From: Ville Syrjälä @ 2020-10-06 8:58 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Tue, Oct 06, 2020 at 02:01:54AM +0300, Imre Deak wrote:
> Atm, if a full modeset is performed during the initial modeset the link
> training will happen with uninitialized max DP rate and lane count. Make
> sure the corresponding encoder state is initialized by adding an encoder
> hook called during driver init and system resume.
>
> A better alternative would be to store all states in the CRTC state and
> make this state available for the link re-training code. Also instead of
> the DPCD read in the hook there should be really a proper sink HW
> readout in place. Both of these require a bigger rework, so for now opting
> for this minimal fix to make at least full initial modesets work.
>
> The patch is based on
> https://patchwork.freedesktop.org/patch/101473/?series=10354&rev=3
>
> v2: (Ville)
> - s/sanitize_state/sync_state/
> - No point in calling the hook when CRTC is disabled, remove the call.
> - No point in calling the hook for MST, remove it.
>
> v3: Check only DPCD_REV to avoid clobbering intel_dp->dpcd. (Ville)
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++++
> drivers/gpu/drm/i915/display/intel_display.c | 2 ++
> .../drm/i915/display/intel_display_types.h | 7 +++++
> drivers/gpu/drm/i915/display/intel_dp.c | 28 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
> 5 files changed, 47 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4e54c55ec99f..6f7bd67732f2 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4564,6 +4564,13 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
> }
>
> +static void intel_ddi_sync_state(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + if (intel_crtc_has_dp_encoder(crtc_state))
> + intel_dp_sync_state(encoder, crtc_state);
> +}
> +
> static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state)
> {
> @@ -5182,6 +5189,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> encoder->update_pipe = intel_ddi_update_pipe;
> encoder->get_hw_state = intel_ddi_get_hw_state;
> encoder->get_config = intel_ddi_get_config;
> + encoder->sync_state = intel_ddi_sync_state;
> encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
> encoder->suspend = intel_dp_encoder_suspend;
> encoder->get_power_domains = intel_ddi_get_power_domains;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 755b83d47f9c..907e1d155443 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -18723,6 +18723,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
>
> encoder->base.crtc = &crtc->base;
> encoder->get_config(encoder, crtc_state);
> + if (encoder->sync_state)
> + encoder->sync_state(encoder, crtc_state);
> } else {
> encoder->base.crtc = NULL;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 5297b2f08ff9..65ae2070576f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -188,6 +188,13 @@ struct intel_encoder {
> void (*get_config)(struct intel_encoder *,
> struct intel_crtc_state *pipe_config);
>
> + /*
> + * Optional hook called during init/resume to sync any state
> + * stored in the encoder (eg. DP link parameters) wrt. the HW state.
> + */
> + void (*sync_state)(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state);
> +
> /*
> * Optional hook, returning true if this encoder allows a fastset
> * during the initial commit, false otherwise.
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index df5277c2b9ba..239016dcd544 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3703,6 +3703,33 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
> }
> }
>
> +static bool
> +intel_dp_get_dpcd(struct intel_dp *intel_dp);
> +
> +/**
> + * intel_dp_sync_state - sync the encoder state during init/resume
> + * @encoder: intel encoder to sync
> + * @crtc_state: state for the CRTC connected to the encoder
> + *
> + * Sync any state stored in the encoder wrt. HW state during driver init
> + * and system resume.
> + */
> +void intel_dp_sync_state(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + /*
> + * Don't clobber DPCD if it's been already read out during output
> + * setup (eDP) or detect.
> + */
> + if (intel_dp->dpcd[DP_DPCD_REV] == 0)
> + intel_dp_get_dpcd(intel_dp);
> +
> + intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
> + intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
> +}
> +
> bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state)
> {
> @@ -8090,6 +8117,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
> intel_encoder->compute_config = intel_dp_compute_config;
> intel_encoder->get_hw_state = intel_dp_get_hw_state;
> intel_encoder->get_config = intel_dp_get_config;
> + intel_encoder->sync_state = intel_dp_sync_state;
> intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
> intel_encoder->update_pipe = intel_panel_update_backlight;
> intel_encoder->suspend = intel_dp_encoder_suspend;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 977585aea3c8..6c201377fdc0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -143,5 +143,7 @@ int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
>
> bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state);
> +void intel_dp_sync_state(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state);
>
> #endif /* __INTEL_DP_H__ */
> --
> 2.25.1
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH v3 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
2020-10-06 1:35 ` [Intel-gfx] [PATCH v3 " Imre Deak
@ 2020-10-06 8:59 ` Ville Syrjälä
0 siblings, 0 replies; 47+ messages in thread
From: Ville Syrjälä @ 2020-10-06 8:59 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Tue, Oct 06, 2020 at 04:35:55AM +0300, Imre Deak wrote:
> The BIOS of at least one ASUS-Z170M system with an SKL I have programs
> the 101b WRPLL PDIV divider value, which is the encoding for PDIV=7 with
> bit#0 incorrectly set.
>
> This happens with the
>
> "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9
>
> HDMI mode (scaled from a 1024x768 src fb) set by BIOS and the
>
> ref_clock=24000, dco_integer=383, dco_fraction=5802, pdiv=7, qdiv=1, kdiv=1
>
> WRPLL parameters (assuming PDIV=7 was the intended setting). This
> corresponds to 262749 PLL frequency/port clock.
>
> Later the driver sets the same mode for which it calculates the same
> dco_int/dco_frac/div WRPLL parameters (with the correct PDIV=7 encoding).
>
> Based on the above, let's assume that PDIV=7 was intended and the HW
> just ignores bit#0 in the PDIV register field for this setting, treating
> 100b and 101b encodings the same way.
>
> While at it add the MISSING_CASE() for the p0,p2 divider decodings.
>
> v2: (Ville)
> - Add a define for the incorrect divider value.
> - Emit only a debug message when detecting the incorrect divider value.
> - Use fallthrough from the incorrect divider value case.
> - Add the MISSING_CASE()s.
>
> v3: Return 0 freq for incorrect divider values. (Ville)
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 +++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index e08684e34078..fff4e154b391 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -1602,9 +1602,19 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
> case DPLL_CFGCR2_PDIV_3:
> p0 = 3;
> break;
> + case DPLL_CFGCR2_PDIV_7_INVALID:
> + /*
> + * Incorrect ASUS-Z170M BIOS setting, the HW seems to ignore bit#0,
> + * handling it the same way as PDIV_7.
> + */
> + drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n");
> + fallthrough;
> case DPLL_CFGCR2_PDIV_7:
> p0 = 7;
> break;
> + default:
> + MISSING_CASE(p0);
> + return 0;
> }
>
> switch (p2) {
> @@ -1620,6 +1630,9 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
> case DPLL_CFGCR2_KDIV_1:
> p2 = 1;
> break;
> + default:
> + MISSING_CASE(p2);
> + return 0;
> }
>
> dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) *
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 88c215cf97d4..d911583526db 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10261,6 +10261,7 @@ enum skl_power_gate {
> #define DPLL_CFGCR2_PDIV_2 (1 << 2)
> #define DPLL_CFGCR2_PDIV_3 (2 << 2)
> #define DPLL_CFGCR2_PDIV_7 (4 << 2)
> +#define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2)
> #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
>
> #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
> --
> 2.25.1
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH v3 2/5] drm/i915: Move the initial fastset commit check to encoder hooks
2020-10-05 21:53 ` [Intel-gfx] [PATCH v3 " Imre Deak
@ 2020-10-06 9:42 ` Jani Nikula
2020-10-06 9:55 ` Imre Deak
0 siblings, 1 reply; 47+ messages in thread
From: Jani Nikula @ 2020-10-06 9:42 UTC (permalink / raw)
To: Imre Deak, intel-gfx
On Tue, 06 Oct 2020, Imre Deak <imre.deak@intel.com> wrote:
> Move the checks to decide whether a fastset is possible during the
> initial commit to an encoder hook. This check is really encoder specific
> and the next patch will also require this adding a DP encoder specific
> check.
>
> v2: Fix negated condition in gen11_dsi_initial_fastset_check().
> v3: Make sure to call the hook for all encoders on the crtc. (Ville)
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 14 ++++++++++
> drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++++++
> drivers/gpu/drm/i915/display/intel_display.c | 27 ++++++++-----------
> .../drm/i915/display/intel_display_types.h | 8 ++++++
> drivers/gpu/drm/i915/display/intel_dp.c | 22 +++++++++++++++
> drivers/gpu/drm/i915/display/intel_dp.h | 3 +++
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 +++++++
> 7 files changed, 78 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index fe946a2e2082..4400e83f783f 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1668,6 +1668,19 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
> return ret;
> }
>
> +static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state)
> +{
> + if (crtc_state->dsc.compression_enable) {
> + drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n");
> + crtc_state->uapi.mode_changed = true;
Just musing... if it's a *check*, why do we pass in a non-const
crtc_state and modify it here?
Would it not be cleaner to pass in const crtc_state and set
crtc_state->uapi.mode_changed in the caller based on the return value?
BR,
Jani.
> +
> + return false;
> + }
> +
> + return true;
> +}
> +
> static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
> {
> intel_encoder_destroy(encoder);
> @@ -1923,6 +1936,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
> encoder->update_pipe = intel_panel_update_backlight;
> encoder->compute_config = gen11_dsi_compute_config;
> encoder->get_hw_state = gen11_dsi_get_hw_state;
> + encoder->initial_fastset_check = gen11_dsi_initial_fastset_check;
> encoder->type = INTEL_OUTPUT_DSI;
> encoder->cloneable = 0;
> encoder->pipe_mask = ~0;
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index b4c520348b3b..4e54c55ec99f 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4564,6 +4564,15 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
> }
>
> +static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state)
> +{
> + if (intel_crtc_has_dp_encoder(crtc_state))
> + return intel_dp_initial_fastset_check(encoder, crtc_state);
> +
> + return true;
> +}
> +
> static enum intel_output_type
> intel_ddi_compute_output_type(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state,
> @@ -5173,6 +5182,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> encoder->update_pipe = intel_ddi_update_pipe;
> encoder->get_hw_state = intel_ddi_get_hw_state;
> encoder->get_config = intel_ddi_get_config;
> + encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
> encoder->suspend = intel_dp_encoder_suspend;
> encoder->get_power_domains = intel_ddi_get_power_domains;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 753f202ef6a0..755b83d47f9c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -17951,6 +17951,8 @@ static int intel_initial_commit(struct drm_device *dev)
> }
>
> if (crtc_state->hw.active) {
> + struct intel_encoder *encoder;
> +
> /*
> * We've not yet detected sink capabilities
> * (audio,infoframes,etc.) and thus we don't want to
> @@ -17972,22 +17974,15 @@ static int intel_initial_commit(struct drm_device *dev)
> */
> crtc_state->uapi.color_mgmt_changed = true;
>
> - /*
> - * FIXME hack to force full modeset when DSC is being
> - * used.
> - *
> - * As long as we do not have full state readout and
> - * config comparison of crtc_state->dsc, we have no way
> - * to ensure reliable fastset. Remove once we have
> - * readout for DSC.
> - */
> - if (crtc_state->dsc.compression_enable) {
> - ret = drm_atomic_add_affected_connectors(state,
> - &crtc->base);
> - if (ret)
> - goto out;
> - crtc_state->uapi.mode_changed = true;
> - drm_dbg_kms(dev, "Force full modeset for DSC\n");
> + for_each_intel_encoder_mask(dev, encoder,
> + crtc_state->uapi.encoder_mask) {
> + if (encoder->initial_fastset_check &&
> + !encoder->initial_fastset_check(encoder, crtc_state)) {
> + ret = drm_atomic_add_affected_connectors(state,
> + &crtc->base);
> + if (ret)
> + goto out;
> + }
> }
> }
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index d5dc18cb8c39..5297b2f08ff9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -187,6 +187,14 @@ struct intel_encoder {
> * be set correctly before calling this function. */
> void (*get_config)(struct intel_encoder *,
> struct intel_crtc_state *pipe_config);
> +
> + /*
> + * Optional hook, returning true if this encoder allows a fastset
> + * during the initial commit, false otherwise.
> + */
> + bool (*initial_fastset_check)(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state);
> +
> /*
> * Acquires the power domains needed for an active encoder during
> * hardware state readout.
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 7429597b57be..d33a3d9fdc3a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3703,6 +3703,27 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
> }
> }
>
> +bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> +
> + /*
> + * FIXME hack to force full modeset when DSC is being used.
> + *
> + * As long as we do not have full state readout and config comparison
> + * of crtc_state->dsc, we have no way to ensure reliable fastset.
> + * Remove once we have readout for DSC.
> + */
> + if (crtc_state->dsc.compression_enable) {
> + drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
> + crtc_state->uapi.mode_changed = true;
> + return false;
> + }
> +
> + return true;
> +}
> +
> static void intel_disable_dp(struct intel_atomic_state *state,
> struct intel_encoder *encoder,
> const struct intel_crtc_state *old_crtc_state,
> @@ -8057,6 +8078,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
> intel_encoder->compute_config = intel_dp_compute_config;
> intel_encoder->get_hw_state = intel_dp_get_hw_state;
> intel_encoder->get_config = intel_dp_get_config;
> + intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
> intel_encoder->update_pipe = intel_panel_update_backlight;
> intel_encoder->suspend = intel_dp_encoder_suspend;
> if (IS_CHERRYVIEW(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 66854aab9887..977585aea3c8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -141,4 +141,7 @@ void intel_ddi_update_pipe(struct intel_atomic_state *state,
> int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
> struct intel_connector *intel_connector);
>
> +bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state);
> +
> #endif /* __INTEL_DP_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 82f38c386dbd..e948aacbd4ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -591,6 +591,15 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
> intel_ddi_get_config(&dig_port->base, pipe_config);
> }
>
> +static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state)
> +{
> + struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
> + struct intel_digital_port *dig_port = intel_mst->primary;
> +
> + return intel_dp_initial_fastset_check(&dig_port->base, crtc_state);
> +}
> +
> static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector)
> {
> struct intel_connector *intel_connector = to_intel_connector(connector);
> @@ -897,6 +906,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe
> intel_encoder->enable = intel_mst_enable_dp;
> intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
> intel_encoder->get_config = intel_dp_mst_enc_get_config;
> + intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;
>
> return intel_mst;
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH v3 2/5] drm/i915: Move the initial fastset commit check to encoder hooks
2020-10-06 9:42 ` Jani Nikula
@ 2020-10-06 9:55 ` Imre Deak
2020-10-06 10:00 ` Jani Nikula
0 siblings, 1 reply; 47+ messages in thread
From: Imre Deak @ 2020-10-06 9:55 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, Oct 06, 2020 at 12:42:58PM +0300, Jani Nikula wrote:
> On Tue, 06 Oct 2020, Imre Deak <imre.deak@intel.com> wrote:
> > Move the checks to decide whether a fastset is possible during the
> > initial commit to an encoder hook. This check is really encoder specific
> > and the next patch will also require this adding a DP encoder specific
> > check.
> >
> > v2: Fix negated condition in gen11_dsi_initial_fastset_check().
> > v3: Make sure to call the hook for all encoders on the crtc. (Ville)
> >
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/icl_dsi.c | 14 ++++++++++
> > drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++++++
> > drivers/gpu/drm/i915/display/intel_display.c | 27 ++++++++-----------
> > .../drm/i915/display/intel_display_types.h | 8 ++++++
> > drivers/gpu/drm/i915/display/intel_dp.c | 22 +++++++++++++++
> > drivers/gpu/drm/i915/display/intel_dp.h | 3 +++
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 +++++++
> > 7 files changed, 78 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index fe946a2e2082..4400e83f783f 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -1668,6 +1668,19 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
> > return ret;
> > }
> >
> > +static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder,
> > + struct intel_crtc_state *crtc_state)
> > +{
> > + if (crtc_state->dsc.compression_enable) {
> > + drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n");
> > + crtc_state->uapi.mode_changed = true;
>
> Just musing... if it's a *check*, why do we pass in a non-const
> crtc_state and modify it here?
>
> Would it not be cleaner to pass in const crtc_state and set
> crtc_state->uapi.mode_changed in the caller based on the return value?
The encoder can update the *_changed flags in crtc_state depending on
what is preventing a fastset.
>
> BR,
> Jani.
>
>
> > +
> > + return false;
> > + }
> > +
> > + return true;
> > +}
> > +
> > static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
> > {
> > intel_encoder_destroy(encoder);
> > @@ -1923,6 +1936,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
> > encoder->update_pipe = intel_panel_update_backlight;
> > encoder->compute_config = gen11_dsi_compute_config;
> > encoder->get_hw_state = gen11_dsi_get_hw_state;
> > + encoder->initial_fastset_check = gen11_dsi_initial_fastset_check;
> > encoder->type = INTEL_OUTPUT_DSI;
> > encoder->cloneable = 0;
> > encoder->pipe_mask = ~0;
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index b4c520348b3b..4e54c55ec99f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -4564,6 +4564,15 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> > intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
> > }
> >
> > +static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
> > + struct intel_crtc_state *crtc_state)
> > +{
> > + if (intel_crtc_has_dp_encoder(crtc_state))
> > + return intel_dp_initial_fastset_check(encoder, crtc_state);
> > +
> > + return true;
> > +}
> > +
> > static enum intel_output_type
> > intel_ddi_compute_output_type(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state,
> > @@ -5173,6 +5182,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> > encoder->update_pipe = intel_ddi_update_pipe;
> > encoder->get_hw_state = intel_ddi_get_hw_state;
> > encoder->get_config = intel_ddi_get_config;
> > + encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
> > encoder->suspend = intel_dp_encoder_suspend;
> > encoder->get_power_domains = intel_ddi_get_power_domains;
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 753f202ef6a0..755b83d47f9c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -17951,6 +17951,8 @@ static int intel_initial_commit(struct drm_device *dev)
> > }
> >
> > if (crtc_state->hw.active) {
> > + struct intel_encoder *encoder;
> > +
> > /*
> > * We've not yet detected sink capabilities
> > * (audio,infoframes,etc.) and thus we don't want to
> > @@ -17972,22 +17974,15 @@ static int intel_initial_commit(struct drm_device *dev)
> > */
> > crtc_state->uapi.color_mgmt_changed = true;
> >
> > - /*
> > - * FIXME hack to force full modeset when DSC is being
> > - * used.
> > - *
> > - * As long as we do not have full state readout and
> > - * config comparison of crtc_state->dsc, we have no way
> > - * to ensure reliable fastset. Remove once we have
> > - * readout for DSC.
> > - */
> > - if (crtc_state->dsc.compression_enable) {
> > - ret = drm_atomic_add_affected_connectors(state,
> > - &crtc->base);
> > - if (ret)
> > - goto out;
> > - crtc_state->uapi.mode_changed = true;
> > - drm_dbg_kms(dev, "Force full modeset for DSC\n");
> > + for_each_intel_encoder_mask(dev, encoder,
> > + crtc_state->uapi.encoder_mask) {
> > + if (encoder->initial_fastset_check &&
> > + !encoder->initial_fastset_check(encoder, crtc_state)) {
> > + ret = drm_atomic_add_affected_connectors(state,
> > + &crtc->base);
> > + if (ret)
> > + goto out;
> > + }
> > }
> > }
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index d5dc18cb8c39..5297b2f08ff9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -187,6 +187,14 @@ struct intel_encoder {
> > * be set correctly before calling this function. */
> > void (*get_config)(struct intel_encoder *,
> > struct intel_crtc_state *pipe_config);
> > +
> > + /*
> > + * Optional hook, returning true if this encoder allows a fastset
> > + * during the initial commit, false otherwise.
> > + */
> > + bool (*initial_fastset_check)(struct intel_encoder *encoder,
> > + struct intel_crtc_state *crtc_state);
> > +
> > /*
> > * Acquires the power domains needed for an active encoder during
> > * hardware state readout.
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 7429597b57be..d33a3d9fdc3a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -3703,6 +3703,27 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
> > }
> > }
> >
> > +bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> > + struct intel_crtc_state *crtc_state)
> > +{
> > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > +
> > + /*
> > + * FIXME hack to force full modeset when DSC is being used.
> > + *
> > + * As long as we do not have full state readout and config comparison
> > + * of crtc_state->dsc, we have no way to ensure reliable fastset.
> > + * Remove once we have readout for DSC.
> > + */
> > + if (crtc_state->dsc.compression_enable) {
> > + drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
> > + crtc_state->uapi.mode_changed = true;
> > + return false;
> > + }
> > +
> > + return true;
> > +}
> > +
> > static void intel_disable_dp(struct intel_atomic_state *state,
> > struct intel_encoder *encoder,
> > const struct intel_crtc_state *old_crtc_state,
> > @@ -8057,6 +8078,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
> > intel_encoder->compute_config = intel_dp_compute_config;
> > intel_encoder->get_hw_state = intel_dp_get_hw_state;
> > intel_encoder->get_config = intel_dp_get_config;
> > + intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
> > intel_encoder->update_pipe = intel_panel_update_backlight;
> > intel_encoder->suspend = intel_dp_encoder_suspend;
> > if (IS_CHERRYVIEW(dev_priv)) {
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> > index 66854aab9887..977585aea3c8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > @@ -141,4 +141,7 @@ void intel_ddi_update_pipe(struct intel_atomic_state *state,
> > int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
> > struct intel_connector *intel_connector);
> >
> > +bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> > + struct intel_crtc_state *crtc_state);
> > +
> > #endif /* __INTEL_DP_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index 82f38c386dbd..e948aacbd4ab 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -591,6 +591,15 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
> > intel_ddi_get_config(&dig_port->base, pipe_config);
> > }
> >
> > +static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,
> > + struct intel_crtc_state *crtc_state)
> > +{
> > + struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
> > + struct intel_digital_port *dig_port = intel_mst->primary;
> > +
> > + return intel_dp_initial_fastset_check(&dig_port->base, crtc_state);
> > +}
> > +
> > static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector)
> > {
> > struct intel_connector *intel_connector = to_intel_connector(connector);
> > @@ -897,6 +906,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe
> > intel_encoder->enable = intel_mst_enable_dp;
> > intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
> > intel_encoder->get_config = intel_dp_mst_enc_get_config;
> > + intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;
> >
> > return intel_mst;
>
> --
> Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH v3 2/5] drm/i915: Move the initial fastset commit check to encoder hooks
2020-10-06 9:55 ` Imre Deak
@ 2020-10-06 10:00 ` Jani Nikula
2020-10-06 10:05 ` Imre Deak
0 siblings, 1 reply; 47+ messages in thread
From: Jani Nikula @ 2020-10-06 10:00 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx
On Tue, 06 Oct 2020, Imre Deak <imre.deak@intel.com> wrote:
> On Tue, Oct 06, 2020 at 12:42:58PM +0300, Jani Nikula wrote:
>> On Tue, 06 Oct 2020, Imre Deak <imre.deak@intel.com> wrote:
>> > +static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder,
>> > + struct intel_crtc_state *crtc_state)
>> > +{
>> > + if (crtc_state->dsc.compression_enable) {
>> > + drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n");
>> > + crtc_state->uapi.mode_changed = true;
>>
>> Just musing... if it's a *check*, why do we pass in a non-const
>> crtc_state and modify it here?
>>
>> Would it not be cleaner to pass in const crtc_state and set
>> crtc_state->uapi.mode_changed in the caller based on the return value?
>
> The encoder can update the *_changed flags in crtc_state depending on
> what is preventing a fastset.
Okay... is this a good design? ;)
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH v3 2/5] drm/i915: Move the initial fastset commit check to encoder hooks
2020-10-06 10:00 ` Jani Nikula
@ 2020-10-06 10:05 ` Imre Deak
0 siblings, 0 replies; 47+ messages in thread
From: Imre Deak @ 2020-10-06 10:05 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, Oct 06, 2020 at 01:00:21PM +0300, Jani Nikula wrote:
> On Tue, 06 Oct 2020, Imre Deak <imre.deak@intel.com> wrote:
> > On Tue, Oct 06, 2020 at 12:42:58PM +0300, Jani Nikula wrote:
> >> On Tue, 06 Oct 2020, Imre Deak <imre.deak@intel.com> wrote:
> >> > +static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder,
> >> > + struct intel_crtc_state *crtc_state)
> >> > +{
> >> > + if (crtc_state->dsc.compression_enable) {
> >> > + drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n");
> >> > + crtc_state->uapi.mode_changed = true;
> >>
> >> Just musing... if it's a *check*, why do we pass in a non-const
> >> crtc_state and modify it here?
> >>
> >> Would it not be cleaner to pass in const crtc_state and set
> >> crtc_state->uapi.mode_changed in the caller based on the return value?
> >
> > The encoder can update the *_changed flags in crtc_state depending on
> > what is preventing a fastset.
>
> Okay... is this a good design? ;)
That's how atomic_check hooks work..
>
> BR,
> Jani.
>
>
> --
> Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6)
2020-10-06 2:39 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6) Patchwork
@ 2020-10-06 10:32 ` Imre Deak
2020-10-06 11:04 ` Imre Deak
0 siblings, 1 reply; 47+ messages in thread
From: Imre Deak @ 2020-10-06 10:32 UTC (permalink / raw)
To: intel-gfx
On Tue, Oct 06, 2020 at 02:39:51AM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6)
> URL : https://patchwork.freedesktop.org/series/82173/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_9098_full -> Patchwork_18629_full
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_18629_full absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_18629_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_18629_full:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@gem_softpin@softpin:
> - shard-iclb: [PASS][1] -> [DMESG-WARN][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-iclb6/igt@gem_softpin@softpin.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-iclb1/igt@gem_softpin@softpin.html
Not sure where this comes from, looks like a GEM related issue. Can't
see how it would be related to the patchset, since the initial modeset
sequence in the log is not affected and the rest of PLL the changes are
TGL specific.
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_18629_full that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@gem_exec_reloc@basic-many-active@vecs0:
> - shard-glk: [PASS][3] -> [FAIL][4] ([i915#2389])
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-glk4/igt@gem_exec_reloc@basic-many-active@vecs0.html
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-glk6/igt@gem_exec_reloc@basic-many-active@vecs0.html
>
> * igt@kms_cursor_legacy@all-pipes-torture-bo:
> - shard-tglb: [PASS][5] -> [DMESG-WARN][6] ([i915#128])
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-tglb3/igt@kms_cursor_legacy@all-pipes-torture-bo.html
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-tglb7/igt@kms_cursor_legacy@all-pipes-torture-bo.html
>
> * igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2:
> - shard-glk: [PASS][7] -> [FAIL][8] ([i915#79])
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html
>
> * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
> - shard-skl: [PASS][9] -> [FAIL][10] ([i915#79]) +1 similar issue
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
>
> * igt@kms_flip@flip-vs-suspend@c-dp1:
> - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +3 similar issues
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-kbl6/igt@kms_flip@flip-vs-suspend@c-dp1.html
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-kbl4/igt@kms_flip@flip-vs-suspend@c-dp1.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render:
> - shard-tglb: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +2 similar issues
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render.html
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render.html
>
> * igt@kms_hdr@bpc-switch-suspend:
> - shard-skl: [PASS][15] -> [FAIL][16] ([i915#1188])
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl10/igt@kms_hdr@bpc-switch-suspend.html
> [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl1/igt@kms_hdr@bpc-switch-suspend.html
>
> * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
> - shard-skl: [PASS][17] -> [INCOMPLETE][18] ([i915#198])
> [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl9/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
> [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
>
> * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
> - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [i915#265])
> [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
>
> * igt@kms_psr@psr2_cursor_plane_move:
> - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +1 similar issue
> [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
> [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-iclb5/igt@kms_psr@psr2_cursor_plane_move.html
>
> * igt@kms_setmode@basic:
> - shard-glk: [PASS][23] -> [FAIL][24] ([i915#31])
> [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-glk4/igt@kms_setmode@basic.html
> [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-glk1/igt@kms_setmode@basic.html
>
> * igt@kms_vblank@pipe-a-ts-continuation-dpms-rpm:
> - shard-skl: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) +11 similar issues
> [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl5/igt@kms_vblank@pipe-a-ts-continuation-dpms-rpm.html
> [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl4/igt@kms_vblank@pipe-a-ts-continuation-dpms-rpm.html
>
> * igt@kms_vblank@pipe-b-wait-forked-busy:
> - shard-apl: [PASS][27] -> [DMESG-WARN][28] ([i915#1635] / [i915#1982]) +2 similar issues
> [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-apl4/igt@kms_vblank@pipe-b-wait-forked-busy.html
> [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-apl3/igt@kms_vblank@pipe-b-wait-forked-busy.html
>
>
> #### Possible fixes ####
>
> * igt@gem_userptr_blits@unsync-unmap-cycles:
> - shard-skl: [TIMEOUT][29] ([i915#2424]) -> [PASS][30]
> [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl1/igt@gem_userptr_blits@unsync-unmap-cycles.html
> [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl9/igt@gem_userptr_blits@unsync-unmap-cycles.html
>
> * {igt@kms_async_flips@async-flip-with-page-flip-events}:
> - shard-glk: [FAIL][31] ([i915#2521]) -> [PASS][32]
> [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-glk9/igt@kms_async_flips@async-flip-with-page-flip-events.html
> [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-glk7/igt@kms_async_flips@async-flip-with-page-flip-events.html
>
> * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
> - shard-glk: [FAIL][33] ([i915#72]) -> [PASS][34]
> [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-glk9/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
> [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-glk7/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
>
> * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled:
> - shard-glk: [DMESG-WARN][35] ([i915#1982]) -> [PASS][36]
> [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-glk9/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled.html
> [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-glk7/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled.html
>
> * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1:
> - shard-glk: [FAIL][37] ([i915#2122]) -> [PASS][38]
> [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1.html
> [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-glk7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1.html
>
> * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
> - shard-kbl: [DMESG-WARN][39] ([i915#180]) -> [PASS][40] +6 similar issues
> [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
> [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
> - shard-tglb: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] +1 similar issue
> [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
> [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
>
> * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
> - shard-skl: [INCOMPLETE][43] ([i915#198]) -> [PASS][44]
> [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl10/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
> [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
>
> * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
> - shard-skl: [FAIL][45] ([fdo#108145] / [i915#265]) -> [PASS][46]
> [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
> [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
>
> * igt@kms_psr@psr2_basic:
> - shard-iclb: [SKIP][47] ([fdo#109441]) -> [PASS][48] +1 similar issue
> [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-iclb1/igt@kms_psr@psr2_basic.html
> [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-iclb2/igt@kms_psr@psr2_basic.html
>
> * igt@perf_pmu@module-unload:
> - shard-apl: [DMESG-WARN][49] ([i915#1635] / [i915#1982]) -> [PASS][50]
> [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-apl1/igt@perf_pmu@module-unload.html
> [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-apl4/igt@perf_pmu@module-unload.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
> [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
> [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
> [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128
> [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
> [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
> [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
> [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
> [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
> [i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
> [i915#2424]: https://gitlab.freedesktop.org/drm/intel/issues/2424
> [i915#2469]: https://gitlab.freedesktop.org/drm/intel/issues/2469
> [i915#2476]: https://gitlab.freedesktop.org/drm/intel/issues/2476
> [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
> [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
> [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
> [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
> [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
>
>
> Participating hosts (11 -> 12)
> ------------------------------
>
> Additional (1): pig-snb-2600
>
>
> Build changes
> -------------
>
> * Linux: CI_DRM_9098 -> Patchwork_18629
>
> CI-20190529: 20190529
> CI_DRM_9098: 877045337ceb241797ac16226a1f2f76b3553d1d @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_5800: 982ca4122fd4f04ad3dfa80c6246f190b36e0c72 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_18629: f3685bccf1c82e3f7abefc8732655b3ee9395c39 @ git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6)
2020-10-06 10:32 ` Imre Deak
@ 2020-10-06 11:04 ` Imre Deak
0 siblings, 0 replies; 47+ messages in thread
From: Imre Deak @ 2020-10-06 11:04 UTC (permalink / raw)
To: intel-gfx, Ville Syrjälä
On Tue, Oct 06, 2020 at 01:32:58PM +0300, Imre Deak wrote:
> On Tue, Oct 06, 2020 at 02:39:51AM +0000, Patchwork wrote:
> > == Series Details ==
> >
> > Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6)
> > URL : https://patchwork.freedesktop.org/series/82173/
> > State : failure
Thanks for the review, pushed to drm-tip.
> >
> > == Summary ==
> >
> > CI Bug Log - changes from CI_DRM_9098_full -> Patchwork_18629_full
> > ====================================================
> >
> > Summary
> > -------
> >
> > **FAILURE**
> >
> > Serious unknown changes coming with Patchwork_18629_full absolutely need to be
> > verified manually.
> >
> > If you think the reported changes have nothing to do with the changes
> > introduced in Patchwork_18629_full, please notify your bug team to allow them
> > to document this new failure mode, which will reduce false positives in CI.
> >
> >
> >
> > Possible new issues
> > -------------------
> >
> > Here are the unknown changes that may have been introduced in Patchwork_18629_full:
> >
> > ### IGT changes ###
> >
> > #### Possible regressions ####
> >
> > * igt@gem_softpin@softpin:
> > - shard-iclb: [PASS][1] -> [DMESG-WARN][2]
> > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-iclb6/igt@gem_softpin@softpin.html
> > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-iclb1/igt@gem_softpin@softpin.html
>
> Not sure where this comes from, looks like a GEM related issue. Can't
> see how it would be related to the patchset, since the initial modeset
> sequence in the log is not affected and the rest of PLL the changes are
> TGL specific.
>
> >
> >
> > Known issues
> > ------------
> >
> > Here are the changes found in Patchwork_18629_full that come from known issues:
> >
> > ### IGT changes ###
> >
> > #### Issues hit ####
> >
> > * igt@gem_exec_reloc@basic-many-active@vecs0:
> > - shard-glk: [PASS][3] -> [FAIL][4] ([i915#2389])
> > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-glk4/igt@gem_exec_reloc@basic-many-active@vecs0.html
> > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-glk6/igt@gem_exec_reloc@basic-many-active@vecs0.html
> >
> > * igt@kms_cursor_legacy@all-pipes-torture-bo:
> > - shard-tglb: [PASS][5] -> [DMESG-WARN][6] ([i915#128])
> > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-tglb3/igt@kms_cursor_legacy@all-pipes-torture-bo.html
> > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-tglb7/igt@kms_cursor_legacy@all-pipes-torture-bo.html
> >
> > * igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2:
> > - shard-glk: [PASS][7] -> [FAIL][8] ([i915#79])
> > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html
> > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html
> >
> > * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
> > - shard-skl: [PASS][9] -> [FAIL][10] ([i915#79]) +1 similar issue
> > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
> > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
> >
> > * igt@kms_flip@flip-vs-suspend@c-dp1:
> > - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +3 similar issues
> > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-kbl6/igt@kms_flip@flip-vs-suspend@c-dp1.html
> > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-kbl4/igt@kms_flip@flip-vs-suspend@c-dp1.html
> >
> > * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render:
> > - shard-tglb: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +2 similar issues
> > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render.html
> > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render.html
> >
> > * igt@kms_hdr@bpc-switch-suspend:
> > - shard-skl: [PASS][15] -> [FAIL][16] ([i915#1188])
> > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl10/igt@kms_hdr@bpc-switch-suspend.html
> > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl1/igt@kms_hdr@bpc-switch-suspend.html
> >
> > * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
> > - shard-skl: [PASS][17] -> [INCOMPLETE][18] ([i915#198])
> > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl9/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
> > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
> >
> > * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
> > - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [i915#265])
> > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
> > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
> >
> > * igt@kms_psr@psr2_cursor_plane_move:
> > - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +1 similar issue
> > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
> > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-iclb5/igt@kms_psr@psr2_cursor_plane_move.html
> >
> > * igt@kms_setmode@basic:
> > - shard-glk: [PASS][23] -> [FAIL][24] ([i915#31])
> > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-glk4/igt@kms_setmode@basic.html
> > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-glk1/igt@kms_setmode@basic.html
> >
> > * igt@kms_vblank@pipe-a-ts-continuation-dpms-rpm:
> > - shard-skl: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) +11 similar issues
> > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl5/igt@kms_vblank@pipe-a-ts-continuation-dpms-rpm.html
> > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl4/igt@kms_vblank@pipe-a-ts-continuation-dpms-rpm.html
> >
> > * igt@kms_vblank@pipe-b-wait-forked-busy:
> > - shard-apl: [PASS][27] -> [DMESG-WARN][28] ([i915#1635] / [i915#1982]) +2 similar issues
> > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-apl4/igt@kms_vblank@pipe-b-wait-forked-busy.html
> > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-apl3/igt@kms_vblank@pipe-b-wait-forked-busy.html
> >
> >
> > #### Possible fixes ####
> >
> > * igt@gem_userptr_blits@unsync-unmap-cycles:
> > - shard-skl: [TIMEOUT][29] ([i915#2424]) -> [PASS][30]
> > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl1/igt@gem_userptr_blits@unsync-unmap-cycles.html
> > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl9/igt@gem_userptr_blits@unsync-unmap-cycles.html
> >
> > * {igt@kms_async_flips@async-flip-with-page-flip-events}:
> > - shard-glk: [FAIL][31] ([i915#2521]) -> [PASS][32]
> > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-glk9/igt@kms_async_flips@async-flip-with-page-flip-events.html
> > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-glk7/igt@kms_async_flips@async-flip-with-page-flip-events.html
> >
> > * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
> > - shard-glk: [FAIL][33] ([i915#72]) -> [PASS][34]
> > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-glk9/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
> > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-glk7/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
> >
> > * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled:
> > - shard-glk: [DMESG-WARN][35] ([i915#1982]) -> [PASS][36]
> > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-glk9/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled.html
> > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-glk7/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled.html
> >
> > * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1:
> > - shard-glk: [FAIL][37] ([i915#2122]) -> [PASS][38]
> > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1.html
> > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-glk7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1.html
> >
> > * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
> > - shard-kbl: [DMESG-WARN][39] ([i915#180]) -> [PASS][40] +6 similar issues
> > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
> > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
> >
> > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
> > - shard-tglb: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] +1 similar issue
> > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
> > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
> >
> > * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
> > - shard-skl: [INCOMPLETE][43] ([i915#198]) -> [PASS][44]
> > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl10/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
> > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
> >
> > * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
> > - shard-skl: [FAIL][45] ([fdo#108145] / [i915#265]) -> [PASS][46]
> > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
> > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
> >
> > * igt@kms_psr@psr2_basic:
> > - shard-iclb: [SKIP][47] ([fdo#109441]) -> [PASS][48] +1 similar issue
> > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-iclb1/igt@kms_psr@psr2_basic.html
> > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-iclb2/igt@kms_psr@psr2_basic.html
> >
> > * igt@perf_pmu@module-unload:
> > - shard-apl: [DMESG-WARN][49] ([i915#1635] / [i915#1982]) -> [PASS][50]
> > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-apl1/igt@perf_pmu@module-unload.html
> > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-apl4/igt@perf_pmu@module-unload.html
> >
> >
> > {name}: This element is suppressed. This means it is ignored when computing
> > the status of the difference (SUCCESS, WARNING, or FAILURE).
> >
> > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
> > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
> > [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
> > [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128
> > [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
> > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
> > [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
> > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
> > [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
> > [i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
> > [i915#2424]: https://gitlab.freedesktop.org/drm/intel/issues/2424
> > [i915#2469]: https://gitlab.freedesktop.org/drm/intel/issues/2469
> > [i915#2476]: https://gitlab.freedesktop.org/drm/intel/issues/2476
> > [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
> > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
> > [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
> > [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
> > [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
> >
> >
> > Participating hosts (11 -> 12)
> > ------------------------------
> >
> > Additional (1): pig-snb-2600
> >
> >
> > Build changes
> > -------------
> >
> > * Linux: CI_DRM_9098 -> Patchwork_18629
> >
> > CI-20190529: 20190529
> > CI_DRM_9098: 877045337ceb241797ac16226a1f2f76b3553d1d @ git://anongit.freedesktop.org/gfx-ci/linux
> > IGT_5800: 982ca4122fd4f04ad3dfa80c6246f190b36e0c72 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> > Patchwork_18629: f3685bccf1c82e3f7abefc8732655b3ee9395c39 @ git://anongit.freedesktop.org/gfx-ci/linux
> > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
> >
> > == Logs ==
> >
> > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/index.html
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
end of thread, other threads:[~2020-10-06 11:04 UTC | newest]
Thread overview: 47+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-03 0:18 [Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
2020-10-03 0:18 ` [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming Imre Deak
2020-10-05 20:08 ` Ville Syrjälä
2020-10-05 20:26 ` Imre Deak
2020-10-05 23:37 ` Ville Syrjälä
2020-10-06 1:24 ` Imre Deak
2020-10-06 1:35 ` [Intel-gfx] [PATCH v3 " Imre Deak
2020-10-06 8:59 ` Ville Syrjälä
2020-10-03 0:18 ` [Intel-gfx] [PATCH 2/5] drm/i915: Move the initial fastset commit check to encoder hooks Imre Deak
2020-10-03 1:07 ` [Intel-gfx] [PATCH v2 " Imre Deak
2020-10-05 20:24 ` Ville Syrjälä
2020-10-05 20:34 ` Imre Deak
2020-10-05 21:53 ` [Intel-gfx] [PATCH v3 " Imre Deak
2020-10-06 9:42 ` Jani Nikula
2020-10-06 9:55 ` Imre Deak
2020-10-06 10:00 ` Jani Nikula
2020-10-06 10:05 ` Imre Deak
2020-10-03 0:18 ` [Intel-gfx] [PATCH 3/5] drm/i915: Check for unsupported DP link rates during initial commit Imre Deak
2020-10-05 20:25 ` Ville Syrjälä
2020-10-03 0:18 ` [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume Imre Deak
2020-10-05 20:30 ` Ville Syrjälä
2020-10-05 20:46 ` Imre Deak
2020-10-05 23:39 ` Ville Syrjälä
2020-10-05 20:40 ` Ville Syrjälä
2020-10-05 20:57 ` Imre Deak
2020-10-05 20:51 ` Ville Syrjälä
2020-10-05 23:00 ` Imre Deak
2020-10-05 21:53 ` [Intel-gfx] [PATCH v2 " Imre Deak
2020-10-05 23:01 ` [Intel-gfx] [PATCH v3 " Imre Deak
2020-10-06 8:58 ` Ville Syrjälä
2020-10-03 0:18 ` [Intel-gfx] [PATCH 5/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
2020-10-03 0:40 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev2) Patchwork
2020-10-03 0:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-03 1:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3) Patchwork
2020-10-03 1:52 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-03 3:56 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-10-03 13:48 ` Imre Deak
2020-10-04 6:12 ` Vudum, Lakshminarayana
2020-10-04 5:47 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
2020-10-06 0:01 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6) Patchwork
2020-10-06 0:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-06 1:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7) Patchwork
2020-10-06 2:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-06 2:39 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6) Patchwork
2020-10-06 10:32 ` Imre Deak
2020-10-06 11:04 ` Imre Deak
2020-10-06 5:39 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7) Patchwork
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