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From: Ben Widawsky <ben.widawsky@intel.com>
To: qemu-devel@nongnu.org
Cc: Vishal Verma <vishal.l.verma@intel.com>,
	Dan Williams <dan.j.williams@intel.com>,
	Igor Mammedov <imammedo@redhat.com>,
	"Michael S. Tsirkin" <mst@redhat.com>
Subject: [RFC PATCH 21/25] acpi/cxl: Introduce a compat-driver UUID for CXL _OSC
Date: Tue, 10 Nov 2020 21:47:20 -0800	[thread overview]
Message-ID: <20201111054724.794888-22-ben.widawsky@intel.com> (raw)
In-Reply-To: <20201111054724.794888-1-ben.widawsky@intel.com>

From: Vishal Verma <vishal.l.verma@intel.com>

Introduce a new UUID for CXL _OSC that only sets CXL related 'Support'
and Control' Dwords, independent of PCI/PCIe Dwords. This is a proposal
and an example AML implementation to demonstrate what such a compat UUID
would look like.

The AML resulting from this change is:

        Method (_OSC, 4, NotSerialized)  // _OSC: Operating System Capabilities
        {
            CreateDWordField (Arg3, Zero, CDW1)
            If ((((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */) || (Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc"))) || (
                Arg0 == ToUUID ("a4d1629d-ff52-4888-be96-e5cade548db1"))))
            {
                If ((Arg0 == ToUUID ("a4d1629d-ff52-4888-be96-e5cade548db1")))
                {
                    CreateDWordField (Arg3, 0x04, CDW2)
                    CreateDWordField (Arg3, 0x08, CDW3)
                    SUPC = CDW2 /* \_SB_.CXL0._OSC.CDW2 */
                    CTRC = CDW3 /* \_SB_.CXL0._OSC.CDW3 */
                    CDW3 |= One
                    Return (Arg3)
                }
                Else
                {
                    CreateDWordField (Arg3, 0x04, CDW2)
                    CreateDWordField (Arg3, 0x08, CDW3)
                    Local0 = CDW3 /* \_SB_.CXL0._OSC.CDW3 */
                    CTRL &= 0x1F
                    If ((Arg1 != One))
                    {
                        CDW1 |= 0x08
                    }

                    If ((CDW3 != Local0))
                    {
                        CDW1 |= 0x10
                    }

                    SUPP = CDW2 /* \_SB_.CXL0._OSC.CDW2 */
                    CTRL = CDW3 /* \_SB_.CXL0._OSC.CDW3 */
                    If ((Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc")))
                    {
                        CreateDWordField (Arg3, 0x0C, CDW4)
                        CreateDWordField (Arg3, 0x10, CDW5)
                        SUPC = CDW4 /* \_SB_.CXL0._OSC.CDW4 */
                        CTRC = CDW5 /* \_SB_.CXL0._OSC.CDW5 */
                        CDW5 |= One
                    }

                    CDW3 = Local0
                    Return (Arg3)
                }
            }

            Return (Arg3)
            Else
            {
                CDW1 |= 0x04
            }
        }

Signed-off-by: Vishal Verma <vishal.l.verma@intel.com>
---
 hw/acpi/cxl.c | 54 ++++++++++++++++++++++++++++++++++++---------------
 1 file changed, 38 insertions(+), 16 deletions(-)

diff --git a/hw/acpi/cxl.c b/hw/acpi/cxl.c
index 7124d5a1a3..31ceaeecc3 100644
--- a/hw/acpi/cxl.c
+++ b/hw/acpi/cxl.c
@@ -29,6 +29,7 @@
 static Aml *__build_cxl_osc_method(void)
 {
     Aml *method, *if_uuid, *else_uuid, *if_arg1_not_1, *if_cxl, *if_caps_masked;
+    Aml *if_compat, *else_nocompat;
     Aml *a_ctrl = aml_local(0);
     Aml *a_cdw1 = aml_name("CDW1");
 
@@ -37,31 +38,51 @@ static Aml *__build_cxl_osc_method(void)
 
     /* 9.14.2.1.4 */
     if_uuid = aml_if(
-        aml_lor(aml_equal(aml_arg(0),
+        aml_lor(
+            aml_lor(aml_equal(aml_arg(0),
                           aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")),
-                aml_equal(aml_arg(0),
-                          aml_touuid("68F2D50B-C469-4D8A-BD3D-941A103FD3FC"))));
-    aml_append(if_uuid, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
-    aml_append(if_uuid, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
-
-    aml_append(if_uuid, aml_store(aml_name("CDW3"), a_ctrl));
+                    aml_equal(aml_arg(0),
+                          aml_touuid("68F2D50B-C469-4D8A-BD3D-941A103FD3FC"))),
+                    aml_equal(aml_arg(0),
+                          aml_touuid("A4D1629D-FF52-4888-BE96-E5CADE548DB1"))));
+
+    if_compat = aml_if(aml_equal(aml_arg(0),
+                          aml_touuid("A4D1629D-FF52-4888-BE96-E5CADE548DB1")));
+    aml_append(if_compat,
+               aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
+    aml_append(if_compat,
+               aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
+    aml_append(if_compat, aml_store(aml_name("CDW2"), aml_name("SUPC")));
+    aml_append(if_compat, aml_store(aml_name("CDW3"), aml_name("CTRC")));
+    aml_append(if_compat,
+               aml_or(aml_name("CDW3"), aml_int(0x1), aml_name("CDW3")));
+    aml_append(if_compat, aml_return(aml_arg(3)));
+    aml_append(if_uuid, if_compat);
+
+    else_nocompat = aml_else();
+    aml_append(else_nocompat,
+               aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
+    aml_append(else_nocompat,
+               aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
+
+    aml_append(else_nocompat, aml_store(aml_name("CDW3"), a_ctrl));
 
     /* This is all the same as what's used for PCIe */
-    aml_append(if_uuid,
+    aml_append(else_nocompat,
                aml_and(aml_name("CTRL"), aml_int(0x1F), aml_name("CTRL")));
 
     if_arg1_not_1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
     /* Unknown revision */
     aml_append(if_arg1_not_1, aml_or(a_cdw1, aml_int(0x08), a_cdw1));
-    aml_append(if_uuid, if_arg1_not_1);
+    aml_append(else_nocompat, if_arg1_not_1);
 
     if_caps_masked = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
     /* Capability bits were masked */
     aml_append(if_caps_masked, aml_or(a_cdw1, aml_int(0x10), a_cdw1));
-    aml_append(if_uuid, if_caps_masked);
+    aml_append(else_nocompat, if_caps_masked);
 
-    aml_append(if_uuid, aml_store(aml_name("CDW2"), aml_name("SUPP")));
-    aml_append(if_uuid, aml_store(aml_name("CDW3"), aml_name("CTRL")));
+    aml_append(else_nocompat, aml_store(aml_name("CDW2"), aml_name("SUPP")));
+    aml_append(else_nocompat, aml_store(aml_name("CDW3"), aml_name("CTRL")));
 
     if_cxl = aml_if(aml_equal(
         aml_arg(0), aml_touuid("68F2D50B-C469-4D8A-BD3D-941A103FD3FC")));
@@ -75,12 +96,13 @@ static Aml *__build_cxl_osc_method(void)
     /* CXL 2.0 Port/Device Register access */
     aml_append(if_cxl,
                aml_or(aml_name("CDW5"), aml_int(0x1), aml_name("CDW5")));
-    aml_append(if_uuid, if_cxl);
+    aml_append(else_nocompat, if_cxl);
 
     /* Update DWORD3 (the return value) */
-    aml_append(if_uuid, aml_store(a_ctrl, aml_name("CDW3")));
+    aml_append(else_nocompat, aml_store(a_ctrl, aml_name("CDW3")));
 
-    aml_append(if_uuid, aml_return(aml_arg(3)));
+    aml_append(else_nocompat, aml_return(aml_arg(3)));
+    aml_append(if_uuid, else_nocompat);
     aml_append(method, if_uuid);
 
     else_uuid = aml_else();
@@ -88,7 +110,7 @@ static Aml *__build_cxl_osc_method(void)
     /* unrecognized uuid */
     aml_append(else_uuid,
                aml_or(aml_name("CDW1"), aml_int(0x4), aml_name("CDW1")));
-    aml_append(else_uuid, aml_return(aml_arg(3)));
+    aml_append(method, aml_return(aml_arg(3)));
     aml_append(method, else_uuid);
 
     return method;
-- 
2.29.2



  parent reply	other threads:[~2020-11-11  5:58 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-11  5:46 [RFC PATCH 00/25] Introduce CXL 2.0 Emulation Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 01/25] Temp: Add the PCI_EXT_ID_DVSEC definition to the qemu pci_regs.h copy Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 02/25] hw/pci/cxl: Add a CXL component type (interface) Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 03/25] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5) Ben Widawsky
2020-11-16 12:03   ` Jonathan Cameron
2020-11-16 19:19     ` Ben Widawsky
2020-11-17 12:29       ` Jonathan Cameron
2020-11-24 23:09         ` Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 04/25] hw/cxl/device: Introduce a CXL device (8.2.8) Ben Widawsky
2020-11-16 13:07   ` Jonathan Cameron
2020-11-16 21:11     ` Ben Widawsky
2020-11-17 14:21       ` Jonathan Cameron
2020-11-11  5:47 ` [RFC PATCH 05/25] hw/cxl/device: Implement the CAP array (8.2.8.1-2) Ben Widawsky
2020-11-16 13:11   ` Jonathan Cameron
2020-11-16 18:08     ` Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 06/25] hw/cxl/device: Add device status (8.2.8.3) Ben Widawsky
2020-11-16 13:16   ` Jonathan Cameron
2020-11-16 21:18     ` Ben Widawsky
2020-11-17 14:24       ` Jonathan Cameron
2020-11-11  5:47 ` [RFC PATCH 07/25] hw/cxl/device: Implement basic mailbox (8.2.8.4) Ben Widawsky
2020-11-16 13:46   ` Jonathan Cameron
2020-11-16 21:42     ` Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 08/25] hw/cxl/device: Add memory devices (8.2.8.5) Ben Widawsky
2020-11-16 16:37   ` Jonathan Cameron
2020-11-16 21:45     ` Ben Widawsky
2020-11-17 14:31       ` Jonathan Cameron
2020-11-11  5:47 ` [RFC PATCH 09/25] hw/pxb: Use a type for realizing expanders Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 10/25] hw/pci/cxl: Create a CXL bus type Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 11/25] hw/pxb: Allow creation of a CXL PXB (host bridge) Ben Widawsky
2020-11-16 16:44   ` Jonathan Cameron
2020-11-16 22:01     ` Ben Widawsky
2020-11-17 14:33       ` Jonathan Cameron
2020-11-11  5:47 ` [RFC PATCH 12/25] acpi/pci: Consolidate host bridge setup Ben Widawsky
2020-11-12 17:46   ` Ben Widawsky
2020-11-16 16:45   ` Jonathan Cameron
2020-11-11  5:47 ` [RFC PATCH 13/25] hw/pci: Plumb _UID through host bridges Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 14/25] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142) Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 15/25] acpi/pxb/cxl: Reserve host bridge MMIO Ben Widawsky
2020-11-16 16:54   ` Jonathan Cameron
2020-11-11  5:47 ` [RFC PATCH 16/25] hw/pxb/cxl: Add "windows" for host bridges Ben Widawsky
2020-11-13  0:49   ` Ben Widawsky
2020-11-23 19:12     ` Philippe Mathieu-Daudé
2020-11-11  5:47 ` [RFC PATCH 17/25] hw/cxl/rp: Add a root port Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 18/25] hw/cxl/device: Add a memory device (8.2.8.5) Ben Widawsky
2020-11-12 18:37   ` Eric Blake
2020-11-13  7:47     ` Markus Armbruster
2020-11-25 16:53       ` Ben Widawsky
2020-11-26  6:36         ` Markus Armbruster
2020-11-30 17:07           ` Ben Widawsky
2020-12-01 17:06             ` Markus Armbruster
2020-11-11  5:47 ` [RFC PATCH 19/25] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12) Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 20/25] acpi/cxl: Add _OSC implementation (9.14.2) Ben Widawsky
2020-11-11  5:47 ` Ben Widawsky [this message]
2020-11-11  5:47 ` [RFC PATCH 22/25] acpi/cxl: Create the CEDT (9.14.1) Ben Widawsky
2020-11-16 17:15   ` Jonathan Cameron
2020-11-16 22:05     ` Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 23/25] Temp: acpi/cxl: Add ACPI0017 (CEDT awareness) Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 24/25] WIP: i386/cxl: Initialize a host bridge Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 25/25] qtest/cxl: Add very basic sanity tests Ben Widawsky
2020-11-16 17:21 ` [RFC PATCH 00/25] Introduce CXL 2.0 Emulation Jonathan Cameron
2020-11-16 18:06   ` Ben Widawsky
2020-11-17 14:09     ` Jonathan Cameron
2020-11-25 18:29       ` Ben Widawsky
2020-12-04 14:27 ` Daniel P. Berrangé

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