All of lore.kernel.org
 help / color / mirror / Atom feed
From: Markus Armbruster <armbru@redhat.com>
To: Ben Widawsky <ben@bwidawsk.net>
Cc: Eduardo Habkost <ehabkost@redhat.com>,
	"Michael S. Tsirkin" <mst@redhat.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	qemu-devel@nongnu.org,
	"Dr. David Alan Gilbert" <dgilbert@redhat.com>,
	Igor Mammedov <imammedo@redhat.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Dan Williams <dan.j.williams@intel.com>,
	Richard Henderson <rth@twiddle.net>
Subject: Re: [RFC PATCH 18/25] hw/cxl/device: Add a memory device (8.2.8.5)
Date: Tue, 01 Dec 2020 18:06:41 +0100	[thread overview]
Message-ID: <878saha21q.fsf@dusky.pond.sub.org> (raw)
In-Reply-To: <20201130170730.o5fkrpaubwcroz4y@mail.bwidawsk.net> (Ben Widawsky's message of "Mon, 30 Nov 2020 09:07:30 -0800")

Ben Widawsky <ben@bwidawsk.net> writes:

> On 20-11-26 07:36:23, Markus Armbruster wrote:
>> Ben Widawsky <ben.widawsky@intel.com> writes:
>> 
>> > On 20-11-13 08:47:59, Markus Armbruster wrote:
>> >> Eric Blake <eblake@redhat.com> writes:
>> >> 
>> >> > On 11/10/20 11:47 PM, Ben Widawsky wrote:
>> >> >> A CXL memory device (AKA Type 3) is a CXL component that contains some
>> >> >> combination of volatile and persistent memory. It also implements the
>> >> >> previously defined mailbox interface as well as the memory device
>> >> >> firmware interface.
>> >> >> 
>> >> >> The following example will create a 256M device in a 512M window:
>> >> >> 
>> >> >> -object "memory-backend-file,id=cxl-mem1,share,mem-path=cxl-type3,size=512M"
>> >> >> -device "cxl-type3,bus=rp0,memdev=cxl-mem1,id=cxl-pmem0,size=256M"
>> >> >> 
>> >> >> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
>> >> >> ---
>> >> >
>> >> >> +++ b/qapi/machine.json
>> >> >> @@ -1394,6 +1394,7 @@
>> >> >>  { 'union': 'MemoryDeviceInfo',
>> >> >>    'data': { 'dimm': 'PCDIMMDeviceInfo',
>> >> >>              'nvdimm': 'PCDIMMDeviceInfo',
>> >> >> +            'cxl': 'PCDIMMDeviceInfo',
>> >> >>              'virtio-pmem': 'VirtioPMEMDeviceInfo',
>> >> >>              'virtio-mem': 'VirtioMEMDeviceInfo'
>> >> >>            }
>> >> >
>> >> > Missing documentation of the new data type, and the fact that it will be
>> >> > introduced in 6.0.
>> >> 
>> >> Old wish list item: improve the QAPI schema frontend to flag this.
>> >> 
>> >
>> > "Introduced in 6.0" - quite the optimist. Kidding aside, this is the area where
>> > I could use some feedback. CXL Type 3 memory devices can contain both volatile
>> > and persistent memory at the same time. As such, I think I'll need a new type to
>> > represent that, but I'd love to know how best to accomplish that.
>> 
>> We can help.  Tell us what information you want to provide in variant
>> 'cxl'.  If it's a superset of an existing variant, give us just the
>> delta.
>> 
>
> I'm not exactly sure what the best way to do this is in QEMU, so I'm not really
> sure what to specify as the delta. A CXL memory device can have both volatile
> and persistent memory. Currently when a CXL memory device implements the
> TYPE_MEMORY_DEVICE interface. So I believe the shortest path is a
> MemoryDeviceInfo that can have two memory devices associated with it, but I
> don't know if that's the best path.

Perhaps a CXL device should contain two sub-devices implementing
TYPE_MEMORY_DEVICE.  Paolo, what do you think?

If yes, one of the existing variants fits the bill, I guess.

If no, I have more ramblings to offer.

query-memory-devices returns a MemoryDeviceInfo for each realized device
that implements interface TYPE_MEMORY_DEVICE.  The interface provides
callback ->fill_device_info() to fill in the MemoryDeviceInfo.  This is
its only use.

This means TYPE_MEMORY_DEVICE places no obvious constraints on how the
callbacks use MemoryDeviceInfo.  Each callback can pick whatever variant
it wants.  This also means *your* callback can pick a new one, which you
define however you want.

What if there are unobvious (and unwritten) constraints?

The existing variants overlap:

* All provide the device's ID: optional member @id

* All provide a physical address (base address, I supposed) and size,
  but the member names differ (argh!): @addr, @size vs. @memaddr, @size

* All provide the memory backend: member @memdev

The members that overlap by necessity (i.e. any conceivable
TYPE_MEMORY_DEVICE will have them) should be common members, not variant
members.  Requires converting the simple union to the equivalent flat
union.

Do these members overlap by necessity?  Paolo, Igor?

[...]



  reply	other threads:[~2020-12-01 17:08 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-11  5:46 [RFC PATCH 00/25] Introduce CXL 2.0 Emulation Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 01/25] Temp: Add the PCI_EXT_ID_DVSEC definition to the qemu pci_regs.h copy Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 02/25] hw/pci/cxl: Add a CXL component type (interface) Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 03/25] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5) Ben Widawsky
2020-11-16 12:03   ` Jonathan Cameron
2020-11-16 19:19     ` Ben Widawsky
2020-11-17 12:29       ` Jonathan Cameron
2020-11-24 23:09         ` Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 04/25] hw/cxl/device: Introduce a CXL device (8.2.8) Ben Widawsky
2020-11-16 13:07   ` Jonathan Cameron
2020-11-16 21:11     ` Ben Widawsky
2020-11-17 14:21       ` Jonathan Cameron
2020-11-11  5:47 ` [RFC PATCH 05/25] hw/cxl/device: Implement the CAP array (8.2.8.1-2) Ben Widawsky
2020-11-16 13:11   ` Jonathan Cameron
2020-11-16 18:08     ` Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 06/25] hw/cxl/device: Add device status (8.2.8.3) Ben Widawsky
2020-11-16 13:16   ` Jonathan Cameron
2020-11-16 21:18     ` Ben Widawsky
2020-11-17 14:24       ` Jonathan Cameron
2020-11-11  5:47 ` [RFC PATCH 07/25] hw/cxl/device: Implement basic mailbox (8.2.8.4) Ben Widawsky
2020-11-16 13:46   ` Jonathan Cameron
2020-11-16 21:42     ` Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 08/25] hw/cxl/device: Add memory devices (8.2.8.5) Ben Widawsky
2020-11-16 16:37   ` Jonathan Cameron
2020-11-16 21:45     ` Ben Widawsky
2020-11-17 14:31       ` Jonathan Cameron
2020-11-11  5:47 ` [RFC PATCH 09/25] hw/pxb: Use a type for realizing expanders Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 10/25] hw/pci/cxl: Create a CXL bus type Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 11/25] hw/pxb: Allow creation of a CXL PXB (host bridge) Ben Widawsky
2020-11-16 16:44   ` Jonathan Cameron
2020-11-16 22:01     ` Ben Widawsky
2020-11-17 14:33       ` Jonathan Cameron
2020-11-11  5:47 ` [RFC PATCH 12/25] acpi/pci: Consolidate host bridge setup Ben Widawsky
2020-11-12 17:46   ` Ben Widawsky
2020-11-16 16:45   ` Jonathan Cameron
2020-11-11  5:47 ` [RFC PATCH 13/25] hw/pci: Plumb _UID through host bridges Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 14/25] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142) Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 15/25] acpi/pxb/cxl: Reserve host bridge MMIO Ben Widawsky
2020-11-16 16:54   ` Jonathan Cameron
2020-11-11  5:47 ` [RFC PATCH 16/25] hw/pxb/cxl: Add "windows" for host bridges Ben Widawsky
2020-11-13  0:49   ` Ben Widawsky
2020-11-23 19:12     ` Philippe Mathieu-Daudé
2020-11-11  5:47 ` [RFC PATCH 17/25] hw/cxl/rp: Add a root port Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 18/25] hw/cxl/device: Add a memory device (8.2.8.5) Ben Widawsky
2020-11-12 18:37   ` Eric Blake
2020-11-13  7:47     ` Markus Armbruster
2020-11-25 16:53       ` Ben Widawsky
2020-11-26  6:36         ` Markus Armbruster
2020-11-30 17:07           ` Ben Widawsky
2020-12-01 17:06             ` Markus Armbruster [this message]
2020-11-11  5:47 ` [RFC PATCH 19/25] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12) Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 20/25] acpi/cxl: Add _OSC implementation (9.14.2) Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 21/25] acpi/cxl: Introduce a compat-driver UUID for CXL _OSC Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 22/25] acpi/cxl: Create the CEDT (9.14.1) Ben Widawsky
2020-11-16 17:15   ` Jonathan Cameron
2020-11-16 22:05     ` Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 23/25] Temp: acpi/cxl: Add ACPI0017 (CEDT awareness) Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 24/25] WIP: i386/cxl: Initialize a host bridge Ben Widawsky
2020-11-11  5:47 ` [RFC PATCH 25/25] qtest/cxl: Add very basic sanity tests Ben Widawsky
2020-11-16 17:21 ` [RFC PATCH 00/25] Introduce CXL 2.0 Emulation Jonathan Cameron
2020-11-16 18:06   ` Ben Widawsky
2020-11-17 14:09     ` Jonathan Cameron
2020-11-25 18:29       ` Ben Widawsky
2020-12-04 14:27 ` Daniel P. Berrangé

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=878saha21q.fsf@dusky.pond.sub.org \
    --to=armbru@redhat.com \
    --cc=ben@bwidawsk.net \
    --cc=dan.j.williams@intel.com \
    --cc=dgilbert@redhat.com \
    --cc=ehabkost@redhat.com \
    --cc=imammedo@redhat.com \
    --cc=mst@redhat.com \
    --cc=pbonzini@redhat.com \
    --cc=qemu-devel@nongnu.org \
    --cc=rth@twiddle.net \
    --cc=vishal.l.verma@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.