* [PATCH 01/11] pinctrl: renesas: r8a779a0: Add EtherAVB pins, groups and functions
2020-11-26 17:21 [PATCH 00/11] pinctrl: renesas: R8A779A0 (V3U) device support Ulrich Hecht
@ 2020-11-26 17:21 ` Ulrich Hecht
2020-11-27 14:44 ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 02/11] pinctrl: renesas: r8a779a0: Add CANFD " Ulrich Hecht
` (10 subsequent siblings)
11 siblings, 1 reply; 26+ messages in thread
From: Ulrich Hecht @ 2020-11-26 17:21 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: wsa, geert, hoai.luu.ub, Ulrich Hecht
This patch adds groups and function for AVB PHY, LINK, MAGIC, MII and
PTP pins for the R8A779A0 (V3U) SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
---
drivers/pinctrl/renesas/pfc-r8a779a0.c | 595 +++++++++++++++++++++++++
1 file changed, 595 insertions(+)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c
index d0d0a682b13b..5fcc8e60167e 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
@@ -1199,6 +1199,462 @@ static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
};
+/* - AVB0 ------------------------------------------------ */
+static const unsigned int avb0_link_pins[] = {
+ /* AVB0_LINK */
+ RCAR_GP_PIN(4, 17),
+};
+static const unsigned int avb0_link_mux[] = {
+ AVB0_LINK_MARK,
+};
+static const unsigned int avb0_magic_pins[] = {
+ /* AVB0_MAGIC */
+ RCAR_GP_PIN(4, 15),
+};
+static const unsigned int avb0_magic_mux[] = {
+ AVB0_MAGIC_MARK,
+};
+static const unsigned int avb0_phy_int_pins[] = {
+ /* AVB0_PHY_INT */
+ RCAR_GP_PIN(4, 16),
+};
+static const unsigned int avb0_phy_int_mux[] = {
+ AVB0_PHY_INT_MARK,
+};
+static const unsigned int avb0_mdio_pins[] = {
+ /* AVB0_MDC, AVB0_MDIO */
+ RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
+};
+static const unsigned int avb0_mdio_mux[] = {
+ AVB0_MDC_MARK, AVB0_MDIO_MARK,
+};
+static const unsigned int avb0_rgmii_pins[] = {
+ /*
+ * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
+ * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3,
+ */
+ RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
+ RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
+ RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
+ RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
+ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
+ RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
+};
+static const unsigned int avb0_rgmii_mux[] = {
+ AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
+ AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
+ AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
+ AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
+};
+static const unsigned int avb0_txcrefclk_pins[] = {
+ /* AVB0_TXCREFCLK */
+ RCAR_GP_PIN(4, 12),
+};
+static const unsigned int avb0_txcrefclk_mux[] = {
+ AVB0_TXCREFCLK_MARK,
+};
+static const unsigned int avb0_avtp_pps_pins[] = {
+ /* AVB0_AVTP_PPS */
+ RCAR_GP_PIN(4, 20),
+};
+static const unsigned int avb0_avtp_pps_mux[] = {
+ AVB0_AVTP_PPS_MARK,
+};
+static const unsigned int avb0_avtp_capture_pins[] = {
+ /* AVB0_AVTP_CAPTURE */
+ RCAR_GP_PIN(4, 19),
+};
+static const unsigned int avb0_avtp_capture_mux[] = {
+ AVB0_AVTP_CAPTURE_MARK,
+};
+static const unsigned int avb0_avtp_match_pins[] = {
+ /* AVB0_AVTP_MATCH */
+ RCAR_GP_PIN(4, 18),
+};
+static const unsigned int avb0_avtp_match_mux[] = {
+ AVB0_AVTP_MATCH_MARK,
+};
+
+/* - AVB1 ------------------------------------------------ */
+static const unsigned int avb1_link_pins[] = {
+ /* AVB1_LINK */
+ RCAR_GP_PIN(5, 17),
+};
+static const unsigned int avb1_link_mux[] = {
+ AVB1_LINK_MARK,
+};
+static const unsigned int avb1_magic_pins[] = {
+ /* AVB1_MAGIC */
+ RCAR_GP_PIN(5, 15),
+};
+static const unsigned int avb1_magic_mux[] = {
+ AVB1_MAGIC_MARK,
+};
+static const unsigned int avb1_phy_int_pins[] = {
+ /* AVB1_PHY_INT */
+ RCAR_GP_PIN(5, 16),
+};
+static const unsigned int avb1_phy_int_mux[] = {
+ AVB1_PHY_INT_MARK,
+};
+static const unsigned int avb1_mdio_pins[] = {
+ /* AVB1_MDC, AVB1_MDIO */
+ RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 13),
+};
+static const unsigned int avb1_mdio_mux[] = {
+ AVB1_MDC_MARK, AVB1_MDIO_MARK,
+};
+static const unsigned int avb1_rgmii_pins[] = {
+ /*
+ * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3,
+ * AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3,
+ */
+ RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
+ RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
+ RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
+ RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
+ RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3),
+ RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
+};
+static const unsigned int avb1_rgmii_mux[] = {
+ AVB1_TX_CTL_MARK, AVB1_TXC_MARK,
+ AVB1_TD0_MARK, AVB1_TD1_MARK, AVB1_TD2_MARK, AVB1_TD3_MARK,
+ AVB1_RX_CTL_MARK, AVB1_RXC_MARK,
+ AVB1_RD0_MARK, AVB1_RD1_MARK, AVB1_RD2_MARK, AVB1_RD3_MARK,
+};
+static const unsigned int avb1_txcrefclk_pins[] = {
+ /* AVB1_TXCREFCLK */
+ RCAR_GP_PIN(5, 12),
+};
+static const unsigned int avb1_txcrefclk_mux[] = {
+ AVB1_TXCREFCLK_MARK,
+};
+static const unsigned int avb1_avtp_pps_pins[] = {
+ /* AVB1_AVTP_PPS */
+ RCAR_GP_PIN(5, 20),
+};
+static const unsigned int avb1_avtp_pps_mux[] = {
+ AVB1_AVTP_PPS_MARK,
+};
+static const unsigned int avb1_avtp_capture_pins[] = {
+ /* AVB1_AVTP_CAPTURE */
+ RCAR_GP_PIN(5, 19),
+};
+static const unsigned int avb1_avtp_capture_mux[] = {
+ AVB1_AVTP_CAPTURE_MARK,
+};
+static const unsigned int avb1_avtp_match_pins[] = {
+ /* AVB1_AVTP_MATCH */
+ RCAR_GP_PIN(5, 18),
+};
+static const unsigned int avb1_avtp_match_mux[] = {
+ AVB1_AVTP_MATCH_MARK,
+};
+
+/* - AVB2 ------------------------------------------------ */
+static const unsigned int avb2_link_pins[] = {
+ /* AVB2_LINK */
+ RCAR_GP_PIN(6, 17),
+};
+static const unsigned int avb2_link_mux[] = {
+ AVB2_LINK_MARK,
+};
+static const unsigned int avb2_magic_pins[] = {
+ /* AVB2_MAGIC */
+ RCAR_GP_PIN(6, 15),
+};
+static const unsigned int avb2_magic_mux[] = {
+ AVB2_MAGIC_MARK,
+};
+static const unsigned int avb2_phy_int_pins[] = {
+ /* AVB2_PHY_INT */
+ RCAR_GP_PIN(6, 16),
+};
+static const unsigned int avb2_phy_int_mux[] = {
+ AVB2_PHY_INT_MARK,
+};
+static const unsigned int avb2_mdio_pins[] = {
+ /* AVB2_MDC, AVB2_MDIO */
+ RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 13),
+};
+static const unsigned int avb2_mdio_mux[] = {
+ AVB2_MDC_MARK, AVB2_MDIO_MARK,
+};
+static const unsigned int avb2_rgmii_pins[] = {
+ /*
+ * AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3,
+ * AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3,
+ */
+ RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
+ RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
+ RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
+ RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
+ RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
+ RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
+};
+static const unsigned int avb2_rgmii_mux[] = {
+ AVB2_TX_CTL_MARK, AVB2_TXC_MARK,
+ AVB2_TD0_MARK, AVB2_TD1_MARK, AVB2_TD2_MARK, AVB2_TD3_MARK,
+ AVB2_RX_CTL_MARK, AVB2_RXC_MARK,
+ AVB2_RD0_MARK, AVB2_RD1_MARK, AVB2_RD2_MARK, AVB2_RD3_MARK,
+};
+static const unsigned int avb2_txcrefclk_pins[] = {
+ /* AVB2_TXCREFCLK */
+ RCAR_GP_PIN(6, 12),
+};
+static const unsigned int avb2_txcrefclk_mux[] = {
+ AVB2_TXCREFCLK_MARK,
+};
+static const unsigned int avb2_avtp_pps_pins[] = {
+ /* AVB2_AVTP_PPS */
+ RCAR_GP_PIN(6, 20),
+};
+static const unsigned int avb2_avtp_pps_mux[] = {
+ AVB2_AVTP_PPS_MARK,
+};
+static const unsigned int avb2_avtp_capture_pins[] = {
+ /* AVB2_AVTP_CAPTURE */
+ RCAR_GP_PIN(6, 19),
+};
+static const unsigned int avb2_avtp_capture_mux[] = {
+ AVB2_AVTP_CAPTURE_MARK,
+};
+static const unsigned int avb2_avtp_match_pins[] = {
+ /* AVB2_AVTP_MATCH */
+ RCAR_GP_PIN(6, 18),
+};
+static const unsigned int avb2_avtp_match_mux[] = {
+ AVB2_AVTP_MATCH_MARK,
+};
+
+/* - AVB3 ------------------------------------------------ */
+static const unsigned int avb3_link_pins[] = {
+ /* AVB3_LINK */
+ RCAR_GP_PIN(7, 17),
+};
+static const unsigned int avb3_link_mux[] = {
+ AVB3_LINK_MARK,
+};
+static const unsigned int avb3_magic_pins[] = {
+ /* AVB3_MAGIC */
+ RCAR_GP_PIN(7, 15),
+};
+static const unsigned int avb3_magic_mux[] = {
+ AVB3_MAGIC_MARK,
+};
+static const unsigned int avb3_phy_int_pins[] = {
+ /* AVB3_PHY_INT */
+ RCAR_GP_PIN(7, 16),
+};
+static const unsigned int avb3_phy_int_mux[] = {
+ AVB3_PHY_INT_MARK,
+};
+static const unsigned int avb3_mdio_pins[] = {
+ /* AVB3_MDC, AVB3_MDIO */
+ RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 13),
+};
+static const unsigned int avb3_mdio_mux[] = {
+ AVB3_MDC_MARK, AVB3_MDIO_MARK,
+};
+static const unsigned int avb3_rgmii_pins[] = {
+ /*
+ * AVB3_TX_CTL, AVB3_TXC, AVB3_TD0, AVB3_TD1, AVB3_TD2, AVB3_TD3,
+ * AVB3_RX_CTL, AVB3_RXC, AVB3_RD0, AVB3_RD1, AVB3_RD2, AVB3_RD3,
+ */
+ RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
+ RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
+ RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
+ RCAR_GP_PIN(7, 0), RCAR_GP_PIN(7, 1),
+ RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3),
+ RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
+};
+static const unsigned int avb3_rgmii_mux[] = {
+ AVB3_TX_CTL_MARK, AVB3_TXC_MARK,
+ AVB3_TD0_MARK, AVB3_TD1_MARK, AVB3_TD2_MARK, AVB3_TD3_MARK,
+ AVB3_RX_CTL_MARK, AVB3_RXC_MARK,
+ AVB3_RD0_MARK, AVB3_RD1_MARK, AVB3_RD2_MARK, AVB3_RD3_MARK,
+};
+static const unsigned int avb3_txcrefclk_pins[] = {
+ /* AVB3_TXCREFCLK */
+ RCAR_GP_PIN(7, 12),
+};
+static const unsigned int avb3_txcrefclk_mux[] = {
+ AVB3_TXCREFCLK_MARK,
+};
+static const unsigned int avb3_avtp_pps_pins[] = {
+ /* AVB3_AVTP_PPS */
+ RCAR_GP_PIN(7, 20),
+};
+static const unsigned int avb3_avtp_pps_mux[] = {
+ AVB3_AVTP_PPS_MARK,
+};
+static const unsigned int avb3_avtp_capture_pins[] = {
+ /* AVB3_AVTP_CAPTURE */
+ RCAR_GP_PIN(7, 19),
+};
+static const unsigned int avb3_avtp_capture_mux[] = {
+ AVB3_AVTP_CAPTURE_MARK,
+};
+static const unsigned int avb3_avtp_match_pins[] = {
+ /* AVB3_AVTP_MATCH */
+ RCAR_GP_PIN(7, 18),
+};
+static const unsigned int avb3_avtp_match_mux[] = {
+ AVB3_AVTP_MATCH_MARK,
+};
+
+/* - AVB4 ------------------------------------------------ */
+static const unsigned int avb4_link_pins[] = {
+ /* AVB4_LINK */
+ RCAR_GP_PIN(8, 17),
+};
+static const unsigned int avb4_link_mux[] = {
+ AVB4_LINK_MARK,
+};
+static const unsigned int avb4_magic_pins[] = {
+ /* AVB4_MAGIC */
+ RCAR_GP_PIN(8, 15),
+};
+static const unsigned int avb4_magic_mux[] = {
+ AVB4_MAGIC_MARK,
+};
+static const unsigned int avb4_phy_int_pins[] = {
+ /* AVB4_PHY_INT */
+ RCAR_GP_PIN(8, 16),
+};
+static const unsigned int avb4_phy_int_mux[] = {
+ AVB4_PHY_INT_MARK,
+};
+static const unsigned int avb4_mdio_pins[] = {
+ /* AVB4_MDC, AVB4_MDIO */
+ RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 13),
+};
+static const unsigned int avb4_mdio_mux[] = {
+ AVB4_MDC_MARK, AVB4_MDIO_MARK,
+};
+static const unsigned int avb4_rgmii_pins[] = {
+ /*
+ * AVB4_TX_CTL, AVB4_TXC, AVB4_TD0, AVB4_TD1, AVB4_TD2, AVB4_TD3,
+ * AVB4_RX_CTL, AVB4_RXC, AVB4_RD0, AVB4_RD1, AVB4_RD2, AVB4_RD3,
+ */
+ RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
+ RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
+ RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
+ RCAR_GP_PIN(8, 0), RCAR_GP_PIN(8, 1),
+ RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3),
+ RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
+};
+static const unsigned int avb4_rgmii_mux[] = {
+ AVB4_TX_CTL_MARK, AVB4_TXC_MARK,
+ AVB4_TD0_MARK, AVB4_TD1_MARK, AVB4_TD2_MARK, AVB4_TD3_MARK,
+ AVB4_RX_CTL_MARK, AVB4_RXC_MARK,
+ AVB4_RD0_MARK, AVB4_RD1_MARK, AVB4_RD2_MARK, AVB4_RD3_MARK,
+};
+static const unsigned int avb4_txcrefclk_pins[] = {
+ /* AVB4_TXCREFCLK */
+ RCAR_GP_PIN(8, 12),
+};
+static const unsigned int avb4_txcrefclk_mux[] = {
+ AVB4_TXCREFCLK_MARK,
+};
+static const unsigned int avb4_avtp_pps_pins[] = {
+ /* AVB4_AVTP_PPS */
+ RCAR_GP_PIN(8, 20),
+};
+static const unsigned int avb4_avtp_pps_mux[] = {
+ AVB4_AVTP_PPS_MARK,
+};
+static const unsigned int avb4_avtp_capture_pins[] = {
+ /* AVB4_AVTP_CAPTURE */
+ RCAR_GP_PIN(8, 19),
+};
+static const unsigned int avb4_avtp_capture_mux[] = {
+ AVB4_AVTP_CAPTURE_MARK,
+};
+static const unsigned int avb4_avtp_match_pins[] = {
+ /* AVB4_AVTP_MATCH */
+ RCAR_GP_PIN(8, 18),
+};
+static const unsigned int avb4_avtp_match_mux[] = {
+ AVB4_AVTP_MATCH_MARK,
+};
+
+/* - AVB5 ------------------------------------------------ */
+static const unsigned int avb5_link_pins[] = {
+ /* AVB5_LINK */
+ RCAR_GP_PIN(9, 17),
+};
+static const unsigned int avb5_link_mux[] = {
+ AVB5_LINK_MARK,
+};
+static const unsigned int avb5_magic_pins[] = {
+ /* AVB5_MAGIC */
+ RCAR_GP_PIN(9, 15),
+};
+static const unsigned int avb5_magic_mux[] = {
+ AVB5_MAGIC_MARK,
+};
+static const unsigned int avb5_phy_int_pins[] = {
+ /* AVB5_PHY_INT */
+ RCAR_GP_PIN(9, 16),
+};
+static const unsigned int avb5_phy_int_mux[] = {
+ AVB5_PHY_INT_MARK,
+};
+static const unsigned int avb5_mdio_pins[] = {
+ /* AVB5_MDC, AVB5_MDIO */
+ RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 13),
+};
+static const unsigned int avb5_mdio_mux[] = {
+ AVB5_MDC_MARK, AVB5_MDIO_MARK,
+};
+static const unsigned int avb5_rgmii_pins[] = {
+ /*
+ * AVB5_TX_CTL, AVB5_TXC, AVB5_TD0, AVB5_TD1, AVB5_TD2, AVB5_TD3,
+ * AVB5_RX_CTL, AVB5_RXC, AVB5_RD0, AVB5_RD1, AVB5_RD2, AVB5_RD3,
+ */
+ RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
+ RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
+ RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
+ RCAR_GP_PIN(9, 0), RCAR_GP_PIN(9, 1),
+ RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3),
+ RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
+};
+static const unsigned int avb5_rgmii_mux[] = {
+ AVB5_TX_CTL_MARK, AVB5_TXC_MARK,
+ AVB5_TD0_MARK, AVB5_TD1_MARK, AVB5_TD2_MARK, AVB5_TD3_MARK,
+ AVB5_RX_CTL_MARK, AVB5_RXC_MARK,
+ AVB5_RD0_MARK, AVB5_RD1_MARK, AVB5_RD2_MARK, AVB5_RD3_MARK,
+};
+static const unsigned int avb5_txcrefclk_pins[] = {
+ /* AVB5_TXCREFCLK */
+ RCAR_GP_PIN(9, 12),
+};
+static const unsigned int avb5_txcrefclk_mux[] = {
+ AVB5_TXCREFCLK_MARK,
+};
+static const unsigned int avb5_avtp_pps_pins[] = {
+ /* AVB5_AVTP_PPS */
+ RCAR_GP_PIN(9, 20),
+};
+static const unsigned int avb5_avtp_pps_mux[] = {
+ AVB5_AVTP_PPS_MARK,
+};
+static const unsigned int avb5_avtp_capture_pins[] = {
+ /* AVB5_AVTP_CAPTURE */
+ RCAR_GP_PIN(9, 19),
+};
+static const unsigned int avb5_avtp_capture_mux[] = {
+ AVB5_AVTP_CAPTURE_MARK,
+};
+static const unsigned int avb5_avtp_match_pins[] = {
+ /* AVB5_AVTP_MATCH */
+ RCAR_GP_PIN(9, 18),
+};
+static const unsigned int avb5_avtp_match_mux[] = {
+ AVB5_AVTP_MATCH_MARK,
+};
+
/* - I2C0 ------------------------------------------------------------------- */
static const unsigned int i2c0_pins[] = {
@@ -1365,6 +1821,66 @@ static const unsigned int scif_clk_mux[] = {
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(avb0_link),
+ SH_PFC_PIN_GROUP(avb0_magic),
+ SH_PFC_PIN_GROUP(avb0_phy_int),
+ SH_PFC_PIN_GROUP(avb0_mdio),
+ SH_PFC_PIN_GROUP(avb0_rgmii),
+ SH_PFC_PIN_GROUP(avb0_txcrefclk),
+ SH_PFC_PIN_GROUP(avb0_avtp_pps),
+ SH_PFC_PIN_GROUP(avb0_avtp_capture),
+ SH_PFC_PIN_GROUP(avb0_avtp_match),
+
+ SH_PFC_PIN_GROUP(avb1_link),
+ SH_PFC_PIN_GROUP(avb1_magic),
+ SH_PFC_PIN_GROUP(avb1_phy_int),
+ SH_PFC_PIN_GROUP(avb1_mdio),
+ SH_PFC_PIN_GROUP(avb1_rgmii),
+ SH_PFC_PIN_GROUP(avb1_txcrefclk),
+ SH_PFC_PIN_GROUP(avb1_avtp_pps),
+ SH_PFC_PIN_GROUP(avb1_avtp_capture),
+ SH_PFC_PIN_GROUP(avb1_avtp_match),
+
+ SH_PFC_PIN_GROUP(avb2_link),
+ SH_PFC_PIN_GROUP(avb2_magic),
+ SH_PFC_PIN_GROUP(avb2_phy_int),
+ SH_PFC_PIN_GROUP(avb2_mdio),
+ SH_PFC_PIN_GROUP(avb2_rgmii),
+ SH_PFC_PIN_GROUP(avb2_txcrefclk),
+ SH_PFC_PIN_GROUP(avb2_avtp_pps),
+ SH_PFC_PIN_GROUP(avb2_avtp_capture),
+ SH_PFC_PIN_GROUP(avb2_avtp_match),
+
+ SH_PFC_PIN_GROUP(avb3_link),
+ SH_PFC_PIN_GROUP(avb3_magic),
+ SH_PFC_PIN_GROUP(avb3_phy_int),
+ SH_PFC_PIN_GROUP(avb3_mdio),
+ SH_PFC_PIN_GROUP(avb3_rgmii),
+ SH_PFC_PIN_GROUP(avb3_txcrefclk),
+ SH_PFC_PIN_GROUP(avb3_avtp_pps),
+ SH_PFC_PIN_GROUP(avb3_avtp_capture),
+ SH_PFC_PIN_GROUP(avb3_avtp_match),
+
+ SH_PFC_PIN_GROUP(avb4_link),
+ SH_PFC_PIN_GROUP(avb4_magic),
+ SH_PFC_PIN_GROUP(avb4_phy_int),
+ SH_PFC_PIN_GROUP(avb4_mdio),
+ SH_PFC_PIN_GROUP(avb4_rgmii),
+ SH_PFC_PIN_GROUP(avb4_txcrefclk),
+ SH_PFC_PIN_GROUP(avb4_avtp_pps),
+ SH_PFC_PIN_GROUP(avb4_avtp_capture),
+ SH_PFC_PIN_GROUP(avb4_avtp_match),
+
+ SH_PFC_PIN_GROUP(avb5_link),
+ SH_PFC_PIN_GROUP(avb5_magic),
+ SH_PFC_PIN_GROUP(avb5_phy_int),
+ SH_PFC_PIN_GROUP(avb5_mdio),
+ SH_PFC_PIN_GROUP(avb5_rgmii),
+ SH_PFC_PIN_GROUP(avb5_txcrefclk),
+ SH_PFC_PIN_GROUP(avb5_avtp_pps),
+ SH_PFC_PIN_GROUP(avb5_avtp_capture),
+ SH_PFC_PIN_GROUP(avb5_avtp_match),
+
SH_PFC_PIN_GROUP(i2c0),
SH_PFC_PIN_GROUP(i2c1),
SH_PFC_PIN_GROUP(i2c2),
@@ -1388,6 +1904,78 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scif_clk),
};
+static const char * const avb0_groups[] = {
+ "avb0_link",
+ "avb0_magic",
+ "avb0_phy_int",
+ "avb0_mdio",
+ "avb0_rgmii",
+ "avb0_txcrefclk",
+ "avb0_avtp_pps",
+ "avb0_avtp_capture",
+ "avb0_avtp_match",
+};
+
+static const char * const avb1_groups[] = {
+ "avb1_link",
+ "avb1_magic",
+ "avb1_phy_int",
+ "avb1_mdio",
+ "avb1_rgmii",
+ "avb1_txcrefclk",
+ "avb1_avtp_pps",
+ "avb1_avtp_capture",
+ "avb1_avtp_match",
+};
+
+static const char * const avb2_groups[] = {
+ "avb2_link",
+ "avb2_magic",
+ "avb2_phy_int",
+ "avb2_mdio",
+ "avb2_rgmii",
+ "avb2_txcrefclk",
+ "avb2_avtp_pps",
+ "avb2_avtp_capture",
+ "avb2_avtp_match",
+};
+
+static const char * const avb3_groups[] = {
+ "avb3_link",
+ "avb3_magic",
+ "avb3_phy_int",
+ "avb3_mdio",
+ "avb3_rgmii",
+ "avb3_txcrefclk",
+ "avb3_avtp_pps",
+ "avb3_avtp_capture",
+ "avb3_avtp_match",
+};
+
+static const char * const avb4_groups[] = {
+ "avb4_link",
+ "avb4_magic",
+ "avb4_phy_int",
+ "avb4_mdio",
+ "avb4_rgmii",
+ "avb4_txcrefclk",
+ "avb4_avtp_pps",
+ "avb4_avtp_capture",
+ "avb4_avtp_match",
+};
+
+static const char * const avb5_groups[] = {
+ "avb5_link",
+ "avb5_magic",
+ "avb5_phy_int",
+ "avb5_mdio",
+ "avb5_rgmii",
+ "avb5_txcrefclk",
+ "avb5_avtp_pps",
+ "avb5_avtp_capture",
+ "avb5_avtp_match",
+};
+
static const char * const i2c0_groups[] = {
"i2c0",
};
@@ -1445,6 +2033,13 @@ static const char * const scif_clk_groups[] = {
};
static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(avb0),
+ SH_PFC_FUNCTION(avb1),
+ SH_PFC_FUNCTION(avb2),
+ SH_PFC_FUNCTION(avb3),
+ SH_PFC_FUNCTION(avb4),
+ SH_PFC_FUNCTION(avb5),
+
SH_PFC_FUNCTION(i2c0),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
--
2.20.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 01/11] pinctrl: renesas: r8a779a0: Add EtherAVB pins, groups and functions
2020-11-26 17:21 ` [PATCH 01/11] pinctrl: renesas: r8a779a0: Add EtherAVB pins, groups and functions Ulrich Hecht
@ 2020-11-27 14:44 ` Geert Uytterhoeven
0 siblings, 0 replies; 26+ messages in thread
From: Geert Uytterhoeven @ 2020-11-27 14:44 UTC (permalink / raw)
To: Ulrich Hecht; +Cc: Linux-Renesas, Wolfram Sang, hoai.luu.ub
Hi Uli,
On Thu, Nov 26, 2020 at 6:22 PM Ulrich Hecht <uli+renesas@fpond.eu> wrote:
> This patch adds groups and function for AVB PHY, LINK, MAGIC, MII and
> PTP pins for the R8A779A0 (V3U) SoC.
>
> Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Thanks for your patch!
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
However, AVB0 and AVB1 also support MII, so I think you should add
separate pin groups to support that.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 02/11] pinctrl: renesas: r8a779a0: Add CANFD pins, groups and functions
2020-11-26 17:21 [PATCH 00/11] pinctrl: renesas: R8A779A0 (V3U) device support Ulrich Hecht
2020-11-26 17:21 ` [PATCH 01/11] pinctrl: renesas: r8a779a0: Add EtherAVB pins, groups and functions Ulrich Hecht
@ 2020-11-26 17:21 ` Ulrich Hecht
2020-11-27 15:35 ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 03/11] pinctrl: renesas: r8a779a0: Add DU pins, groups and function Ulrich Hecht
` (9 subsequent siblings)
11 siblings, 1 reply; 26+ messages in thread
From: Ulrich Hecht @ 2020-11-26 17:21 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: wsa, geert, hoai.luu.ub, Ulrich Hecht
This patch adds CANFD 0-7 and CANFD clock pinmux support for the
R8A779A0 (V3U) SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
---
drivers/pinctrl/renesas/pfc-r8a779a0.c | 137 +++++++++++++++++++++++++
1 file changed, 137 insertions(+)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c
index 5fcc8e60167e..725d6b58bb4d 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
@@ -1655,6 +1655,87 @@ static const unsigned int avb5_avtp_match_mux[] = {
AVB5_AVTP_MATCH_MARK,
};
+/* - CANFD0 ----------------------------------------------------------------- */
+static const unsigned int canfd0_data_pins[] = {
+ /* CANFD0_TX, CANFD0_RX */
+ RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
+};
+static const unsigned int canfd0_data_mux[] = {
+ CANFD0_TX_MARK, CANFD0_RX_MARK,
+};
+
+/* - CANFD1 ----------------------------------------------------------------- */
+static const unsigned int canfd1_data_pins[] = {
+ /* CANFD1_TX, CANFD1_RX */
+ RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
+};
+static const unsigned int canfd1_data_mux[] = {
+ CANFD1_TX_MARK, CANFD1_RX_MARK,
+};
+
+/* - CANFD2 ----------------------------------------------------------------- */
+static const unsigned int canfd2_data_pins[] = {
+ /* CANFD2_TX, CANFD2_RX */
+ RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
+};
+static const unsigned int canfd2_data_mux[] = {
+ CANFD2_TX_MARK, CANFD2_RX_MARK,
+};
+
+/* - CANFD3 ----------------------------------------------------------------- */
+static const unsigned int canfd3_data_pins[] = {
+ /* CANFD3_TX, CANFD3_RX */
+ RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
+};
+static const unsigned int canfd3_data_mux[] = {
+ CANFD3_TX_MARK, CANFD3_RX_MARK,
+};
+
+/* - CANFD4 ----------------------------------------------------------------- */
+static const unsigned int canfd4_data_pins[] = {
+ /* CANFD4_TX, CANFD4_RX */
+ RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
+};
+static const unsigned int canfd4_data_mux[] = {
+ CANFD4_TX_MARK, CANFD4_RX_MARK,
+};
+
+/* - CANFD5 ----------------------------------------------------------------- */
+static const unsigned int canfd5_data_pins[] = {
+ /* CANFD5_TX, CANFD5_RX */
+ RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
+};
+static const unsigned int canfd5_data_mux[] = {
+ CANFD5_TX_MARK, CANFD5_RX_MARK,
+};
+
+/* - CANFD6 ----------------------------------------------------------------- */
+static const unsigned int canfd6_data_pins[] = {
+ /* CANFD6_TX, CANFD6_RX */
+ RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
+};
+static const unsigned int canfd6_data_mux[] = {
+ CANFD6_TX_MARK, CANFD6_RX_MARK,
+};
+
+/* - CANFD7 ----------------------------------------------------------------- */
+static const unsigned int canfd7_data_pins[] = {
+ /* CANFD7_TX, CANFD7_RX */
+ RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
+};
+static const unsigned int canfd7_data_mux[] = {
+ CANFD7_TX_MARK, CANFD7_RX_MARK,
+};
+
+/* - CANFD Clock ------------------------------------------------------------ */
+static const unsigned int canfd_clk_pins[] = {
+ /* CAN_CLK */
+ RCAR_GP_PIN(3, 0),
+};
+static const unsigned int canfd_clk_mux[] = {
+ CAN_CLK_MARK,
+};
+
/* - I2C0 ------------------------------------------------------------------- */
static const unsigned int i2c0_pins[] = {
@@ -1881,6 +1962,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(avb5_avtp_capture),
SH_PFC_PIN_GROUP(avb5_avtp_match),
+ SH_PFC_PIN_GROUP(canfd0_data),
+ SH_PFC_PIN_GROUP(canfd1_data),
+ SH_PFC_PIN_GROUP(canfd2_data),
+ SH_PFC_PIN_GROUP(canfd3_data),
+ SH_PFC_PIN_GROUP(canfd4_data),
+ SH_PFC_PIN_GROUP(canfd5_data),
+ SH_PFC_PIN_GROUP(canfd6_data),
+ SH_PFC_PIN_GROUP(canfd7_data),
+ SH_PFC_PIN_GROUP(canfd_clk),
+
SH_PFC_PIN_GROUP(i2c0),
SH_PFC_PIN_GROUP(i2c1),
SH_PFC_PIN_GROUP(i2c2),
@@ -1976,6 +2067,42 @@ static const char * const avb5_groups[] = {
"avb5_avtp_match",
};
+static const char * const canfd0_groups[] = {
+ "canfd0_data",
+};
+
+static const char * const canfd1_groups[] = {
+ "canfd1_data",
+};
+
+static const char * const canfd2_groups[] = {
+ "canfd2_data",
+};
+
+static const char * const canfd3_groups[] = {
+ "canfd3_data",
+};
+
+static const char * const canfd4_groups[] = {
+ "canfd4_data",
+};
+
+static const char * const canfd5_groups[] = {
+ "canfd5_data",
+};
+
+static const char * const canfd6_groups[] = {
+ "canfd6_data",
+};
+
+static const char * const canfd7_groups[] = {
+ "canfd7_data",
+};
+
+static const char * const canfd_clk_groups[] = {
+ "canfd_clk",
+};
+
static const char * const i2c0_groups[] = {
"i2c0",
};
@@ -2040,6 +2167,16 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(avb4),
SH_PFC_FUNCTION(avb5),
+ SH_PFC_FUNCTION(canfd0),
+ SH_PFC_FUNCTION(canfd1),
+ SH_PFC_FUNCTION(canfd2),
+ SH_PFC_FUNCTION(canfd3),
+ SH_PFC_FUNCTION(canfd4),
+ SH_PFC_FUNCTION(canfd5),
+ SH_PFC_FUNCTION(canfd6),
+ SH_PFC_FUNCTION(canfd7),
+ SH_PFC_FUNCTION(canfd_clk),
+
SH_PFC_FUNCTION(i2c0),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
--
2.20.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 02/11] pinctrl: renesas: r8a779a0: Add CANFD pins, groups and functions
2020-11-26 17:21 ` [PATCH 02/11] pinctrl: renesas: r8a779a0: Add CANFD " Ulrich Hecht
@ 2020-11-27 15:35 ` Geert Uytterhoeven
0 siblings, 0 replies; 26+ messages in thread
From: Geert Uytterhoeven @ 2020-11-27 15:35 UTC (permalink / raw)
To: Ulrich Hecht; +Cc: Linux-Renesas, Wolfram Sang, hoai.luu.ub
Hi Uli,
On Thu, Nov 26, 2020 at 6:22 PM Ulrich Hecht <uli+renesas@fpond.eu> wrote:
> This patch adds CANFD 0-7 and CANFD clock pinmux support for the
> R8A779A0 (V3U) SoC.
>
> Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Thanks for your patch!
> --- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
> +/* - CANFD Clock ------------------------------------------------------------ */
> +static const unsigned int canfd_clk_pins[] = {
> + /* CAN_CLK */
> + RCAR_GP_PIN(3, 0),
> +};
> +static const unsigned int canfd_clk_mux[] = {
> + CAN_CLK_MARK,
> +};
The User's Manual calls this "can_clk", so I'm wondering if we should do the
same, like on most R-Car SoCs,to avoid confusing with the internal CANFD
clock.
I know we call it "canfd_clk" on R-Car V3M (it is called that way in the manual)
and on R-Car V3H (either copied from V3M, or changed later in the manual),
the two other SoCs that don't have separate (non-FD) CAN controllers.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 03/11] pinctrl: renesas: r8a779a0: Add DU pins, groups and function
2020-11-26 17:21 [PATCH 00/11] pinctrl: renesas: R8A779A0 (V3U) device support Ulrich Hecht
2020-11-26 17:21 ` [PATCH 01/11] pinctrl: renesas: r8a779a0: Add EtherAVB pins, groups and functions Ulrich Hecht
2020-11-26 17:21 ` [PATCH 02/11] pinctrl: renesas: r8a779a0: Add CANFD " Ulrich Hecht
@ 2020-11-26 17:21 ` Ulrich Hecht
2020-11-27 15:50 ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 04/11] pinctrl: renesas: r8a779a0: Add HSCIF pins, groups and functions Ulrich Hecht
` (8 subsequent siblings)
11 siblings, 1 reply; 26+ messages in thread
From: Ulrich Hecht @ 2020-11-26 17:21 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: wsa, geert, hoai.luu.ub, Ulrich Hecht
This patch adds DU pins, groups and function for the R8A779A0 (V3U) SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
---
drivers/pinctrl/renesas/pfc-r8a779a0.c | 64 ++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c
index 725d6b58bb4d..9b1f140372fd 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
@@ -1736,6 +1736,53 @@ static const unsigned int canfd_clk_mux[] = {
CAN_CLK_MARK,
};
+/* - DU --------------------------------------------------------------------- */
+static const unsigned int du_rgb888_pins[] = {
+ /* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */
+ RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
+ RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
+ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
+ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
+ RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
+ RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
+};
+static const unsigned int du_rgb888_mux[] = {
+ DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
+ DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
+ DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
+ DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
+ DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
+ DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
+};
+static const unsigned int du_clk_out_pins[] = {
+ /* DU_DOTCLKOUT */
+ RCAR_GP_PIN(1, 24),
+};
+static const unsigned int du_clk_out_mux[] = {
+ DU_DOTCLKOUT_MARK,
+};
+static const unsigned int du_oddf_pins[] = {
+ /* DU_EXODDF/DU_ODDF/DISP/CDE */
+ RCAR_GP_PIN(1, 27),
+};
+static const unsigned int du_oddf_mux[] = {
+ DU_ODDF_DISP_CDE_MARK,
+};
+static const unsigned int du_cde_pins[] = {
+ /* DU_CDE */
+ RCAR_GP_PIN(1, 27),
+};
+static const unsigned int du_cde_mux[] = {
+ DU_ODDF_DISP_CDE_MARK,
+};
+static const unsigned int du_disp_pins[] = {
+ /* DU_DISP */
+ RCAR_GP_PIN(1, 27),
+};
+static const unsigned int du_disp_mux[] = {
+ DU_ODDF_DISP_CDE_MARK,
+};
+
/* - I2C0 ------------------------------------------------------------------- */
static const unsigned int i2c0_pins[] = {
@@ -1972,6 +2019,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(canfd7_data),
SH_PFC_PIN_GROUP(canfd_clk),
+ SH_PFC_PIN_GROUP(du_rgb888),
+ SH_PFC_PIN_GROUP(du_clk_out),
+ SH_PFC_PIN_GROUP(du_oddf),
+ SH_PFC_PIN_GROUP(du_cde),
+ SH_PFC_PIN_GROUP(du_disp),
+
SH_PFC_PIN_GROUP(i2c0),
SH_PFC_PIN_GROUP(i2c1),
SH_PFC_PIN_GROUP(i2c2),
@@ -2103,6 +2156,15 @@ static const char * const canfd_clk_groups[] = {
"canfd_clk",
};
+static const char * const du_groups[] = {
+ "du_rgb888",
+ "du_clk_out",
+ "du_sync",
+ "du_oddf",
+ "du_cde",
+ "du_disp",
+};
+
static const char * const i2c0_groups[] = {
"i2c0",
};
@@ -2177,6 +2239,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(canfd7),
SH_PFC_FUNCTION(canfd_clk),
+ SH_PFC_FUNCTION(du),
+
SH_PFC_FUNCTION(i2c0),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
--
2.20.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 03/11] pinctrl: renesas: r8a779a0: Add DU pins, groups and function
2020-11-26 17:21 ` [PATCH 03/11] pinctrl: renesas: r8a779a0: Add DU pins, groups and function Ulrich Hecht
@ 2020-11-27 15:50 ` Geert Uytterhoeven
0 siblings, 0 replies; 26+ messages in thread
From: Geert Uytterhoeven @ 2020-11-27 15:50 UTC (permalink / raw)
To: Ulrich Hecht; +Cc: Linux-Renesas, Wolfram Sang, hoai.luu.ub
Hi Uli,
On Thu, Nov 26, 2020 at 6:22 PM Ulrich Hecht <uli+renesas@fpond.eu> wrote:
> This patch adds DU pins, groups and function for the R8A779A0 (V3U) SoC.
> Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Thanks for your patch!
> --- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
> @@ -1736,6 +1736,53 @@ static const unsigned int canfd_clk_mux[] = {
> CAN_CLK_MARK,
> };
>
> +/* - DU --------------------------------------------------------------------- */
> +static const unsigned int du_rgb888_pins[] = {
> + /* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */
> + RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
> + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
> + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
> + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
> + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
> + RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
> +};
> +static const unsigned int du_rgb888_mux[] = {
> + DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
> + DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
> + DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
> + DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
> + DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
> + DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
> +};
> +static const unsigned int du_clk_out_pins[] = {
> + /* DU_DOTCLKOUT */
> + RCAR_GP_PIN(1, 24),
> +};
> +static const unsigned int du_clk_out_mux[] = {
> + DU_DOTCLKOUT_MARK,
> +};
> +static const unsigned int du_oddf_pins[] = {
> + /* DU_EXODDF/DU_ODDF/DISP/CDE */
> + RCAR_GP_PIN(1, 27),
> +};
> +static const unsigned int du_oddf_mux[] = {
> + DU_ODDF_DISP_CDE_MARK,
> +};
> +static const unsigned int du_cde_pins[] = {
> + /* DU_CDE */
> + RCAR_GP_PIN(1, 27),
> +};
> +static const unsigned int du_cde_mux[] = {
> + DU_ODDF_DISP_CDE_MARK,
> +};
> +static const unsigned int du_disp_pins[] = {
> + /* DU_DISP */
> + RCAR_GP_PIN(1, 27),
> +};
> +static const unsigned int du_disp_mux[] = {
> + DU_ODDF_DISP_CDE_MARK,
> +};
With not-yet-submitted debug checks:
r8a779a0_pfc: groups du_cde can be an alias for du_oddf
r8a779a0_pfc: groups du_disp can be an alias for du_oddf
r8a779a0_pfc: groups du_disp can be an alias for du_cde
Do we need all three?
> @@ -2103,6 +2156,15 @@ static const char * const canfd_clk_groups[] = {
> "canfd_clk",
> };
>
> +static const char * const du_groups[] = {
> + "du_rgb888",
> + "du_clk_out",
> + "du_sync",
With CONFIG_DEBUG_PINCTRL=y:
r8a779a0_pfc: function du: group du_sync not found
And indeed, the sync group with the HSYNC (GP1_25) and VSYNC (GP1_26)
pins is missing.
With the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 04/11] pinctrl: renesas: r8a779a0: Add HSCIF pins, groups and functions
2020-11-26 17:21 [PATCH 00/11] pinctrl: renesas: R8A779A0 (V3U) device support Ulrich Hecht
` (2 preceding siblings ...)
2020-11-26 17:21 ` [PATCH 03/11] pinctrl: renesas: r8a779a0: Add DU pins, groups and function Ulrich Hecht
@ 2020-11-26 17:21 ` Ulrich Hecht
2020-11-30 13:31 ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 05/11] pinctrl: renesas: r8a779a0: Add INTC-EX pins, groups and function Ulrich Hecht
` (7 subsequent siblings)
11 siblings, 1 reply; 26+ messages in thread
From: Ulrich Hecht @ 2020-11-26 17:21 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: wsa, geert, hoai.luu.ub, Ulrich Hecht
This patch adds HSCIF0-3 pins, groups and functions to the R8A779A0
(V3U) SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
---
drivers/pinctrl/renesas/pfc-r8a779a0.c | 134 +++++++++++++++++++++++++
1 file changed, 134 insertions(+)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c
index 9b1f140372fd..7b1fccf14956 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
@@ -1783,6 +1783,98 @@ static const unsigned int du_disp_mux[] = {
DU_ODDF_DISP_CDE_MARK,
};
+/* - HSCIF0 ----------------------------------------------------------------- */
+static const unsigned int hscif0_data_pins[] = {
+ /* HRX0, HTX0 */
+ RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 5),
+};
+static const unsigned int hscif0_data_mux[] = {
+ HRX0_MARK, HTX0_MARK,
+};
+static const unsigned int hscif0_clk_pins[] = {
+ /* HSCK0 */
+ RCAR_GP_PIN(1, 2),
+};
+static const unsigned int hscif0_clk_mux[] = {
+ HSCK0_MARK,
+};
+static const unsigned int hscif0_ctrl_pins[] = {
+ /* HRTS0#, HCTS0# */
+ RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
+};
+static const unsigned int hscif0_ctrl_mux[] = {
+ HRTS0_N_MARK, HCTS0_N_MARK,
+};
+
+/* - HSCIF1 ----------------------------------------------------------------- */
+static const unsigned int hscif1_data_pins[] = {
+ /* HRX1, HTX1 */
+ RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
+};
+static const unsigned int hscif1_data_mux[] = {
+ HRX1_MARK, HTX1_MARK,
+};
+static const unsigned int hscif1_clk_pins[] = {
+ /* HSCK1 */
+ RCAR_GP_PIN(1, 18),
+};
+static const unsigned int hscif1_clk_mux[] = {
+ HSCK1_MARK,
+};
+static const unsigned int hscif1_ctrl_pins[] = {
+ /* HRTS1#, HCTS1# */
+ RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19),
+};
+static const unsigned int hscif1_ctrl_mux[] = {
+ HRTS1_N_MARK, HCTS1_N_MARK,
+};
+
+/* - HSCIF2 ----------------------------------------------------------------- */
+static const unsigned int hscif2_data_pins[] = {
+ /* HRX2, HTX2 */
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+};
+static const unsigned int hscif2_data_mux[] = {
+ HRX2_MARK, HTX2_MARK,
+};
+static const unsigned int hscif2_clk_pins[] = {
+ /* HSCK2 */
+ RCAR_GP_PIN(2, 5),
+};
+static const unsigned int hscif2_clk_mux[] = {
+ HSCK2_MARK,
+};
+static const unsigned int hscif2_ctrl_pins[] = {
+ /* HRTS2#, HCTS2# */
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6),
+};
+static const unsigned int hscif2_ctrl_mux[] = {
+ HRTS2_N_MARK, HCTS2_N_MARK,
+};
+
+/* - HSCIF3 ----------------------------------------------------------------- */
+static const unsigned int hscif3_data_pins[] = {
+ /* HRX3, HTX3 */
+ RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 17),
+};
+static const unsigned int hscif3_data_mux[] = {
+ HRX3_MARK, HTX3_MARK,
+};
+static const unsigned int hscif3_clk_pins[] = {
+ /* HSCK3 */
+ RCAR_GP_PIN(1, 14),
+};
+static const unsigned int hscif3_clk_mux[] = {
+ HSCK3_MARK,
+};
+static const unsigned int hscif3_ctrl_pins[] = {
+ /* HRTS3#, HCTS3# */
+ RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
+};
+static const unsigned int hscif3_ctrl_mux[] = {
+ HRTS3_N_MARK, HCTS3_N_MARK,
+};
+
/* - I2C0 ------------------------------------------------------------------- */
static const unsigned int i2c0_pins[] = {
@@ -2025,6 +2117,19 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(du_disp),
+ SH_PFC_PIN_GROUP(hscif0_data),
+ SH_PFC_PIN_GROUP(hscif0_clk),
+ SH_PFC_PIN_GROUP(hscif0_ctrl),
+ SH_PFC_PIN_GROUP(hscif1_data),
+ SH_PFC_PIN_GROUP(hscif1_clk),
+ SH_PFC_PIN_GROUP(hscif1_ctrl),
+ SH_PFC_PIN_GROUP(hscif2_data),
+ SH_PFC_PIN_GROUP(hscif2_clk),
+ SH_PFC_PIN_GROUP(hscif2_ctrl),
+ SH_PFC_PIN_GROUP(hscif3_data),
+ SH_PFC_PIN_GROUP(hscif3_clk),
+ SH_PFC_PIN_GROUP(hscif3_ctrl),
+
SH_PFC_PIN_GROUP(i2c0),
SH_PFC_PIN_GROUP(i2c1),
SH_PFC_PIN_GROUP(i2c2),
@@ -2165,6 +2270,30 @@ static const char * const du_groups[] = {
"du_disp",
};
+static const char * const hscif0_groups[] = {
+ "hscif0_data",
+ "hscif0_clk",
+ "hscif0_ctrl",
+};
+
+static const char * const hscif1_groups[] = {
+ "hscif1_data",
+ "hscif1_clk",
+ "hscif1_ctrl",
+};
+
+static const char * const hscif2_groups[] = {
+ "hscif2_data",
+ "hscif2_clk",
+ "hscif2_ctrl",
+};
+
+static const char * const hscif3_groups[] = {
+ "hscif3_data",
+ "hscif3_clk",
+ "hscif3_ctrl",
+};
+
static const char * const i2c0_groups[] = {
"i2c0",
};
@@ -2241,6 +2370,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(du),
+ SH_PFC_FUNCTION(hscif0),
+ SH_PFC_FUNCTION(hscif1),
+ SH_PFC_FUNCTION(hscif2),
+ SH_PFC_FUNCTION(hscif3),
+
SH_PFC_FUNCTION(i2c0),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
--
2.20.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 04/11] pinctrl: renesas: r8a779a0: Add HSCIF pins, groups and functions
2020-11-26 17:21 ` [PATCH 04/11] pinctrl: renesas: r8a779a0: Add HSCIF pins, groups and functions Ulrich Hecht
@ 2020-11-30 13:31 ` Geert Uytterhoeven
0 siblings, 0 replies; 26+ messages in thread
From: Geert Uytterhoeven @ 2020-11-30 13:31 UTC (permalink / raw)
To: Ulrich Hecht; +Cc: Linux-Renesas, Wolfram Sang, hoai.luu.ub
On Thu, Nov 26, 2020 at 6:22 PM Ulrich Hecht <uli+renesas@fpond.eu> wrote:
> This patch adds HSCIF0-3 pins, groups and functions to the R8A779A0
> (V3U) SoC.
>
> Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 05/11] pinctrl: renesas: r8a779a0: Add INTC-EX pins, groups and function
2020-11-26 17:21 [PATCH 00/11] pinctrl: renesas: R8A779A0 (V3U) device support Ulrich Hecht
` (3 preceding siblings ...)
2020-11-26 17:21 ` [PATCH 04/11] pinctrl: renesas: r8a779a0: Add HSCIF pins, groups and functions Ulrich Hecht
@ 2020-11-26 17:21 ` Ulrich Hecht
2020-11-30 13:33 ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 06/11] pinctrl: renesas: r8a779a0: Add MMC pins, groups and functions Ulrich Hecht
` (6 subsequent siblings)
11 siblings, 1 reply; 26+ messages in thread
From: Ulrich Hecht @ 2020-11-26 17:21 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: wsa, geert, hoai.luu.ub, Ulrich Hecht
Add pins, groups, and function for the Interrupt Controller for External
Devices (INTC-EX) on the R-Car R8A779A0 (V3U) SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
---
drivers/pinctrl/renesas/pfc-r8a779a0.c | 62 ++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c
index 7b1fccf14956..8b5313a7917a 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
@@ -1939,6 +1939,50 @@ static const unsigned int i2c6_mux[] = {
GP2_15_MARK, GP2_14_MARK,
};
+/* - INTC-EX ---------------------------------------------------------------- */
+static const unsigned int intc_ex_irq0_pins[] = {
+ /* IRQ0 */
+ RCAR_GP_PIN(1, 24),
+};
+static const unsigned int intc_ex_irq0_mux[] = {
+ IRQ0_MARK,
+};
+static const unsigned int intc_ex_irq1_pins[] = {
+ /* IRQ1 */
+ RCAR_GP_PIN(1, 25),
+};
+static const unsigned int intc_ex_irq1_mux[] = {
+ IRQ1_MARK,
+};
+static const unsigned int intc_ex_irq2_pins[] = {
+ /* IRQ2 */
+ RCAR_GP_PIN(1, 26),
+};
+static const unsigned int intc_ex_irq2_mux[] = {
+ IRQ2_MARK,
+};
+static const unsigned int intc_ex_irq3_pins[] = {
+ /* IRQ3 */
+ RCAR_GP_PIN(1, 27),
+};
+static const unsigned int intc_ex_irq3_mux[] = {
+ IRQ3_MARK,
+};
+static const unsigned int intc_ex_irq4_pins[] = {
+ /* IRQ4 */
+ RCAR_GP_PIN(2, 14),
+};
+static const unsigned int intc_ex_irq4_mux[] = {
+ IRQ4_MARK,
+};
+static const unsigned int intc_ex_irq5_pins[] = {
+ /* IRQ5 */
+ RCAR_GP_PIN(2, 15),
+};
+static const unsigned int intc_ex_irq5_mux[] = {
+ IRQ5_MARK,
+};
+
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_pins[] = {
/* RX0, TX0 */
@@ -2138,6 +2182,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(i2c5),
SH_PFC_PIN_GROUP(i2c6),
+ SH_PFC_PIN_GROUP(intc_ex_irq0),
+ SH_PFC_PIN_GROUP(intc_ex_irq1),
+ SH_PFC_PIN_GROUP(intc_ex_irq2),
+ SH_PFC_PIN_GROUP(intc_ex_irq3),
+ SH_PFC_PIN_GROUP(intc_ex_irq4),
+ SH_PFC_PIN_GROUP(intc_ex_irq5),
+
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -2322,6 +2373,15 @@ static const char * const i2c6_groups[] = {
"i2c6",
};
+static const char * const intc_ex_groups[] = {
+ "intc_ex_irq0",
+ "intc_ex_irq1",
+ "intc_ex_irq2",
+ "intc_ex_irq3",
+ "intc_ex_irq4",
+ "intc_ex_irq5",
+};
+
static const char * const scif0_groups[] = {
"scif0_data",
"scif0_clk",
@@ -2383,6 +2443,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(i2c5),
SH_PFC_FUNCTION(i2c6),
+ SH_PFC_FUNCTION(intc_ex),
+
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif3),
--
2.20.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 05/11] pinctrl: renesas: r8a779a0: Add INTC-EX pins, groups and function
2020-11-26 17:21 ` [PATCH 05/11] pinctrl: renesas: r8a779a0: Add INTC-EX pins, groups and function Ulrich Hecht
@ 2020-11-30 13:33 ` Geert Uytterhoeven
0 siblings, 0 replies; 26+ messages in thread
From: Geert Uytterhoeven @ 2020-11-30 13:33 UTC (permalink / raw)
To: Ulrich Hecht; +Cc: Linux-Renesas, Wolfram Sang, hoai.luu.ub
On Thu, Nov 26, 2020 at 6:22 PM Ulrich Hecht <uli+renesas@fpond.eu> wrote:
> Add pins, groups, and function for the Interrupt Controller for External
> Devices (INTC-EX) on the R-Car R8A779A0 (V3U) SoC.
>
> Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 06/11] pinctrl: renesas: r8a779a0: Add MMC pins, groups and functions
2020-11-26 17:21 [PATCH 00/11] pinctrl: renesas: R8A779A0 (V3U) device support Ulrich Hecht
` (4 preceding siblings ...)
2020-11-26 17:21 ` [PATCH 05/11] pinctrl: renesas: r8a779a0: Add INTC-EX pins, groups and function Ulrich Hecht
@ 2020-11-26 17:21 ` Ulrich Hecht
2020-11-30 13:37 ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 07/11] pinctrl: renesas: r8a779a0: Add MSIOF " Ulrich Hecht
` (5 subsequent siblings)
11 siblings, 1 reply; 26+ messages in thread
From: Ulrich Hecht @ 2020-11-26 17:21 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: wsa, geert, hoai.luu.ub, Ulrich Hecht
This patch adds MMC pins, groups and functions to R8A779A0 (V3U) SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
---
drivers/pinctrl/renesas/pfc-r8a779a0.c | 79 ++++++++++++++++++++++++++
1 file changed, 79 insertions(+)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c
index 8b5313a7917a..854b60653d0c 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
@@ -1983,6 +1983,65 @@ static const unsigned int intc_ex_irq5_mux[] = {
IRQ5_MARK,
};
+/* - MMC -------------------------------------------------------------------- */
+static const unsigned int mmc_data1_pins[] = {
+ /* MMC_SD_D0 */
+ RCAR_GP_PIN(0, 19),
+};
+static const unsigned int mmc_data1_mux[] = {
+ MMC_SD_D0_MARK,
+};
+static const unsigned int mmc_data4_pins[] = {
+ /* MMC_SD_D[0:3] */
+ RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
+ RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
+};
+static const unsigned int mmc_data4_mux[] = {
+ MMC_SD_D0_MARK, MMC_SD_D1_MARK,
+ MMC_SD_D2_MARK, MMC_SD_D3_MARK,
+};
+static const unsigned int mmc_data8_pins[] = {
+ /* MMC_SD_D[0:3], MMC_D[4:7] */
+ RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
+ RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
+ RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
+ RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 27),
+};
+static const unsigned int mmc_data8_mux[] = {
+ MMC_SD_D0_MARK, MMC_SD_D1_MARK,
+ MMC_SD_D2_MARK, MMC_SD_D3_MARK,
+ MMC_D4_MARK, MMC_D5_MARK,
+ MMC_D6_MARK, MMC_D7_MARK,
+};
+static const unsigned int mmc_ctrl_pins[] = {
+ /* MMC_SD_CLK, MMC_SD_CMD */
+ RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 18),
+};
+static const unsigned int mmc_ctrl_mux[] = {
+ MMC_SD_CLK_MARK, MMC_SD_CMD_MARK,
+};
+static const unsigned int mmc_cd_pins[] = {
+ /* SD_CD */
+ RCAR_GP_PIN(0, 16),
+};
+static const unsigned int mmc_cd_mux[] = {
+ SD_CD_MARK,
+};
+static const unsigned int mmc_wp_pins[] = {
+ /* SD_WP */
+ RCAR_GP_PIN(0, 15),
+};
+static const unsigned int mmc_wp_mux[] = {
+ SD_WP_MARK,
+};
+static const unsigned int mmc_ds_pins[] = {
+ /* MMC_DS */
+ RCAR_GP_PIN(0, 17),
+};
+static const unsigned int mmc_ds_mux[] = {
+ MMC_DS_MARK,
+};
+
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_pins[] = {
/* RX0, TX0 */
@@ -2189,6 +2248,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(intc_ex_irq4),
SH_PFC_PIN_GROUP(intc_ex_irq5),
+ SH_PFC_PIN_GROUP(mmc_data1),
+ SH_PFC_PIN_GROUP(mmc_data4),
+ SH_PFC_PIN_GROUP(mmc_data8),
+ SH_PFC_PIN_GROUP(mmc_ctrl),
+ SH_PFC_PIN_GROUP(mmc_cd),
+ SH_PFC_PIN_GROUP(mmc_wp),
+ SH_PFC_PIN_GROUP(mmc_ds),
+
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -2382,6 +2449,16 @@ static const char * const intc_ex_groups[] = {
"intc_ex_irq5",
};
+static const char * const mmc_groups[] = {
+ "mmc_data1",
+ "mmc_data4",
+ "mmc_data8",
+ "mmc_ctrl",
+ "mmc_cd",
+ "mmc_wp",
+ "mmc_ds",
+};
+
static const char * const scif0_groups[] = {
"scif0_data",
"scif0_clk",
@@ -2445,6 +2522,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(intc_ex),
+ SH_PFC_FUNCTION(mmc),
+
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif3),
--
2.20.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 06/11] pinctrl: renesas: r8a779a0: Add MMC pins, groups and functions
2020-11-26 17:21 ` [PATCH 06/11] pinctrl: renesas: r8a779a0: Add MMC pins, groups and functions Ulrich Hecht
@ 2020-11-30 13:37 ` Geert Uytterhoeven
0 siblings, 0 replies; 26+ messages in thread
From: Geert Uytterhoeven @ 2020-11-30 13:37 UTC (permalink / raw)
To: Ulrich Hecht; +Cc: Linux-Renesas, Wolfram Sang, hoai.luu.ub
On Thu, Nov 26, 2020 at 6:22 PM Ulrich Hecht <uli+renesas@fpond.eu> wrote:
> This patch adds MMC pins, groups and functions to R8A779A0 (V3U) SoC.
>
> Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 07/11] pinctrl: renesas: r8a779a0: Add MSIOF pins, groups and functions
2020-11-26 17:21 [PATCH 00/11] pinctrl: renesas: R8A779A0 (V3U) device support Ulrich Hecht
` (5 preceding siblings ...)
2020-11-26 17:21 ` [PATCH 06/11] pinctrl: renesas: r8a779a0: Add MMC pins, groups and functions Ulrich Hecht
@ 2020-11-26 17:21 ` Ulrich Hecht
2020-11-30 13:43 ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 08/11] pinctrl: renesas: r8a779a0: Add PWM " Ulrich Hecht
` (4 subsequent siblings)
11 siblings, 1 reply; 26+ messages in thread
From: Ulrich Hecht @ 2020-11-26 17:21 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: wsa, geert, hoai.luu.ub, Ulrich Hecht
This patch adds MSIOF0-5 pins, groups and functions to R8A779A0 (V3U)
SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
---
drivers/pinctrl/renesas/pfc-r8a779a0.c | 330 +++++++++++++++++++++++++
1 file changed, 330 insertions(+)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c
index 854b60653d0c..403c6fca3282 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
@@ -2042,6 +2042,270 @@ static const unsigned int mmc_ds_mux[] = {
MMC_DS_MARK,
};
+/* - MSIOF0 ----------------------------------------------------------------- */
+static const unsigned int msiof0_clk_pins[] = {
+ /* MSIOF0_SCK */
+ RCAR_GP_PIN(1, 8),
+};
+static const unsigned int msiof0_clk_mux[] = {
+ MSIOF0_SCK_MARK,
+};
+static const unsigned int msiof0_sync_pins[] = {
+ /* MSIOF0_SYNC */
+ RCAR_GP_PIN(1, 9),
+};
+static const unsigned int msiof0_sync_mux[] = {
+ MSIOF0_SYNC_MARK,
+};
+static const unsigned int msiof0_ss1_pins[] = {
+ /* MSIOF0_SS1 */
+ RCAR_GP_PIN(1, 10),
+};
+static const unsigned int msiof0_ss1_mux[] = {
+ MSIOF0_SS1_MARK,
+};
+static const unsigned int msiof0_ss2_pins[] = {
+ /* MSIOF0_SS2 */
+ RCAR_GP_PIN(1, 11),
+};
+static const unsigned int msiof0_ss2_mux[] = {
+ MSIOF0_SS2_MARK,
+};
+static const unsigned int msiof0_txd_pins[] = {
+ /* MSIOF0_TXD */
+ RCAR_GP_PIN(1, 7),
+};
+static const unsigned int msiof0_txd_mux[] = {
+ MSIOF0_TXD_MARK,
+};
+static const unsigned int msiof0_rxd_pins[] = {
+ /* MSIOF0_RXD */
+ RCAR_GP_PIN(1, 6),
+};
+static const unsigned int msiof0_rxd_mux[] = {
+ MSIOF0_RXD_MARK,
+};
+
+/* - MSIOF1 ----------------------------------------------------------------- */
+static const unsigned int msiof1_clk_pins[] = {
+ /* MSIOF1_SCK */
+ RCAR_GP_PIN(1, 14),
+};
+static const unsigned int msiof1_clk_mux[] = {
+ MSIOF1_SCK_MARK,
+};
+static const unsigned int msiof1_sync_pins[] = {
+ /* MSIOF1_SYNC */
+ RCAR_GP_PIN(1, 15),
+};
+static const unsigned int msiof1_sync_mux[] = {
+ MSIOF1_SYNC_MARK,
+};
+static const unsigned int msiof1_ss1_pins[] = {
+ /* MSIOF1_SS1 */
+ RCAR_GP_PIN(1, 16),
+};
+static const unsigned int msiof1_ss1_mux[] = {
+ MSIOF1_SS1_MARK,
+};
+static const unsigned int msiof1_ss2_pins[] = {
+ /* MSIOF1_SS2 */
+ RCAR_GP_PIN(1, 17),
+};
+static const unsigned int msiof1_ss2_mux[] = {
+ MSIOF1_SS2_MARK,
+};
+static const unsigned int msiof1_txd_pins[] = {
+ /* MSIOF1_TXD */
+ RCAR_GP_PIN(1, 13),
+};
+static const unsigned int msiof1_txd_mux[] = {
+ MSIOF1_TXD_MARK,
+};
+static const unsigned int msiof1_rxd_pins[] = {
+ /* MSIOF1_RXD */
+ RCAR_GP_PIN(1, 12),
+};
+static const unsigned int msiof1_rxd_mux[] = {
+ MSIOF1_RXD_MARK,
+};
+
+/* - MSIOF2 ----------------------------------------------------------------- */
+static const unsigned int msiof2_clk_pins[] = {
+ /* MSIOF2_SCK */
+ RCAR_GP_PIN(1, 20),
+};
+static const unsigned int msiof2_clk_mux[] = {
+ MSIOF2_SCK_MARK,
+};
+static const unsigned int msiof2_sync_pins[] = {
+ /* MSIOF2_SYNC */
+ RCAR_GP_PIN(1, 21),
+};
+static const unsigned int msiof2_sync_mux[] = {
+ MSIOF2_SYNC_MARK,
+};
+static const unsigned int msiof2_ss1_pins[] = {
+ /* MSIOF2_SS1 */
+ RCAR_GP_PIN(1, 22),
+};
+static const unsigned int msiof2_ss1_mux[] = {
+ MSIOF2_SS1_MARK,
+};
+static const unsigned int msiof2_ss2_pins[] = {
+ /* MSIOF2_SS2 */
+ RCAR_GP_PIN(1, 23),
+};
+static const unsigned int msiof2_ss2_mux[] = {
+ MSIOF2_SS2_MARK,
+};
+static const unsigned int msiof2_txd_pins[] = {
+ /* MSIOF2_TXD */
+ RCAR_GP_PIN(1, 19),
+};
+static const unsigned int msiof2_txd_mux[] = {
+ MSIOF2_TXD_MARK,
+};
+static const unsigned int msiof2_rxd_pins[] = {
+ /* MSIOF2_RXD */
+ RCAR_GP_PIN(1, 18),
+};
+static const unsigned int msiof2_rxd_mux[] = {
+ MSIOF2_RXD_MARK,
+};
+
+/* - MSIOF3 ----------------------------------------------------------------- */
+static const unsigned int msiof3_clk_pins[] = {
+ /* MSIOF3_SCK */
+ RCAR_GP_PIN(2, 20),
+};
+static const unsigned int msiof3_clk_mux[] = {
+ MSIOF3_SCK_MARK,
+};
+static const unsigned int msiof3_sync_pins[] = {
+ /* MSIOF3_SYNC */
+ RCAR_GP_PIN(2, 21),
+};
+static const unsigned int msiof3_sync_mux[] = {
+ MSIOF3_SYNC_MARK,
+};
+static const unsigned int msiof3_ss1_pins[] = {
+ /* MSIOF3_SS1 */
+ RCAR_GP_PIN(2, 16),
+};
+static const unsigned int msiof3_ss1_mux[] = {
+ MSIOF3_SS1_MARK,
+};
+static const unsigned int msiof3_ss2_pins[] = {
+ /* MSIOF3_SS2 */
+ RCAR_GP_PIN(2, 17),
+};
+static const unsigned int msiof3_ss2_mux[] = {
+ MSIOF3_SS2_MARK,
+};
+static const unsigned int msiof3_txd_pins[] = {
+ /* MSIOF3_TXD */
+ RCAR_GP_PIN(2, 19),
+};
+static const unsigned int msiof3_txd_mux[] = {
+ MSIOF3_TXD_MARK,
+};
+static const unsigned int msiof3_rxd_pins[] = {
+ /* MSIOF3_RXD */
+ RCAR_GP_PIN(2, 18),
+};
+static const unsigned int msiof3_rxd_mux[] = {
+ MSIOF3_RXD_MARK,
+};
+
+/* - MSIOF4 ----------------------------------------------------------------- */
+static const unsigned int msiof4_clk_pins[] = {
+ /* MSIOF4_SCK */
+ RCAR_GP_PIN(2, 6),
+};
+static const unsigned int msiof4_clk_mux[] = {
+ MSIOF4_SCK_MARK,
+};
+static const unsigned int msiof4_sync_pins[] = {
+ /* MSIOF4_SYNC */
+ RCAR_GP_PIN(2, 7),
+};
+static const unsigned int msiof4_sync_mux[] = {
+ MSIOF4_SYNC_MARK,
+};
+static const unsigned int msiof4_ss1_pins[] = {
+ /* MSIOF4_SS1 */
+ RCAR_GP_PIN(2, 8),
+};
+static const unsigned int msiof4_ss1_mux[] = {
+ MSIOF4_SS1_MARK,
+};
+static const unsigned int msiof4_ss2_pins[] = {
+ /* MSIOF4_SS2 */
+ RCAR_GP_PIN(2, 9),
+};
+static const unsigned int msiof4_ss2_mux[] = {
+ MSIOF4_SS2_MARK,
+};
+static const unsigned int msiof4_txd_pins[] = {
+ /* MSIOF4_TXD */
+ RCAR_GP_PIN(2, 5),
+};
+static const unsigned int msiof4_txd_mux[] = {
+ MSIOF4_TXD_MARK,
+};
+static const unsigned int msiof4_rxd_pins[] = {
+ /* MSIOF4_RXD */
+ RCAR_GP_PIN(2, 4),
+};
+static const unsigned int msiof4_rxd_mux[] = {
+ MSIOF4_RXD_MARK,
+};
+
+/* - MSIOF5 ----------------------------------------------------------------- */
+static const unsigned int msiof5_clk_pins[] = {
+ /* MSIOF5_SCK */
+ RCAR_GP_PIN(2, 12),
+};
+static const unsigned int msiof5_clk_mux[] = {
+ MSIOF5_SCK_MARK,
+};
+static const unsigned int msiof5_sync_pins[] = {
+ /* MSIOF5_SYNC */
+ RCAR_GP_PIN(2, 13),
+};
+static const unsigned int msiof5_sync_mux[] = {
+ MSIOF5_SYNC_MARK,
+};
+static const unsigned int msiof5_ss1_pins[] = {
+ /* MSIOF5_SS1 */
+ RCAR_GP_PIN(2, 14),
+};
+static const unsigned int msiof5_ss1_mux[] = {
+ MSIOF5_SS1_MARK,
+};
+static const unsigned int msiof5_ss2_pins[] = {
+ /* MSIOF5_SS2 */
+ RCAR_GP_PIN(2, 15),
+};
+static const unsigned int msiof5_ss2_mux[] = {
+ MSIOF5_SS2_MARK,
+};
+static const unsigned int msiof5_txd_pins[] = {
+ /* MSIOF5_TXD */
+ RCAR_GP_PIN(2, 11),
+};
+static const unsigned int msiof5_txd_mux[] = {
+ MSIOF5_TXD_MARK,
+};
+static const unsigned int msiof5_rxd_pins[] = {
+ /* MSIOF5_RXD */
+ RCAR_GP_PIN(2, 10),
+};
+static const unsigned int msiof5_rxd_mux[] = {
+ MSIOF5_RXD_MARK,
+};
+
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_pins[] = {
/* RX0, TX0 */
@@ -2256,6 +2520,31 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(mmc_wp),
SH_PFC_PIN_GROUP(mmc_ds),
+ SH_PFC_PIN_GROUP(msiof0_clk),
+ SH_PFC_PIN_GROUP(msiof0_sync),
+ SH_PFC_PIN_GROUP(msiof0_ss1),
+ SH_PFC_PIN_GROUP(msiof0_ss2),
+ SH_PFC_PIN_GROUP(msiof0_txd),
+ SH_PFC_PIN_GROUP(msiof0_rxd),
+ SH_PFC_PIN_GROUP(msiof1_clk),
+ SH_PFC_PIN_GROUP(msiof1_sync),
+ SH_PFC_PIN_GROUP(msiof1_ss1),
+ SH_PFC_PIN_GROUP(msiof1_ss2),
+ SH_PFC_PIN_GROUP(msiof1_txd),
+ SH_PFC_PIN_GROUP(msiof1_rxd),
+ SH_PFC_PIN_GROUP(msiof2_clk),
+ SH_PFC_PIN_GROUP(msiof2_sync),
+ SH_PFC_PIN_GROUP(msiof2_ss1),
+ SH_PFC_PIN_GROUP(msiof2_ss2),
+ SH_PFC_PIN_GROUP(msiof2_txd),
+ SH_PFC_PIN_GROUP(msiof2_rxd),
+ SH_PFC_PIN_GROUP(msiof3_clk),
+ SH_PFC_PIN_GROUP(msiof3_sync),
+ SH_PFC_PIN_GROUP(msiof3_ss1),
+ SH_PFC_PIN_GROUP(msiof3_ss2),
+ SH_PFC_PIN_GROUP(msiof3_txd),
+ SH_PFC_PIN_GROUP(msiof3_rxd),
+
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -2459,6 +2748,42 @@ static const char * const mmc_groups[] = {
"mmc_ds",
};
+static const char * const msiof0_groups[] = {
+ "msiof0_clk",
+ "msiof0_sync",
+ "msiof0_ss1",
+ "msiof0_ss2",
+ "msiof0_txd",
+ "msiof0_rxd",
+};
+
+static const char * const msiof1_groups[] = {
+ "msiof1_clk",
+ "msiof1_sync",
+ "msiof1_ss1",
+ "msiof1_ss2",
+ "msiof1_txd",
+ "msiof1_rxd",
+};
+
+static const char * const msiof2_groups[] = {
+ "msiof2_clk",
+ "msiof2_sync",
+ "msiof2_ss1",
+ "msiof2_ss2",
+ "msiof2_txd",
+ "msiof2_rxd",
+};
+
+static const char * const msiof3_groups[] = {
+ "msiof3_clk",
+ "msiof3_sync",
+ "msiof3_ss1",
+ "msiof3_ss2",
+ "msiof3_txd",
+ "msiof3_rxd",
+};
+
static const char * const scif0_groups[] = {
"scif0_data",
"scif0_clk",
@@ -2524,6 +2849,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(mmc),
+ SH_PFC_FUNCTION(msiof0),
+ SH_PFC_FUNCTION(msiof1),
+ SH_PFC_FUNCTION(msiof2),
+ SH_PFC_FUNCTION(msiof3),
+
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif3),
--
2.20.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 07/11] pinctrl: renesas: r8a779a0: Add MSIOF pins, groups and functions
2020-11-26 17:21 ` [PATCH 07/11] pinctrl: renesas: r8a779a0: Add MSIOF " Ulrich Hecht
@ 2020-11-30 13:43 ` Geert Uytterhoeven
0 siblings, 0 replies; 26+ messages in thread
From: Geert Uytterhoeven @ 2020-11-30 13:43 UTC (permalink / raw)
To: Ulrich Hecht; +Cc: Linux-Renesas, Wolfram Sang, hoai.luu.ub
Hi Uli,
On Thu, Nov 26, 2020 at 6:22 PM Ulrich Hecht <uli+renesas@fpond.eu> wrote:
> This patch adds MSIOF0-5 pins, groups and functions to R8A779A0 (V3U)
> SoC.
>
> Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Thanks for your patch!
> --- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
> @@ -2256,6 +2520,31 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
> SH_PFC_PIN_GROUP(mmc_wp),
> SH_PFC_PIN_GROUP(mmc_ds),
>
> + SH_PFC_PIN_GROUP(msiof0_clk),
> + SH_PFC_PIN_GROUP(msiof0_sync),
> + SH_PFC_PIN_GROUP(msiof0_ss1),
> + SH_PFC_PIN_GROUP(msiof0_ss2),
> + SH_PFC_PIN_GROUP(msiof0_txd),
> + SH_PFC_PIN_GROUP(msiof0_rxd),
> + SH_PFC_PIN_GROUP(msiof1_clk),
> + SH_PFC_PIN_GROUP(msiof1_sync),
> + SH_PFC_PIN_GROUP(msiof1_ss1),
> + SH_PFC_PIN_GROUP(msiof1_ss2),
> + SH_PFC_PIN_GROUP(msiof1_txd),
> + SH_PFC_PIN_GROUP(msiof1_rxd),
> + SH_PFC_PIN_GROUP(msiof2_clk),
> + SH_PFC_PIN_GROUP(msiof2_sync),
> + SH_PFC_PIN_GROUP(msiof2_ss1),
> + SH_PFC_PIN_GROUP(msiof2_ss2),
> + SH_PFC_PIN_GROUP(msiof2_txd),
> + SH_PFC_PIN_GROUP(msiof2_rxd),
> + SH_PFC_PIN_GROUP(msiof3_clk),
> + SH_PFC_PIN_GROUP(msiof3_sync),
> + SH_PFC_PIN_GROUP(msiof3_ss1),
> + SH_PFC_PIN_GROUP(msiof3_ss2),
> + SH_PFC_PIN_GROUP(msiof3_txd),
> + SH_PFC_PIN_GROUP(msiof3_rxd),
What happened to msiof[45]?
> +
> SH_PFC_PIN_GROUP(scif0_data),
> SH_PFC_PIN_GROUP(scif0_clk),
> SH_PFC_PIN_GROUP(scif0_ctrl),
> @@ -2459,6 +2748,42 @@ static const char * const mmc_groups[] = {
> "mmc_ds",
> };
>
> +static const char * const msiof0_groups[] = {
> + "msiof0_clk",
> + "msiof0_sync",
> + "msiof0_ss1",
> + "msiof0_ss2",
> + "msiof0_txd",
> + "msiof0_rxd",
> +};
> +
> +static const char * const msiof1_groups[] = {
> + "msiof1_clk",
> + "msiof1_sync",
> + "msiof1_ss1",
> + "msiof1_ss2",
> + "msiof1_txd",
> + "msiof1_rxd",
> +};
> +
> +static const char * const msiof2_groups[] = {
> + "msiof2_clk",
> + "msiof2_sync",
> + "msiof2_ss1",
> + "msiof2_ss2",
> + "msiof2_txd",
> + "msiof2_rxd",
> +};
> +
> +static const char * const msiof3_groups[] = {
> + "msiof3_clk",
> + "msiof3_sync",
> + "msiof3_ss1",
> + "msiof3_ss2",
> + "msiof3_txd",
> + "msiof3_rxd",
> +};
Likewise.
> +
> static const char * const scif0_groups[] = {
> "scif0_data",
> "scif0_clk",
> @@ -2524,6 +2849,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
>
> SH_PFC_FUNCTION(mmc),
>
> + SH_PFC_FUNCTION(msiof0),
> + SH_PFC_FUNCTION(msiof1),
> + SH_PFC_FUNCTION(msiof2),
> + SH_PFC_FUNCTION(msiof3),
Likewise.
> +
> SH_PFC_FUNCTION(scif0),
> SH_PFC_FUNCTION(scif1),
> SH_PFC_FUNCTION(scif3),
With the missing entries added:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 08/11] pinctrl: renesas: r8a779a0: Add PWM pins, groups and functions
2020-11-26 17:21 [PATCH 00/11] pinctrl: renesas: R8A779A0 (V3U) device support Ulrich Hecht
` (6 preceding siblings ...)
2020-11-26 17:21 ` [PATCH 07/11] pinctrl: renesas: r8a779a0: Add MSIOF " Ulrich Hecht
@ 2020-11-26 17:21 ` Ulrich Hecht
2020-11-30 13:45 ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 09/11] pinctrl: renesas: r8a779a0: Add QSPI pins, groups, " Ulrich Hecht
` (3 subsequent siblings)
11 siblings, 1 reply; 26+ messages in thread
From: Ulrich Hecht @ 2020-11-26 17:21 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: wsa, geert, hoai.luu.ub, Ulrich Hecht
This patch adds PWM0-4 pins, groups and functions to the R8A779A0 (V3U)
SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
---
drivers/pinctrl/renesas/pfc-r8a779a0.c | 77 ++++++++++++++++++++++++++
1 file changed, 77 insertions(+)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c
index 403c6fca3282..a5ed01a50857 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
@@ -2306,6 +2306,51 @@ static const unsigned int msiof5_rxd_mux[] = {
MSIOF5_RXD_MARK,
};
+/* - PWM0 ------------------------------------------------------------------- */
+static const unsigned int pwm0_pins[] = {
+ /* PWM0 */
+ RCAR_GP_PIN(3, 5),
+};
+static const unsigned int pwm0_mux[] = {
+ PWM0_MARK,
+};
+
+/* - PWM1 ------------------------------------------------------------------- */
+static const unsigned int pwm1_pins[] = {
+ /* PWM1 */
+ RCAR_GP_PIN(3, 6),
+};
+static const unsigned int pwm1_mux[] = {
+ PWM1_MARK,
+};
+
+/* - PWM2 ------------------------------------------------------------------- */
+static const unsigned int pwm2_pins[] = {
+ /* PWM2 */
+ RCAR_GP_PIN(3, 7),
+};
+static const unsigned int pwm2_mux[] = {
+ PWM2_MARK,
+};
+
+/* - PWM3 ------------------------------------------------------------------- */
+static const unsigned int pwm3_pins[] = {
+ /* PWM3 */
+ RCAR_GP_PIN(3, 8),
+};
+static const unsigned int pwm3_mux[] = {
+ PWM3_MARK,
+};
+
+/* - PWM4 ------------------------------------------------------------------- */
+static const unsigned int pwm4_pins[] = {
+ /* PWM4 */
+ RCAR_GP_PIN(3, 9),
+};
+static const unsigned int pwm4_mux[] = {
+ PWM4_MARK,
+};
+
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_pins[] = {
/* RX0, TX0 */
@@ -2545,6 +2590,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(msiof3_txd),
SH_PFC_PIN_GROUP(msiof3_rxd),
+ SH_PFC_PIN_GROUP(pwm0),
+ SH_PFC_PIN_GROUP(pwm1),
+ SH_PFC_PIN_GROUP(pwm2),
+ SH_PFC_PIN_GROUP(pwm3),
+ SH_PFC_PIN_GROUP(pwm4),
+
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -2784,6 +2835,26 @@ static const char * const msiof3_groups[] = {
"msiof3_rxd",
};
+static const char * const pwm0_groups[] = {
+ "pwm0",
+};
+
+static const char * const pwm1_groups[] = {
+ "pwm1",
+};
+
+static const char * const pwm2_groups[] = {
+ "pwm2",
+};
+
+static const char * const pwm3_groups[] = {
+ "pwm3",
+};
+
+static const char * const pwm4_groups[] = {
+ "pwm4",
+};
+
static const char * const scif0_groups[] = {
"scif0_data",
"scif0_clk",
@@ -2854,6 +2925,12 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(msiof2),
SH_PFC_FUNCTION(msiof3),
+ SH_PFC_FUNCTION(pwm0),
+ SH_PFC_FUNCTION(pwm1),
+ SH_PFC_FUNCTION(pwm2),
+ SH_PFC_FUNCTION(pwm3),
+ SH_PFC_FUNCTION(pwm4),
+
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif3),
--
2.20.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 08/11] pinctrl: renesas: r8a779a0: Add PWM pins, groups and functions
2020-11-26 17:21 ` [PATCH 08/11] pinctrl: renesas: r8a779a0: Add PWM " Ulrich Hecht
@ 2020-11-30 13:45 ` Geert Uytterhoeven
0 siblings, 0 replies; 26+ messages in thread
From: Geert Uytterhoeven @ 2020-11-30 13:45 UTC (permalink / raw)
To: Ulrich Hecht; +Cc: Linux-Renesas, Wolfram Sang, hoai.luu.ub
On Thu, Nov 26, 2020 at 6:22 PM Ulrich Hecht <uli+renesas@fpond.eu> wrote:
> This patch adds PWM0-4 pins, groups and functions to the R8A779A0 (V3U)
> SoC.
>
> Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 09/11] pinctrl: renesas: r8a779a0: Add QSPI pins, groups, and functions
2020-11-26 17:21 [PATCH 00/11] pinctrl: renesas: R8A779A0 (V3U) device support Ulrich Hecht
` (7 preceding siblings ...)
2020-11-26 17:21 ` [PATCH 08/11] pinctrl: renesas: r8a779a0: Add PWM " Ulrich Hecht
@ 2020-11-26 17:21 ` Ulrich Hecht
2020-11-30 13:49 ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 10/11] pinctrl: renesas: r8a779a0: Add TMU pins, groups " Ulrich Hecht
` (2 subsequent siblings)
11 siblings, 1 reply; 26+ messages in thread
From: Ulrich Hecht @ 2020-11-26 17:21 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: wsa, geert, hoai.luu.ub, Ulrich Hecht
Add the QSPI0-1 pins, groups and functions to the R8A779A0 (V3U) PFC
driver.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
---
drivers/pinctrl/renesas/pfc-r8a779a0.c | 72 ++++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c
index a5ed01a50857..a83b6fa9ab9e 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
@@ -2351,6 +2351,56 @@ static const unsigned int pwm4_mux[] = {
PWM4_MARK,
};
+/* - QSPI0 ------------------------------------------------------------------ */
+static const unsigned int qspi0_ctrl_pins[] = {
+ /* SPCLK, SSL */
+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 5),
+};
+static const unsigned int qspi0_ctrl_mux[] = {
+ QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
+};
+static const unsigned int qspi0_data2_pins[] = {
+ /* MOSI_IO0, MISO_IO1 */
+ RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
+};
+static const unsigned int qspi0_data2_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+};
+static const unsigned int qspi0_data4_pins[] = {
+ /* MOSI_IO0, MISO_IO1, IO2, IO3 */
+ RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
+ RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
+};
+static const unsigned int qspi0_data4_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+ QSPI0_IO2_MARK, QSPI0_IO3_MARK
+};
+
+/* - QSPI1 ------------------------------------------------------------------ */
+static const unsigned int qspi1_ctrl_pins[] = {
+ /* SPCLK, SSL */
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 11),
+};
+static const unsigned int qspi1_ctrl_mux[] = {
+ QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
+};
+static const unsigned int qspi1_data2_pins[] = {
+ /* MOSI_IO0, MISO_IO1 */
+ RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
+};
+static const unsigned int qspi1_data2_mux[] = {
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+};
+static const unsigned int qspi1_data4_pins[] = {
+ /* MOSI_IO0, MISO_IO1, IO2, IO3 */
+ RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
+ RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
+};
+static const unsigned int qspi1_data4_mux[] = {
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+ QSPI1_IO2_MARK, QSPI1_IO3_MARK
+};
+
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_pins[] = {
/* RX0, TX0 */
@@ -2596,6 +2646,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(pwm3),
SH_PFC_PIN_GROUP(pwm4),
+ SH_PFC_PIN_GROUP(qspi0_ctrl),
+ SH_PFC_PIN_GROUP(qspi0_data2),
+ SH_PFC_PIN_GROUP(qspi0_data4),
+ SH_PFC_PIN_GROUP(qspi1_ctrl),
+ SH_PFC_PIN_GROUP(qspi1_data2),
+ SH_PFC_PIN_GROUP(qspi1_data4),
+
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -2855,6 +2912,18 @@ static const char * const pwm4_groups[] = {
"pwm4",
};
+static const char * const qspi0_groups[] = {
+ "qspi0_ctrl",
+ "qspi0_data2",
+ "qspi0_data4",
+};
+
+static const char * const qspi1_groups[] = {
+ "qspi1_ctrl",
+ "qspi1_data2",
+ "qspi1_data4",
+};
+
static const char * const scif0_groups[] = {
"scif0_data",
"scif0_clk",
@@ -2931,6 +3000,9 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(pwm3),
SH_PFC_FUNCTION(pwm4),
+ SH_PFC_FUNCTION(qspi0),
+ SH_PFC_FUNCTION(qspi1),
+
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif3),
--
2.20.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 09/11] pinctrl: renesas: r8a779a0: Add QSPI pins, groups, and functions
2020-11-26 17:21 ` [PATCH 09/11] pinctrl: renesas: r8a779a0: Add QSPI pins, groups, " Ulrich Hecht
@ 2020-11-30 13:49 ` Geert Uytterhoeven
0 siblings, 0 replies; 26+ messages in thread
From: Geert Uytterhoeven @ 2020-11-30 13:49 UTC (permalink / raw)
To: Ulrich Hecht; +Cc: Linux-Renesas, Wolfram Sang, hoai.luu.ub
On Thu, Nov 26, 2020 at 6:22 PM Ulrich Hecht <uli+renesas@fpond.eu> wrote:
> Add the QSPI0-1 pins, groups and functions to the R8A779A0 (V3U) PFC
> driver.
>
> Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 10/11] pinctrl: renesas: r8a779a0: Add TMU pins, groups and functions
2020-11-26 17:21 [PATCH 00/11] pinctrl: renesas: R8A779A0 (V3U) device support Ulrich Hecht
` (8 preceding siblings ...)
2020-11-26 17:21 ` [PATCH 09/11] pinctrl: renesas: r8a779a0: Add QSPI pins, groups, " Ulrich Hecht
@ 2020-11-26 17:21 ` Ulrich Hecht
2020-11-30 13:57 ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 11/11] pinctrl: renesas: r8a779a0: Add TPU " Ulrich Hecht
2020-11-27 10:33 ` [PATCH 00/11] pinctrl: renesas: R8A779A0 (V3U) device support Geert Uytterhoeven
11 siblings, 1 reply; 26+ messages in thread
From: Ulrich Hecht @ 2020-11-26 17:21 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: wsa, geert, hoai.luu.ub, Ulrich Hecht
This patch adds TMU TCLK1-4 pins, groups and functions to the R8A779A0
(V3U) SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
---
drivers/pinctrl/renesas/pfc-r8a779a0.c | 47 ++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c
index a83b6fa9ab9e..4aa725b3fbca 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
@@ -2502,6 +2502,39 @@ static const unsigned int scif_clk_mux[] = {
SCIF_CLK_MARK,
};
+/* - TMU -------------------------------------------------------------------- */
+static const unsigned int tmu_tclk1_pins[] = {
+ /* TCLK1 */
+ RCAR_GP_PIN(2, 23),
+};
+static const unsigned int tmu_tclk1_mux[] = {
+ TCLK1_MARK,
+};
+
+static const unsigned int tmu_tclk2_pins[] = {
+ /* TCLK2 */
+ RCAR_GP_PIN(2, 24),
+};
+static const unsigned int tmu_tclk2_mux[] = {
+ TCLK2_MARK,
+};
+
+static const unsigned int tmu_tclk3_pins[] = {
+ /* TCLK3 */
+ RCAR_GP_PIN(2, 11),
+};
+static const unsigned int tmu_tclk3_mux[] = {
+ TCLK3_MARK,
+};
+
+static const unsigned int tmu_tclk4_pins[] = {
+ /* TCLK4 */
+ RCAR_GP_PIN(2, 12),
+};
+static const unsigned int tmu_tclk4_mux[] = {
+ TCLK4_MARK,
+};
+
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(avb0_link),
SH_PFC_PIN_GROUP(avb0_magic),
@@ -2666,6 +2699,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scif4_clk),
SH_PFC_PIN_GROUP(scif4_ctrl),
SH_PFC_PIN_GROUP(scif_clk),
+
+ SH_PFC_PIN_GROUP(tmu_tclk1),
+ SH_PFC_PIN_GROUP(tmu_tclk2),
+ SH_PFC_PIN_GROUP(tmu_tclk3),
+ SH_PFC_PIN_GROUP(tmu_tclk4),
};
static const char * const avb0_groups[] = {
@@ -2952,6 +2990,13 @@ static const char * const scif_clk_groups[] = {
"scif_clk",
};
+static const char * const tmu_groups[] = {
+ "tmu_tclk1",
+ "tmu_tclk2",
+ "tmu_tclk3",
+ "tmu_tclk4",
+};
+
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(avb0),
SH_PFC_FUNCTION(avb1),
@@ -3008,6 +3053,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(scif3),
SH_PFC_FUNCTION(scif4),
SH_PFC_FUNCTION(scif_clk),
+
+ SH_PFC_FUNCTION(tmu),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
--
2.20.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 10/11] pinctrl: renesas: r8a779a0: Add TMU pins, groups and functions
2020-11-26 17:21 ` [PATCH 10/11] pinctrl: renesas: r8a779a0: Add TMU pins, groups " Ulrich Hecht
@ 2020-11-30 13:57 ` Geert Uytterhoeven
0 siblings, 0 replies; 26+ messages in thread
From: Geert Uytterhoeven @ 2020-11-30 13:57 UTC (permalink / raw)
To: Ulrich Hecht; +Cc: Linux-Renesas, Wolfram Sang, hoai.luu.ub
Hi Uli,
On Thu, Nov 26, 2020 at 6:22 PM Ulrich Hecht <uli+renesas@fpond.eu> wrote:
> This patch adds TMU TCLK1-4 pins, groups and functions to the R8A779A0
> (V3U) SoC.
>
> Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Thanks for your patch!
> ---
> drivers/pinctrl/renesas/pfc-r8a779a0.c | 47 ++++++++++++++++++++++++++
> 1 file changed, 47 insertions(+)
>
> diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c
> index a83b6fa9ab9e..4aa725b3fbca 100644
> --- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
> @@ -2502,6 +2502,39 @@ static const unsigned int scif_clk_mux[] = {
> SCIF_CLK_MARK,
> };
>
> +/* - TMU -------------------------------------------------------------------- */
> +static const unsigned int tmu_tclk1_pins[] = {
> + /* TCLK1 */
> + RCAR_GP_PIN(2, 23),
> +};
> +static const unsigned int tmu_tclk1_mux[] = {
> + TCLK1_MARK,
> +};
According to the R-Car V3U Pin Multiplex Table, there are two sets.
The above definition corresponds to set A.
Set B is available on pin GP1_23.
> +
> +static const unsigned int tmu_tclk2_pins[] = {
> + /* TCLK2 */
> + RCAR_GP_PIN(2, 24),
> +};
> +static const unsigned int tmu_tclk2_mux[] = {
> + TCLK2_MARK,
> +};
According to the R-Car V3U Pin Multiplex Table, there are two sets.
The above definition corresponds to set A.
Set B is available on pin GP2_10.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 11/11] pinctrl: renesas: r8a779a0: Add TPU pins, groups and functions
2020-11-26 17:21 [PATCH 00/11] pinctrl: renesas: R8A779A0 (V3U) device support Ulrich Hecht
` (9 preceding siblings ...)
2020-11-26 17:21 ` [PATCH 10/11] pinctrl: renesas: r8a779a0: Add TMU pins, groups " Ulrich Hecht
@ 2020-11-26 17:21 ` Ulrich Hecht
2020-11-30 13:59 ` Geert Uytterhoeven
2020-11-27 10:33 ` [PATCH 00/11] pinctrl: renesas: R8A779A0 (V3U) device support Geert Uytterhoeven
11 siblings, 1 reply; 26+ messages in thread
From: Ulrich Hecht @ 2020-11-26 17:21 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: wsa, geert, hoai.luu.ub, Ulrich Hecht
Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs
on the R-Car R8A779A0 (V3U) SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
---
drivers/pinctrl/renesas/pfc-r8a779a0.c | 44 ++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c
index 4aa725b3fbca..ec5d9708a5e9 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
@@ -2535,6 +2535,36 @@ static const unsigned int tmu_tclk4_mux[] = {
TCLK4_MARK,
};
+/* - TPU ------------------------------------------------------------------- */
+static const unsigned int tpu_to0_pins[] = {
+ /* TPU0TO0 */
+ RCAR_GP_PIN(2, 21),
+};
+static const unsigned int tpu_to0_mux[] = {
+ TPU0TO0_MARK,
+};
+static const unsigned int tpu_to1_pins[] = {
+ /* TPU0TO1 */
+ RCAR_GP_PIN(2, 22),
+};
+static const unsigned int tpu_to1_mux[] = {
+ TPU0TO1_MARK,
+};
+static const unsigned int tpu_to2_pins[] = {
+ /* TPU0TO2 */
+ RCAR_GP_PIN(3, 5),
+};
+static const unsigned int tpu_to2_mux[] = {
+ TPU0TO2_MARK,
+};
+static const unsigned int tpu_to3_pins[] = {
+ /* TPU0TO3 */
+ RCAR_GP_PIN(3, 6),
+};
+static const unsigned int tpu_to3_mux[] = {
+ TPU0TO3_MARK,
+};
+
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(avb0_link),
SH_PFC_PIN_GROUP(avb0_magic),
@@ -2704,6 +2734,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(tmu_tclk2),
SH_PFC_PIN_GROUP(tmu_tclk3),
SH_PFC_PIN_GROUP(tmu_tclk4),
+
+ SH_PFC_PIN_GROUP(tpu_to0),
+ SH_PFC_PIN_GROUP(tpu_to1),
+ SH_PFC_PIN_GROUP(tpu_to2),
+ SH_PFC_PIN_GROUP(tpu_to3),
};
static const char * const avb0_groups[] = {
@@ -2997,6 +3032,13 @@ static const char * const tmu_groups[] = {
"tmu_tclk4",
};
+static const char * const tpu_groups[] = {
+ "tpu_to0",
+ "tpu_to1",
+ "tpu_to2",
+ "tpu_to3",
+};
+
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(avb0),
SH_PFC_FUNCTION(avb1),
@@ -3055,6 +3097,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(scif_clk),
SH_PFC_FUNCTION(tmu),
+
+ SH_PFC_FUNCTION(tpu),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
--
2.20.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 11/11] pinctrl: renesas: r8a779a0: Add TPU pins, groups and functions
2020-11-26 17:21 ` [PATCH 11/11] pinctrl: renesas: r8a779a0: Add TPU " Ulrich Hecht
@ 2020-11-30 13:59 ` Geert Uytterhoeven
0 siblings, 0 replies; 26+ messages in thread
From: Geert Uytterhoeven @ 2020-11-30 13:59 UTC (permalink / raw)
To: Ulrich Hecht; +Cc: Linux-Renesas, Wolfram Sang, hoai.luu.ub
On Thu, Nov 26, 2020 at 6:22 PM Ulrich Hecht <uli+renesas@fpond.eu> wrote:
> Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs
> on the R-Car R8A779A0 (V3U) SoC.
>
> Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 00/11] pinctrl: renesas: R8A779A0 (V3U) device support
2020-11-26 17:21 [PATCH 00/11] pinctrl: renesas: R8A779A0 (V3U) device support Ulrich Hecht
` (10 preceding siblings ...)
2020-11-26 17:21 ` [PATCH 11/11] pinctrl: renesas: r8a779a0: Add TPU " Ulrich Hecht
@ 2020-11-27 10:33 ` Geert Uytterhoeven
2020-11-30 8:24 ` Ulrich Hecht
11 siblings, 1 reply; 26+ messages in thread
From: Geert Uytterhoeven @ 2020-11-27 10:33 UTC (permalink / raw)
To: Ulrich Hecht; +Cc: Linux-Renesas, Wolfram Sang, hoai.luu.ub
Hi Uli,
On Thu, Nov 26, 2020 at 6:22 PM Ulrich Hecht <uli+renesas@fpond.eu> wrote:
> This series adds V3U pin control support for EtherAVB, CANFD, DU, HSCIF,
> INTC-EX, MMC, MSIOF, PWM, QSPI, TMU and TPU.
>
> It has been ported from the BSP and has been compile-tested only. It
> depends on the "pinctrl: renesas: basic R8A779A0 (V3U) support" series
> posted earlier.
Thanks for your series!
> Ulrich Hecht (11):
> pinctrl: renesas: r8a779a0: Add EtherAVB pins, groups and functions
This patch depends on i2c support, which was not included in your series?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [PATCH 00/11] pinctrl: renesas: R8A779A0 (V3U) device support
2020-11-27 10:33 ` [PATCH 00/11] pinctrl: renesas: R8A779A0 (V3U) device support Geert Uytterhoeven
@ 2020-11-30 8:24 ` Ulrich Hecht
2020-11-30 9:01 ` Geert Uytterhoeven
0 siblings, 1 reply; 26+ messages in thread
From: Ulrich Hecht @ 2020-11-30 8:24 UTC (permalink / raw)
To: Geert Uytterhoeven, Ulrich Hecht; +Cc: Linux-Renesas, Wolfram Sang, hoai.luu.ub
> On 11/27/2020 11:33 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
>
> Hi Uli,
>
> On Thu, Nov 26, 2020 at 6:22 PM Ulrich Hecht <uli+renesas@fpond.eu> wrote:
> > This series adds V3U pin control support for EtherAVB, CANFD, DU, HSCIF,
> > INTC-EX, MMC, MSIOF, PWM, QSPI, TMU and TPU.
> >
> > It has been ported from the BSP and has been compile-tested only. It
> > depends on the "pinctrl: renesas: basic R8A779A0 (V3U) support" series
> > posted earlier.
>
> Thanks for your series!
>
> > Ulrich Hecht (11):
> > pinctrl: renesas: r8a779a0: Add EtherAVB pins, groups and functions
>
> This patch depends on i2c support, which was not included in your series?
Whoops, screwed up the format-patch there...
I'll post the I2C patch separately for review and include it in v2 of this series.
CU
Uli
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 00/11] pinctrl: renesas: R8A779A0 (V3U) device support
2020-11-30 8:24 ` Ulrich Hecht
@ 2020-11-30 9:01 ` Geert Uytterhoeven
0 siblings, 0 replies; 26+ messages in thread
From: Geert Uytterhoeven @ 2020-11-30 9:01 UTC (permalink / raw)
To: Ulrich Hecht; +Cc: Ulrich Hecht, Linux-Renesas, Wolfram Sang, hoai.luu.ub
Hi Uli,
On Mon, Nov 30, 2020 at 9:28 AM Ulrich Hecht <uli@fpond.eu> wrote:
> > On 11/27/2020 11:33 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Thu, Nov 26, 2020 at 6:22 PM Ulrich Hecht <uli+renesas@fpond.eu> wrote:
> > > This series adds V3U pin control support for EtherAVB, CANFD, DU, HSCIF,
> > > INTC-EX, MMC, MSIOF, PWM, QSPI, TMU and TPU.
> > >
> > > It has been ported from the BSP and has been compile-tested only. It
> > > depends on the "pinctrl: renesas: basic R8A779A0 (V3U) support" series
> > > posted earlier.
> >
> > Thanks for your series!
> >
> > > Ulrich Hecht (11):
> > > pinctrl: renesas: r8a779a0: Add EtherAVB pins, groups and functions
> >
> > This patch depends on i2c support, which was not included in your series?
>
> Whoops, screwed up the format-patch there...
> I'll post the I2C patch separately for review and include it in v2 of this series.
Thank you! No need to send v2 yet (still reviewing).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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