[Intel-gfx] [PATCH 00/22] Introduce Alderlake-S

[Intel-gfx] [PATCH 00/22] Introduce Alderlake-S

[Aditya Swarup]

Rev 3 with all the comments addressed from Rev 2:
https://patchwork.freedesktop.org/series/82917/

Aditya Swarup (9):
  drm/i915/tgl: Fix REVID macros for TGL to fetch correct stepping
  drm/i915/tgl: Add bound checks and simplify TGL REVID macros
  drm/i915/adl_s: Configure DPLL for ADL-S
  drm/i915/adl_s: Configure Port clock registers for ADL-S
  drm/i915/adl_s: Initialize display for ADL-S
  drm/i915/adl_s: Add adl-s ddc pin mapping
  drm/i915/adl_s: Add vbt port and aux channel settings for adls
  drm/i915/adl_s: Add display WAs for ADL-S
  drm/i915/adl_s: Add GT and CTX WAs for ADL-S

Anusha Srivatsa (4):
  drm/i915/adl_s: Add PCH support
  drm/i915/adl_s: Add Interrupt Support
  drm/i915/adl_s: Add PHYs for Alderlake S
  drm/i915/adl_s: Load DMC

Caz Yokoyama (3):
  drm/i915/adl_s: Add ADL-S platform info and PCI ids
  x86/gpu: add ADL_S stolen memory support
  drm/i915/adl_s: MCHBAR memory info registers are moved

José Roberto de Souza (1):
  drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION

Lucas De Marchi (1):
  drm/i915/adl_s: Add power wells

Matt Roper (3):
  drm/i915/adl_s: Update combo PHY master/slave relationships
  drm/i915/adl_s: Update PHY_MISC programming
  drm/i915/adl_s: Re-use TGL GuC/HuC firmware

Tejas Upadhyay (1):
  drm/i915/adl_s: Update memory bandwidth parameters

 arch/x86/kernel/early-quirks.c                |   1 +
 drivers/gpu/drm/i915/display/intel_bios.c     |  70 +++++++++--
 drivers/gpu/drm/i915/display/intel_bw.c       |   8 ++
 .../gpu/drm/i915/display/intel_combo_phy.c    |  23 +++-
 drivers/gpu/drm/i915/display/intel_csr.c      |  10 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  64 ++++++----
 drivers/gpu/drm/i915/display/intel_display.c  |  36 +++++-
 .../drm/i915/display/intel_display_power.c    |  11 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  38 +++++-
 drivers/gpu/drm/i915/display/intel_hdmi.c     |  20 ++-
 drivers/gpu/drm/i915/display/intel_psr.c      |   4 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |   8 +-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |   4 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 119 ++++++++++++------
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c      |   4 +-
 drivers/gpu/drm/i915/i915_drv.h               |  72 ++++++++---
 drivers/gpu/drm/i915/i915_irq.c               |   5 +-
 drivers/gpu/drm/i915/i915_pci.c               |  13 ++
 drivers/gpu/drm/i915/i915_reg.h               |  54 +++++++-
 drivers/gpu/drm/i915/intel_device_info.c      |   9 +-
 drivers/gpu/drm/i915/intel_device_info.h      |   1 +
 drivers/gpu/drm/i915/intel_dram.c             |  23 +++-
 drivers/gpu/drm/i915/intel_pch.c              |   8 +-
 drivers/gpu/drm/i915/intel_pch.h              |   3 +
 drivers/gpu/drm/i915/intel_pm.c               |   2 +-
 include/drm/i915_pciids.h                     |  13 ++
 26 files changed, 489 insertions(+), 134 deletions(-)

-- 
2.27.0

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[Intel-gfx] [PATCH 01/22] drm/i915/tgl: Fix REVID macros for TGL to fetch correct stepping

[Aditya Swarup]

Fix TGL REVID macros to fetch correct display/gt stepping based
on SOC rev id from INTEL_REVID() macro. Previously, we were just
returning the first element of the revid array instead of using
the correct index based on SOC rev id.

Fixes: ("drm/i915/tgl: Fix stepping WA matching")
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fc1090c6889c..2e2149c9a2f4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1580,9 +1580,9 @@ static inline const struct i915_rev_steppings *
 tgl_revids_get(struct drm_i915_private *dev_priv)
 {
 	if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv))
-		return tgl_uy_revids;
+		return &tgl_uy_revids[INTEL_REVID(dev_priv)];
 	else
-		return tgl_revids;
+		return &tgl_revids[INTEL_REVID(dev_priv)];
 }
 
 #define IS_TGL_DISP_REVID(p, since, until) \
@@ -1592,14 +1592,14 @@ tgl_revids_get(struct drm_i915_private *dev_priv)
 
 #define IS_TGL_UY_GT_REVID(p, since, until) \
 	((IS_TGL_U(p) || IS_TGL_Y(p)) && \
-	 tgl_uy_revids->gt_stepping >= (since) && \
-	 tgl_uy_revids->gt_stepping <= (until))
+	 tgl_uy_revids[INTEL_REVID(p)].gt_stepping >= (since) && \
+	 tgl_uy_revids[INTEL_REVID(p)].gt_stepping <= (until))
 
 #define IS_TGL_GT_REVID(p, since, until) \
 	(IS_TIGERLAKE(p) && \
 	 !(IS_TGL_U(p) || IS_TGL_Y(p)) && \
-	 tgl_revids->gt_stepping >= (since) && \
-	 tgl_revids->gt_stepping <= (until))
+	 tgl_revids[INTEL_REVID(p)].gt_stepping >= (since) && \
+	 tgl_revids[INTEL_REVID(p)].gt_stepping <= (until))
 
 #define RKL_REVID_A0		0x0
 #define RKL_REVID_B0		0x1
-- 
2.27.0

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[Intel-gfx] [PATCH 02/22] drm/i915/tgl: Add bound checks and simplify TGL REVID macros

[Aditya Swarup]

Add bound checks for TGL REV ID array. Since, there might
be a possibility of using older kernels on latest platform
revisions, resulting in out of bounds access for rev ID array.
In this scenario, use the latest rev ID available and apply
those WAs.

Also, simplify GT macros for TGL rev ID to reuse tgl_revids_get().

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 34 +++++++++++++++++++++++----------
 1 file changed, 24 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2e2149c9a2f4..37c2df19ce52 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1573,16 +1573,30 @@ enum {
 	TGL_REVID_D0,
 };
 
-extern const struct i915_rev_steppings tgl_uy_revids[];
-extern const struct i915_rev_steppings tgl_revids[];
+#define TGL_UY_REVIDS_SIZE	4
+#define TGL_REVIDS_SIZE		2
+
+extern const struct i915_rev_steppings tgl_uy_revids[TGL_UY_REVIDS_SIZE];
+extern const struct i915_rev_steppings tgl_revids[TGL_REVIDS_SIZE];
 
 static inline const struct i915_rev_steppings *
 tgl_revids_get(struct drm_i915_private *dev_priv)
 {
-	if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv))
-		return &tgl_uy_revids[INTEL_REVID(dev_priv)];
-	else
-		return &tgl_revids[INTEL_REVID(dev_priv)];
+	u8 revid = INTEL_REVID(dev_priv);
+	u8 size;
+	const struct i915_rev_steppings *tgl_revid_tbl;
+
+	if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
+		tgl_revid_tbl = tgl_uy_revids;
+		size = ARRAY_SIZE(tgl_uy_revids);
+	} else {
+		tgl_revid_tbl = tgl_revids;
+		size = ARRAY_SIZE(tgl_revids);
+	}
+
+	revid = min_t(u8, revid, size - 1);
+
+	return &tgl_revid_tbl[revid];
 }
 
 #define IS_TGL_DISP_REVID(p, since, until) \
@@ -1592,14 +1606,14 @@ tgl_revids_get(struct drm_i915_private *dev_priv)
 
 #define IS_TGL_UY_GT_REVID(p, since, until) \
 	((IS_TGL_U(p) || IS_TGL_Y(p)) && \
-	 tgl_uy_revids[INTEL_REVID(p)].gt_stepping >= (since) && \
-	 tgl_uy_revids[INTEL_REVID(p)].gt_stepping <= (until))
+	 tgl_revids_get(p)->gt_stepping >= (since) && \
+	 tgl_revids_get(p)->gt_stepping <= (until))
 
 #define IS_TGL_GT_REVID(p, since, until) \
 	(IS_TIGERLAKE(p) && \
 	 !(IS_TGL_U(p) || IS_TGL_Y(p)) && \
-	 tgl_revids[INTEL_REVID(p)].gt_stepping >= (since) && \
-	 tgl_revids[INTEL_REVID(p)].gt_stepping <= (until))
+	 tgl_revids_get(p)->gt_stepping >= (since) && \
+	 tgl_revids_get(p)->gt_stepping <= (until))
 
 #define RKL_REVID_A0		0x0
 #define RKL_REVID_B0		0x1
-- 
2.27.0

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[Intel-gfx] [PATCH 03/22] drm/i915/adl_s: Add ADL-S platform info and PCI ids

[Aditya Swarup]

From: Caz Yokoyama <caz.yokoyama@intel.com>

- Add the initial platform information for Alderlake-S.
- Specify ppgtt_size value
- Add dma_mask_size
- Add ADLS REVIDs
- HW tracking(Selective Update Tracking Enable) has been
  removed from ADLS. Disable PSR2 till we enable software/
  manual tracking.

v2:
- Add support for different ADLS SOC steppings to select
  correct GT/DISP stepping based on Bspec 53655 based on
  feedback from Matt Roper.(aswarup)

v3:
- Make display/gt steppings info generic for reuse with TGL and ADLS.
- Modify the macros to reuse tgl_revids_get()
- Add HTI support to adls device info.(mdroper)

Bspec: 53597
Bspec: 53648
Bspec: 53655
Bspec: 48028
Bspec: 53650
BSpec: 50422

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 .../drm/i915/display/intel_display_power.c    |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |  4 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 28 +++++++-----
 drivers/gpu/drm/i915/i915_drv.h               | 45 ++++++++++++++-----
 drivers/gpu/drm/i915/i915_pci.c               | 13 ++++++
 drivers/gpu/drm/i915/intel_device_info.c      |  1 +
 drivers/gpu/drm/i915/intel_device_info.h      |  1 +
 drivers/gpu/drm/i915/intel_pm.c               |  2 +-
 include/drm/i915_pciids.h                     | 13 ++++++
 10 files changed, 86 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index fe2d90bba536..06c036e2092c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5283,7 +5283,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
 	int config, i;
 
 	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
-	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
+	    IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_B0))
 		/* Wa_1409767108:tgl,dg1 */
 		table = wa_1409767108_buddy_page_masks;
 	else
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index d9a395c486d3..1771f5000a45 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -550,7 +550,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 
 	if (dev_priv->psr.psr2_sel_fetch_enabled) {
 		/* WA 1408330847 */
-		if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
+		if (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_A0) ||
 		    IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
 			intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
 				     DIS_RAM_BYPASS_PSR2_MAN_TRACK,
@@ -1102,7 +1102,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 
 	/* WA 1408330847 */
 	if (dev_priv->psr.psr2_sel_fetch_enabled &&
-	    (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
+	    (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_A0) ||
 	     IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
 		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
 			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index b7e208816074..e19d4f873b94 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -3032,7 +3032,7 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
 {
 	/* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
 	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
-	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
+	    IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_C0))
 		return false;
 
 	return plane_id < PLANE_SPRITE4;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 7c6b21ced56f..3db57b577a79 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -71,16 +71,24 @@ const struct i915_rev_steppings kbl_revids[] = {
 };
 
 const struct i915_rev_steppings tgl_uy_revids[] = {
-	[0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0 },
-	[1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0 },
-	[2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0 },
-	[3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0 },
+	[0] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_A0 },
+	[1] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_C0 },
+	[2] = { .gt_stepping = REVID_B1, .disp_stepping = REVID_C0 },
+	[3] = { .gt_stepping = REVID_C0, .disp_stepping = REVID_D0 },
 };
 
 /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */
 const struct i915_rev_steppings tgl_revids[] = {
-	[0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_B0 },
-	[1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_D0 },
+	[0] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_B0 },
+	[1] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_D0 },
+};
+
+const struct i915_rev_steppings adls_revids[] = {
+	[ADLS_REVID_A0] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_A0 },
+	[ADLS_REVID_A2] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_A2 },
+	[ADLS_REVID_B0] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_B0 },
+	[ADLS_REVID_G0] = { .gt_stepping = REVID_C0, .disp_stepping = REVID_B0 },
+	[ADLS_REVID_C0] = { .gt_stepping = REVID_D0, .disp_stepping = REVID_C0 },
 };
 
 static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
@@ -1250,13 +1258,13 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 	gen12_gt_workarounds_init(i915, wal);
 
 	/* Wa_1409420604:tgl */
-	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
+	if (IS_TGL_UY_GT_REVID(i915, REVID_A0, REVID_A0))
 		wa_write_or(wal,
 			    SUBSLICE_UNIT_LEVEL_CLKGATE2,
 			    CPSSUNIT_CLKGATE_DIS);
 
 	/* Wa_1607087056:tgl also know as BUG:1409180338 */
-	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
+	if (IS_TGL_UY_GT_REVID(i915, REVID_A0, REVID_A0))
 		wa_write_or(wal,
 			    SLICE_UNIT_LEVEL_CLKGATE,
 			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
@@ -1734,7 +1742,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 	struct drm_i915_private *i915 = engine->i915;
 
 	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
-	    IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
+	    IS_TGL_UY_GT_REVID(i915, REVID_A0, REVID_A0)) {
 		/*
 		 * Wa_1607138336:tgl[a0],dg1[a0]
 		 * Wa_1607063988:tgl[a0],dg1[a0]
@@ -1744,7 +1752,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 			    GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
 	}
 
-	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
+	if (IS_TGL_UY_GT_REVID(i915, REVID_A0, REVID_A0)) {
 		/*
 		 * Wa_1606679103:tgl
 		 * (see also Wa_1606682166:icl)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 37c2df19ce52..91bd262dd871 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1424,6 +1424,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_TIGERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
 #define IS_ROCKETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
 #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
+#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
 				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
 #define IS_BDW_ULT(dev_priv) \
@@ -1566,37 +1567,43 @@ extern const struct i915_rev_steppings kbl_revids[];
 	(IS_JSL_EHL(p) && IS_REVID(p, since, until))
 
 enum {
-	TGL_REVID_A0,
-	TGL_REVID_B0,
-	TGL_REVID_B1,
-	TGL_REVID_C0,
-	TGL_REVID_D0,
+	REVID_A0,
+	REVID_A2,
+	REVID_B0,
+	REVID_B1,
+	REVID_C0,
+	REVID_D0,
 };
 
 #define TGL_UY_REVIDS_SIZE	4
 #define TGL_REVIDS_SIZE		2
+#define ADLS_REVIDS_SIZE	13
 
 extern const struct i915_rev_steppings tgl_uy_revids[TGL_UY_REVIDS_SIZE];
 extern const struct i915_rev_steppings tgl_revids[TGL_REVIDS_SIZE];
+extern const struct i915_rev_steppings adls_revids[ADLS_REVIDS_SIZE];
 
 static inline const struct i915_rev_steppings *
 tgl_revids_get(struct drm_i915_private *dev_priv)
 {
 	u8 revid = INTEL_REVID(dev_priv);
 	u8 size;
-	const struct i915_rev_steppings *tgl_revid_tbl;
+	const struct i915_rev_steppings *revid_tbl;
 
-	if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
-		tgl_revid_tbl = tgl_uy_revids;
+	if (IS_ALDERLAKE_S(dev_priv)) {
+		revid_tbl = adls_revids;
+		size = ARRAY_SIZE(adls_revids);
+	} else if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
+		revid_tbl = tgl_uy_revids;
 		size = ARRAY_SIZE(tgl_uy_revids);
 	} else {
-		tgl_revid_tbl = tgl_revids;
+		revid_tbl = tgl_revids;
 		size = ARRAY_SIZE(tgl_revids);
 	}
 
 	revid = min_t(u8, revid, size - 1);
 
-	return &tgl_revid_tbl[revid];
+	return &revid_tbl[revid];
 }
 
 #define IS_TGL_DISP_REVID(p, since, until) \
@@ -1628,6 +1635,24 @@ tgl_revids_get(struct drm_i915_private *dev_priv)
 #define IS_DG1_REVID(p, since, until) \
 	(IS_DG1(p) && IS_REVID(p, since, until))
 
+#define ADLS_REVID_A0		0x0
+#define ADLS_REVID_A2		0x1
+#define ADLS_REVID_B0		0x4
+#define ADLS_REVID_G0		0x8
+#define ADLS_REVID_C0		0xC /*Same as H0 ADLS SOC stepping*/
+
+extern const struct i915_rev_steppings adls_revids[];
+
+#define IS_ADLS_DISP_REVID(p, since, until) \
+	(IS_ALDERLAKE_S(p) && \
+	 tgl_revids_get(p)->disp_stepping >= (since) && \
+	 tgl_revids_get(p)->disp_stepping <= (until))
+
+#define IS_ADLS_GT_REVID(p, since, until) \
+	(IS_ALDERLAKE_S(p) && \
+	 tgl_revids_get(p)->gt_stepping >= (since) && \
+	 tgl_revids_get(p)->gt_stepping <= (until))
+
 #define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
 #define IS_GEN9_LP(dev_priv)	(IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
 #define IS_GEN9_BC(dev_priv)	(IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 11fe790b1969..26e4bf8bb4ef 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -925,6 +925,18 @@ static const struct intel_device_info dg1_info __maybe_unused = {
 	.ppgtt_size = 47,
 };
 
+static const struct intel_device_info adl_s_info = {
+	GEN12_FEATURES,
+	PLATFORM(INTEL_ALDERLAKE_S),
+	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+	.require_force_probe = 1,
+	.display.has_hti = 1,
+	.display.has_psr_hw_tracking = 0,
+	.platform_engine_mask =
+		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
+	.dma_mask_size = 46,
+};
+
 #undef GEN
 #undef PLATFORM
 
@@ -1001,6 +1013,7 @@ static const struct pci_device_id pciidlist[] = {
 	INTEL_JSL_IDS(&jsl_info),
 	INTEL_TGL_12_IDS(&tgl_info),
 	INTEL_RKL_IDS(&rkl_info),
+	INTEL_ADLS_IDS(&adl_s_info),
 	{0, 0, 0}
 };
 MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index ef767f04c37c..ce8c69c17b8e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -66,6 +66,7 @@ static const char * const platform_names[] = {
 	PLATFORM_NAME(TIGERLAKE),
 	PLATFORM_NAME(ROCKETLAKE),
 	PLATFORM_NAME(DG1),
+	PLATFORM_NAME(ALDERLAKE_S),
 };
 #undef PLATFORM_NAME
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index d92fa041c700..360f3f1835f5 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -84,6 +84,7 @@ enum intel_platform {
 	INTEL_TIGERLAKE,
 	INTEL_ROCKETLAKE,
 	INTEL_DG1,
+	INTEL_ALDERLAKE_S,
 	INTEL_MAX_PLATFORMS
 };
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bbc73df7f753..d92616581819 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7110,7 +7110,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
 		   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
 
 	/* Wa_1409825376:tgl (pre-prod)*/
-	if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
+	if (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_B1))
 		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
 			   TGL_VRH_GATING_DIS);
 
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 931e46191047..ae53ff8462ae 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -634,4 +634,17 @@
 	INTEL_VGA_DEVICE(0x4907, info), \
 	INTEL_VGA_DEVICE(0x4908, info)
 
+/* ADL-S */
+#define INTEL_ADLS_IDS(info) \
+	INTEL_VGA_DEVICE(0x4680, info), \
+	INTEL_VGA_DEVICE(0x4681, info), \
+	INTEL_VGA_DEVICE(0x4682, info), \
+	INTEL_VGA_DEVICE(0x4683, info), \
+	INTEL_VGA_DEVICE(0x4690, info), \
+	INTEL_VGA_DEVICE(0x4691, info), \
+	INTEL_VGA_DEVICE(0x4692, info), \
+	INTEL_VGA_DEVICE(0x4693, info), \
+	INTEL_VGA_DEVICE(0x4698, info), \
+	INTEL_VGA_DEVICE(0x4699, info)
+
 #endif /* _I915_PCIIDS_H */
-- 
2.27.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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Re: [Intel-gfx] [PATCH 03/22] drm/i915/adl_s: Add ADL-S platform info and PCI ids

[Souza, Jose]

This patch should at least be splitted into two, all the stepping changes here should go to a new patch.

On Fri, 2020-12-04 at 17:08 -0800, Aditya Swarup wrote:
> From: Caz Yokoyama <caz.yokoyama@intel.com>
> 
> - Add the initial platform information for Alderlake-S.
> - Specify ppgtt_size value
> - Add dma_mask_size
> - Add ADLS REVIDs
> - HW tracking(Selective Update Tracking Enable) has been
>   removed from ADLS. Disable PSR2 till we enable software/
>   manual tracking.
> 
> v2:
> - Add support for different ADLS SOC steppings to select
>   correct GT/DISP stepping based on Bspec 53655 based on
>   feedback from Matt Roper.(aswarup)
> 
> v3:
> - Make display/gt steppings info generic for reuse with TGL and ADLS.
> - Modify the macros to reuse tgl_revids_get()
> - Add HTI support to adls device info.(mdroper)
> 
> Bspec: 53597
> Bspec: 53648
> Bspec: 53655
> Bspec: 48028
> Bspec: 53650
> BSpec: 50422
> 
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> ---
>  .../drm/i915/display/intel_display_power.c    |  2 +-
>  drivers/gpu/drm/i915/display/intel_psr.c      |  4 +-
>  drivers/gpu/drm/i915/display/intel_sprite.c   |  2 +-
>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 28 +++++++-----
>  drivers/gpu/drm/i915/i915_drv.h               | 45 ++++++++++++++-----
>  drivers/gpu/drm/i915/i915_pci.c               | 13 ++++++
>  drivers/gpu/drm/i915/intel_device_info.c      |  1 +
>  drivers/gpu/drm/i915/intel_device_info.h      |  1 +
>  drivers/gpu/drm/i915/intel_pm.c               |  2 +-
>  include/drm/i915_pciids.h                     | 13 ++++++
>  10 files changed, 86 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index fe2d90bba536..06c036e2092c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5283,7 +5283,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
>  	int config, i;
>  
> 
>  	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
> -	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
> +	    IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_B0))
>  		/* Wa_1409767108:tgl,dg1 */
>  		table = wa_1409767108_buddy_page_masks;
>  	else
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index d9a395c486d3..1771f5000a45 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -550,7 +550,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  
> 
>  	if (dev_priv->psr.psr2_sel_fetch_enabled) {
>  		/* WA 1408330847 */
> -		if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
> +		if (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_A0) ||
>  		    IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
>  			intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>  				     DIS_RAM_BYPASS_PSR2_MAN_TRACK,
> @@ -1102,7 +1102,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>  
> 
>  	/* WA 1408330847 */
>  	if (dev_priv->psr.psr2_sel_fetch_enabled &&
> -	    (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
> +	    (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_A0) ||
>  	     IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
>  		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>  			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index b7e208816074..e19d4f873b94 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -3032,7 +3032,7 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
>  {
>  	/* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
>  	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
> -	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
> +	    IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_C0))
>  		return false;
>  
> 
>  	return plane_id < PLANE_SPRITE4;
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 7c6b21ced56f..3db57b577a79 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -71,16 +71,24 @@ const struct i915_rev_steppings kbl_revids[] = {
>  };
>  
> 
>  const struct i915_rev_steppings tgl_uy_revids[] = {
> -	[0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0 },
> -	[1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0 },
> -	[2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0 },
> -	[3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0 },
> +	[0] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_A0 },
> +	[1] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_C0 },
> +	[2] = { .gt_stepping = REVID_B1, .disp_stepping = REVID_C0 },
> +	[3] = { .gt_stepping = REVID_C0, .disp_stepping = REVID_D0 },
>  };
>  
> 
>  /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */
>  const struct i915_rev_steppings tgl_revids[] = {
> -	[0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_B0 },
> -	[1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_D0 },
> +	[0] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_B0 },
> +	[1] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_D0 },
> +};
> +
> +const struct i915_rev_steppings adls_revids[] = {
> +	[ADLS_REVID_A0] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_A0 },
> +	[ADLS_REVID_A2] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_A2 },
> +	[ADLS_REVID_B0] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_B0 },
> +	[ADLS_REVID_G0] = { .gt_stepping = REVID_C0, .disp_stepping = REVID_B0 },
> +	[ADLS_REVID_C0] = { .gt_stepping = REVID_D0, .disp_stepping = REVID_C0 },
>  };
>  
> 
>  static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
> @@ -1250,13 +1258,13 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>  	gen12_gt_workarounds_init(i915, wal);
>  
> 
>  	/* Wa_1409420604:tgl */
> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
> +	if (IS_TGL_UY_GT_REVID(i915, REVID_A0, REVID_A0))
>  		wa_write_or(wal,
>  			    SUBSLICE_UNIT_LEVEL_CLKGATE2,
>  			    CPSSUNIT_CLKGATE_DIS);
>  
> 
>  	/* Wa_1607087056:tgl also know as BUG:1409180338 */
> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
> +	if (IS_TGL_UY_GT_REVID(i915, REVID_A0, REVID_A0))
>  		wa_write_or(wal,
>  			    SLICE_UNIT_LEVEL_CLKGATE,
>  			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> @@ -1734,7 +1742,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  	struct drm_i915_private *i915 = engine->i915;
>  
> 
>  	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
> -	    IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
> +	    IS_TGL_UY_GT_REVID(i915, REVID_A0, REVID_A0)) {
>  		/*
>  		 * Wa_1607138336:tgl[a0],dg1[a0]
>  		 * Wa_1607063988:tgl[a0],dg1[a0]
> @@ -1744,7 +1752,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  			    GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
>  	}
>  
> 
> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
> +	if (IS_TGL_UY_GT_REVID(i915, REVID_A0, REVID_A0)) {
>  		/*
>  		 * Wa_1606679103:tgl
>  		 * (see also Wa_1606682166:icl)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 37c2df19ce52..91bd262dd871 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1424,6 +1424,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define IS_TIGERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
>  #define IS_ROCKETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
>  #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
> +#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
>  #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
>  				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
>  #define IS_BDW_ULT(dev_priv) \
> @@ -1566,37 +1567,43 @@ extern const struct i915_rev_steppings kbl_revids[];
>  	(IS_JSL_EHL(p) && IS_REVID(p, since, until))
>  
> 
>  enum {
> -	TGL_REVID_A0,
> -	TGL_REVID_B0,
> -	TGL_REVID_B1,
> -	TGL_REVID_C0,
> -	TGL_REVID_D0,
> +	REVID_A0,
> +	REVID_A2,
> +	REVID_B0,
> +	REVID_B1,
> +	REVID_C0,
> +	REVID_D0,
>  };
>  
> 
>  #define TGL_UY_REVIDS_SIZE	4
>  #define TGL_REVIDS_SIZE		2
> +#define ADLS_REVIDS_SIZE	13
>  
> 
>  extern const struct i915_rev_steppings tgl_uy_revids[TGL_UY_REVIDS_SIZE];
>  extern const struct i915_rev_steppings tgl_revids[TGL_REVIDS_SIZE];
> +extern const struct i915_rev_steppings adls_revids[ADLS_REVIDS_SIZE];
>  
> 
>  static inline const struct i915_rev_steppings *
>  tgl_revids_get(struct drm_i915_private *dev_priv)
>  {
>  	u8 revid = INTEL_REVID(dev_priv);
>  	u8 size;
> -	const struct i915_rev_steppings *tgl_revid_tbl;
> +	const struct i915_rev_steppings *revid_tbl;
>  
> 
> -	if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
> -		tgl_revid_tbl = tgl_uy_revids;
> +	if (IS_ALDERLAKE_S(dev_priv)) {
> +		revid_tbl = adls_revids;
> +		size = ARRAY_SIZE(adls_revids);
> +	} else if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
> +		revid_tbl = tgl_uy_revids;
>  		size = ARRAY_SIZE(tgl_uy_revids);
>  	} else {
> -		tgl_revid_tbl = tgl_revids;
> +		revid_tbl = tgl_revids;
>  		size = ARRAY_SIZE(tgl_revids);
>  	}
>  
> 
>  	revid = min_t(u8, revid, size - 1);
>  
> 
> -	return &tgl_revid_tbl[revid];
> +	return &revid_tbl[revid];
>  }
>  
> 
>  #define IS_TGL_DISP_REVID(p, since, until) \
> @@ -1628,6 +1635,24 @@ tgl_revids_get(struct drm_i915_private *dev_priv)
>  #define IS_DG1_REVID(p, since, until) \
>  	(IS_DG1(p) && IS_REVID(p, since, until))
>  
> 
> +#define ADLS_REVID_A0		0x0
> +#define ADLS_REVID_A2		0x1
> +#define ADLS_REVID_B0		0x4
> +#define ADLS_REVID_G0		0x8
> +#define ADLS_REVID_C0		0xC /*Same as H0 ADLS SOC stepping*/
> +
> +extern const struct i915_rev_steppings adls_revids[];
> +
> +#define IS_ADLS_DISP_REVID(p, since, until) \
> +	(IS_ALDERLAKE_S(p) && \
> +	 tgl_revids_get(p)->disp_stepping >= (since) && \
> +	 tgl_revids_get(p)->disp_stepping <= (until))
> +
> +#define IS_ADLS_GT_REVID(p, since, until) \
> +	(IS_ALDERLAKE_S(p) && \
> +	 tgl_revids_get(p)->gt_stepping >= (since) && \
> +	 tgl_revids_get(p)->gt_stepping <= (until))
> +
>  #define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
>  #define IS_GEN9_LP(dev_priv)	(IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
>  #define IS_GEN9_BC(dev_priv)	(IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 11fe790b1969..26e4bf8bb4ef 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -925,6 +925,18 @@ static const struct intel_device_info dg1_info __maybe_unused = {
>  	.ppgtt_size = 47,
>  };
>  
> 
> +static const struct intel_device_info adl_s_info = {
> +	GEN12_FEATURES,
> +	PLATFORM(INTEL_ALDERLAKE_S),
> +	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> +	.require_force_probe = 1,
> +	.display.has_hti = 1,
> +	.display.has_psr_hw_tracking = 0,
> +	.platform_engine_mask =
> +		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> +	.dma_mask_size = 46,
> +};
> +
>  #undef GEN
>  #undef PLATFORM
>  
> 
> @@ -1001,6 +1013,7 @@ static const struct pci_device_id pciidlist[] = {
>  	INTEL_JSL_IDS(&jsl_info),
>  	INTEL_TGL_12_IDS(&tgl_info),
>  	INTEL_RKL_IDS(&rkl_info),
> +	INTEL_ADLS_IDS(&adl_s_info),
>  	{0, 0, 0}
>  };
>  MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index ef767f04c37c..ce8c69c17b8e 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -66,6 +66,7 @@ static const char * const platform_names[] = {
>  	PLATFORM_NAME(TIGERLAKE),
>  	PLATFORM_NAME(ROCKETLAKE),
>  	PLATFORM_NAME(DG1),
> +	PLATFORM_NAME(ALDERLAKE_S),
>  };
>  #undef PLATFORM_NAME
>  
> 
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index d92fa041c700..360f3f1835f5 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -84,6 +84,7 @@ enum intel_platform {
>  	INTEL_TIGERLAKE,
>  	INTEL_ROCKETLAKE,
>  	INTEL_DG1,
> +	INTEL_ALDERLAKE_S,
>  	INTEL_MAX_PLATFORMS
>  };
>  
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index bbc73df7f753..d92616581819 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7110,7 +7110,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
>  		   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
>  
> 
>  	/* Wa_1409825376:tgl (pre-prod)*/
> -	if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
> +	if (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_B1))
>  		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
>  			   TGL_VRH_GATING_DIS);
>  
> 
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 931e46191047..ae53ff8462ae 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -634,4 +634,17 @@
>  	INTEL_VGA_DEVICE(0x4907, info), \
>  	INTEL_VGA_DEVICE(0x4908, info)
>  
> 
> +/* ADL-S */
> +#define INTEL_ADLS_IDS(info) \
> +	INTEL_VGA_DEVICE(0x4680, info), \
> +	INTEL_VGA_DEVICE(0x4681, info), \
> +	INTEL_VGA_DEVICE(0x4682, info), \
> +	INTEL_VGA_DEVICE(0x4683, info), \
> +	INTEL_VGA_DEVICE(0x4690, info), \
> +	INTEL_VGA_DEVICE(0x4691, info), \
> +	INTEL_VGA_DEVICE(0x4692, info), \
> +	INTEL_VGA_DEVICE(0x4693, info), \
> +	INTEL_VGA_DEVICE(0x4698, info), \
> +	INTEL_VGA_DEVICE(0x4699, info)
> +
>  #endif /* _I915_PCIIDS_H */

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[Intel-gfx] [PATCH 04/22] x86/gpu: add ADL_S stolen memory support

[Aditya Swarup]

From: Caz Yokoyama <caz.yokoyama@intel.com>

ADL_S re-uses the same stolen memory registers as TGL and ICL.

This patch has a dependency on:
("drm/i915/adl_s: Add ADL-S platform info and PCI ids")

Bspec: 52055
Bspec: 49589
Bspec: 49636

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: x86@kernel.org
Cc: Ingo Molnar <mingo@redhat.com>,
Cc: Thomas Gleixner <tglx@linutronix.de>,
Cc: Borislav Petkov <bp@suse.de>
Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 arch/x86/kernel/early-quirks.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index a4b5af03dcc1..6edd1e2ee8af 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -551,6 +551,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = {
 	INTEL_EHL_IDS(&gen11_early_ops),
 	INTEL_TGL_12_IDS(&gen11_early_ops),
 	INTEL_RKL_IDS(&gen11_early_ops),
+	INTEL_ADLS_IDS(&gen11_early_ops),
 };
 
 struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
-- 
2.27.0

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[Intel-gfx] [PATCH 05/22] drm/i915/adl_s: Add PCH support

[Aditya Swarup]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

Add support for Alderpoint(ADP) PCH used with Alderlake-S.

v2:
- Use drm_dbg_kms and drm_WARN_ON based on Jani's feedback.(aswarup)

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Caz Yokoyama <caz.yokoyama@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/intel_pch.c | 8 +++++++-
 drivers/gpu/drm/i915/intel_pch.h | 3 +++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index f31c0dabd0cc..2a6d70f247e8 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -128,6 +128,10 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 		drm_dbg_kms(&dev_priv->drm, "Found Jasper Lake PCH\n");
 		drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
 		return PCH_JSP;
+	case INTEL_PCH_ADP_DEVICE_ID_TYPE:
+		drm_dbg_kms(&dev_priv->drm, "Found Alder Lake PCH\n");
+		drm_WARN_ON(&dev_priv->drm, !IS_ALDERLAKE_S(dev_priv));
+		return PCH_ADP;
 	default:
 		return PCH_NONE;
 	}
@@ -155,7 +159,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
 	 * make an educated guess as to which PCH is really there.
 	 */
 
-	if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
+	if (IS_ALDERLAKE_S(dev_priv))
+		id = INTEL_PCH_ADP_DEVICE_ID_TYPE;
+	else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
 		id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
 	else if (IS_JSL_EHL(dev_priv))
 		id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h
index 06d2cd50af0b..7318377503b0 100644
--- a/drivers/gpu/drm/i915/intel_pch.h
+++ b/drivers/gpu/drm/i915/intel_pch.h
@@ -26,6 +26,7 @@ enum intel_pch {
 	PCH_JSP,	/* Jasper Lake PCH */
 	PCH_MCC,        /* Mule Creek Canyon PCH */
 	PCH_TGP,	/* Tiger Lake PCH */
+	PCH_ADP,	/* Alder Lake PCH */
 
 	/* Fake PCHs, functionality handled on the same PCI dev */
 	PCH_DG1 = 1024,
@@ -53,12 +54,14 @@ enum intel_pch {
 #define INTEL_PCH_TGP2_DEVICE_ID_TYPE		0x4380
 #define INTEL_PCH_JSP_DEVICE_ID_TYPE		0x4D80
 #define INTEL_PCH_JSP2_DEVICE_ID_TYPE		0x3880
+#define INTEL_PCH_ADP_DEVICE_ID_TYPE		0x7A80
 #define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
 #define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
 
 #define INTEL_PCH_TYPE(dev_priv)		((dev_priv)->pch_type)
 #define INTEL_PCH_ID(dev_priv)			((dev_priv)->pch_id)
+#define HAS_PCH_ADP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
 #define HAS_PCH_DG1(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
 #define HAS_PCH_JSP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_JSP)
 #define HAS_PCH_MCC(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
-- 
2.27.0

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[Intel-gfx] [PATCH 06/22] drm/i915/adl_s: Add Interrupt Support

[Aditya Swarup]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

ADLS follows ICP/TGP like interrupts.

v2: Use "INTEL_PCH_TYPE(dev_priv) >= PCH_ICP" of hpd_icp (Lucas)

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b245109f73e3..d1b4893d6c92 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -191,8 +191,7 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
 
 	if (HAS_PCH_DG1(dev_priv))
 		hpd->pch_hpd = hpd_sde_dg1;
-	else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
-		 HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
+	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
 		hpd->pch_hpd = hpd_icp;
 	else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
 		hpd->pch_hpd = hpd_spt;
-- 
2.27.0

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[Intel-gfx] [PATCH 07/22] drm/i915/adl_s: Add PHYs for Alderlake S

[Aditya Swarup]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

Alderlake-S has 5 combo phys, add reg definitions for
combo phys and update the port to phy helper for ADL-S.

v2:
- Change IS_GEN() >= 12 to IS_TIGERLAKE() in intel_phy_is_tc()
and return false for platforms RKL,DG1 and ADLS.(mdroper)

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 10 ++++++----
 drivers/gpu/drm/i915/i915_reg.h              |  5 ++++-
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9187a20a8aca..2d1c5bfe4032 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7397,6 +7397,8 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
 {
 	if (phy == PHY_NONE)
 		return false;
+	else if (IS_ALDERLAKE_S(dev_priv))
+		return phy <= PHY_E;
 	else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 		return phy <= PHY_D;
 	else if (IS_JSL_EHL(dev_priv))
@@ -7409,9 +7411,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
 
 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
 {
-	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
-		return false;
-	else if (INTEL_GEN(dev_priv) >= 12)
+	if (IS_TIGERLAKE(dev_priv))
 		return phy >= PHY_D && phy <= PHY_I;
 	else if (INTEL_GEN(dev_priv) >= 11 && !IS_JSL_EHL(dev_priv))
 		return phy >= PHY_C && phy <= PHY_F;
@@ -7421,7 +7421,9 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
 
 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
 {
-	if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
+	if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
+		return PHY_B + port - PORT_TC1;
+	else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
 		return PHY_C + port - PORT_TC1;
 	else if (IS_JSL_EHL(i915) && port == PORT_D)
 		return PHY_A;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cdc67f583a9c..60a0d4c35cae 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1874,10 +1874,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define _ICL_COMBOPHY_B			0x6C000
 #define _EHL_COMBOPHY_C			0x160000
 #define _RKL_COMBOPHY_D			0x161000
+#define _ADL_COMBOPHY_E			0x16B000
+
 #define _ICL_COMBOPHY(phy)		_PICK(phy, _ICL_COMBOPHY_A, \
 					      _ICL_COMBOPHY_B, \
 					      _EHL_COMBOPHY_C, \
-					      _RKL_COMBOPHY_D)
+					      _RKL_COMBOPHY_D, \
+					      _ADL_COMBOPHY_E)
 
 /* CNL/ICL Port CL_DW registers */
 #define _ICL_PORT_CL_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
-- 
2.27.0

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Re: [Intel-gfx] [PATCH 07/22] drm/i915/adl_s: Add PHYs for Alderlake S

[Matt Roper]

On Fri, Dec 04, 2020 at 05:08:29PM -0800, Aditya Swarup wrote:
> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
> 
> Alderlake-S has 5 combo phys, add reg definitions for
> combo phys and update the port to phy helper for ADL-S.
> 
> v2:
> - Change IS_GEN() >= 12 to IS_TIGERLAKE() in intel_phy_is_tc()
> and return false for platforms RKL,DG1 and ADLS.(mdroper)
> 
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 10 ++++++----
>  drivers/gpu/drm/i915/i915_reg.h              |  5 ++++-
>  2 files changed, 10 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 9187a20a8aca..2d1c5bfe4032 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7397,6 +7397,8 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
>  {
>  	if (phy == PHY_NONE)
>  		return false;
> +	else if (IS_ALDERLAKE_S(dev_priv))
> +		return phy <= PHY_E;
>  	else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
>  		return phy <= PHY_D;
>  	else if (IS_JSL_EHL(dev_priv))
> @@ -7409,9 +7411,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
>  
>  bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
>  {
> -	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
> -		return false;
> -	else if (INTEL_GEN(dev_priv) >= 12)
> +	if (IS_TIGERLAKE(dev_priv))
>  		return phy >= PHY_D && phy <= PHY_I;
>  	else if (INTEL_GEN(dev_priv) >= 11 && !IS_JSL_EHL(dev_priv))
>  		return phy >= PHY_C && phy <= PHY_F;
> @@ -7421,7 +7421,9 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
>  
>  enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
>  {
> -	if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
> +	if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
> +		return PHY_B + port - PORT_TC1;
> +	else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
>  		return PHY_C + port - PORT_TC1;
>  	else if (IS_JSL_EHL(i915) && port == PORT_D)
>  		return PHY_A;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index cdc67f583a9c..60a0d4c35cae 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1874,10 +1874,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define _ICL_COMBOPHY_B			0x6C000
>  #define _EHL_COMBOPHY_C			0x160000
>  #define _RKL_COMBOPHY_D			0x161000
> +#define _ADL_COMBOPHY_E			0x16B000
> +
>  #define _ICL_COMBOPHY(phy)		_PICK(phy, _ICL_COMBOPHY_A, \
>  					      _ICL_COMBOPHY_B, \
>  					      _EHL_COMBOPHY_C, \
> -					      _RKL_COMBOPHY_D)
> +					      _RKL_COMBOPHY_D, \
> +					      _ADL_COMBOPHY_E)
>  
>  /* CNL/ICL Port CL_DW registers */
>  #define _ICL_PORT_CL_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
> -- 
> 2.27.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 08/22] drm/i915/adl_s: Configure DPLL for ADL-S

[Aditya Swarup]

Add changes for configuring DPLL for ADL-S
- Reusing DG1 DPLL 2 & DPLL 3 for ADL-S
- Extend CNL macro to choose DPLL_ENABLE
  for ADL-S.
- Select CFGCR0 and CFGCR1 for ADL-S plls.

On BSpec: 53720 PLL arrangement dig for adls:
DPLL2 cfgcr is programmed using _ADLS_DPLL3_CFGCR(0/1)
DPLL3 cfgcr is programmed using _ADLS_DPLL4_CFGCR(0/1)

v2 (Lucas): add missing update_ref_clks

Bspec: 50288
Bspec: 50289
Bspec: 49443

v3 : Adding another bit to HDPORT_DPLL_USED_MASK bitfield
for DPLL3_USED.(mdroper)

Bspec: 53707

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 38 +++++++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h               | 21 +++++++++-
 2 files changed, 53 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index f6ad257a260e..529b1d569af2 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3559,7 +3559,13 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
 
 	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
 
-	if (IS_DG1(dev_priv)) {
+	if (IS_ALDERLAKE_S(dev_priv)) {
+		dpll_mask =
+			BIT(DPLL_ID_DG1_DPLL3) |
+			BIT(DPLL_ID_DG1_DPLL2) |
+			BIT(DPLL_ID_ICL_DPLL1) |
+			BIT(DPLL_ID_ICL_DPLL0);
+	} else if (IS_DG1(dev_priv)) {
 		if (port == PORT_D || port == PORT_E) {
 			dpll_mask =
 				BIT(DPLL_ID_DG1_DPLL2) |
@@ -3865,7 +3871,10 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
 	if (!(val & PLL_ENABLE))
 		goto out;
 
-	if (IS_DG1(dev_priv)) {
+	if (IS_ALDERLAKE_S(dev_priv)) {
+		hw_state->cfgcr0 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR0(id));
+		hw_state->cfgcr1 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR1(id));
+	} else if (IS_DG1(dev_priv)) {
 		hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id));
 		hw_state->cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id));
 	} else if (IS_ROCKETLAKE(dev_priv)) {
@@ -3921,7 +3930,10 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
 	const enum intel_dpll_id id = pll->info->id;
 	i915_reg_t cfgcr0_reg, cfgcr1_reg;
 
-	if (IS_DG1(dev_priv)) {
+	if (IS_ALDERLAKE_S(dev_priv)) {
+		cfgcr0_reg = ADLS_DPLL_CFGCR0(id);
+		cfgcr1_reg = ADLS_DPLL_CFGCR1(id);
+	} else if (IS_DG1(dev_priv)) {
 		cfgcr0_reg = DG1_DPLL_CFGCR0(id);
 		cfgcr1_reg = DG1_DPLL_CFGCR1(id);
 	} else if (IS_ROCKETLAKE(dev_priv)) {
@@ -4384,6 +4396,22 @@ static const struct intel_dpll_mgr dg1_pll_mgr = {
 	.dump_hw_state = icl_dump_hw_state,
 };
 
+static const struct dpll_info adls_plls[] = {
+	{ "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
+	{ "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
+	{ "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 },
+	{ "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 },
+	{ },
+};
+
+static const struct intel_dpll_mgr adls_pll_mgr = {
+	.dpll_info = adls_plls,
+	.get_dplls = icl_get_dplls,
+	.put_dplls = icl_put_dplls,
+	.update_ref_clks = icl_update_dpll_ref_clks,
+	.dump_hw_state = icl_dump_hw_state,
+};
+
 /**
  * intel_shared_dpll_init - Initialize shared DPLLs
  * @dev: drm device
@@ -4397,7 +4425,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
 	const struct dpll_info *dpll_info;
 	int i;
 
-	if (IS_DG1(dev_priv))
+	if (IS_ALDERLAKE_S(dev_priv))
+		dpll_mgr = &adls_pll_mgr;
+	else if (IS_DG1(dev_priv))
 		dpll_mgr = &dg1_pll_mgr;
 	else if (IS_ROCKETLAKE(dev_priv))
 		dpll_mgr = &rkl_pll_mgr;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 60a0d4c35cae..999b4eb422db 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2930,7 +2930,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define MBUS_BBOX_CTL_S2		_MMIO(0x45044)
 
 #define HDPORT_STATE			_MMIO(0x45050)
-#define   HDPORT_DPLL_USED_MASK		REG_GENMASK(14, 12)
+#define   HDPORT_DPLL_USED_MASK		REG_GENMASK(15, 12)
 #define   HDPORT_PHY_USED_DP(phy)	REG_BIT(2 * (phy) + 2)
 #define   HDPORT_PHY_USED_HDMI(phy)	REG_BIT(2 * (phy) + 1)
 #define   HDPORT_ENABLED		REG_BIT(0)
@@ -10345,11 +10345,14 @@ enum skl_power_gate {
 /* CNL PLL */
 #define DPLL0_ENABLE		0x46010
 #define DPLL1_ENABLE		0x46014
+#define _ADLS_DPLL2_ENABLE	0x46018
+#define _ADLS_DPLL3_ENABLE	0x46030
 #define  PLL_ENABLE		(1 << 31)
 #define  PLL_LOCK		(1 << 30)
 #define  PLL_POWER_ENABLE	(1 << 27)
 #define  PLL_POWER_STATE	(1 << 26)
-#define CNL_DPLL_ENABLE(pll)	_MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
+#define CNL_DPLL_ENABLE(pll)	_MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
+					   _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE)
 
 #define TBT_PLL_ENABLE		_MMIO(0x46020)
 
@@ -10595,6 +10598,20 @@ enum skl_power_gate {
 						   _DG1_DPLL2_CFGCR1, \
 						   _DG1_DPLL3_CFGCR1)
 
+#define _ADLS_DPLL3_CFGCR0		0x1642C0
+#define _ADLS_DPLL4_CFGCR0		0x164294
+#define ADLS_DPLL_CFGCR0(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
+						   _TGL_DPLL1_CFGCR0, \
+						   _ADLS_DPLL3_CFGCR0, \
+						   _ADLS_DPLL4_CFGCR0)
+
+#define _ADLS_DPLL3_CFGCR1		0x1642C4
+#define _ADLS_DPLL4_CFGCR1		0x164298
+#define ADLS_DPLL_CFGCR1(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
+						   _TGL_DPLL1_CFGCR1, \
+						   _ADLS_DPLL3_CFGCR1, \
+						   _ADLS_DPLL4_CFGCR1)
+
 #define _DKL_PHY1_BASE			0x168000
 #define _DKL_PHY2_BASE			0x169000
 #define _DKL_PHY3_BASE			0x16A000
-- 
2.27.0

_______________________________________________
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Re: [Intel-gfx] [PATCH 08/22] drm/i915/adl_s: Configure DPLL for ADL-S

[Matt Roper]

On Fri, Dec 04, 2020 at 05:08:30PM -0800, Aditya Swarup wrote:
> Add changes for configuring DPLL for ADL-S
> - Reusing DG1 DPLL 2 & DPLL 3 for ADL-S
> - Extend CNL macro to choose DPLL_ENABLE
>   for ADL-S.
> - Select CFGCR0 and CFGCR1 for ADL-S plls.
> 
> On BSpec: 53720 PLL arrangement dig for adls:
> DPLL2 cfgcr is programmed using _ADLS_DPLL3_CFGCR(0/1)
> DPLL3 cfgcr is programmed using _ADLS_DPLL4_CFGCR(0/1)

53720 shows DPLL's 0/1/2/3 in the diagram but the registers are named as
DPLL 0/1/3/4 (no #2).  I don't see anywhere on 53720 that it explicitly
gives the mapping you mention here, but on page 53723 I see a note:

        Due to current BSpec filtering limitations, the DPLL4_CRCFG0/1
        (164294h/164298h) are used to control the DPLL2.

Assuming that's correct, the patch below has the registers for the last
two DPLL's swapped.

...
> +
> +#define _ADLS_DPLL3_CFGCR1		0x1642C4
> +#define _ADLS_DPLL4_CFGCR1		0x164298
> +#define ADLS_DPLL_CFGCR1(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
> +						   _TGL_DPLL1_CFGCR1, \
> +						   _ADLS_DPLL3_CFGCR1, \
> +						   _ADLS_DPLL4_CFGCR1)

I.e., this should be 

        #define ADLS_DPLL_CFGCR1(pll)	_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
                                                        _TGL_DPLL1_CFGCR1, \
                                                        _ADLS_DPLL4_CFGCR1, \
                                                        _ADLS_DPLL3_CFGCR1)

Given the strange spec naming, I think this calls for a comment in the
code as well to clarify that yes, we really do want 4 before 3 and that
there's no 2.


Matt

> +
>  #define _DKL_PHY1_BASE			0x168000
>  #define _DKL_PHY2_BASE			0x169000
>  #define _DKL_PHY3_BASE			0x16A000
> -- 
> 2.27.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 09/22] drm/i915/adl_s: Configure Port clock registers for ADL-S

[Aditya Swarup]

Add changes to configure port clock registers for ADL-S. Combo phy port
clocks are configured by DPCLKA_CFGCR0 and DPCLKA_CFGCR1 registers.

The DDI to internal clock mappings in DPCLKA_CFGCR0 register for ADL-S
translates to
DDI A -> DDIA
DDI B -> USBC1
DDI I -> USBC2

For DPCLKA_CFGCR1
DDI J -> USBC3
DDI K -> USBC4

Bspec: 50287
Bspec: 53812
Bspec: 53723

v2: Replace I915_READ() with intel_de_read().(Jani)

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c     | 64 +++++++++++++-------
 drivers/gpu/drm/i915/display/intel_display.c | 18 +++++-
 drivers/gpu/drm/i915/i915_reg.h              | 23 ++++++-
 3 files changed, 82 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 76e975b4765b..fdf692be2bc3 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3088,25 +3088,30 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-	u32 val;
+	u32 val, mask, sel;
+	i915_reg_t reg;
+
+	if (IS_ALDERLAKE_S(dev_priv)) {
+		reg = ADLS_DPCLKA_CFGCR(phy);
+		mask = ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
+		sel = ((pll->info->id) << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
+	} else if (IS_ROCKETLAKE(dev_priv)) {
+		reg = ICL_DPCLKA_CFGCR0;
+		mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+		sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+	} else {
+		reg = ICL_DPCLKA_CFGCR0;
+		mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+		sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+	}
 
 	mutex_lock(&dev_priv->dpll.lock);
 
-	val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
+	val = intel_de_read(dev_priv, reg);
 	drm_WARN_ON(&dev_priv->drm,
 		    (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
 
 	if (intel_phy_is_combo(dev_priv, phy)) {
-		u32 mask, sel;
-
-		if (IS_ROCKETLAKE(dev_priv)) {
-			mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
-			sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
-		} else {
-			mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
-			sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
-		}
-
 		/*
 		 * Even though this register references DDIs, note that we
 		 * want to pass the PHY rather than the port (DDI).  For
@@ -3119,12 +3124,12 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 		 */
 		val &= ~mask;
 		val |= sel;
-		intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
-		intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
+		intel_de_write(dev_priv, reg, val);
+		intel_de_posting_read(dev_priv, reg);
 	}
 
 	val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
-	intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
+	intel_de_write(dev_priv, reg, val);
 
 	mutex_unlock(&dev_priv->dpll.lock);
 }
@@ -3150,9 +3155,17 @@ static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
 
 	mutex_lock(&dev_priv->dpll.lock);
 
-	val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
+	if (IS_ALDERLAKE_S(dev_priv))
+		val = intel_de_read(dev_priv, ADLS_DPCLKA_CFGCR(phy));
+	else
+		val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
+
 	val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
-	intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
+
+	if (IS_ALDERLAKE_S(dev_priv))
+		intel_de_write(dev_priv, ADLS_DPCLKA_CFGCR(phy), val);
+	else
+		intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
 
 	mutex_unlock(&dev_priv->dpll.lock);
 }
@@ -3192,13 +3205,19 @@ static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
 				      u32 port_mask, bool ddi_clk_needed)
 {
 	enum port port;
+	bool ddi_clk_off;
 	u32 val;
 
-	val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
 	for_each_port_masked(port, port_mask) {
 		enum phy phy = intel_port_to_phy(dev_priv, port);
-		bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
-								   phy);
+
+		if (IS_ALDERLAKE_S(dev_priv))
+			val = intel_de_read(dev_priv, ADLS_DPCLKA_CFGCR(phy));
+		else
+			val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
+
+		ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
+							      phy);
 
 		if (ddi_clk_needed == !ddi_clk_off)
 			continue;
@@ -3214,7 +3233,10 @@ static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
 			   "PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
 			   phy_name(phy));
 		val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
-		intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
+		if (IS_ALDERLAKE_S(dev_priv))
+			intel_de_write(dev_priv, ADLS_DPCLKA_CFGCR(phy), val);
+		else
+			intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2d1c5bfe4032..0ff0eeabab8c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11028,6 +11028,20 @@ static int hsw_crtc_compute_clock(struct intel_crtc *crtc,
 	return 0;
 }
 
+static void adls_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
+			     struct intel_crtc_state *pipe_config)
+{
+	enum phy phy = intel_port_to_phy(dev_priv, port);
+	enum intel_dpll_id id;
+	u32 val;
+
+	val = intel_de_read(dev_priv, ADLS_DPCLKA_CFGCR(phy));
+	val &= ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
+	id = val >> ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy);
+
+	pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
+}
+
 static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
 			    struct intel_crtc_state *pipe_config)
 {
@@ -11401,7 +11415,9 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
 			port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
 	}
 
-	if (IS_DG1(dev_priv))
+	if (IS_ALDERLAKE_S(dev_priv))
+		adls_get_ddi_pll(dev_priv, port, pipe_config);
+	else if (IS_DG1(dev_priv))
 		dg1_get_ddi_pll(dev_priv, port, pipe_config);
 	else if (INTEL_GEN(dev_priv) >= 11)
 		icl_get_ddi_pll(dev_priv, port, pipe_config);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 999b4eb422db..ce4ef7fa4000 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10307,7 +10307,7 @@ enum skl_power_gate {
 
 /* ICL Clocks */
 #define ICL_DPCLKA_CFGCR0			_MMIO(0x164280)
-#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10, 11, 24))
+#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10, 11, 24, 4, 5))
 #define  RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	REG_BIT((phy) + 10)
 #define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < TC_PORT_4 ? \
 						       (tc_port) + 12 : \
@@ -10342,6 +10342,27 @@ enum skl_power_gate {
 #define   DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_DPLL_MAP(clk_sel, phy) \
 	(((clk_sel) >> DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) + _DG1_PHY_DPLL_MAP(phy))
 
+/* ADLS Clocks */
+#define _ADLS_DPCLKA_CFGCR0			0x164280
+#define _ADLS_DPCLKA_CFGCR1			0x1642BC
+#define ADLS_DPCLKA_CFGCR(phy)			_MMIO_PHY((phy) / 3, \
+							  _ADLS_DPCLKA_CFGCR0, \
+							  _ADLS_DPCLKA_CFGCR1)
+#define  ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)		(((phy) % 3) * 2)
+/* ADLS DPCLKA_CFGCR0 DDI mask */
+#define  ADLS_DPCLKA_DDII_SEL_MASK			REG_GENMASK(5, 4)
+#define  ADLS_DPCLKA_DDIB_SEL_MASK			REG_GENMASK(3, 2)
+#define  ADLS_DPCLKA_DDIA_SEL_MASK			REG_GENMASK(1, 0)
+/* ADLS DPCLKA_CFGCR1 DDI mask */
+#define  ADLS_DPCLKA_DDIK_SEL_MASK			REG_GENMASK(3, 2)
+#define  ADLS_DPCLKA_DDIJ_SEL_MASK			REG_GENMASK(1, 0)
+#define  ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy)	_PICK((phy), \
+							ADLS_DPCLKA_DDIA_SEL_MASK, \
+							ADLS_DPCLKA_DDIB_SEL_MASK, \
+							ADLS_DPCLKA_DDII_SEL_MASK, \
+							ADLS_DPCLKA_DDIJ_SEL_MASK, \
+							ADLS_DPCLKA_DDIK_SEL_MASK)
+
 /* CNL PLL */
 #define DPLL0_ENABLE		0x46010
 #define DPLL1_ENABLE		0x46014
-- 
2.27.0

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Re: [Intel-gfx] [PATCH 09/22] drm/i915/adl_s: Configure Port clock registers for ADL-S

[Matt Roper]

On Fri, Dec 04, 2020 at 05:08:31PM -0800, Aditya Swarup wrote:
> Add changes to configure port clock registers for ADL-S. Combo phy port
> clocks are configured by DPCLKA_CFGCR0 and DPCLKA_CFGCR1 registers.
> 
> The DDI to internal clock mappings in DPCLKA_CFGCR0 register for ADL-S
> translates to
> DDI A -> DDIA
> DDI B -> USBC1
> DDI I -> USBC2
> 
> For DPCLKA_CFGCR1
> DDI J -> USBC3
> DDI K -> USBC4
> 
> Bspec: 50287
> Bspec: 53812
> Bspec: 53723
> 
> v2: Replace I915_READ() with intel_de_read().(Jani)
> 
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c     | 64 +++++++++++++-------
>  drivers/gpu/drm/i915/display/intel_display.c | 18 +++++-
>  drivers/gpu/drm/i915/i915_reg.h              | 23 ++++++-
>  3 files changed, 82 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 76e975b4765b..fdf692be2bc3 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3088,25 +3088,30 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
>  	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> -	u32 val;
> +	u32 val, mask, sel;
> +	i915_reg_t reg;
> +
> +	if (IS_ALDERLAKE_S(dev_priv)) {
> +		reg = ADLS_DPCLKA_CFGCR(phy);
> +		mask = ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
> +		sel = ((pll->info->id) << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
> +	} else if (IS_ROCKETLAKE(dev_priv)) {
> +		reg = ICL_DPCLKA_CFGCR0;
> +		mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> +		sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> +	} else {
> +		reg = ICL_DPCLKA_CFGCR0;
> +		mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> +		sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> +	}
>  
>  	mutex_lock(&dev_priv->dpll.lock);
>  
> -	val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
> +	val = intel_de_read(dev_priv, reg);
>  	drm_WARN_ON(&dev_priv->drm,
>  		    (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
>  
>  	if (intel_phy_is_combo(dev_priv, phy)) {
> -		u32 mask, sel;
> -
> -		if (IS_ROCKETLAKE(dev_priv)) {
> -			mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> -			sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> -		} else {
> -			mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> -			sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> -		}
> -
>  		/*
>  		 * Even though this register references DDIs, note that we
>  		 * want to pass the PHY rather than the port (DDI).  For
> @@ -3119,12 +3124,12 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
>  		 */
>  		val &= ~mask;
>  		val |= sel;
> -		intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
> -		intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
> +		intel_de_write(dev_priv, reg, val);
> +		intel_de_posting_read(dev_priv, reg);
>  	}
>  
>  	val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
> -	intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
> +	intel_de_write(dev_priv, reg, val);
>  
>  	mutex_unlock(&dev_priv->dpll.lock);
>  }
> @@ -3150,9 +3155,17 @@ static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
>  
>  	mutex_lock(&dev_priv->dpll.lock);
>  
> -	val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
> +	if (IS_ALDERLAKE_S(dev_priv))
> +		val = intel_de_read(dev_priv, ADLS_DPCLKA_CFGCR(phy));
> +	else
> +		val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
> +
>  	val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
> -	intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
> +
> +	if (IS_ALDERLAKE_S(dev_priv))
> +		intel_de_write(dev_priv, ADLS_DPCLKA_CFGCR(phy), val);
> +	else
> +		intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);

We could potentially assign the register to a local at the top of the
function like we did in icl_map_plls_to_ports() to avoid having to do
two separate conditionals.  Up to you though; it doesn't really matter
either way.

>  
>  	mutex_unlock(&dev_priv->dpll.lock);
>  }
> @@ -3192,13 +3205,19 @@ static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
>  				      u32 port_mask, bool ddi_clk_needed)
>  {
>  	enum port port;
> +	bool ddi_clk_off;
>  	u32 val;
>  
> -	val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
>  	for_each_port_masked(port, port_mask) {
>  		enum phy phy = intel_port_to_phy(dev_priv, port);
> -		bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
> -								   phy);
> +
> +		if (IS_ALDERLAKE_S(dev_priv))
> +			val = intel_de_read(dev_priv, ADLS_DPCLKA_CFGCR(phy));
> +		else
> +			val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
> +
> +		ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
> +							      phy);
>  
>  		if (ddi_clk_needed == !ddi_clk_off)
>  			continue;
> @@ -3214,7 +3233,10 @@ static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
>  			   "PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
>  			   phy_name(phy));
>  		val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
> -		intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
> +		if (IS_ALDERLAKE_S(dev_priv))
> +			intel_de_write(dev_priv, ADLS_DPCLKA_CFGCR(phy), val);
> +		else
> +			intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);

Same comment here.

Either way,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

The way the bits are spread across two different registers and with
strange offsets is sort of an unintuitive hardware design, but your
implementation here looks correct to me.


Matt

>  	}
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 2d1c5bfe4032..0ff0eeabab8c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -11028,6 +11028,20 @@ static int hsw_crtc_compute_clock(struct intel_crtc *crtc,
>  	return 0;
>  }
>  
> +static void adls_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
> +			     struct intel_crtc_state *pipe_config)
> +{
> +	enum phy phy = intel_port_to_phy(dev_priv, port);
> +	enum intel_dpll_id id;
> +	u32 val;
> +
> +	val = intel_de_read(dev_priv, ADLS_DPCLKA_CFGCR(phy));
> +	val &= ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
> +	id = val >> ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy);
> +
> +	pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
> +}
> +
>  static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
>  			    struct intel_crtc_state *pipe_config)
>  {
> @@ -11401,7 +11415,9 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
>  			port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
>  	}
>  
> -	if (IS_DG1(dev_priv))
> +	if (IS_ALDERLAKE_S(dev_priv))
> +		adls_get_ddi_pll(dev_priv, port, pipe_config);
> +	else if (IS_DG1(dev_priv))
>  		dg1_get_ddi_pll(dev_priv, port, pipe_config);
>  	else if (INTEL_GEN(dev_priv) >= 11)
>  		icl_get_ddi_pll(dev_priv, port, pipe_config);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 999b4eb422db..ce4ef7fa4000 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10307,7 +10307,7 @@ enum skl_power_gate {
>  
>  /* ICL Clocks */
>  #define ICL_DPCLKA_CFGCR0			_MMIO(0x164280)
> -#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10, 11, 24))
> +#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10, 11, 24, 4, 5))
>  #define  RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	REG_BIT((phy) + 10)
>  #define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < TC_PORT_4 ? \
>  						       (tc_port) + 12 : \
> @@ -10342,6 +10342,27 @@ enum skl_power_gate {
>  #define   DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_DPLL_MAP(clk_sel, phy) \
>  	(((clk_sel) >> DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) + _DG1_PHY_DPLL_MAP(phy))
>  
> +/* ADLS Clocks */
> +#define _ADLS_DPCLKA_CFGCR0			0x164280
> +#define _ADLS_DPCLKA_CFGCR1			0x1642BC
> +#define ADLS_DPCLKA_CFGCR(phy)			_MMIO_PHY((phy) / 3, \
> +							  _ADLS_DPCLKA_CFGCR0, \
> +							  _ADLS_DPCLKA_CFGCR1)
> +#define  ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)		(((phy) % 3) * 2)
> +/* ADLS DPCLKA_CFGCR0 DDI mask */
> +#define  ADLS_DPCLKA_DDII_SEL_MASK			REG_GENMASK(5, 4)
> +#define  ADLS_DPCLKA_DDIB_SEL_MASK			REG_GENMASK(3, 2)
> +#define  ADLS_DPCLKA_DDIA_SEL_MASK			REG_GENMASK(1, 0)
> +/* ADLS DPCLKA_CFGCR1 DDI mask */
> +#define  ADLS_DPCLKA_DDIK_SEL_MASK			REG_GENMASK(3, 2)
> +#define  ADLS_DPCLKA_DDIJ_SEL_MASK			REG_GENMASK(1, 0)
> +#define  ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy)	_PICK((phy), \
> +							ADLS_DPCLKA_DDIA_SEL_MASK, \
> +							ADLS_DPCLKA_DDIB_SEL_MASK, \
> +							ADLS_DPCLKA_DDII_SEL_MASK, \
> +							ADLS_DPCLKA_DDIJ_SEL_MASK, \
> +							ADLS_DPCLKA_DDIK_SEL_MASK)
> +
>  /* CNL PLL */
>  #define DPLL0_ENABLE		0x46010
>  #define DPLL1_ENABLE		0x46014
> -- 
> 2.27.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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[Intel-gfx] [PATCH 10/22] drm/i915/adl_s: Initialize display for ADL-S

[Aditya Swarup]

Initialize display outputs for ADL-S. ADL-S has 5 display
outputs -> 1 eDP, 2 HDMI and 2 DP++ outputs.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0ff0eeabab8c..19ed51e6c647 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17627,7 +17627,13 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 	if (!HAS_DISPLAY(dev_priv))
 		return;
 
-	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
+	if (IS_ALDERLAKE_S(dev_priv)) {
+		intel_ddi_init(dev_priv, PORT_A);
+		intel_ddi_init(dev_priv, PORT_D);	/* DDI TC1 */
+		intel_ddi_init(dev_priv, PORT_E);	/* DDI TC2 */
+		intel_ddi_init(dev_priv, PORT_F);	/* DDI TC3 */
+		intel_ddi_init(dev_priv, PORT_G);	/* DDI TC4 */
+	} else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
 		intel_ddi_init(dev_priv, PORT_TC1);
-- 
2.27.0

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Re: [Intel-gfx] [PATCH 10/22] drm/i915/adl_s: Initialize display for ADL-S

[Matt Roper]

On Fri, Dec 04, 2020 at 05:08:32PM -0800, Aditya Swarup wrote:
> Initialize display outputs for ADL-S. ADL-S has 5 display
> outputs -> 1 eDP, 2 HDMI and 2 DP++ outputs.
> 
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 0ff0eeabab8c..19ed51e6c647 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -17627,7 +17627,13 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
>  	if (!HAS_DISPLAY(dev_priv))
>  		return;
>  
> -	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
> +	if (IS_ALDERLAKE_S(dev_priv)) {
> +		intel_ddi_init(dev_priv, PORT_A);
> +		intel_ddi_init(dev_priv, PORT_D);	/* DDI TC1 */

It all comes out the same in the end, but we should just pass PORT_TC1
and such for these outputs since that's the formal name in the bspec
(and matches how we handle RKL/DG1 that also have "TC" DDIs that are
actually combo PHYs).


Matt

> +		intel_ddi_init(dev_priv, PORT_E);	/* DDI TC2 */
> +		intel_ddi_init(dev_priv, PORT_F);	/* DDI TC3 */
> +		intel_ddi_init(dev_priv, PORT_G);	/* DDI TC4 */
> +	} else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
>  		intel_ddi_init(dev_priv, PORT_A);
>  		intel_ddi_init(dev_priv, PORT_B);
>  		intel_ddi_init(dev_priv, PORT_TC1);
> -- 
> 2.27.0
> 

-- 
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Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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[Intel-gfx] [PATCH 11/22] drm/i915/adl_s: Add adl-s ddc pin mapping

[Aditya Swarup]

ADL-S requires TC pins to set up ddc for Combo PHY B, C, D and E.
Combo PHY A still uses the old ddc pin mapping.

From VBT, ddc pin info suggests the following mapping:
VBT 			               DRIVER
DDI B->ddc_pin=2 should translate to PORT_D->0x9
DDI C->ddc_pin=3 should translate to PORT_E->0xa
DDI D->ddc_pin=4 should translate to PORT_F->0xb
DDI E->ddc_pin=5 should translate to PORT_G->0xc

Adding pin map to facilitate this translation as we cannot use existing
icl ddc pin map due to conflict with DDI B and DDI C info.

Bspec:20124

v2: Replace IS_ALDERLAKE_S() with HAS_PCH_ADP() as the pin map pairing
depends on the PCH being used rather than the platform.(mdroper)

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 13 +++++++++++-
 drivers/gpu/drm/i915/display/intel_hdmi.c     | 20 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |  4 ++++
 3 files changed, 35 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 4cc949b228f2..9dc67c03ffc0 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1623,12 +1623,23 @@ static const u8 icp_ddc_pin_map[] = {
 	[TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
 };
 
+static const u8 adls_ddc_pin_map[] = {
+	[ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
+	[ADLS_DDC_BUS_PORT_TC1] = GMBUS_PIN_9_TC1_ICP,
+	[ADLS_DDC_BUS_PORT_TC2] = GMBUS_PIN_10_TC2_ICP,
+	[ADLS_DDC_BUS_PORT_TC3] = GMBUS_PIN_11_TC3_ICP,
+	[ADLS_DDC_BUS_PORT_TC4] = GMBUS_PIN_12_TC4_ICP,
+};
+
 static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
 {
 	const u8 *ddc_pin_map;
 	int n_entries;
 
-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
+	if (HAS_PCH_ADP(dev_priv)) {
+		ddc_pin_map = adls_ddc_pin_map;
+		n_entries = ARRAY_SIZE(adls_ddc_pin_map);
+	} else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
 		return vbt_pin;
 	} else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
 		ddc_pin_map = icp_ddc_pin_map;
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index e10fdb369daa..060a13b63aa9 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3135,6 +3135,22 @@ static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
 	return intel_port_to_phy(dev_priv, port) + 1;
 }
 
+static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
+{
+	enum phy phy = intel_port_to_phy(dev_priv, port);
+
+	WARN_ON(port == PORT_B || port == PORT_C);
+
+	/*
+	 * Pin mapping for ADL-S requires TC pins for all combo phy outputs
+	 * except first combo output.
+	 */
+	if (IS_ALDERLAKE_S(dev_priv) && phy >= PHY_B)
+		return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
+
+	return GMBUS_PIN_1_BXT + phy;
+}
+
 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
 			      enum port port)
 {
@@ -3172,7 +3188,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
 		return ddc_pin;
 	}
 
-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+	if (IS_ALDERLAKE_S(dev_priv))
+		ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
+	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
 		ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
 	else if (IS_ROCKETLAKE(dev_priv))
 		ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 49b4b5fca941..32d1b4f05760 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -325,6 +325,10 @@ enum vbt_gmbus_ddi {
 	ICL_DDC_BUS_PORT_4,
 	TGL_DDC_BUS_PORT_5,
 	TGL_DDC_BUS_PORT_6,
+	ADLS_DDC_BUS_PORT_TC1 = 0x2,
+	ADLS_DDC_BUS_PORT_TC2,
+	ADLS_DDC_BUS_PORT_TC3,
+	ADLS_DDC_BUS_PORT_TC4
 };
 
 #define DP_AUX_A 0x40
-- 
2.27.0

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Re: [Intel-gfx] [PATCH 11/22] drm/i915/adl_s: Add adl-s ddc pin mapping

[Matt Roper]

On Fri, Dec 04, 2020 at 05:08:33PM -0800, Aditya Swarup wrote:
> ADL-S requires TC pins to set up ddc for Combo PHY B, C, D and E.
> Combo PHY A still uses the old ddc pin mapping.
> 
> From VBT, ddc pin info suggests the following mapping:
> VBT 			               DRIVER
> DDI B->ddc_pin=2 should translate to PORT_D->0x9
> DDI C->ddc_pin=3 should translate to PORT_E->0xa
> DDI D->ddc_pin=4 should translate to PORT_F->0xb
> DDI E->ddc_pin=5 should translate to PORT_G->0xc
> 
> Adding pin map to facilitate this translation as we cannot use existing
> icl ddc pin map due to conflict with DDI B and DDI C info.
> 
> Bspec:20124
> 
> v2: Replace IS_ALDERLAKE_S() with HAS_PCH_ADP() as the pin map pairing
> depends on the PCH being used rather than the platform.(mdroper)
> 
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bios.c     | 13 +++++++++++-
>  drivers/gpu/drm/i915/display/intel_hdmi.c     | 20 ++++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_vbt_defs.h |  4 ++++
>  3 files changed, 35 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 4cc949b228f2..9dc67c03ffc0 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1623,12 +1623,23 @@ static const u8 icp_ddc_pin_map[] = {
>  	[TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
>  };
>  
> +static const u8 adls_ddc_pin_map[] = {
> +	[ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
> +	[ADLS_DDC_BUS_PORT_TC1] = GMBUS_PIN_9_TC1_ICP,
> +	[ADLS_DDC_BUS_PORT_TC2] = GMBUS_PIN_10_TC2_ICP,
> +	[ADLS_DDC_BUS_PORT_TC3] = GMBUS_PIN_11_TC3_ICP,
> +	[ADLS_DDC_BUS_PORT_TC4] = GMBUS_PIN_12_TC4_ICP,
> +};

Can't we use icp_ddc_pin_map[] since it's a superset of this?  The ICP
table has some extra entries that we'll never map through, but that's
true for other platforms as well.  E.g., ICP itself can never have a
DDI_C or TC5/TC6, but it doesn't hurt anything to have those outputs as
extra entries in the table that never get looked up.


> +
>  static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
>  {
>  	const u8 *ddc_pin_map;
>  	int n_entries;
>  
> -	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
> +	if (HAS_PCH_ADP(dev_priv)) {
> +		ddc_pin_map = adls_ddc_pin_map;
> +		n_entries = ARRAY_SIZE(adls_ddc_pin_map);
> +	} else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
>  		return vbt_pin;
>  	} else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
>  		ddc_pin_map = icp_ddc_pin_map;
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index e10fdb369daa..060a13b63aa9 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -3135,6 +3135,22 @@ static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
>  	return intel_port_to_phy(dev_priv, port) + 1;
>  }
>  
> +static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
> +{
> +	enum phy phy = intel_port_to_phy(dev_priv, port);
> +
> +	WARN_ON(port == PORT_B || port == PORT_C);
> +
> +	/*
> +	 * Pin mapping for ADL-S requires TC pins for all combo phy outputs
> +	 * except first combo output.
> +	 */
> +	if (IS_ALDERLAKE_S(dev_priv) && phy >= PHY_B)

The IS_ADLS test here is redundant since we only call this function on
ADL-S, right?

> +		return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
> +
> +	return GMBUS_PIN_1_BXT + phy;

There's only one possible output that can get to this return
(PORT_A/PHY_A), so the generic "+ phy" seems unnecessary.

Actually it might more more sensible to make PHY_A the special case we
test for in the 'if' condition and then make the PHY_B+ case the
function's regular return.

> +}
> +
>  static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
>  			      enum port port)
>  {
> @@ -3172,7 +3188,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
>  		return ddc_pin;
>  	}
>  
> -	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> +	if (IS_ALDERLAKE_S(dev_priv))

This should probably be a PCH check instead of a platform check too.


Matt

> +		ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
> +	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
>  		ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
>  	else if (IS_ROCKETLAKE(dev_priv))
>  		ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index 49b4b5fca941..32d1b4f05760 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -325,6 +325,10 @@ enum vbt_gmbus_ddi {
>  	ICL_DDC_BUS_PORT_4,
>  	TGL_DDC_BUS_PORT_5,
>  	TGL_DDC_BUS_PORT_6,
> +	ADLS_DDC_BUS_PORT_TC1 = 0x2,
> +	ADLS_DDC_BUS_PORT_TC2,
> +	ADLS_DDC_BUS_PORT_TC3,
> +	ADLS_DDC_BUS_PORT_TC4
>  };
>  
>  #define DP_AUX_A 0x40
> -- 
> 2.27.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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[Intel-gfx] [PATCH 12/22] drm/i915/adl_s: Add vbt port and aux channel settings for adls

[Aditya Swarup]

- ADL-S driver internal mapping uses PORT D, E, F, G for Combo phy B, C, D and E.
- Add ADLS specific port mappings for vbt port dvo settings.
- Select appropriate AUX CH specific to ADLS based on port mapping.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c | 57 ++++++++++++++++++-----
 1 file changed, 46 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 9dc67c03ffc0..8f166f49b6cc 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1709,8 +1709,26 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
 		[PORT_TC1] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
 		[PORT_TC2] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
 	};
+	/*
+	 * Alderlake S ports used in the driver are PORT_A, PORT_D, PORT_E,
+	 * PORT_F and PORT_G, we need to map that to correct VBT sections.
+	 */
+	static const int adls_port_mapping[][3] = {
+		[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
+		[PORT_B] = { -1 },
+		[PORT_C] = { -1 },
+		[PORT_TC1] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
+		[PORT_TC2] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
+		[PORT_TC3] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
+		[PORT_TC4] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 },
+	};
 
-	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+	if (IS_ALDERLAKE_S(dev_priv))
+		return __dvo_port_to_port(ARRAY_SIZE(adls_port_mapping),
+					  ARRAY_SIZE(adls_port_mapping[0]),
+					  adls_port_mapping,
+					  dvo_port);
+	else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 		return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping),
 					  ARRAY_SIZE(rkl_port_mapping[0]),
 					  rkl_port_mapping,
@@ -2667,27 +2685,44 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
 		return aux_ch;
 	}
 
+	/*
+	 * RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D
+	 * map to DDI A,B,TC1,TC2 respectively.
+	 *
+	 * ADL-S VBT uses PHY based mapping. Combo PHYs A,B,C,D,E
+	 * map to DDI A,TC1,TC2,TC3,TC4 respectively.
+	 */
 	switch (info->alternate_aux_channel) {
 	case DP_AUX_A:
 		aux_ch = AUX_CH_A;
 		break;
 	case DP_AUX_B:
-		aux_ch = AUX_CH_B;
+		if (IS_ALDERLAKE_S(dev_priv))
+			aux_ch = AUX_CH_USBC1;
+		else
+			aux_ch = AUX_CH_B;
 		break;
 	case DP_AUX_C:
-		/*
-		 * RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D
-		 * map to DDI A,B,TC1,TC2 respectively.
-		 */
-		aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
-			AUX_CH_USBC1 : AUX_CH_C;
+		if (IS_ALDERLAKE_S(dev_priv))
+			aux_ch = AUX_CH_USBC2;
+		else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+			aux_ch = AUX_CH_USBC1;
+		else
+			aux_ch = AUX_CH_C;
 		break;
 	case DP_AUX_D:
-		aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
-			AUX_CH_USBC2 : AUX_CH_D;
+		if (IS_ALDERLAKE_S(dev_priv))
+			aux_ch = AUX_CH_USBC3;
+		else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+			aux_ch = AUX_CH_USBC2;
+		else
+			aux_ch = AUX_CH_D;
 		break;
 	case DP_AUX_E:
-		aux_ch = AUX_CH_E;
+		if (IS_ALDERLAKE_S(dev_priv))
+			aux_ch = AUX_CH_USBC4;
+		else
+			aux_ch = AUX_CH_E;
 		break;
 	case DP_AUX_F:
 		aux_ch = AUX_CH_F;
-- 
2.27.0

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Re: [Intel-gfx] [PATCH 12/22] drm/i915/adl_s: Add vbt port and aux channel settings for adls

[Matt Roper]

On Fri, Dec 04, 2020 at 05:08:34PM -0800, Aditya Swarup wrote:
> - ADL-S driver internal mapping uses PORT D, E, F, G for Combo phy B, C, D and E.
> - Add ADLS specific port mappings for vbt port dvo settings.
> - Select appropriate AUX CH specific to ADLS based on port mapping.

The aux stuff is getting really messy; we're definitely going to have to
move to a table-based approach for some of this stuff soon to keep it
from getting too out of hand.

The changes here look correct for the current style though.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> 
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bios.c | 57 ++++++++++++++++++-----
>  1 file changed, 46 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 9dc67c03ffc0..8f166f49b6cc 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1709,8 +1709,26 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
>  		[PORT_TC1] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
>  		[PORT_TC2] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
>  	};
> +	/*
> +	 * Alderlake S ports used in the driver are PORT_A, PORT_D, PORT_E,
> +	 * PORT_F and PORT_G, we need to map that to correct VBT sections.
> +	 */
> +	static const int adls_port_mapping[][3] = {
> +		[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
> +		[PORT_B] = { -1 },
> +		[PORT_C] = { -1 },
> +		[PORT_TC1] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
> +		[PORT_TC2] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
> +		[PORT_TC3] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
> +		[PORT_TC4] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 },
> +	};
>  
> -	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
> +	if (IS_ALDERLAKE_S(dev_priv))
> +		return __dvo_port_to_port(ARRAY_SIZE(adls_port_mapping),
> +					  ARRAY_SIZE(adls_port_mapping[0]),
> +					  adls_port_mapping,
> +					  dvo_port);
> +	else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
>  		return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping),
>  					  ARRAY_SIZE(rkl_port_mapping[0]),
>  					  rkl_port_mapping,
> @@ -2667,27 +2685,44 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
>  		return aux_ch;
>  	}
>  
> +	/*
> +	 * RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D
> +	 * map to DDI A,B,TC1,TC2 respectively.
> +	 *
> +	 * ADL-S VBT uses PHY based mapping. Combo PHYs A,B,C,D,E
> +	 * map to DDI A,TC1,TC2,TC3,TC4 respectively.
> +	 */
>  	switch (info->alternate_aux_channel) {
>  	case DP_AUX_A:
>  		aux_ch = AUX_CH_A;
>  		break;
>  	case DP_AUX_B:
> -		aux_ch = AUX_CH_B;
> +		if (IS_ALDERLAKE_S(dev_priv))
> +			aux_ch = AUX_CH_USBC1;
> +		else
> +			aux_ch = AUX_CH_B;
>  		break;
>  	case DP_AUX_C:
> -		/*
> -		 * RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D
> -		 * map to DDI A,B,TC1,TC2 respectively.
> -		 */
> -		aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
> -			AUX_CH_USBC1 : AUX_CH_C;
> +		if (IS_ALDERLAKE_S(dev_priv))
> +			aux_ch = AUX_CH_USBC2;
> +		else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
> +			aux_ch = AUX_CH_USBC1;
> +		else
> +			aux_ch = AUX_CH_C;
>  		break;
>  	case DP_AUX_D:
> -		aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
> -			AUX_CH_USBC2 : AUX_CH_D;
> +		if (IS_ALDERLAKE_S(dev_priv))
> +			aux_ch = AUX_CH_USBC3;
> +		else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
> +			aux_ch = AUX_CH_USBC2;
> +		else
> +			aux_ch = AUX_CH_D;
>  		break;
>  	case DP_AUX_E:
> -		aux_ch = AUX_CH_E;
> +		if (IS_ALDERLAKE_S(dev_priv))
> +			aux_ch = AUX_CH_USBC4;
> +		else
> +			aux_ch = AUX_CH_E;
>  		break;
>  	case DP_AUX_F:
>  		aux_ch = AUX_CH_F;
> -- 
> 2.27.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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[Intel-gfx] [PATCH 13/22] drm/i915/adl_s: Update combo PHY master/slave relationships

[Aditya Swarup]

From: Matt Roper <matthew.d.roper@intel.com>

ADL-S switches up which PHYs are considered a master to other PHYs;
PHY-C is no longer a master, but PHY-D is now.

Bspec: 49291
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_combo_phy.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 996ae0608a62..dd45cbafcf42 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -246,14 +246,21 @@ static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)
 	 * RKL,DG1:
 	 *   A(master) -> B(slave)
 	 *   C(master) -> D(slave)
+	 * ADL-S:
+	 *   A(master) -> B(slave), C(slave)
+	 *   D(master) -> E(slave)
 	 *
 	 * We must set the IREFGEN bit for any PHY acting as a master
 	 * to another PHY.
 	 */
-	if ((IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) && phy == PHY_C)
+	if (phy == PHY_A)
 		return true;
+	else if (IS_ALDERLAKE_S(dev_priv))
+		return phy == PHY_D;
+	else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+		return phy == PHY_C;
 
-	return phy == PHY_A;
+	return false;
 }
 
 static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
-- 
2.27.0

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[Intel-gfx] [PATCH 14/22] drm/i915/adl_s: Update PHY_MISC programming

[Aditya Swarup]

From: Matt Roper <matthew.d.roper@intel.com>

ADL-S switches up which PHYs are considered a master to other PHYs;
PHY-C is no longer a master, but PHY-D is now.

Bspec: 49291
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/display/intel_combo_phy.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index dd45cbafcf42..c55813c6194a 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -187,10 +187,16 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
 	 * Some platforms only expect PHY_MISC to be programmed for PHY-A and
 	 * PHY-B and may not even have instances of the register for the
 	 * other combo PHY's.
+	 *
+	 * ADL-S technically has three instances of PHY_MISC, but only requires
+	 * that we program it for PHY A.
 	 */
-	if (IS_JSL_EHL(i915) ||
-	    IS_ROCKETLAKE(i915) ||
-	    IS_DG1(i915))
+
+	if (IS_ALDERLAKE_S(i915))
+		return phy == PHY_A;
+	else if (IS_JSL_EHL(i915) ||
+		 IS_ROCKETLAKE(i915) ||
+		 IS_DG1(i915))
 		return phy < PHY_C;
 
 	return true;
-- 
2.27.0

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[Intel-gfx] [PATCH 15/22] drm/i915/adl_s: Add display WAs for ADL-S

[Aditya Swarup]

- Extend permanent driver WA Wa_1409767108, Wa_14010685332
  and Wa_14011294188 to adl-s.
- Extend permanent driver WA Wa_1606054188 to adl-s.
- Add Wa_14011765242 for adl-s A0 stepping.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 7 ++++---
 drivers/gpu/drm/i915/display/intel_sprite.c        | 4 ++--
 drivers/gpu/drm/i915/intel_device_info.c           | 6 +++++-
 3 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 06c036e2092c..8b163d804a41 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5282,9 +5282,10 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
 	unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
 	int config, i;
 
-	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
+	if (IS_ALDERLAKE_S(dev_priv) ||
+	    IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
 	    IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_B0))
-		/* Wa_1409767108:tgl,dg1 */
+		/* Wa_1409767108:tgl,dg1,adl-s */
 		table = wa_1409767108_buddy_page_masks;
 	else
 		table = tgl_buddy_page_masks;
@@ -5322,7 +5323,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
 
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
-	/* Wa_14011294188:ehl,jsl,tgl,rkl */
+	/* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_JSP &&
 	    INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
 		intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index e19d4f873b94..2d820ff2b236 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2371,8 +2371,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 		return -EINVAL;
 	}
 
-	/* Wa_1606054188:tgl */
-	if (IS_TIGERLAKE(dev_priv) &&
+	/* Wa_1606054188:tgl,adl-s */
+	if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
 	    plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
 	    intel_format_is_p01x(fb->format->format)) {
 		drm_dbg_kms(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index ce8c69c17b8e..da651ef10014 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -394,7 +394,11 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 	struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
 	enum pipe pipe;
 
-	if (INTEL_GEN(dev_priv) >= 10) {
+	/* Wa_14011765242: adl-s A0 */
+	if (IS_ADLS_DISP_REVID(dev_priv, REVID_A0, REVID_A0))
+		for_each_pipe(dev_priv, pipe)
+			runtime->num_scalers[pipe] = 0;
+	else if (INTEL_GEN(dev_priv) >= 10) {
 		for_each_pipe(dev_priv, pipe)
 			runtime->num_scalers[pipe] = 2;
 	} else if (IS_GEN(dev_priv, 9)) {
-- 
2.27.0

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[Intel-gfx] [PATCH 16/22] drm/i915/adl_s: Add GT and CTX WAs for ADL-S

[Aditya Swarup]

- Add placeholders for gt and ctx WAs for ADL-S
- Extend Wa_1606931601 and Wa_1409804808 to ADL-S.
- Extend Wa_14010919138 and Wa_14010229206 to ADL-S (Madhumitha)
- Extend Wa_22010271021 to ADLS (cyokoyam)

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 91 ++++++++++++++-------
 1 file changed, 61 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3db57b577a79..1a1958d3e617 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -664,22 +664,6 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 				     struct i915_wa_list *wal)
 {
 	gen12_ctx_workarounds_init(engine, wal);
-
-	/*
-	 * Wa_1604555607:tgl,rkl
-	 *
-	 * Note that the implementation of this workaround is further modified
-	 * according to the FF_MODE2 guidance given by Wa_1608008084:gen12.
-	 * FF_MODE2 register will return the wrong value when read. The default
-	 * value for this register is zero for all fields and there are no bit
-	 * masks. So instead of doing a RMW we should just write the GS Timer
-	 * and TDS timer values for Wa_1604555607 and Wa_16011163337.
-	 */
-	wa_add(wal,
-	       FF_MODE2,
-	       FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK,
-	       FF_MODE2_GS_TIMER_224  | FF_MODE2_TDS_TIMER_128,
-	       0);
 }
 
 static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
@@ -696,6 +680,12 @@ static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
 			  DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
 }
 
+static void adls_ctx_workarounds_init(struct intel_engine_cs *engine,
+				      struct i915_wa_list *wal)
+{
+	gen12_ctx_workarounds_init(engine, wal);
+}
+
 static void
 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
 			   struct i915_wa_list *wal,
@@ -708,7 +698,31 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
 
 	wa_init_start(wal, name, engine->name);
 
-	if (IS_DG1(i915))
+	if (INTEL_GEN(i915) >= 12) {
+		/*
+		 * This setting isn't actually a workaround, but is a general
+		 * tuning setting that needs to be programmed on all platforms
+		 * gen12+. Although some platforms also refer to this setting
+		 * as Wa_1604555607, we need to program it even on platforms that
+		 * don't explicitly list that workaround.
+		 *
+		 * Note that the implementation is further modified according
+		 * to the FF_MODE2 guidance given by Wa_1608008084:gen12.
+		 * FF_MODE2 register will return the wrong value when read.
+		 * The default value for this register is zero for all fields
+		 * and there are no bit masks. So instead of doing a RMW, we
+		 * should just write the value directly.
+		 */
+		wa_add(wal,
+		       FF_MODE2,
+		       FF_MODE2_TDS_TIMER_MASK,
+		       FF_MODE2_TDS_TIMER_128,
+		       0);
+	}
+
+	if (IS_ALDERLAKE_S(i915))
+		adls_ctx_workarounds_init(engine, wal);
+	else if (IS_DG1(i915))
 		dg1_ctx_workarounds_init(engine, wal);
 	else if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915))
 		tgl_ctx_workarounds_init(engine, wal);
@@ -1294,10 +1308,18 @@ dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 			    VSUNIT_CLKGATE_DIS_TGL);
 }
 
+static void
+adls_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+	gen12_gt_workarounds_init(i915, wal);
+}
+
 static void
 gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
 {
-	if (IS_DG1(i915))
+	if (IS_ALDERLAKE_S(i915))
+		adls_gt_workarounds_init(i915, wal);
+	else if (IS_DG1(i915))
 		dg1_gt_workarounds_init(i915, wal);
 	else if (IS_TIGERLAKE(i915))
 		tgl_gt_workarounds_init(i915, wal);
@@ -1678,6 +1700,11 @@ static void dg1_whitelist_build(struct intel_engine_cs *engine)
 				  RING_FORCE_TO_NONPRIV_ACCESS_RD);
 }
 
+static void adls_whitelist_build(struct intel_engine_cs *engine)
+{
+	tgl_whitelist_build(engine);
+}
+
 void intel_engine_init_whitelist(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *i915 = engine->i915;
@@ -1685,7 +1712,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
 
 	wa_init_start(w, "whitelist", engine->name);
 
-	if (IS_DG1(i915))
+	if (IS_ALDERLAKE_S(i915))
+		adls_whitelist_build(engine);
+	else if (IS_DG1(i915))
 		dg1_whitelist_build(engine);
 	else if (IS_GEN(i915, 12))
 		tgl_whitelist_build(engine);
@@ -1766,22 +1795,23 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 			    VSUNIT_CLKGATE_DIS_TGL);
 	}
 
-	if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
-		/* Wa_1606931601:tgl,rkl,dg1 */
+	if (IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
+	    IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+		/* Wa_1606931601:tgl,rkl,dg1,adl-s */
 		wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
 
 		/*
 		 * Wa_1407928979:tgl A*
 		 * Wa_18011464164:tgl[B0+],dg1[B0+]
 		 * Wa_22010931296:tgl[B0+],dg1[B0+]
-		 * Wa_14010919138:rkl, dg1
+		 * Wa_14010919138:rkl,dg1,adl-s
 		 */
 		wa_write_or(wal, GEN7_FF_THREAD_MODE,
 			    GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
 
 		/*
 		 * Wa_1606700617:tgl,dg1
-		 * Wa_22010271021:tgl,rkl,dg1
+		 * Wa_22010271021:tgl,rkl,dg1, adl-s
 		 */
 		wa_masked_en(wal,
 			     GEN9_CS_DEBUG_MODE1,
@@ -1793,15 +1823,15 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 			     ENABLE_SMALLPL);
 	}
 
-	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+	if (IS_ALDERLAKE_S(i915) || IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
 	    IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
-		/* Wa_1409804808:tgl,rkl,dg1[a0] */
+		/* Wa_1409804808:tgl,rkl,dg1[a0],adl-s */
 		wa_masked_en(wal, GEN7_ROW_CHICKEN2,
 			     GEN12_PUSH_CONST_DEREF_HOLD_DIS);
 
 		/*
 		 * Wa_1409085225:tgl
-		 * Wa_14010229206:tgl,rkl,dg1[a0]
+		 * Wa_14010229206:tgl,rkl,dg1[a0],adl-s
 		 */
 		wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
 
@@ -1815,10 +1845,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 		 * it applies to all steppings so we trust the "all steppings."
 		 * For DG1 this only applies to A0.
 		 */
-		wa_masked_en(wal,
-			     GEN6_RC_SLEEP_PSMI_CONTROL,
-			     GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
-			     GEN8_RC_SEMA_IDLE_MSG_DISABLE);
+		if (!IS_ALDERLAKE_S(i915))
+			wa_masked_en(wal,
+				     GEN6_RC_SLEEP_PSMI_CONTROL,
+				     GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
+				     GEN8_RC_SEMA_IDLE_MSG_DISABLE);
 	}
 
 	if (IS_GEN(i915, 11)) {
-- 
2.27.0

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[Intel-gfx] [PATCH 17/22] drm/i915/adl_s: MCHBAR memory info registers are moved

[Aditya Swarup]

From: Caz Yokoyama <caz.yokoyama@intel.com>

The crwebview indicates on ADL-S that some of our MCHBAR
registers have moved from their traditional 0x50XX offsets to
new locations. The meaning and bit layout of the registers
remain same.

v2: Simplify logic to a single if else chain and fix indents.(Lucas)

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   |  5 +++++
 drivers/gpu/drm/i915/intel_dram.c | 23 +++++++++++++++++------
 2 files changed, 22 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ce4ef7fa4000..55e186293fbb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10865,6 +10865,8 @@ enum skl_power_gate {
 #define  SKL_DRAM_DDR_TYPE_LPDDR3		(2 << 0)
 #define  SKL_DRAM_DDR_TYPE_LPDDR4		(3 << 0)
 
+#define ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6048)
+
 #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
 #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
 #define  SKL_DRAM_S_SHIFT			16
@@ -10892,6 +10894,9 @@ enum skl_power_gate {
 #define  CNL_DRAM_RANK_3			(0x2 << 9)
 #define  CNL_DRAM_RANK_4			(0x3 << 9)
 
+#define ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6054)
+#define ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6058)
+
 /*
  * Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
  * since on HSW we can't write to it using intel_uncore_write.
diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
index 4754296a250e..fc9942139ccc 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -181,17 +181,24 @@ skl_dram_get_channels_info(struct drm_i915_private *i915)
 {
 	struct dram_info *dram_info = &i915->dram_info;
 	struct dram_channel_info ch0 = {}, ch1 = {};
+	i915_reg_t ch0_reg, ch1_reg;
 	u32 val;
 	int ret;
 
-	val = intel_uncore_read(&i915->uncore,
-				SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
+	if (IS_ALDERLAKE_S(i915)) {
+		ch0_reg = ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR;
+		ch1_reg = ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR;
+	} else {
+		ch0_reg = ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR;
+		ch1_reg = ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR;
+	}
+
+	val = intel_uncore_read(&i915->uncore, ch0_reg);
 	ret = skl_dram_get_channel_info(i915, &ch0, 0, val);
 	if (ret == 0)
 		dram_info->num_channels++;
 
-	val = intel_uncore_read(&i915->uncore,
-				SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
+	val = intel_uncore_read(&i915->uncore, ch1_reg);
 	ret = skl_dram_get_channel_info(i915, &ch1, 1, val);
 	if (ret == 0)
 		dram_info->num_channels++;
@@ -231,8 +238,12 @@ skl_get_dram_type(struct drm_i915_private *i915)
 {
 	u32 val;
 
-	val = intel_uncore_read(&i915->uncore,
-				SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
+	if (IS_ALDERLAKE_S(i915))
+		val = intel_uncore_read(&i915->uncore,
+					ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR);
+	else
+		val = intel_uncore_read(&i915->uncore,
+					SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
 
 	switch (val & SKL_DRAM_DDR_TYPE_MASK) {
 	case SKL_DRAM_DDR_TYPE_DDR3:
-- 
2.27.0

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Re: [Intel-gfx] [PATCH 17/22] drm/i915/adl_s: MCHBAR memory info registers are moved

[Lucas De Marchi]

On Fri, Dec 04, 2020 at 05:08:39PM -0800, Aditya Swarup wrote:
>From: Caz Yokoyama <caz.yokoyama@intel.com>
>
>The crwebview indicates on ADL-S that some of our MCHBAR
>registers have moved from their traditional 0x50XX offsets to
>new locations. The meaning and bit layout of the registers
>remain same.
>
>v2: Simplify logic to a single if else chain and fix indents.(Lucas)
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Cc: Jani Nikula <jani.nikula@intel.com>
>Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>Cc: Imre Deak <imre.deak@intel.com>
>Cc: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
>Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>---
> drivers/gpu/drm/i915/i915_reg.h   |  5 +++++
> drivers/gpu/drm/i915/intel_dram.c | 23 +++++++++++++++++------
> 2 files changed, 22 insertions(+), 6 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index ce4ef7fa4000..55e186293fbb 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -10865,6 +10865,8 @@ enum skl_power_gate {
> #define  SKL_DRAM_DDR_TYPE_LPDDR3		(2 << 0)
> #define  SKL_DRAM_DDR_TYPE_LPDDR4		(3 << 0)
>
>+#define ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6048)
>+
> #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
> #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
> #define  SKL_DRAM_S_SHIFT			16
>@@ -10892,6 +10894,9 @@ enum skl_power_gate {
> #define  CNL_DRAM_RANK_3			(0x2 << 9)
> #define  CNL_DRAM_RANK_4			(0x3 << 9)
>
>+#define ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6054)
>+#define ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6058)
>+
> /*
>  * Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
>  * since on HSW we can't write to it using intel_uncore_write.
>diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
>index 4754296a250e..fc9942139ccc 100644
>--- a/drivers/gpu/drm/i915/intel_dram.c
>+++ b/drivers/gpu/drm/i915/intel_dram.c
>@@ -181,17 +181,24 @@ skl_dram_get_channels_info(struct drm_i915_private *i915)
> {
> 	struct dram_info *dram_info = &i915->dram_info;
> 	struct dram_channel_info ch0 = {}, ch1 = {};
>+	i915_reg_t ch0_reg, ch1_reg;
> 	u32 val;
> 	int ret;
>
>-	val = intel_uncore_read(&i915->uncore,
>-				SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
>+	if (IS_ALDERLAKE_S(i915)) {
>+		ch0_reg = ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR;
>+		ch1_reg = ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR;
>+	} else {
>+		ch0_reg = ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR;
>+		ch1_reg = ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR;

this is not right and breaks all the other platforms.

Also this patch conflicts with
https://patchwork.freedesktop.org/series/86092/
and general direction that we should get these values from pcode rather
than keep changing the offset we use to avoid MCHBAR.

Lucas De Marchi
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[Intel-gfx] [PATCH 18/22] drm/i915/adl_s: Add power wells

[Aditya Swarup]

From: Lucas De Marchi <lucas.demarchi@intel.com>

TGL power wells can be re-used for ADL-S with the exception of the fake
power well for TC_COLD, just like DG-1.

Bspec: 53597

Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 8b163d804a41..152cf4a6826d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4632,7 +4632,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
 	 * The enabling order will be from lower to higher indexed wells,
 	 * the disabling order is reversed.
 	 */
-	if (IS_DG1(dev_priv)) {
+	if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) {
 		err = set_power_wells_mask(power_domains, tgl_power_wells,
 					   BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
 	} else if (IS_ROCKETLAKE(dev_priv)) {
-- 
2.27.0

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[Intel-gfx] [PATCH 19/22] drm/i915/adl_s: Re-use TGL GuC/HuC firmware

[Aditya Swarup]

From: Matt Roper <matthew.d.roper@intel.com>

ADL-S, like RKL, uses the same internal device ID for the GuC and HuC as
TGL did, making them all firmware-compatible.  Let's re-use TGL's
firmware for ADL-S.

Bspec: 50668
Cc: John Harrison <John.C.Harrison@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 180c23e2e25e..2d123158df0d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -44,9 +44,11 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
  * List of required GuC and HuC binaries per-platform.
  * Must be ordered based on platform + revid, from newer to older.
  *
- * Note that RKL uses the same firmware as TGL.
+ * Note that RKL and ADL-S have the same GuC/HuC device ID's and use the same
+ * firmware as TGL.
  */
 #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
+	fw_def(ALDERLAKE_S, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl,  7, 5, 0)) \
 	fw_def(ROCKETLAKE,  0, guc_def(tgl, 49, 0, 1), huc_def(tgl,  7, 5, 0)) \
 	fw_def(TIGERLAKE,   0, guc_def(tgl, 49, 0, 1), huc_def(tgl,  7, 5, 0)) \
 	fw_def(JASPERLAKE,  0, guc_def(ehl, 49, 0, 1), huc_def(ehl,  9, 0, 0)) \
-- 
2.27.0

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[Intel-gfx] [PATCH 20/22] drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION

[Aditya Swarup]

From: José Roberto de Souza <jose.souza@intel.com>

- As RKL and ADL-S only have 5 planes, primary and 4 sprites and
  the cursor plane, let's group the handling together under
  HAS_D12_PLANE_MINIMIZATION.
- Also use macro to select pipe irq fault error mask.

BSpec: 49251
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_sprite.c | 2 +-
 drivers/gpu/drm/i915/i915_drv.h             | 3 +++
 drivers/gpu/drm/i915/i915_irq.c             | 2 +-
 drivers/gpu/drm/i915/intel_device_info.c    | 2 +-
 4 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 2d820ff2b236..10176b174e50 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -366,7 +366,7 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 
 static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
 {
-	if (IS_ROCKETLAKE(i915))
+	if (HAS_D12_PLANE_MINIMIZATION(i915))
 		return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
 	else
 		return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 91bd262dd871..1d710d9d8dee 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1796,6 +1796,9 @@ extern const struct i915_rev_steppings adls_revids[];
 #define INTEL_DISPLAY_ENABLED(dev_priv) \
 	(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display)
 
+#define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
+					      IS_ALDERLAKE_S(dev_priv))
+
 static inline bool intel_vtd_active(void)
 {
 #ifdef CONFIG_INTEL_IOMMU
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d1b4893d6c92..bcb0f7c96c65 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2246,7 +2246,7 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
 
 static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
 {
-	if (IS_ROCKETLAKE(dev_priv))
+	if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
 		return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
 	else if (INTEL_GEN(dev_priv) >= 11)
 		return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index da651ef10014..c94a52642f32 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -409,7 +409,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 
 	BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
 
-	if (IS_ROCKETLAKE(dev_priv))
+	if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
 		for_each_pipe(dev_priv, pipe)
 			runtime->num_sprites[pipe] = 4;
 	else if (INTEL_GEN(dev_priv) >= 11)
-- 
2.27.0

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[Intel-gfx] [PATCH 21/22] drm/i915/adl_s: Load DMC

[Aditya Swarup]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

Load DMC on ADL_S v2.01. This is the first offcial
release of DMC for ADL_S.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/display/intel_csr.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
index 67dc64df78a5..db9f219c4b5a 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -40,6 +40,10 @@
 
 #define GEN12_CSR_MAX_FW_SIZE		ICL_CSR_MAX_FW_SIZE
 
+#define ADLS_CSR_PATH			"i915/adls_dmc_ver2_01.bin"
+#define ADLS_CSR_VERSION_REQUIRED	CSR_VERSION(2, 1)
+MODULE_FIRMWARE(ADLS_CSR_PATH);
+
 #define DG1_CSR_PATH			"i915/dg1_dmc_ver2_02.bin"
 #define DG1_CSR_VERSION_REQUIRED	CSR_VERSION(2, 2)
 MODULE_FIRMWARE(DG1_CSR_PATH);
@@ -689,7 +693,11 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
 	 */
 	intel_csr_runtime_pm_get(dev_priv);
 
-	if (IS_DG1(dev_priv)) {
+	if (IS_ALDERLAKE_S(dev_priv)) {
+		csr->fw_path = ADLS_CSR_PATH;
+		csr->required_version = ADLS_CSR_VERSION_REQUIRED;
+		csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+	} else if (IS_DG1(dev_priv)) {
 		csr->fw_path = DG1_CSR_PATH;
 		csr->required_version = DG1_CSR_VERSION_REQUIRED;
 		csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
-- 
2.27.0

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[Intel-gfx] [PATCH 22/22] drm/i915/adl_s: Update memory bandwidth parameters

[Aditya Swarup]

From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>

Just like RKL, the ADL_S platform also has different memory
characteristics from past platforms.  Update the values used
by our memory bandwidth calculations accordingly.

Bspec: 64631
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index bd060404d249..32522ec1ffb9 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -205,6 +205,12 @@ static const struct intel_sa_info rkl_sa_info = {
 	.displayrtids = 128,
 };
 
+static const struct intel_sa_info adls_sa_info = {
+	.deburst = 16,
+	.deprogbwlimit = 38, /* GB/s */
+	.displayrtids = 256,
+};
+
 static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
 {
 	struct intel_qgv_info qi = {};
@@ -317,6 +323,8 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
 
 	if (IS_ROCKETLAKE(dev_priv))
 		icl_get_bw_info(dev_priv, &rkl_sa_info);
+	else if (IS_ALDERLAKE_S(dev_priv))
+		icl_get_bw_info(dev_priv, &adls_sa_info);
 	else if (IS_GEN(dev_priv, 12))
 		icl_get_bw_info(dev_priv, &tgl_sa_info);
 	else if (IS_GEN(dev_priv, 11))
-- 
2.27.0

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Alderlake-S (rev3)

[Patchwork]

== Series Details ==

Series: Introduce Alderlake-S (rev3)
URL   : https://patchwork.freedesktop.org/series/82917/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
d90e9bb9cd0e drm/i915/tgl: Fix REVID macros for TGL to fetch correct stepping
deb53d194dbb drm/i915/tgl: Add bound checks and simplify TGL REVID macros
75d8d0e1ed7d drm/i915/adl_s: Add ADL-S platform info and PCI ids
-:239: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#239: FILE: drivers/gpu/drm/i915/i915_drv.h:1646:
+#define IS_ADLS_DISP_REVID(p, since, until) \
+	(IS_ALDERLAKE_S(p) && \
+	 tgl_revids_get(p)->disp_stepping >= (since) && \
+	 tgl_revids_get(p)->disp_stepping <= (until))

-:244: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#244: FILE: drivers/gpu/drm/i915/i915_drv.h:1651:
+#define IS_ADLS_GT_REVID(p, since, until) \
+	(IS_ALDERLAKE_S(p) && \
+	 tgl_revids_get(p)->gt_stepping >= (since) && \
+	 tgl_revids_get(p)->gt_stepping <= (until))

-:329: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#329: FILE: include/drm/i915_pciids.h:638:
+#define INTEL_ADLS_IDS(info) \
+	INTEL_VGA_DEVICE(0x4680, info), \
+	INTEL_VGA_DEVICE(0x4681, info), \
+	INTEL_VGA_DEVICE(0x4682, info), \
+	INTEL_VGA_DEVICE(0x4683, info), \
+	INTEL_VGA_DEVICE(0x4690, info), \
+	INTEL_VGA_DEVICE(0x4691, info), \
+	INTEL_VGA_DEVICE(0x4692, info), \
+	INTEL_VGA_DEVICE(0x4693, info), \
+	INTEL_VGA_DEVICE(0x4698, info), \
+	INTEL_VGA_DEVICE(0x4699, info)

-:329: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#329: FILE: include/drm/i915_pciids.h:638:
+#define INTEL_ADLS_IDS(info) \
+	INTEL_VGA_DEVICE(0x4680, info), \
+	INTEL_VGA_DEVICE(0x4681, info), \
+	INTEL_VGA_DEVICE(0x4682, info), \
+	INTEL_VGA_DEVICE(0x4683, info), \
+	INTEL_VGA_DEVICE(0x4690, info), \
+	INTEL_VGA_DEVICE(0x4691, info), \
+	INTEL_VGA_DEVICE(0x4692, info), \
+	INTEL_VGA_DEVICE(0x4693, info), \
+	INTEL_VGA_DEVICE(0x4698, info), \
+	INTEL_VGA_DEVICE(0x4699, info)

total: 1 errors, 0 warnings, 3 checks, 241 lines checked
150a0b30604f x86/gpu: add ADL_S stolen memory support
130950398722 drm/i915/adl_s: Add PCH support
ca0a9e7d58c5 drm/i915/adl_s: Add Interrupt Support
d1bd8b907825 drm/i915/adl_s: Add PHYs for Alderlake S
114e7efe0b1a drm/i915/adl_s: Configure DPLL for ADL-S
2591c7399649 drm/i915/adl_s: Configure Port clock registers for ADL-S
8982e3cd419c drm/i915/adl_s: Initialize display for ADL-S
241ce3db14df drm/i915/adl_s: Add adl-s ddc pin mapping
fbd148aa96fd drm/i915/adl_s: Add vbt port and aux channel settings for adls
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#10: 
- ADL-S driver internal mapping uses PORT D, E, F, G for Combo phy B, C, D and E.

total: 0 errors, 1 warnings, 0 checks, 81 lines checked
b3310f98c834 drm/i915/adl_s: Update combo PHY master/slave relationships
cc24f634335a drm/i915/adl_s: Update PHY_MISC programming
b2ac95cad0d1 drm/i915/adl_s: Add display WAs for ADL-S
ea3c5de02c7f drm/i915/adl_s: Add GT and CTX WAs for ADL-S
7363cd5f8d3f drm/i915/adl_s: MCHBAR memory info registers are moved
3c42824c88e1 drm/i915/adl_s: Add power wells
e234d322b07f drm/i915/adl_s: Re-use TGL GuC/HuC firmware
75bb40138464 drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION
-:45: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#45: FILE: drivers/gpu/drm/i915/i915_drv.h:1799:
+#define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
+					      IS_ALDERLAKE_S(dev_priv))

total: 0 errors, 0 warnings, 1 checks, 33 lines checked
fceb5bcdc2e0 drm/i915/adl_s: Load DMC
4550beb694af drm/i915/adl_s: Update memory bandwidth parameters


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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce Alderlake-S (rev3)

[Patchwork]

== Series Details ==

Series: Introduce Alderlake-S (rev3)
URL   : https://patchwork.freedesktop.org/series/82917/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:    expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:    expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:    expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:    expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:    expected unsigned int [usertype] *s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1447:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1501:15: warning: memset with byte count of 16777216
+./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for Introduce Alderlake-S (rev3)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 4717 bytes --]

== Series Details ==

Series: Introduce Alderlake-S (rev3)
URL   : https://patchwork.freedesktop.org/series/82917/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9445 -> Patchwork_19067
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/index.html

New tests
---------

  New tests have been introduced between CI_DRM_9445 and Patchwork_19067:

### New CI tests (1) ###

  * boot:
    - Statuses : 1 fail(s) 38 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_19067 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_render_linear_blits@basic:
    - fi-tgl-y:           [PASS][1] -> [DMESG-WARN][2] ([i915#402])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/fi-tgl-y/igt@gem_render_linear_blits@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/fi-tgl-y/igt@gem_render_linear_blits@basic.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-skl-6700k2:      [PASS][3] -> [INCOMPLETE][4] ([i915#146] / [i915#2405])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/fi-skl-6700k2/igt@kms_chamelium@common-hpd-after-suspend.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/fi-skl-6700k2/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@prime_vgem@basic-fence-flip:
    - fi-cml-s:           [PASS][5] -> [INCOMPLETE][6] ([i915#2377])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/fi-cml-s/igt@prime_vgem@basic-fence-flip.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/fi-cml-s/igt@prime_vgem@basic-fence-flip.html

  
#### Possible fixes ####

  * igt@gem_basic@create-fd-close:
    - fi-tgl-y:           [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/fi-tgl-y/igt@gem_basic@create-fd-close.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/fi-tgl-y/igt@gem_basic@create-fd-close.html

  * igt@gem_exec_suspend@basic-s3:
    - fi-snb-2600:        [INCOMPLETE][9] -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/fi-snb-2600/igt@gem_exec_suspend@basic-s3.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/fi-snb-2600/igt@gem_exec_suspend@basic-s3.html

  
  [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
  [i915#2377]: https://gitlab.freedesktop.org/drm/intel/issues/2377
  [i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (43 -> 39)
------------------------------

  Missing    (4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u 


Build changes
-------------

  * Linux: CI_DRM_9445 -> Patchwork_19067

  CI-20190529: 20190529
  CI_DRM_9445: 2e3d245730b4ce190e96d9731a2a6f06bb0ec57a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5881: 10d4e2e9177eb747b9f2ab9122e3ab60e91654fb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19067: 4550beb694af36a8cea5bfd14dc1353644abd1ed @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

4550beb694af drm/i915/adl_s: Update memory bandwidth parameters
fceb5bcdc2e0 drm/i915/adl_s: Load DMC
75bb40138464 drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION
e234d322b07f drm/i915/adl_s: Re-use TGL GuC/HuC firmware
3c42824c88e1 drm/i915/adl_s: Add power wells
7363cd5f8d3f drm/i915/adl_s: MCHBAR memory info registers are moved
ea3c5de02c7f drm/i915/adl_s: Add GT and CTX WAs for ADL-S
b2ac95cad0d1 drm/i915/adl_s: Add display WAs for ADL-S
cc24f634335a drm/i915/adl_s: Update PHY_MISC programming
b3310f98c834 drm/i915/adl_s: Update combo PHY master/slave relationships
fbd148aa96fd drm/i915/adl_s: Add vbt port and aux channel settings for adls
241ce3db14df drm/i915/adl_s: Add adl-s ddc pin mapping
8982e3cd419c drm/i915/adl_s: Initialize display for ADL-S
2591c7399649 drm/i915/adl_s: Configure Port clock registers for ADL-S
114e7efe0b1a drm/i915/adl_s: Configure DPLL for ADL-S
d1bd8b907825 drm/i915/adl_s: Add PHYs for Alderlake S
ca0a9e7d58c5 drm/i915/adl_s: Add Interrupt Support
130950398722 drm/i915/adl_s: Add PCH support
150a0b30604f x86/gpu: add ADL_S stolen memory support
75d8d0e1ed7d drm/i915/adl_s: Add ADL-S platform info and PCI ids
deb53d194dbb drm/i915/tgl: Add bound checks and simplify TGL REVID macros
d90e9bb9cd0e drm/i915/tgl: Fix REVID macros for TGL to fetch correct stepping

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/index.html

[-- Attachment #1.2: Type: text/html, Size: 5663 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for Introduce Alderlake-S (rev3)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 12324 bytes --]

== Series Details ==

Series: Introduce Alderlake-S (rev3)
URL   : https://patchwork.freedesktop.org/series/82917/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9445_full -> Patchwork_19067_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

New tests
---------

  New tests have been introduced between CI_DRM_9445_full and Patchwork_19067_full:

### New CI tests (1) ###

  * boot:
    - Statuses : 173 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_19067_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_softpin@noreloc-s3:
    - shard-apl:          [PASS][1] -> [INCOMPLETE][2] ([i915#2405])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-apl4/igt@gem_softpin@noreloc-s3.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-apl6/igt@gem_softpin@noreloc-s3.html

  * igt@kms_async_flips@alternate-sync-async-flip:
    - shard-skl:          [PASS][3] -> [FAIL][4] ([i915#2521])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-skl2/igt@kms_async_flips@alternate-sync-async-flip.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-skl5/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen:
    - shard-skl:          [PASS][5] -> [FAIL][6] ([i915#54]) +2 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-skl5/igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-skl4/igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen.html

  * igt@kms_flip@flip-vs-suspend@a-dp1:
    - shard-kbl:          [PASS][7] -> [INCOMPLETE][8] ([i915#155] / [i915#180])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-kbl2/igt@kms_flip@flip-vs-suspend@a-dp1.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-kbl3/igt@kms_flip@flip-vs-suspend@a-dp1.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
    - shard-apl:          [PASS][9] -> [FAIL][10] ([i915#49])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-apl7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-apl3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
    - shard-glk:          [PASS][11] -> [FAIL][12] ([i915#49])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-glk2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-glk9/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
    - shard-kbl:          [PASS][13] -> [FAIL][14] ([i915#49])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-skl:          [PASS][15] -> [FAIL][16] ([i915#1188])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-skl4/igt@kms_hdr@bpc-switch-suspend.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-skl5/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265]) +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_primary_mmap_gtt:
    - shard-iclb:         [PASS][19] -> [SKIP][20] ([fdo#109441])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-iclb3/igt@kms_psr@psr2_primary_mmap_gtt.html

  * igt@perf@polling-parameterized:
    - shard-iclb:         [PASS][21] -> [FAIL][22] ([i915#1542])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-iclb1/igt@perf@polling-parameterized.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-iclb3/igt@perf@polling-parameterized.html

  
#### Possible fixes ####

  * {igt@gem_ctx_exec@basic-close-race}:
    - shard-skl:          [INCOMPLETE][23] -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-skl1/igt@gem_ctx_exec@basic-close-race.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-skl3/igt@gem_ctx_exec@basic-close-race.html

  * igt@gem_exec_whisper@basic-contexts-priority:
    - shard-iclb:         [INCOMPLETE][25] -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-iclb5/igt@gem_exec_whisper@basic-contexts-priority.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-iclb5/igt@gem_exec_whisper@basic-contexts-priority.html

  * igt@gem_exec_whisper@basic-fds-priority:
    - shard-glk:          [DMESG-WARN][27] ([i915#118] / [i915#95]) -> [PASS][28] +1 similar issue
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-glk8/igt@gem_exec_whisper@basic-fds-priority.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-glk1/igt@gem_exec_whisper@basic-fds-priority.html

  * igt@gem_mmap_offset@clear:
    - shard-skl:          [DMESG-WARN][29] ([i915#1982]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-skl9/igt@gem_mmap_offset@clear.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-skl1/igt@gem_mmap_offset@clear.html

  * igt@kms_cursor_crc@pipe-b-cursor-256x256-offscreen:
    - shard-skl:          [FAIL][31] ([i915#54]) -> [PASS][32] +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-skl2/igt@kms_cursor_crc@pipe-b-cursor-256x256-offscreen.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-skl5/igt@kms_cursor_crc@pipe-b-cursor-256x256-offscreen.html

  * igt@kms_dp_aux_dev:
    - shard-iclb:         [DMESG-WARN][33] ([i915#262]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-iclb7/igt@kms_dp_aux_dev.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-iclb1/igt@kms_dp_aux_dev.html

  * igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1:
    - shard-glk:          [FAIL][35] ([i915#79]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-glk2/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-glk6/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
    - shard-skl:          [FAIL][37] ([i915#2122]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-skl5/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt:
    - shard-glk:          [FAIL][39] ([i915#49]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-glk9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-glk4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [FAIL][41] ([i915#1188]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-skl8/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_plane_lowres@pipe-b-tiling-yf:
    - shard-iclb:         [FAIL][43] ([i915#899]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-iclb6/igt@kms_plane_lowres@pipe-b-tiling-yf.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-iclb7/igt@kms_plane_lowres@pipe-b-tiling-yf.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-iclb:         [SKIP][45] ([fdo#109441]) -> [PASS][46] +1 similar issue
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-iclb1/igt@kms_psr@psr2_cursor_mmap_cpu.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html

  
#### Warnings ####

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-iclb:         [WARN][47] ([i915#2684]) -> [WARN][48] ([i915#1804] / [i915#2684])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-iclb3/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
    - shard-tglb:         [INCOMPLETE][49] ([i915#1602] / [i915#2411] / [i915#456]) -> [INCOMPLETE][50] ([i915#1436] / [i915#1602] / [i915#1887] / [i915#2411] / [i915#456])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-tglb8/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-tglb5/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
  [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
  [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
  [i915#1887]: https://gitlab.freedesktop.org/drm/intel/issues/1887
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
  [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
  [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_9445 -> Patchwork_19067

  CI-20190529: 20190529
  CI_DRM_9445: 2e3d245730b4ce190e96d9731a2a6f06bb0ec57a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5881: 10d4e2e9177eb747b9f2ab9122e3ab60e91654fb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19067: 4550beb694af36a8cea5bfd14dc1353644abd1ed @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/index.html

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Re: [Intel-gfx] [PATCH 00/22] Introduce Alderlake-S

[Jani Nikula]

On Fri, 04 Dec 2020, Aditya Swarup <aditya.swarup@intel.com> wrote:
> Rev 3 with all the comments addressed from Rev 2:
> https://patchwork.freedesktop.org/series/82917/

Please rebase and resend the series, and let's get this reviewed and
merged to topic/adl-s-enabling.

BR,
Jani.


>
> Aditya Swarup (9):
>   drm/i915/tgl: Fix REVID macros for TGL to fetch correct stepping
>   drm/i915/tgl: Add bound checks and simplify TGL REVID macros
>   drm/i915/adl_s: Configure DPLL for ADL-S
>   drm/i915/adl_s: Configure Port clock registers for ADL-S
>   drm/i915/adl_s: Initialize display for ADL-S
>   drm/i915/adl_s: Add adl-s ddc pin mapping
>   drm/i915/adl_s: Add vbt port and aux channel settings for adls
>   drm/i915/adl_s: Add display WAs for ADL-S
>   drm/i915/adl_s: Add GT and CTX WAs for ADL-S
>
> Anusha Srivatsa (4):
>   drm/i915/adl_s: Add PCH support
>   drm/i915/adl_s: Add Interrupt Support
>   drm/i915/adl_s: Add PHYs for Alderlake S
>   drm/i915/adl_s: Load DMC
>
> Caz Yokoyama (3):
>   drm/i915/adl_s: Add ADL-S platform info and PCI ids
>   x86/gpu: add ADL_S stolen memory support
>   drm/i915/adl_s: MCHBAR memory info registers are moved
>
> José Roberto de Souza (1):
>   drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION
>
> Lucas De Marchi (1):
>   drm/i915/adl_s: Add power wells
>
> Matt Roper (3):
>   drm/i915/adl_s: Update combo PHY master/slave relationships
>   drm/i915/adl_s: Update PHY_MISC programming
>   drm/i915/adl_s: Re-use TGL GuC/HuC firmware
>
> Tejas Upadhyay (1):
>   drm/i915/adl_s: Update memory bandwidth parameters
>
>  arch/x86/kernel/early-quirks.c                |   1 +
>  drivers/gpu/drm/i915/display/intel_bios.c     |  70 +++++++++--
>  drivers/gpu/drm/i915/display/intel_bw.c       |   8 ++
>  .../gpu/drm/i915/display/intel_combo_phy.c    |  23 +++-
>  drivers/gpu/drm/i915/display/intel_csr.c      |  10 +-
>  drivers/gpu/drm/i915/display/intel_ddi.c      |  64 ++++++----
>  drivers/gpu/drm/i915/display/intel_display.c  |  36 +++++-
>  .../drm/i915/display/intel_display_power.c    |  11 +-
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  38 +++++-
>  drivers/gpu/drm/i915/display/intel_hdmi.c     |  20 ++-
>  drivers/gpu/drm/i915/display/intel_psr.c      |   4 +-
>  drivers/gpu/drm/i915/display/intel_sprite.c   |   8 +-
>  drivers/gpu/drm/i915/display/intel_vbt_defs.h |   4 +
>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 119 ++++++++++++------
>  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c      |   4 +-
>  drivers/gpu/drm/i915/i915_drv.h               |  72 ++++++++---
>  drivers/gpu/drm/i915/i915_irq.c               |   5 +-
>  drivers/gpu/drm/i915/i915_pci.c               |  13 ++
>  drivers/gpu/drm/i915/i915_reg.h               |  54 +++++++-
>  drivers/gpu/drm/i915/intel_device_info.c      |   9 +-
>  drivers/gpu/drm/i915/intel_device_info.h      |   1 +
>  drivers/gpu/drm/i915/intel_dram.c             |  23 +++-
>  drivers/gpu/drm/i915/intel_pch.c              |   8 +-
>  drivers/gpu/drm/i915/intel_pch.h              |   3 +
>  drivers/gpu/drm/i915/intel_pm.c               |   2 +-
>  include/drm/i915_pciids.h                     |  13 ++
>  26 files changed, 489 insertions(+), 134 deletions(-)

-- 
Jani Nikula, Intel Open Source Graphics Center
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