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From: Andrew Lunn <andrew@lunn.ch>
To: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Steen Hegelund <steen.hegelund@microchip.com>,
	"David S. Miller" <davem@davemloft.net>,
	Jakub Kicinski <kuba@kernel.org>,
	Russell King <linux@armlinux.org.uk>,
	Lars Povlsen <lars.povlsen@microchip.com>,
	Bjarni Jonasson <bjarni.jonasson@microchip.com>,
	Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>,
	Madalin Bucur <madalin.bucur@oss.nxp.com>,
	Nicolas Ferre <nicolas.ferre@microchip.com>,
	Mark Einon <mark.einon@gmail.com>,
	Masahiro Yamada <masahiroy@kernel.org>,
	Arnd Bergmann <arnd@arndb.de>,
	netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [RFC PATCH v2 3/8] net: sparx5: add hostmode with phylink support
Date: Wed, 23 Dec 2020 22:05:21 +0100	[thread overview]
Message-ID: <20201223210521.GB3253993@lunn.ch> (raw)
In-Reply-To: <20201223205852.GA4138276@piout.net>

On Wed, Dec 23, 2020 at 09:58:52PM +0100, Alexandre Belloni wrote:
> On 22/12/2020 15:41:41+0100, Andrew Lunn wrote:
> > > Yes the register based injection/extration is not going to be fast, but
> > > the FDMA and its driver is being sent later as separate series to keep
> > > the size of this review down.
> > 
> > FDMA?
> > 
> > I need a bit more background here, just to make use this should be a
> > pure switchdev driver and not a DSA driver.
> > 
> 
> I don't think this should be a DSA driver. As for Ocelot, the CPU
> port is not a MAC and in that use case, this would be like a top of the
> rack switch with traffic going to the CPU port being mostly used for
> managmement (dhcp, stp, etc...) as opposed to being used to forward
> traffic to another interface, like WAN or wifi.
> 
> However, I would think there will be cases where the internal CPU is not
> use and instead use ths switch in a DSA setting, very much like what is
> done for Felix with regards to Ocelot.

From what i have heard so far, it does seem like a pure switchdev
driver is correct. So long as FDMA is not a standalone Ethernet
driver, but just a DMA engine incorporated into this driver, the
architecture looks correct.

I was asking because from the information that was available, it was
impossible to say what the correct architecture should be.

     Andrew

WARNING: multiple messages have this Message-ID (diff)
From: Andrew Lunn <andrew@lunn.ch>
To: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Bjarni Jonasson <bjarni.jonasson@microchip.com>,
	linux-kernel@vger.kernel.org, Arnd Bergmann <arnd@arndb.de>,
	Madalin Bucur <madalin.bucur@oss.nxp.com>,
	netdev@vger.kernel.org,
	Steen Hegelund <steen.hegelund@microchip.com>,
	Russell King <linux@armlinux.org.uk>,
	Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>,
	linux-arm-kernel@lists.infradead.org,
	Mark Einon <mark.einon@gmail.com>,
	Jakub Kicinski <kuba@kernel.org>,
	Masahiro Yamada <masahiroy@kernel.org>,
	"David S. Miller" <davem@davemloft.net>,
	Lars Povlsen <lars.povlsen@microchip.com>
Subject: Re: [RFC PATCH v2 3/8] net: sparx5: add hostmode with phylink support
Date: Wed, 23 Dec 2020 22:05:21 +0100	[thread overview]
Message-ID: <20201223210521.GB3253993@lunn.ch> (raw)
In-Reply-To: <20201223205852.GA4138276@piout.net>

On Wed, Dec 23, 2020 at 09:58:52PM +0100, Alexandre Belloni wrote:
> On 22/12/2020 15:41:41+0100, Andrew Lunn wrote:
> > > Yes the register based injection/extration is not going to be fast, but
> > > the FDMA and its driver is being sent later as separate series to keep
> > > the size of this review down.
> > 
> > FDMA?
> > 
> > I need a bit more background here, just to make use this should be a
> > pure switchdev driver and not a DSA driver.
> > 
> 
> I don't think this should be a DSA driver. As for Ocelot, the CPU
> port is not a MAC and in that use case, this would be like a top of the
> rack switch with traffic going to the CPU port being mostly used for
> managmement (dhcp, stp, etc...) as opposed to being used to forward
> traffic to another interface, like WAN or wifi.
> 
> However, I would think there will be cases where the internal CPU is not
> use and instead use ths switch in a DSA setting, very much like what is
> done for Felix with regards to Ocelot.

From what i have heard so far, it does seem like a pure switchdev
driver is correct. So long as FDMA is not a standalone Ethernet
driver, but just a DMA engine incorporated into this driver, the
architecture looks correct.

I was asking because from the information that was available, it was
impossible to say what the correct architecture should be.

     Andrew

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  reply	other threads:[~2020-12-23 21:06 UTC|newest]

Thread overview: 75+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-17  7:51 [RFC PATCH v2 0/8] Adding the Sparx5 Switch Driver Steen Hegelund
2020-12-17  7:51 ` Steen Hegelund
2020-12-17  7:51 ` [RFC PATCH v2 1/8] dt-bindings: net: sparx5: Add sparx5-switch bindings Steen Hegelund
2020-12-17  7:51   ` Steen Hegelund
2020-12-19 17:54   ` Andrew Lunn
2020-12-19 17:54     ` Andrew Lunn
2020-12-21  0:55   ` Florian Fainelli
2020-12-21  0:55     ` Florian Fainelli
2020-12-21 10:00     ` Steen Hegelund
2020-12-21 10:00       ` Steen Hegelund
2020-12-21 21:40   ` Rob Herring
2020-12-21 21:40     ` Rob Herring
2020-12-22  7:30     ` Steen Hegelund
2020-12-22  7:30       ` Steen Hegelund
2020-12-17  7:51 ` [RFC PATCH v2 2/8] net: sparx5: add the basic sparx5 driver Steen Hegelund
2020-12-19 19:11   ` Andrew Lunn
2020-12-19 19:11     ` Andrew Lunn
2020-12-22 13:50     ` Steen Hegelund
2020-12-22 13:50       ` Steen Hegelund
2020-12-22 15:01       ` Andrew Lunn
2020-12-22 15:01         ` Andrew Lunn
2020-12-22 16:56         ` Alexandre Belloni
2020-12-22 16:56           ` Alexandre Belloni
2020-12-23  9:03           ` Lars Povlsen
2020-12-23  9:03             ` Lars Povlsen
2020-12-23  8:52         ` Steen Hegelund
2020-12-23  8:52           ` Steen Hegelund
2020-12-17  7:51 ` [RFC PATCH v2 3/8] net: sparx5: add hostmode with phylink support Steen Hegelund
2020-12-17  7:51   ` Steen Hegelund
2020-12-19 19:51   ` Andrew Lunn
2020-12-19 19:51     ` Andrew Lunn
2020-12-22  9:46     ` Steen Hegelund
2020-12-22  9:46       ` Steen Hegelund
2020-12-22 14:41       ` Andrew Lunn
2020-12-22 14:41         ` Andrew Lunn
2020-12-23 13:29         ` Steen Hegelund
2020-12-23 13:29           ` Steen Hegelund
2020-12-23 20:58         ` Alexandre Belloni
2020-12-23 20:58           ` Alexandre Belloni
2020-12-23 21:05           ` Andrew Lunn [this message]
2020-12-23 21:05             ` Andrew Lunn
2020-12-17  7:51 ` [RFC PATCH v2 4/8] net: sparx5: add port module support Steen Hegelund
2020-12-17  7:51   ` Steen Hegelund
2020-12-20 23:35   ` Andrew Lunn
2020-12-20 23:35     ` Andrew Lunn
2020-12-22 14:55     ` Bjarni Jonasson
2020-12-22 14:55       ` Bjarni Jonasson
2020-12-22 15:08       ` Andrew Lunn
2020-12-22 15:08         ` Andrew Lunn
2020-12-17  7:51 ` [RFC PATCH v2 5/8] net: sparx5: add switching, vlan and mactable support Steen Hegelund
2020-12-17  7:51   ` Steen Hegelund
2020-12-21  0:25   ` Andrew Lunn
2020-12-21  0:25     ` Andrew Lunn
2020-12-23 13:54     ` Steen Hegelund
2020-12-23 13:54       ` Steen Hegelund
2020-12-17  7:51 ` [RFC PATCH v2 6/8] net: sparx5: add calendar bandwidth allocation support Steen Hegelund
2020-12-17  7:51   ` Steen Hegelund
2020-12-17  7:51 ` [RFC PATCH v2 7/8] net: sparx5: add ethtool configuration and statistics support Steen Hegelund
2020-12-17  7:51   ` Steen Hegelund
2020-12-19 23:31   ` Andrew Lunn
2020-12-19 23:31     ` Andrew Lunn
2020-12-17  7:51 ` [RFC PATCH v2 8/8] arm64: dts: sparx5: Add the Sparx5 switch node Steen Hegelund
2020-12-17  7:51   ` Steen Hegelund
2020-12-19 20:24   ` Andrew Lunn
2020-12-19 20:24     ` Andrew Lunn
2020-12-23 14:31     ` Steen Hegelund
2020-12-23 14:31       ` Steen Hegelund
2020-12-23 15:49       ` Andrew Lunn
2020-12-23 15:49         ` Andrew Lunn
2020-12-21  0:58 ` [RFC PATCH v2 0/8] Adding the Sparx5 Switch Driver Florian Fainelli
2020-12-21  0:58   ` Florian Fainelli
2020-12-21 14:31   ` Steen Hegelund
2020-12-21 14:31     ` Steen Hegelund
2020-12-22 11:29   ` Lars Povlsen
2020-12-22 11:29     ` Lars Povlsen

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