All of lore.kernel.org
 help / color / mirror / Atom feed
From: Mark Rutland <mark.rutland@arm.com>
To: Vincenzo Frascino <vincenzo.frascino@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Branislav Rankov <Branislav.Rankov@arm.com>,
	Marco Elver <elver@google.com>,
	Andrey Konovalov <andreyknvl@google.com>,
	Evgenii Stepanov <eugenis@google.com>,
	linux-kernel@vger.kernel.org, kasan-dev@googlegroups.com,
	Alexander Potapenko <glider@google.com>,
	linux-arm-kernel@lists.infradead.org,
	Andrey Ryabinin <aryabinin@virtuozzo.com>,
	Will Deacon <will@kernel.org>, Dmitry Vyukov <dvyukov@google.com>
Subject: Re: [PATCH v3 3/4] arm64: mte: Enable async tag check fault
Date: Mon, 18 Jan 2021 14:14:29 +0000	[thread overview]
Message-ID: <20210118141429.GC31263@C02TD0UTHF1T.local> (raw)
In-Reply-To: <c076b1cc-8ce5-91a0-9957-7dcd78026b18@arm.com>

On Mon, Jan 18, 2021 at 01:37:35PM +0000, Vincenzo Frascino wrote:
> On 1/18/21 12:57 PM, Catalin Marinas wrote:

> >> +	if (tfsr_el1 & SYS_TFSR_EL1_TF1) {
> >> +		write_sysreg_s(0, SYS_TFSR_EL1);
> >> +		isb();
> > While in general we use ISB after a sysreg update, I haven't convinced
> > myself it's needed here. There's no side-effect to updating this reg and
> > a subsequent TFSR access should see the new value.
> 
> Why there is no side-effect?

Catalin's saying that the value of TFSR_EL1 doesn't affect anything
other than a read of TFSR_EL1, i.e. there are no indirect reads of
TFSR_EL1 where the value has an effect, so there are no side-effects.

Looking at the ARM ARM, no synchronization is requires from a direct
write to an indirect write (per ARM DDI 0487F.c table D13-1), so I agree
that we don't need the ISB here so long as there are no indirect reads.

Are you aware of cases where the TFSR_EL1 value is read other than by an
MRS? e.g. are there any cases where checks are elided if TF1 is set? If
so, we may need the ISB to order the direct write against subsequent
indirect reads.

Thanks,
Mark.

WARNING: multiple messages have this Message-ID (diff)
From: Mark Rutland <mark.rutland@arm.com>
To: Vincenzo Frascino <vincenzo.frascino@arm.com>
Cc: Branislav Rankov <Branislav.Rankov@arm.com>,
	Will Deacon <will@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	linux-kernel@vger.kernel.org, kasan-dev@googlegroups.com,
	Alexander Potapenko <glider@google.com>,
	linux-arm-kernel@lists.infradead.org,
	Andrey Konovalov <andreyknvl@google.com>,
	Dmitry Vyukov <dvyukov@google.com>,
	Andrey Ryabinin <aryabinin@virtuozzo.com>,
	Marco Elver <elver@google.com>,
	Evgenii Stepanov <eugenis@google.com>
Subject: Re: [PATCH v3 3/4] arm64: mte: Enable async tag check fault
Date: Mon, 18 Jan 2021 14:14:29 +0000	[thread overview]
Message-ID: <20210118141429.GC31263@C02TD0UTHF1T.local> (raw)
In-Reply-To: <c076b1cc-8ce5-91a0-9957-7dcd78026b18@arm.com>

On Mon, Jan 18, 2021 at 01:37:35PM +0000, Vincenzo Frascino wrote:
> On 1/18/21 12:57 PM, Catalin Marinas wrote:

> >> +	if (tfsr_el1 & SYS_TFSR_EL1_TF1) {
> >> +		write_sysreg_s(0, SYS_TFSR_EL1);
> >> +		isb();
> > While in general we use ISB after a sysreg update, I haven't convinced
> > myself it's needed here. There's no side-effect to updating this reg and
> > a subsequent TFSR access should see the new value.
> 
> Why there is no side-effect?

Catalin's saying that the value of TFSR_EL1 doesn't affect anything
other than a read of TFSR_EL1, i.e. there are no indirect reads of
TFSR_EL1 where the value has an effect, so there are no side-effects.

Looking at the ARM ARM, no synchronization is requires from a direct
write to an indirect write (per ARM DDI 0487F.c table D13-1), so I agree
that we don't need the ISB here so long as there are no indirect reads.

Are you aware of cases where the TFSR_EL1 value is read other than by an
MRS? e.g. are there any cases where checks are elided if TF1 is set? If
so, we may need the ISB to order the direct write against subsequent
indirect reads.

Thanks,
Mark.

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2021-01-18 14:17 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-15 12:00 [PATCH v3 0/4] arm64: ARMv8.5-A: MTE: Add async mode support Vincenzo Frascino
2021-01-15 12:00 ` Vincenzo Frascino
2021-01-15 12:00 ` [PATCH v3 1/4] kasan, arm64: Add KASAN light mode Vincenzo Frascino
2021-01-15 12:00   ` Vincenzo Frascino
2021-01-15 15:08   ` Mark Rutland
2021-01-15 15:08     ` Mark Rutland
2021-01-16 13:47     ` Vincenzo Frascino
2021-01-16 13:47       ` Vincenzo Frascino
2021-01-16 14:09       ` Andrey Konovalov
2021-01-16 14:09         ` Andrey Konovalov
2021-01-18 10:24       ` Mark Rutland
2021-01-18 10:24         ` Mark Rutland
2021-01-15 18:59   ` Andrey Konovalov
2021-01-15 18:59     ` Andrey Konovalov
2021-01-16 13:40     ` Vincenzo Frascino
2021-01-16 13:40       ` Vincenzo Frascino
2021-01-16 13:59       ` Andrey Konovalov
2021-01-16 13:59         ` Andrey Konovalov
2021-01-16 14:06         ` Vincenzo Frascino
2021-01-16 14:06           ` Vincenzo Frascino
2021-01-15 12:00 ` [PATCH v3 2/4] arm64: mte: Add asynchronous mode support Vincenzo Frascino
2021-01-15 12:00   ` Vincenzo Frascino
2021-01-15 15:13   ` Mark Rutland
2021-01-15 15:13     ` Mark Rutland
2021-01-16 13:49     ` Vincenzo Frascino
2021-01-16 13:49       ` Vincenzo Frascino
2021-01-15 12:00 ` [PATCH v3 3/4] arm64: mte: Enable async tag check fault Vincenzo Frascino
2021-01-15 12:00   ` Vincenzo Frascino
2021-01-15 15:37   ` Mark Rutland
2021-01-15 15:37     ` Mark Rutland
2021-01-18 12:57   ` Catalin Marinas
2021-01-18 12:57     ` Catalin Marinas
2021-01-18 13:37     ` Vincenzo Frascino
2021-01-18 13:37       ` Vincenzo Frascino
2021-01-18 14:14       ` Mark Rutland [this message]
2021-01-18 14:14         ` Mark Rutland
2021-01-18 14:48         ` Vincenzo Frascino
2021-01-18 14:48           ` Vincenzo Frascino
2021-01-18 15:39           ` Vincenzo Frascino
2021-01-18 15:39             ` Vincenzo Frascino
2021-01-18 15:40       ` Vincenzo Frascino
2021-01-18 15:40         ` Vincenzo Frascino
2021-01-15 12:00 ` [PATCH v3 4/4] arm64: mte: Optimize mte_assign_mem_tag_range() Vincenzo Frascino
2021-01-15 12:00   ` Vincenzo Frascino
2021-01-15 15:45   ` Mark Rutland
2021-01-15 15:45     ` Mark Rutland
2021-01-16 14:22     ` Vincenzo Frascino
2021-01-16 14:22       ` Vincenzo Frascino
2021-01-17 12:27       ` Vincenzo Frascino
2021-01-17 12:27         ` Vincenzo Frascino
2021-01-18 10:41         ` Mark Rutland
2021-01-18 10:41           ` Mark Rutland
2021-01-18 11:00           ` Vincenzo Frascino
2021-01-18 11:00             ` Vincenzo Frascino

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210118141429.GC31263@C02TD0UTHF1T.local \
    --to=mark.rutland@arm.com \
    --cc=Branislav.Rankov@arm.com \
    --cc=andreyknvl@google.com \
    --cc=aryabinin@virtuozzo.com \
    --cc=catalin.marinas@arm.com \
    --cc=dvyukov@google.com \
    --cc=elver@google.com \
    --cc=eugenis@google.com \
    --cc=glider@google.com \
    --cc=kasan-dev@googlegroups.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=vincenzo.frascino@arm.com \
    --cc=will@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.