From: Bjorn Helgaas <helgaas@kernel.org> To: Vinicius Costa Gomes <vinicius.gomes@intel.com> Cc: intel-wired-lan@lists.osuosl.org, sasha.neftin@intel.com, anthony.l.nguyen@intel.com, linux-pci@vger.kernel.org, bhelgaas@google.com, netdev@vger.kernel.org, mlichvar@redhat.com, richardcochran@gmail.com Subject: Re: [PATCH next-queue v3 3/3] igc: Add support for PTP getcrosststamp() Date: Tue, 23 Mar 2021 14:39:23 -0500 [thread overview] Message-ID: <20210323193923.GA597480@bjorn-Precision-5520> (raw) In-Reply-To: <20210322161822.1546454-4-vinicius.gomes@intel.com> On Mon, Mar 22, 2021 at 09:18:22AM -0700, Vinicius Costa Gomes wrote: > i225 has support for PCIe PTM, which allows us to implement support > for the PTP_SYS_OFFSET_PRECISE ioctl(), implemented in the driver via > the getcrosststamp() function. > +static bool igc_is_ptm_supported(struct igc_adapter *adapter) > +{ > +#if IS_ENABLED(CONFIG_X86_TSC) && IS_ENABLED(CONFIG_PCIE_PTM) > + return adapter->pdev->ptm_enabled; > +#endif It's not obvious why you make this x86-specific. Maybe a comment? You shouldn't have to test for CONFIG_PCIE_PTM, either. We probably should have a pdev->ptm_enabled() predicate with a stub that returns false when CONFIG_PCIE_PTM is not set. > + return false; > +} > +/* PCIe Registers */ > +#define IGC_PTM_CTRL 0x12540 /* PTM Control */ > +#define IGC_PTM_STAT 0x12544 /* PTM Status */ > +#define IGC_PTM_CYCLE_CTRL 0x1254C /* PTM Cycle Control */ > + > +/* PTM Time registers */ > +#define IGC_PTM_T1_TIM0_L 0x12558 /* T1 on Timer 0 Low */ > +#define IGC_PTM_T1_TIM0_H 0x1255C /* T1 on Timer 0 High */ > + > +#define IGC_PTM_CURR_T2_L 0x1258C /* Current T2 Low */ > +#define IGC_PTM_CURR_T2_H 0x12590 /* Current T2 High */ > +#define IGC_PTM_PREV_T2_L 0x12584 /* Previous T2 Low */ > +#define IGC_PTM_PREV_T2_H 0x12588 /* Previous T2 High */ > +#define IGC_PTM_PREV_T4M1 0x12578 /* T4 Minus T1 on previous PTM Cycle */ > +#define IGC_PTM_CURR_T4M1 0x1257C /* T4 Minus T1 on this PTM Cycle */ > +#define IGC_PTM_PREV_T3M2 0x12580 /* T3 Minus T2 on previous PTM Cycle */ > +#define IGC_PTM_TDELAY 0x12594 /* PTM PCIe Link Delay */ > + > +#define IGC_PCIE_DIG_DELAY 0x12550 /* PCIe Digital Delay */ > +#define IGC_PCIE_PHY_DELAY 0x12554 /* PCIe PHY Delay */ I assume the above are device-specific registers, right? Nothing that would be found in the PCIe base spec? Bjorn
WARNING: multiple messages have this Message-ID (diff)
From: Bjorn Helgaas <helgaas@kernel.org> To: intel-wired-lan@osuosl.org Subject: [Intel-wired-lan] [PATCH next-queue v3 3/3] igc: Add support for PTP getcrosststamp() Date: Tue, 23 Mar 2021 14:39:23 -0500 [thread overview] Message-ID: <20210323193923.GA597480@bjorn-Precision-5520> (raw) In-Reply-To: <20210322161822.1546454-4-vinicius.gomes@intel.com> On Mon, Mar 22, 2021 at 09:18:22AM -0700, Vinicius Costa Gomes wrote: > i225 has support for PCIe PTM, which allows us to implement support > for the PTP_SYS_OFFSET_PRECISE ioctl(), implemented in the driver via > the getcrosststamp() function. > +static bool igc_is_ptm_supported(struct igc_adapter *adapter) > +{ > +#if IS_ENABLED(CONFIG_X86_TSC) && IS_ENABLED(CONFIG_PCIE_PTM) > + return adapter->pdev->ptm_enabled; > +#endif It's not obvious why you make this x86-specific. Maybe a comment? You shouldn't have to test for CONFIG_PCIE_PTM, either. We probably should have a pdev->ptm_enabled() predicate with a stub that returns false when CONFIG_PCIE_PTM is not set. > + return false; > +} > +/* PCIe Registers */ > +#define IGC_PTM_CTRL 0x12540 /* PTM Control */ > +#define IGC_PTM_STAT 0x12544 /* PTM Status */ > +#define IGC_PTM_CYCLE_CTRL 0x1254C /* PTM Cycle Control */ > + > +/* PTM Time registers */ > +#define IGC_PTM_T1_TIM0_L 0x12558 /* T1 on Timer 0 Low */ > +#define IGC_PTM_T1_TIM0_H 0x1255C /* T1 on Timer 0 High */ > + > +#define IGC_PTM_CURR_T2_L 0x1258C /* Current T2 Low */ > +#define IGC_PTM_CURR_T2_H 0x12590 /* Current T2 High */ > +#define IGC_PTM_PREV_T2_L 0x12584 /* Previous T2 Low */ > +#define IGC_PTM_PREV_T2_H 0x12588 /* Previous T2 High */ > +#define IGC_PTM_PREV_T4M1 0x12578 /* T4 Minus T1 on previous PTM Cycle */ > +#define IGC_PTM_CURR_T4M1 0x1257C /* T4 Minus T1 on this PTM Cycle */ > +#define IGC_PTM_PREV_T3M2 0x12580 /* T3 Minus T2 on previous PTM Cycle */ > +#define IGC_PTM_TDELAY 0x12594 /* PTM PCIe Link Delay */ > + > +#define IGC_PCIE_DIG_DELAY 0x12550 /* PCIe Digital Delay */ > +#define IGC_PCIE_PHY_DELAY 0x12554 /* PCIe PHY Delay */ I assume the above are device-specific registers, right? Nothing that would be found in the PCIe base spec? Bjorn
next prev parent reply other threads:[~2021-03-23 19:40 UTC|newest] Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-03-22 16:18 [PATCH next-queue v3 0/3] igc: Add support for PCIe PTM Vinicius Costa Gomes 2021-03-22 16:18 ` [Intel-wired-lan] " Vinicius Costa Gomes 2021-03-22 16:18 ` [PATCH next-queue v3 1/3] Revert "PCI: Make pci_enable_ptm() private" Vinicius Costa Gomes 2021-03-22 16:18 ` [Intel-wired-lan] " Vinicius Costa Gomes 2021-03-23 16:01 ` Christoph Hellwig 2021-03-23 16:01 ` [Intel-wired-lan] " Christoph Hellwig 2021-03-23 18:40 ` Vinicius Costa Gomes 2021-03-23 18:40 ` [Intel-wired-lan] " Vinicius Costa Gomes 2021-03-23 18:45 ` Christoph Hellwig 2021-03-23 18:45 ` [Intel-wired-lan] " Christoph Hellwig 2021-03-23 19:40 ` Bjorn Helgaas 2021-03-23 19:40 ` [Intel-wired-lan] " Bjorn Helgaas 2021-03-23 22:49 ` Vinicius Costa Gomes 2021-03-23 22:49 ` [Intel-wired-lan] " Vinicius Costa Gomes 2021-03-22 16:18 ` [PATCH next-queue v3 2/3] igc: Enable PCIe PTM Vinicius Costa Gomes 2021-03-22 16:18 ` [Intel-wired-lan] " Vinicius Costa Gomes 2021-03-23 19:29 ` Bjorn Helgaas 2021-03-23 19:29 ` [Intel-wired-lan] " Bjorn Helgaas 2021-03-23 19:40 ` Vinicius Costa Gomes 2021-03-23 19:40 ` [Intel-wired-lan] " Vinicius Costa Gomes 2021-03-22 16:18 ` [PATCH next-queue v3 3/3] igc: Add support for PTP getcrosststamp() Vinicius Costa Gomes 2021-03-22 16:18 ` [Intel-wired-lan] " Vinicius Costa Gomes 2021-03-23 19:39 ` Bjorn Helgaas [this message] 2021-03-23 19:39 ` Bjorn Helgaas 2021-03-23 21:37 ` Vinicius Costa Gomes 2021-03-23 21:37 ` [Intel-wired-lan] " Vinicius Costa Gomes
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