All of lore.kernel.org
 help / color / mirror / Atom feed
From: Vinicius Costa Gomes <vinicius.gomes@intel.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: intel-wired-lan@lists.osuosl.org, sasha.neftin@intel.com,
	anthony.l.nguyen@intel.com, linux-pci@vger.kernel.org,
	bhelgaas@google.com, netdev@vger.kernel.org, mlichvar@redhat.com,
	richardcochran@gmail.com
Subject: Re: [PATCH next-queue v3 2/3] igc: Enable PCIe PTM
Date: Tue, 23 Mar 2021 12:40:49 -0700	[thread overview]
Message-ID: <87mtutk69q.fsf@vcostago-mobl2.amr.corp.intel.com> (raw)
In-Reply-To: <20210323192920.GA597326@bjorn-Precision-5520>

Bjorn Helgaas <helgaas@kernel.org> writes:

> On Mon, Mar 22, 2021 at 09:18:21AM -0700, Vinicius Costa Gomes wrote:
>> In practice, enabling PTM also sets the enabled_ptm flag in the PCI
>> device, the flag will be used for detecting if PTM is enabled before
>> adding support for the SYSOFFSET_PRECISE ioctl() (which is added by
>> implementing the getcrosststamp() PTP function).
>
> I think you're referring to the "pci_dev.ptm_enabled" flag.  I'm not
> sure what the connection to this patch is.  The SYSOFFSET_PRECISE
> stuff also seems to belong with some other patch.

Yeah, I will improve the commit message to make it clear that this patch
is a preparation patch for the one that will add support for
PTP_SYS_OFFSET_PRECISE/getcrosststamp() and what's the relation with
PCIe PTM.

>
> This patch merely enables PTM if it's supported (might be worth
> expanding Precision Time Measurement for context).

Yes. Will expand the definition in the commit message.


Cheers,
-- 
Vinicius

WARNING: multiple messages have this Message-ID (diff)
From: Vinicius Costa Gomes <vinicius.gomes@intel.com>
To: intel-wired-lan@osuosl.org
Subject: [Intel-wired-lan] [PATCH next-queue v3 2/3] igc: Enable PCIe PTM
Date: Tue, 23 Mar 2021 12:40:49 -0700	[thread overview]
Message-ID: <87mtutk69q.fsf@vcostago-mobl2.amr.corp.intel.com> (raw)
In-Reply-To: <20210323192920.GA597326@bjorn-Precision-5520>

Bjorn Helgaas <helgaas@kernel.org> writes:

> On Mon, Mar 22, 2021 at 09:18:21AM -0700, Vinicius Costa Gomes wrote:
>> In practice, enabling PTM also sets the enabled_ptm flag in the PCI
>> device, the flag will be used for detecting if PTM is enabled before
>> adding support for the SYSOFFSET_PRECISE ioctl() (which is added by
>> implementing the getcrosststamp() PTP function).
>
> I think you're referring to the "pci_dev.ptm_enabled" flag.  I'm not
> sure what the connection to this patch is.  The SYSOFFSET_PRECISE
> stuff also seems to belong with some other patch.

Yeah, I will improve the commit message to make it clear that this patch
is a preparation patch for the one that will add support for
PTP_SYS_OFFSET_PRECISE/getcrosststamp() and what's the relation with
PCIe PTM.

>
> This patch merely enables PTM if it's supported (might be worth
> expanding Precision Time Measurement for context).

Yes. Will expand the definition in the commit message.


Cheers,
-- 
Vinicius

  reply	other threads:[~2021-03-23 19:42 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-22 16:18 [PATCH next-queue v3 0/3] igc: Add support for PCIe PTM Vinicius Costa Gomes
2021-03-22 16:18 ` [Intel-wired-lan] " Vinicius Costa Gomes
2021-03-22 16:18 ` [PATCH next-queue v3 1/3] Revert "PCI: Make pci_enable_ptm() private" Vinicius Costa Gomes
2021-03-22 16:18   ` [Intel-wired-lan] " Vinicius Costa Gomes
2021-03-23 16:01   ` Christoph Hellwig
2021-03-23 16:01     ` [Intel-wired-lan] " Christoph Hellwig
2021-03-23 18:40     ` Vinicius Costa Gomes
2021-03-23 18:40       ` [Intel-wired-lan] " Vinicius Costa Gomes
2021-03-23 18:45       ` Christoph Hellwig
2021-03-23 18:45         ` [Intel-wired-lan] " Christoph Hellwig
2021-03-23 19:40   ` Bjorn Helgaas
2021-03-23 19:40     ` [Intel-wired-lan] " Bjorn Helgaas
2021-03-23 22:49     ` Vinicius Costa Gomes
2021-03-23 22:49       ` [Intel-wired-lan] " Vinicius Costa Gomes
2021-03-22 16:18 ` [PATCH next-queue v3 2/3] igc: Enable PCIe PTM Vinicius Costa Gomes
2021-03-22 16:18   ` [Intel-wired-lan] " Vinicius Costa Gomes
2021-03-23 19:29   ` Bjorn Helgaas
2021-03-23 19:29     ` [Intel-wired-lan] " Bjorn Helgaas
2021-03-23 19:40     ` Vinicius Costa Gomes [this message]
2021-03-23 19:40       ` Vinicius Costa Gomes
2021-03-22 16:18 ` [PATCH next-queue v3 3/3] igc: Add support for PTP getcrosststamp() Vinicius Costa Gomes
2021-03-22 16:18   ` [Intel-wired-lan] " Vinicius Costa Gomes
2021-03-23 19:39   ` Bjorn Helgaas
2021-03-23 19:39     ` [Intel-wired-lan] " Bjorn Helgaas
2021-03-23 21:37     ` Vinicius Costa Gomes
2021-03-23 21:37       ` [Intel-wired-lan] " Vinicius Costa Gomes

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=87mtutk69q.fsf@vcostago-mobl2.amr.corp.intel.com \
    --to=vinicius.gomes@intel.com \
    --cc=anthony.l.nguyen@intel.com \
    --cc=bhelgaas@google.com \
    --cc=helgaas@kernel.org \
    --cc=intel-wired-lan@lists.osuosl.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=mlichvar@redhat.com \
    --cc=netdev@vger.kernel.org \
    --cc=richardcochran@gmail.com \
    --cc=sasha.neftin@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.