* [PATCH v6 00/18] cpu: Introduce SysemuCPUOps structure
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, qemu-riscv, Juan Quintela, Peter Maydell,
Claudio Fontana, qemu-arm, Eduardo Habkost, qemu-ppc,
Richard Henderson, Laurent Vivier, qemu-s390x,
Philippe Mathieu-Daudé
Missing review: patch 6, 7, 8, 10
Hi,
This series is inspired on Claudio TCG work.
Instead of separate TCG from other accelerators, here we
separate sysemu operations (system VS user).
Patches 1-5 are generic cleanups.
Patches 6-14 move from CPUClass to SysemuCPUOps
Patch 15 restricts SysemuCPUOps to sysemu
Since v5:
- Rework patch 10 after Peter Maydell explanation on v3:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg800849.html
Since v4:
- Removed watchpoint patches (need more work) (Richard)
- Merged patch 1 & 7 "Move CPUClass::vmsd to SysemuCPUOps" (Eduardo)
- Reworded cpu_virtio_is_big_endian description (Greg)
- Move write_elf() in target/riscv/cpu.c (rebased on top of 43a965888)
- Added R-b tags
Since v3:
- SysemuCPUOps const (Richard)
- added missing xtensa #ifdef'ry
- added missing aa64/sve #ifdef'ry
- added Laurent R-b
Since v2:
- fixed lm32/unicore32
- remove USER_ONLY ifdef'ry from "cpu.h" (Claudio)
Since v1:
- Name 'sysemu' (Claudio)
- change each field progressively (Richard)
$ git backport-diff
Key:
[----] : patches are identical
[####] : number of functional differences between upstream/downstream patch
[down] : patch is downstream-only
The flags [FC] indicate (F)unctional and (C)ontextual differences, respective=
ly
001/18:[----] [--] 'cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from=
_attrs'
002/18:[----] [--] 'cpu: Introduce cpu_virtio_is_big_endian()'
003/18:[----] [--] 'cpu: Directly use cpu_write_elf*() fallback handlers in p=
lace'
004/18:[----] [--] 'cpu: Directly use get_paging_enabled() fallback handlers =
in place'
005/18:[----] [--] 'cpu: Directly use get_memory_mapping() fallback handlers =
in place'
006/18:[down] 'cpu: Assert DeviceClass::vmsd is NULL on user emulation'
007/18:[down] 'cpu: Rename CPUClass vmsd -> legacy_vmsd'
008/18:[down] 'cpu/{avr,lm32,moxie}: Set DeviceClass vmsd field (not CPUClass=
one)'
009/18:[0010] [FC] 'cpu: Introduce SysemuCPUOps structure'
010/18:[0118] [FC] 'cpu: Move CPUClass::vmsd to SysemuCPUOps'
011/18:[----] [-C] 'cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps'
012/18:[----] [-C] 'cpu: Move CPUClass::get_crash_info to SysemuCPUOps'
013/18:[----] [-C] 'cpu: Move CPUClass::write_elf* to SysemuCPUOps'
014/18:[----] [--] 'cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps'
015/18:[0002] [FC] 'cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps'
016/18:[----] [--] 'cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps'
017/18:[----] [--] 'cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps'
018/18:[----] [--] 'cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c'
CI: https://gitlab.com/philmd/qemu/-/pipelines/290833005
Regards,
Phil.
Philippe Mathieu-Daud=C3=A9 (18):
cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs
cpu: Introduce cpu_virtio_is_big_endian()
cpu: Directly use cpu_write_elf*() fallback handlers in place
cpu: Directly use get_paging_enabled() fallback handlers in place
cpu: Directly use get_memory_mapping() fallback handlers in place
cpu: Assert DeviceClass::vmsd is NULL on user emulation
cpu: Rename CPUClass vmsd -> legacy_vmsd
cpu/{avr,lm32,moxie}: Set DeviceClass vmsd field (not CPUClass one)
cpu: Introduce SysemuCPUOps structure
cpu: Move CPUClass::vmsd to SysemuCPUOps
cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps
cpu: Move CPUClass::get_crash_info to SysemuCPUOps
cpu: Move CPUClass::write_elf* to SysemuCPUOps
cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps
cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps
cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps
cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps
cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c
include/hw/core/cpu.h | 92 ++++++-------------------
include/hw/core/sysemu-cpu-ops.h | 90 ++++++++++++++++++++++++
include/migration/vmstate.h | 2 -
target/alpha/cpu.h | 3 +
target/arm/cpu.h | 3 +
target/avr/cpu.h | 1 +
target/cris/cpu.h | 3 +
target/hexagon/cpu.h | 3 +
target/hppa/cpu.h | 3 +
target/i386/cpu.h | 3 +
target/lm32/cpu.h | 3 +
target/m68k/cpu.h | 3 +
target/microblaze/cpu.h | 1 +
target/mips/cpu.h | 3 +
target/moxie/cpu.h | 3 +
target/nios2/cpu.h | 1 +
target/openrisc/cpu.h | 3 +
target/ppc/cpu.h | 3 +
target/riscv/cpu.h | 3 +
target/rx/cpu.h | 1 +
target/s390x/cpu.h | 3 +
target/sh4/cpu.h | 3 +
target/sparc/cpu.h | 3 +
target/tricore/cpu.h | 3 +
target/unicore32/cpu.h | 3 +
target/xtensa/cpu.h | 3 +
cpu.c | 17 ++---
hw/core/cpu.c | 113 +++++++++++++++++--------------
hw/virtio/virtio.c | 4 +-
stubs/vmstate.c | 2 -
target/alpha/cpu.c | 8 ++-
target/arm/cpu.c | 18 +++--
target/avr/cpu.c | 8 ++-
target/cris/cpu.c | 8 ++-
target/hppa/cpu.c | 8 ++-
target/i386/cpu.c | 28 +++++---
target/lm32/cpu.c | 10 ++-
target/m68k/cpu.c | 8 ++-
target/microblaze/cpu.c | 8 ++-
target/mips/cpu.c | 10 ++-
target/moxie/cpu.c | 8 ++-
target/nios2/cpu.c | 8 ++-
target/openrisc/cpu.c | 8 ++-
target/riscv/cpu.c | 16 +++--
target/rx/cpu.c | 10 ++-
target/s390x/cpu.c | 14 ++--
target/sh4/cpu.c | 11 ++-
target/sparc/cpu.c | 10 ++-
target/tricore/cpu.c | 6 +-
target/unicore32/cpu.c | 10 ++-
target/xtensa/cpu.c | 10 ++-
target/ppc/translate_init.c.inc | 20 +++---
52 files changed, 430 insertions(+), 196 deletions(-)
create mode 100644 include/hw/core/sysemu-cpu-ops.h
--=20
2.26.3
^ permalink raw reply [flat|nested] 51+ messages in thread* [PATCH v6 01/18] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs
2021-04-22 19:38 ` Philippe Mathieu-Daudé
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-riscv, Eduardo Habkost, Juan Quintela,
Richard Henderson, Dr. David Alan Gilbert, Laurent Vivier,
qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana,
Philippe Mathieu-Daudé
To be able to later extract the cpu_get_phys_page_debug() and
cpu_asidx_from_attrs() handlers from CPUClass, un-inline them
from "hw/core/cpu.h".
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 33 ++++-----------------------------
hw/core/cpu.c | 32 ++++++++++++++++++++++++++++++++
2 files changed, 36 insertions(+), 29 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index c68bc3ba8af..9338e80aa4b 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -580,18 +580,8 @@ void cpu_dump_statistics(CPUState *cpu, int flags);
*
* Returns: Corresponding physical page address or -1 if no page found.
*/
-static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
- MemTxAttrs *attrs)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (cc->get_phys_page_attrs_debug) {
- return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
- }
- /* Fallback for CPUs which don't implement the _attrs_ hook */
- *attrs = MEMTXATTRS_UNSPECIFIED;
- return cc->get_phys_page_debug(cpu, addr);
-}
+hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
+ MemTxAttrs *attrs);
/**
* cpu_get_phys_page_debug:
@@ -603,12 +593,7 @@ static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
*
* Returns: Corresponding physical page address or -1 if no page found.
*/
-static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
-{
- MemTxAttrs attrs = {};
-
- return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
-}
+hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
/** cpu_asidx_from_attrs:
* @cpu: CPU
@@ -617,17 +602,7 @@ static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
* Returns the address space index specifying the CPU AddressSpace
* to use for a memory access with the given transaction attributes.
*/
-static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
- int ret = 0;
-
- if (cc->asidx_from_attrs) {
- ret = cc->asidx_from_attrs(cpu, attrs);
- assert(ret < cpu->num_ases && ret >= 0);
- }
- return ret;
-}
+int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
#endif /* CONFIG_USER_ONLY */
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 00330ba07de..4dce35f832f 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -94,6 +94,38 @@ static void cpu_common_get_memory_mapping(CPUState *cpu,
error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
}
+hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
+ MemTxAttrs *attrs)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->get_phys_page_attrs_debug) {
+ return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
+ }
+ /* Fallback for CPUs which don't implement the _attrs_ hook */
+ *attrs = MEMTXATTRS_UNSPECIFIED;
+ return cc->get_phys_page_debug(cpu, addr);
+}
+
+hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
+{
+ MemTxAttrs attrs = {};
+
+ return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
+}
+
+int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+ int ret = 0;
+
+ if (cc->asidx_from_attrs) {
+ ret = cc->asidx_from_attrs(cpu, attrs);
+ assert(ret < cpu->num_ases && ret >= 0);
+ }
+ return ret;
+}
+
/* Resetting the IRQ comes from across the code base so we take the
* BQL here if we need to. cpu_interrupt assumes it is held.*/
void cpu_reset_interrupt(CPUState *cpu, int mask)
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v6 01/18] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, qemu-riscv, Juan Quintela, Peter Maydell,
Claudio Fontana, qemu-arm, Eduardo Habkost, qemu-ppc,
Richard Henderson, Laurent Vivier, qemu-s390x,
Philippe Mathieu-Daudé,
Marcel Apfelbaum
To be able to later extract the cpu_get_phys_page_debug() and
cpu_asidx_from_attrs() handlers from CPUClass, un-inline them
from "hw/core/cpu.h".
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 33 ++++-----------------------------
hw/core/cpu.c | 32 ++++++++++++++++++++++++++++++++
2 files changed, 36 insertions(+), 29 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index c68bc3ba8af..9338e80aa4b 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -580,18 +580,8 @@ void cpu_dump_statistics(CPUState *cpu, int flags);
*
* Returns: Corresponding physical page address or -1 if no page found.
*/
-static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
- MemTxAttrs *attrs)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (cc->get_phys_page_attrs_debug) {
- return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
- }
- /* Fallback for CPUs which don't implement the _attrs_ hook */
- *attrs = MEMTXATTRS_UNSPECIFIED;
- return cc->get_phys_page_debug(cpu, addr);
-}
+hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
+ MemTxAttrs *attrs);
/**
* cpu_get_phys_page_debug:
@@ -603,12 +593,7 @@ static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
*
* Returns: Corresponding physical page address or -1 if no page found.
*/
-static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
-{
- MemTxAttrs attrs = {};
-
- return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
-}
+hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
/** cpu_asidx_from_attrs:
* @cpu: CPU
@@ -617,17 +602,7 @@ static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
* Returns the address space index specifying the CPU AddressSpace
* to use for a memory access with the given transaction attributes.
*/
-static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
- int ret = 0;
-
- if (cc->asidx_from_attrs) {
- ret = cc->asidx_from_attrs(cpu, attrs);
- assert(ret < cpu->num_ases && ret >= 0);
- }
- return ret;
-}
+int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
#endif /* CONFIG_USER_ONLY */
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 00330ba07de..4dce35f832f 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -94,6 +94,38 @@ static void cpu_common_get_memory_mapping(CPUState *cpu,
error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
}
+hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
+ MemTxAttrs *attrs)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->get_phys_page_attrs_debug) {
+ return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
+ }
+ /* Fallback for CPUs which don't implement the _attrs_ hook */
+ *attrs = MEMTXATTRS_UNSPECIFIED;
+ return cc->get_phys_page_debug(cpu, addr);
+}
+
+hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
+{
+ MemTxAttrs attrs = {};
+
+ return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
+}
+
+int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+ int ret = 0;
+
+ if (cc->asidx_from_attrs) {
+ ret = cc->asidx_from_attrs(cpu, attrs);
+ assert(ret < cpu->num_ases && ret >= 0);
+ }
+ return ret;
+}
+
/* Resetting the IRQ comes from across the code base so we take the
* BQL here if we need to. cpu_interrupt assumes it is held.*/
void cpu_reset_interrupt(CPUState *cpu, int mask)
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v6 02/18] cpu: Introduce cpu_virtio_is_big_endian()
2021-04-22 19:38 ` Philippe Mathieu-Daudé
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-riscv, Eduardo Habkost, Juan Quintela,
Michael S. Tsirkin, Richard Henderson, Dr. David Alan Gilbert,
Laurent Vivier, qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana,
Philippe Mathieu-Daudé
Introduce the cpu_virtio_is_big_endian() generic helper to avoid
calling CPUClass internal virtio_is_big_endian() one.
Similarly to commit bf7663c4bd8 ("cpu: introduce
CPUClass::virtio_is_big_endian()"), we keep 'virtio' in the method
name to hint this handler shouldn't be called anywhere but from the
virtio code.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 9 +++++++++
hw/core/cpu.c | 8 ++++++--
hw/virtio/virtio.c | 4 +---
3 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 9338e80aa4b..08af2c383a5 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -604,6 +604,15 @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
*/
int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
+/**
+ * cpu_virtio_is_big_endian:
+ * @cpu: CPU
+
+ * Returns %true if a CPU which supports runtime configurable endianness
+ * is currently big-endian.
+ */
+bool cpu_virtio_is_big_endian(CPUState *cpu);
+
#endif /* CONFIG_USER_ONLY */
/**
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 4dce35f832f..daaff56a79e 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -218,8 +218,13 @@ static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
return 0;
}
-static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
+bool cpu_virtio_is_big_endian(CPUState *cpu)
{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->virtio_is_big_endian) {
+ return cc->virtio_is_big_endian(cpu);
+ }
return target_words_bigendian();
}
@@ -438,7 +443,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->write_elf64_note = cpu_common_write_elf64_note;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
- k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
dc->realize = cpu_common_realizefn;
dc->unrealize = cpu_common_unrealizefn;
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 07f4e60b309..8a364496fd5 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -1973,9 +1973,7 @@ static enum virtio_device_endian virtio_default_endian(void)
static enum virtio_device_endian virtio_current_cpu_endian(void)
{
- CPUClass *cc = CPU_GET_CLASS(current_cpu);
-
- if (cc->virtio_is_big_endian(current_cpu)) {
+ if (cpu_virtio_is_big_endian(current_cpu)) {
return VIRTIO_DEVICE_ENDIAN_BIG;
} else {
return VIRTIO_DEVICE_ENDIAN_LITTLE;
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v6 02/18] cpu: Introduce cpu_virtio_is_big_endian()
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, qemu-riscv, Juan Quintela, Peter Maydell,
Claudio Fontana, qemu-arm, Eduardo Habkost, qemu-ppc,
Richard Henderson, Laurent Vivier, qemu-s390x,
Philippe Mathieu-Daudé,
Marcel Apfelbaum, Michael S. Tsirkin
Introduce the cpu_virtio_is_big_endian() generic helper to avoid
calling CPUClass internal virtio_is_big_endian() one.
Similarly to commit bf7663c4bd8 ("cpu: introduce
CPUClass::virtio_is_big_endian()"), we keep 'virtio' in the method
name to hint this handler shouldn't be called anywhere but from the
virtio code.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 9 +++++++++
hw/core/cpu.c | 8 ++++++--
hw/virtio/virtio.c | 4 +---
3 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 9338e80aa4b..08af2c383a5 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -604,6 +604,15 @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
*/
int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
+/**
+ * cpu_virtio_is_big_endian:
+ * @cpu: CPU
+
+ * Returns %true if a CPU which supports runtime configurable endianness
+ * is currently big-endian.
+ */
+bool cpu_virtio_is_big_endian(CPUState *cpu);
+
#endif /* CONFIG_USER_ONLY */
/**
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 4dce35f832f..daaff56a79e 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -218,8 +218,13 @@ static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
return 0;
}
-static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
+bool cpu_virtio_is_big_endian(CPUState *cpu)
{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->virtio_is_big_endian) {
+ return cc->virtio_is_big_endian(cpu);
+ }
return target_words_bigendian();
}
@@ -438,7 +443,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->write_elf64_note = cpu_common_write_elf64_note;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
- k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
dc->realize = cpu_common_realizefn;
dc->unrealize = cpu_common_unrealizefn;
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 07f4e60b309..8a364496fd5 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -1973,9 +1973,7 @@ static enum virtio_device_endian virtio_default_endian(void)
static enum virtio_device_endian virtio_current_cpu_endian(void)
{
- CPUClass *cc = CPU_GET_CLASS(current_cpu);
-
- if (cc->virtio_is_big_endian(current_cpu)) {
+ if (cpu_virtio_is_big_endian(current_cpu)) {
return VIRTIO_DEVICE_ENDIAN_BIG;
} else {
return VIRTIO_DEVICE_ENDIAN_LITTLE;
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v6 03/18] cpu: Directly use cpu_write_elf*() fallback handlers in place
2021-04-22 19:38 ` Philippe Mathieu-Daudé
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-riscv, Eduardo Habkost, Juan Quintela,
Richard Henderson, Dr. David Alan Gilbert, Laurent Vivier,
qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana,
Philippe Mathieu-Daudé
No code directly accesses CPUClass::write_elf*() handlers out
of hw/core/cpu.c (the rest are assignation in target/ code):
$ git grep -F -- '->write_elf'
hw/core/cpu.c:157: return (*cc->write_elf32_qemunote)(f, cpu, opaque);
hw/core/cpu.c:171: return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
hw/core/cpu.c:186: return (*cc->write_elf64_qemunote)(f, cpu, opaque);
hw/core/cpu.c:200: return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
hw/core/cpu.c:440: k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
hw/core/cpu.c:441: k->write_elf32_note = cpu_common_write_elf32_note;
hw/core/cpu.c:442: k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
hw/core/cpu.c:443: k->write_elf64_note = cpu_common_write_elf64_note;
target/arm/cpu.c:2304: cc->write_elf64_note = arm_cpu_write_elf64_note;
target/arm/cpu.c:2305: cc->write_elf32_note = arm_cpu_write_elf32_note;
target/i386/cpu.c:7425: cc->write_elf64_note = x86_cpu_write_elf64_note;
target/i386/cpu.c:7426: cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
target/i386/cpu.c:7427: cc->write_elf32_note = x86_cpu_write_elf32_note;
target/i386/cpu.c:7428: cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
target/ppc/translate_init.c.inc:10891: cc->write_elf64_note = ppc64_cpu_write_elf64_note;
target/ppc/translate_init.c.inc:10892: cc->write_elf32_note = ppc32_cpu_write_elf32_note;
target/s390x/cpu.c:522: cc->write_elf64_note = s390_cpu_write_elf64_note;
Check the handler presence in place and remove the common fallback code.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/core/cpu.c | 43 ++++++++++++-------------------------------
1 file changed, 12 insertions(+), 31 deletions(-)
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index daaff56a79e..a9ee2c74ec5 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -154,60 +154,45 @@ int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+ if (!cc->write_elf32_qemunote) {
+ return 0;
+ }
return (*cc->write_elf32_qemunote)(f, cpu, opaque);
}
-static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f,
- CPUState *cpu, void *opaque)
-{
- return 0;
-}
-
int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+ if (!cc->write_elf32_note) {
+ return -1;
+ }
return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
}
-static int cpu_common_write_elf32_note(WriteCoreDumpFunction f,
- CPUState *cpu, int cpuid,
- void *opaque)
-{
- return -1;
-}
-
int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+ if (!cc->write_elf64_qemunote) {
+ return 0;
+ }
return (*cc->write_elf64_qemunote)(f, cpu, opaque);
}
-static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f,
- CPUState *cpu, void *opaque)
-{
- return 0;
-}
-
int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+ if (!cc->write_elf64_note) {
+ return -1;
+ }
return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
}
-static int cpu_common_write_elf64_note(WriteCoreDumpFunction f,
- CPUState *cpu, int cpuid,
- void *opaque)
-{
- return -1;
-}
-
-
static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
{
return 0;
@@ -437,10 +422,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->has_work = cpu_common_has_work;
k->get_paging_enabled = cpu_common_get_paging_enabled;
k->get_memory_mapping = cpu_common_get_memory_mapping;
- k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
- k->write_elf32_note = cpu_common_write_elf32_note;
- k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
- k->write_elf64_note = cpu_common_write_elf64_note;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v6 03/18] cpu: Directly use cpu_write_elf*() fallback handlers in place
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, qemu-riscv, Juan Quintela, Peter Maydell,
Claudio Fontana, qemu-arm, Eduardo Habkost, qemu-ppc,
Richard Henderson, Laurent Vivier, qemu-s390x,
Philippe Mathieu-Daudé,
Marcel Apfelbaum
No code directly accesses CPUClass::write_elf*() handlers out
of hw/core/cpu.c (the rest are assignation in target/ code):
$ git grep -F -- '->write_elf'
hw/core/cpu.c:157: return (*cc->write_elf32_qemunote)(f, cpu, opaque);
hw/core/cpu.c:171: return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
hw/core/cpu.c:186: return (*cc->write_elf64_qemunote)(f, cpu, opaque);
hw/core/cpu.c:200: return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
hw/core/cpu.c:440: k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
hw/core/cpu.c:441: k->write_elf32_note = cpu_common_write_elf32_note;
hw/core/cpu.c:442: k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
hw/core/cpu.c:443: k->write_elf64_note = cpu_common_write_elf64_note;
target/arm/cpu.c:2304: cc->write_elf64_note = arm_cpu_write_elf64_note;
target/arm/cpu.c:2305: cc->write_elf32_note = arm_cpu_write_elf32_note;
target/i386/cpu.c:7425: cc->write_elf64_note = x86_cpu_write_elf64_note;
target/i386/cpu.c:7426: cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
target/i386/cpu.c:7427: cc->write_elf32_note = x86_cpu_write_elf32_note;
target/i386/cpu.c:7428: cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
target/ppc/translate_init.c.inc:10891: cc->write_elf64_note = ppc64_cpu_write_elf64_note;
target/ppc/translate_init.c.inc:10892: cc->write_elf32_note = ppc32_cpu_write_elf32_note;
target/s390x/cpu.c:522: cc->write_elf64_note = s390_cpu_write_elf64_note;
Check the handler presence in place and remove the common fallback code.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/core/cpu.c | 43 ++++++++++++-------------------------------
1 file changed, 12 insertions(+), 31 deletions(-)
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index daaff56a79e..a9ee2c74ec5 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -154,60 +154,45 @@ int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+ if (!cc->write_elf32_qemunote) {
+ return 0;
+ }
return (*cc->write_elf32_qemunote)(f, cpu, opaque);
}
-static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f,
- CPUState *cpu, void *opaque)
-{
- return 0;
-}
-
int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+ if (!cc->write_elf32_note) {
+ return -1;
+ }
return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
}
-static int cpu_common_write_elf32_note(WriteCoreDumpFunction f,
- CPUState *cpu, int cpuid,
- void *opaque)
-{
- return -1;
-}
-
int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+ if (!cc->write_elf64_qemunote) {
+ return 0;
+ }
return (*cc->write_elf64_qemunote)(f, cpu, opaque);
}
-static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f,
- CPUState *cpu, void *opaque)
-{
- return 0;
-}
-
int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+ if (!cc->write_elf64_note) {
+ return -1;
+ }
return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
}
-static int cpu_common_write_elf64_note(WriteCoreDumpFunction f,
- CPUState *cpu, int cpuid,
- void *opaque)
-{
- return -1;
-}
-
-
static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
{
return 0;
@@ -437,10 +422,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->has_work = cpu_common_has_work;
k->get_paging_enabled = cpu_common_get_paging_enabled;
k->get_memory_mapping = cpu_common_get_memory_mapping;
- k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
- k->write_elf32_note = cpu_common_write_elf32_note;
- k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
- k->write_elf64_note = cpu_common_write_elf64_note;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v6 04/18] cpu: Directly use get_paging_enabled() fallback handlers in place
2021-04-22 19:38 ` Philippe Mathieu-Daudé
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-riscv, Eduardo Habkost, Juan Quintela,
Richard Henderson, Dr. David Alan Gilbert, Laurent Vivier,
qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana,
Philippe Mathieu-Daudé
No code uses CPUClass::get_paging_enabled() outside of hw/core/cpu.c:
$ git grep -F -- '->get_paging_enabled'
hw/core/cpu.c:74: return cc->get_paging_enabled(cpu);
hw/core/cpu.c:438: k->get_paging_enabled = cpu_common_get_paging_enabled;
target/i386/cpu.c:7418: cc->get_paging_enabled = x86_cpu_get_paging_enabled;
Check the handler presence in place and remove the common fallback code.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/core/cpu.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index a9ee2c74ec5..1de00bbb474 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -71,11 +71,10 @@ bool cpu_paging_enabled(const CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- return cc->get_paging_enabled(cpu);
-}
+ if (cc->get_paging_enabled) {
+ return cc->get_paging_enabled(cpu);
+ }
-static bool cpu_common_get_paging_enabled(const CPUState *cpu)
-{
return false;
}
@@ -420,7 +419,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->parse_features = cpu_common_parse_features;
k->get_arch_id = cpu_common_get_arch_id;
k->has_work = cpu_common_has_work;
- k->get_paging_enabled = cpu_common_get_paging_enabled;
k->get_memory_mapping = cpu_common_get_memory_mapping;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v6 04/18] cpu: Directly use get_paging_enabled() fallback handlers in place
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, qemu-riscv, Juan Quintela, Peter Maydell,
Claudio Fontana, qemu-arm, Eduardo Habkost, qemu-ppc,
Richard Henderson, Laurent Vivier, qemu-s390x,
Philippe Mathieu-Daudé,
Marcel Apfelbaum
No code uses CPUClass::get_paging_enabled() outside of hw/core/cpu.c:
$ git grep -F -- '->get_paging_enabled'
hw/core/cpu.c:74: return cc->get_paging_enabled(cpu);
hw/core/cpu.c:438: k->get_paging_enabled = cpu_common_get_paging_enabled;
target/i386/cpu.c:7418: cc->get_paging_enabled = x86_cpu_get_paging_enabled;
Check the handler presence in place and remove the common fallback code.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/core/cpu.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index a9ee2c74ec5..1de00bbb474 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -71,11 +71,10 @@ bool cpu_paging_enabled(const CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- return cc->get_paging_enabled(cpu);
-}
+ if (cc->get_paging_enabled) {
+ return cc->get_paging_enabled(cpu);
+ }
-static bool cpu_common_get_paging_enabled(const CPUState *cpu)
-{
return false;
}
@@ -420,7 +419,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->parse_features = cpu_common_parse_features;
k->get_arch_id = cpu_common_get_arch_id;
k->has_work = cpu_common_has_work;
- k->get_paging_enabled = cpu_common_get_paging_enabled;
k->get_memory_mapping = cpu_common_get_memory_mapping;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v6 05/18] cpu: Directly use get_memory_mapping() fallback handlers in place
2021-04-22 19:38 ` Philippe Mathieu-Daudé
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-riscv, Eduardo Habkost, Juan Quintela,
Richard Henderson, Dr. David Alan Gilbert, Laurent Vivier,
qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana,
Philippe Mathieu-Daudé
No code uses CPUClass::get_memory_mapping() outside of hw/core/cpu.c:
$ git grep -F -- '->get_memory_mapping'
hw/core/cpu.c:87: cc->get_memory_mapping(cpu, list, errp);
hw/core/cpu.c:439: k->get_memory_mapping = cpu_common_get_memory_mapping;
target/i386/cpu.c:7422: cc->get_memory_mapping = x86_cpu_get_memory_mapping;
Check the handler presence in place and remove the common fallback code.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/core/cpu.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 1de00bbb474..5abf8bed2e4 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -83,13 +83,11 @@ void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- cc->get_memory_mapping(cpu, list, errp);
-}
+ if (cc->get_memory_mapping) {
+ cc->get_memory_mapping(cpu, list, errp);
+ return;
+ }
-static void cpu_common_get_memory_mapping(CPUState *cpu,
- MemoryMappingList *list,
- Error **errp)
-{
error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
}
@@ -419,7 +417,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->parse_features = cpu_common_parse_features;
k->get_arch_id = cpu_common_get_arch_id;
k->has_work = cpu_common_has_work;
- k->get_memory_mapping = cpu_common_get_memory_mapping;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v6 05/18] cpu: Directly use get_memory_mapping() fallback handlers in place
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, qemu-riscv, Juan Quintela, Peter Maydell,
Claudio Fontana, qemu-arm, Eduardo Habkost, qemu-ppc,
Richard Henderson, Laurent Vivier, qemu-s390x,
Philippe Mathieu-Daudé,
Marcel Apfelbaum
No code uses CPUClass::get_memory_mapping() outside of hw/core/cpu.c:
$ git grep -F -- '->get_memory_mapping'
hw/core/cpu.c:87: cc->get_memory_mapping(cpu, list, errp);
hw/core/cpu.c:439: k->get_memory_mapping = cpu_common_get_memory_mapping;
target/i386/cpu.c:7422: cc->get_memory_mapping = x86_cpu_get_memory_mapping;
Check the handler presence in place and remove the common fallback code.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/core/cpu.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 1de00bbb474..5abf8bed2e4 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -83,13 +83,11 @@ void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- cc->get_memory_mapping(cpu, list, errp);
-}
+ if (cc->get_memory_mapping) {
+ cc->get_memory_mapping(cpu, list, errp);
+ return;
+ }
-static void cpu_common_get_memory_mapping(CPUState *cpu,
- MemoryMappingList *list,
- Error **errp)
-{
error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
}
@@ -419,7 +417,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->parse_features = cpu_common_parse_features;
k->get_arch_id = cpu_common_get_arch_id;
k->has_work = cpu_common_has_work;
- k->get_memory_mapping = cpu_common_get_memory_mapping;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v6 06/18] cpu: Assert DeviceClass::vmsd is NULL on user emulation
2021-04-22 19:38 ` Philippe Mathieu-Daudé
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-riscv, Eduardo Habkost, Yoshinori Sato,
Juan Quintela, Richard Henderson, Dr. David Alan Gilbert,
Laurent Vivier, Max Filippov, qemu-s390x, qemu-arm, qemu-ppc,
Claudio Fontana, Guan Xuetao, Philippe Mathieu-Daudé
Migration is specific to system emulation.
Restrict current DeviceClass::vmsd to sysemu using #ifdef'ry,
and assert in cpu_exec_realizefn() that dc->vmsd not set under
user emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
cpu.c | 1 +
target/sh4/cpu.c | 5 +++--
target/unicore32/cpu.c | 4 ++++
target/xtensa/cpu.c | 4 +++-
4 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/cpu.c b/cpu.c
index bfbe5a66f95..4fed04219df 100644
--- a/cpu.c
+++ b/cpu.c
@@ -138,6 +138,7 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
#endif /* CONFIG_TCG */
#ifdef CONFIG_USER_ONLY
+ assert(qdev_get_vmsd(DEVICE(cpu)) == NULL);
assert(cc->vmsd == NULL);
#else
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index ac65c88f1f8..35d4251aaf3 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -218,10 +218,12 @@ static void superh_cpu_initfn(Object *obj)
env->movcal_backup_tail = &(env->movcal_backup);
}
+#ifndef CONFIG_USER_ONLY
static const VMStateDescription vmstate_sh_cpu = {
.name = "cpu",
.unmigratable = 1,
};
+#endif
#include "hw/core/tcg-cpu-ops.h"
@@ -257,12 +259,11 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = superh_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
+ dc->vmsd = &vmstate_sh_cpu;
#endif
cc->disas_set_info = superh_cpu_disas_set_info;
cc->gdb_num_core_regs = 59;
-
- dc->vmsd = &vmstate_sh_cpu;
cc->tcg_ops = &superh_tcg_ops;
}
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 0258884f845..a74ac7b6140 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -115,10 +115,12 @@ static void uc32_cpu_initfn(Object *obj)
#endif
}
+#ifndef CONFIG_USER_ONLY
static const VMStateDescription vmstate_uc32_cpu = {
.name = "cpu",
.unmigratable = 1,
};
+#endif
#include "hw/core/tcg-cpu-ops.h"
@@ -146,7 +148,9 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
+#ifndef CONFIG_USER_ONLY
dc->vmsd = &vmstate_uc32_cpu;
+#endif
cc->tcg_ops = &uc32_tcg_ops;
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index e2b2c7a71c1..a66527e2d45 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -176,10 +176,12 @@ static void xtensa_cpu_initfn(Object *obj)
#endif
}
+#ifndef CONFIG_USER_ONLY
static const VMStateDescription vmstate_xtensa_cpu = {
.name = "cpu",
.unmigratable = 1,
};
+#endif
#include "hw/core/tcg-cpu-ops.h"
@@ -216,9 +218,9 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
+ dc->vmsd = &vmstate_xtensa_cpu;
#endif
cc->disas_set_info = xtensa_cpu_disas_set_info;
- dc->vmsd = &vmstate_xtensa_cpu;
cc->tcg_ops = &xtensa_tcg_ops;
}
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v6 06/18] cpu: Assert DeviceClass::vmsd is NULL on user emulation
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, qemu-riscv, Juan Quintela, Peter Maydell,
Claudio Fontana, qemu-arm, Eduardo Habkost, qemu-ppc,
Richard Henderson, Laurent Vivier, qemu-s390x,
Philippe Mathieu-Daudé,
Marcel Apfelbaum, Yoshinori Sato, Guan Xuetao, Max Filippov
Migration is specific to system emulation.
Restrict current DeviceClass::vmsd to sysemu using #ifdef'ry,
and assert in cpu_exec_realizefn() that dc->vmsd not set under
user emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
cpu.c | 1 +
target/sh4/cpu.c | 5 +++--
target/unicore32/cpu.c | 4 ++++
target/xtensa/cpu.c | 4 +++-
4 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/cpu.c b/cpu.c
index bfbe5a66f95..4fed04219df 100644
--- a/cpu.c
+++ b/cpu.c
@@ -138,6 +138,7 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
#endif /* CONFIG_TCG */
#ifdef CONFIG_USER_ONLY
+ assert(qdev_get_vmsd(DEVICE(cpu)) == NULL);
assert(cc->vmsd == NULL);
#else
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index ac65c88f1f8..35d4251aaf3 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -218,10 +218,12 @@ static void superh_cpu_initfn(Object *obj)
env->movcal_backup_tail = &(env->movcal_backup);
}
+#ifndef CONFIG_USER_ONLY
static const VMStateDescription vmstate_sh_cpu = {
.name = "cpu",
.unmigratable = 1,
};
+#endif
#include "hw/core/tcg-cpu-ops.h"
@@ -257,12 +259,11 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = superh_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
+ dc->vmsd = &vmstate_sh_cpu;
#endif
cc->disas_set_info = superh_cpu_disas_set_info;
cc->gdb_num_core_regs = 59;
-
- dc->vmsd = &vmstate_sh_cpu;
cc->tcg_ops = &superh_tcg_ops;
}
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 0258884f845..a74ac7b6140 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -115,10 +115,12 @@ static void uc32_cpu_initfn(Object *obj)
#endif
}
+#ifndef CONFIG_USER_ONLY
static const VMStateDescription vmstate_uc32_cpu = {
.name = "cpu",
.unmigratable = 1,
};
+#endif
#include "hw/core/tcg-cpu-ops.h"
@@ -146,7 +148,9 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
+#ifndef CONFIG_USER_ONLY
dc->vmsd = &vmstate_uc32_cpu;
+#endif
cc->tcg_ops = &uc32_tcg_ops;
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index e2b2c7a71c1..a66527e2d45 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -176,10 +176,12 @@ static void xtensa_cpu_initfn(Object *obj)
#endif
}
+#ifndef CONFIG_USER_ONLY
static const VMStateDescription vmstate_xtensa_cpu = {
.name = "cpu",
.unmigratable = 1,
};
+#endif
#include "hw/core/tcg-cpu-ops.h"
@@ -216,9 +218,9 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
+ dc->vmsd = &vmstate_xtensa_cpu;
#endif
cc->disas_set_info = xtensa_cpu_disas_set_info;
- dc->vmsd = &vmstate_xtensa_cpu;
cc->tcg_ops = &xtensa_tcg_ops;
}
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v6 06/18] cpu: Assert DeviceClass::vmsd is NULL on user emulation
2021-04-22 19:38 ` Philippe Mathieu-Daudé
@ 2021-04-23 1:08 ` Richard Henderson
-1 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2021-04-23 1:08 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, qemu-riscv, Eduardo Habkost, Yoshinori Sato,
Juan Quintela, Dr. David Alan Gilbert, Laurent Vivier,
Max Filippov, qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana,
Guan Xuetao
On 4/22/21 12:38 PM, Philippe Mathieu-Daudé wrote:
> Migration is specific to system emulation.
>
> Restrict current DeviceClass::vmsd to sysemu using #ifdef'ry,
> and assert in cpu_exec_realizefn() that dc->vmsd not set under
> user emulation.
>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> cpu.c | 1 +
> target/sh4/cpu.c | 5 +++--
> target/unicore32/cpu.c | 4 ++++
> target/xtensa/cpu.c | 4 +++-
> 4 files changed, 11 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v6 06/18] cpu: Assert DeviceClass::vmsd is NULL on user emulation
@ 2021-04-23 1:08 ` Richard Henderson
0 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2021-04-23 1:08 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Dr. David Alan Gilbert, qemu-riscv, Juan Quintela, Peter Maydell,
Claudio Fontana, qemu-arm, Eduardo Habkost, qemu-ppc,
Laurent Vivier, qemu-s390x, Marcel Apfelbaum, Yoshinori Sato,
Guan Xuetao, Max Filippov
On 4/22/21 12:38 PM, Philippe Mathieu-Daudé wrote:
> Migration is specific to system emulation.
>
> Restrict current DeviceClass::vmsd to sysemu using #ifdef'ry,
> and assert in cpu_exec_realizefn() that dc->vmsd not set under
> user emulation.
>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> cpu.c | 1 +
> target/sh4/cpu.c | 5 +++--
> target/unicore32/cpu.c | 4 ++++
> target/xtensa/cpu.c | 4 +++-
> 4 files changed, 11 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v6 06/18] cpu: Assert DeviceClass::vmsd is NULL on user emulation
2021-04-22 19:38 ` Philippe Mathieu-Daudé
@ 2021-04-26 16:15 ` Dr. David Alan Gilbert
-1 siblings, 0 replies; 51+ messages in thread
From: Dr. David Alan Gilbert @ 2021-04-26 16:15 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, qemu-riscv, Eduardo Habkost, Yoshinori Sato,
Juan Quintela, Richard Henderson, qemu-devel, Laurent Vivier,
Max Filippov, qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana,
Guan Xuetao
* Philippe Mathieu-Daudé (f4bug@amsat.org) wrote:
> Migration is specific to system emulation.
>
> Restrict current DeviceClass::vmsd to sysemu using #ifdef'ry,
> and assert in cpu_exec_realizefn() that dc->vmsd not set under
> user emulation.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> cpu.c | 1 +
> target/sh4/cpu.c | 5 +++--
> target/unicore32/cpu.c | 4 ++++
> target/xtensa/cpu.c | 4 +++-
> 4 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/cpu.c b/cpu.c
> index bfbe5a66f95..4fed04219df 100644
> --- a/cpu.c
> +++ b/cpu.c
> @@ -138,6 +138,7 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
> #endif /* CONFIG_TCG */
>
> #ifdef CONFIG_USER_ONLY
> + assert(qdev_get_vmsd(DEVICE(cpu)) == NULL);
Why not make that:
assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
qdev_get_vmsd(DEVICE(cpu)->unmigratable)
then you don't have to worry about the changes below.
Dave
> assert(cc->vmsd == NULL);
> #else
> if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
> diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
> index ac65c88f1f8..35d4251aaf3 100644
> --- a/target/sh4/cpu.c
> +++ b/target/sh4/cpu.c
> @@ -218,10 +218,12 @@ static void superh_cpu_initfn(Object *obj)
> env->movcal_backup_tail = &(env->movcal_backup);
> }
>
> +#ifndef CONFIG_USER_ONLY
> static const VMStateDescription vmstate_sh_cpu = {
> .name = "cpu",
> .unmigratable = 1,
> };
> +#endif
>
> #include "hw/core/tcg-cpu-ops.h"
>
> @@ -257,12 +259,11 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
> cc->gdb_write_register = superh_cpu_gdb_write_register;
> #ifndef CONFIG_USER_ONLY
> cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
> + dc->vmsd = &vmstate_sh_cpu;
> #endif
> cc->disas_set_info = superh_cpu_disas_set_info;
>
> cc->gdb_num_core_regs = 59;
> -
> - dc->vmsd = &vmstate_sh_cpu;
> cc->tcg_ops = &superh_tcg_ops;
> }
>
> diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
> index 0258884f845..a74ac7b6140 100644
> --- a/target/unicore32/cpu.c
> +++ b/target/unicore32/cpu.c
> @@ -115,10 +115,12 @@ static void uc32_cpu_initfn(Object *obj)
> #endif
> }
>
> +#ifndef CONFIG_USER_ONLY
> static const VMStateDescription vmstate_uc32_cpu = {
> .name = "cpu",
> .unmigratable = 1,
> };
> +#endif
>
> #include "hw/core/tcg-cpu-ops.h"
>
> @@ -146,7 +148,9 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
> cc->dump_state = uc32_cpu_dump_state;
> cc->set_pc = uc32_cpu_set_pc;
> cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
> +#ifndef CONFIG_USER_ONLY
> dc->vmsd = &vmstate_uc32_cpu;
> +#endif
> cc->tcg_ops = &uc32_tcg_ops;
> }
>
> diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
> index e2b2c7a71c1..a66527e2d45 100644
> --- a/target/xtensa/cpu.c
> +++ b/target/xtensa/cpu.c
> @@ -176,10 +176,12 @@ static void xtensa_cpu_initfn(Object *obj)
> #endif
> }
>
> +#ifndef CONFIG_USER_ONLY
> static const VMStateDescription vmstate_xtensa_cpu = {
> .name = "cpu",
> .unmigratable = 1,
> };
> +#endif
>
> #include "hw/core/tcg-cpu-ops.h"
>
> @@ -216,9 +218,9 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
> cc->gdb_stop_before_watchpoint = true;
> #ifndef CONFIG_USER_ONLY
> cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
> + dc->vmsd = &vmstate_xtensa_cpu;
> #endif
> cc->disas_set_info = xtensa_cpu_disas_set_info;
> - dc->vmsd = &vmstate_xtensa_cpu;
> cc->tcg_ops = &xtensa_tcg_ops;
> }
>
> --
> 2.26.3
>
--
Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH v6 06/18] cpu: Assert DeviceClass::vmsd is NULL on user emulation
@ 2021-04-26 16:15 ` Dr. David Alan Gilbert
0 siblings, 0 replies; 51+ messages in thread
From: Dr. David Alan Gilbert @ 2021-04-26 16:15 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, qemu-riscv, Juan Quintela, Peter Maydell,
Claudio Fontana, qemu-arm, Eduardo Habkost, qemu-ppc,
Richard Henderson, Laurent Vivier, qemu-s390x, Marcel Apfelbaum,
Yoshinori Sato, Guan Xuetao, Max Filippov
* Philippe Mathieu-Daudé (f4bug@amsat.org) wrote:
> Migration is specific to system emulation.
>
> Restrict current DeviceClass::vmsd to sysemu using #ifdef'ry,
> and assert in cpu_exec_realizefn() that dc->vmsd not set under
> user emulation.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> cpu.c | 1 +
> target/sh4/cpu.c | 5 +++--
> target/unicore32/cpu.c | 4 ++++
> target/xtensa/cpu.c | 4 +++-
> 4 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/cpu.c b/cpu.c
> index bfbe5a66f95..4fed04219df 100644
> --- a/cpu.c
> +++ b/cpu.c
> @@ -138,6 +138,7 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
> #endif /* CONFIG_TCG */
>
> #ifdef CONFIG_USER_ONLY
> + assert(qdev_get_vmsd(DEVICE(cpu)) == NULL);
Why not make that:
assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
qdev_get_vmsd(DEVICE(cpu)->unmigratable)
then you don't have to worry about the changes below.
Dave
> assert(cc->vmsd == NULL);
> #else
> if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
> diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
> index ac65c88f1f8..35d4251aaf3 100644
> --- a/target/sh4/cpu.c
> +++ b/target/sh4/cpu.c
> @@ -218,10 +218,12 @@ static void superh_cpu_initfn(Object *obj)
> env->movcal_backup_tail = &(env->movcal_backup);
> }
>
> +#ifndef CONFIG_USER_ONLY
> static const VMStateDescription vmstate_sh_cpu = {
> .name = "cpu",
> .unmigratable = 1,
> };
> +#endif
>
> #include "hw/core/tcg-cpu-ops.h"
>
> @@ -257,12 +259,11 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
> cc->gdb_write_register = superh_cpu_gdb_write_register;
> #ifndef CONFIG_USER_ONLY
> cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
> + dc->vmsd = &vmstate_sh_cpu;
> #endif
> cc->disas_set_info = superh_cpu_disas_set_info;
>
> cc->gdb_num_core_regs = 59;
> -
> - dc->vmsd = &vmstate_sh_cpu;
> cc->tcg_ops = &superh_tcg_ops;
> }
>
> diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
> index 0258884f845..a74ac7b6140 100644
> --- a/target/unicore32/cpu.c
> +++ b/target/unicore32/cpu.c
> @@ -115,10 +115,12 @@ static void uc32_cpu_initfn(Object *obj)
> #endif
> }
>
> +#ifndef CONFIG_USER_ONLY
> static const VMStateDescription vmstate_uc32_cpu = {
> .name = "cpu",
> .unmigratable = 1,
> };
> +#endif
>
> #include "hw/core/tcg-cpu-ops.h"
>
> @@ -146,7 +148,9 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
> cc->dump_state = uc32_cpu_dump_state;
> cc->set_pc = uc32_cpu_set_pc;
> cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
> +#ifndef CONFIG_USER_ONLY
> dc->vmsd = &vmstate_uc32_cpu;
> +#endif
> cc->tcg_ops = &uc32_tcg_ops;
> }
>
> diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
> index e2b2c7a71c1..a66527e2d45 100644
> --- a/target/xtensa/cpu.c
> +++ b/target/xtensa/cpu.c
> @@ -176,10 +176,12 @@ static void xtensa_cpu_initfn(Object *obj)
> #endif
> }
>
> +#ifndef CONFIG_USER_ONLY
> static const VMStateDescription vmstate_xtensa_cpu = {
> .name = "cpu",
> .unmigratable = 1,
> };
> +#endif
>
> #include "hw/core/tcg-cpu-ops.h"
>
> @@ -216,9 +218,9 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
> cc->gdb_stop_before_watchpoint = true;
> #ifndef CONFIG_USER_ONLY
> cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
> + dc->vmsd = &vmstate_xtensa_cpu;
> #endif
> cc->disas_set_info = xtensa_cpu_disas_set_info;
> - dc->vmsd = &vmstate_xtensa_cpu;
> cc->tcg_ops = &xtensa_tcg_ops;
> }
>
> --
> 2.26.3
>
--
Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH v6 06/18] cpu: Assert DeviceClass::vmsd is NULL on user emulation
2021-04-26 16:15 ` Dr. David Alan Gilbert
(?)
@ 2021-04-26 16:50 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-26 16:50 UTC (permalink / raw)
To: Dr. David Alan Gilbert
Cc: Peter Maydell, qemu-riscv, Eduardo Habkost, Yoshinori Sato,
Juan Quintela, Richard Henderson, qemu-devel, Laurent Vivier,
Max Filippov, qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana,
Guan Xuetao
On 4/26/21 6:15 PM, Dr. David Alan Gilbert wrote:
> * Philippe Mathieu-Daudé (f4bug@amsat.org) wrote:
>> Migration is specific to system emulation.
>>
>> Restrict current DeviceClass::vmsd to sysemu using #ifdef'ry,
>> and assert in cpu_exec_realizefn() that dc->vmsd not set under
>> user emulation.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>> cpu.c | 1 +
>> target/sh4/cpu.c | 5 +++--
>> target/unicore32/cpu.c | 4 ++++
>> target/xtensa/cpu.c | 4 +++-
>> 4 files changed, 11 insertions(+), 3 deletions(-)
>>
>> diff --git a/cpu.c b/cpu.c
>> index bfbe5a66f95..4fed04219df 100644
>> --- a/cpu.c
>> +++ b/cpu.c
>> @@ -138,6 +138,7 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
>> #endif /* CONFIG_TCG */
>>
>> #ifdef CONFIG_USER_ONLY
>> + assert(qdev_get_vmsd(DEVICE(cpu)) == NULL);
>
> Why not make that:
> assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
> qdev_get_vmsd(DEVICE(cpu)->unmigratable)
>
> then you don't have to worry about the changes below.
Thanks for the tip! For my defense the VMStateDescription
fields aren't documented at all ;)
>
> Dave
>
>> assert(cc->vmsd == NULL);
>> #else
>> if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v6 07/18] cpu: Rename CPUClass vmsd -> legacy_vmsd
2021-04-22 19:38 ` Philippe Mathieu-Daudé
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Sagar Karandikar, David Hildenbrand,
Anthony Green, Mark Cave-Ayland, Thomas Huth,
Philippe Mathieu-Daudé,
Alistair Francis, Juan Quintela, Claudio Fontana, Palmer Dabbelt,
Artyom Tarasenko, Aleksandar Rikalo, Eduardo Habkost,
Richard Henderson, Dr. David Alan Gilbert, Greg Kurz, qemu-s390x,
qemu-arm, Michael Rolnik, David Gibson, qemu-riscv,
Bastian Koppelmann, Cornelia Huck, Laurent Vivier, Michael Walle,
qemu-ppc, Paolo Bonzini, Aurelien Jarno
Quoting Peter Maydell [*]:
There are two ways to handle migration for
a CPU object:
(1) like any other device, so it has a dc->vmsd that covers
migration for the whole object. As usual for objects that are a
subclass of a parent that has state, the first entry in the
VMStateDescription field list is VMSTATE_CPU(), which migrates
the cpu_common fields, followed by whatever the CPU's own migration
fields are.
(2) a backwards-compatible mechanism for CPUs that were
originally migrated using manual "write fields to the migration
stream structures". The on-the-wire migration format
for those is based on the 'env' pointer (which isn't a QOM object),
and the cpu_common part of the migration data is elsewhere.
cpu_exec_realizefn() handles both possibilities:
* for type 1, dc->vmsd is set and cc->vmsd is not,
so cpu_exec_realizefn() does nothing, and the standard
"register dc->vmsd for a device" code does everything needed
* for type 2, dc->vmsd is NULL and so we register the
vmstate_cpu_common directly to handle the cpu-common fields,
and the cc->vmsd to handle the per-CPU stuff
You can't change a CPU from one type to the other without breaking
migration compatibility, which is why some guest architectures
are stuck on the cc->vmsd form. New targets should use dc->vmsd.
To avoid new targets to start using type (2), rename cc->vmsd as
cc->legacy_vmsd. The correct field to implement is dc->vmsd (the
DeviceClass one).
See also commit b170fce3dd0 ("cpu: Register VMStateDescription
through CPUState") for historic background.
[*] https://www.mail-archive.com/qemu-devel@nongnu.org/msg800849.html
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 5 +++--
cpu.c | 12 ++++++------
target/arm/cpu.c | 2 +-
target/avr/cpu.c | 2 +-
target/i386/cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/moxie/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 2 +-
12 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 08af2c383a5..10dd16531ba 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -122,7 +122,8 @@ struct AccelCPUClass;
* 32-bit VM coredump.
* @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
* note to a 32-bit VM coredump.
- * @vmsd: State description for migration.
+ * @legacy_vmsd: Legacy state description for migration.
+ * Do not use in new targets, use #DeviceClass::vmsd instead.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
* @gdb_core_xml_file: File name for core registers GDB XML description.
* @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
@@ -177,7 +178,7 @@ struct CPUClass {
int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque);
- const VMStateDescription *vmsd;
+ const VMStateDescription *legacy_vmsd;
const char *gdb_core_xml_file;
gchar * (*gdb_arch_name)(CPUState *cpu);
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
diff --git a/cpu.c b/cpu.c
index 4fed04219df..c1c9cdebc3e 100644
--- a/cpu.c
+++ b/cpu.c
@@ -139,13 +139,13 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
#ifdef CONFIG_USER_ONLY
assert(qdev_get_vmsd(DEVICE(cpu)) == NULL);
- assert(cc->vmsd == NULL);
+ assert(cc->legacy_vmsd == NULL);
#else
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
}
- if (cc->vmsd != NULL) {
- vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
+ if (cc->legacy_vmsd != NULL) {
+ vmstate_register(NULL, cpu->cpu_index, cc->legacy_vmsd, cpu);
}
#endif /* CONFIG_USER_ONLY */
}
@@ -155,10 +155,10 @@ void cpu_exec_unrealizefn(CPUState *cpu)
CPUClass *cc = CPU_GET_CLASS(cpu);
#ifdef CONFIG_USER_ONLY
- assert(cc->vmsd == NULL);
+ assert(cc->legacy_vmsd == NULL);
#else
- if (cc->vmsd != NULL) {
- vmstate_unregister(NULL, cc->vmsd, cpu);
+ if (cc->legacy_vmsd != NULL) {
+ vmstate_unregister(NULL, cc->legacy_vmsd, cpu);
}
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 0dd623e5909..3062e8c702e 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1982,7 +1982,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
- cc->vmsd = &vmstate_arm_cpu;
+ cc->legacy_vmsd = &vmstate_arm_cpu;
cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
cc->write_elf64_note = arm_cpu_write_elf64_note;
cc->write_elf32_note = arm_cpu_write_elf32_note;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 0f4596932ba..37a8ebcc86f 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -213,7 +213,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
- cc->vmsd = &vms_avr_cpu;
+ cc->legacy_vmsd = &vms_avr_cpu;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->gdb_read_register = avr_cpu_gdb_read_register;
cc->gdb_write_register = avr_cpu_gdb_write_register;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ad99cad0e7c..f85ae518dd4 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7431,7 +7431,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
cc->write_elf32_note = x86_cpu_write_elf32_note;
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
- cc->vmsd = &vmstate_x86_cpu;
+ cc->legacy_vmsd = &vmstate_x86_cpu;
#endif /* !CONFIG_USER_ONLY */
cc->gdb_arch_name = x86_gdb_arch_name;
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index c23d72874c0..c0388142528 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -241,7 +241,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = lm32_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_lm32_cpu;
+ cc->legacy_vmsd = &vmstate_lm32_cpu;
#endif
cc->gdb_num_core_regs = 32 + 7;
cc->gdb_stop_before_watchpoint = true;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index dce1e166bde..11604954504 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -720,7 +720,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_mips_cpu;
+ cc->legacy_vmsd = &vmstate_mips_cpu;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
cc->gdb_num_core_regs = 73;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 83bec34d36c..3c81a088eaa 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -122,7 +122,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = moxie_cpu_set_pc;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_moxie_cpu;
+ cc->legacy_vmsd = &vmstate_moxie_cpu;
#endif
cc->disas_set_info = moxie_cpu_disas_set_info;
cc->tcg_ops = &moxie_tcg_ops;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7d6ed80f6b6..70be7e8287a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -624,7 +624,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
/* For now, mark unmigratable: */
- cc->vmsd = &vmstate_riscv_cpu;
+ cc->legacy_vmsd = &vmstate_riscv_cpu;
cc->write_elf64_note = riscv_cpu_write_elf64_note;
cc->write_elf32_note = riscv_cpu_write_elf32_note;
#endif
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index d35eb39a1bb..197c4b87f30 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -517,7 +517,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_s390_cpu;
+ cc->legacy_vmsd = &vmstate_s390_cpu;
cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
#endif
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index aece2c7dc83..ba497561bfa 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -889,7 +889,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = sparc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_sparc_cpu;
+ cc->legacy_vmsd = &vmstate_sparc_cpu;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index c03a7c4f526..110a68a867e 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10920,7 +10920,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = ppc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_ppc_cpu;
+ cc->legacy_vmsd = &vmstate_ppc_cpu;
#endif
#if defined(CONFIG_SOFTMMU)
cc->write_elf64_note = ppc64_cpu_write_elf64_note;
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v6 07/18] cpu: Rename CPUClass vmsd -> legacy_vmsd
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, qemu-riscv, Juan Quintela, Peter Maydell,
Claudio Fontana, qemu-arm, Eduardo Habkost, qemu-ppc,
Richard Henderson, Laurent Vivier, qemu-s390x,
Philippe Mathieu-Daudé,
Marcel Apfelbaum, Michael Rolnik, Paolo Bonzini, Michael Walle,
Aurelien Jarno, Jiaxun Yang, Aleksandar Rikalo, Anthony Green,
David Gibson, Greg Kurz, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann, David Hildenbrand,
Cornelia Huck, Thomas Huth, Mark Cave-Ayland, Artyom Tarasenko
Quoting Peter Maydell [*]:
There are two ways to handle migration for
a CPU object:
(1) like any other device, so it has a dc->vmsd that covers
migration for the whole object. As usual for objects that are a
subclass of a parent that has state, the first entry in the
VMStateDescription field list is VMSTATE_CPU(), which migrates
the cpu_common fields, followed by whatever the CPU's own migration
fields are.
(2) a backwards-compatible mechanism for CPUs that were
originally migrated using manual "write fields to the migration
stream structures". The on-the-wire migration format
for those is based on the 'env' pointer (which isn't a QOM object),
and the cpu_common part of the migration data is elsewhere.
cpu_exec_realizefn() handles both possibilities:
* for type 1, dc->vmsd is set and cc->vmsd is not,
so cpu_exec_realizefn() does nothing, and the standard
"register dc->vmsd for a device" code does everything needed
* for type 2, dc->vmsd is NULL and so we register the
vmstate_cpu_common directly to handle the cpu-common fields,
and the cc->vmsd to handle the per-CPU stuff
You can't change a CPU from one type to the other without breaking
migration compatibility, which is why some guest architectures
are stuck on the cc->vmsd form. New targets should use dc->vmsd.
To avoid new targets to start using type (2), rename cc->vmsd as
cc->legacy_vmsd. The correct field to implement is dc->vmsd (the
DeviceClass one).
See also commit b170fce3dd0 ("cpu: Register VMStateDescription
through CPUState") for historic background.
[*] https://www.mail-archive.com/qemu-devel@nongnu.org/msg800849.html
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 5 +++--
cpu.c | 12 ++++++------
target/arm/cpu.c | 2 +-
target/avr/cpu.c | 2 +-
target/i386/cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/moxie/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 2 +-
12 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 08af2c383a5..10dd16531ba 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -122,7 +122,8 @@ struct AccelCPUClass;
* 32-bit VM coredump.
* @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
* note to a 32-bit VM coredump.
- * @vmsd: State description for migration.
+ * @legacy_vmsd: Legacy state description for migration.
+ * Do not use in new targets, use #DeviceClass::vmsd instead.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
* @gdb_core_xml_file: File name for core registers GDB XML description.
* @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
@@ -177,7 +178,7 @@ struct CPUClass {
int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque);
- const VMStateDescription *vmsd;
+ const VMStateDescription *legacy_vmsd;
const char *gdb_core_xml_file;
gchar * (*gdb_arch_name)(CPUState *cpu);
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
diff --git a/cpu.c b/cpu.c
index 4fed04219df..c1c9cdebc3e 100644
--- a/cpu.c
+++ b/cpu.c
@@ -139,13 +139,13 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
#ifdef CONFIG_USER_ONLY
assert(qdev_get_vmsd(DEVICE(cpu)) == NULL);
- assert(cc->vmsd == NULL);
+ assert(cc->legacy_vmsd == NULL);
#else
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
}
- if (cc->vmsd != NULL) {
- vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
+ if (cc->legacy_vmsd != NULL) {
+ vmstate_register(NULL, cpu->cpu_index, cc->legacy_vmsd, cpu);
}
#endif /* CONFIG_USER_ONLY */
}
@@ -155,10 +155,10 @@ void cpu_exec_unrealizefn(CPUState *cpu)
CPUClass *cc = CPU_GET_CLASS(cpu);
#ifdef CONFIG_USER_ONLY
- assert(cc->vmsd == NULL);
+ assert(cc->legacy_vmsd == NULL);
#else
- if (cc->vmsd != NULL) {
- vmstate_unregister(NULL, cc->vmsd, cpu);
+ if (cc->legacy_vmsd != NULL) {
+ vmstate_unregister(NULL, cc->legacy_vmsd, cpu);
}
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 0dd623e5909..3062e8c702e 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1982,7 +1982,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
- cc->vmsd = &vmstate_arm_cpu;
+ cc->legacy_vmsd = &vmstate_arm_cpu;
cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
cc->write_elf64_note = arm_cpu_write_elf64_note;
cc->write_elf32_note = arm_cpu_write_elf32_note;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 0f4596932ba..37a8ebcc86f 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -213,7 +213,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
- cc->vmsd = &vms_avr_cpu;
+ cc->legacy_vmsd = &vms_avr_cpu;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->gdb_read_register = avr_cpu_gdb_read_register;
cc->gdb_write_register = avr_cpu_gdb_write_register;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ad99cad0e7c..f85ae518dd4 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7431,7 +7431,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
cc->write_elf32_note = x86_cpu_write_elf32_note;
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
- cc->vmsd = &vmstate_x86_cpu;
+ cc->legacy_vmsd = &vmstate_x86_cpu;
#endif /* !CONFIG_USER_ONLY */
cc->gdb_arch_name = x86_gdb_arch_name;
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index c23d72874c0..c0388142528 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -241,7 +241,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = lm32_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_lm32_cpu;
+ cc->legacy_vmsd = &vmstate_lm32_cpu;
#endif
cc->gdb_num_core_regs = 32 + 7;
cc->gdb_stop_before_watchpoint = true;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index dce1e166bde..11604954504 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -720,7 +720,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_mips_cpu;
+ cc->legacy_vmsd = &vmstate_mips_cpu;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
cc->gdb_num_core_regs = 73;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 83bec34d36c..3c81a088eaa 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -122,7 +122,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = moxie_cpu_set_pc;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_moxie_cpu;
+ cc->legacy_vmsd = &vmstate_moxie_cpu;
#endif
cc->disas_set_info = moxie_cpu_disas_set_info;
cc->tcg_ops = &moxie_tcg_ops;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7d6ed80f6b6..70be7e8287a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -624,7 +624,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
/* For now, mark unmigratable: */
- cc->vmsd = &vmstate_riscv_cpu;
+ cc->legacy_vmsd = &vmstate_riscv_cpu;
cc->write_elf64_note = riscv_cpu_write_elf64_note;
cc->write_elf32_note = riscv_cpu_write_elf32_note;
#endif
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index d35eb39a1bb..197c4b87f30 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -517,7 +517,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_s390_cpu;
+ cc->legacy_vmsd = &vmstate_s390_cpu;
cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
#endif
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index aece2c7dc83..ba497561bfa 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -889,7 +889,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = sparc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_sparc_cpu;
+ cc->legacy_vmsd = &vmstate_sparc_cpu;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index c03a7c4f526..110a68a867e 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10920,7 +10920,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = ppc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_ppc_cpu;
+ cc->legacy_vmsd = &vmstate_ppc_cpu;
#endif
#if defined(CONFIG_SOFTMMU)
cc->write_elf64_note = ppc64_cpu_write_elf64_note;
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v6 07/18] cpu: Rename CPUClass vmsd -> legacy_vmsd
2021-04-22 19:38 ` Philippe Mathieu-Daudé
@ 2021-04-23 1:11 ` Richard Henderson
-1 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2021-04-23 1:11 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, Sagar Karandikar, David Hildenbrand,
Anthony Green, Mark Cave-Ayland, Thomas Huth, Alistair Francis,
Juan Quintela, Claudio Fontana, Palmer Dabbelt, Artyom Tarasenko,
Aleksandar Rikalo, Eduardo Habkost, Dr. David Alan Gilbert,
Greg Kurz, qemu-s390x, qemu-arm, Michael Rolnik, David Gibson,
qemu-riscv, Bastian Koppelmann, Cornelia Huck, Laurent Vivier,
Michael Walle, qemu-ppc, Paolo Bonzini, Aurelien Jarno
On 4/22/21 12:38 PM, Philippe Mathieu-Daudé wrote:
> Quoting Peter Maydell [*]:
>
> There are two ways to handle migration for
> a CPU object:
>
> (1) like any other device, so it has a dc->vmsd that covers
> migration for the whole object. As usual for objects that are a
> subclass of a parent that has state, the first entry in the
> VMStateDescription field list is VMSTATE_CPU(), which migrates
> the cpu_common fields, followed by whatever the CPU's own migration
> fields are.
>
> (2) a backwards-compatible mechanism for CPUs that were
> originally migrated using manual "write fields to the migration
> stream structures". The on-the-wire migration format
> for those is based on the 'env' pointer (which isn't a QOM object),
> and the cpu_common part of the migration data is elsewhere.
>
> cpu_exec_realizefn() handles both possibilities:
>
> * for type 1, dc->vmsd is set and cc->vmsd is not,
> so cpu_exec_realizefn() does nothing, and the standard
> "register dc->vmsd for a device" code does everything needed
>
> * for type 2, dc->vmsd is NULL and so we register the
> vmstate_cpu_common directly to handle the cpu-common fields,
> and the cc->vmsd to handle the per-CPU stuff
>
> You can't change a CPU from one type to the other without breaking
> migration compatibility, which is why some guest architectures
> are stuck on the cc->vmsd form. New targets should use dc->vmsd.
>
> To avoid new targets to start using type (2), rename cc->vmsd as
> cc->legacy_vmsd. The correct field to implement is dc->vmsd (the
> DeviceClass one).
>
> See also commit b170fce3dd0 ("cpu: Register VMStateDescription
> through CPUState") for historic background.
>
> [*]https://www.mail-archive.com/qemu-devel@nongnu.org/msg800849.html
>
> Cc: Peter Maydell<peter.maydell@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> include/hw/core/cpu.h | 5 +++--
> cpu.c | 12 ++++++------
> target/arm/cpu.c | 2 +-
> target/avr/cpu.c | 2 +-
> target/i386/cpu.c | 2 +-
> target/lm32/cpu.c | 2 +-
> target/mips/cpu.c | 2 +-
> target/moxie/cpu.c | 2 +-
> target/riscv/cpu.c | 2 +-
> target/s390x/cpu.c | 2 +-
> target/sparc/cpu.c | 2 +-
> target/ppc/translate_init.c.inc | 2 +-
> 12 files changed, 19 insertions(+), 18 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH v6 07/18] cpu: Rename CPUClass vmsd -> legacy_vmsd
@ 2021-04-23 1:11 ` Richard Henderson
0 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2021-04-23 1:11 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Dr. David Alan Gilbert, qemu-riscv, Juan Quintela, Peter Maydell,
Claudio Fontana, qemu-arm, Eduardo Habkost, qemu-ppc,
Laurent Vivier, qemu-s390x, Marcel Apfelbaum, Michael Rolnik,
Paolo Bonzini, Michael Walle, Aurelien Jarno, Jiaxun Yang,
Aleksandar Rikalo, Anthony Green, David Gibson, Greg Kurz,
Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, David Hildenbrand, Cornelia Huck,
Thomas Huth, Mark Cave-Ayland, Artyom Tarasenko
On 4/22/21 12:38 PM, Philippe Mathieu-Daudé wrote:
> Quoting Peter Maydell [*]:
>
> There are two ways to handle migration for
> a CPU object:
>
> (1) like any other device, so it has a dc->vmsd that covers
> migration for the whole object. As usual for objects that are a
> subclass of a parent that has state, the first entry in the
> VMStateDescription field list is VMSTATE_CPU(), which migrates
> the cpu_common fields, followed by whatever the CPU's own migration
> fields are.
>
> (2) a backwards-compatible mechanism for CPUs that were
> originally migrated using manual "write fields to the migration
> stream structures". The on-the-wire migration format
> for those is based on the 'env' pointer (which isn't a QOM object),
> and the cpu_common part of the migration data is elsewhere.
>
> cpu_exec_realizefn() handles both possibilities:
>
> * for type 1, dc->vmsd is set and cc->vmsd is not,
> so cpu_exec_realizefn() does nothing, and the standard
> "register dc->vmsd for a device" code does everything needed
>
> * for type 2, dc->vmsd is NULL and so we register the
> vmstate_cpu_common directly to handle the cpu-common fields,
> and the cc->vmsd to handle the per-CPU stuff
>
> You can't change a CPU from one type to the other without breaking
> migration compatibility, which is why some guest architectures
> are stuck on the cc->vmsd form. New targets should use dc->vmsd.
>
> To avoid new targets to start using type (2), rename cc->vmsd as
> cc->legacy_vmsd. The correct field to implement is dc->vmsd (the
> DeviceClass one).
>
> See also commit b170fce3dd0 ("cpu: Register VMStateDescription
> through CPUState") for historic background.
>
> [*]https://www.mail-archive.com/qemu-devel@nongnu.org/msg800849.html
>
> Cc: Peter Maydell<peter.maydell@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> include/hw/core/cpu.h | 5 +++--
> cpu.c | 12 ++++++------
> target/arm/cpu.c | 2 +-
> target/avr/cpu.c | 2 +-
> target/i386/cpu.c | 2 +-
> target/lm32/cpu.c | 2 +-
> target/mips/cpu.c | 2 +-
> target/moxie/cpu.c | 2 +-
> target/riscv/cpu.c | 2 +-
> target/s390x/cpu.c | 2 +-
> target/sparc/cpu.c | 2 +-
> target/ppc/translate_init.c.inc | 2 +-
> 12 files changed, 19 insertions(+), 18 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v6 08/18] cpu/{avr, lm32, moxie}: Set DeviceClass vmsd field (not CPUClass one)
2021-04-22 19:38 ` Philippe Mathieu-Daudé
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Michael Walle, qemu-riscv, Eduardo Habkost,
Juan Quintela, Anthony Green, Richard Henderson,
Dr. David Alan Gilbert, Laurent Vivier, qemu-s390x, qemu-arm,
qemu-ppc, Claudio Fontana, Michael Rolnik,
Philippe Mathieu-Daudé
See rationale in previous commit. Targets should use the vmsd field
of DeviceClass, not CPUClass. As migration is not important on the
avr/lm32/moxie targets, break the migration compatibility and set
the DeviceClass vmsd field.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/avr/cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/moxie/cpu.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 37a8ebcc86f..3353bcb9fc7 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -213,7 +213,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
- cc->legacy_vmsd = &vms_avr_cpu;
+ dc->vmsd = &vms_avr_cpu;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->gdb_read_register = avr_cpu_gdb_read_register;
cc->gdb_write_register = avr_cpu_gdb_write_register;
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index c0388142528..e27c1a8bc97 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -241,7 +241,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = lm32_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
- cc->legacy_vmsd = &vmstate_lm32_cpu;
+ dc->vmsd = &vmstate_lm32_cpu;
#endif
cc->gdb_num_core_regs = 32 + 7;
cc->gdb_stop_before_watchpoint = true;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 3c81a088eaa..e5da3fa3f17 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -122,7 +122,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = moxie_cpu_set_pc;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug;
- cc->legacy_vmsd = &vmstate_moxie_cpu;
+ dc->vmsd = &vmstate_moxie_cpu;
#endif
cc->disas_set_info = moxie_cpu_disas_set_info;
cc->tcg_ops = &moxie_tcg_ops;
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v6 08/18] cpu/{avr, lm32, moxie}: Set DeviceClass vmsd field (not CPUClass one)
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, qemu-riscv, Juan Quintela, Peter Maydell,
Claudio Fontana, qemu-arm, Eduardo Habkost, qemu-ppc,
Richard Henderson, Laurent Vivier, qemu-s390x,
Philippe Mathieu-Daudé,
Michael Rolnik, Michael Walle, Anthony Green
See rationale in previous commit. Targets should use the vmsd field
of DeviceClass, not CPUClass. As migration is not important on the
avr/lm32/moxie targets, break the migration compatibility and set
the DeviceClass vmsd field.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/avr/cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/moxie/cpu.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 37a8ebcc86f..3353bcb9fc7 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -213,7 +213,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
- cc->legacy_vmsd = &vms_avr_cpu;
+ dc->vmsd = &vms_avr_cpu;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->gdb_read_register = avr_cpu_gdb_read_register;
cc->gdb_write_register = avr_cpu_gdb_write_register;
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index c0388142528..e27c1a8bc97 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -241,7 +241,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = lm32_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
- cc->legacy_vmsd = &vmstate_lm32_cpu;
+ dc->vmsd = &vmstate_lm32_cpu;
#endif
cc->gdb_num_core_regs = 32 + 7;
cc->gdb_stop_before_watchpoint = true;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 3c81a088eaa..e5da3fa3f17 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -122,7 +122,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = moxie_cpu_set_pc;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug;
- cc->legacy_vmsd = &vmstate_moxie_cpu;
+ dc->vmsd = &vmstate_moxie_cpu;
#endif
cc->disas_set_info = moxie_cpu_disas_set_info;
cc->tcg_ops = &moxie_tcg_ops;
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v6 08/18] cpu/{avr, lm32, moxie}: Set DeviceClass vmsd field (not CPUClass one)
2021-04-22 19:38 ` Philippe Mathieu-Daudé
@ 2021-04-23 1:16 ` Richard Henderson
-1 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2021-04-23 1:16 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, Michael Walle, qemu-riscv, Eduardo Habkost,
Juan Quintela, Anthony Green, Dr. David Alan Gilbert,
Laurent Vivier, qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana,
Michael Rolnik
On 4/22/21 12:38 PM, Philippe Mathieu-Daudé wrote:
> See rationale in previous commit. Targets should use the vmsd field
> of DeviceClass, not CPUClass. As migration is not important on the
> avr/lm32/moxie targets, break the migration compatibility and set
> the DeviceClass vmsd field.
>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> target/avr/cpu.c | 2 +-
> target/lm32/cpu.c | 2 +-
> target/moxie/cpu.c | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
Do you not have to increment the vmstate versions?
Though I can't see how the version numbers would even get compared, since we're
looking for them in different locations?
r~
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH v6 08/18] cpu/{avr, lm32, moxie}: Set DeviceClass vmsd field (not CPUClass one)
@ 2021-04-23 1:16 ` Richard Henderson
0 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2021-04-23 1:16 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Dr. David Alan Gilbert, qemu-riscv, Juan Quintela, Peter Maydell,
Claudio Fontana, qemu-arm, Eduardo Habkost, qemu-ppc,
Laurent Vivier, qemu-s390x, Michael Rolnik, Michael Walle,
Anthony Green
On 4/22/21 12:38 PM, Philippe Mathieu-Daudé wrote:
> See rationale in previous commit. Targets should use the vmsd field
> of DeviceClass, not CPUClass. As migration is not important on the
> avr/lm32/moxie targets, break the migration compatibility and set
> the DeviceClass vmsd field.
>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> target/avr/cpu.c | 2 +-
> target/lm32/cpu.c | 2 +-
> target/moxie/cpu.c | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
Do you not have to increment the vmstate versions?
Though I can't see how the version numbers would even get compared, since we're
looking for them in different locations?
r~
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH v6 08/18] cpu/{avr, lm32, moxie}: Set DeviceClass vmsd field (not CPUClass one)
2021-04-23 1:16 ` Richard Henderson
@ 2021-05-17 5:27 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-05-17 5:27 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Peter Maydell, qemu-riscv, Eduardo Habkost, Juan Quintela,
qemu-s390x, Anthony Green, Dr. David Alan Gilbert,
Laurent Vivier, Michael Walle, qemu-arm, qemu-ppc,
Claudio Fontana, Michael Rolnik
On 4/23/21 3:16 AM, Richard Henderson wrote:
> On 4/22/21 12:38 PM, Philippe Mathieu-Daudé wrote:
>> See rationale in previous commit. Targets should use the vmsd field
>> of DeviceClass, not CPUClass. As migration is not important on the
>> avr/lm32/moxie targets, break the migration compatibility and set
>> the DeviceClass vmsd field.
>>
>> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
>> ---
>> target/avr/cpu.c | 2 +-
>> target/lm32/cpu.c | 2 +-
>> target/moxie/cpu.c | 2 +-
>> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> Do you not have to increment the vmstate versions?
>
> Though I can't see how the version numbers would even get compared,
> since we're looking for them in different locations?
Yes, I am not sure how that will work. Anyway, better safe than sorry!
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH v6 08/18] cpu/{avr, lm32, moxie}: Set DeviceClass vmsd field (not CPUClass one)
@ 2021-05-17 5:27 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-05-17 5:27 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Peter Maydell, Michael Walle, qemu-riscv, Eduardo Habkost,
Juan Quintela, Anthony Green, Dr. David Alan Gilbert,
Laurent Vivier, qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana,
Michael Rolnik
On 4/23/21 3:16 AM, Richard Henderson wrote:
> On 4/22/21 12:38 PM, Philippe Mathieu-Daudé wrote:
>> See rationale in previous commit. Targets should use the vmsd field
>> of DeviceClass, not CPUClass. As migration is not important on the
>> avr/lm32/moxie targets, break the migration compatibility and set
>> the DeviceClass vmsd field.
>>
>> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
>> ---
>> target/avr/cpu.c | 2 +-
>> target/lm32/cpu.c | 2 +-
>> target/moxie/cpu.c | 2 +-
>> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> Do you not have to increment the vmstate versions?
>
> Though I can't see how the version numbers would even get compared,
> since we're looking for them in different locations?
Yes, I am not sure how that will work. Anyway, better safe than sorry!
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v6 09/18] cpu: Introduce SysemuCPUOps structure
2021-04-22 19:38 ` Philippe Mathieu-Daudé
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Cornelia Huck, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland, Thomas Huth,
Philippe Mathieu-Daudé,
Max Filippov, Alistair Francis, Edgar E. Iglesias, Guan Xuetao,
Marek Vasut, Yoshinori Sato, Juan Quintela, Claudio Fontana,
Palmer Dabbelt, Artyom Tarasenko, Aleksandar Rikalo,
Eduardo Habkost, Richard Henderson, Dr. David Alan Gilbert,
Greg Kurz, qemu-s390x, qemu-arm, Michael Rolnik, Stafford Horne,
David Gibson, qemu-riscv, Bastian Koppelmann, Chris Wulff,
Laurent Vivier, Michael Walle, qemu-ppc, Paolo Bonzini,
Aurelien Jarno
Introduce a structure to hold handler specific to sysemu.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 5 +++++
include/hw/core/sysemu-cpu-ops.h | 21 +++++++++++++++++++++
target/alpha/cpu.c | 6 ++++++
target/arm/cpu.c | 6 ++++++
target/avr/cpu.c | 4 ++++
target/cris/cpu.c | 6 ++++++
target/hppa/cpu.c | 6 ++++++
target/i386/cpu.c | 6 ++++++
target/lm32/cpu.c | 6 ++++++
target/m68k/cpu.c | 6 ++++++
target/microblaze/cpu.c | 6 ++++++
target/mips/cpu.c | 6 ++++++
target/moxie/cpu.c | 4 ++++
target/nios2/cpu.c | 6 ++++++
target/openrisc/cpu.c | 6 ++++++
target/riscv/cpu.c | 6 ++++++
target/rx/cpu.c | 8 ++++++++
target/s390x/cpu.c | 6 ++++++
target/sh4/cpu.c | 4 ++++
target/sparc/cpu.c | 6 ++++++
target/tricore/cpu.c | 4 ++++
target/unicore32/cpu.c | 4 ++++
target/xtensa/cpu.c | 4 ++++
target/ppc/translate_init.c.inc | 6 ++++++
24 files changed, 148 insertions(+)
create mode 100644 include/hw/core/sysemu-cpu-ops.h
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 10dd16531ba..23b718a4a51 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -80,6 +80,8 @@ struct TCGCPUOps;
/* see accel-cpu.h */
struct AccelCPUClass;
+#include "hw/core/sysemu-cpu-ops.h"
+
/**
* CPUClass:
* @class_by_name: Callback to map -cpu command line model name to an
@@ -191,6 +193,9 @@ struct CPUClass {
bool gdb_stop_before_watchpoint;
struct AccelCPUClass *accel_cpu;
+ /* when system emulation is not available, this pointer is NULL */
+ const struct SysemuCPUOps *sysemu_ops;
+
/* when TCG is not available, this pointer is NULL */
struct TCGCPUOps *tcg_ops;
};
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
new file mode 100644
index 00000000000..e54a08ea25e
--- /dev/null
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -0,0 +1,21 @@
+/*
+ * CPU operations specific to system emulation
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef SYSEMU_CPU_OPS_H
+#define SYSEMU_CPU_OPS_H
+
+#include "hw/core/cpu.h"
+
+/*
+ * struct SysemuCPUOps: System operations specific to a CPU class
+ */
+typedef struct SysemuCPUOps {
+} SysemuCPUOps;
+
+#endif /* SYSEMU_CPU_OPS_H */
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 27192b62e22..cd01d34d92f 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -206,6 +206,11 @@ static void alpha_cpu_initfn(Object *obj)
#endif
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps alpha_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps alpha_tcg_ops = {
@@ -238,6 +243,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_alpha_cpu;
+ cc->sysemu_ops = &alpha_sysemu_ops;
#endif
cc->disas_set_info = alpha_cpu_disas_set_info;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 3062e8c702e..c1943194cf1 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1943,6 +1943,11 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
return g_strdup("arm");
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps arm_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
static struct TCGCPUOps arm_tcg_ops = {
.initialize = arm_translate_init,
@@ -1986,6 +1991,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
cc->write_elf64_note = arm_cpu_write_elf64_note;
cc->write_elf32_note = arm_cpu_write_elf32_note;
+ cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
cc->gdb_core_xml_file = "arm-core.xml";
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 3353bcb9fc7..5c8bb9b3fec 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -184,6 +184,9 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, "\n");
}
+static const struct SysemuCPUOps avr_sysemu_ops = {
+};
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps avr_tcg_ops = {
@@ -214,6 +217,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
dc->vmsd = &vms_avr_cpu;
+ cc->sysemu_ops = &avr_sysemu_ops;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->gdb_read_register = avr_cpu_gdb_read_register;
cc->gdb_write_register = avr_cpu_gdb_write_register;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index ed983380fca..394df655c9f 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -193,6 +193,11 @@ static void cris_cpu_initfn(Object *obj)
#endif
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps cris_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps crisv10_tcg_ops = {
@@ -294,6 +299,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_cris_cpu;
+ cc->sysemu_ops = &cris_sysemu_ops;
#endif
cc->gdb_num_core_regs = 49;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index d8fad52d1fe..6605c42e509 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -131,6 +131,11 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
return object_class_by_name(TYPE_HPPA_CPU);
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps hppa_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps hppa_tcg_ops = {
@@ -163,6 +168,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_hppa_cpu;
+ cc->sysemu_ops = &hppa_sysemu_ops;
#endif
cc->disas_set_info = hppa_cpu_disas_set_info;
cc->gdb_num_core_regs = 128;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f85ae518dd4..0920eeef1e7 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7391,6 +7391,11 @@ static Property x86_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST()
};
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps i386_sysemu_ops = {
+};
+#endif
+
static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
{
X86CPUClass *xcc = X86_CPU_CLASS(oc);
@@ -7432,6 +7437,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->write_elf32_note = x86_cpu_write_elf32_note;
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
cc->legacy_vmsd = &vmstate_x86_cpu;
+ cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
cc->gdb_arch_name = x86_gdb_arch_name;
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index e27c1a8bc97..2b40f2b2559 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -210,6 +210,11 @@ static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
return oc;
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps lm32_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps lm32_tcg_ops = {
@@ -242,6 +247,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_lm32_cpu;
+ cc->sysemu_ops = &lm32_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 7;
cc->gdb_stop_before_watchpoint = true;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index a14874b4da2..600812d682b 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -503,6 +503,11 @@ static const VMStateDescription vmstate_m68k_cpu = {
};
#endif
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps m68k_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps m68k_tcg_ops = {
@@ -535,6 +540,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
#if defined(CONFIG_SOFTMMU)
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_m68k_cpu;
+ cc->sysemu_ops = &m68k_sysemu_ops;
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 433ba202037..c6a10b1a52b 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -352,6 +352,11 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
return object_class_by_name(TYPE_MICROBLAZE_CPU);
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps mb_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps mb_tcg_ops = {
@@ -388,6 +393,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
dc->vmsd = &vmstate_mb_cpu;
+ cc->sysemu_ops = &mb_sysemu_ops;
#endif
device_class_set_props(dc, mb_properties);
cc->gdb_num_core_regs = 32 + 27;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 11604954504..0bbaff3b57a 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -680,6 +680,11 @@ static Property mips_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST()
};
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps mips_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
/*
@@ -721,6 +726,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
cc->legacy_vmsd = &vmstate_mips_cpu;
+ cc->sysemu_ops = &mips_sysemu_ops;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
cc->gdb_num_core_regs = 73;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index e5da3fa3f17..e7bf5298c67 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -94,6 +94,9 @@ static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model)
return oc;
}
+static const struct SysemuCPUOps moxie_sysemu_ops = {
+};
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps moxie_tcg_ops = {
@@ -125,6 +128,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
dc->vmsd = &vmstate_moxie_cpu;
#endif
cc->disas_set_info = moxie_cpu_disas_set_info;
+ cc->sysemu_ops = &moxie_sysemu_ops;
cc->tcg_ops = &moxie_tcg_ops;
}
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index e9c9fc3a389..296ccc0ed3c 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -207,6 +207,11 @@ static Property nios2_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps nios2_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps nios2_tcg_ops = {
@@ -238,6 +243,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->disas_set_info = nios2_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug;
+ cc->sysemu_ops = &nios2_sysemu_ops;
#endif
cc->gdb_read_register = nios2_cpu_gdb_read_register;
cc->gdb_write_register = nios2_cpu_gdb_write_register;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 2c64842f46b..cd8e3ae6754 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -174,6 +174,11 @@ static void openrisc_any_initfn(Object *obj)
| (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps openrisc_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps openrisc_tcg_ops = {
@@ -205,6 +210,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_openrisc_cpu;
+ cc->sysemu_ops = &openrisc_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 3;
cc->disas_set_info = openrisc_disas_set_info;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 70be7e8287a..c465695f00d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -581,6 +581,11 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
return NULL;
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps riscv_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps riscv_tcg_ops = {
@@ -625,6 +630,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
/* For now, mark unmigratable: */
cc->legacy_vmsd = &vmstate_riscv_cpu;
+ cc->sysemu_ops = &riscv_sysemu_ops;
cc->write_elf64_note = riscv_cpu_write_elf64_note;
cc->write_elf32_note = riscv_cpu_write_elf32_note;
#endif
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 7ac6618b26b..bbee1cb913f 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -173,6 +173,11 @@ static void rx_cpu_init(Object *obj)
qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps rx_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps rx_tcg_ops = {
@@ -202,6 +207,9 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->dump_state = rx_cpu_dump_state;
cc->set_pc = rx_cpu_set_pc;
+#ifndef CONFIG_USER_ONLY
+ cc->sysemu_ops = &rx_sysemu_ops;
+#endif
cc->gdb_read_register = rx_cpu_gdb_read_register;
cc->gdb_write_register = rx_cpu_gdb_write_register;
cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 197c4b87f30..7503b9e0c8b 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -477,6 +477,11 @@ static void s390_cpu_reset_full(DeviceState *dev)
return s390_cpu_reset(s, S390_CPU_RESET_CLEAR);
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps s390_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
@@ -520,6 +525,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->legacy_vmsd = &vmstate_s390_cpu;
cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
+ cc->sysemu_ops = &s390_sysemu_ops;
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
cc->gdb_num_core_regs = S390_NUM_CORE_REGS;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 35d4251aaf3..85e15ec9954 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -223,6 +223,9 @@ static const VMStateDescription vmstate_sh_cpu = {
.name = "cpu",
.unmigratable = 1,
};
+
+static const struct SysemuCPUOps sh4_sysemu_ops = {
+};
#endif
#include "hw/core/tcg-cpu-ops.h"
@@ -259,6 +262,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = superh_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
+ cc->sysemu_ops = &sh4_sysemu_ops;
dc->vmsd = &vmstate_sh_cpu;
#endif
cc->disas_set_info = superh_cpu_disas_set_info;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index ba497561bfa..743a7287a4f 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -848,6 +848,11 @@ static Property sparc_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST()
};
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps sparc_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
@@ -890,6 +895,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
cc->legacy_vmsd = &vmstate_sparc_cpu;
+ cc->sysemu_ops = &sparc_sysemu_ops;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 0b1e139bcba..8865fa18fce 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -142,6 +142,9 @@ static void tc27x_initfn(Object *obj)
set_feature(&cpu->env, TRICORE_FEATURE_161);
}
+static const struct SysemuCPUOps tricore_sysemu_ops = {
+};
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps tricore_tcg_ops = {
@@ -171,6 +174,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->dump_state = tricore_cpu_dump_state;
cc->set_pc = tricore_cpu_set_pc;
cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
+ cc->sysemu_ops = &tricore_sysemu_ops;
cc->tcg_ops = &tricore_tcg_ops;
}
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index a74ac7b6140..60ae917f0ee 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -120,6 +120,9 @@ static const VMStateDescription vmstate_uc32_cpu = {
.name = "cpu",
.unmigratable = 1,
};
+
+static const struct SysemuCPUOps uc32_sysemu_ops = {
+};
#endif
#include "hw/core/tcg-cpu-ops.h"
@@ -149,6 +152,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = uc32_cpu_set_pc;
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
#ifndef CONFIG_USER_ONLY
+ cc->sysemu_ops = &uc32_sysemu_ops;
dc->vmsd = &vmstate_uc32_cpu;
#endif
cc->tcg_ops = &uc32_tcg_ops;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index a66527e2d45..d0bf06696e4 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -181,6 +181,9 @@ static const VMStateDescription vmstate_xtensa_cpu = {
.name = "cpu",
.unmigratable = 1,
};
+
+static const struct SysemuCPUOps xtensa_sysemu_ops = {
+};
#endif
#include "hw/core/tcg-cpu-ops.h"
@@ -217,6 +220,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = xtensa_cpu_gdb_write_register;
cc->gdb_stop_before_watchpoint = true;
#ifndef CONFIG_USER_ONLY
+ cc->sysemu_ops = &xtensa_sysemu_ops;
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_xtensa_cpu;
#endif
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 110a68a867e..b15abc36851 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10878,6 +10878,11 @@ static Property ppc_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps ppc_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
@@ -10921,6 +10926,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
cc->legacy_vmsd = &vmstate_ppc_cpu;
+ cc->sysemu_ops = &ppc_sysemu_ops;
#endif
#if defined(CONFIG_SOFTMMU)
cc->write_elf64_note = ppc64_cpu_write_elf64_note;
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v6 09/18] cpu: Introduce SysemuCPUOps structure
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, qemu-riscv, Juan Quintela, Peter Maydell,
Claudio Fontana, qemu-arm, Eduardo Habkost, qemu-ppc,
Richard Henderson, Laurent Vivier, qemu-s390x,
Philippe Mathieu-Daudé,
Marcel Apfelbaum, Michael Rolnik, Edgar E. Iglesias,
Paolo Bonzini, Michael Walle, Aurelien Jarno, Jiaxun Yang,
Aleksandar Rikalo, Anthony Green, Chris Wulff, Marek Vasut,
Stafford Horne, David Gibson, Greg Kurz, Palmer Dabbelt,
Alistair Francis, Sagar Karandikar, Bastian Koppelmann,
Yoshinori Sato, Cornelia Huck, Thomas Huth, David Hildenbrand,
Mark Cave-Ayland, Artyom Tarasenko, Guan Xuetao, Max Filippov
Introduce a structure to hold handler specific to sysemu.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 5 +++++
include/hw/core/sysemu-cpu-ops.h | 21 +++++++++++++++++++++
target/alpha/cpu.c | 6 ++++++
target/arm/cpu.c | 6 ++++++
target/avr/cpu.c | 4 ++++
target/cris/cpu.c | 6 ++++++
target/hppa/cpu.c | 6 ++++++
target/i386/cpu.c | 6 ++++++
target/lm32/cpu.c | 6 ++++++
target/m68k/cpu.c | 6 ++++++
target/microblaze/cpu.c | 6 ++++++
target/mips/cpu.c | 6 ++++++
target/moxie/cpu.c | 4 ++++
target/nios2/cpu.c | 6 ++++++
target/openrisc/cpu.c | 6 ++++++
target/riscv/cpu.c | 6 ++++++
target/rx/cpu.c | 8 ++++++++
target/s390x/cpu.c | 6 ++++++
target/sh4/cpu.c | 4 ++++
target/sparc/cpu.c | 6 ++++++
target/tricore/cpu.c | 4 ++++
target/unicore32/cpu.c | 4 ++++
target/xtensa/cpu.c | 4 ++++
target/ppc/translate_init.c.inc | 6 ++++++
24 files changed, 148 insertions(+)
create mode 100644 include/hw/core/sysemu-cpu-ops.h
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 10dd16531ba..23b718a4a51 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -80,6 +80,8 @@ struct TCGCPUOps;
/* see accel-cpu.h */
struct AccelCPUClass;
+#include "hw/core/sysemu-cpu-ops.h"
+
/**
* CPUClass:
* @class_by_name: Callback to map -cpu command line model name to an
@@ -191,6 +193,9 @@ struct CPUClass {
bool gdb_stop_before_watchpoint;
struct AccelCPUClass *accel_cpu;
+ /* when system emulation is not available, this pointer is NULL */
+ const struct SysemuCPUOps *sysemu_ops;
+
/* when TCG is not available, this pointer is NULL */
struct TCGCPUOps *tcg_ops;
};
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
new file mode 100644
index 00000000000..e54a08ea25e
--- /dev/null
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -0,0 +1,21 @@
+/*
+ * CPU operations specific to system emulation
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef SYSEMU_CPU_OPS_H
+#define SYSEMU_CPU_OPS_H
+
+#include "hw/core/cpu.h"
+
+/*
+ * struct SysemuCPUOps: System operations specific to a CPU class
+ */
+typedef struct SysemuCPUOps {
+} SysemuCPUOps;
+
+#endif /* SYSEMU_CPU_OPS_H */
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 27192b62e22..cd01d34d92f 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -206,6 +206,11 @@ static void alpha_cpu_initfn(Object *obj)
#endif
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps alpha_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps alpha_tcg_ops = {
@@ -238,6 +243,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_alpha_cpu;
+ cc->sysemu_ops = &alpha_sysemu_ops;
#endif
cc->disas_set_info = alpha_cpu_disas_set_info;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 3062e8c702e..c1943194cf1 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1943,6 +1943,11 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
return g_strdup("arm");
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps arm_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
static struct TCGCPUOps arm_tcg_ops = {
.initialize = arm_translate_init,
@@ -1986,6 +1991,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
cc->write_elf64_note = arm_cpu_write_elf64_note;
cc->write_elf32_note = arm_cpu_write_elf32_note;
+ cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
cc->gdb_core_xml_file = "arm-core.xml";
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 3353bcb9fc7..5c8bb9b3fec 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -184,6 +184,9 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, "\n");
}
+static const struct SysemuCPUOps avr_sysemu_ops = {
+};
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps avr_tcg_ops = {
@@ -214,6 +217,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
dc->vmsd = &vms_avr_cpu;
+ cc->sysemu_ops = &avr_sysemu_ops;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->gdb_read_register = avr_cpu_gdb_read_register;
cc->gdb_write_register = avr_cpu_gdb_write_register;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index ed983380fca..394df655c9f 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -193,6 +193,11 @@ static void cris_cpu_initfn(Object *obj)
#endif
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps cris_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps crisv10_tcg_ops = {
@@ -294,6 +299,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_cris_cpu;
+ cc->sysemu_ops = &cris_sysemu_ops;
#endif
cc->gdb_num_core_regs = 49;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index d8fad52d1fe..6605c42e509 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -131,6 +131,11 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
return object_class_by_name(TYPE_HPPA_CPU);
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps hppa_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps hppa_tcg_ops = {
@@ -163,6 +168,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_hppa_cpu;
+ cc->sysemu_ops = &hppa_sysemu_ops;
#endif
cc->disas_set_info = hppa_cpu_disas_set_info;
cc->gdb_num_core_regs = 128;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f85ae518dd4..0920eeef1e7 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7391,6 +7391,11 @@ static Property x86_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST()
};
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps i386_sysemu_ops = {
+};
+#endif
+
static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
{
X86CPUClass *xcc = X86_CPU_CLASS(oc);
@@ -7432,6 +7437,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->write_elf32_note = x86_cpu_write_elf32_note;
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
cc->legacy_vmsd = &vmstate_x86_cpu;
+ cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
cc->gdb_arch_name = x86_gdb_arch_name;
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index e27c1a8bc97..2b40f2b2559 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -210,6 +210,11 @@ static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
return oc;
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps lm32_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps lm32_tcg_ops = {
@@ -242,6 +247,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_lm32_cpu;
+ cc->sysemu_ops = &lm32_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 7;
cc->gdb_stop_before_watchpoint = true;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index a14874b4da2..600812d682b 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -503,6 +503,11 @@ static const VMStateDescription vmstate_m68k_cpu = {
};
#endif
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps m68k_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps m68k_tcg_ops = {
@@ -535,6 +540,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
#if defined(CONFIG_SOFTMMU)
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_m68k_cpu;
+ cc->sysemu_ops = &m68k_sysemu_ops;
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 433ba202037..c6a10b1a52b 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -352,6 +352,11 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
return object_class_by_name(TYPE_MICROBLAZE_CPU);
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps mb_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps mb_tcg_ops = {
@@ -388,6 +393,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
dc->vmsd = &vmstate_mb_cpu;
+ cc->sysemu_ops = &mb_sysemu_ops;
#endif
device_class_set_props(dc, mb_properties);
cc->gdb_num_core_regs = 32 + 27;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 11604954504..0bbaff3b57a 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -680,6 +680,11 @@ static Property mips_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST()
};
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps mips_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
/*
@@ -721,6 +726,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
cc->legacy_vmsd = &vmstate_mips_cpu;
+ cc->sysemu_ops = &mips_sysemu_ops;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
cc->gdb_num_core_regs = 73;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index e5da3fa3f17..e7bf5298c67 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -94,6 +94,9 @@ static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model)
return oc;
}
+static const struct SysemuCPUOps moxie_sysemu_ops = {
+};
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps moxie_tcg_ops = {
@@ -125,6 +128,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
dc->vmsd = &vmstate_moxie_cpu;
#endif
cc->disas_set_info = moxie_cpu_disas_set_info;
+ cc->sysemu_ops = &moxie_sysemu_ops;
cc->tcg_ops = &moxie_tcg_ops;
}
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index e9c9fc3a389..296ccc0ed3c 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -207,6 +207,11 @@ static Property nios2_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps nios2_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps nios2_tcg_ops = {
@@ -238,6 +243,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->disas_set_info = nios2_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug;
+ cc->sysemu_ops = &nios2_sysemu_ops;
#endif
cc->gdb_read_register = nios2_cpu_gdb_read_register;
cc->gdb_write_register = nios2_cpu_gdb_write_register;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 2c64842f46b..cd8e3ae6754 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -174,6 +174,11 @@ static void openrisc_any_initfn(Object *obj)
| (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps openrisc_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps openrisc_tcg_ops = {
@@ -205,6 +210,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_openrisc_cpu;
+ cc->sysemu_ops = &openrisc_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 3;
cc->disas_set_info = openrisc_disas_set_info;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 70be7e8287a..c465695f00d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -581,6 +581,11 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
return NULL;
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps riscv_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps riscv_tcg_ops = {
@@ -625,6 +630,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
/* For now, mark unmigratable: */
cc->legacy_vmsd = &vmstate_riscv_cpu;
+ cc->sysemu_ops = &riscv_sysemu_ops;
cc->write_elf64_note = riscv_cpu_write_elf64_note;
cc->write_elf32_note = riscv_cpu_write_elf32_note;
#endif
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 7ac6618b26b..bbee1cb913f 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -173,6 +173,11 @@ static void rx_cpu_init(Object *obj)
qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps rx_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps rx_tcg_ops = {
@@ -202,6 +207,9 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->dump_state = rx_cpu_dump_state;
cc->set_pc = rx_cpu_set_pc;
+#ifndef CONFIG_USER_ONLY
+ cc->sysemu_ops = &rx_sysemu_ops;
+#endif
cc->gdb_read_register = rx_cpu_gdb_read_register;
cc->gdb_write_register = rx_cpu_gdb_write_register;
cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 197c4b87f30..7503b9e0c8b 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -477,6 +477,11 @@ static void s390_cpu_reset_full(DeviceState *dev)
return s390_cpu_reset(s, S390_CPU_RESET_CLEAR);
}
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps s390_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
@@ -520,6 +525,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->legacy_vmsd = &vmstate_s390_cpu;
cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
+ cc->sysemu_ops = &s390_sysemu_ops;
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
cc->gdb_num_core_regs = S390_NUM_CORE_REGS;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 35d4251aaf3..85e15ec9954 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -223,6 +223,9 @@ static const VMStateDescription vmstate_sh_cpu = {
.name = "cpu",
.unmigratable = 1,
};
+
+static const struct SysemuCPUOps sh4_sysemu_ops = {
+};
#endif
#include "hw/core/tcg-cpu-ops.h"
@@ -259,6 +262,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = superh_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
+ cc->sysemu_ops = &sh4_sysemu_ops;
dc->vmsd = &vmstate_sh_cpu;
#endif
cc->disas_set_info = superh_cpu_disas_set_info;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index ba497561bfa..743a7287a4f 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -848,6 +848,11 @@ static Property sparc_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST()
};
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps sparc_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
@@ -890,6 +895,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
cc->legacy_vmsd = &vmstate_sparc_cpu;
+ cc->sysemu_ops = &sparc_sysemu_ops;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 0b1e139bcba..8865fa18fce 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -142,6 +142,9 @@ static void tc27x_initfn(Object *obj)
set_feature(&cpu->env, TRICORE_FEATURE_161);
}
+static const struct SysemuCPUOps tricore_sysemu_ops = {
+};
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps tricore_tcg_ops = {
@@ -171,6 +174,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->dump_state = tricore_cpu_dump_state;
cc->set_pc = tricore_cpu_set_pc;
cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
+ cc->sysemu_ops = &tricore_sysemu_ops;
cc->tcg_ops = &tricore_tcg_ops;
}
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index a74ac7b6140..60ae917f0ee 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -120,6 +120,9 @@ static const VMStateDescription vmstate_uc32_cpu = {
.name = "cpu",
.unmigratable = 1,
};
+
+static const struct SysemuCPUOps uc32_sysemu_ops = {
+};
#endif
#include "hw/core/tcg-cpu-ops.h"
@@ -149,6 +152,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = uc32_cpu_set_pc;
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
#ifndef CONFIG_USER_ONLY
+ cc->sysemu_ops = &uc32_sysemu_ops;
dc->vmsd = &vmstate_uc32_cpu;
#endif
cc->tcg_ops = &uc32_tcg_ops;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index a66527e2d45..d0bf06696e4 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -181,6 +181,9 @@ static const VMStateDescription vmstate_xtensa_cpu = {
.name = "cpu",
.unmigratable = 1,
};
+
+static const struct SysemuCPUOps xtensa_sysemu_ops = {
+};
#endif
#include "hw/core/tcg-cpu-ops.h"
@@ -217,6 +220,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = xtensa_cpu_gdb_write_register;
cc->gdb_stop_before_watchpoint = true;
#ifndef CONFIG_USER_ONLY
+ cc->sysemu_ops = &xtensa_sysemu_ops;
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_xtensa_cpu;
#endif
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 110a68a867e..b15abc36851 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10878,6 +10878,11 @@ static Property ppc_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+#ifndef CONFIG_USER_ONLY
+static const struct SysemuCPUOps ppc_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
@@ -10921,6 +10926,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
cc->legacy_vmsd = &vmstate_ppc_cpu;
+ cc->sysemu_ops = &ppc_sysemu_ops;
#endif
#if defined(CONFIG_SOFTMMU)
cc->write_elf64_note = ppc64_cpu_write_elf64_note;
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v6 10/18] cpu: Move CPUClass::vmsd to SysemuCPUOps
2021-04-22 19:38 ` Philippe Mathieu-Daudé
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Sagar Karandikar, David Hildenbrand,
Mark Cave-Ayland, Thomas Huth, Philippe Mathieu-Daudé,
Alistair Francis, Juan Quintela, Claudio Fontana, Palmer Dabbelt,
Artyom Tarasenko, Aleksandar Rikalo, Eduardo Habkost,
Richard Henderson, Dr. David Alan Gilbert, Greg Kurz, qemu-s390x,
qemu-arm, David Gibson, qemu-riscv, Bastian Koppelmann,
Cornelia Huck, Laurent Vivier, qemu-ppc, Paolo Bonzini,
Aurelien Jarno
Migration is specific to system emulation.
- Move the CPUClass::vmsd field to SysemuCPUOps,
- restrict VMSTATE_CPU() macro to sysemu,
- vmstate_dummy is now unused, remove it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
Since v3: Merged in patch 1 (Eduardo)
therefore removed Richard R-b.
'vmsd' is not a 'system operation' prototype but a const
pointer field, so it belongs to a const structure,
but maybe this structure could be better named than SysemuCPUOps?
This field comes from:
commit b170fce3dd06372f7bfec9a780ebcb1fce6d57e4
Author: Andreas Färber <afaerber@suse.de>
Date: Sun Jan 20 20:23:22 2013 +0100
cpu: Register VMStateDescription through CPUState
In comparison to DeviceClass::vmsd, CPU VMState is split in two,
"cpu_common" and "cpu", and uses cpu_index as instance_id instead of -1.
Therefore add a CPU-specific CPUClass::vmsd field.
Unlike the legacy CPUArchState registration, rather register CPUState.
---
include/hw/core/cpu.h | 8 ++------
include/hw/core/sysemu-cpu-ops.h | 5 +++++
include/migration/vmstate.h | 2 --
cpu.c | 15 +++++++--------
stubs/vmstate.c | 2 --
target/arm/cpu.c | 2 +-
target/i386/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/riscv/cpu.c | 4 ++--
target/s390x/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 2 +-
12 files changed, 22 insertions(+), 26 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 23b718a4a51..bdc702894bf 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -124,8 +124,6 @@ struct AccelCPUClass;
* 32-bit VM coredump.
* @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
* note to a 32-bit VM coredump.
- * @legacy_vmsd: Legacy state description for migration.
- * Do not use in new targets, use #DeviceClass::vmsd instead.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
* @gdb_core_xml_file: File name for core registers GDB XML description.
* @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
@@ -180,7 +178,6 @@ struct CPUClass {
int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque);
- const VMStateDescription *legacy_vmsd;
const char *gdb_core_xml_file;
gchar * (*gdb_arch_name)(CPUState *cpu);
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
@@ -1058,10 +1055,8 @@ bool target_words_bigendian(void);
#ifdef NEED_CPU_H
#ifdef CONFIG_SOFTMMU
+
extern const VMStateDescription vmstate_cpu_common;
-#else
-#define vmstate_cpu_common vmstate_dummy
-#endif
#define VMSTATE_CPU() { \
.name = "parent_obj", \
@@ -1070,6 +1065,7 @@ extern const VMStateDescription vmstate_cpu_common;
.flags = VMS_STRUCT, \
.offset = 0, \
}
+#endif /* CONFIG_SOFTMMU */
#endif /* NEED_CPU_H */
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index e54a08ea25e..a10d9fbdd16 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,11 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @legacy_vmsd: Legacy state for migration.
+ * Do not use in new targets, use #DeviceClass::vmsd instead.
+ */
+ const VMStateDescription *legacy_vmsd;
} SysemuCPUOps;
#endif /* SYSEMU_CPU_OPS_H */
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
index 075ee800960..8df7b69f389 100644
--- a/include/migration/vmstate.h
+++ b/include/migration/vmstate.h
@@ -194,8 +194,6 @@ struct VMStateDescription {
const VMStateDescription **subsections;
};
-extern const VMStateDescription vmstate_dummy;
-
extern const VMStateInfo vmstate_info_bool;
extern const VMStateInfo vmstate_info_int8;
diff --git a/cpu.c b/cpu.c
index c1c9cdebc3e..47eb8c40775 100644
--- a/cpu.c
+++ b/cpu.c
@@ -126,7 +126,9 @@ const VMStateDescription vmstate_cpu_common = {
void cpu_exec_realizefn(CPUState *cpu, Error **errp)
{
+#ifndef CONFIG_USER_ONLY
CPUClass *cc = CPU_GET_CLASS(cpu);
+#endif
cpu_list_add(cpu);
@@ -139,26 +141,23 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
#ifdef CONFIG_USER_ONLY
assert(qdev_get_vmsd(DEVICE(cpu)) == NULL);
- assert(cc->legacy_vmsd == NULL);
#else
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
}
- if (cc->legacy_vmsd != NULL) {
- vmstate_register(NULL, cpu->cpu_index, cc->legacy_vmsd, cpu);
+ if (cc->sysemu_ops->legacy_vmsd != NULL) {
+ vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->legacy_vmsd, cpu);
}
#endif /* CONFIG_USER_ONLY */
}
void cpu_exec_unrealizefn(CPUState *cpu)
{
+#ifndef CONFIG_USER_ONLY
CPUClass *cc = CPU_GET_CLASS(cpu);
-#ifdef CONFIG_USER_ONLY
- assert(cc->legacy_vmsd == NULL);
-#else
- if (cc->legacy_vmsd != NULL) {
- vmstate_unregister(NULL, cc->legacy_vmsd, cpu);
+ if (cc->sysemu_ops->legacy_vmsd != NULL) {
+ vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
}
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
diff --git a/stubs/vmstate.c b/stubs/vmstate.c
index cc4fe41dfc2..8513d9204e4 100644
--- a/stubs/vmstate.c
+++ b/stubs/vmstate.c
@@ -1,8 +1,6 @@
#include "qemu/osdep.h"
#include "migration/vmstate.h"
-const VMStateDescription vmstate_dummy = {};
-
int vmstate_register_with_alias_id(VMStateIf *obj,
uint32_t instance_id,
const VMStateDescription *vmsd,
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index c1943194cf1..9b598bf10a8 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1945,6 +1945,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps arm_sysemu_ops = {
+ .legacy_vmsd = &vmstate_arm_cpu,
};
#endif
@@ -1987,7 +1988,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
- cc->legacy_vmsd = &vmstate_arm_cpu;
cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
cc->write_elf64_note = arm_cpu_write_elf64_note;
cc->write_elf32_note = arm_cpu_write_elf32_note;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 0920eeef1e7..eb96dd42556 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7393,6 +7393,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
+ .legacy_vmsd = &vmstate_x86_cpu,
};
#endif
@@ -7436,7 +7437,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
cc->write_elf32_note = x86_cpu_write_elf32_note;
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
- cc->legacy_vmsd = &vmstate_x86_cpu;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 0bbaff3b57a..4023d487669 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -682,6 +682,7 @@ static Property mips_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps mips_sysemu_ops = {
+ .legacy_vmsd = &vmstate_mips_cpu,
};
#endif
@@ -725,7 +726,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
- cc->legacy_vmsd = &vmstate_mips_cpu;
cc->sysemu_ops = &mips_sysemu_ops;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c465695f00d..5514e23c1d2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -583,6 +583,8 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps riscv_sysemu_ops = {
+ /* For now, mark unmigratable: */
+ .legacy_vmsd = &vmstate_riscv_cpu,
};
#endif
@@ -628,8 +630,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
- /* For now, mark unmigratable: */
- cc->legacy_vmsd = &vmstate_riscv_cpu;
cc->sysemu_ops = &riscv_sysemu_ops;
cc->write_elf64_note = riscv_cpu_write_elf64_note;
cc->write_elf32_note = riscv_cpu_write_elf32_note;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 7503b9e0c8b..131e7dfdf82 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps s390_sysemu_ops = {
+ .legacy_vmsd = &vmstate_s390_cpu,
};
#endif
@@ -522,7 +523,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
- cc->legacy_vmsd = &vmstate_s390_cpu;
cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
cc->sysemu_ops = &s390_sysemu_ops;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 743a7287a4f..543853c24dc 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -850,6 +850,7 @@ static Property sparc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps sparc_sysemu_ops = {
+ .legacy_vmsd = &vmstate_sparc_cpu,
};
#endif
@@ -894,7 +895,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = sparc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
- cc->legacy_vmsd = &vmstate_sparc_cpu;
cc->sysemu_ops = &sparc_sysemu_ops;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index b15abc36851..e3f2f2fefa3 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10880,6 +10880,7 @@ static Property ppc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps ppc_sysemu_ops = {
+ .legacy_vmsd = &vmstate_ppc_cpu,
};
#endif
@@ -10925,7 +10926,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = ppc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
- cc->legacy_vmsd = &vmstate_ppc_cpu;
cc->sysemu_ops = &ppc_sysemu_ops;
#endif
#if defined(CONFIG_SOFTMMU)
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v6 10/18] cpu: Move CPUClass::vmsd to SysemuCPUOps
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, qemu-riscv, Juan Quintela, Peter Maydell,
Claudio Fontana, qemu-arm, Eduardo Habkost, qemu-ppc,
Richard Henderson, Laurent Vivier, qemu-s390x,
Philippe Mathieu-Daudé,
Marcel Apfelbaum, Paolo Bonzini, Aurelien Jarno, Jiaxun Yang,
Aleksandar Rikalo, David Gibson, Greg Kurz, Palmer Dabbelt,
Alistair Francis, Sagar Karandikar, Bastian Koppelmann,
David Hildenbrand, Cornelia Huck, Thomas Huth, Mark Cave-Ayland,
Artyom Tarasenko
Migration is specific to system emulation.
- Move the CPUClass::vmsd field to SysemuCPUOps,
- restrict VMSTATE_CPU() macro to sysemu,
- vmstate_dummy is now unused, remove it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
Since v3: Merged in patch 1 (Eduardo)
therefore removed Richard R-b.
'vmsd' is not a 'system operation' prototype but a const
pointer field, so it belongs to a const structure,
but maybe this structure could be better named than SysemuCPUOps?
This field comes from:
commit b170fce3dd06372f7bfec9a780ebcb1fce6d57e4
Author: Andreas Färber <afaerber@suse.de>
Date: Sun Jan 20 20:23:22 2013 +0100
cpu: Register VMStateDescription through CPUState
In comparison to DeviceClass::vmsd, CPU VMState is split in two,
"cpu_common" and "cpu", and uses cpu_index as instance_id instead of -1.
Therefore add a CPU-specific CPUClass::vmsd field.
Unlike the legacy CPUArchState registration, rather register CPUState.
---
include/hw/core/cpu.h | 8 ++------
include/hw/core/sysemu-cpu-ops.h | 5 +++++
include/migration/vmstate.h | 2 --
cpu.c | 15 +++++++--------
stubs/vmstate.c | 2 --
target/arm/cpu.c | 2 +-
target/i386/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/riscv/cpu.c | 4 ++--
target/s390x/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 2 +-
12 files changed, 22 insertions(+), 26 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 23b718a4a51..bdc702894bf 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -124,8 +124,6 @@ struct AccelCPUClass;
* 32-bit VM coredump.
* @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
* note to a 32-bit VM coredump.
- * @legacy_vmsd: Legacy state description for migration.
- * Do not use in new targets, use #DeviceClass::vmsd instead.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
* @gdb_core_xml_file: File name for core registers GDB XML description.
* @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
@@ -180,7 +178,6 @@ struct CPUClass {
int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque);
- const VMStateDescription *legacy_vmsd;
const char *gdb_core_xml_file;
gchar * (*gdb_arch_name)(CPUState *cpu);
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
@@ -1058,10 +1055,8 @@ bool target_words_bigendian(void);
#ifdef NEED_CPU_H
#ifdef CONFIG_SOFTMMU
+
extern const VMStateDescription vmstate_cpu_common;
-#else
-#define vmstate_cpu_common vmstate_dummy
-#endif
#define VMSTATE_CPU() { \
.name = "parent_obj", \
@@ -1070,6 +1065,7 @@ extern const VMStateDescription vmstate_cpu_common;
.flags = VMS_STRUCT, \
.offset = 0, \
}
+#endif /* CONFIG_SOFTMMU */
#endif /* NEED_CPU_H */
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index e54a08ea25e..a10d9fbdd16 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,11 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @legacy_vmsd: Legacy state for migration.
+ * Do not use in new targets, use #DeviceClass::vmsd instead.
+ */
+ const VMStateDescription *legacy_vmsd;
} SysemuCPUOps;
#endif /* SYSEMU_CPU_OPS_H */
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
index 075ee800960..8df7b69f389 100644
--- a/include/migration/vmstate.h
+++ b/include/migration/vmstate.h
@@ -194,8 +194,6 @@ struct VMStateDescription {
const VMStateDescription **subsections;
};
-extern const VMStateDescription vmstate_dummy;
-
extern const VMStateInfo vmstate_info_bool;
extern const VMStateInfo vmstate_info_int8;
diff --git a/cpu.c b/cpu.c
index c1c9cdebc3e..47eb8c40775 100644
--- a/cpu.c
+++ b/cpu.c
@@ -126,7 +126,9 @@ const VMStateDescription vmstate_cpu_common = {
void cpu_exec_realizefn(CPUState *cpu, Error **errp)
{
+#ifndef CONFIG_USER_ONLY
CPUClass *cc = CPU_GET_CLASS(cpu);
+#endif
cpu_list_add(cpu);
@@ -139,26 +141,23 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
#ifdef CONFIG_USER_ONLY
assert(qdev_get_vmsd(DEVICE(cpu)) == NULL);
- assert(cc->legacy_vmsd == NULL);
#else
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
}
- if (cc->legacy_vmsd != NULL) {
- vmstate_register(NULL, cpu->cpu_index, cc->legacy_vmsd, cpu);
+ if (cc->sysemu_ops->legacy_vmsd != NULL) {
+ vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->legacy_vmsd, cpu);
}
#endif /* CONFIG_USER_ONLY */
}
void cpu_exec_unrealizefn(CPUState *cpu)
{
+#ifndef CONFIG_USER_ONLY
CPUClass *cc = CPU_GET_CLASS(cpu);
-#ifdef CONFIG_USER_ONLY
- assert(cc->legacy_vmsd == NULL);
-#else
- if (cc->legacy_vmsd != NULL) {
- vmstate_unregister(NULL, cc->legacy_vmsd, cpu);
+ if (cc->sysemu_ops->legacy_vmsd != NULL) {
+ vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
}
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
diff --git a/stubs/vmstate.c b/stubs/vmstate.c
index cc4fe41dfc2..8513d9204e4 100644
--- a/stubs/vmstate.c
+++ b/stubs/vmstate.c
@@ -1,8 +1,6 @@
#include "qemu/osdep.h"
#include "migration/vmstate.h"
-const VMStateDescription vmstate_dummy = {};
-
int vmstate_register_with_alias_id(VMStateIf *obj,
uint32_t instance_id,
const VMStateDescription *vmsd,
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index c1943194cf1..9b598bf10a8 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1945,6 +1945,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps arm_sysemu_ops = {
+ .legacy_vmsd = &vmstate_arm_cpu,
};
#endif
@@ -1987,7 +1988,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
- cc->legacy_vmsd = &vmstate_arm_cpu;
cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
cc->write_elf64_note = arm_cpu_write_elf64_note;
cc->write_elf32_note = arm_cpu_write_elf32_note;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 0920eeef1e7..eb96dd42556 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7393,6 +7393,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
+ .legacy_vmsd = &vmstate_x86_cpu,
};
#endif
@@ -7436,7 +7437,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
cc->write_elf32_note = x86_cpu_write_elf32_note;
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
- cc->legacy_vmsd = &vmstate_x86_cpu;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 0bbaff3b57a..4023d487669 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -682,6 +682,7 @@ static Property mips_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps mips_sysemu_ops = {
+ .legacy_vmsd = &vmstate_mips_cpu,
};
#endif
@@ -725,7 +726,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
- cc->legacy_vmsd = &vmstate_mips_cpu;
cc->sysemu_ops = &mips_sysemu_ops;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c465695f00d..5514e23c1d2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -583,6 +583,8 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps riscv_sysemu_ops = {
+ /* For now, mark unmigratable: */
+ .legacy_vmsd = &vmstate_riscv_cpu,
};
#endif
@@ -628,8 +630,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
- /* For now, mark unmigratable: */
- cc->legacy_vmsd = &vmstate_riscv_cpu;
cc->sysemu_ops = &riscv_sysemu_ops;
cc->write_elf64_note = riscv_cpu_write_elf64_note;
cc->write_elf32_note = riscv_cpu_write_elf32_note;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 7503b9e0c8b..131e7dfdf82 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps s390_sysemu_ops = {
+ .legacy_vmsd = &vmstate_s390_cpu,
};
#endif
@@ -522,7 +523,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
- cc->legacy_vmsd = &vmstate_s390_cpu;
cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
cc->sysemu_ops = &s390_sysemu_ops;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 743a7287a4f..543853c24dc 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -850,6 +850,7 @@ static Property sparc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps sparc_sysemu_ops = {
+ .legacy_vmsd = &vmstate_sparc_cpu,
};
#endif
@@ -894,7 +895,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = sparc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
- cc->legacy_vmsd = &vmstate_sparc_cpu;
cc->sysemu_ops = &sparc_sysemu_ops;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index b15abc36851..e3f2f2fefa3 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10880,6 +10880,7 @@ static Property ppc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps ppc_sysemu_ops = {
+ .legacy_vmsd = &vmstate_ppc_cpu,
};
#endif
@@ -10925,7 +10926,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = ppc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
- cc->legacy_vmsd = &vmstate_ppc_cpu;
cc->sysemu_ops = &ppc_sysemu_ops;
#endif
#if defined(CONFIG_SOFTMMU)
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v6 10/18] cpu: Move CPUClass::vmsd to SysemuCPUOps
2021-04-22 19:38 ` Philippe Mathieu-Daudé
@ 2021-04-23 1:24 ` Richard Henderson
-1 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2021-04-23 1:24 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, Sagar Karandikar, David Hildenbrand,
Mark Cave-Ayland, Thomas Huth, Alistair Francis, Juan Quintela,
Claudio Fontana, Palmer Dabbelt, Artyom Tarasenko,
Aleksandar Rikalo, Eduardo Habkost, Dr. David Alan Gilbert,
Greg Kurz, qemu-s390x, qemu-arm, David Gibson, qemu-riscv,
Bastian Koppelmann, Cornelia Huck, Laurent Vivier, qemu-ppc,
Paolo Bonzini, Aurelien Jarno
On 4/22/21 12:38 PM, Philippe Mathieu-Daudé wrote:
> Migration is specific to system emulation.
>
> - Move the CPUClass::vmsd field to SysemuCPUOps,
> - restrict VMSTATE_CPU() macro to sysemu,
> - vmstate_dummy is now unused, remove it.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> #ifndef CONFIG_USER_ONLY
> static const struct SysemuCPUOps riscv_sysemu_ops = {
> + /* For now, mark unmigratable: */
> + .legacy_vmsd = &vmstate_riscv_cpu,
> };
> #endif
>
> @@ -628,8 +630,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
> cc->disas_set_info = riscv_cpu_disas_set_info;
> #ifndef CONFIG_USER_ONLY
> cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
> - /* For now, mark unmigratable: */
> - cc->legacy_vmsd = &vmstate_riscv_cpu;
I'll note that the comment has been incorrect since f7697f0e629.
r~
> cc->sysemu_ops = &riscv_sysemu_ops;
> cc->write_elf64_note = riscv_cpu_write_elf64_note;
> cc->write_elf32_note = riscv_cpu_write_elf32_note;
> diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
> index 7503b9e0c8b..131e7dfdf82 100644
> --- a/target/s390x/cpu.c
> +++ b/target/s390x/cpu.c
> @@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
>
> #ifndef CONFIG_USER_ONLY
> static const struct SysemuCPUOps s390_sysemu_ops = {
> + .legacy_vmsd = &vmstate_s390_cpu,
> };
> #endif
>
> @@ -522,7 +523,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
> cc->gdb_write_register = s390_cpu_gdb_write_register;
> #ifndef CONFIG_USER_ONLY
> cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
> - cc->legacy_vmsd = &vmstate_s390_cpu;
> cc->get_crash_info = s390_cpu_get_crash_info;
> cc->write_elf64_note = s390_cpu_write_elf64_note;
> cc->sysemu_ops = &s390_sysemu_ops;
> diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
> index 743a7287a4f..543853c24dc 100644
> --- a/target/sparc/cpu.c
> +++ b/target/sparc/cpu.c
> @@ -850,6 +850,7 @@ static Property sparc_cpu_properties[] = {
>
> #ifndef CONFIG_USER_ONLY
> static const struct SysemuCPUOps sparc_sysemu_ops = {
> + .legacy_vmsd = &vmstate_sparc_cpu,
> };
> #endif
>
> @@ -894,7 +895,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
> cc->gdb_write_register = sparc_cpu_gdb_write_register;
> #ifndef CONFIG_USER_ONLY
> cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
> - cc->legacy_vmsd = &vmstate_sparc_cpu;
> cc->sysemu_ops = &sparc_sysemu_ops;
> #endif
> cc->disas_set_info = cpu_sparc_disas_set_info;
> diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
> index b15abc36851..e3f2f2fefa3 100644
> --- a/target/ppc/translate_init.c.inc
> +++ b/target/ppc/translate_init.c.inc
> @@ -10880,6 +10880,7 @@ static Property ppc_cpu_properties[] = {
>
> #ifndef CONFIG_USER_ONLY
> static const struct SysemuCPUOps ppc_sysemu_ops = {
> + .legacy_vmsd = &vmstate_ppc_cpu,
> };
> #endif
>
> @@ -10925,7 +10926,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
> cc->gdb_write_register = ppc_cpu_gdb_write_register;
> #ifndef CONFIG_USER_ONLY
> cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
> - cc->legacy_vmsd = &vmstate_ppc_cpu;
> cc->sysemu_ops = &ppc_sysemu_ops;
> #endif
> #if defined(CONFIG_SOFTMMU)
>
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH v6 10/18] cpu: Move CPUClass::vmsd to SysemuCPUOps
@ 2021-04-23 1:24 ` Richard Henderson
0 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2021-04-23 1:24 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Dr. David Alan Gilbert, qemu-riscv, Juan Quintela, Peter Maydell,
Claudio Fontana, qemu-arm, Eduardo Habkost, qemu-ppc,
Laurent Vivier, qemu-s390x, Marcel Apfelbaum, Paolo Bonzini,
Aurelien Jarno, Jiaxun Yang, Aleksandar Rikalo, David Gibson,
Greg Kurz, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, David Hildenbrand, Cornelia Huck,
Thomas Huth, Mark Cave-Ayland, Artyom Tarasenko
On 4/22/21 12:38 PM, Philippe Mathieu-Daudé wrote:
> Migration is specific to system emulation.
>
> - Move the CPUClass::vmsd field to SysemuCPUOps,
> - restrict VMSTATE_CPU() macro to sysemu,
> - vmstate_dummy is now unused, remove it.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> #ifndef CONFIG_USER_ONLY
> static const struct SysemuCPUOps riscv_sysemu_ops = {
> + /* For now, mark unmigratable: */
> + .legacy_vmsd = &vmstate_riscv_cpu,
> };
> #endif
>
> @@ -628,8 +630,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
> cc->disas_set_info = riscv_cpu_disas_set_info;
> #ifndef CONFIG_USER_ONLY
> cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
> - /* For now, mark unmigratable: */
> - cc->legacy_vmsd = &vmstate_riscv_cpu;
I'll note that the comment has been incorrect since f7697f0e629.
r~
> cc->sysemu_ops = &riscv_sysemu_ops;
> cc->write_elf64_note = riscv_cpu_write_elf64_note;
> cc->write_elf32_note = riscv_cpu_write_elf32_note;
> diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
> index 7503b9e0c8b..131e7dfdf82 100644
> --- a/target/s390x/cpu.c
> +++ b/target/s390x/cpu.c
> @@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
>
> #ifndef CONFIG_USER_ONLY
> static const struct SysemuCPUOps s390_sysemu_ops = {
> + .legacy_vmsd = &vmstate_s390_cpu,
> };
> #endif
>
> @@ -522,7 +523,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
> cc->gdb_write_register = s390_cpu_gdb_write_register;
> #ifndef CONFIG_USER_ONLY
> cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
> - cc->legacy_vmsd = &vmstate_s390_cpu;
> cc->get_crash_info = s390_cpu_get_crash_info;
> cc->write_elf64_note = s390_cpu_write_elf64_note;
> cc->sysemu_ops = &s390_sysemu_ops;
> diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
> index 743a7287a4f..543853c24dc 100644
> --- a/target/sparc/cpu.c
> +++ b/target/sparc/cpu.c
> @@ -850,6 +850,7 @@ static Property sparc_cpu_properties[] = {
>
> #ifndef CONFIG_USER_ONLY
> static const struct SysemuCPUOps sparc_sysemu_ops = {
> + .legacy_vmsd = &vmstate_sparc_cpu,
> };
> #endif
>
> @@ -894,7 +895,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
> cc->gdb_write_register = sparc_cpu_gdb_write_register;
> #ifndef CONFIG_USER_ONLY
> cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
> - cc->legacy_vmsd = &vmstate_sparc_cpu;
> cc->sysemu_ops = &sparc_sysemu_ops;
> #endif
> cc->disas_set_info = cpu_sparc_disas_set_info;
> diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
> index b15abc36851..e3f2f2fefa3 100644
> --- a/target/ppc/translate_init.c.inc
> +++ b/target/ppc/translate_init.c.inc
> @@ -10880,6 +10880,7 @@ static Property ppc_cpu_properties[] = {
>
> #ifndef CONFIG_USER_ONLY
> static const struct SysemuCPUOps ppc_sysemu_ops = {
> + .legacy_vmsd = &vmstate_ppc_cpu,
> };
> #endif
>
> @@ -10925,7 +10926,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
> cc->gdb_write_register = ppc_cpu_gdb_write_register;
> #ifndef CONFIG_USER_ONLY
> cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
> - cc->legacy_vmsd = &vmstate_ppc_cpu;
> cc->sysemu_ops = &ppc_sysemu_ops;
> #endif
> #if defined(CONFIG_SOFTMMU)
>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v6 11/18] cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps
2021-04-22 19:38 ` Philippe Mathieu-Daudé
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-riscv, Eduardo Habkost, Juan Quintela,
Richard Henderson, Dr. David Alan Gilbert, Laurent Vivier,
qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Greg Kurz,
David Gibson, Philippe Mathieu-Daudé
VirtIO devices are only meaningful with system emulation.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 5 -----
include/hw/core/sysemu-cpu-ops.h | 8 ++++++++
hw/core/cpu.c | 4 ++--
target/arm/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 4 +---
5 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index bdc702894bf..e3c702b8b74 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -89,10 +89,6 @@ struct AccelCPUClass;
* @parse_features: Callback to parse command line arguments.
* @reset_dump_flags: #CPUDumpFlags to use for reset logging.
* @has_work: Callback for checking if there is work to do.
- * @virtio_is_big_endian: Callback to return %true if a CPU which supports
- * runtime configurable endianness is currently big-endian. Non-configurable
- * CPUs can use the default implementation of this method. This method should
- * not be used by any callers other than the pre-1.0 virtio devices.
* @memory_rw_debug: Callback for GDB memory access.
* @dump_state: Callback for dumping state.
* @dump_statistics: Callback for dumping statistics.
@@ -151,7 +147,6 @@ struct CPUClass {
int reset_dump_flags;
bool (*has_work)(CPUState *cpu);
- bool (*virtio_is_big_endian)(CPUState *cpu);
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write);
void (*dump_state)(CPUState *cpu, FILE *, int flags);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index a10d9fbdd16..1c325d62b94 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,14 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @virtio_is_big_endian: Callback to return %true if a CPU which supports
+ * runtime configurable endianness is currently big-endian.
+ * Non-configurable CPUs can use the default implementation of this method.
+ * This method should not be used by any callers other than the pre-1.0
+ * virtio devices.
+ */
+ bool (*virtio_is_big_endian)(CPUState *cpu);
/**
* @legacy_vmsd: Legacy state for migration.
* Do not use in new targets, use #DeviceClass::vmsd instead.
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 5abf8bed2e4..09eaa3fa49f 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -204,8 +204,8 @@ bool cpu_virtio_is_big_endian(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->virtio_is_big_endian) {
- return cc->virtio_is_big_endian(cpu);
+ if (cc->sysemu_ops->virtio_is_big_endian) {
+ return cc->sysemu_ops->virtio_is_big_endian(cpu);
}
return target_words_bigendian();
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 9b598bf10a8..d071ae72ba3 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1945,6 +1945,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps arm_sysemu_ops = {
+ .virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
.legacy_vmsd = &vmstate_arm_cpu,
};
#endif
@@ -1988,7 +1989,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
- cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
cc->write_elf64_note = arm_cpu_write_elf64_note;
cc->write_elf32_note = arm_cpu_write_elf32_note;
cc->sysemu_ops = &arm_sysemu_ops;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index e3f2f2fefa3..8d6bc6c0087 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10880,6 +10880,7 @@ static Property ppc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps ppc_sysemu_ops = {
+ .virtio_is_big_endian = ppc_cpu_is_big_endian,
.legacy_vmsd = &vmstate_ppc_cpu,
};
#endif
@@ -10948,9 +10949,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_core_xml_file = "power64-core.xml";
#else
cc->gdb_core_xml_file = "power-core.xml";
-#endif
-#ifndef CONFIG_USER_ONLY
- cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
#endif
cc->disas_set_info = ppc_disas_set_info;
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v6 11/18] cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, qemu-riscv, Juan Quintela, Peter Maydell,
Claudio Fontana, qemu-arm, Eduardo Habkost, qemu-ppc,
Richard Henderson, Laurent Vivier, qemu-s390x,
Philippe Mathieu-Daudé,
Marcel Apfelbaum, David Gibson, Greg Kurz
VirtIO devices are only meaningful with system emulation.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 5 -----
include/hw/core/sysemu-cpu-ops.h | 8 ++++++++
hw/core/cpu.c | 4 ++--
target/arm/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 4 +---
5 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index bdc702894bf..e3c702b8b74 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -89,10 +89,6 @@ struct AccelCPUClass;
* @parse_features: Callback to parse command line arguments.
* @reset_dump_flags: #CPUDumpFlags to use for reset logging.
* @has_work: Callback for checking if there is work to do.
- * @virtio_is_big_endian: Callback to return %true if a CPU which supports
- * runtime configurable endianness is currently big-endian. Non-configurable
- * CPUs can use the default implementation of this method. This method should
- * not be used by any callers other than the pre-1.0 virtio devices.
* @memory_rw_debug: Callback for GDB memory access.
* @dump_state: Callback for dumping state.
* @dump_statistics: Callback for dumping statistics.
@@ -151,7 +147,6 @@ struct CPUClass {
int reset_dump_flags;
bool (*has_work)(CPUState *cpu);
- bool (*virtio_is_big_endian)(CPUState *cpu);
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write);
void (*dump_state)(CPUState *cpu, FILE *, int flags);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index a10d9fbdd16..1c325d62b94 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,14 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @virtio_is_big_endian: Callback to return %true if a CPU which supports
+ * runtime configurable endianness is currently big-endian.
+ * Non-configurable CPUs can use the default implementation of this method.
+ * This method should not be used by any callers other than the pre-1.0
+ * virtio devices.
+ */
+ bool (*virtio_is_big_endian)(CPUState *cpu);
/**
* @legacy_vmsd: Legacy state for migration.
* Do not use in new targets, use #DeviceClass::vmsd instead.
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 5abf8bed2e4..09eaa3fa49f 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -204,8 +204,8 @@ bool cpu_virtio_is_big_endian(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->virtio_is_big_endian) {
- return cc->virtio_is_big_endian(cpu);
+ if (cc->sysemu_ops->virtio_is_big_endian) {
+ return cc->sysemu_ops->virtio_is_big_endian(cpu);
}
return target_words_bigendian();
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 9b598bf10a8..d071ae72ba3 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1945,6 +1945,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps arm_sysemu_ops = {
+ .virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
.legacy_vmsd = &vmstate_arm_cpu,
};
#endif
@@ -1988,7 +1989,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
- cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
cc->write_elf64_note = arm_cpu_write_elf64_note;
cc->write_elf32_note = arm_cpu_write_elf32_note;
cc->sysemu_ops = &arm_sysemu_ops;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index e3f2f2fefa3..8d6bc6c0087 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10880,6 +10880,7 @@ static Property ppc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps ppc_sysemu_ops = {
+ .virtio_is_big_endian = ppc_cpu_is_big_endian,
.legacy_vmsd = &vmstate_ppc_cpu,
};
#endif
@@ -10948,9 +10949,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_core_xml_file = "power64-core.xml";
#else
cc->gdb_core_xml_file = "power-core.xml";
-#endif
-#ifndef CONFIG_USER_ONLY
- cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
#endif
cc->disas_set_info = ppc_disas_set_info;
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v6 12/18] cpu: Move CPUClass::get_crash_info to SysemuCPUOps
2021-04-22 19:38 ` Philippe Mathieu-Daudé
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Thomas Huth, qemu-riscv, Eduardo Habkost,
Juan Quintela, Cornelia Huck, Richard Henderson,
Dr. David Alan Gilbert, Laurent Vivier, qemu-s390x, qemu-arm,
qemu-ppc, Claudio Fontana, Paolo Bonzini, David Hildenbrand,
Philippe Mathieu-Daudé
cpu_get_crash_info() is called on GUEST_PANICKED events,
which only occur in system emulation.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 1 -
include/hw/core/sysemu-cpu-ops.h | 5 +++++
hw/core/cpu.c | 4 ++--
target/i386/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
5 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index e3c702b8b74..4289cd0d78a 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -150,7 +150,6 @@ struct CPUClass {
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write);
void (*dump_state)(CPUState *cpu, FILE *, int flags);
- GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
void (*dump_statistics)(CPUState *cpu, int flags);
int64_t (*get_arch_id)(CPUState *cpu);
bool (*get_paging_enabled)(const CPUState *cpu);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 1c325d62b94..f7a91a66e06 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,11 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @get_crash_info: Callback for reporting guest crash information in
+ * GUEST_PANICKED events.
+ */
+ GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
/**
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
* runtime configurable endianness is currently big-endian.
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 09eaa3fa49f..0aebc18c41f 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -220,8 +220,8 @@ GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
CPUClass *cc = CPU_GET_CLASS(cpu);
GuestPanicInformation *res = NULL;
- if (cc->get_crash_info) {
- res = cc->get_crash_info(cpu);
+ if (cc->sysemu_ops->get_crash_info) {
+ res = cc->sysemu_ops->get_crash_info(cpu);
}
return res;
}
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index eb96dd42556..ab0c07fe9b4 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7393,6 +7393,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
+ .get_crash_info = x86_cpu_get_crash_info,
.legacy_vmsd = &vmstate_x86_cpu,
};
#endif
@@ -7432,7 +7433,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->asidx_from_attrs = x86_asidx_from_attrs;
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
- cc->get_crash_info = x86_cpu_get_crash_info;
cc->write_elf64_note = x86_cpu_write_elf64_note;
cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
cc->write_elf32_note = x86_cpu_write_elf32_note;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 131e7dfdf82..55d7a727602 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps s390_sysemu_ops = {
+ .get_crash_info = s390_cpu_get_crash_info,
.legacy_vmsd = &vmstate_s390_cpu,
};
#endif
@@ -523,7 +524,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
- cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
cc->sysemu_ops = &s390_sysemu_ops;
#endif
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v6 12/18] cpu: Move CPUClass::get_crash_info to SysemuCPUOps
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, qemu-riscv, Juan Quintela, Peter Maydell,
Claudio Fontana, qemu-arm, Eduardo Habkost, qemu-ppc,
Richard Henderson, Laurent Vivier, qemu-s390x,
Philippe Mathieu-Daudé,
Marcel Apfelbaum, Paolo Bonzini, Cornelia Huck, Thomas Huth,
David Hildenbrand
cpu_get_crash_info() is called on GUEST_PANICKED events,
which only occur in system emulation.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 1 -
include/hw/core/sysemu-cpu-ops.h | 5 +++++
hw/core/cpu.c | 4 ++--
target/i386/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
5 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index e3c702b8b74..4289cd0d78a 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -150,7 +150,6 @@ struct CPUClass {
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write);
void (*dump_state)(CPUState *cpu, FILE *, int flags);
- GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
void (*dump_statistics)(CPUState *cpu, int flags);
int64_t (*get_arch_id)(CPUState *cpu);
bool (*get_paging_enabled)(const CPUState *cpu);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 1c325d62b94..f7a91a66e06 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,11 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @get_crash_info: Callback for reporting guest crash information in
+ * GUEST_PANICKED events.
+ */
+ GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
/**
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
* runtime configurable endianness is currently big-endian.
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 09eaa3fa49f..0aebc18c41f 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -220,8 +220,8 @@ GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
CPUClass *cc = CPU_GET_CLASS(cpu);
GuestPanicInformation *res = NULL;
- if (cc->get_crash_info) {
- res = cc->get_crash_info(cpu);
+ if (cc->sysemu_ops->get_crash_info) {
+ res = cc->sysemu_ops->get_crash_info(cpu);
}
return res;
}
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index eb96dd42556..ab0c07fe9b4 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7393,6 +7393,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
+ .get_crash_info = x86_cpu_get_crash_info,
.legacy_vmsd = &vmstate_x86_cpu,
};
#endif
@@ -7432,7 +7433,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->asidx_from_attrs = x86_asidx_from_attrs;
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
- cc->get_crash_info = x86_cpu_get_crash_info;
cc->write_elf64_note = x86_cpu_write_elf64_note;
cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
cc->write_elf32_note = x86_cpu_write_elf32_note;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 131e7dfdf82..55d7a727602 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps s390_sysemu_ops = {
+ .get_crash_info = s390_cpu_get_crash_info,
.legacy_vmsd = &vmstate_s390_cpu,
};
#endif
@@ -523,7 +524,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
- cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
cc->sysemu_ops = &s390_sysemu_ops;
#endif
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v6 13/18] cpu: Move CPUClass::write_elf* to SysemuCPUOps
2021-04-22 19:38 ` Philippe Mathieu-Daudé
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Sagar Karandikar, David Hildenbrand,
Philippe Mathieu-Daudé,
Alistair Francis, Juan Quintela, Claudio Fontana, Palmer Dabbelt,
Thomas Huth, Eduardo Habkost, Richard Henderson,
Dr. David Alan Gilbert, Greg Kurz, qemu-s390x, qemu-arm,
David Gibson, qemu-riscv, Bastian Koppelmann, Cornelia Huck,
Laurent Vivier, qemu-ppc, Paolo Bonzini
The write_elf*() handlers are used to dump vmcore images.
This feature is only meaningful for system emulation.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 17 -----------------
include/hw/core/sysemu-cpu-ops.h | 24 ++++++++++++++++++++++++
hw/core/cpu.c | 16 ++++++++--------
target/arm/cpu.c | 4 ++--
target/i386/cpu.c | 8 ++++----
target/riscv/cpu.c | 4 ++--
target/s390x/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 6 ++----
8 files changed, 43 insertions(+), 38 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 4289cd0d78a..b7095bc4192 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -112,14 +112,6 @@ struct AccelCPUClass;
* a memory access with the specified memory transaction attributes.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
- * @write_elf64_note: Callback for writing a CPU-specific ELF note to a
- * 64-bit VM coredump.
- * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
- * note to a 32-bit VM coredump.
- * @write_elf32_note: Callback for writing a CPU-specific ELF note to a
- * 32-bit VM coredump.
- * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
- * note to a 32-bit VM coredump.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
* @gdb_core_xml_file: File name for core registers GDB XML description.
* @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
@@ -163,15 +155,6 @@ struct CPUClass {
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
- int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
- int cpuid, void *opaque);
- int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
- void *opaque);
- int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
- int cpuid, void *opaque);
- int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
- void *opaque);
-
const char *gdb_core_xml_file;
gchar * (*gdb_arch_name)(CPUState *cpu);
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index f7a91a66e06..bdc76d580e9 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -21,6 +21,30 @@ typedef struct SysemuCPUOps {
* GUEST_PANICKED events.
*/
GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
+ /**
+ * @write_elf32_note: Callback for writing a CPU-specific ELF note to a
+ * 32-bit VM coredump.
+ */
+ int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
+ int cpuid, void *opaque);
+ /**
+ * @write_elf64_note: Callback for writing a CPU-specific ELF note to a
+ * 64-bit VM coredump.
+ */
+ int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
+ int cpuid, void *opaque);
+ /**
+ * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
+ * note to a 32-bit VM coredump.
+ */
+ int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
+ void *opaque);
+ /**
+ * @write_elf64_qemunote: Callback for writing a CPU- and QEMU-specific ELF
+ * note to a 64-bit VM coredump.
+ */
+ int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
+ void *opaque);
/**
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
* runtime configurable endianness is currently big-endian.
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 0aebc18c41f..c74390aafbf 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -151,10 +151,10 @@ int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf32_qemunote) {
+ if (!cc->sysemu_ops->write_elf32_qemunote) {
return 0;
}
- return (*cc->write_elf32_qemunote)(f, cpu, opaque);
+ return (*cc->sysemu_ops->write_elf32_qemunote)(f, cpu, opaque);
}
int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
@@ -162,10 +162,10 @@ int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf32_note) {
+ if (!cc->sysemu_ops->write_elf32_note) {
return -1;
}
- return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
+ return (*cc->sysemu_ops->write_elf32_note)(f, cpu, cpuid, opaque);
}
int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
@@ -173,10 +173,10 @@ int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf64_qemunote) {
+ if (!cc->sysemu_ops->write_elf64_qemunote) {
return 0;
}
- return (*cc->write_elf64_qemunote)(f, cpu, opaque);
+ return (*cc->sysemu_ops->write_elf64_qemunote)(f, cpu, opaque);
}
int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
@@ -184,10 +184,10 @@ int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf64_note) {
+ if (!cc->sysemu_ops->write_elf64_note) {
return -1;
}
- return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
+ return (*cc->sysemu_ops->write_elf64_note)(f, cpu, cpuid, opaque);
}
static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index d071ae72ba3..cbfdb9d0b70 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1945,6 +1945,8 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps arm_sysemu_ops = {
+ .write_elf32_note = arm_cpu_write_elf32_note,
+ .write_elf64_note = arm_cpu_write_elf64_note,
.virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
.legacy_vmsd = &vmstate_arm_cpu,
};
@@ -1989,8 +1991,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
- cc->write_elf64_note = arm_cpu_write_elf64_note;
- cc->write_elf32_note = arm_cpu_write_elf32_note;
cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ab0c07fe9b4..fd7788907ea 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7394,6 +7394,10 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
.get_crash_info = x86_cpu_get_crash_info,
+ .write_elf32_note = x86_cpu_write_elf32_note,
+ .write_elf64_note = x86_cpu_write_elf64_note,
+ .write_elf32_qemunote = x86_cpu_write_elf32_qemunote,
+ .write_elf64_qemunote = x86_cpu_write_elf64_qemunote,
.legacy_vmsd = &vmstate_x86_cpu,
};
#endif
@@ -7433,10 +7437,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->asidx_from_attrs = x86_asidx_from_attrs;
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
- cc->write_elf64_note = x86_cpu_write_elf64_note;
- cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
- cc->write_elf32_note = x86_cpu_write_elf32_note;
- cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5514e23c1d2..cacec059754 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -583,6 +583,8 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps riscv_sysemu_ops = {
+ .write_elf64_note = riscv_cpu_write_elf64_note,
+ .write_elf32_note = riscv_cpu_write_elf32_note,
/* For now, mark unmigratable: */
.legacy_vmsd = &vmstate_riscv_cpu,
};
@@ -631,8 +633,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
cc->sysemu_ops = &riscv_sysemu_ops;
- cc->write_elf64_note = riscv_cpu_write_elf64_note;
- cc->write_elf32_note = riscv_cpu_write_elf32_note;
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 55d7a727602..afb55be5c8c 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -480,6 +480,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps s390_sysemu_ops = {
.get_crash_info = s390_cpu_get_crash_info,
+ .write_elf64_note = s390_cpu_write_elf64_note,
.legacy_vmsd = &vmstate_s390_cpu,
};
#endif
@@ -524,7 +525,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
- cc->write_elf64_note = s390_cpu_write_elf64_note;
cc->sysemu_ops = &s390_sysemu_ops;
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 8d6bc6c0087..b348b08868d 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10880,6 +10880,8 @@ static Property ppc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps ppc_sysemu_ops = {
+ .write_elf32_note = ppc32_cpu_write_elf32_note,
+ .write_elf64_note = ppc64_cpu_write_elf64_note,
.virtio_is_big_endian = ppc_cpu_is_big_endian,
.legacy_vmsd = &vmstate_ppc_cpu,
};
@@ -10929,10 +10931,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
cc->sysemu_ops = &ppc_sysemu_ops;
#endif
-#if defined(CONFIG_SOFTMMU)
- cc->write_elf64_note = ppc64_cpu_write_elf64_note;
- cc->write_elf32_note = ppc32_cpu_write_elf32_note;
-#endif
cc->gdb_num_core_regs = 71;
#ifndef CONFIG_USER_ONLY
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v6 13/18] cpu: Move CPUClass::write_elf* to SysemuCPUOps
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, qemu-riscv, Juan Quintela, Peter Maydell,
Claudio Fontana, qemu-arm, Eduardo Habkost, qemu-ppc,
Richard Henderson, Laurent Vivier, qemu-s390x,
Philippe Mathieu-Daudé,
Marcel Apfelbaum, Paolo Bonzini, David Gibson, Greg Kurz,
Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, David Hildenbrand, Cornelia Huck,
Thomas Huth
The write_elf*() handlers are used to dump vmcore images.
This feature is only meaningful for system emulation.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 17 -----------------
include/hw/core/sysemu-cpu-ops.h | 24 ++++++++++++++++++++++++
hw/core/cpu.c | 16 ++++++++--------
target/arm/cpu.c | 4 ++--
target/i386/cpu.c | 8 ++++----
target/riscv/cpu.c | 4 ++--
target/s390x/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 6 ++----
8 files changed, 43 insertions(+), 38 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 4289cd0d78a..b7095bc4192 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -112,14 +112,6 @@ struct AccelCPUClass;
* a memory access with the specified memory transaction attributes.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
- * @write_elf64_note: Callback for writing a CPU-specific ELF note to a
- * 64-bit VM coredump.
- * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
- * note to a 32-bit VM coredump.
- * @write_elf32_note: Callback for writing a CPU-specific ELF note to a
- * 32-bit VM coredump.
- * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
- * note to a 32-bit VM coredump.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
* @gdb_core_xml_file: File name for core registers GDB XML description.
* @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
@@ -163,15 +155,6 @@ struct CPUClass {
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
- int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
- int cpuid, void *opaque);
- int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
- void *opaque);
- int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
- int cpuid, void *opaque);
- int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
- void *opaque);
-
const char *gdb_core_xml_file;
gchar * (*gdb_arch_name)(CPUState *cpu);
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index f7a91a66e06..bdc76d580e9 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -21,6 +21,30 @@ typedef struct SysemuCPUOps {
* GUEST_PANICKED events.
*/
GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
+ /**
+ * @write_elf32_note: Callback for writing a CPU-specific ELF note to a
+ * 32-bit VM coredump.
+ */
+ int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
+ int cpuid, void *opaque);
+ /**
+ * @write_elf64_note: Callback for writing a CPU-specific ELF note to a
+ * 64-bit VM coredump.
+ */
+ int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
+ int cpuid, void *opaque);
+ /**
+ * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
+ * note to a 32-bit VM coredump.
+ */
+ int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
+ void *opaque);
+ /**
+ * @write_elf64_qemunote: Callback for writing a CPU- and QEMU-specific ELF
+ * note to a 64-bit VM coredump.
+ */
+ int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
+ void *opaque);
/**
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
* runtime configurable endianness is currently big-endian.
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 0aebc18c41f..c74390aafbf 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -151,10 +151,10 @@ int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf32_qemunote) {
+ if (!cc->sysemu_ops->write_elf32_qemunote) {
return 0;
}
- return (*cc->write_elf32_qemunote)(f, cpu, opaque);
+ return (*cc->sysemu_ops->write_elf32_qemunote)(f, cpu, opaque);
}
int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
@@ -162,10 +162,10 @@ int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf32_note) {
+ if (!cc->sysemu_ops->write_elf32_note) {
return -1;
}
- return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
+ return (*cc->sysemu_ops->write_elf32_note)(f, cpu, cpuid, opaque);
}
int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
@@ -173,10 +173,10 @@ int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf64_qemunote) {
+ if (!cc->sysemu_ops->write_elf64_qemunote) {
return 0;
}
- return (*cc->write_elf64_qemunote)(f, cpu, opaque);
+ return (*cc->sysemu_ops->write_elf64_qemunote)(f, cpu, opaque);
}
int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
@@ -184,10 +184,10 @@ int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf64_note) {
+ if (!cc->sysemu_ops->write_elf64_note) {
return -1;
}
- return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
+ return (*cc->sysemu_ops->write_elf64_note)(f, cpu, cpuid, opaque);
}
static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index d071ae72ba3..cbfdb9d0b70 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1945,6 +1945,8 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps arm_sysemu_ops = {
+ .write_elf32_note = arm_cpu_write_elf32_note,
+ .write_elf64_note = arm_cpu_write_elf64_note,
.virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
.legacy_vmsd = &vmstate_arm_cpu,
};
@@ -1989,8 +1991,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
- cc->write_elf64_note = arm_cpu_write_elf64_note;
- cc->write_elf32_note = arm_cpu_write_elf32_note;
cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ab0c07fe9b4..fd7788907ea 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7394,6 +7394,10 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
.get_crash_info = x86_cpu_get_crash_info,
+ .write_elf32_note = x86_cpu_write_elf32_note,
+ .write_elf64_note = x86_cpu_write_elf64_note,
+ .write_elf32_qemunote = x86_cpu_write_elf32_qemunote,
+ .write_elf64_qemunote = x86_cpu_write_elf64_qemunote,
.legacy_vmsd = &vmstate_x86_cpu,
};
#endif
@@ -7433,10 +7437,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->asidx_from_attrs = x86_asidx_from_attrs;
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
- cc->write_elf64_note = x86_cpu_write_elf64_note;
- cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
- cc->write_elf32_note = x86_cpu_write_elf32_note;
- cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5514e23c1d2..cacec059754 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -583,6 +583,8 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps riscv_sysemu_ops = {
+ .write_elf64_note = riscv_cpu_write_elf64_note,
+ .write_elf32_note = riscv_cpu_write_elf32_note,
/* For now, mark unmigratable: */
.legacy_vmsd = &vmstate_riscv_cpu,
};
@@ -631,8 +633,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
cc->sysemu_ops = &riscv_sysemu_ops;
- cc->write_elf64_note = riscv_cpu_write_elf64_note;
- cc->write_elf32_note = riscv_cpu_write_elf32_note;
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 55d7a727602..afb55be5c8c 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -480,6 +480,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps s390_sysemu_ops = {
.get_crash_info = s390_cpu_get_crash_info,
+ .write_elf64_note = s390_cpu_write_elf64_note,
.legacy_vmsd = &vmstate_s390_cpu,
};
#endif
@@ -524,7 +525,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
- cc->write_elf64_note = s390_cpu_write_elf64_note;
cc->sysemu_ops = &s390_sysemu_ops;
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 8d6bc6c0087..b348b08868d 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10880,6 +10880,8 @@ static Property ppc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps ppc_sysemu_ops = {
+ .write_elf32_note = ppc32_cpu_write_elf32_note,
+ .write_elf64_note = ppc64_cpu_write_elf64_note,
.virtio_is_big_endian = ppc_cpu_is_big_endian,
.legacy_vmsd = &vmstate_ppc_cpu,
};
@@ -10929,10 +10931,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
cc->sysemu_ops = &ppc_sysemu_ops;
#endif
-#if defined(CONFIG_SOFTMMU)
- cc->write_elf64_note = ppc64_cpu_write_elf64_note;
- cc->write_elf32_note = ppc32_cpu_write_elf32_note;
-#endif
cc->gdb_num_core_regs = 71;
#ifndef CONFIG_USER_ONLY
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v6 14/18] cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps
2021-04-22 19:38 ` Philippe Mathieu-Daudé
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-riscv, Eduardo Habkost, Juan Quintela,
Richard Henderson, Dr. David Alan Gilbert, Laurent Vivier,
qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 3 ---
include/hw/core/sysemu-cpu-ops.h | 5 +++++
hw/core/cpu.c | 4 ++--
target/arm/cpu.c | 2 +-
target/i386/cpu.c | 2 +-
5 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index b7095bc4192..28c4fc541a2 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -108,8 +108,6 @@ struct AccelCPUClass;
* associated memory transaction attributes to use for the access.
* CPUs which use memory transaction attributes should implement this
* instead of get_phys_page_debug.
- * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
- * a memory access with the specified memory transaction attributes.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
@@ -151,7 +149,6 @@ struct CPUClass {
hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs);
- int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index bdc76d580e9..52a05ea9b3e 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,11 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
+ * a memory access with the specified memory transaction attributes.
+ */
+ int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
/**
* @get_crash_info: Callback for reporting guest crash information in
* GUEST_PANICKED events.
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index c74390aafbf..c44229205ff 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -116,8 +116,8 @@ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
CPUClass *cc = CPU_GET_CLASS(cpu);
int ret = 0;
- if (cc->asidx_from_attrs) {
- ret = cc->asidx_from_attrs(cpu, attrs);
+ if (cc->sysemu_ops->asidx_from_attrs) {
+ ret = cc->sysemu_ops->asidx_from_attrs(cpu, attrs);
assert(ret < cpu->num_ases && ret >= 0);
}
return ret;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index cbfdb9d0b70..e030890c11b 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1945,6 +1945,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps arm_sysemu_ops = {
+ .asidx_from_attrs = arm_asidx_from_attrs,
.write_elf32_note = arm_cpu_write_elf32_note,
.write_elf64_note = arm_cpu_write_elf64_note,
.virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
@@ -1990,7 +1991,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = arm_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
- cc->asidx_from_attrs = arm_asidx_from_attrs;
cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index fd7788907ea..70b0108b748 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7393,6 +7393,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
+ .asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
.write_elf32_note = x86_cpu_write_elf32_note,
.write_elf64_note = x86_cpu_write_elf64_note,
@@ -7434,7 +7435,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
- cc->asidx_from_attrs = x86_asidx_from_attrs;
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
cc->sysemu_ops = &i386_sysemu_ops;
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v6 14/18] cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, qemu-riscv, Juan Quintela, Peter Maydell,
Claudio Fontana, qemu-arm, Eduardo Habkost, qemu-ppc,
Richard Henderson, Laurent Vivier, qemu-s390x,
Philippe Mathieu-Daudé,
Marcel Apfelbaum, Paolo Bonzini
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 3 ---
include/hw/core/sysemu-cpu-ops.h | 5 +++++
hw/core/cpu.c | 4 ++--
target/arm/cpu.c | 2 +-
target/i386/cpu.c | 2 +-
5 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index b7095bc4192..28c4fc541a2 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -108,8 +108,6 @@ struct AccelCPUClass;
* associated memory transaction attributes to use for the access.
* CPUs which use memory transaction attributes should implement this
* instead of get_phys_page_debug.
- * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
- * a memory access with the specified memory transaction attributes.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
@@ -151,7 +149,6 @@ struct CPUClass {
hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs);
- int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index bdc76d580e9..52a05ea9b3e 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,11 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
+ * a memory access with the specified memory transaction attributes.
+ */
+ int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
/**
* @get_crash_info: Callback for reporting guest crash information in
* GUEST_PANICKED events.
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index c74390aafbf..c44229205ff 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -116,8 +116,8 @@ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
CPUClass *cc = CPU_GET_CLASS(cpu);
int ret = 0;
- if (cc->asidx_from_attrs) {
- ret = cc->asidx_from_attrs(cpu, attrs);
+ if (cc->sysemu_ops->asidx_from_attrs) {
+ ret = cc->sysemu_ops->asidx_from_attrs(cpu, attrs);
assert(ret < cpu->num_ases && ret >= 0);
}
return ret;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index cbfdb9d0b70..e030890c11b 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1945,6 +1945,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps arm_sysemu_ops = {
+ .asidx_from_attrs = arm_asidx_from_attrs,
.write_elf32_note = arm_cpu_write_elf32_note,
.write_elf64_note = arm_cpu_write_elf64_note,
.virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
@@ -1990,7 +1991,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = arm_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
- cc->asidx_from_attrs = arm_asidx_from_attrs;
cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index fd7788907ea..70b0108b748 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7393,6 +7393,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
+ .asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
.write_elf32_note = x86_cpu_write_elf32_note,
.write_elf64_note = x86_cpu_write_elf64_note,
@@ -7434,7 +7435,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
- cc->asidx_from_attrs = x86_asidx_from_attrs;
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
cc->sysemu_ops = &i386_sysemu_ops;
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v6 15/18] cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps
2021-04-22 19:38 ` Philippe Mathieu-Daudé
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Cornelia Huck, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland, Thomas Huth,
Philippe Mathieu-Daudé,
Max Filippov, Alistair Francis, Edgar E. Iglesias, Guan Xuetao,
Marek Vasut, Yoshinori Sato, Juan Quintela, Claudio Fontana,
Palmer Dabbelt, Artyom Tarasenko, Aleksandar Rikalo,
Eduardo Habkost, Richard Henderson, Dr. David Alan Gilbert,
Greg Kurz, qemu-s390x, qemu-arm, Michael Rolnik, Stafford Horne,
David Gibson, qemu-riscv, Bastian Koppelmann, Chris Wulff,
Laurent Vivier, Michael Walle, qemu-ppc, Paolo Bonzini,
Aurelien Jarno
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 8 --------
include/hw/core/sysemu-cpu-ops.h | 13 +++++++++++++
hw/core/cpu.c | 6 +++---
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 2 +-
target/avr/cpu.c | 2 +-
target/cris/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/i386/cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/moxie/cpu.c | 2 +-
target/nios2/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/tricore/cpu.c | 2 +-
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 2 +-
25 files changed, 38 insertions(+), 33 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 28c4fc541a2..88a0a90ac7b 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -103,11 +103,6 @@ struct AccelCPUClass;
* If the target behaviour here is anything other than "set
* the PC register to the value passed in" then the target must
* also implement the synchronize_from_tb hook.
- * @get_phys_page_debug: Callback for obtaining a physical address.
- * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the
- * associated memory transaction attributes to use for the access.
- * CPUs which use memory transaction attributes should implement this
- * instead of get_phys_page_debug.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
@@ -146,9 +141,6 @@ struct CPUClass {
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
void (*set_pc)(CPUState *cpu, vaddr value);
- hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
- hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
- MemTxAttrs *attrs);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 52a05ea9b3e..4be4a4b4da7 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,19 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @get_phys_page_debug: Callback for obtaining a physical address.
+ */
+ hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
+ /**
+ * @get_phys_page_attrs_debug: Callback for obtaining a physical address
+ * and the associated memory transaction attributes to use for the
+ * access.
+ * CPUs which use memory transaction attributes should implement this
+ * instead of get_phys_page_debug.
+ */
+ hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
+ MemTxAttrs *attrs);
/**
* @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
* a memory access with the specified memory transaction attributes.
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index c44229205ff..6932781425a 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -96,12 +96,12 @@ hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->get_phys_page_attrs_debug) {
- return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
+ if (cc->sysemu_ops->get_phys_page_attrs_debug) {
+ return cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr, attrs);
}
/* Fallback for CPUs which don't implement the _attrs_ hook */
*attrs = MEMTXATTRS_UNSPECIFIED;
- return cc->get_phys_page_debug(cpu, addr);
+ return cc->sysemu_ops->get_phys_page_debug(cpu, addr);
}
hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index cd01d34d92f..979a4c0be1e 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -208,6 +208,7 @@ static void alpha_cpu_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps alpha_sysemu_ops = {
+ .get_phys_page_debug = alpha_cpu_get_phys_page_debug,
};
#endif
@@ -241,7 +242,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = alpha_cpu_gdb_read_register;
cc->gdb_write_register = alpha_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_alpha_cpu;
cc->sysemu_ops = &alpha_sysemu_ops;
#endif
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index e030890c11b..4b7d298827f 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1945,6 +1945,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps arm_sysemu_ops = {
+ .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = arm_asidx_from_attrs,
.write_elf32_note = arm_cpu_write_elf32_note,
.write_elf64_note = arm_cpu_write_elf64_note,
@@ -1990,7 +1991,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = arm_cpu_gdb_read_register;
cc->gdb_write_register = arm_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 5c8bb9b3fec..a357ff0bffb 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -185,6 +185,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
static const struct SysemuCPUOps avr_sysemu_ops = {
+ .get_phys_page_debug = avr_cpu_get_phys_page_debug,
};
#include "hw/core/tcg-cpu-ops.h"
@@ -215,7 +216,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = avr_cpu_dump_state;
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
- cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
dc->vmsd = &vms_avr_cpu;
cc->sysemu_ops = &avr_sysemu_ops;
cc->disas_set_info = avr_cpu_disas_set_info;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 394df655c9f..58193c02cbf 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -195,6 +195,7 @@ static void cris_cpu_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps cris_sysemu_ops = {
+ .get_phys_page_debug = cris_cpu_get_phys_page_debug,
};
#endif
@@ -297,7 +298,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = cris_cpu_gdb_read_register;
cc->gdb_write_register = cris_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_cris_cpu;
cc->sysemu_ops = &cris_sysemu_ops;
#endif
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 6605c42e509..0d755b8a880 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -133,6 +133,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps hppa_sysemu_ops = {
+ .get_phys_page_debug = hppa_cpu_get_phys_page_debug,
};
#endif
@@ -166,7 +167,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = hppa_cpu_gdb_read_register;
cc->gdb_write_register = hppa_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_hppa_cpu;
cc->sysemu_ops = &hppa_sysemu_ops;
#endif
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 70b0108b748..ead0aafd9d1 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7393,6 +7393,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
+ .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
.write_elf32_note = x86_cpu_write_elf32_note,
@@ -7436,7 +7437,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
- cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index 2b40f2b2559..01fbd751eb2 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -212,6 +212,7 @@ static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps lm32_sysemu_ops = {
+ .get_phys_page_debug = lm32_cpu_get_phys_page_debug,
};
#endif
@@ -245,7 +246,6 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = lm32_cpu_gdb_read_register;
cc->gdb_write_register = lm32_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_lm32_cpu;
cc->sysemu_ops = &lm32_sysemu_ops;
#endif
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 600812d682b..f743a86c7d5 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -505,6 +505,7 @@ static const VMStateDescription vmstate_m68k_cpu = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps m68k_sysemu_ops = {
+ .get_phys_page_debug = m68k_cpu_get_phys_page_debug,
};
#endif
@@ -538,7 +539,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_read_register = m68k_cpu_gdb_read_register;
cc->gdb_write_register = m68k_cpu_gdb_write_register;
#if defined(CONFIG_SOFTMMU)
- cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_m68k_cpu;
cc->sysemu_ops = &m68k_sysemu_ops;
#endif
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index c6a10b1a52b..8ccac373631 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -354,6 +354,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps mb_sysemu_ops = {
+ .get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug,
};
#endif
@@ -391,7 +392,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = mb_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
dc->vmsd = &vmstate_mb_cpu;
cc->sysemu_ops = &mb_sysemu_ops;
#endif
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 4023d487669..dd6033c576e 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -682,6 +682,7 @@ static Property mips_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps mips_sysemu_ops = {
+ .get_phys_page_debug = mips_cpu_get_phys_page_debug,
.legacy_vmsd = &vmstate_mips_cpu,
};
#endif
@@ -725,7 +726,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_read_register = mips_cpu_gdb_read_register;
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
cc->sysemu_ops = &mips_sysemu_ops;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index e7bf5298c67..295ccde10e5 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -95,6 +95,7 @@ static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model)
}
static const struct SysemuCPUOps moxie_sysemu_ops = {
+ .get_phys_page_debug = moxie_cpu_get_phys_page_debug,
};
#include "hw/core/tcg-cpu-ops.h"
@@ -124,7 +125,6 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = moxie_cpu_dump_state;
cc->set_pc = moxie_cpu_set_pc;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_moxie_cpu;
#endif
cc->disas_set_info = moxie_cpu_disas_set_info;
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 296ccc0ed3c..f3b51732c29 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -209,6 +209,7 @@ static Property nios2_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps nios2_sysemu_ops = {
+ .get_phys_page_debug = nios2_cpu_get_phys_page_debug,
};
#endif
@@ -242,7 +243,6 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = nios2_cpu_set_pc;
cc->disas_set_info = nios2_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug;
cc->sysemu_ops = &nios2_sysemu_ops;
#endif
cc->gdb_read_register = nios2_cpu_gdb_read_register;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index cd8e3ae6754..babe637cda6 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -176,6 +176,7 @@ static void openrisc_any_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps openrisc_sysemu_ops = {
+ .get_phys_page_debug = openrisc_cpu_get_phys_page_debug,
};
#endif
@@ -208,7 +209,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = openrisc_cpu_gdb_read_register;
cc->gdb_write_register = openrisc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_openrisc_cpu;
cc->sysemu_ops = &openrisc_sysemu_ops;
#endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cacec059754..0c350195e07 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -583,6 +583,7 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps riscv_sysemu_ops = {
+ .get_phys_page_debug = riscv_cpu_get_phys_page_debug,
.write_elf64_note = riscv_cpu_write_elf64_note,
.write_elf32_note = riscv_cpu_write_elf32_note,
/* For now, mark unmigratable: */
@@ -631,7 +632,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
cc->sysemu_ops = &riscv_sysemu_ops;
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index bbee1cb913f..e76b7708b89 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -175,6 +175,7 @@ static void rx_cpu_init(Object *obj)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps rx_sysemu_ops = {
+ .get_phys_page_debug = rx_cpu_get_phys_page_debug,
};
#endif
@@ -212,7 +213,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
#endif
cc->gdb_read_register = rx_cpu_gdb_read_register;
cc->gdb_write_register = rx_cpu_gdb_write_register;
- cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
cc->disas_set_info = rx_cpu_disas_set_info;
cc->gdb_num_core_regs = 26;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index afb55be5c8c..5b3551e290c 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps s390_sysemu_ops = {
+ .get_phys_page_debug = s390_cpu_get_phys_page_debug,
.get_crash_info = s390_cpu_get_crash_info,
.write_elf64_note = s390_cpu_write_elf64_note,
.legacy_vmsd = &vmstate_s390_cpu,
@@ -524,7 +525,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = s390_cpu_gdb_read_register;
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
cc->sysemu_ops = &s390_sysemu_ops;
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 85e15ec9954..09de295cf91 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -225,6 +225,7 @@ static const VMStateDescription vmstate_sh_cpu = {
};
static const struct SysemuCPUOps sh4_sysemu_ops = {
+ .get_phys_page_debug = superh_cpu_get_phys_page_debug,
};
#endif
@@ -261,7 +262,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = superh_cpu_gdb_read_register;
cc->gdb_write_register = superh_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
cc->sysemu_ops = &sh4_sysemu_ops;
dc->vmsd = &vmstate_sh_cpu;
#endif
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 543853c24dc..90658ba8e61 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -850,6 +850,7 @@ static Property sparc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps sparc_sysemu_ops = {
+ .get_phys_page_debug = sparc_cpu_get_phys_page_debug,
.legacy_vmsd = &vmstate_sparc_cpu,
};
#endif
@@ -894,7 +895,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = sparc_cpu_gdb_read_register;
cc->gdb_write_register = sparc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
cc->sysemu_ops = &sparc_sysemu_ops;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 8865fa18fce..4572dde1486 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -143,6 +143,7 @@ static void tc27x_initfn(Object *obj)
}
static const struct SysemuCPUOps tricore_sysemu_ops = {
+ .get_phys_page_debug = tricore_cpu_get_phys_page_debug,
};
#include "hw/core/tcg-cpu-ops.h"
@@ -173,7 +174,6 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->dump_state = tricore_cpu_dump_state;
cc->set_pc = tricore_cpu_set_pc;
- cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
cc->sysemu_ops = &tricore_sysemu_ops;
cc->tcg_ops = &tricore_tcg_ops;
}
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 60ae917f0ee..36d712259f2 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -122,6 +122,7 @@ static const VMStateDescription vmstate_uc32_cpu = {
};
static const struct SysemuCPUOps uc32_sysemu_ops = {
+ .get_phys_page_debug = uc32_cpu_get_phys_page_debug,
};
#endif
@@ -150,7 +151,6 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = uc32_cpu_has_work;
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
- cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
#ifndef CONFIG_USER_ONLY
cc->sysemu_ops = &uc32_sysemu_ops;
dc->vmsd = &vmstate_uc32_cpu;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index d0bf06696e4..eb61ee55be4 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -183,6 +183,7 @@ static const VMStateDescription vmstate_xtensa_cpu = {
};
static const struct SysemuCPUOps xtensa_sysemu_ops = {
+ .get_phys_page_debug = xtensa_cpu_get_phys_page_debug,
};
#endif
@@ -221,7 +222,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
#ifndef CONFIG_USER_ONLY
cc->sysemu_ops = &xtensa_sysemu_ops;
- cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_xtensa_cpu;
#endif
cc->disas_set_info = xtensa_cpu_disas_set_info;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index b348b08868d..dc53cc545f4 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10880,6 +10880,7 @@ static Property ppc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps ppc_sysemu_ops = {
+ .get_phys_page_debug = ppc_cpu_get_phys_page_debug,
.write_elf32_note = ppc32_cpu_write_elf32_note,
.write_elf64_note = ppc64_cpu_write_elf64_note,
.virtio_is_big_endian = ppc_cpu_is_big_endian,
@@ -10928,7 +10929,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = ppc_cpu_gdb_read_register;
cc->gdb_write_register = ppc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
cc->sysemu_ops = &ppc_sysemu_ops;
#endif
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v6 15/18] cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps
@ 2021-04-22 19:38 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:38 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, qemu-riscv, Juan Quintela, Peter Maydell,
Claudio Fontana, qemu-arm, Eduardo Habkost, qemu-ppc,
Richard Henderson, Laurent Vivier, qemu-s390x,
Philippe Mathieu-Daudé,
Marcel Apfelbaum, Michael Rolnik, Edgar E. Iglesias,
Paolo Bonzini, Michael Walle, Aurelien Jarno, Jiaxun Yang,
Aleksandar Rikalo, Anthony Green, Chris Wulff, Marek Vasut,
Stafford Horne, David Gibson, Greg Kurz, Palmer Dabbelt,
Alistair Francis, Sagar Karandikar, Bastian Koppelmann,
Yoshinori Sato, Cornelia Huck, Thomas Huth, David Hildenbrand,
Mark Cave-Ayland, Artyom Tarasenko, Guan Xuetao, Max Filippov
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 8 --------
include/hw/core/sysemu-cpu-ops.h | 13 +++++++++++++
hw/core/cpu.c | 6 +++---
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 2 +-
target/avr/cpu.c | 2 +-
target/cris/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/i386/cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/moxie/cpu.c | 2 +-
target/nios2/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/tricore/cpu.c | 2 +-
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 2 +-
25 files changed, 38 insertions(+), 33 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 28c4fc541a2..88a0a90ac7b 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -103,11 +103,6 @@ struct AccelCPUClass;
* If the target behaviour here is anything other than "set
* the PC register to the value passed in" then the target must
* also implement the synchronize_from_tb hook.
- * @get_phys_page_debug: Callback for obtaining a physical address.
- * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the
- * associated memory transaction attributes to use for the access.
- * CPUs which use memory transaction attributes should implement this
- * instead of get_phys_page_debug.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
@@ -146,9 +141,6 @@ struct CPUClass {
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
void (*set_pc)(CPUState *cpu, vaddr value);
- hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
- hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
- MemTxAttrs *attrs);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 52a05ea9b3e..4be4a4b4da7 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,19 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @get_phys_page_debug: Callback for obtaining a physical address.
+ */
+ hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
+ /**
+ * @get_phys_page_attrs_debug: Callback for obtaining a physical address
+ * and the associated memory transaction attributes to use for the
+ * access.
+ * CPUs which use memory transaction attributes should implement this
+ * instead of get_phys_page_debug.
+ */
+ hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
+ MemTxAttrs *attrs);
/**
* @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
* a memory access with the specified memory transaction attributes.
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index c44229205ff..6932781425a 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -96,12 +96,12 @@ hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->get_phys_page_attrs_debug) {
- return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
+ if (cc->sysemu_ops->get_phys_page_attrs_debug) {
+ return cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr, attrs);
}
/* Fallback for CPUs which don't implement the _attrs_ hook */
*attrs = MEMTXATTRS_UNSPECIFIED;
- return cc->get_phys_page_debug(cpu, addr);
+ return cc->sysemu_ops->get_phys_page_debug(cpu, addr);
}
hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index cd01d34d92f..979a4c0be1e 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -208,6 +208,7 @@ static void alpha_cpu_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps alpha_sysemu_ops = {
+ .get_phys_page_debug = alpha_cpu_get_phys_page_debug,
};
#endif
@@ -241,7 +242,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = alpha_cpu_gdb_read_register;
cc->gdb_write_register = alpha_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_alpha_cpu;
cc->sysemu_ops = &alpha_sysemu_ops;
#endif
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index e030890c11b..4b7d298827f 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1945,6 +1945,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps arm_sysemu_ops = {
+ .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = arm_asidx_from_attrs,
.write_elf32_note = arm_cpu_write_elf32_note,
.write_elf64_note = arm_cpu_write_elf64_note,
@@ -1990,7 +1991,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = arm_cpu_gdb_read_register;
cc->gdb_write_register = arm_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 5c8bb9b3fec..a357ff0bffb 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -185,6 +185,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
static const struct SysemuCPUOps avr_sysemu_ops = {
+ .get_phys_page_debug = avr_cpu_get_phys_page_debug,
};
#include "hw/core/tcg-cpu-ops.h"
@@ -215,7 +216,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = avr_cpu_dump_state;
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
- cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
dc->vmsd = &vms_avr_cpu;
cc->sysemu_ops = &avr_sysemu_ops;
cc->disas_set_info = avr_cpu_disas_set_info;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 394df655c9f..58193c02cbf 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -195,6 +195,7 @@ static void cris_cpu_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps cris_sysemu_ops = {
+ .get_phys_page_debug = cris_cpu_get_phys_page_debug,
};
#endif
@@ -297,7 +298,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = cris_cpu_gdb_read_register;
cc->gdb_write_register = cris_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_cris_cpu;
cc->sysemu_ops = &cris_sysemu_ops;
#endif
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 6605c42e509..0d755b8a880 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -133,6 +133,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps hppa_sysemu_ops = {
+ .get_phys_page_debug = hppa_cpu_get_phys_page_debug,
};
#endif
@@ -166,7 +167,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = hppa_cpu_gdb_read_register;
cc->gdb_write_register = hppa_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_hppa_cpu;
cc->sysemu_ops = &hppa_sysemu_ops;
#endif
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 70b0108b748..ead0aafd9d1 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7393,6 +7393,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
+ .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
.write_elf32_note = x86_cpu_write_elf32_note,
@@ -7436,7 +7437,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
- cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index 2b40f2b2559..01fbd751eb2 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -212,6 +212,7 @@ static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps lm32_sysemu_ops = {
+ .get_phys_page_debug = lm32_cpu_get_phys_page_debug,
};
#endif
@@ -245,7 +246,6 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = lm32_cpu_gdb_read_register;
cc->gdb_write_register = lm32_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_lm32_cpu;
cc->sysemu_ops = &lm32_sysemu_ops;
#endif
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 600812d682b..f743a86c7d5 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -505,6 +505,7 @@ static const VMStateDescription vmstate_m68k_cpu = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps m68k_sysemu_ops = {
+ .get_phys_page_debug = m68k_cpu_get_phys_page_debug,
};
#endif
@@ -538,7 +539,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_read_register = m68k_cpu_gdb_read_register;
cc->gdb_write_register = m68k_cpu_gdb_write_register;
#if defined(CONFIG_SOFTMMU)
- cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_m68k_cpu;
cc->sysemu_ops = &m68k_sysemu_ops;
#endif
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index c6a10b1a52b..8ccac373631 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -354,6 +354,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps mb_sysemu_ops = {
+ .get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug,
};
#endif
@@ -391,7 +392,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = mb_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
dc->vmsd = &vmstate_mb_cpu;
cc->sysemu_ops = &mb_sysemu_ops;
#endif
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 4023d487669..dd6033c576e 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -682,6 +682,7 @@ static Property mips_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps mips_sysemu_ops = {
+ .get_phys_page_debug = mips_cpu_get_phys_page_debug,
.legacy_vmsd = &vmstate_mips_cpu,
};
#endif
@@ -725,7 +726,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_read_register = mips_cpu_gdb_read_register;
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
cc->sysemu_ops = &mips_sysemu_ops;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index e7bf5298c67..295ccde10e5 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -95,6 +95,7 @@ static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model)
}
static const struct SysemuCPUOps moxie_sysemu_ops = {
+ .get_phys_page_debug = moxie_cpu_get_phys_page_debug,
};
#include "hw/core/tcg-cpu-ops.h"
@@ -124,7 +125,6 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = moxie_cpu_dump_state;
cc->set_pc = moxie_cpu_set_pc;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_moxie_cpu;
#endif
cc->disas_set_info = moxie_cpu_disas_set_info;
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 296ccc0ed3c..f3b51732c29 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -209,6 +209,7 @@ static Property nios2_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps nios2_sysemu_ops = {
+ .get_phys_page_debug = nios2_cpu_get_phys_page_debug,
};
#endif
@@ -242,7 +243,6 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = nios2_cpu_set_pc;
cc->disas_set_info = nios2_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug;
cc->sysemu_ops = &nios2_sysemu_ops;
#endif
cc->gdb_read_register = nios2_cpu_gdb_read_register;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index cd8e3ae6754..babe637cda6 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -176,6 +176,7 @@ static void openrisc_any_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps openrisc_sysemu_ops = {
+ .get_phys_page_debug = openrisc_cpu_get_phys_page_debug,
};
#endif
@@ -208,7 +209,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = openrisc_cpu_gdb_read_register;
cc->gdb_write_register = openrisc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_openrisc_cpu;
cc->sysemu_ops = &openrisc_sysemu_ops;
#endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cacec059754..0c350195e07 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -583,6 +583,7 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps riscv_sysemu_ops = {
+ .get_phys_page_debug = riscv_cpu_get_phys_page_debug,
.write_elf64_note = riscv_cpu_write_elf64_note,
.write_elf32_note = riscv_cpu_write_elf32_note,
/* For now, mark unmigratable: */
@@ -631,7 +632,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
cc->sysemu_ops = &riscv_sysemu_ops;
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index bbee1cb913f..e76b7708b89 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -175,6 +175,7 @@ static void rx_cpu_init(Object *obj)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps rx_sysemu_ops = {
+ .get_phys_page_debug = rx_cpu_get_phys_page_debug,
};
#endif
@@ -212,7 +213,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
#endif
cc->gdb_read_register = rx_cpu_gdb_read_register;
cc->gdb_write_register = rx_cpu_gdb_write_register;
- cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
cc->disas_set_info = rx_cpu_disas_set_info;
cc->gdb_num_core_regs = 26;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index afb55be5c8c..5b3551e290c 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps s390_sysemu_ops = {
+ .get_phys_page_debug = s390_cpu_get_phys_page_debug,
.get_crash_info = s390_cpu_get_crash_info,
.write_elf64_note = s390_cpu_write_elf64_note,
.legacy_vmsd = &vmstate_s390_cpu,
@@ -524,7 +525,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = s390_cpu_gdb_read_register;
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
cc->sysemu_ops = &s390_sysemu_ops;
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 85e15ec9954..09de295cf91 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -225,6 +225,7 @@ static const VMStateDescription vmstate_sh_cpu = {
};
static const struct SysemuCPUOps sh4_sysemu_ops = {
+ .get_phys_page_debug = superh_cpu_get_phys_page_debug,
};
#endif
@@ -261,7 +262,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = superh_cpu_gdb_read_register;
cc->gdb_write_register = superh_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
cc->sysemu_ops = &sh4_sysemu_ops;
dc->vmsd = &vmstate_sh_cpu;
#endif
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 543853c24dc..90658ba8e61 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -850,6 +850,7 @@ static Property sparc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps sparc_sysemu_ops = {
+ .get_phys_page_debug = sparc_cpu_get_phys_page_debug,
.legacy_vmsd = &vmstate_sparc_cpu,
};
#endif
@@ -894,7 +895,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = sparc_cpu_gdb_read_register;
cc->gdb_write_register = sparc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
cc->sysemu_ops = &sparc_sysemu_ops;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 8865fa18fce..4572dde1486 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -143,6 +143,7 @@ static void tc27x_initfn(Object *obj)
}
static const struct SysemuCPUOps tricore_sysemu_ops = {
+ .get_phys_page_debug = tricore_cpu_get_phys_page_debug,
};
#include "hw/core/tcg-cpu-ops.h"
@@ -173,7 +174,6 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->dump_state = tricore_cpu_dump_state;
cc->set_pc = tricore_cpu_set_pc;
- cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
cc->sysemu_ops = &tricore_sysemu_ops;
cc->tcg_ops = &tricore_tcg_ops;
}
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 60ae917f0ee..36d712259f2 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -122,6 +122,7 @@ static const VMStateDescription vmstate_uc32_cpu = {
};
static const struct SysemuCPUOps uc32_sysemu_ops = {
+ .get_phys_page_debug = uc32_cpu_get_phys_page_debug,
};
#endif
@@ -150,7 +151,6 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = uc32_cpu_has_work;
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
- cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
#ifndef CONFIG_USER_ONLY
cc->sysemu_ops = &uc32_sysemu_ops;
dc->vmsd = &vmstate_uc32_cpu;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index d0bf06696e4..eb61ee55be4 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -183,6 +183,7 @@ static const VMStateDescription vmstate_xtensa_cpu = {
};
static const struct SysemuCPUOps xtensa_sysemu_ops = {
+ .get_phys_page_debug = xtensa_cpu_get_phys_page_debug,
};
#endif
@@ -221,7 +222,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
#ifndef CONFIG_USER_ONLY
cc->sysemu_ops = &xtensa_sysemu_ops;
- cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_xtensa_cpu;
#endif
cc->disas_set_info = xtensa_cpu_disas_set_info;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index b348b08868d..dc53cc545f4 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10880,6 +10880,7 @@ static Property ppc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps ppc_sysemu_ops = {
+ .get_phys_page_debug = ppc_cpu_get_phys_page_debug,
.write_elf32_note = ppc32_cpu_write_elf32_note,
.write_elf64_note = ppc64_cpu_write_elf64_note,
.virtio_is_big_endian = ppc_cpu_is_big_endian,
@@ -10928,7 +10929,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = ppc_cpu_gdb_read_register;
cc->gdb_write_register = ppc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
cc->sysemu_ops = &ppc_sysemu_ops;
#endif
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v6 16/18] cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps
2021-04-22 19:38 ` Philippe Mathieu-Daudé
@ 2021-04-22 19:39 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:39 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-riscv, Eduardo Habkost, Juan Quintela,
Richard Henderson, Dr. David Alan Gilbert, Laurent Vivier,
qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 3 ---
include/hw/core/sysemu-cpu-ops.h | 5 +++++
hw/core/cpu.c | 4 ++--
target/i386/cpu.c | 2 +-
4 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 88a0a90ac7b..6dd60c3ada4 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -94,7 +94,6 @@ struct AccelCPUClass;
* @dump_statistics: Callback for dumping statistics.
* @get_arch_id: Callback for getting architecture-dependent CPU ID.
* @get_paging_enabled: Callback for inquiring whether paging is enabled.
- * @get_memory_mapping: Callback for obtaining the memory mappings.
* @set_pc: Callback for setting the Program Counter register. This
* should have the semantics used by the target architecture when
* setting the PC from a source such as an ELF file entry point;
@@ -138,8 +137,6 @@ struct CPUClass {
void (*dump_statistics)(CPUState *cpu, int flags);
int64_t (*get_arch_id)(CPUState *cpu);
bool (*get_paging_enabled)(const CPUState *cpu);
- void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
- Error **errp);
void (*set_pc)(CPUState *cpu, vaddr value);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 4be4a4b4da7..344561b7827 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,11 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @get_memory_mapping: Callback for obtaining the memory mappings.
+ */
+ void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
+ Error **errp);
/**
* @get_phys_page_debug: Callback for obtaining a physical address.
*/
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 6932781425a..339bdfadd7a 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -83,8 +83,8 @@ void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->get_memory_mapping) {
- cc->get_memory_mapping(cpu, list, errp);
+ if (cc->sysemu_ops->get_memory_mapping) {
+ cc->sysemu_ops->get_memory_mapping(cpu, list, errp);
return;
}
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ead0aafd9d1..5d35d8e329f 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7393,6 +7393,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
+ .get_memory_mapping = x86_cpu_get_memory_mapping,
.get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
@@ -7436,7 +7437,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
- cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v6 16/18] cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps
@ 2021-04-22 19:39 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:39 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, qemu-riscv, Juan Quintela, Peter Maydell,
Claudio Fontana, qemu-arm, Eduardo Habkost, qemu-ppc,
Richard Henderson, Laurent Vivier, qemu-s390x,
Philippe Mathieu-Daudé,
Marcel Apfelbaum, Paolo Bonzini
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 3 ---
include/hw/core/sysemu-cpu-ops.h | 5 +++++
hw/core/cpu.c | 4 ++--
target/i386/cpu.c | 2 +-
4 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 88a0a90ac7b..6dd60c3ada4 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -94,7 +94,6 @@ struct AccelCPUClass;
* @dump_statistics: Callback for dumping statistics.
* @get_arch_id: Callback for getting architecture-dependent CPU ID.
* @get_paging_enabled: Callback for inquiring whether paging is enabled.
- * @get_memory_mapping: Callback for obtaining the memory mappings.
* @set_pc: Callback for setting the Program Counter register. This
* should have the semantics used by the target architecture when
* setting the PC from a source such as an ELF file entry point;
@@ -138,8 +137,6 @@ struct CPUClass {
void (*dump_statistics)(CPUState *cpu, int flags);
int64_t (*get_arch_id)(CPUState *cpu);
bool (*get_paging_enabled)(const CPUState *cpu);
- void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
- Error **errp);
void (*set_pc)(CPUState *cpu, vaddr value);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 4be4a4b4da7..344561b7827 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,11 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @get_memory_mapping: Callback for obtaining the memory mappings.
+ */
+ void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
+ Error **errp);
/**
* @get_phys_page_debug: Callback for obtaining a physical address.
*/
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 6932781425a..339bdfadd7a 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -83,8 +83,8 @@ void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->get_memory_mapping) {
- cc->get_memory_mapping(cpu, list, errp);
+ if (cc->sysemu_ops->get_memory_mapping) {
+ cc->sysemu_ops->get_memory_mapping(cpu, list, errp);
return;
}
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ead0aafd9d1..5d35d8e329f 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7393,6 +7393,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
+ .get_memory_mapping = x86_cpu_get_memory_mapping,
.get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
@@ -7436,7 +7437,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
- cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v6 17/18] cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps
2021-04-22 19:38 ` Philippe Mathieu-Daudé
@ 2021-04-22 19:39 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:39 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-riscv, Eduardo Habkost, Juan Quintela,
Richard Henderson, Dr. David Alan Gilbert, Laurent Vivier,
qemu-s390x, qemu-arm, qemu-ppc, Claudio Fontana, Paolo Bonzini,
Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 2 --
include/hw/core/sysemu-cpu-ops.h | 4 ++++
hw/core/cpu.c | 4 ++--
target/i386/cpu.c | 4 +++-
4 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 6dd60c3ada4..d0187798eea 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -93,7 +93,6 @@ struct AccelCPUClass;
* @dump_state: Callback for dumping state.
* @dump_statistics: Callback for dumping statistics.
* @get_arch_id: Callback for getting architecture-dependent CPU ID.
- * @get_paging_enabled: Callback for inquiring whether paging is enabled.
* @set_pc: Callback for setting the Program Counter register. This
* should have the semantics used by the target architecture when
* setting the PC from a source such as an ELF file entry point;
@@ -136,7 +135,6 @@ struct CPUClass {
void (*dump_state)(CPUState *cpu, FILE *, int flags);
void (*dump_statistics)(CPUState *cpu, int flags);
int64_t (*get_arch_id)(CPUState *cpu);
- bool (*get_paging_enabled)(const CPUState *cpu);
void (*set_pc)(CPUState *cpu, vaddr value);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 344561b7827..f0707f012b4 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -21,6 +21,10 @@ typedef struct SysemuCPUOps {
*/
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
+ /**
+ * @get_paging_enabled: Callback for inquiring whether paging is enabled.
+ */
+ bool (*get_paging_enabled)(const CPUState *cpu);
/**
* @get_phys_page_debug: Callback for obtaining a physical address.
*/
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 339bdfadd7a..7a8487d468f 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -71,8 +71,8 @@ bool cpu_paging_enabled(const CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->get_paging_enabled) {
- return cc->get_paging_enabled(cpu);
+ if (cc->sysemu_ops->get_paging_enabled) {
+ return cc->sysemu_ops->get_paging_enabled(cpu);
}
return false;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 5d35d8e329f..abdebdfe9b8 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7162,12 +7162,14 @@ static int64_t x86_cpu_get_arch_id(CPUState *cs)
return cpu->apic_id;
}
+#if !defined(CONFIG_USER_ONLY)
static bool x86_cpu_get_paging_enabled(const CPUState *cs)
{
X86CPU *cpu = X86_CPU(cs);
return cpu->env.cr[0] & CR0_PG_MASK;
}
+#endif /* !CONFIG_USER_ONLY */
static void x86_cpu_set_pc(CPUState *cs, vaddr value)
{
@@ -7394,6 +7396,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
.get_memory_mapping = x86_cpu_get_memory_mapping,
+ .get_paging_enabled = x86_cpu_get_paging_enabled,
.get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
@@ -7434,7 +7437,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = x86_cpu_gdb_read_register;
cc->gdb_write_register = x86_cpu_gdb_write_register;
cc->get_arch_id = x86_cpu_get_arch_id;
- cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
cc->sysemu_ops = &i386_sysemu_ops;
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v6 17/18] cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps
@ 2021-04-22 19:39 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:39 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, qemu-riscv, Juan Quintela, Peter Maydell,
Claudio Fontana, qemu-arm, Eduardo Habkost, qemu-ppc,
Richard Henderson, Laurent Vivier, qemu-s390x,
Philippe Mathieu-Daudé,
Marcel Apfelbaum, Paolo Bonzini
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 2 --
include/hw/core/sysemu-cpu-ops.h | 4 ++++
hw/core/cpu.c | 4 ++--
target/i386/cpu.c | 4 +++-
4 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 6dd60c3ada4..d0187798eea 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -93,7 +93,6 @@ struct AccelCPUClass;
* @dump_state: Callback for dumping state.
* @dump_statistics: Callback for dumping statistics.
* @get_arch_id: Callback for getting architecture-dependent CPU ID.
- * @get_paging_enabled: Callback for inquiring whether paging is enabled.
* @set_pc: Callback for setting the Program Counter register. This
* should have the semantics used by the target architecture when
* setting the PC from a source such as an ELF file entry point;
@@ -136,7 +135,6 @@ struct CPUClass {
void (*dump_state)(CPUState *cpu, FILE *, int flags);
void (*dump_statistics)(CPUState *cpu, int flags);
int64_t (*get_arch_id)(CPUState *cpu);
- bool (*get_paging_enabled)(const CPUState *cpu);
void (*set_pc)(CPUState *cpu, vaddr value);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 344561b7827..f0707f012b4 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -21,6 +21,10 @@ typedef struct SysemuCPUOps {
*/
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
+ /**
+ * @get_paging_enabled: Callback for inquiring whether paging is enabled.
+ */
+ bool (*get_paging_enabled)(const CPUState *cpu);
/**
* @get_phys_page_debug: Callback for obtaining a physical address.
*/
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 339bdfadd7a..7a8487d468f 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -71,8 +71,8 @@ bool cpu_paging_enabled(const CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->get_paging_enabled) {
- return cc->get_paging_enabled(cpu);
+ if (cc->sysemu_ops->get_paging_enabled) {
+ return cc->sysemu_ops->get_paging_enabled(cpu);
}
return false;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 5d35d8e329f..abdebdfe9b8 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7162,12 +7162,14 @@ static int64_t x86_cpu_get_arch_id(CPUState *cs)
return cpu->apic_id;
}
+#if !defined(CONFIG_USER_ONLY)
static bool x86_cpu_get_paging_enabled(const CPUState *cs)
{
X86CPU *cpu = X86_CPU(cs);
return cpu->env.cr[0] & CR0_PG_MASK;
}
+#endif /* !CONFIG_USER_ONLY */
static void x86_cpu_set_pc(CPUState *cs, vaddr value)
{
@@ -7394,6 +7396,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static const struct SysemuCPUOps i386_sysemu_ops = {
.get_memory_mapping = x86_cpu_get_memory_mapping,
+ .get_paging_enabled = x86_cpu_get_paging_enabled,
.get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
@@ -7434,7 +7437,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = x86_cpu_gdb_read_register;
cc->gdb_write_register = x86_cpu_gdb_write_register;
cc->get_arch_id = x86_cpu_get_arch_id;
- cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
cc->sysemu_ops = &i386_sysemu_ops;
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v6 18/18] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c
2021-04-22 19:38 ` Philippe Mathieu-Daudé
@ 2021-04-22 19:39 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:39 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Cornelia Huck, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland, Thomas Huth,
Philippe Mathieu-Daudé,
Max Filippov, Taylor Simpson, Alistair Francis,
Edgar E. Iglesias, Guan Xuetao, Marek Vasut, Yoshinori Sato,
Juan Quintela, Claudio Fontana, Palmer Dabbelt, Artyom Tarasenko,
Aleksandar Rikalo, Eduardo Habkost, Richard Henderson,
Dr. David Alan Gilbert, Greg Kurz, qemu-s390x, qemu-arm,
Michael Rolnik, Stafford Horne, David Gibson, qemu-riscv,
Bastian Koppelmann, Chris Wulff, Laurent Vivier, Michael Walle,
qemu-ppc, Paolo Bonzini, Aurelien Jarno
Somehow similar to commit 78271684719 ("cpu: tcg_ops: move to
tcg-cpu-ops.h, keep a pointer in CPUClass"):
We cannot in principle make the SysEmu Operations field definitions
conditional on CONFIG_SOFTMMU in code that is included by both
common_ss and specific_ss modules.
Therefore, what we can do safely to restrict the SysEmu fields to
system emulation builds, is to move all sysemu operations into a
separate header file, which is only included by system-specific code.
This leaves just a NULL pointer in the cpu.h for the user-mode builds.
Inspired-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 3 ++-
target/alpha/cpu.h | 3 +++
target/arm/cpu.h | 3 +++
target/avr/cpu.h | 1 +
target/cris/cpu.h | 3 +++
target/hexagon/cpu.h | 3 +++
target/hppa/cpu.h | 3 +++
target/i386/cpu.h | 3 +++
target/lm32/cpu.h | 3 +++
target/m68k/cpu.h | 3 +++
target/microblaze/cpu.h | 1 +
target/mips/cpu.h | 3 +++
target/moxie/cpu.h | 3 +++
target/nios2/cpu.h | 1 +
target/openrisc/cpu.h | 3 +++
target/ppc/cpu.h | 3 +++
target/riscv/cpu.h | 3 +++
target/rx/cpu.h | 1 +
target/s390x/cpu.h | 3 +++
target/sh4/cpu.h | 3 +++
target/sparc/cpu.h | 3 +++
target/tricore/cpu.h | 3 +++
target/unicore32/cpu.h | 3 +++
target/xtensa/cpu.h | 3 +++
cpu.c | 1 +
hw/core/cpu.c | 1 +
26 files changed, 65 insertions(+), 1 deletion(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index d0187798eea..3422d405b49 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -80,7 +80,8 @@ struct TCGCPUOps;
/* see accel-cpu.h */
struct AccelCPUClass;
-#include "hw/core/sysemu-cpu-ops.h"
+/* see sysemu-cpu-ops.h */
+struct SysemuCPUOps;
/**
* CPUClass:
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 82df108967b..f1218a27706 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -22,6 +22,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* Alpha processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 193a49ec7fa..d9228d1d990 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -25,6 +25,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "qapi/qapi-types-common.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* ARM processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index d148e8c75a4..e0419649fa7 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -23,6 +23,7 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#include "hw/core/sysemu-cpu-ops.h"
#ifdef CONFIG_USER_ONLY
#error "AVR 8-bit does not support user mode"
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index d3b64929096..4450f2268ea 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -23,6 +23,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define EXCP_NMI 1
#define EXCP_GURU 2
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index e04eac591c8..2a878e77f08 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -26,6 +26,9 @@ typedef struct CPUHexagonState CPUHexagonState;
#include "qemu-common.h"
#include "exec/cpu-defs.h"
#include "hex_regs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define NUM_PREGS 4
#define TOTAL_PER_THREAD_REGS 64
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 61178fa6a2a..94d2d4701c4 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -23,6 +23,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "exec/memory.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* PA-RISC 1.x processors have a strong memory model. */
/* ??? While we do not yet implement PA-RISC 2.0, those processors have
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 570f916878f..2f520cb6fc1 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -25,6 +25,9 @@
#include "kvm/hyperv-proto.h"
#include "exec/cpu-defs.h"
#include "qapi/qapi-types-common.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* The x86 has a strong memory model with some store-after-load re-ordering */
#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h
index ea7c01ca8b0..034183dad30 100644
--- a/target/lm32/cpu.h
+++ b/target/lm32/cpu.h
@@ -22,6 +22,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
typedef struct CPULM32State CPULM32State;
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 402c86c8769..681dc0d1d13 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -23,6 +23,9 @@
#include "exec/cpu-defs.h"
#include "cpu-qom.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define OS_BYTE 0
#define OS_WORD 1
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index e4bba8a7551..3f5c2e048e5 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -26,6 +26,7 @@
typedef struct CPUMBState CPUMBState;
#if !defined(CONFIG_USER_ONLY)
+#include "hw/core/sysemu-cpu-ops.h"
#include "mmu.h"
#endif
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 075c24abdad..923ab71f8d7 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -6,6 +6,9 @@
#include "fpu/softfloat-types.h"
#include "hw/clock.h"
#include "mips-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h
index bd6ab66084d..7a0a5e95d01 100644
--- a/target/moxie/cpu.h
+++ b/target/moxie/cpu.h
@@ -22,6 +22,9 @@
#include "exec/cpu-defs.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define MOXIE_EX_DIV0 0
#define MOXIE_EX_BAD 1
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 2ab82fdc713..1b88b027063 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -27,6 +27,7 @@
typedef struct CPUNios2State CPUNios2State;
#if !defined(CONFIG_USER_ONLY)
+#include "hw/core/sysemu-cpu-ops.h"
#include "mmu.h"
#endif
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 82cbaeb4f84..2a6f9f48547 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -23,6 +23,9 @@
#include "exec/cpu-defs.h"
#include "hw/core/cpu.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */
struct OpenRISCCPU;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index e73416da68d..f889c28e548 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -24,6 +24,9 @@
#include "exec/cpu-defs.h"
#include "cpu-qom.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define TCG_GUEST_DEFAULT_MO 0
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0a33d387ba8..90ac5097718 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -25,6 +25,9 @@
#include "exec/cpu-defs.h"
#include "fpu/softfloat-types.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define TCG_GUEST_DEFAULT_MO 0
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index 0b4b998c7be..d9b7b63716a 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -25,6 +25,7 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#include "hw/core/sysemu-cpu-ops.h"
/* PSW define */
REG32(PSW, 0)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 2464d4076c0..8f7233d97c2 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -28,6 +28,9 @@
#include "cpu-qom.h"
#include "cpu_models.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define ELF_MACHINE_UNAME "S390X"
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 01c43440822..6c3d3a29fc2 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -22,6 +22,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* CPU Subtypes */
#define SH_CPU_SH7750 (1 << 0)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 4b2290650be..237ffc4fe66 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -4,6 +4,9 @@
#include "qemu/bswap.h"
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#if !defined(TARGET_SPARC64)
#define TARGET_DPREGS 16
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 4b61a2c03f8..a7636c0e870 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -23,6 +23,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "tricore-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
struct tricore_boot_info;
diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h
index 7a32e086ed3..de475d0fc2e 100644
--- a/target/unicore32/cpu.h
+++ b/target/unicore32/cpu.h
@@ -14,6 +14,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
typedef struct CPUUniCore32State {
/* Regs for current mode. */
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 3bd4f691c1a..ea4ee5338f3 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -31,6 +31,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "xtensa-isa.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* Xtensa processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/cpu.c b/cpu.c
index 47eb8c40775..610df6660b3 100644
--- a/cpu.c
+++ b/cpu.c
@@ -29,6 +29,7 @@
#ifdef CONFIG_USER_ONLY
#include "qemu.h"
#else
+#include "hw/core/sysemu-cpu-ops.h"
#include "exec/address-spaces.h"
#endif
#include "sysemu/tcg.h"
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 7a8487d468f..da7543be514 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -35,6 +35,7 @@
#include "trace/trace-root.h"
#include "qemu/plugin.h"
#include "sysemu/hw_accel.h"
+#include "hw/core/sysemu-cpu-ops.h"
CPUState *cpu_by_arch_id(int64_t id)
{
--
2.26.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v6 18/18] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c
@ 2021-04-22 19:39 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 19:39 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, qemu-riscv, Juan Quintela, Peter Maydell,
Claudio Fontana, qemu-arm, Eduardo Habkost, qemu-ppc,
Richard Henderson, Laurent Vivier, qemu-s390x,
Philippe Mathieu-Daudé,
Taylor Simpson, Marcel Apfelbaum, Michael Rolnik,
Edgar E. Iglesias, Paolo Bonzini, Michael Walle, Aurelien Jarno,
Jiaxun Yang, Aleksandar Rikalo, Anthony Green, Chris Wulff,
Marek Vasut, Stafford Horne, David Gibson, Greg Kurz,
Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, Yoshinori Sato, David Hildenbrand,
Cornelia Huck, Thomas Huth, Mark Cave-Ayland, Artyom Tarasenko,
Guan Xuetao, Max Filippov
Somehow similar to commit 78271684719 ("cpu: tcg_ops: move to
tcg-cpu-ops.h, keep a pointer in CPUClass"):
We cannot in principle make the SysEmu Operations field definitions
conditional on CONFIG_SOFTMMU in code that is included by both
common_ss and specific_ss modules.
Therefore, what we can do safely to restrict the SysEmu fields to
system emulation builds, is to move all sysemu operations into a
separate header file, which is only included by system-specific code.
This leaves just a NULL pointer in the cpu.h for the user-mode builds.
Inspired-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 3 ++-
target/alpha/cpu.h | 3 +++
target/arm/cpu.h | 3 +++
target/avr/cpu.h | 1 +
target/cris/cpu.h | 3 +++
target/hexagon/cpu.h | 3 +++
target/hppa/cpu.h | 3 +++
target/i386/cpu.h | 3 +++
target/lm32/cpu.h | 3 +++
target/m68k/cpu.h | 3 +++
target/microblaze/cpu.h | 1 +
target/mips/cpu.h | 3 +++
target/moxie/cpu.h | 3 +++
target/nios2/cpu.h | 1 +
target/openrisc/cpu.h | 3 +++
target/ppc/cpu.h | 3 +++
target/riscv/cpu.h | 3 +++
target/rx/cpu.h | 1 +
target/s390x/cpu.h | 3 +++
target/sh4/cpu.h | 3 +++
target/sparc/cpu.h | 3 +++
target/tricore/cpu.h | 3 +++
target/unicore32/cpu.h | 3 +++
target/xtensa/cpu.h | 3 +++
cpu.c | 1 +
hw/core/cpu.c | 1 +
26 files changed, 65 insertions(+), 1 deletion(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index d0187798eea..3422d405b49 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -80,7 +80,8 @@ struct TCGCPUOps;
/* see accel-cpu.h */
struct AccelCPUClass;
-#include "hw/core/sysemu-cpu-ops.h"
+/* see sysemu-cpu-ops.h */
+struct SysemuCPUOps;
/**
* CPUClass:
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 82df108967b..f1218a27706 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -22,6 +22,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* Alpha processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 193a49ec7fa..d9228d1d990 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -25,6 +25,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "qapi/qapi-types-common.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* ARM processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index d148e8c75a4..e0419649fa7 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -23,6 +23,7 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#include "hw/core/sysemu-cpu-ops.h"
#ifdef CONFIG_USER_ONLY
#error "AVR 8-bit does not support user mode"
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index d3b64929096..4450f2268ea 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -23,6 +23,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define EXCP_NMI 1
#define EXCP_GURU 2
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index e04eac591c8..2a878e77f08 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -26,6 +26,9 @@ typedef struct CPUHexagonState CPUHexagonState;
#include "qemu-common.h"
#include "exec/cpu-defs.h"
#include "hex_regs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define NUM_PREGS 4
#define TOTAL_PER_THREAD_REGS 64
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 61178fa6a2a..94d2d4701c4 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -23,6 +23,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "exec/memory.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* PA-RISC 1.x processors have a strong memory model. */
/* ??? While we do not yet implement PA-RISC 2.0, those processors have
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 570f916878f..2f520cb6fc1 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -25,6 +25,9 @@
#include "kvm/hyperv-proto.h"
#include "exec/cpu-defs.h"
#include "qapi/qapi-types-common.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* The x86 has a strong memory model with some store-after-load re-ordering */
#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h
index ea7c01ca8b0..034183dad30 100644
--- a/target/lm32/cpu.h
+++ b/target/lm32/cpu.h
@@ -22,6 +22,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
typedef struct CPULM32State CPULM32State;
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 402c86c8769..681dc0d1d13 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -23,6 +23,9 @@
#include "exec/cpu-defs.h"
#include "cpu-qom.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define OS_BYTE 0
#define OS_WORD 1
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index e4bba8a7551..3f5c2e048e5 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -26,6 +26,7 @@
typedef struct CPUMBState CPUMBState;
#if !defined(CONFIG_USER_ONLY)
+#include "hw/core/sysemu-cpu-ops.h"
#include "mmu.h"
#endif
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 075c24abdad..923ab71f8d7 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -6,6 +6,9 @@
#include "fpu/softfloat-types.h"
#include "hw/clock.h"
#include "mips-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h
index bd6ab66084d..7a0a5e95d01 100644
--- a/target/moxie/cpu.h
+++ b/target/moxie/cpu.h
@@ -22,6 +22,9 @@
#include "exec/cpu-defs.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define MOXIE_EX_DIV0 0
#define MOXIE_EX_BAD 1
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 2ab82fdc713..1b88b027063 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -27,6 +27,7 @@
typedef struct CPUNios2State CPUNios2State;
#if !defined(CONFIG_USER_ONLY)
+#include "hw/core/sysemu-cpu-ops.h"
#include "mmu.h"
#endif
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 82cbaeb4f84..2a6f9f48547 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -23,6 +23,9 @@
#include "exec/cpu-defs.h"
#include "hw/core/cpu.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */
struct OpenRISCCPU;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index e73416da68d..f889c28e548 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -24,6 +24,9 @@
#include "exec/cpu-defs.h"
#include "cpu-qom.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define TCG_GUEST_DEFAULT_MO 0
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0a33d387ba8..90ac5097718 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -25,6 +25,9 @@
#include "exec/cpu-defs.h"
#include "fpu/softfloat-types.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define TCG_GUEST_DEFAULT_MO 0
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index 0b4b998c7be..d9b7b63716a 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -25,6 +25,7 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#include "hw/core/sysemu-cpu-ops.h"
/* PSW define */
REG32(PSW, 0)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 2464d4076c0..8f7233d97c2 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -28,6 +28,9 @@
#include "cpu-qom.h"
#include "cpu_models.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define ELF_MACHINE_UNAME "S390X"
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 01c43440822..6c3d3a29fc2 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -22,6 +22,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* CPU Subtypes */
#define SH_CPU_SH7750 (1 << 0)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 4b2290650be..237ffc4fe66 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -4,6 +4,9 @@
#include "qemu/bswap.h"
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#if !defined(TARGET_SPARC64)
#define TARGET_DPREGS 16
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 4b61a2c03f8..a7636c0e870 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -23,6 +23,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "tricore-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
struct tricore_boot_info;
diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h
index 7a32e086ed3..de475d0fc2e 100644
--- a/target/unicore32/cpu.h
+++ b/target/unicore32/cpu.h
@@ -14,6 +14,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
typedef struct CPUUniCore32State {
/* Regs for current mode. */
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 3bd4f691c1a..ea4ee5338f3 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -31,6 +31,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "xtensa-isa.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* Xtensa processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/cpu.c b/cpu.c
index 47eb8c40775..610df6660b3 100644
--- a/cpu.c
+++ b/cpu.c
@@ -29,6 +29,7 @@
#ifdef CONFIG_USER_ONLY
#include "qemu.h"
#else
+#include "hw/core/sysemu-cpu-ops.h"
#include "exec/address-spaces.h"
#endif
#include "sysemu/tcg.h"
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 7a8487d468f..da7543be514 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -35,6 +35,7 @@
#include "trace/trace-root.h"
#include "qemu/plugin.h"
#include "sysemu/hw_accel.h"
+#include "hw/core/sysemu-cpu-ops.h"
CPUState *cpu_by_arch_id(int64_t id)
{
--
2.26.3
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