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From: Fuad Tabba <tabba@google.com>
To: linux-arm-kernel@lists.infradead.org
Cc: will@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com,
	 maz@kernel.org, ardb@kernel.org, james.morse@arm.com,
	 alexandru.elisei@arm.com, suzuki.poulose@arm.com,
	robin.murphy@arm.com,  tabba@google.com
Subject: [PATCH v4 11/18] arm64: dcache_by_line_op to take end parameter instead of size
Date: Mon, 24 May 2021 09:29:54 +0100	[thread overview]
Message-ID: <20210524083001.2586635-12-tabba@google.com> (raw)
In-Reply-To: <20210524083001.2586635-1-tabba@google.com>

To be consistent with other functions with similar names and
functionality in cacheflush.h, cache.S, and cachetlb.rst, change
to specify the range in terms of start and end, as opposed to
start and size.

No functional change intended.

Reported-by: Will Deacon <will@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
---
 arch/arm64/include/asm/assembler.h | 27 +++++++++++++--------------
 arch/arm64/kvm/hyp/nvhe/cache.S    |  1 +
 arch/arm64/mm/cache.S              |  7 ++++++-
 3 files changed, 20 insertions(+), 15 deletions(-)

diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
index ced791124b28..c4cecf85dccf 100644
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -397,40 +397,39 @@ alternative_endif
 
 /*
  * Macro to perform a data cache maintenance for the interval
- * [addr, addr + size)
+ * [start, end)
  *
  * 	op:		operation passed to dc instruction
  * 	domain:		domain used in dsb instruciton
- * 	addr:		starting virtual address of the region
- * 	size:		size of the region
+ * 	start:          starting virtual address of the region
+ * 	end:            end virtual address of the region
  * 	fixup:		optional label to branch to on user fault
- * 	Corrupts:	addr, size, tmp1, tmp2
+ * 	Corrupts:       start, end, tmp1, tmp2
  */
-	.macro dcache_by_line_op op, domain, addr, size, tmp1, tmp2, fixup
+	.macro dcache_by_line_op op, domain, start, end, tmp1, tmp2, fixup
 	dcache_line_size \tmp1, \tmp2
-	add	\size, \addr, \size
 	sub	\tmp2, \tmp1, #1
-	bic	\addr, \addr, \tmp2
+	bic	\start, \start, \tmp2
 .Ldcache_op\@:
 	.ifc	\op, cvau
-	__dcache_op_workaround_clean_cache \op, \addr
+	__dcache_op_workaround_clean_cache \op, \start
 	.else
 	.ifc	\op, cvac
-	__dcache_op_workaround_clean_cache \op, \addr
+	__dcache_op_workaround_clean_cache \op, \start
 	.else
 	.ifc	\op, cvap
-	sys	3, c7, c12, 1, \addr	// dc cvap
+	sys	3, c7, c12, 1, \start	// dc cvap
 	.else
 	.ifc	\op, cvadp
-	sys	3, c7, c13, 1, \addr	// dc cvadp
+	sys	3, c7, c13, 1, \start	// dc cvadp
 	.else
-	dc	\op, \addr
+	dc	\op, \start
 	.endif
 	.endif
 	.endif
 	.endif
-	add	\addr, \addr, \tmp1
-	cmp	\addr, \size
+	add	\start, \start, \tmp1
+	cmp	\start, \end
 	b.lo	.Ldcache_op\@
 	dsb	\domain
 
diff --git a/arch/arm64/kvm/hyp/nvhe/cache.S b/arch/arm64/kvm/hyp/nvhe/cache.S
index 36cef6915428..3bcfa3cac46f 100644
--- a/arch/arm64/kvm/hyp/nvhe/cache.S
+++ b/arch/arm64/kvm/hyp/nvhe/cache.S
@@ -8,6 +8,7 @@
 #include <asm/alternative.h>
 
 SYM_FUNC_START_PI(__flush_dcache_area)
+	add	x1, x0, x1
 	dcache_by_line_op civac, sy, x0, x1, x2, x3
 	ret
 SYM_FUNC_END_PI(__flush_dcache_area)
diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
index 03c1a7659ffb..fff883f691f2 100644
--- a/arch/arm64/mm/cache.S
+++ b/arch/arm64/mm/cache.S
@@ -31,7 +31,7 @@ alternative_if ARM64_HAS_CACHE_IDC
 	b       .Ldc_skip_\@
 alternative_else_nop_endif
 	mov     x2, x0
-	sub     x3, x1, x0
+	mov     x3, x1
 	dcache_by_line_op cvau, ish, x2, x3, x4, x5, \fixup
 .Ldc_skip_\@:
 alternative_if ARM64_HAS_CACHE_DIC
@@ -108,6 +108,7 @@ SYM_FUNC_END(invalidate_icache_range)
  *	- size    - size in question
  */
 SYM_FUNC_START_PI(__flush_dcache_area)
+	add	x1, x0, x1
 	dcache_by_line_op civac, sy, x0, x1, x2, x3
 	ret
 SYM_FUNC_END_PI(__flush_dcache_area)
@@ -126,6 +127,7 @@ alternative_if ARM64_HAS_CACHE_IDC
 	dsb	ishst
 	ret
 alternative_else_nop_endif
+	add	x1, x0, x1
 	dcache_by_line_op cvau, ish, x0, x1, x2, x3
 	ret
 SYM_FUNC_END(__clean_dcache_area_pou)
@@ -187,6 +189,7 @@ SYM_FUNC_START_PI(__clean_dcache_area_poc)
  *	- start   - virtual start address of region
  *	- size    - size in question
  */
+	add	x1, x0, x1
 	dcache_by_line_op cvac, sy, x0, x1, x2, x3
 	ret
 SYM_FUNC_END_PI(__clean_dcache_area_poc)
@@ -205,6 +208,7 @@ SYM_FUNC_START_PI(__clean_dcache_area_pop)
 	alternative_if_not ARM64_HAS_DCPOP
 	b	__clean_dcache_area_poc
 	alternative_else_nop_endif
+	add	x1, x0, x1
 	dcache_by_line_op cvap, sy, x0, x1, x2, x3
 	ret
 SYM_FUNC_END_PI(__clean_dcache_area_pop)
@@ -218,6 +222,7 @@ SYM_FUNC_END_PI(__clean_dcache_area_pop)
  *	- size    - size in question
  */
 SYM_FUNC_START_PI(__dma_flush_area)
+	add	x1, x0, x1
 	dcache_by_line_op civac, sy, x0, x1, x2, x3
 	ret
 SYM_FUNC_END_PI(__dma_flush_area)
-- 
2.31.1.818.g46aad6cb9e-goog


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  parent reply	other threads:[~2021-05-24 21:26 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-24  8:29 [PATCH v4 00/18] Tidy up cache.S Fuad Tabba
2021-05-24  8:29 ` [PATCH v4 01/18] arm64: assembler: replace `kaddr` with `addr` Fuad Tabba
2021-05-24  8:29 ` [PATCH v4 02/18] arm64: assembler: add conditional cache fixups Fuad Tabba
2021-05-24  8:29 ` [PATCH v4 03/18] arm64: Apply errata to swsusp_arch_suspend_exit Fuad Tabba
2021-05-24  8:29 ` [PATCH v4 04/18] arm64: Do not enable uaccess for flush_icache_range Fuad Tabba
2021-05-24  9:02   ` Ard Biesheuvel
2021-05-24  9:20     ` Fuad Tabba
2021-05-24  9:41       ` Ard Biesheuvel
2021-05-24  9:53         ` Mark Rutland
2021-05-24  9:57   ` Mark Rutland
2021-05-25 11:20   ` Catalin Marinas
2021-05-24  8:29 ` [PATCH v4 05/18] arm64: Do not enable uaccess for invalidate_icache_range Fuad Tabba
2021-05-25 11:21   ` Catalin Marinas
2021-05-24  8:29 ` [PATCH v4 06/18] arm64: Downgrade flush_icache_range to invalidate Fuad Tabba
2021-05-25 11:21   ` Catalin Marinas
2021-05-24  8:29 ` [PATCH v4 07/18] arm64: assembler: remove user_alt Fuad Tabba
2021-05-24  9:58   ` Mark Rutland
2021-05-24  8:29 ` [PATCH v4 08/18] arm64: Move documentation of dcache_by_line_op Fuad Tabba
2021-05-24  8:29 ` [PATCH v4 09/18] arm64: Fix comments to refer to correct function __flush_icache_range Fuad Tabba
2021-05-24  8:29 ` [PATCH v4 10/18] arm64: __inval_dcache_area to take end parameter instead of size Fuad Tabba
2021-05-24  8:29 ` Fuad Tabba [this message]
2021-05-24  8:29 ` [PATCH v4 12/18] arm64: __flush_dcache_area " Fuad Tabba
2021-05-24  8:29 ` [PATCH v4 13/18] arm64: __clean_dcache_area_poc " Fuad Tabba
2021-05-24  8:29 ` [PATCH v4 14/18] arm64: __clean_dcache_area_pop " Fuad Tabba
2021-05-24  8:29 ` [PATCH v4 15/18] arm64: __clean_dcache_area_pou " Fuad Tabba
2021-05-24  8:29 ` [PATCH v4 16/18] arm64: sync_icache_aliases " Fuad Tabba
2021-05-24  8:30 ` [PATCH v4 17/18] arm64: Fix cache maintenance function comments Fuad Tabba
2021-05-24  8:30 ` [PATCH v4 18/18] arm64: Rename arm64-internal cache maintenance functions Fuad Tabba
2021-05-24  9:47 ` [PATCH v4 00/18] Tidy up cache.S Ard Biesheuvel
2021-05-25 18:58 ` Will Deacon

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