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From: Fuad Tabba <tabba@google.com>
To: linux-arm-kernel@lists.infradead.org
Cc: will@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com,
	 maz@kernel.org, ardb@kernel.org, james.morse@arm.com,
	 alexandru.elisei@arm.com, suzuki.poulose@arm.com,
	robin.murphy@arm.com,  tabba@google.com
Subject: [PATCH v4 09/18] arm64: Fix comments to refer to correct function __flush_icache_range
Date: Mon, 24 May 2021 09:29:52 +0100	[thread overview]
Message-ID: <20210524083001.2586635-10-tabba@google.com> (raw)
In-Reply-To: <20210524083001.2586635-1-tabba@google.com>

Many comments refer to the function flush_icache_range, where the
intent is in fact __flush_icache_range. Fix these comments to
refer to the intended function.

That's probably due to commit 3b8c9f1cdfc506e9 ("arm64: IPI each
CPU after invalidating the I-cache for kernel mappings"), which
renamed flush_icache_range() to __flush_icache_range() and added
a wrapper.

No functional change intended.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
---
 arch/arm64/kernel/hibernate-asm.S | 4 ++--
 arch/arm64/mm/cache.S             | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/kernel/hibernate-asm.S b/arch/arm64/kernel/hibernate-asm.S
index 0ed2f72a6b94..ef2ab7caf815 100644
--- a/arch/arm64/kernel/hibernate-asm.S
+++ b/arch/arm64/kernel/hibernate-asm.S
@@ -45,7 +45,7 @@
  * Because this code has to be copied to a 'safe' page, it can't call out to
  * other functions by PC-relative address. Also remember that it may be
  * mid-way through over-writing other functions. For this reason it contains
- * code from flush_icache_range() and uses the copy_page() macro.
+ * code from __flush_icache_range() and uses the copy_page() macro.
  *
  * This 'safe' page is mapped via ttbr0, and executed from there. This function
  * switches to a copy of the linear map in ttbr1, performs the restore, then
@@ -87,7 +87,7 @@ SYM_CODE_START(swsusp_arch_suspend_exit)
 	copy_page	x0, x1, x2, x3, x4, x5, x6, x7, x8, x9
 
 	add	x1, x10, #PAGE_SIZE
-	/* Clean the copied page to PoU - based on flush_icache_range() */
+	/* Clean the copied page to PoU - based on __flush_icache_range() */
 	raw_dcache_line_size x2, x3
 	sub	x3, x2, #1
 	bic	x4, x10, x3
diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
index 14eac9d76d57..910ae8f6a389 100644
--- a/arch/arm64/mm/cache.S
+++ b/arch/arm64/mm/cache.S
@@ -43,7 +43,7 @@ alternative_else_nop_endif
 .endm
 
 /*
- *	flush_icache_range(start,end)
+ *	__flush_icache_range(start,end)
  *
  *	Ensure that the I and D caches are coherent within specified region.
  *	This is typically used when code has been written to a memory region,
-- 
2.31.1.818.g46aad6cb9e-goog


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  parent reply	other threads:[~2021-05-24 18:12 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-24  8:29 [PATCH v4 00/18] Tidy up cache.S Fuad Tabba
2021-05-24  8:29 ` [PATCH v4 01/18] arm64: assembler: replace `kaddr` with `addr` Fuad Tabba
2021-05-24  8:29 ` [PATCH v4 02/18] arm64: assembler: add conditional cache fixups Fuad Tabba
2021-05-24  8:29 ` [PATCH v4 03/18] arm64: Apply errata to swsusp_arch_suspend_exit Fuad Tabba
2021-05-24  8:29 ` [PATCH v4 04/18] arm64: Do not enable uaccess for flush_icache_range Fuad Tabba
2021-05-24  9:02   ` Ard Biesheuvel
2021-05-24  9:20     ` Fuad Tabba
2021-05-24  9:41       ` Ard Biesheuvel
2021-05-24  9:53         ` Mark Rutland
2021-05-24  9:57   ` Mark Rutland
2021-05-25 11:20   ` Catalin Marinas
2021-05-24  8:29 ` [PATCH v4 05/18] arm64: Do not enable uaccess for invalidate_icache_range Fuad Tabba
2021-05-25 11:21   ` Catalin Marinas
2021-05-24  8:29 ` [PATCH v4 06/18] arm64: Downgrade flush_icache_range to invalidate Fuad Tabba
2021-05-25 11:21   ` Catalin Marinas
2021-05-24  8:29 ` [PATCH v4 07/18] arm64: assembler: remove user_alt Fuad Tabba
2021-05-24  9:58   ` Mark Rutland
2021-05-24  8:29 ` [PATCH v4 08/18] arm64: Move documentation of dcache_by_line_op Fuad Tabba
2021-05-24  8:29 ` Fuad Tabba [this message]
2021-05-24  8:29 ` [PATCH v4 10/18] arm64: __inval_dcache_area to take end parameter instead of size Fuad Tabba
2021-05-24  8:29 ` [PATCH v4 11/18] arm64: dcache_by_line_op " Fuad Tabba
2021-05-24  8:29 ` [PATCH v4 12/18] arm64: __flush_dcache_area " Fuad Tabba
2021-05-24  8:29 ` [PATCH v4 13/18] arm64: __clean_dcache_area_poc " Fuad Tabba
2021-05-24  8:29 ` [PATCH v4 14/18] arm64: __clean_dcache_area_pop " Fuad Tabba
2021-05-24  8:29 ` [PATCH v4 15/18] arm64: __clean_dcache_area_pou " Fuad Tabba
2021-05-24  8:29 ` [PATCH v4 16/18] arm64: sync_icache_aliases " Fuad Tabba
2021-05-24  8:30 ` [PATCH v4 17/18] arm64: Fix cache maintenance function comments Fuad Tabba
2021-05-24  8:30 ` [PATCH v4 18/18] arm64: Rename arm64-internal cache maintenance functions Fuad Tabba
2021-05-24  9:47 ` [PATCH v4 00/18] Tidy up cache.S Ard Biesheuvel
2021-05-25 18:58 ` Will Deacon

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